1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * tas2764.h - ALSA SoC Texas Instruments TAS2764 Mono Audio Amplifier 4 * 5 * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com 6 * 7 * Author: Dan Murphy <dmurphy@ti.com> 8 */ 9 10 #ifndef __TAS2764__ 11 #define __TAS2764__ 12 13 /* Book Control Register */ 14 #define TAS2764_BOOKCTL_PAGE 0 15 #define TAS2764_BOOKCTL_REG 127 16 #define TAS2764_REG(page, reg) ((page * 128) + reg) 17 18 /* Page */ 19 #define TAS2764_PAGE TAS2764_REG(0X0, 0x00) 20 #define TAS2764_PAGE_PAGE_MASK 255 21 22 /* Software Reset */ 23 #define TAS2764_SW_RST TAS2764_REG(0X0, 0x01) 24 #define TAS2764_RST BIT(0) 25 26 /* Power Control */ 27 #define TAS2764_PWR_CTRL TAS2764_REG(0X0, 0x02) 28 #define TAS2764_PWR_CTRL_MASK GENMASK(1, 0) 29 #define TAS2764_PWR_CTRL_ACTIVE 0x0 30 #define TAS2764_PWR_CTRL_MUTE BIT(0) 31 #define TAS2764_PWR_CTRL_SHUTDOWN BIT(1) 32 33 #define TAS2764_VSENSE_POWER_EN 3 34 #define TAS2764_ISENSE_POWER_EN 4 35 36 /* Digital Volume Control */ 37 #define TAS2764_DVC TAS2764_REG(0X0, 0x1a) 38 #define TAS2764_DVC_MAX 0xc9 39 40 #define TAS2764_CHNL_0 TAS2764_REG(0X0, 0x03) 41 42 /* TDM Configuration Reg0 */ 43 #define TAS2764_TDM_CFG0 TAS2764_REG(0X0, 0x08) 44 #define TAS2764_TDM_CFG0_SMP_MASK BIT(5) 45 #define TAS2764_TDM_CFG0_SMP_48KHZ 0x0 46 #define TAS2764_TDM_CFG0_SMP_44_1KHZ BIT(5) 47 #define TAS2764_TDM_CFG0_MASK GENMASK(3, 1) 48 #define TAS2764_TDM_CFG0_44_1_48KHZ BIT(3) 49 #define TAS2764_TDM_CFG0_88_2_96KHZ (BIT(3) | BIT(1)) 50 51 /* TDM Configuration Reg1 */ 52 #define TAS2764_TDM_CFG1 TAS2764_REG(0X0, 0x09) 53 #define TAS2764_TDM_CFG1_MASK GENMASK(5, 1) 54 #define TAS2764_TDM_CFG1_51_SHIFT 1 55 #define TAS2764_TDM_CFG1_RX_MASK BIT(0) 56 #define TAS2764_TDM_CFG1_RX_RISING 0x0 57 #define TAS2764_TDM_CFG1_RX_FALLING BIT(0) 58 59 /* TDM Configuration Reg2 */ 60 #define TAS2764_TDM_CFG2 TAS2764_REG(0X0, 0x0a) 61 #define TAS2764_TDM_CFG2_RXW_MASK GENMASK(3, 2) 62 #define TAS2764_TDM_CFG2_RXW_16BITS 0x0 63 #define TAS2764_TDM_CFG2_RXW_24BITS BIT(3) 64 #define TAS2764_TDM_CFG2_RXW_32BITS (BIT(3) | BIT(2)) 65 #define TAS2764_TDM_CFG2_RXS_MASK GENMASK(1, 0) 66 #define TAS2764_TDM_CFG2_RXS_16BITS 0x0 67 #define TAS2764_TDM_CFG2_RXS_24BITS BIT(0) 68 #define TAS2764_TDM_CFG2_RXS_32BITS BIT(1) 69 #define TAS2764_TDM_CFG2_SCFG_MASK GENMASK(5, 4) 70 #define TAS2764_TDM_CFG2_SCFG_I2S 0x0 71 #define TAS2764_TDM_CFG2_SCFG_LEFT_J BIT(4) 72 #define TAS2764_TDM_CFG2_SCFG_RIGHT_J BIT(5) 73 74 /* TDM Configuration Reg3 */ 75 #define TAS2764_TDM_CFG3 TAS2764_REG(0X0, 0x0c) 76 #define TAS2764_TDM_CFG3_RXS_MASK GENMASK(7, 4) 77 #define TAS2764_TDM_CFG3_RXS_SHIFT 0x4 78 #define TAS2764_TDM_CFG3_MASK GENMASK(3, 0) 79 80 /* TDM Configuration Reg5 */ 81 #define TAS2764_TDM_CFG5 TAS2764_REG(0X0, 0x0e) 82 #define TAS2764_TDM_CFG5_VSNS_MASK BIT(6) 83 #define TAS2764_TDM_CFG5_VSNS_ENABLE BIT(6) 84 #define TAS2764_TDM_CFG5_50_MASK GENMASK(5, 0) 85 86 /* TDM Configuration Reg6 */ 87 #define TAS2764_TDM_CFG6 TAS2764_REG(0X0, 0x0f) 88 #define TAS2764_TDM_CFG6_ISNS_MASK BIT(6) 89 #define TAS2764_TDM_CFG6_ISNS_ENABLE BIT(6) 90 #define TAS2764_TDM_CFG6_50_MASK GENMASK(5, 0) 91 92 #endif /* __TAS2764__ */ 93