1827ed8a0SDan Murphy /* SPDX-License-Identifier: GPL-2.0-only */ 2827ed8a0SDan Murphy /* 3827ed8a0SDan Murphy * tas2764.h - ALSA SoC Texas Instruments TAS2764 Mono Audio Amplifier 4827ed8a0SDan Murphy * 5827ed8a0SDan Murphy * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com 6827ed8a0SDan Murphy * 7827ed8a0SDan Murphy * Author: Dan Murphy <dmurphy@ti.com> 8827ed8a0SDan Murphy */ 9827ed8a0SDan Murphy 10827ed8a0SDan Murphy #ifndef __TAS2764__ 11827ed8a0SDan Murphy #define __TAS2764__ 12827ed8a0SDan Murphy 13827ed8a0SDan Murphy /* Book Control Register */ 14827ed8a0SDan Murphy #define TAS2764_BOOKCTL_PAGE 0 15827ed8a0SDan Murphy #define TAS2764_BOOKCTL_REG 127 16827ed8a0SDan Murphy #define TAS2764_REG(page, reg) ((page * 128) + reg) 17827ed8a0SDan Murphy 18827ed8a0SDan Murphy /* Page */ 19827ed8a0SDan Murphy #define TAS2764_PAGE TAS2764_REG(0X0, 0x00) 20827ed8a0SDan Murphy #define TAS2764_PAGE_PAGE_MASK 255 21827ed8a0SDan Murphy 22827ed8a0SDan Murphy /* Software Reset */ 23827ed8a0SDan Murphy #define TAS2764_SW_RST TAS2764_REG(0X0, 0x01) 24827ed8a0SDan Murphy #define TAS2764_RST BIT(0) 25827ed8a0SDan Murphy 26827ed8a0SDan Murphy /* Power Control */ 27827ed8a0SDan Murphy #define TAS2764_PWR_CTRL TAS2764_REG(0X0, 0x02) 28827ed8a0SDan Murphy #define TAS2764_PWR_CTRL_MASK GENMASK(1, 0) 29827ed8a0SDan Murphy #define TAS2764_PWR_CTRL_ACTIVE 0x0 30827ed8a0SDan Murphy #define TAS2764_PWR_CTRL_MUTE BIT(0) 31827ed8a0SDan Murphy #define TAS2764_PWR_CTRL_SHUTDOWN BIT(1) 32827ed8a0SDan Murphy 33827ed8a0SDan Murphy #define TAS2764_VSENSE_POWER_EN 3 34827ed8a0SDan Murphy #define TAS2764_ISENSE_POWER_EN 4 35827ed8a0SDan Murphy 36827ed8a0SDan Murphy /* Digital Volume Control */ 37827ed8a0SDan Murphy #define TAS2764_DVC TAS2764_REG(0X0, 0x1a) 38827ed8a0SDan Murphy #define TAS2764_DVC_MAX 0xc9 39827ed8a0SDan Murphy 40827ed8a0SDan Murphy #define TAS2764_CHNL_0 TAS2764_REG(0X0, 0x03) 41827ed8a0SDan Murphy 42827ed8a0SDan Murphy /* TDM Configuration Reg0 */ 43827ed8a0SDan Murphy #define TAS2764_TDM_CFG0 TAS2764_REG(0X0, 0x08) 44827ed8a0SDan Murphy #define TAS2764_TDM_CFG0_SMP_MASK BIT(5) 45827ed8a0SDan Murphy #define TAS2764_TDM_CFG0_SMP_48KHZ 0x0 46827ed8a0SDan Murphy #define TAS2764_TDM_CFG0_SMP_44_1KHZ BIT(5) 47827ed8a0SDan Murphy #define TAS2764_TDM_CFG0_MASK GENMASK(3, 1) 48827ed8a0SDan Murphy #define TAS2764_TDM_CFG0_44_1_48KHZ BIT(3) 49827ed8a0SDan Murphy #define TAS2764_TDM_CFG0_88_2_96KHZ (BIT(3) | BIT(1)) 50827ed8a0SDan Murphy 51827ed8a0SDan Murphy /* TDM Configuration Reg1 */ 52827ed8a0SDan Murphy #define TAS2764_TDM_CFG1 TAS2764_REG(0X0, 0x09) 53827ed8a0SDan Murphy #define TAS2764_TDM_CFG1_MASK GENMASK(5, 1) 54827ed8a0SDan Murphy #define TAS2764_TDM_CFG1_51_SHIFT 1 55827ed8a0SDan Murphy #define TAS2764_TDM_CFG1_RX_MASK BIT(0) 56827ed8a0SDan Murphy #define TAS2764_TDM_CFG1_RX_RISING 0x0 57827ed8a0SDan Murphy #define TAS2764_TDM_CFG1_RX_FALLING BIT(0) 58827ed8a0SDan Murphy 59827ed8a0SDan Murphy /* TDM Configuration Reg2 */ 60827ed8a0SDan Murphy #define TAS2764_TDM_CFG2 TAS2764_REG(0X0, 0x0a) 61827ed8a0SDan Murphy #define TAS2764_TDM_CFG2_RXW_MASK GENMASK(3, 2) 62827ed8a0SDan Murphy #define TAS2764_TDM_CFG2_RXW_16BITS 0x0 63827ed8a0SDan Murphy #define TAS2764_TDM_CFG2_RXW_24BITS BIT(3) 64827ed8a0SDan Murphy #define TAS2764_TDM_CFG2_RXW_32BITS (BIT(3) | BIT(2)) 65827ed8a0SDan Murphy #define TAS2764_TDM_CFG2_RXS_MASK GENMASK(1, 0) 66827ed8a0SDan Murphy #define TAS2764_TDM_CFG2_RXS_16BITS 0x0 67827ed8a0SDan Murphy #define TAS2764_TDM_CFG2_RXS_24BITS BIT(0) 68827ed8a0SDan Murphy #define TAS2764_TDM_CFG2_RXS_32BITS BIT(1) 69827ed8a0SDan Murphy #define TAS2764_TDM_CFG2_SCFG_MASK GENMASK(5, 4) 70827ed8a0SDan Murphy #define TAS2764_TDM_CFG2_SCFG_I2S 0x0 71827ed8a0SDan Murphy #define TAS2764_TDM_CFG2_SCFG_LEFT_J BIT(4) 72827ed8a0SDan Murphy #define TAS2764_TDM_CFG2_SCFG_RIGHT_J BIT(5) 73827ed8a0SDan Murphy 74827ed8a0SDan Murphy /* TDM Configuration Reg3 */ 75827ed8a0SDan Murphy #define TAS2764_TDM_CFG3 TAS2764_REG(0X0, 0x0c) 76827ed8a0SDan Murphy #define TAS2764_TDM_CFG3_RXS_MASK GENMASK(7, 4) 77827ed8a0SDan Murphy #define TAS2764_TDM_CFG3_RXS_SHIFT 0x4 78827ed8a0SDan Murphy #define TAS2764_TDM_CFG3_MASK GENMASK(3, 0) 79827ed8a0SDan Murphy 80827ed8a0SDan Murphy /* TDM Configuration Reg5 */ 81827ed8a0SDan Murphy #define TAS2764_TDM_CFG5 TAS2764_REG(0X0, 0x0e) 82827ed8a0SDan Murphy #define TAS2764_TDM_CFG5_VSNS_MASK BIT(6) 83827ed8a0SDan Murphy #define TAS2764_TDM_CFG5_VSNS_ENABLE BIT(6) 84827ed8a0SDan Murphy #define TAS2764_TDM_CFG5_50_MASK GENMASK(5, 0) 85827ed8a0SDan Murphy 86827ed8a0SDan Murphy /* TDM Configuration Reg6 */ 87827ed8a0SDan Murphy #define TAS2764_TDM_CFG6 TAS2764_REG(0X0, 0x0f) 88827ed8a0SDan Murphy #define TAS2764_TDM_CFG6_ISNS_MASK BIT(6) 89827ed8a0SDan Murphy #define TAS2764_TDM_CFG6_ISNS_ENABLE BIT(6) 90827ed8a0SDan Murphy #define TAS2764_TDM_CFG6_50_MASK GENMASK(5, 0) 91827ed8a0SDan Murphy 92827ed8a0SDan Murphy #endif /* __TAS2764__ */ 93