1 /* 2 * Codec driver for ST STA32x 2.1-channel high-efficiency digital audio system 3 * 4 * Copyright: 2011 Raumfeld GmbH 5 * Author: Johannes Stezenbach <js@sig21.net> 6 * 7 * based on code from: 8 * Wolfson Microelectronics PLC. 9 * Mark Brown <broonie@opensource.wolfsonmicro.com> 10 * Freescale Semiconductor, Inc. 11 * Timur Tabi <timur@freescale.com> 12 * 13 * This program is free software; you can redistribute it and/or modify it 14 * under the terms of the GNU General Public License as published by the 15 * Free Software Foundation; either version 2 of the License, or (at your 16 * option) any later version. 17 */ 18 19 #define pr_fmt(fmt) KBUILD_MODNAME ":%s:%d: " fmt, __func__, __LINE__ 20 21 #include <linux/module.h> 22 #include <linux/moduleparam.h> 23 #include <linux/init.h> 24 #include <linux/delay.h> 25 #include <linux/pm.h> 26 #include <linux/i2c.h> 27 #include <linux/regmap.h> 28 #include <linux/regulator/consumer.h> 29 #include <linux/slab.h> 30 #include <linux/workqueue.h> 31 #include <sound/core.h> 32 #include <sound/pcm.h> 33 #include <sound/pcm_params.h> 34 #include <sound/soc.h> 35 #include <sound/soc-dapm.h> 36 #include <sound/initval.h> 37 #include <sound/tlv.h> 38 39 #include <sound/sta32x.h> 40 #include "sta32x.h" 41 42 #define STA32X_RATES (SNDRV_PCM_RATE_32000 | \ 43 SNDRV_PCM_RATE_44100 | \ 44 SNDRV_PCM_RATE_48000 | \ 45 SNDRV_PCM_RATE_88200 | \ 46 SNDRV_PCM_RATE_96000 | \ 47 SNDRV_PCM_RATE_176400 | \ 48 SNDRV_PCM_RATE_192000) 49 50 #define STA32X_FORMATS \ 51 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S16_BE | \ 52 SNDRV_PCM_FMTBIT_S18_3LE | SNDRV_PCM_FMTBIT_S18_3BE | \ 53 SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S20_3BE | \ 54 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S24_3BE | \ 55 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S24_BE | \ 56 SNDRV_PCM_FMTBIT_S32_LE | SNDRV_PCM_FMTBIT_S32_BE) 57 58 /* Power-up register defaults */ 59 static const struct reg_default sta32x_regs[] = { 60 { 0x0, 0x63 }, 61 { 0x1, 0x80 }, 62 { 0x2, 0xc2 }, 63 { 0x3, 0x40 }, 64 { 0x4, 0xc2 }, 65 { 0x5, 0x5c }, 66 { 0x6, 0x10 }, 67 { 0x7, 0xff }, 68 { 0x8, 0x60 }, 69 { 0x9, 0x60 }, 70 { 0xa, 0x60 }, 71 { 0xb, 0x80 }, 72 { 0xc, 0x00 }, 73 { 0xd, 0x00 }, 74 { 0xe, 0x00 }, 75 { 0xf, 0x40 }, 76 { 0x10, 0x80 }, 77 { 0x11, 0x77 }, 78 { 0x12, 0x6a }, 79 { 0x13, 0x69 }, 80 { 0x14, 0x6a }, 81 { 0x15, 0x69 }, 82 { 0x16, 0x00 }, 83 { 0x17, 0x00 }, 84 { 0x18, 0x00 }, 85 { 0x19, 0x00 }, 86 { 0x1a, 0x00 }, 87 { 0x1b, 0x00 }, 88 { 0x1c, 0x00 }, 89 { 0x1d, 0x00 }, 90 { 0x1e, 0x00 }, 91 { 0x1f, 0x00 }, 92 { 0x20, 0x00 }, 93 { 0x21, 0x00 }, 94 { 0x22, 0x00 }, 95 { 0x23, 0x00 }, 96 { 0x24, 0x00 }, 97 { 0x25, 0x00 }, 98 { 0x26, 0x00 }, 99 { 0x27, 0x2d }, 100 { 0x28, 0xc0 }, 101 { 0x2b, 0x00 }, 102 { 0x2c, 0x0c }, 103 }; 104 105 /* regulator power supply names */ 106 static const char *sta32x_supply_names[] = { 107 "Vdda", /* analog supply, 3.3VV */ 108 "Vdd3", /* digital supply, 3.3V */ 109 "Vcc" /* power amp spply, 10V - 36V */ 110 }; 111 112 /* codec private data */ 113 struct sta32x_priv { 114 struct regmap *regmap; 115 struct regulator_bulk_data supplies[ARRAY_SIZE(sta32x_supply_names)]; 116 struct snd_soc_codec *codec; 117 struct sta32x_platform_data *pdata; 118 119 unsigned int mclk; 120 unsigned int format; 121 122 u32 coef_shadow[STA32X_COEF_COUNT]; 123 struct delayed_work watchdog_work; 124 int shutdown; 125 }; 126 127 static const DECLARE_TLV_DB_SCALE(mvol_tlv, -12700, 50, 1); 128 static const DECLARE_TLV_DB_SCALE(chvol_tlv, -7950, 50, 1); 129 static const DECLARE_TLV_DB_SCALE(tone_tlv, -120, 200, 0); 130 131 static const char *sta32x_drc_ac[] = { 132 "Anti-Clipping", "Dynamic Range Compression" }; 133 static const char *sta32x_auto_eq_mode[] = { 134 "User", "Preset", "Loudness" }; 135 static const char *sta32x_auto_gc_mode[] = { 136 "User", "AC no clipping", "AC limited clipping (10%)", 137 "DRC nighttime listening mode" }; 138 static const char *sta32x_auto_xo_mode[] = { 139 "User", "80Hz", "100Hz", "120Hz", "140Hz", "160Hz", "180Hz", "200Hz", 140 "220Hz", "240Hz", "260Hz", "280Hz", "300Hz", "320Hz", "340Hz", "360Hz" }; 141 static const char *sta32x_preset_eq_mode[] = { 142 "Flat", "Rock", "Soft Rock", "Jazz", "Classical", "Dance", "Pop", "Soft", 143 "Hard", "Party", "Vocal", "Hip-Hop", "Dialog", "Bass-boost #1", 144 "Bass-boost #2", "Bass-boost #3", "Loudness 1", "Loudness 2", 145 "Loudness 3", "Loudness 4", "Loudness 5", "Loudness 6", "Loudness 7", 146 "Loudness 8", "Loudness 9", "Loudness 10", "Loudness 11", "Loudness 12", 147 "Loudness 13", "Loudness 14", "Loudness 15", "Loudness 16" }; 148 static const char *sta32x_limiter_select[] = { 149 "Limiter Disabled", "Limiter #1", "Limiter #2" }; 150 static const char *sta32x_limiter_attack_rate[] = { 151 "3.1584", "2.7072", "2.2560", "1.8048", "1.3536", "0.9024", 152 "0.4512", "0.2256", "0.1504", "0.1123", "0.0902", "0.0752", 153 "0.0645", "0.0564", "0.0501", "0.0451" }; 154 static const char *sta32x_limiter_release_rate[] = { 155 "0.5116", "0.1370", "0.0744", "0.0499", "0.0360", "0.0299", 156 "0.0264", "0.0208", "0.0198", "0.0172", "0.0147", "0.0137", 157 "0.0134", "0.0117", "0.0110", "0.0104" }; 158 159 static const unsigned int sta32x_limiter_ac_attack_tlv[] = { 160 TLV_DB_RANGE_HEAD(2), 161 0, 7, TLV_DB_SCALE_ITEM(-1200, 200, 0), 162 8, 16, TLV_DB_SCALE_ITEM(300, 100, 0), 163 }; 164 165 static const unsigned int sta32x_limiter_ac_release_tlv[] = { 166 TLV_DB_RANGE_HEAD(5), 167 0, 0, TLV_DB_SCALE_ITEM(TLV_DB_GAIN_MUTE, 0, 0), 168 1, 1, TLV_DB_SCALE_ITEM(-2900, 0, 0), 169 2, 2, TLV_DB_SCALE_ITEM(-2000, 0, 0), 170 3, 8, TLV_DB_SCALE_ITEM(-1400, 200, 0), 171 8, 16, TLV_DB_SCALE_ITEM(-700, 100, 0), 172 }; 173 174 static const unsigned int sta32x_limiter_drc_attack_tlv[] = { 175 TLV_DB_RANGE_HEAD(3), 176 0, 7, TLV_DB_SCALE_ITEM(-3100, 200, 0), 177 8, 13, TLV_DB_SCALE_ITEM(-1600, 100, 0), 178 14, 16, TLV_DB_SCALE_ITEM(-1000, 300, 0), 179 }; 180 181 static const unsigned int sta32x_limiter_drc_release_tlv[] = { 182 TLV_DB_RANGE_HEAD(5), 183 0, 0, TLV_DB_SCALE_ITEM(TLV_DB_GAIN_MUTE, 0, 0), 184 1, 2, TLV_DB_SCALE_ITEM(-3800, 200, 0), 185 3, 4, TLV_DB_SCALE_ITEM(-3300, 200, 0), 186 5, 12, TLV_DB_SCALE_ITEM(-3000, 200, 0), 187 13, 16, TLV_DB_SCALE_ITEM(-1500, 300, 0), 188 }; 189 190 static SOC_ENUM_SINGLE_DECL(sta32x_drc_ac_enum, 191 STA32X_CONFD, STA32X_CONFD_DRC_SHIFT, 192 sta32x_drc_ac); 193 static SOC_ENUM_SINGLE_DECL(sta32x_auto_eq_enum, 194 STA32X_AUTO1, STA32X_AUTO1_AMEQ_SHIFT, 195 sta32x_auto_eq_mode); 196 static SOC_ENUM_SINGLE_DECL(sta32x_auto_gc_enum, 197 STA32X_AUTO1, STA32X_AUTO1_AMGC_SHIFT, 198 sta32x_auto_gc_mode); 199 static SOC_ENUM_SINGLE_DECL(sta32x_auto_xo_enum, 200 STA32X_AUTO2, STA32X_AUTO2_XO_SHIFT, 201 sta32x_auto_xo_mode); 202 static SOC_ENUM_SINGLE_DECL(sta32x_preset_eq_enum, 203 STA32X_AUTO3, STA32X_AUTO3_PEQ_SHIFT, 204 sta32x_preset_eq_mode); 205 static SOC_ENUM_SINGLE_DECL(sta32x_limiter_ch1_enum, 206 STA32X_C1CFG, STA32X_CxCFG_LS_SHIFT, 207 sta32x_limiter_select); 208 static SOC_ENUM_SINGLE_DECL(sta32x_limiter_ch2_enum, 209 STA32X_C2CFG, STA32X_CxCFG_LS_SHIFT, 210 sta32x_limiter_select); 211 static SOC_ENUM_SINGLE_DECL(sta32x_limiter_ch3_enum, 212 STA32X_C3CFG, STA32X_CxCFG_LS_SHIFT, 213 sta32x_limiter_select); 214 static SOC_ENUM_SINGLE_DECL(sta32x_limiter1_attack_rate_enum, 215 STA32X_L1AR, STA32X_LxA_SHIFT, 216 sta32x_limiter_attack_rate); 217 static SOC_ENUM_SINGLE_DECL(sta32x_limiter2_attack_rate_enum, 218 STA32X_L2AR, STA32X_LxA_SHIFT, 219 sta32x_limiter_attack_rate); 220 static SOC_ENUM_SINGLE_DECL(sta32x_limiter1_release_rate_enum, 221 STA32X_L1AR, STA32X_LxR_SHIFT, 222 sta32x_limiter_release_rate); 223 static SOC_ENUM_SINGLE_DECL(sta32x_limiter2_release_rate_enum, 224 STA32X_L2AR, STA32X_LxR_SHIFT, 225 sta32x_limiter_release_rate); 226 227 /* byte array controls for setting biquad, mixer, scaling coefficients; 228 * for biquads all five coefficients need to be set in one go, 229 * mixer and pre/postscale coefs can be set individually; 230 * each coef is 24bit, the bytes are ordered in the same way 231 * as given in the STA32x data sheet (big endian; b1, b2, a1, a2, b0) 232 */ 233 234 static int sta32x_coefficient_info(struct snd_kcontrol *kcontrol, 235 struct snd_ctl_elem_info *uinfo) 236 { 237 int numcoef = kcontrol->private_value >> 16; 238 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES; 239 uinfo->count = 3 * numcoef; 240 return 0; 241 } 242 243 static int sta32x_coefficient_get(struct snd_kcontrol *kcontrol, 244 struct snd_ctl_elem_value *ucontrol) 245 { 246 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); 247 int numcoef = kcontrol->private_value >> 16; 248 int index = kcontrol->private_value & 0xffff; 249 unsigned int cfud; 250 int i; 251 252 /* preserve reserved bits in STA32X_CFUD */ 253 cfud = snd_soc_read(codec, STA32X_CFUD) & 0xf0; 254 /* chip documentation does not say if the bits are self clearing, 255 * so do it explicitly */ 256 snd_soc_write(codec, STA32X_CFUD, cfud); 257 258 snd_soc_write(codec, STA32X_CFADDR2, index); 259 if (numcoef == 1) 260 snd_soc_write(codec, STA32X_CFUD, cfud | 0x04); 261 else if (numcoef == 5) 262 snd_soc_write(codec, STA32X_CFUD, cfud | 0x08); 263 else 264 return -EINVAL; 265 for (i = 0; i < 3 * numcoef; i++) 266 ucontrol->value.bytes.data[i] = 267 snd_soc_read(codec, STA32X_B1CF1 + i); 268 269 return 0; 270 } 271 272 static int sta32x_coefficient_put(struct snd_kcontrol *kcontrol, 273 struct snd_ctl_elem_value *ucontrol) 274 { 275 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); 276 struct sta32x_priv *sta32x = snd_soc_codec_get_drvdata(codec); 277 int numcoef = kcontrol->private_value >> 16; 278 int index = kcontrol->private_value & 0xffff; 279 unsigned int cfud; 280 int i; 281 282 /* preserve reserved bits in STA32X_CFUD */ 283 cfud = snd_soc_read(codec, STA32X_CFUD) & 0xf0; 284 /* chip documentation does not say if the bits are self clearing, 285 * so do it explicitly */ 286 snd_soc_write(codec, STA32X_CFUD, cfud); 287 288 snd_soc_write(codec, STA32X_CFADDR2, index); 289 for (i = 0; i < numcoef && (index + i < STA32X_COEF_COUNT); i++) 290 sta32x->coef_shadow[index + i] = 291 (ucontrol->value.bytes.data[3 * i] << 16) 292 | (ucontrol->value.bytes.data[3 * i + 1] << 8) 293 | (ucontrol->value.bytes.data[3 * i + 2]); 294 for (i = 0; i < 3 * numcoef; i++) 295 snd_soc_write(codec, STA32X_B1CF1 + i, 296 ucontrol->value.bytes.data[i]); 297 if (numcoef == 1) 298 snd_soc_write(codec, STA32X_CFUD, cfud | 0x01); 299 else if (numcoef == 5) 300 snd_soc_write(codec, STA32X_CFUD, cfud | 0x02); 301 else 302 return -EINVAL; 303 304 return 0; 305 } 306 307 static int sta32x_sync_coef_shadow(struct snd_soc_codec *codec) 308 { 309 struct sta32x_priv *sta32x = snd_soc_codec_get_drvdata(codec); 310 unsigned int cfud; 311 int i; 312 313 /* preserve reserved bits in STA32X_CFUD */ 314 cfud = snd_soc_read(codec, STA32X_CFUD) & 0xf0; 315 316 for (i = 0; i < STA32X_COEF_COUNT; i++) { 317 snd_soc_write(codec, STA32X_CFADDR2, i); 318 snd_soc_write(codec, STA32X_B1CF1, 319 (sta32x->coef_shadow[i] >> 16) & 0xff); 320 snd_soc_write(codec, STA32X_B1CF2, 321 (sta32x->coef_shadow[i] >> 8) & 0xff); 322 snd_soc_write(codec, STA32X_B1CF3, 323 (sta32x->coef_shadow[i]) & 0xff); 324 /* chip documentation does not say if the bits are 325 * self-clearing, so do it explicitly */ 326 snd_soc_write(codec, STA32X_CFUD, cfud); 327 snd_soc_write(codec, STA32X_CFUD, cfud | 0x01); 328 } 329 return 0; 330 } 331 332 static int sta32x_cache_sync(struct snd_soc_codec *codec) 333 { 334 struct sta32x_priv *sta32x = snd_soc_codec_get_drvdata(codec); 335 unsigned int mute; 336 int rc; 337 338 /* mute during register sync */ 339 mute = snd_soc_read(codec, STA32X_MMUTE); 340 snd_soc_write(codec, STA32X_MMUTE, mute | STA32X_MMUTE_MMUTE); 341 sta32x_sync_coef_shadow(codec); 342 rc = regcache_sync(sta32x->regmap); 343 snd_soc_write(codec, STA32X_MMUTE, mute); 344 return rc; 345 } 346 347 /* work around ESD issue where sta32x resets and loses all configuration */ 348 static void sta32x_watchdog(struct work_struct *work) 349 { 350 struct sta32x_priv *sta32x = container_of(work, struct sta32x_priv, 351 watchdog_work.work); 352 struct snd_soc_codec *codec = sta32x->codec; 353 unsigned int confa, confa_cached; 354 355 /* check if sta32x has reset itself */ 356 confa_cached = snd_soc_read(codec, STA32X_CONFA); 357 regcache_cache_bypass(sta32x->regmap, true); 358 confa = snd_soc_read(codec, STA32X_CONFA); 359 regcache_cache_bypass(sta32x->regmap, false); 360 if (confa != confa_cached) { 361 regcache_mark_dirty(sta32x->regmap); 362 sta32x_cache_sync(codec); 363 } 364 365 if (!sta32x->shutdown) 366 queue_delayed_work(system_power_efficient_wq, 367 &sta32x->watchdog_work, 368 round_jiffies_relative(HZ)); 369 } 370 371 static void sta32x_watchdog_start(struct sta32x_priv *sta32x) 372 { 373 if (sta32x->pdata->needs_esd_watchdog) { 374 sta32x->shutdown = 0; 375 queue_delayed_work(system_power_efficient_wq, 376 &sta32x->watchdog_work, 377 round_jiffies_relative(HZ)); 378 } 379 } 380 381 static void sta32x_watchdog_stop(struct sta32x_priv *sta32x) 382 { 383 if (sta32x->pdata->needs_esd_watchdog) { 384 sta32x->shutdown = 1; 385 cancel_delayed_work_sync(&sta32x->watchdog_work); 386 } 387 } 388 389 #define SINGLE_COEF(xname, index) \ 390 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 391 .info = sta32x_coefficient_info, \ 392 .get = sta32x_coefficient_get,\ 393 .put = sta32x_coefficient_put, \ 394 .private_value = index | (1 << 16) } 395 396 #define BIQUAD_COEFS(xname, index) \ 397 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 398 .info = sta32x_coefficient_info, \ 399 .get = sta32x_coefficient_get,\ 400 .put = sta32x_coefficient_put, \ 401 .private_value = index | (5 << 16) } 402 403 static const struct snd_kcontrol_new sta32x_snd_controls[] = { 404 SOC_SINGLE_TLV("Master Volume", STA32X_MVOL, 0, 0xff, 1, mvol_tlv), 405 SOC_SINGLE("Master Switch", STA32X_MMUTE, 0, 1, 1), 406 SOC_SINGLE("Ch1 Switch", STA32X_MMUTE, 1, 1, 1), 407 SOC_SINGLE("Ch2 Switch", STA32X_MMUTE, 2, 1, 1), 408 SOC_SINGLE("Ch3 Switch", STA32X_MMUTE, 3, 1, 1), 409 SOC_SINGLE_TLV("Ch1 Volume", STA32X_C1VOL, 0, 0xff, 1, chvol_tlv), 410 SOC_SINGLE_TLV("Ch2 Volume", STA32X_C2VOL, 0, 0xff, 1, chvol_tlv), 411 SOC_SINGLE_TLV("Ch3 Volume", STA32X_C3VOL, 0, 0xff, 1, chvol_tlv), 412 SOC_SINGLE("De-emphasis Filter Switch", STA32X_CONFD, STA32X_CONFD_DEMP_SHIFT, 1, 0), 413 SOC_ENUM("Compressor/Limiter Switch", sta32x_drc_ac_enum), 414 SOC_SINGLE("Miami Mode Switch", STA32X_CONFD, STA32X_CONFD_MME_SHIFT, 1, 0), 415 SOC_SINGLE("Zero Cross Switch", STA32X_CONFE, STA32X_CONFE_ZCE_SHIFT, 1, 0), 416 SOC_SINGLE("Soft Ramp Switch", STA32X_CONFE, STA32X_CONFE_SVE_SHIFT, 1, 0), 417 SOC_SINGLE("Auto-Mute Switch", STA32X_CONFF, STA32X_CONFF_IDE_SHIFT, 1, 0), 418 SOC_ENUM("Automode EQ", sta32x_auto_eq_enum), 419 SOC_ENUM("Automode GC", sta32x_auto_gc_enum), 420 SOC_ENUM("Automode XO", sta32x_auto_xo_enum), 421 SOC_ENUM("Preset EQ", sta32x_preset_eq_enum), 422 SOC_SINGLE("Ch1 Tone Control Bypass Switch", STA32X_C1CFG, STA32X_CxCFG_TCB_SHIFT, 1, 0), 423 SOC_SINGLE("Ch2 Tone Control Bypass Switch", STA32X_C2CFG, STA32X_CxCFG_TCB_SHIFT, 1, 0), 424 SOC_SINGLE("Ch1 EQ Bypass Switch", STA32X_C1CFG, STA32X_CxCFG_EQBP_SHIFT, 1, 0), 425 SOC_SINGLE("Ch2 EQ Bypass Switch", STA32X_C2CFG, STA32X_CxCFG_EQBP_SHIFT, 1, 0), 426 SOC_SINGLE("Ch1 Master Volume Bypass Switch", STA32X_C1CFG, STA32X_CxCFG_VBP_SHIFT, 1, 0), 427 SOC_SINGLE("Ch2 Master Volume Bypass Switch", STA32X_C1CFG, STA32X_CxCFG_VBP_SHIFT, 1, 0), 428 SOC_SINGLE("Ch3 Master Volume Bypass Switch", STA32X_C1CFG, STA32X_CxCFG_VBP_SHIFT, 1, 0), 429 SOC_ENUM("Ch1 Limiter Select", sta32x_limiter_ch1_enum), 430 SOC_ENUM("Ch2 Limiter Select", sta32x_limiter_ch2_enum), 431 SOC_ENUM("Ch3 Limiter Select", sta32x_limiter_ch3_enum), 432 SOC_SINGLE_TLV("Bass Tone Control", STA32X_TONE, STA32X_TONE_BTC_SHIFT, 15, 0, tone_tlv), 433 SOC_SINGLE_TLV("Treble Tone Control", STA32X_TONE, STA32X_TONE_TTC_SHIFT, 15, 0, tone_tlv), 434 SOC_ENUM("Limiter1 Attack Rate (dB/ms)", sta32x_limiter1_attack_rate_enum), 435 SOC_ENUM("Limiter2 Attack Rate (dB/ms)", sta32x_limiter2_attack_rate_enum), 436 SOC_ENUM("Limiter1 Release Rate (dB/ms)", sta32x_limiter1_release_rate_enum), 437 SOC_ENUM("Limiter2 Release Rate (dB/ms)", sta32x_limiter2_release_rate_enum), 438 439 /* depending on mode, the attack/release thresholds have 440 * two different enum definitions; provide both 441 */ 442 SOC_SINGLE_TLV("Limiter1 Attack Threshold (AC Mode)", STA32X_L1ATRT, STA32X_LxA_SHIFT, 443 16, 0, sta32x_limiter_ac_attack_tlv), 444 SOC_SINGLE_TLV("Limiter2 Attack Threshold (AC Mode)", STA32X_L2ATRT, STA32X_LxA_SHIFT, 445 16, 0, sta32x_limiter_ac_attack_tlv), 446 SOC_SINGLE_TLV("Limiter1 Release Threshold (AC Mode)", STA32X_L1ATRT, STA32X_LxR_SHIFT, 447 16, 0, sta32x_limiter_ac_release_tlv), 448 SOC_SINGLE_TLV("Limiter2 Release Threshold (AC Mode)", STA32X_L2ATRT, STA32X_LxR_SHIFT, 449 16, 0, sta32x_limiter_ac_release_tlv), 450 SOC_SINGLE_TLV("Limiter1 Attack Threshold (DRC Mode)", STA32X_L1ATRT, STA32X_LxA_SHIFT, 451 16, 0, sta32x_limiter_drc_attack_tlv), 452 SOC_SINGLE_TLV("Limiter2 Attack Threshold (DRC Mode)", STA32X_L2ATRT, STA32X_LxA_SHIFT, 453 16, 0, sta32x_limiter_drc_attack_tlv), 454 SOC_SINGLE_TLV("Limiter1 Release Threshold (DRC Mode)", STA32X_L1ATRT, STA32X_LxR_SHIFT, 455 16, 0, sta32x_limiter_drc_release_tlv), 456 SOC_SINGLE_TLV("Limiter2 Release Threshold (DRC Mode)", STA32X_L2ATRT, STA32X_LxR_SHIFT, 457 16, 0, sta32x_limiter_drc_release_tlv), 458 459 BIQUAD_COEFS("Ch1 - Biquad 1", 0), 460 BIQUAD_COEFS("Ch1 - Biquad 2", 5), 461 BIQUAD_COEFS("Ch1 - Biquad 3", 10), 462 BIQUAD_COEFS("Ch1 - Biquad 4", 15), 463 BIQUAD_COEFS("Ch2 - Biquad 1", 20), 464 BIQUAD_COEFS("Ch2 - Biquad 2", 25), 465 BIQUAD_COEFS("Ch2 - Biquad 3", 30), 466 BIQUAD_COEFS("Ch2 - Biquad 4", 35), 467 BIQUAD_COEFS("High-pass", 40), 468 BIQUAD_COEFS("Low-pass", 45), 469 SINGLE_COEF("Ch1 - Prescale", 50), 470 SINGLE_COEF("Ch2 - Prescale", 51), 471 SINGLE_COEF("Ch1 - Postscale", 52), 472 SINGLE_COEF("Ch2 - Postscale", 53), 473 SINGLE_COEF("Ch3 - Postscale", 54), 474 SINGLE_COEF("Thermal warning - Postscale", 55), 475 SINGLE_COEF("Ch1 - Mix 1", 56), 476 SINGLE_COEF("Ch1 - Mix 2", 57), 477 SINGLE_COEF("Ch2 - Mix 1", 58), 478 SINGLE_COEF("Ch2 - Mix 2", 59), 479 SINGLE_COEF("Ch3 - Mix 1", 60), 480 SINGLE_COEF("Ch3 - Mix 2", 61), 481 }; 482 483 static const struct snd_soc_dapm_widget sta32x_dapm_widgets[] = { 484 SND_SOC_DAPM_DAC("DAC", "Playback", SND_SOC_NOPM, 0, 0), 485 SND_SOC_DAPM_OUTPUT("LEFT"), 486 SND_SOC_DAPM_OUTPUT("RIGHT"), 487 SND_SOC_DAPM_OUTPUT("SUB"), 488 }; 489 490 static const struct snd_soc_dapm_route sta32x_dapm_routes[] = { 491 { "LEFT", NULL, "DAC" }, 492 { "RIGHT", NULL, "DAC" }, 493 { "SUB", NULL, "DAC" }, 494 }; 495 496 /* MCLK interpolation ratio per fs */ 497 static struct { 498 int fs; 499 int ir; 500 } interpolation_ratios[] = { 501 { 32000, 0 }, 502 { 44100, 0 }, 503 { 48000, 0 }, 504 { 88200, 1 }, 505 { 96000, 1 }, 506 { 176400, 2 }, 507 { 192000, 2 }, 508 }; 509 510 /* MCLK to fs clock ratios */ 511 static struct { 512 int ratio; 513 int mcs; 514 } mclk_ratios[3][7] = { 515 { { 768, 0 }, { 512, 1 }, { 384, 2 }, { 256, 3 }, 516 { 128, 4 }, { 576, 5 }, { 0, 0 } }, 517 { { 384, 2 }, { 256, 3 }, { 192, 4 }, { 128, 5 }, {64, 0 }, { 0, 0 } }, 518 { { 384, 2 }, { 256, 3 }, { 192, 4 }, { 128, 5 }, {64, 0 }, { 0, 0 } }, 519 }; 520 521 522 /** 523 * sta32x_set_dai_sysclk - configure MCLK 524 * @codec_dai: the codec DAI 525 * @clk_id: the clock ID (ignored) 526 * @freq: the MCLK input frequency 527 * @dir: the clock direction (ignored) 528 * 529 * The value of MCLK is used to determine which sample rates are supported 530 * by the STA32X, based on the mclk_ratios table. 531 * 532 * This function must be called by the machine driver's 'startup' function, 533 * otherwise the list of supported sample rates will not be available in 534 * time for ALSA. 535 * 536 * For setups with variable MCLKs, pass 0 as 'freq' argument. This will cause 537 * theoretically possible sample rates to be enabled. Call it again with a 538 * proper value set one the external clock is set (most probably you would do 539 * that from a machine's driver 'hw_param' hook. 540 */ 541 static int sta32x_set_dai_sysclk(struct snd_soc_dai *codec_dai, 542 int clk_id, unsigned int freq, int dir) 543 { 544 struct snd_soc_codec *codec = codec_dai->codec; 545 struct sta32x_priv *sta32x = snd_soc_codec_get_drvdata(codec); 546 int i, j, ir, fs; 547 unsigned int rates = 0; 548 unsigned int rate_min = -1; 549 unsigned int rate_max = 0; 550 551 pr_debug("mclk=%u\n", freq); 552 sta32x->mclk = freq; 553 554 if (sta32x->mclk) { 555 for (i = 0; i < ARRAY_SIZE(interpolation_ratios); i++) { 556 ir = interpolation_ratios[i].ir; 557 fs = interpolation_ratios[i].fs; 558 for (j = 0; mclk_ratios[ir][j].ratio; j++) { 559 if (mclk_ratios[ir][j].ratio * fs == freq) { 560 rates |= snd_pcm_rate_to_rate_bit(fs); 561 if (fs < rate_min) 562 rate_min = fs; 563 if (fs > rate_max) 564 rate_max = fs; 565 break; 566 } 567 } 568 } 569 /* FIXME: soc should support a rate list */ 570 rates &= ~SNDRV_PCM_RATE_KNOT; 571 572 if (!rates) { 573 dev_err(codec->dev, "could not find a valid sample rate\n"); 574 return -EINVAL; 575 } 576 } else { 577 /* enable all possible rates */ 578 rates = STA32X_RATES; 579 rate_min = 32000; 580 rate_max = 192000; 581 } 582 583 codec_dai->driver->playback.rates = rates; 584 codec_dai->driver->playback.rate_min = rate_min; 585 codec_dai->driver->playback.rate_max = rate_max; 586 return 0; 587 } 588 589 /** 590 * sta32x_set_dai_fmt - configure the codec for the selected audio format 591 * @codec_dai: the codec DAI 592 * @fmt: a SND_SOC_DAIFMT_x value indicating the data format 593 * 594 * This function takes a bitmask of SND_SOC_DAIFMT_x bits and programs the 595 * codec accordingly. 596 */ 597 static int sta32x_set_dai_fmt(struct snd_soc_dai *codec_dai, 598 unsigned int fmt) 599 { 600 struct snd_soc_codec *codec = codec_dai->codec; 601 struct sta32x_priv *sta32x = snd_soc_codec_get_drvdata(codec); 602 u8 confb = snd_soc_read(codec, STA32X_CONFB); 603 604 pr_debug("\n"); 605 confb &= ~(STA32X_CONFB_C1IM | STA32X_CONFB_C2IM); 606 607 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 608 case SND_SOC_DAIFMT_CBS_CFS: 609 break; 610 default: 611 return -EINVAL; 612 } 613 614 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 615 case SND_SOC_DAIFMT_I2S: 616 case SND_SOC_DAIFMT_RIGHT_J: 617 case SND_SOC_DAIFMT_LEFT_J: 618 sta32x->format = fmt & SND_SOC_DAIFMT_FORMAT_MASK; 619 break; 620 default: 621 return -EINVAL; 622 } 623 624 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 625 case SND_SOC_DAIFMT_NB_NF: 626 confb |= STA32X_CONFB_C2IM; 627 break; 628 case SND_SOC_DAIFMT_NB_IF: 629 confb |= STA32X_CONFB_C1IM; 630 break; 631 default: 632 return -EINVAL; 633 } 634 635 snd_soc_write(codec, STA32X_CONFB, confb); 636 return 0; 637 } 638 639 /** 640 * sta32x_hw_params - program the STA32X with the given hardware parameters. 641 * @substream: the audio stream 642 * @params: the hardware parameters to set 643 * @dai: the SOC DAI (ignored) 644 * 645 * This function programs the hardware with the values provided. 646 * Specifically, the sample rate and the data format. 647 */ 648 static int sta32x_hw_params(struct snd_pcm_substream *substream, 649 struct snd_pcm_hw_params *params, 650 struct snd_soc_dai *dai) 651 { 652 struct snd_soc_codec *codec = dai->codec; 653 struct sta32x_priv *sta32x = snd_soc_codec_get_drvdata(codec); 654 unsigned int rate; 655 int i, mcs = -1, ir = -1; 656 u8 confa, confb; 657 658 rate = params_rate(params); 659 pr_debug("rate: %u\n", rate); 660 for (i = 0; i < ARRAY_SIZE(interpolation_ratios); i++) 661 if (interpolation_ratios[i].fs == rate) { 662 ir = interpolation_ratios[i].ir; 663 break; 664 } 665 if (ir < 0) 666 return -EINVAL; 667 for (i = 0; mclk_ratios[ir][i].ratio; i++) 668 if (mclk_ratios[ir][i].ratio * rate == sta32x->mclk) { 669 mcs = mclk_ratios[ir][i].mcs; 670 break; 671 } 672 if (mcs < 0) 673 return -EINVAL; 674 675 confa = snd_soc_read(codec, STA32X_CONFA); 676 confa &= ~(STA32X_CONFA_MCS_MASK | STA32X_CONFA_IR_MASK); 677 confa |= (ir << STA32X_CONFA_IR_SHIFT) | (mcs << STA32X_CONFA_MCS_SHIFT); 678 679 confb = snd_soc_read(codec, STA32X_CONFB); 680 confb &= ~(STA32X_CONFB_SAI_MASK | STA32X_CONFB_SAIFB); 681 switch (params_format(params)) { 682 case SNDRV_PCM_FORMAT_S24_LE: 683 case SNDRV_PCM_FORMAT_S24_BE: 684 case SNDRV_PCM_FORMAT_S24_3LE: 685 case SNDRV_PCM_FORMAT_S24_3BE: 686 pr_debug("24bit\n"); 687 /* fall through */ 688 case SNDRV_PCM_FORMAT_S32_LE: 689 case SNDRV_PCM_FORMAT_S32_BE: 690 pr_debug("24bit or 32bit\n"); 691 switch (sta32x->format) { 692 case SND_SOC_DAIFMT_I2S: 693 confb |= 0x0; 694 break; 695 case SND_SOC_DAIFMT_LEFT_J: 696 confb |= 0x1; 697 break; 698 case SND_SOC_DAIFMT_RIGHT_J: 699 confb |= 0x2; 700 break; 701 } 702 703 break; 704 case SNDRV_PCM_FORMAT_S20_3LE: 705 case SNDRV_PCM_FORMAT_S20_3BE: 706 pr_debug("20bit\n"); 707 switch (sta32x->format) { 708 case SND_SOC_DAIFMT_I2S: 709 confb |= 0x4; 710 break; 711 case SND_SOC_DAIFMT_LEFT_J: 712 confb |= 0x5; 713 break; 714 case SND_SOC_DAIFMT_RIGHT_J: 715 confb |= 0x6; 716 break; 717 } 718 719 break; 720 case SNDRV_PCM_FORMAT_S18_3LE: 721 case SNDRV_PCM_FORMAT_S18_3BE: 722 pr_debug("18bit\n"); 723 switch (sta32x->format) { 724 case SND_SOC_DAIFMT_I2S: 725 confb |= 0x8; 726 break; 727 case SND_SOC_DAIFMT_LEFT_J: 728 confb |= 0x9; 729 break; 730 case SND_SOC_DAIFMT_RIGHT_J: 731 confb |= 0xa; 732 break; 733 } 734 735 break; 736 case SNDRV_PCM_FORMAT_S16_LE: 737 case SNDRV_PCM_FORMAT_S16_BE: 738 pr_debug("16bit\n"); 739 switch (sta32x->format) { 740 case SND_SOC_DAIFMT_I2S: 741 confb |= 0x0; 742 break; 743 case SND_SOC_DAIFMT_LEFT_J: 744 confb |= 0xd; 745 break; 746 case SND_SOC_DAIFMT_RIGHT_J: 747 confb |= 0xe; 748 break; 749 } 750 751 break; 752 default: 753 return -EINVAL; 754 } 755 756 snd_soc_write(codec, STA32X_CONFA, confa); 757 snd_soc_write(codec, STA32X_CONFB, confb); 758 return 0; 759 } 760 761 /** 762 * sta32x_set_bias_level - DAPM callback 763 * @codec: the codec device 764 * @level: DAPM power level 765 * 766 * This is called by ALSA to put the codec into low power mode 767 * or to wake it up. If the codec is powered off completely 768 * all registers must be restored after power on. 769 */ 770 static int sta32x_set_bias_level(struct snd_soc_codec *codec, 771 enum snd_soc_bias_level level) 772 { 773 int ret; 774 struct sta32x_priv *sta32x = snd_soc_codec_get_drvdata(codec); 775 776 pr_debug("level = %d\n", level); 777 switch (level) { 778 case SND_SOC_BIAS_ON: 779 break; 780 781 case SND_SOC_BIAS_PREPARE: 782 /* Full power on */ 783 snd_soc_update_bits(codec, STA32X_CONFF, 784 STA32X_CONFF_PWDN | STA32X_CONFF_EAPD, 785 STA32X_CONFF_PWDN | STA32X_CONFF_EAPD); 786 break; 787 788 case SND_SOC_BIAS_STANDBY: 789 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) { 790 ret = regulator_bulk_enable(ARRAY_SIZE(sta32x->supplies), 791 sta32x->supplies); 792 if (ret != 0) { 793 dev_err(codec->dev, 794 "Failed to enable supplies: %d\n", ret); 795 return ret; 796 } 797 798 sta32x_cache_sync(codec); 799 sta32x_watchdog_start(sta32x); 800 } 801 802 /* Power up to mute */ 803 /* FIXME */ 804 snd_soc_update_bits(codec, STA32X_CONFF, 805 STA32X_CONFF_PWDN | STA32X_CONFF_EAPD, 806 STA32X_CONFF_PWDN | STA32X_CONFF_EAPD); 807 808 break; 809 810 case SND_SOC_BIAS_OFF: 811 /* The chip runs through the power down sequence for us. */ 812 snd_soc_update_bits(codec, STA32X_CONFF, 813 STA32X_CONFF_PWDN | STA32X_CONFF_EAPD, 814 STA32X_CONFF_PWDN); 815 msleep(300); 816 sta32x_watchdog_stop(sta32x); 817 regulator_bulk_disable(ARRAY_SIZE(sta32x->supplies), 818 sta32x->supplies); 819 break; 820 } 821 codec->dapm.bias_level = level; 822 return 0; 823 } 824 825 static const struct snd_soc_dai_ops sta32x_dai_ops = { 826 .hw_params = sta32x_hw_params, 827 .set_sysclk = sta32x_set_dai_sysclk, 828 .set_fmt = sta32x_set_dai_fmt, 829 }; 830 831 static struct snd_soc_dai_driver sta32x_dai = { 832 .name = "STA32X", 833 .playback = { 834 .stream_name = "Playback", 835 .channels_min = 2, 836 .channels_max = 2, 837 .rates = STA32X_RATES, 838 .formats = STA32X_FORMATS, 839 }, 840 .ops = &sta32x_dai_ops, 841 }; 842 843 #ifdef CONFIG_PM 844 static int sta32x_suspend(struct snd_soc_codec *codec) 845 { 846 sta32x_set_bias_level(codec, SND_SOC_BIAS_OFF); 847 return 0; 848 } 849 850 static int sta32x_resume(struct snd_soc_codec *codec) 851 { 852 sta32x_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 853 return 0; 854 } 855 #else 856 #define sta32x_suspend NULL 857 #define sta32x_resume NULL 858 #endif 859 860 static int sta32x_probe(struct snd_soc_codec *codec) 861 { 862 struct sta32x_priv *sta32x = snd_soc_codec_get_drvdata(codec); 863 int i, ret = 0, thermal = 0; 864 865 sta32x->codec = codec; 866 sta32x->pdata = dev_get_platdata(codec->dev); 867 868 ret = regulator_bulk_enable(ARRAY_SIZE(sta32x->supplies), 869 sta32x->supplies); 870 if (ret != 0) { 871 dev_err(codec->dev, "Failed to enable supplies: %d\n", ret); 872 return ret; 873 } 874 875 /* Chip documentation explicitly requires that the reset values 876 * of reserved register bits are left untouched. 877 * Write the register default value to cache for reserved registers, 878 * so the write to the these registers are suppressed by the cache 879 * restore code when it skips writes of default registers. 880 */ 881 regcache_cache_only(sta32x->regmap, true); 882 snd_soc_write(codec, STA32X_CONFC, 0xc2); 883 snd_soc_write(codec, STA32X_CONFE, 0xc2); 884 snd_soc_write(codec, STA32X_CONFF, 0x5c); 885 snd_soc_write(codec, STA32X_MMUTE, 0x10); 886 snd_soc_write(codec, STA32X_AUTO1, 0x60); 887 snd_soc_write(codec, STA32X_AUTO3, 0x00); 888 snd_soc_write(codec, STA32X_C3CFG, 0x40); 889 regcache_cache_only(sta32x->regmap, false); 890 891 /* set thermal warning adjustment and recovery */ 892 if (!(sta32x->pdata->thermal_conf & STA32X_THERMAL_ADJUSTMENT_ENABLE)) 893 thermal |= STA32X_CONFA_TWAB; 894 if (!(sta32x->pdata->thermal_conf & STA32X_THERMAL_RECOVERY_ENABLE)) 895 thermal |= STA32X_CONFA_TWRB; 896 snd_soc_update_bits(codec, STA32X_CONFA, 897 STA32X_CONFA_TWAB | STA32X_CONFA_TWRB, 898 thermal); 899 900 /* select output configuration */ 901 snd_soc_update_bits(codec, STA32X_CONFF, 902 STA32X_CONFF_OCFG_MASK, 903 sta32x->pdata->output_conf 904 << STA32X_CONFF_OCFG_SHIFT); 905 906 /* channel to output mapping */ 907 snd_soc_update_bits(codec, STA32X_C1CFG, 908 STA32X_CxCFG_OM_MASK, 909 sta32x->pdata->ch1_output_mapping 910 << STA32X_CxCFG_OM_SHIFT); 911 snd_soc_update_bits(codec, STA32X_C2CFG, 912 STA32X_CxCFG_OM_MASK, 913 sta32x->pdata->ch2_output_mapping 914 << STA32X_CxCFG_OM_SHIFT); 915 snd_soc_update_bits(codec, STA32X_C3CFG, 916 STA32X_CxCFG_OM_MASK, 917 sta32x->pdata->ch3_output_mapping 918 << STA32X_CxCFG_OM_SHIFT); 919 920 /* initialize coefficient shadow RAM with reset values */ 921 for (i = 4; i <= 49; i += 5) 922 sta32x->coef_shadow[i] = 0x400000; 923 for (i = 50; i <= 54; i++) 924 sta32x->coef_shadow[i] = 0x7fffff; 925 sta32x->coef_shadow[55] = 0x5a9df7; 926 sta32x->coef_shadow[56] = 0x7fffff; 927 sta32x->coef_shadow[59] = 0x7fffff; 928 sta32x->coef_shadow[60] = 0x400000; 929 sta32x->coef_shadow[61] = 0x400000; 930 931 if (sta32x->pdata->needs_esd_watchdog) 932 INIT_DELAYED_WORK(&sta32x->watchdog_work, sta32x_watchdog); 933 934 sta32x_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 935 /* Bias level configuration will have done an extra enable */ 936 regulator_bulk_disable(ARRAY_SIZE(sta32x->supplies), sta32x->supplies); 937 938 return 0; 939 } 940 941 static int sta32x_remove(struct snd_soc_codec *codec) 942 { 943 struct sta32x_priv *sta32x = snd_soc_codec_get_drvdata(codec); 944 945 sta32x_watchdog_stop(sta32x); 946 sta32x_set_bias_level(codec, SND_SOC_BIAS_OFF); 947 regulator_bulk_disable(ARRAY_SIZE(sta32x->supplies), sta32x->supplies); 948 949 return 0; 950 } 951 952 static bool sta32x_reg_is_volatile(struct device *dev, unsigned int reg) 953 { 954 switch (reg) { 955 case STA32X_CONFA ... STA32X_L2ATRT: 956 case STA32X_MPCC1 ... STA32X_FDRC2: 957 return 0; 958 } 959 return 1; 960 } 961 962 static const struct snd_soc_codec_driver sta32x_codec = { 963 .probe = sta32x_probe, 964 .remove = sta32x_remove, 965 .suspend = sta32x_suspend, 966 .resume = sta32x_resume, 967 .set_bias_level = sta32x_set_bias_level, 968 .controls = sta32x_snd_controls, 969 .num_controls = ARRAY_SIZE(sta32x_snd_controls), 970 .dapm_widgets = sta32x_dapm_widgets, 971 .num_dapm_widgets = ARRAY_SIZE(sta32x_dapm_widgets), 972 .dapm_routes = sta32x_dapm_routes, 973 .num_dapm_routes = ARRAY_SIZE(sta32x_dapm_routes), 974 }; 975 976 static const struct regmap_config sta32x_regmap = { 977 .reg_bits = 8, 978 .val_bits = 8, 979 .max_register = STA32X_FDRC2, 980 .reg_defaults = sta32x_regs, 981 .num_reg_defaults = ARRAY_SIZE(sta32x_regs), 982 .cache_type = REGCACHE_RBTREE, 983 .volatile_reg = sta32x_reg_is_volatile, 984 }; 985 986 static int sta32x_i2c_probe(struct i2c_client *i2c, 987 const struct i2c_device_id *id) 988 { 989 struct sta32x_priv *sta32x; 990 int ret, i; 991 992 sta32x = devm_kzalloc(&i2c->dev, sizeof(struct sta32x_priv), 993 GFP_KERNEL); 994 if (!sta32x) 995 return -ENOMEM; 996 997 /* regulators */ 998 for (i = 0; i < ARRAY_SIZE(sta32x->supplies); i++) 999 sta32x->supplies[i].supply = sta32x_supply_names[i]; 1000 1001 ret = devm_regulator_bulk_get(&i2c->dev, ARRAY_SIZE(sta32x->supplies), 1002 sta32x->supplies); 1003 if (ret != 0) { 1004 dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret); 1005 return ret; 1006 } 1007 1008 sta32x->regmap = devm_regmap_init_i2c(i2c, &sta32x_regmap); 1009 if (IS_ERR(sta32x->regmap)) { 1010 ret = PTR_ERR(sta32x->regmap); 1011 dev_err(&i2c->dev, "Failed to init regmap: %d\n", ret); 1012 return ret; 1013 } 1014 1015 i2c_set_clientdata(i2c, sta32x); 1016 1017 ret = snd_soc_register_codec(&i2c->dev, &sta32x_codec, &sta32x_dai, 1); 1018 if (ret != 0) 1019 dev_err(&i2c->dev, "Failed to register codec (%d)\n", ret); 1020 1021 return ret; 1022 } 1023 1024 static int sta32x_i2c_remove(struct i2c_client *client) 1025 { 1026 snd_soc_unregister_codec(&client->dev); 1027 return 0; 1028 } 1029 1030 static const struct i2c_device_id sta32x_i2c_id[] = { 1031 { "sta326", 0 }, 1032 { "sta328", 0 }, 1033 { "sta329", 0 }, 1034 { } 1035 }; 1036 MODULE_DEVICE_TABLE(i2c, sta32x_i2c_id); 1037 1038 static struct i2c_driver sta32x_i2c_driver = { 1039 .driver = { 1040 .name = "sta32x", 1041 .owner = THIS_MODULE, 1042 }, 1043 .probe = sta32x_i2c_probe, 1044 .remove = sta32x_i2c_remove, 1045 .id_table = sta32x_i2c_id, 1046 }; 1047 1048 module_i2c_driver(sta32x_i2c_driver); 1049 1050 MODULE_DESCRIPTION("ASoC STA32X driver"); 1051 MODULE_AUTHOR("Johannes Stezenbach <js@sig21.net>"); 1052 MODULE_LICENSE("GPL"); 1053