1*68cd394eSKiseokJo /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*68cd394eSKiseokJo /* 3*68cd394eSKiseokJo * sma1303.h -- sma1303 ALSA SoC Audio driver 4*68cd394eSKiseokJo * 5*68cd394eSKiseokJo * Copyright 2023 Iron Device Corporation 6*68cd394eSKiseokJo * 7*68cd394eSKiseokJo * Author: Kiseok Jo <kiseok.jo@irondevice.com> 8*68cd394eSKiseokJo * 9*68cd394eSKiseokJo */ 10*68cd394eSKiseokJo 11*68cd394eSKiseokJo #ifndef _SMA1303_H 12*68cd394eSKiseokJo #define _SMA1303_H 13*68cd394eSKiseokJo 14*68cd394eSKiseokJo #define SMA1303_I2C_ADDR_00 0x1e 15*68cd394eSKiseokJo #define SMA1303_I2C_ADDR_01 0x3e 16*68cd394eSKiseokJo #define SMA1303_I2C_ADDR_10 0x5e 17*68cd394eSKiseokJo #define SMA1303_I2C_ADDR_11 0x7e 18*68cd394eSKiseokJo 19*68cd394eSKiseokJo #define SMA1303_EXTERNAL_CLOCK_19_2 0x00 20*68cd394eSKiseokJo #define SMA1303_EXTERNAL_CLOCK_24_576 0x01 21*68cd394eSKiseokJo #define SMA1303_PLL_CLKIN_MCLK 0x02 22*68cd394eSKiseokJo #define SMA1303_PLL_CLKIN_BCLK 0x03 23*68cd394eSKiseokJo 24*68cd394eSKiseokJo #define SMA1303_MONO 0x00 25*68cd394eSKiseokJo #define SMA1303_STEREO 0x01 26*68cd394eSKiseokJo 27*68cd394eSKiseokJo #define SMA1303_I2C_RETRY_COUNT 3 28*68cd394eSKiseokJo 29*68cd394eSKiseokJo /* 30*68cd394eSKiseokJo * SMA1303 Register Definition 31*68cd394eSKiseokJo */ 32*68cd394eSKiseokJo 33*68cd394eSKiseokJo /* SMA1303 Register Addresses */ 34*68cd394eSKiseokJo #define SMA1303_00_SYSTEM_CTRL 0x00 35*68cd394eSKiseokJo #define SMA1303_01_INPUT1_CTRL1 0x01 36*68cd394eSKiseokJo #define SMA1303_02_INPUT1_CTRL2 0x02 37*68cd394eSKiseokJo #define SMA1303_03_INPUT1_CTRL3 0x03 38*68cd394eSKiseokJo #define SMA1303_04_INPUT1_CTRL4 0x04 39*68cd394eSKiseokJo /* 0x05 ~ 0x08 : Reserved */ 40*68cd394eSKiseokJo #define SMA1303_09_OUTPUT_CTRL 0x09 41*68cd394eSKiseokJo #define SMA1303_0A_SPK_VOL 0x0a 42*68cd394eSKiseokJo #define SMA1303_0B_BST_TEST 0x0b 43*68cd394eSKiseokJo #define SMA1303_0C_BST_TEST1 0x0c 44*68cd394eSKiseokJo #define SMA1303_0D_SPK_TEST 0x0d 45*68cd394eSKiseokJo #define SMA1303_0E_MUTE_VOL_CTRL 0x0e 46*68cd394eSKiseokJo /* 0x0F : Reserved */ 47*68cd394eSKiseokJo #define SMA1303_10_SYSTEM_CTRL1 0x10 48*68cd394eSKiseokJo #define SMA1303_11_SYSTEM_CTRL2 0x11 49*68cd394eSKiseokJo #define SMA1303_12_SYSTEM_CTRL3 0x12 50*68cd394eSKiseokJo /* 0x13 : Reserved */ 51*68cd394eSKiseokJo #define SMA1303_14_MODULATOR 0x14 52*68cd394eSKiseokJo #define SMA1303_15_BASS_SPK1 0x15 53*68cd394eSKiseokJo #define SMA1303_16_BASS_SPK2 0x16 54*68cd394eSKiseokJo #define SMA1303_17_BASS_SPK3 0x17 55*68cd394eSKiseokJo #define SMA1303_18_BASS_SPK4 0x18 56*68cd394eSKiseokJo #define SMA1303_19_BASS_SPK5 0x19 57*68cd394eSKiseokJo #define SMA1303_1A_BASS_SPK6 0x1a 58*68cd394eSKiseokJo #define SMA1303_1B_BASS_SPK7 0x1b 59*68cd394eSKiseokJo /* 0x1C ~ 0x22 : Reserved */ 60*68cd394eSKiseokJo #define SMA1303_23_COMP_LIM1 0x23 61*68cd394eSKiseokJo #define SMA1303_24_COMP_LIM2 0x24 62*68cd394eSKiseokJo #define SMA1303_25_COMP_LIM3 0x25 63*68cd394eSKiseokJo #define SMA1303_26_COMP_LIM4 0x26 64*68cd394eSKiseokJo /* 0x27 ~ 0x32 : Reserved */ 65*68cd394eSKiseokJo #define SMA1303_33_SDM_CTRL 0x33 66*68cd394eSKiseokJo #define SMA1303_34_OTP_DATA1 0x34 67*68cd394eSKiseokJo /* 0x35 : Reserved */ 68*68cd394eSKiseokJo #define SMA1303_36_PROTECTION 0x36 69*68cd394eSKiseokJo #define SMA1303_37_SLOPE_CTRL 0x37 70*68cd394eSKiseokJo #define SMA1303_38_OTP_TRM0 0x38 71*68cd394eSKiseokJo /* 0x39 ~ 0x3A : Reserved */ 72*68cd394eSKiseokJo #define SMA1303_3B_TEST1 0x3b 73*68cd394eSKiseokJo #define SMA1303_3C_TEST2 0x3c 74*68cd394eSKiseokJo #define SMA1303_3D_TEST3 0x3d 75*68cd394eSKiseokJo #define SMA1303_3E_ATEST1 0x3e 76*68cd394eSKiseokJo #define SMA1303_3F_ATEST2 0x3f 77*68cd394eSKiseokJo /* 0x40 ~ 0x8A : Reserved */ 78*68cd394eSKiseokJo #define SMA1303_8B_PLL_POST_N 0x8b 79*68cd394eSKiseokJo #define SMA1303_8C_PLL_N 0x8c 80*68cd394eSKiseokJo #define SMA1303_8D_PLL_A_SETTING 0x8d 81*68cd394eSKiseokJo #define SMA1303_8E_PLL_CTRL 0x8e 82*68cd394eSKiseokJo #define SMA1303_8F_PLL_P_CP 0x8f 83*68cd394eSKiseokJo #define SMA1303_90_POSTSCALER 0x90 84*68cd394eSKiseokJo #define SMA1303_91_CLASS_G_CTRL 0x91 85*68cd394eSKiseokJo #define SMA1303_92_FDPEC_CTRL 0x92 86*68cd394eSKiseokJo /* 0x93 : Reserved */ 87*68cd394eSKiseokJo #define SMA1303_94_BOOST_CTRL1 0x94 88*68cd394eSKiseokJo #define SMA1303_95_BOOST_CTRL2 0x95 89*68cd394eSKiseokJo #define SMA1303_96_BOOST_CTRL3 0x96 90*68cd394eSKiseokJo #define SMA1303_97_BOOST_CTRL4 0x97 91*68cd394eSKiseokJo /* 0x98 ~ 0x9F : Reserved */ 92*68cd394eSKiseokJo #define SMA1303_A0_PAD_CTRL0 0xa0 93*68cd394eSKiseokJo #define SMA1303_A1_PAD_CTRL1 0xa1 94*68cd394eSKiseokJo #define SMA1303_A2_TOP_MAN1 0xa2 95*68cd394eSKiseokJo #define SMA1303_A3_TOP_MAN2 0xa3 96*68cd394eSKiseokJo #define SMA1303_A4_TOP_MAN3 0xa4 97*68cd394eSKiseokJo #define SMA1303_A5_TDM1 0xa5 98*68cd394eSKiseokJo #define SMA1303_A6_TDM2 0xa6 99*68cd394eSKiseokJo #define SMA1303_A7_CLK_MON 0xa7 100*68cd394eSKiseokJo /* 0xA8 ~ 0xF9 : Reserved */ 101*68cd394eSKiseokJo #define SMA1303_FA_STATUS1 0xfa 102*68cd394eSKiseokJo #define SMA1303_FB_STATUS2 0xfb 103*68cd394eSKiseokJo /* 0xFC ~ 0xFE : Reserved */ 104*68cd394eSKiseokJo #define SMA1303_FF_DEVICE_INDEX 0xff 105*68cd394eSKiseokJo 106*68cd394eSKiseokJo /* SMA1303 Registers Bit Fields */ 107*68cd394eSKiseokJo 108*68cd394eSKiseokJo /* SYSTEM_CTRL : 0x00 */ 109*68cd394eSKiseokJo #define SMA1303_RESETBYI2C_MASK (1<<1) 110*68cd394eSKiseokJo #define SMA1303_RESETBYI2C_NORMAL (0<<1) 111*68cd394eSKiseokJo #define SMA1303_RESETBYI2C_RESET (1<<1) 112*68cd394eSKiseokJo 113*68cd394eSKiseokJo #define SMA1303_POWER_MASK (1<<0) 114*68cd394eSKiseokJo #define SMA1303_POWER_OFF (0<<0) 115*68cd394eSKiseokJo #define SMA1303_POWER_ON (1<<0) 116*68cd394eSKiseokJo 117*68cd394eSKiseokJo /* INTPUT CTRL1 : 0x01 */ 118*68cd394eSKiseokJo #define SMA1303_CONTROLLER_DEVICE_MASK (1<<7) 119*68cd394eSKiseokJo #define SMA1303_DEVICE_MODE (0<<7) 120*68cd394eSKiseokJo #define SMA1303_CONTROLLER_MODE (1<<7) 121*68cd394eSKiseokJo 122*68cd394eSKiseokJo #define SMA1303_I2S_MODE_MASK (7<<4) 123*68cd394eSKiseokJo #define SMA1303_STANDARD_I2S (0<<4) 124*68cd394eSKiseokJo #define SMA1303_LJ (1<<4) 125*68cd394eSKiseokJo #define SMA1303_RJ_16BIT (4<<4) 126*68cd394eSKiseokJo #define SMA1303_RJ_18BIT (5<<4) 127*68cd394eSKiseokJo #define SMA1303_RJ_20BIT (6<<4) 128*68cd394eSKiseokJo #define SMA1303_RJ_24BIT (7<<4) 129*68cd394eSKiseokJo 130*68cd394eSKiseokJo #define SMA1303_LEFTPOL_MASK (1<<3) 131*68cd394eSKiseokJo #define SMA1303_LOW_FIRST_CH (0<<3) 132*68cd394eSKiseokJo #define SMA1303_HIGH_FIRST_CH (1<<3) 133*68cd394eSKiseokJo 134*68cd394eSKiseokJo #define SMA1303_SCK_RISING_MASK (1<<2) 135*68cd394eSKiseokJo #define SMA1303_SCK_FALLING_EDGE (0<<2) 136*68cd394eSKiseokJo #define SMA1303_SCK_RISING_EDGE (1<<2) 137*68cd394eSKiseokJo 138*68cd394eSKiseokJo /* INTPUT CTRL2 : 0x02 */ 139*68cd394eSKiseokJo #define SMA1303_IMODE_MASK (3<<6) 140*68cd394eSKiseokJo #define SMA1303_I2S (0<<6) 141*68cd394eSKiseokJo #define SMA1303_PCM_SHORT (1<<6) 142*68cd394eSKiseokJo #define SMA1303_PCM_LONG (2<<6) 143*68cd394eSKiseokJo 144*68cd394eSKiseokJo #define RSMA1303_IGHT_FIRST_MASK (1<<5) 145*68cd394eSKiseokJo #define SMA1303_LEFT_NORMAL (0<<5) 146*68cd394eSKiseokJo #define SMA1303_RIGHT_INVERTED (1<<5) 147*68cd394eSKiseokJo 148*68cd394eSKiseokJo #define SMA1303_PCM_ALAW_MASK (1<<4) 149*68cd394eSKiseokJo #define SMA1303_PCM_U_DECODING (0<<4) 150*68cd394eSKiseokJo #define SMA1303_PCM_A_DECODING (1<<4) 151*68cd394eSKiseokJo 152*68cd394eSKiseokJo #define SMA1303_PCM_COMP_MASK (1<<3) 153*68cd394eSKiseokJo #define SMA1303_PCM_LINEAR (0<<3) 154*68cd394eSKiseokJo #define SMA1303_PCM_COMPANDING (1<<3) 155*68cd394eSKiseokJo 156*68cd394eSKiseokJo #define SMA1303_INPUTSEL_MASK (1<<2) 157*68cd394eSKiseokJo #define SMA1303_PCM_8KHZ (0<<2) 158*68cd394eSKiseokJo #define SMA1303_PCM_16KHZ (1<<2) 159*68cd394eSKiseokJo 160*68cd394eSKiseokJo #define SMA1303_PCM_STEREO_MASK (1<<1) 161*68cd394eSKiseokJo #define SMA1303_PCM_MONO (0<<1) 162*68cd394eSKiseokJo #define SMA1303_PCM_STEREO (1<<1) 163*68cd394eSKiseokJo 164*68cd394eSKiseokJo #define SMA1303_PCM_DL_MASK (1<<0) 165*68cd394eSKiseokJo #define SMA1303_PCM_8BIT (0<<0) 166*68cd394eSKiseokJo #define SMA1303_PCM_16BIT (1<<0) 167*68cd394eSKiseokJo 168*68cd394eSKiseokJo /* INTPUT CTRL3 : 0x03 */ 169*68cd394eSKiseokJo #define SMA1303_PCM_N_SLOT_MASK (15<<0) 170*68cd394eSKiseokJo #define SMA1303_PCM_N_SLOT1 (0<<0) 171*68cd394eSKiseokJo #define SMA1303_PCM_N_SLOT2 (1<<0) 172*68cd394eSKiseokJo #define SMA1303_PCM_N_SLOT3 (2<<0) 173*68cd394eSKiseokJo #define SMA1303_PCM_N_SLOT4 (3<<0) 174*68cd394eSKiseokJo #define SMA1303_PCM_N_SLOT5 (4<<0) 175*68cd394eSKiseokJo #define SMA1303_PCM_N_SLOT6 (5<<0) 176*68cd394eSKiseokJo #define SMA1303_PCM_N_SLOT7 (6<<0) 177*68cd394eSKiseokJo #define SMA1303_PCM_N_SLOT8 (7<<0) 178*68cd394eSKiseokJo #define SMA1303_PCM_N_SLOT9 (8<<0) 179*68cd394eSKiseokJo #define SMA1303_PCM_N_SLOT10 (9<<0) 180*68cd394eSKiseokJo #define SMA1303_PCM_N_SLOT11 (10<<0) 181*68cd394eSKiseokJo #define SMA1303_PCM_N_SLOT12 (11<<0) 182*68cd394eSKiseokJo #define SMA1303_PCM_N_SLOT13 (12<<0) 183*68cd394eSKiseokJo #define SMA1303_PCM_N_SLOT14 (13<<0) 184*68cd394eSKiseokJo #define SMA1303_PCM_N_SLOT15 (14<<0) 185*68cd394eSKiseokJo #define SMA1303_PCM_N_SLOT16 (15<<0) 186*68cd394eSKiseokJo 187*68cd394eSKiseokJo /* INTPUT CTRL4 : 0x04 */ 188*68cd394eSKiseokJo #define SMA1303_PCM1_SLOT_MASK (15<<4) 189*68cd394eSKiseokJo #define SMA1303_PCM1_SLOT1 (0<<4) 190*68cd394eSKiseokJo #define SMA1303_PCM1_SLOT2 (1<<4) 191*68cd394eSKiseokJo #define SMA1303_PCM1_SLOT3 (2<<4) 192*68cd394eSKiseokJo #define SMA1303_PCM1_SLOT4 (3<<4) 193*68cd394eSKiseokJo #define SMA1303_PCM1_SLOT5 (4<<4) 194*68cd394eSKiseokJo #define SMA1303_PCM1_SLOT6 (5<<4) 195*68cd394eSKiseokJo #define SMA1303_PCM1_SLOT7 (6<<4) 196*68cd394eSKiseokJo #define SMA1303_PCM1_SLOT8 (7<<4) 197*68cd394eSKiseokJo #define SMA1303_PCM1_SLOT9 (8<<4) 198*68cd394eSKiseokJo #define SMA1303_PCM1_SLOT10 (9<<4) 199*68cd394eSKiseokJo #define SMA1303_PCM1_SLOT11 (10<<4) 200*68cd394eSKiseokJo #define SMA1303_PCM1_SLOT12 (11<<4) 201*68cd394eSKiseokJo #define SMA1303_PCM1_SLOT13 (12<<4) 202*68cd394eSKiseokJo #define SMA1303_PCM1_SLOT14 (13<<4) 203*68cd394eSKiseokJo #define SMA1303_PCM1_SLOT15 (14<<4) 204*68cd394eSKiseokJo #define SMA1303_PCM1_SLOT16 (15<<4) 205*68cd394eSKiseokJo 206*68cd394eSKiseokJo #define SMA1303_PCM2_SLOT_MASK (15<<0) 207*68cd394eSKiseokJo #define SMA1303_PCM2_SLOT1 (0<<0) 208*68cd394eSKiseokJo #define SMA1303_PCM2_SLOT2 (1<<0) 209*68cd394eSKiseokJo #define SMA1303_PCM2_SLOT3 (2<<0) 210*68cd394eSKiseokJo #define SMA1303_PCM2_SLOT4 (3<<0) 211*68cd394eSKiseokJo #define SMA1303_PCM2_SLOT5 (4<<0) 212*68cd394eSKiseokJo #define SMA1303_PCM2_SLOT6 (5<<0) 213*68cd394eSKiseokJo #define SMA1303_PCM2_SLOT7 (6<<0) 214*68cd394eSKiseokJo #define SMA1303_PCM2_SLOT8 (7<<0) 215*68cd394eSKiseokJo #define SMA1303_PCM2_SLOT9 (8<<0) 216*68cd394eSKiseokJo #define SMA1303_PCM2_SLOT10 (9<<0) 217*68cd394eSKiseokJo #define SMA1303_PCM2_SLOT11 (10<<0) 218*68cd394eSKiseokJo #define SMA1303_PCM2_SLOT12 (11<<0) 219*68cd394eSKiseokJo #define SMA1303_PCM2_SLOT13 (12<<0) 220*68cd394eSKiseokJo #define SMA1303_PCM2_SLOT14 (13<<0) 221*68cd394eSKiseokJo #define SMA1303_PCM2_SLOT15 (14<<0) 222*68cd394eSKiseokJo #define SMA1303_PCM2_SLOT16 (15<<0) 223*68cd394eSKiseokJo 224*68cd394eSKiseokJo /* OUTPUT CTRL : 0x09 */ 225*68cd394eSKiseokJo #define SMA1303_PORT_CONFIG_MASK (3<<5) 226*68cd394eSKiseokJo #define SMA1303_INPUT_PORT_ONLY (0<<5) 227*68cd394eSKiseokJo #define SMA1303_OUTPUT_PORT_ENABLE (2<<5) 228*68cd394eSKiseokJo 229*68cd394eSKiseokJo #define SMA1303_PORT_OUT_SEL_MASK (7<<0) 230*68cd394eSKiseokJo #define SMA1303_OUT_SEL_DISABLE (0<<0) 231*68cd394eSKiseokJo #define SMA1303_FORMAT_CONVERTER (1<<0) 232*68cd394eSKiseokJo #define SMA1303_MIXER_OUTPUT (2<<0) 233*68cd394eSKiseokJo #define SMA1303_SPEAKER_PATH (3<<0) 234*68cd394eSKiseokJo #define SMA1303_POSTSCALER_OUTPUT (4<<0) 235*68cd394eSKiseokJo 236*68cd394eSKiseokJo /* BST_TEST : 0x0B */ 237*68cd394eSKiseokJo #define SMA1303_BST_OFF_SLOPE_MASK (3<<6) 238*68cd394eSKiseokJo #define SMA1303_BST_OFF_SLOPE_6_7ns (0<<6) 239*68cd394eSKiseokJo #define SMA1303_BST_OFF_SLOPE_4_8ns (1<<6) 240*68cd394eSKiseokJo #define SMA1303_BST_OFF_SLOPE_2_6ns (2<<6) 241*68cd394eSKiseokJo #define SMA1303_BST_OFF_SLOPE_1_2ns (3<<6) 242*68cd394eSKiseokJo 243*68cd394eSKiseokJo #define SMA1303_OCP_TEST_MASK (1<<5) 244*68cd394eSKiseokJo #define SMA1303_OCP_NORMAL_MODE (0<<5) 245*68cd394eSKiseokJo #define SMA1303_OCP_TEST_MODE (1<<5) 246*68cd394eSKiseokJo 247*68cd394eSKiseokJo #define SMA1303_BST_FAST_LEBN_MASK (1<<4) 248*68cd394eSKiseokJo #define SMA1303_BST_SHORT_LEB (0<<4) 249*68cd394eSKiseokJo #define SMA1303_BST_LONG_LEB (1<<4) 250*68cd394eSKiseokJo 251*68cd394eSKiseokJo #define SMA1303_HIGH_PGAIN_MASK (1<<3) 252*68cd394eSKiseokJo #define SMA1303_NORMAL_P_GAIN (0<<3) 253*68cd394eSKiseokJo #define SMA1303_HIGH_P_GAIN (1<<3) 254*68cd394eSKiseokJo 255*68cd394eSKiseokJo #define SMA1303_VCOMP_MASK (1<<2) 256*68cd394eSKiseokJo #define SMA1303_VCOMP_NORMAL_MODE (0<<2) 257*68cd394eSKiseokJo #define SMA1303_VCOMP_V_MON_MODE (1<<2) 258*68cd394eSKiseokJo 259*68cd394eSKiseokJo #define SMA1303_PMOS_ON_MASK (1<<1) 260*68cd394eSKiseokJo #define SMA1303_PMOS_NORMAL_MODE (0<<1) 261*68cd394eSKiseokJo #define SMA1303_PMOS_TEST_MODE (1<<1) 262*68cd394eSKiseokJo 263*68cd394eSKiseokJo #define SMA1303_NMOS_ON_MASK (1<<0) 264*68cd394eSKiseokJo #define SMA1303_NMOS_NORMAL_MODE (0<<0) 265*68cd394eSKiseokJo #define SMA1303_NMOS_TEST_MODE (1<<0) 266*68cd394eSKiseokJo 267*68cd394eSKiseokJo /* BST_TEST1 : 0x0C */ 268*68cd394eSKiseokJo #define SMA1303_SET_OCP_H_MASK (3<<6) 269*68cd394eSKiseokJo #define SMA1303_HIGH_OCP_4_5_LVL (0<<6) 270*68cd394eSKiseokJo #define SMA1303_HIGH_OCP_3_2_LVL (1<<6) 271*68cd394eSKiseokJo #define SMA1303_HIGH_OCP_2_1_LVL (2<<6) 272*68cd394eSKiseokJo #define SMA1303_HIGH_OCP_0_9_LVL (3<<6) 273*68cd394eSKiseokJo 274*68cd394eSKiseokJo #define SMA1303_OCL_TEST_MASK (1<<5) 275*68cd394eSKiseokJo #define SMA1303_OCL_NORMAL_MODE (0<<5) 276*68cd394eSKiseokJo #define SMA1303_OCL_TEST_MODE (1<<5) 277*68cd394eSKiseokJo 278*68cd394eSKiseokJo #define SMA1303_LOOP_CHECK_MASK (1<<4) 279*68cd394eSKiseokJo #define SMA1303_BST_LOOP_NORMAL_MODE (0<<4) 280*68cd394eSKiseokJo #define SMA1303_BST_LOOP_CHECK_MODE (1<<4) 281*68cd394eSKiseokJo 282*68cd394eSKiseokJo #define SMA1303_EN_SH_PRT_MASK (1<<3) 283*68cd394eSKiseokJo #define SMA1303_EN_SH_PRT_DISABLE (0<<3) 284*68cd394eSKiseokJo #define SMA1303_EN_SH_PRT_ENABLE (1<<3) 285*68cd394eSKiseokJo 286*68cd394eSKiseokJo /* SPK_TEST : 0x0D */ 287*68cd394eSKiseokJo #define SMA1303_VREF_MON_MASK (1<<3) 288*68cd394eSKiseokJo #define SMA1303_VREF_NORMAL_MODE (0<<3) 289*68cd394eSKiseokJo #define SMA1303_VREF_V_MON_MODE (1<<3) 290*68cd394eSKiseokJo 291*68cd394eSKiseokJo #define SMA1303_SPK_OCP_DLYN_MASK (1<<2) 292*68cd394eSKiseokJo #define SMA1303_SPK_OCP_LONG_DELAY (0<<2) 293*68cd394eSKiseokJo #define SMA1303_SPK_OCP_NORMAL (1<<2) 294*68cd394eSKiseokJo 295*68cd394eSKiseokJo #define SMA1303_SPK_OFF_SLOPE_MASK (3<<0) 296*68cd394eSKiseokJo #define SMA1303_SPK_OFF_SLOPE_SLOW (0<<0) 297*68cd394eSKiseokJo #define SMA1303_SPK_OFF_SLOPE_FAST (3<<0) 298*68cd394eSKiseokJo 299*68cd394eSKiseokJo /* MUTE_VOL_CTRL : 0x0E */ 300*68cd394eSKiseokJo #define SMA1303_VOL_SLOPE_MASK (3<<6) 301*68cd394eSKiseokJo #define SMA1303_VOL_SLOPE_OFF (0<<6) 302*68cd394eSKiseokJo #define SMA1303_VOL_SLOPE_SLOW (1<<6) 303*68cd394eSKiseokJo #define SMA1303_VOL_SLOPE_MID (2<<6) 304*68cd394eSKiseokJo #define SMA1303_VOL_SLOPE_FAST (3<<6) 305*68cd394eSKiseokJo 306*68cd394eSKiseokJo #define SMA1303_MUTE_SLOPE_MASK (3<<4) 307*68cd394eSKiseokJo #define SMA1303_MUTE_SLOPE_OFF (0<<4) 308*68cd394eSKiseokJo #define SMA1303_MUTE_SLOPE_SLOW (1<<4) 309*68cd394eSKiseokJo #define SMA1303_MUTE_SLOPE_MID (2<<4) 310*68cd394eSKiseokJo #define SMA1303_MUTE_SLOPE_FAST (3<<4) 311*68cd394eSKiseokJo 312*68cd394eSKiseokJo #define SMA1303_SPK_MUTE_MASK (1<<0) 313*68cd394eSKiseokJo #define SMA1303_SPK_UNMUTE (0<<0) 314*68cd394eSKiseokJo #define SMA1303_SPK_MUTE (1<<0) 315*68cd394eSKiseokJo 316*68cd394eSKiseokJo /* SYSTEM_CTRL1 :0x10 */ 317*68cd394eSKiseokJo #define SMA1303_SPK_MODE_MASK (7<<2) 318*68cd394eSKiseokJo #define SMA1303_SPK_OFF (0<<2) 319*68cd394eSKiseokJo #define SMA1303_SPK_MONO (1<<2) 320*68cd394eSKiseokJo #define SMA1303_SPK_STEREO (4<<2) 321*68cd394eSKiseokJo 322*68cd394eSKiseokJo /* SYSTEM_CTRL2 : 0x11 */ 323*68cd394eSKiseokJo #define SMA1303_SPK_BS_MASK (1<<6) 324*68cd394eSKiseokJo #define SMA1303_SPK_BS_BYP (0<<6) 325*68cd394eSKiseokJo #define SMA1303_SPK_BS_EN (1<<6) 326*68cd394eSKiseokJo #define SMA1303_SPK_LIM_MASK (1<<5) 327*68cd394eSKiseokJo #define SMA1303_SPK_LIM_BYP (0<<5) 328*68cd394eSKiseokJo #define SMA1303_SPK_LIM_EN (1<<5) 329*68cd394eSKiseokJo 330*68cd394eSKiseokJo #define SMA1303_LR_DATA_SW_MASK (1<<4) 331*68cd394eSKiseokJo #define SMA1303_LR_DATA_SW_NORMAL (0<<4) 332*68cd394eSKiseokJo #define SMA1303_LR_DATA_SW_SWAP (1<<4) 333*68cd394eSKiseokJo 334*68cd394eSKiseokJo #define SMA1303_MONOMIX_MASK (1<<0) 335*68cd394eSKiseokJo #define SMA1303_MONOMIX_OFF (0<<0) 336*68cd394eSKiseokJo #define SMA1303_MONOMIX_ON (1<<0) 337*68cd394eSKiseokJo 338*68cd394eSKiseokJo /* SYSTEM_CTRL3 : 0x12 */ 339*68cd394eSKiseokJo #define SMA1303_INPUT_MASK (3<<6) 340*68cd394eSKiseokJo #define SMA1303_INPUT_0_DB (0<<6) 341*68cd394eSKiseokJo #define SMA1303_INPUT_M6_DB (1<<6) 342*68cd394eSKiseokJo #define SMA1303_INPUT_M12_DB (2<<6) 343*68cd394eSKiseokJo #define SMA1303_INPUT_INFI_DB (3<<6) 344*68cd394eSKiseokJo #define SMA1303_INPUT_R_MASK (3<<4) 345*68cd394eSKiseokJo #define SMA1303_INPUT_R_0_DB (0<<4) 346*68cd394eSKiseokJo #define SMA1303_INPUT_R_M6_DB (1<<4) 347*68cd394eSKiseokJo #define SMA1303_INPUT_R_M12_DB (2<<4) 348*68cd394eSKiseokJo #define SMA1303_INPUT_R_INFI_DB (3<<4) 349*68cd394eSKiseokJo 350*68cd394eSKiseokJo /* Modulator : 0x14 */ 351*68cd394eSKiseokJo #define SMA1303_SPK_HYSFB_MASK (3<<6) 352*68cd394eSKiseokJo #define SMA1303_HYSFB_625K (0<<6) 353*68cd394eSKiseokJo #define SMA1303_HYSFB_414K (1<<6) 354*68cd394eSKiseokJo #define SMA1303_HYSFB_297K (2<<6) 355*68cd394eSKiseokJo #define SMA1303_HYSFB_226K (3<<6) 356*68cd394eSKiseokJo #define SMA1303_SPK_BDELAY_MASK (63<<0) 357*68cd394eSKiseokJo 358*68cd394eSKiseokJo /* SDM CONTROL : 0x33 */ 359*68cd394eSKiseokJo #define SMA1303_SDM_Q_SEL_MASK (1<<2) 360*68cd394eSKiseokJo #define SMA1303_QUART_SEL_1_DIV_4 (0<<2) 361*68cd394eSKiseokJo #define SMA1303_QUART_SEL_1_DIV_8 (1<<2) 362*68cd394eSKiseokJo 363*68cd394eSKiseokJo /* OTP_DATA1 : 0x34 */ 364*68cd394eSKiseokJo #define SMA1303_OTP_LVL_MASK (1<<5) 365*68cd394eSKiseokJo #define SMA1303_OTP_LVL_NORMAL (0<<5) 366*68cd394eSKiseokJo #define SMA1303_OTP_LVL_LOW (1<<5) 367*68cd394eSKiseokJo 368*68cd394eSKiseokJo /* PROTECTION : 0x36 */ 369*68cd394eSKiseokJo #define SMA1303_EDGE_DIS_MASK (1<<7) 370*68cd394eSKiseokJo #define SMA1303_EDGE_DIS_ENABLE (0<<7) 371*68cd394eSKiseokJo #define SMA1303_EDGE_DIS_DISABLE (1<<7) 372*68cd394eSKiseokJo 373*68cd394eSKiseokJo #define SMA1303_SPK_OCP_DIS_MASK (1<<3) 374*68cd394eSKiseokJo #define SMA1303_SPK_OCP_ENABLE (0<<3) 375*68cd394eSKiseokJo #define SMA1303_SPK_OCP_DISABLE (1<<3) 376*68cd394eSKiseokJo 377*68cd394eSKiseokJo #define SMA1303_OCP_MODE_MASK (1<<2) 378*68cd394eSKiseokJo #define SMA1303_AUTO_RECOVER (0<<2) 379*68cd394eSKiseokJo #define SMA1303_SHUT_DOWN_PERMANENT (1<<2) 380*68cd394eSKiseokJo 381*68cd394eSKiseokJo #define SMA1303_OTP_MODE_MASK (3<<0) 382*68cd394eSKiseokJo #define SMA1303_OTP_MODE_DISABLE (0<<0) 383*68cd394eSKiseokJo #define SMA1303_IG_THR1_SHUT_THR2 (1<<0) 384*68cd394eSKiseokJo #define SMA1303_REC_THR1_SHUT_THR2 (2<<0) 385*68cd394eSKiseokJo #define SMA1303_SHUT_THR1_SHUT_THR2 (3<<0) 386*68cd394eSKiseokJo 387*68cd394eSKiseokJo /* TEST2 : 0x3C */ 388*68cd394eSKiseokJo #define SMA1303_SPK_HSDM_BP_MASK (1<<4) 389*68cd394eSKiseokJo #define SMA1303_SPK_HSDM_ENABLE (0<<4) 390*68cd394eSKiseokJo #define SMA1303_SPK_HSDM_BYPASS (1<<4) 391*68cd394eSKiseokJo 392*68cd394eSKiseokJo #define SMA1303_SDM_SYNC_DIS_MASK (1<<5) 393*68cd394eSKiseokJo #define SMA1303_SDM_SYNC_NORMAL (0<<5) 394*68cd394eSKiseokJo #define SMA1303_SDM_SYNC_DISABLE (1<<5) 395*68cd394eSKiseokJo 396*68cd394eSKiseokJo /* ATEST2 : 0x3F */ 397*68cd394eSKiseokJo #define SMA1303_SPK_OUT_FREQ_MASK (1<<2) 398*68cd394eSKiseokJo #define SMA1303_SPK_OUT_FREQ_360K (0<<2) 399*68cd394eSKiseokJo #define SMA1303_SPK_OUT_FREQ_410K (1<<2) 400*68cd394eSKiseokJo 401*68cd394eSKiseokJo #define SMA1303_LOW_POWER_MODE_MASK (1<<3) 402*68cd394eSKiseokJo #define SMA1303_LOW_POWER_MODE_DISABLE (0<<3) 403*68cd394eSKiseokJo #define SMA1303_LOW_POWER_MODE_ENABLE (1<<3) 404*68cd394eSKiseokJo 405*68cd394eSKiseokJo #define SMA1303_THERMAL_ADJUST_MASK (3<<5) 406*68cd394eSKiseokJo #define SMA1303_THERMAL_150_110 (0<<5) 407*68cd394eSKiseokJo #define SMA1303_THERMAL_160_120 (1<<5) 408*68cd394eSKiseokJo #define SMA1303_THERMAL_140_100 (2<<5) 409*68cd394eSKiseokJo 410*68cd394eSKiseokJo #define SMA1303_FAST_OFF_DRIVE_SPK_MASK (1<<0) 411*68cd394eSKiseokJo #define SMA1303_FAST_OFF_DRIVE_SPK_DISABLE (0<<0) 412*68cd394eSKiseokJo #define SMA1303_FAST_OFF_DRIVE_SPK_ENABLE (1<<0) 413*68cd394eSKiseokJo 414*68cd394eSKiseokJo /* PLL_CTRL : 0x8E */ 415*68cd394eSKiseokJo #define SMA1303_TRM_LVL_MASK (1<<4) 416*68cd394eSKiseokJo #define SMA1303_TRM_LVL_NORMAL (0<<4) 417*68cd394eSKiseokJo #define SMA1303_TRM_LVL_LOW (1<<4) 418*68cd394eSKiseokJo 419*68cd394eSKiseokJo #define SMA1303_LOW_OCL_MODE_MASK (1<<3) 420*68cd394eSKiseokJo #define SMA1303_LOW_OCL_MODE (0<<3) 421*68cd394eSKiseokJo #define SMA1303_NORMAL_OCL_MODE (1<<3) 422*68cd394eSKiseokJo 423*68cd394eSKiseokJo #define SMA1303_PLL_PD2_MASK (7<<0) 424*68cd394eSKiseokJo #define SMA1303_PLL_PD2 (7<<0) 425*68cd394eSKiseokJo #define SMA1303_PLL_OPERATION2 (0<<0) 426*68cd394eSKiseokJo 427*68cd394eSKiseokJo /* POSTSCALER : 0x90 */ 428*68cd394eSKiseokJo #define SMA1303_BYP_POST_MASK (1<<0) 429*68cd394eSKiseokJo #define SMA1303_EN_POST_SCALER (0<<0) 430*68cd394eSKiseokJo #define SMA1303_BYP_POST_SCALER (1<<0) 431*68cd394eSKiseokJo 432*68cd394eSKiseokJo /* FDPEC CONTROL : 0x92 */ 433*68cd394eSKiseokJo #define SMA1303_FLT_VDD_GAIN_MASK (15<<4) 434*68cd394eSKiseokJo #define SMA1303_FLT_VDD_GAIN_2P40 (0<<4) 435*68cd394eSKiseokJo #define SMA1303_FLT_VDD_GAIN_2P45 (1<<4) 436*68cd394eSKiseokJo #define SMA1303_FLT_VDD_GAIN_2P50 (2<<4) 437*68cd394eSKiseokJo #define SMA1303_FLT_VDD_GAIN_2P55 (3<<4) 438*68cd394eSKiseokJo #define SMA1303_FLT_VDD_GAIN_2P60 (4<<4) 439*68cd394eSKiseokJo #define SMA1303_FLT_VDD_GAIN_2P65 (5<<4) 440*68cd394eSKiseokJo #define SMA1303_FLT_VDD_GAIN_2P70 (6<<4) 441*68cd394eSKiseokJo #define SMA1303_FLT_VDD_GAIN_2P75 (7<<4) 442*68cd394eSKiseokJo #define SMA1303_FLT_VDD_GAIN_2P80 (8<<4) 443*68cd394eSKiseokJo #define SMA1303_FLT_VDD_GAIN_2P85 (9<<4) 444*68cd394eSKiseokJo #define SMA1303_FLT_VDD_GAIN_2P90 (10<<4) 445*68cd394eSKiseokJo #define SMA1303_FLT_VDD_GAIN_2P95 (11<<4) 446*68cd394eSKiseokJo #define SMA1303_FLT_VDD_GAIN_3P00 (12<<4) 447*68cd394eSKiseokJo #define SMA1303_FLT_VDD_GAIN_3P05 (13<<4) 448*68cd394eSKiseokJo #define SMA1303_FLT_VDD_GAIN_3P10 (14<<4) 449*68cd394eSKiseokJo #define SMA1303_FLT_VDD_GAIN_3P15 (15<<4) 450*68cd394eSKiseokJo 451*68cd394eSKiseokJo #define SMA1303_DIS_FCHG_MASK (1<<2) 452*68cd394eSKiseokJo #define SMA1303_EN_FAST_CHARGE (0<<2) 453*68cd394eSKiseokJo #define SMA1303_DIS_FAST_CHARGE (1<<2) 454*68cd394eSKiseokJo 455*68cd394eSKiseokJo /* BOOST_CONTROL4 : 0x97 */ 456*68cd394eSKiseokJo #define SMA1303_TRM_VBST_MASK (7<<2) 457*68cd394eSKiseokJo #define SMA1303_TRM_VBST_5P5 (0<<2) 458*68cd394eSKiseokJo #define SMA1303_TRM_VBST_5P6 (1<<2) 459*68cd394eSKiseokJo #define SMA1303_TRM_VBST_5P7 (2<<2) 460*68cd394eSKiseokJo #define SMA1303_TRM_VBST_5P8 (3<<2) 461*68cd394eSKiseokJo #define SMA1303_TRM_VBST_5P9 (4<<2) 462*68cd394eSKiseokJo #define SMA1303_TRM_VBST_6P0 (5<<2) 463*68cd394eSKiseokJo #define SMA1303_TRM_VBST_6P1 (6<<2) 464*68cd394eSKiseokJo #define SMA1303_TRM_VBST_6P2 (7<<2) 465*68cd394eSKiseokJo 466*68cd394eSKiseokJo /* TOP_MAN1 : 0xA2 */ 467*68cd394eSKiseokJo #define SMA1303_PLL_LOCK_SKIP_MASK (1<<7) 468*68cd394eSKiseokJo #define SMA1303_PLL_LOCK_ENABLE (0<<7) 469*68cd394eSKiseokJo #define SMA1303_PLL_LOCK_DISABLE (1<<7) 470*68cd394eSKiseokJo 471*68cd394eSKiseokJo #define SMA1303_PLL_PD_MASK (1<<6) 472*68cd394eSKiseokJo #define SMA1303_PLL_OPERATION (0<<6) 473*68cd394eSKiseokJo #define SMA1303_PLL_PD (1<<6) 474*68cd394eSKiseokJo 475*68cd394eSKiseokJo #define SMA1303_PLL_DIV_MASK (3<<4) 476*68cd394eSKiseokJo #define SMA1303_PLL_OUT (0<<4) 477*68cd394eSKiseokJo #define SMA1303_PLL_OUT_2 (1<<4) 478*68cd394eSKiseokJo #define SMA1303_PLL_OUT_4 (2<<4) 479*68cd394eSKiseokJo #define SMA1303_PLL_OUT_8 (3<<4) 480*68cd394eSKiseokJo 481*68cd394eSKiseokJo #define SMA1303_PLL_REF_CLK_MASK (1<<3) 482*68cd394eSKiseokJo #define SMA1303_PLL_REF_CLK1 (0<<3) 483*68cd394eSKiseokJo #define SMA1303_PLL_SCK (1<<3) 484*68cd394eSKiseokJo 485*68cd394eSKiseokJo #define SMA1303_DAC_DN_CONV_MASK (1<<2) 486*68cd394eSKiseokJo #define SMA1303_DAC_DN_CONV_DISABLE (0<<2) 487*68cd394eSKiseokJo #define SMA1303_DAC_DN_CONV_ENABLE (1<<2) 488*68cd394eSKiseokJo 489*68cd394eSKiseokJo #define SMA1303_SDO_IO_MASK (1<<1) 490*68cd394eSKiseokJo #define SMA1303_HIGH_Z_LRCK_H (0<<1) 491*68cd394eSKiseokJo #define SMA1303_HIGH_Z_LRCK_L (1<<1) 492*68cd394eSKiseokJo 493*68cd394eSKiseokJo #define SMA1303_SDO_OUTPUT2_MASK (1<<0) 494*68cd394eSKiseokJo #define SMA1303_SDO_NORMAL (0<<0) 495*68cd394eSKiseokJo #define SMA1303_SDO_OUTPUT_ONLY (1<<0) 496*68cd394eSKiseokJo 497*68cd394eSKiseokJo /* TOP_MAN2 : 0xA3 */ 498*68cd394eSKiseokJo #define SMA1303_MON_OSC_PLL_MASK (1<<7) 499*68cd394eSKiseokJo #define SMA1303_PLL_SDO (0<<7) 500*68cd394eSKiseokJo #define SMA1303_OSC_SDO (1<<7) 501*68cd394eSKiseokJo 502*68cd394eSKiseokJo #define SMA1303_TEST_CLKO_EN_MASK (1<<6) 503*68cd394eSKiseokJo #define SMA1303_NORMAL_SDO (0<<6) 504*68cd394eSKiseokJo #define SMA1303_CLK_OUT_SDO (1<<6) 505*68cd394eSKiseokJo 506*68cd394eSKiseokJo #define SMA1303_SDO_OUTPUT_MASK (1<<3) 507*68cd394eSKiseokJo #define SMA1303_NORMAL_OUT (0<<3) 508*68cd394eSKiseokJo #define SMA1303_HIGH_Z_OUT (1<<3) 509*68cd394eSKiseokJo 510*68cd394eSKiseokJo #define SMA1303_CLOCK_MON_MASK (1<<1) 511*68cd394eSKiseokJo #define SMA1303_CLOCK_MON (0<<1) 512*68cd394eSKiseokJo #define SMA1303_CLOCK_NOT_MON (1<<1) 513*68cd394eSKiseokJo 514*68cd394eSKiseokJo #define SMA1303_OSC_PD_MASK (1<<0) 515*68cd394eSKiseokJo #define SMA1303_NORMAL_OPERATION_OSC (0<<0) 516*68cd394eSKiseokJo #define SMA1303_POWER_DOWN_OSC (1<<0) 517*68cd394eSKiseokJo 518*68cd394eSKiseokJo /* TOP_MAN3 0xA4 */ 519*68cd394eSKiseokJo #define SMA1303_O_FORMAT_MASK (7<<5) 520*68cd394eSKiseokJo #define SMA1303_O_FMT_LJ (1<<5) 521*68cd394eSKiseokJo #define SMA1303_O_FMT_I2S (2<<5) 522*68cd394eSKiseokJo #define SMA1303_O_FMT_TDM (4<<5) 523*68cd394eSKiseokJo 524*68cd394eSKiseokJo #define SMA1303_SCK_RATE_MASK (1<<3) 525*68cd394eSKiseokJo #define SMA1303_SCK_64FS (0<<3) 526*68cd394eSKiseokJo #define SMA1303_SCK_32FS (2<<3) 527*68cd394eSKiseokJo 528*68cd394eSKiseokJo #define SMA1303_LRCK_POL_MASK (1<<0) 529*68cd394eSKiseokJo #define SMA1303_L_VALID (0<<0) 530*68cd394eSKiseokJo #define SMA1303_R_VALID (1<<0) 531*68cd394eSKiseokJo 532*68cd394eSKiseokJo /* TDM1 FORMAT : 0xA5 */ 533*68cd394eSKiseokJo #define SMA1303_TDM_CLK_POL_MASK (1<<7) 534*68cd394eSKiseokJo #define SMA1303_TDM_CLK_POL_RISE (0<<7) 535*68cd394eSKiseokJo #define SMA1303_TDM_CLK_POL_FALL (1<<7) 536*68cd394eSKiseokJo 537*68cd394eSKiseokJo #define SMA1303_TDM_TX_MODE_MASK (1<<6) 538*68cd394eSKiseokJo #define SMA1303_TDM_TX_MONO (0<<6) 539*68cd394eSKiseokJo #define SMA1303_TDM_TX_STEREO (1<<6) 540*68cd394eSKiseokJo 541*68cd394eSKiseokJo #define SMA1303_TDM_SLOT1_RX_POS_MASK (7<<3) 542*68cd394eSKiseokJo #define SMA1303_TDM_SLOT1_RX_POS_0 (0<<3) 543*68cd394eSKiseokJo #define SMA1303_TDM_SLOT1_RX_POS_1 (1<<3) 544*68cd394eSKiseokJo #define SMA1303_TDM_SLOT1_RX_POS_2 (2<<3) 545*68cd394eSKiseokJo #define SMA1303_TDM_SLOT1_RX_POS_3 (3<<3) 546*68cd394eSKiseokJo #define SMA1303_TDM_SLOT1_RX_POS_4 (4<<3) 547*68cd394eSKiseokJo #define SMA1303_TDM_SLOT1_RX_POS_5 (5<<3) 548*68cd394eSKiseokJo #define SMA1303_TDM_SLOT1_RX_POS_6 (6<<3) 549*68cd394eSKiseokJo #define SMA1303_TDM_SLOT1_RX_POS_7 (7<<3) 550*68cd394eSKiseokJo 551*68cd394eSKiseokJo #define SMA1303_TDM_SLOT2_RX_POS_MASK (7<<0) 552*68cd394eSKiseokJo #define SMA1303_TDM_SLOT2_RX_POS_0 (0<<0) 553*68cd394eSKiseokJo #define SMA1303_TDM_SLOT2_RX_POS_1 (1<<0) 554*68cd394eSKiseokJo #define SMA1303_TDM_SLOT2_RX_POS_2 (2<<0) 555*68cd394eSKiseokJo #define SMA1303_TDM_SLOT2_RX_POS_3 (3<<0) 556*68cd394eSKiseokJo #define SMA1303_TDM_SLOT2_RX_POS_4 (4<<0) 557*68cd394eSKiseokJo #define SMA1303_TDM_SLOT2_RX_POS_5 (5<<0) 558*68cd394eSKiseokJo #define SMA1303_TDM_SLOT2_RX_POS_6 (6<<0) 559*68cd394eSKiseokJo #define SMA1303_TDM_SLOT2_RX_POS_7 (7<<0) 560*68cd394eSKiseokJo 561*68cd394eSKiseokJo /* TDM2 FORMAT : 0xA6 */ 562*68cd394eSKiseokJo #define SMA1303_TDM_DL_MASK (1<<7) 563*68cd394eSKiseokJo #define SMA1303_TDM_DL_16 (0<<7) 564*68cd394eSKiseokJo #define SMA1303_TDM_DL_32 (1<<7) 565*68cd394eSKiseokJo 566*68cd394eSKiseokJo #define SMA1303_TDM_N_SLOT_MASK (1<<6) 567*68cd394eSKiseokJo #define SMA1303_TDM_N_SLOT_4 (0<<6) 568*68cd394eSKiseokJo #define SMA1303_TDM_N_SLOT_8 (1<<6) 569*68cd394eSKiseokJo 570*68cd394eSKiseokJo #define SMA1303_TDM_SLOT1_TX_POS_MASK (7<<3) 571*68cd394eSKiseokJo #define SMA1303_TDM_SLOT1_TX_POS_0 (0<<3) 572*68cd394eSKiseokJo #define SMA1303_TDM_SLOT1_TX_POS_1 (1<<3) 573*68cd394eSKiseokJo #define SMA1303_TDM_SLOT1_TX_POS_2 (2<<3) 574*68cd394eSKiseokJo #define SMA1303_TDM_SLOT1_TX_POS_3 (3<<3) 575*68cd394eSKiseokJo #define SMA1303_TDM_SLOT1_TX_POS_4 (4<<3) 576*68cd394eSKiseokJo #define SMA1303_TDM_SLOT1_TX_POS_5 (5<<3) 577*68cd394eSKiseokJo #define SMA1303_TDM_SLOT1_TX_POS_6 (6<<3) 578*68cd394eSKiseokJo #define SMA1303_TDM_SLOT1_TX_POS_7 (7<<3) 579*68cd394eSKiseokJo 580*68cd394eSKiseokJo #define SMA1303_TDM_SLOT2_TX_POS_MASK (7<<0) 581*68cd394eSKiseokJo #define SMA1303_TDM_SLOT2_TX_POS_0 (0<<0) 582*68cd394eSKiseokJo #define SMA1303_TDM_SLOT2_TX_POS_1 (1<<0) 583*68cd394eSKiseokJo #define SMA1303_TDM_SLOT2_TX_POS_2 (2<<0) 584*68cd394eSKiseokJo #define SMA1303_TDM_SLOT2_TX_POS_3 (3<<0) 585*68cd394eSKiseokJo #define SMA1303_TDM_SLOT2_TX_POS_4 (4<<0) 586*68cd394eSKiseokJo #define SMA1303_TDM_SLOT2_TX_POS_5 (5<<0) 587*68cd394eSKiseokJo #define SMA1303_TDM_SLOT2_TX_POS_6 (6<<0) 588*68cd394eSKiseokJo #define SMA1303_TDM_SLOT2_TX_POS_7 (7<<0) 589*68cd394eSKiseokJo 590*68cd394eSKiseokJo /* STATUS1 : 0xFA */ 591*68cd394eSKiseokJo #define SMA1303_OT1_OK_STATUS (1<<7) 592*68cd394eSKiseokJo #define SMA1303_OT2_OK_STATUS (1<<6) 593*68cd394eSKiseokJo 594*68cd394eSKiseokJo /* STATUS2 : 0xFB */ 595*68cd394eSKiseokJo #define SMA1303_OCP_SPK_STATUS (1<<5) 596*68cd394eSKiseokJo #define SMA1303_OCP_BST_STATUS (1<<4) 597*68cd394eSKiseokJo #define SMA1303_OTP_STAT_OK_0 (5<<1) 598*68cd394eSKiseokJo #define SMA1303_OTP_STAT_OK_1 (2<<2) 599*68cd394eSKiseokJo 600*68cd394eSKiseokJo #define SMA1303_CLK_MON_STATUS (1<<0) 601*68cd394eSKiseokJo 602*68cd394eSKiseokJo /* DEVICE_INFO : 0xFF */ 603*68cd394eSKiseokJo #define SMA1303_DEVICE_ID (2<<3) 604*68cd394eSKiseokJo #define SMA1303_UVLO_BST_STATUS (1<<2) 605*68cd394eSKiseokJo #define SMA1303_REV_NUM_STATUS (3<<0) 606*68cd394eSKiseokJo #define SMA1303_REV_NUM_TV0 (0<<0) 607*68cd394eSKiseokJo #define SMA1303_REV_NUM_TV1 (1<<0) 608*68cd394eSKiseokJo 609*68cd394eSKiseokJo #endif 610