1 /* 2 * sgtl5000.c -- SGTL5000 ALSA SoC Audio driver 3 * 4 * Copyright 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11 #include <linux/module.h> 12 #include <linux/moduleparam.h> 13 #include <linux/init.h> 14 #include <linux/delay.h> 15 #include <linux/slab.h> 16 #include <linux/pm.h> 17 #include <linux/i2c.h> 18 #include <linux/clk.h> 19 #include <linux/regmap.h> 20 #include <linux/regulator/driver.h> 21 #include <linux/regulator/machine.h> 22 #include <linux/regulator/consumer.h> 23 #include <linux/of_device.h> 24 #include <sound/core.h> 25 #include <sound/tlv.h> 26 #include <sound/pcm.h> 27 #include <sound/pcm_params.h> 28 #include <sound/soc.h> 29 #include <sound/soc-dapm.h> 30 #include <sound/initval.h> 31 32 #include "sgtl5000.h" 33 34 #define SGTL5000_DAP_REG_OFFSET 0x0100 35 #define SGTL5000_MAX_REG_OFFSET 0x013A 36 37 /* default value of sgtl5000 registers */ 38 static const struct reg_default sgtl5000_reg_defaults[] = { 39 { SGTL5000_CHIP_CLK_CTRL, 0x0008 }, 40 { SGTL5000_CHIP_I2S_CTRL, 0x0010 }, 41 { SGTL5000_CHIP_SSS_CTRL, 0x0010 }, 42 { SGTL5000_CHIP_DAC_VOL, 0x3c3c }, 43 { SGTL5000_CHIP_PAD_STRENGTH, 0x015f }, 44 { SGTL5000_CHIP_ANA_HP_CTRL, 0x1818 }, 45 { SGTL5000_CHIP_ANA_CTRL, 0x0111 }, 46 { SGTL5000_CHIP_LINE_OUT_VOL, 0x0404 }, 47 { SGTL5000_CHIP_ANA_POWER, 0x7060 }, 48 { SGTL5000_CHIP_PLL_CTRL, 0x5000 }, 49 { SGTL5000_DAP_BASS_ENHANCE, 0x0040 }, 50 { SGTL5000_DAP_BASS_ENHANCE_CTRL, 0x051f }, 51 { SGTL5000_DAP_SURROUND, 0x0040 }, 52 { SGTL5000_DAP_EQ_BASS_BAND0, 0x002f }, 53 { SGTL5000_DAP_EQ_BASS_BAND1, 0x002f }, 54 { SGTL5000_DAP_EQ_BASS_BAND2, 0x002f }, 55 { SGTL5000_DAP_EQ_BASS_BAND3, 0x002f }, 56 { SGTL5000_DAP_EQ_BASS_BAND4, 0x002f }, 57 { SGTL5000_DAP_MAIN_CHAN, 0x8000 }, 58 { SGTL5000_DAP_AVC_CTRL, 0x0510 }, 59 { SGTL5000_DAP_AVC_THRESHOLD, 0x1473 }, 60 { SGTL5000_DAP_AVC_ATTACK, 0x0028 }, 61 { SGTL5000_DAP_AVC_DECAY, 0x0050 }, 62 }; 63 64 /* regulator supplies for sgtl5000, VDDD is an optional external supply */ 65 enum sgtl5000_regulator_supplies { 66 VDDA, 67 VDDIO, 68 VDDD, 69 SGTL5000_SUPPLY_NUM 70 }; 71 72 /* vddd is optional supply */ 73 static const char *supply_names[SGTL5000_SUPPLY_NUM] = { 74 "VDDA", 75 "VDDIO", 76 "VDDD" 77 }; 78 79 #define LDO_CONSUMER_NAME "VDDD_LDO" 80 #define LDO_VOLTAGE 1200000 81 82 static struct regulator_consumer_supply ldo_consumer[] = { 83 REGULATOR_SUPPLY(LDO_CONSUMER_NAME, NULL), 84 }; 85 86 static struct regulator_init_data ldo_init_data = { 87 .constraints = { 88 .min_uV = 1200000, 89 .max_uV = 1200000, 90 .valid_modes_mask = REGULATOR_MODE_NORMAL, 91 .valid_ops_mask = REGULATOR_CHANGE_STATUS, 92 }, 93 .num_consumer_supplies = 1, 94 .consumer_supplies = &ldo_consumer[0], 95 }; 96 97 /* 98 * sgtl5000 internal ldo regulator, 99 * enabled when VDDD not provided 100 */ 101 struct ldo_regulator { 102 struct regulator_desc desc; 103 struct regulator_dev *dev; 104 int voltage; 105 void *codec_data; 106 bool enabled; 107 }; 108 109 /* sgtl5000 private structure in codec */ 110 struct sgtl5000_priv { 111 int sysclk; /* sysclk rate */ 112 int master; /* i2s master or not */ 113 int fmt; /* i2s data format */ 114 struct regulator_bulk_data supplies[SGTL5000_SUPPLY_NUM]; 115 struct ldo_regulator *ldo; 116 struct regmap *regmap; 117 struct clk *mclk; 118 }; 119 120 /* 121 * mic_bias power on/off share the same register bits with 122 * output impedance of mic bias, when power on mic bias, we 123 * need reclaim it to impedance value. 124 * 0x0 = Powered off 125 * 0x1 = 2Kohm 126 * 0x2 = 4Kohm 127 * 0x3 = 8Kohm 128 */ 129 static int mic_bias_event(struct snd_soc_dapm_widget *w, 130 struct snd_kcontrol *kcontrol, int event) 131 { 132 switch (event) { 133 case SND_SOC_DAPM_POST_PMU: 134 /* change mic bias resistor to 4Kohm */ 135 snd_soc_update_bits(w->codec, SGTL5000_CHIP_MIC_CTRL, 136 SGTL5000_BIAS_R_MASK, 137 SGTL5000_BIAS_R_4k << SGTL5000_BIAS_R_SHIFT); 138 break; 139 140 case SND_SOC_DAPM_PRE_PMD: 141 snd_soc_update_bits(w->codec, SGTL5000_CHIP_MIC_CTRL, 142 SGTL5000_BIAS_R_MASK, 0); 143 break; 144 } 145 return 0; 146 } 147 148 /* 149 * As manual described, ADC/DAC only works when VAG powerup, 150 * So enabled VAG before ADC/DAC up. 151 * In power down case, we need wait 400ms when vag fully ramped down. 152 */ 153 static int power_vag_event(struct snd_soc_dapm_widget *w, 154 struct snd_kcontrol *kcontrol, int event) 155 { 156 const u32 mask = SGTL5000_DAC_POWERUP | SGTL5000_ADC_POWERUP; 157 158 switch (event) { 159 case SND_SOC_DAPM_POST_PMU: 160 snd_soc_update_bits(w->codec, SGTL5000_CHIP_ANA_POWER, 161 SGTL5000_VAG_POWERUP, SGTL5000_VAG_POWERUP); 162 break; 163 164 case SND_SOC_DAPM_PRE_PMD: 165 /* 166 * Don't clear VAG_POWERUP, when both DAC and ADC are 167 * operational to prevent inadvertently starving the 168 * other one of them. 169 */ 170 if ((snd_soc_read(w->codec, SGTL5000_CHIP_ANA_POWER) & 171 mask) != mask) { 172 snd_soc_update_bits(w->codec, SGTL5000_CHIP_ANA_POWER, 173 SGTL5000_VAG_POWERUP, 0); 174 msleep(400); 175 } 176 break; 177 default: 178 break; 179 } 180 181 return 0; 182 } 183 184 /* input sources for ADC */ 185 static const char *adc_mux_text[] = { 186 "MIC_IN", "LINE_IN" 187 }; 188 189 static const struct soc_enum adc_enum = 190 SOC_ENUM_SINGLE(SGTL5000_CHIP_ANA_CTRL, 2, 2, adc_mux_text); 191 192 static const struct snd_kcontrol_new adc_mux = 193 SOC_DAPM_ENUM("Capture Mux", adc_enum); 194 195 /* input sources for DAC */ 196 static const char *dac_mux_text[] = { 197 "DAC", "LINE_IN" 198 }; 199 200 static const struct soc_enum dac_enum = 201 SOC_ENUM_SINGLE(SGTL5000_CHIP_ANA_CTRL, 6, 2, dac_mux_text); 202 203 static const struct snd_kcontrol_new dac_mux = 204 SOC_DAPM_ENUM("Headphone Mux", dac_enum); 205 206 static const struct snd_soc_dapm_widget sgtl5000_dapm_widgets[] = { 207 SND_SOC_DAPM_INPUT("LINE_IN"), 208 SND_SOC_DAPM_INPUT("MIC_IN"), 209 210 SND_SOC_DAPM_OUTPUT("HP_OUT"), 211 SND_SOC_DAPM_OUTPUT("LINE_OUT"), 212 213 SND_SOC_DAPM_SUPPLY("Mic Bias", SGTL5000_CHIP_MIC_CTRL, 8, 0, 214 mic_bias_event, 215 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 216 217 SND_SOC_DAPM_PGA("HP", SGTL5000_CHIP_ANA_POWER, 4, 0, NULL, 0), 218 SND_SOC_DAPM_PGA("LO", SGTL5000_CHIP_ANA_POWER, 0, 0, NULL, 0), 219 220 SND_SOC_DAPM_MUX("Capture Mux", SND_SOC_NOPM, 0, 0, &adc_mux), 221 SND_SOC_DAPM_MUX("Headphone Mux", SND_SOC_NOPM, 0, 0, &dac_mux), 222 223 /* aif for i2s input */ 224 SND_SOC_DAPM_AIF_IN("AIFIN", "Playback", 225 0, SGTL5000_CHIP_DIG_POWER, 226 0, 0), 227 228 /* aif for i2s output */ 229 SND_SOC_DAPM_AIF_OUT("AIFOUT", "Capture", 230 0, SGTL5000_CHIP_DIG_POWER, 231 1, 0), 232 233 SND_SOC_DAPM_ADC("ADC", "Capture", SGTL5000_CHIP_ANA_POWER, 1, 0), 234 SND_SOC_DAPM_DAC("DAC", "Playback", SGTL5000_CHIP_ANA_POWER, 3, 0), 235 236 SND_SOC_DAPM_PRE("VAG_POWER_PRE", power_vag_event), 237 SND_SOC_DAPM_POST("VAG_POWER_POST", power_vag_event), 238 }; 239 240 /* routes for sgtl5000 */ 241 static const struct snd_soc_dapm_route sgtl5000_dapm_routes[] = { 242 {"Capture Mux", "LINE_IN", "LINE_IN"}, /* line_in --> adc_mux */ 243 {"Capture Mux", "MIC_IN", "MIC_IN"}, /* mic_in --> adc_mux */ 244 245 {"ADC", NULL, "Capture Mux"}, /* adc_mux --> adc */ 246 {"AIFOUT", NULL, "ADC"}, /* adc --> i2s_out */ 247 248 {"DAC", NULL, "AIFIN"}, /* i2s-->dac,skip audio mux */ 249 {"Headphone Mux", "DAC", "DAC"}, /* dac --> hp_mux */ 250 {"LO", NULL, "DAC"}, /* dac --> line_out */ 251 252 {"Headphone Mux", "LINE_IN", "LINE_IN"},/* line_in --> hp_mux */ 253 {"HP", NULL, "Headphone Mux"}, /* hp_mux --> hp */ 254 255 {"LINE_OUT", NULL, "LO"}, 256 {"HP_OUT", NULL, "HP"}, 257 }; 258 259 /* custom function to fetch info of PCM playback volume */ 260 static int dac_info_volsw(struct snd_kcontrol *kcontrol, 261 struct snd_ctl_elem_info *uinfo) 262 { 263 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 264 uinfo->count = 2; 265 uinfo->value.integer.min = 0; 266 uinfo->value.integer.max = 0xfc - 0x3c; 267 return 0; 268 } 269 270 /* 271 * custom function to get of PCM playback volume 272 * 273 * dac volume register 274 * 15-------------8-7--------------0 275 * | R channel vol | L channel vol | 276 * ------------------------------- 277 * 278 * PCM volume with 0.5017 dB steps from 0 to -90 dB 279 * 280 * register values map to dB 281 * 0x3B and less = Reserved 282 * 0x3C = 0 dB 283 * 0x3D = -0.5 dB 284 * 0xF0 = -90 dB 285 * 0xFC and greater = Muted 286 * 287 * register value map to userspace value 288 * 289 * register value 0x3c(0dB) 0xf0(-90dB)0xfc 290 * ------------------------------ 291 * userspace value 0xc0 0 292 */ 293 static int dac_get_volsw(struct snd_kcontrol *kcontrol, 294 struct snd_ctl_elem_value *ucontrol) 295 { 296 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 297 int reg; 298 int l; 299 int r; 300 301 reg = snd_soc_read(codec, SGTL5000_CHIP_DAC_VOL); 302 303 /* get left channel volume */ 304 l = (reg & SGTL5000_DAC_VOL_LEFT_MASK) >> SGTL5000_DAC_VOL_LEFT_SHIFT; 305 306 /* get right channel volume */ 307 r = (reg & SGTL5000_DAC_VOL_RIGHT_MASK) >> SGTL5000_DAC_VOL_RIGHT_SHIFT; 308 309 /* make sure value fall in (0x3c,0xfc) */ 310 l = clamp(l, 0x3c, 0xfc); 311 r = clamp(r, 0x3c, 0xfc); 312 313 /* invert it and map to userspace value */ 314 l = 0xfc - l; 315 r = 0xfc - r; 316 317 ucontrol->value.integer.value[0] = l; 318 ucontrol->value.integer.value[1] = r; 319 320 return 0; 321 } 322 323 /* 324 * custom function to put of PCM playback volume 325 * 326 * dac volume register 327 * 15-------------8-7--------------0 328 * | R channel vol | L channel vol | 329 * ------------------------------- 330 * 331 * PCM volume with 0.5017 dB steps from 0 to -90 dB 332 * 333 * register values map to dB 334 * 0x3B and less = Reserved 335 * 0x3C = 0 dB 336 * 0x3D = -0.5 dB 337 * 0xF0 = -90 dB 338 * 0xFC and greater = Muted 339 * 340 * userspace value map to register value 341 * 342 * userspace value 0xc0 0 343 * ------------------------------ 344 * register value 0x3c(0dB) 0xf0(-90dB)0xfc 345 */ 346 static int dac_put_volsw(struct snd_kcontrol *kcontrol, 347 struct snd_ctl_elem_value *ucontrol) 348 { 349 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 350 int reg; 351 int l; 352 int r; 353 354 l = ucontrol->value.integer.value[0]; 355 r = ucontrol->value.integer.value[1]; 356 357 /* make sure userspace volume fall in (0, 0xfc-0x3c) */ 358 l = clamp(l, 0, 0xfc - 0x3c); 359 r = clamp(r, 0, 0xfc - 0x3c); 360 361 /* invert it, get the value can be set to register */ 362 l = 0xfc - l; 363 r = 0xfc - r; 364 365 /* shift to get the register value */ 366 reg = l << SGTL5000_DAC_VOL_LEFT_SHIFT | 367 r << SGTL5000_DAC_VOL_RIGHT_SHIFT; 368 369 snd_soc_write(codec, SGTL5000_CHIP_DAC_VOL, reg); 370 371 return 0; 372 } 373 374 static const DECLARE_TLV_DB_SCALE(capture_6db_attenuate, -600, 600, 0); 375 376 /* tlv for mic gain, 0db 20db 30db 40db */ 377 static const unsigned int mic_gain_tlv[] = { 378 TLV_DB_RANGE_HEAD(2), 379 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0), 380 1, 3, TLV_DB_SCALE_ITEM(2000, 1000, 0), 381 }; 382 383 /* tlv for hp volume, -51.5db to 12.0db, step .5db */ 384 static const DECLARE_TLV_DB_SCALE(headphone_volume, -5150, 50, 0); 385 386 static const struct snd_kcontrol_new sgtl5000_snd_controls[] = { 387 /* SOC_DOUBLE_S8_TLV with invert */ 388 { 389 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 390 .name = "PCM Playback Volume", 391 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ | 392 SNDRV_CTL_ELEM_ACCESS_READWRITE, 393 .info = dac_info_volsw, 394 .get = dac_get_volsw, 395 .put = dac_put_volsw, 396 }, 397 398 SOC_DOUBLE("Capture Volume", SGTL5000_CHIP_ANA_ADC_CTRL, 0, 4, 0xf, 0), 399 SOC_SINGLE_TLV("Capture Attenuate Switch (-6dB)", 400 SGTL5000_CHIP_ANA_ADC_CTRL, 401 8, 1, 0, capture_6db_attenuate), 402 SOC_SINGLE("Capture ZC Switch", SGTL5000_CHIP_ANA_CTRL, 1, 1, 0), 403 404 SOC_DOUBLE_TLV("Headphone Playback Volume", 405 SGTL5000_CHIP_ANA_HP_CTRL, 406 0, 8, 407 0x7f, 1, 408 headphone_volume), 409 SOC_SINGLE("Headphone Playback ZC Switch", SGTL5000_CHIP_ANA_CTRL, 410 5, 1, 0), 411 412 SOC_SINGLE_TLV("Mic Volume", SGTL5000_CHIP_MIC_CTRL, 413 0, 3, 0, mic_gain_tlv), 414 }; 415 416 /* mute the codec used by alsa core */ 417 static int sgtl5000_digital_mute(struct snd_soc_dai *codec_dai, int mute) 418 { 419 struct snd_soc_codec *codec = codec_dai->codec; 420 u16 adcdac_ctrl = SGTL5000_DAC_MUTE_LEFT | SGTL5000_DAC_MUTE_RIGHT; 421 422 snd_soc_update_bits(codec, SGTL5000_CHIP_ADCDAC_CTRL, 423 adcdac_ctrl, mute ? adcdac_ctrl : 0); 424 425 return 0; 426 } 427 428 /* set codec format */ 429 static int sgtl5000_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt) 430 { 431 struct snd_soc_codec *codec = codec_dai->codec; 432 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); 433 u16 i2sctl = 0; 434 435 sgtl5000->master = 0; 436 /* 437 * i2s clock and frame master setting. 438 * ONLY support: 439 * - clock and frame slave, 440 * - clock and frame master 441 */ 442 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 443 case SND_SOC_DAIFMT_CBS_CFS: 444 break; 445 case SND_SOC_DAIFMT_CBM_CFM: 446 i2sctl |= SGTL5000_I2S_MASTER; 447 sgtl5000->master = 1; 448 break; 449 default: 450 return -EINVAL; 451 } 452 453 /* setting i2s data format */ 454 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 455 case SND_SOC_DAIFMT_DSP_A: 456 i2sctl |= SGTL5000_I2S_MODE_PCM; 457 break; 458 case SND_SOC_DAIFMT_DSP_B: 459 i2sctl |= SGTL5000_I2S_MODE_PCM; 460 i2sctl |= SGTL5000_I2S_LRALIGN; 461 break; 462 case SND_SOC_DAIFMT_I2S: 463 i2sctl |= SGTL5000_I2S_MODE_I2S_LJ; 464 break; 465 case SND_SOC_DAIFMT_RIGHT_J: 466 i2sctl |= SGTL5000_I2S_MODE_RJ; 467 i2sctl |= SGTL5000_I2S_LRPOL; 468 break; 469 case SND_SOC_DAIFMT_LEFT_J: 470 i2sctl |= SGTL5000_I2S_MODE_I2S_LJ; 471 i2sctl |= SGTL5000_I2S_LRALIGN; 472 break; 473 default: 474 return -EINVAL; 475 } 476 477 sgtl5000->fmt = fmt & SND_SOC_DAIFMT_FORMAT_MASK; 478 479 /* Clock inversion */ 480 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 481 case SND_SOC_DAIFMT_NB_NF: 482 break; 483 case SND_SOC_DAIFMT_IB_NF: 484 i2sctl |= SGTL5000_I2S_SCLK_INV; 485 break; 486 default: 487 return -EINVAL; 488 } 489 490 snd_soc_write(codec, SGTL5000_CHIP_I2S_CTRL, i2sctl); 491 492 return 0; 493 } 494 495 /* set codec sysclk */ 496 static int sgtl5000_set_dai_sysclk(struct snd_soc_dai *codec_dai, 497 int clk_id, unsigned int freq, int dir) 498 { 499 struct snd_soc_codec *codec = codec_dai->codec; 500 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); 501 502 switch (clk_id) { 503 case SGTL5000_SYSCLK: 504 sgtl5000->sysclk = freq; 505 break; 506 default: 507 return -EINVAL; 508 } 509 510 return 0; 511 } 512 513 /* 514 * set clock according to i2s frame clock, 515 * sgtl5000 provide 2 clock sources. 516 * 1. sys_mclk. sample freq can only configure to 517 * 1/256, 1/384, 1/512 of sys_mclk. 518 * 2. pll. can derive any audio clocks. 519 * 520 * clock setting rules: 521 * 1. in slave mode, only sys_mclk can use. 522 * 2. as constraint by sys_mclk, sample freq should 523 * set to 32k, 44.1k and above. 524 * 3. using sys_mclk prefer to pll to save power. 525 */ 526 static int sgtl5000_set_clock(struct snd_soc_codec *codec, int frame_rate) 527 { 528 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); 529 int clk_ctl = 0; 530 int sys_fs; /* sample freq */ 531 532 /* 533 * sample freq should be divided by frame clock, 534 * if frame clock lower than 44.1khz, sample feq should set to 535 * 32khz or 44.1khz. 536 */ 537 switch (frame_rate) { 538 case 8000: 539 case 16000: 540 sys_fs = 32000; 541 break; 542 case 11025: 543 case 22050: 544 sys_fs = 44100; 545 break; 546 default: 547 sys_fs = frame_rate; 548 break; 549 } 550 551 /* set divided factor of frame clock */ 552 switch (sys_fs / frame_rate) { 553 case 4: 554 clk_ctl |= SGTL5000_RATE_MODE_DIV_4 << SGTL5000_RATE_MODE_SHIFT; 555 break; 556 case 2: 557 clk_ctl |= SGTL5000_RATE_MODE_DIV_2 << SGTL5000_RATE_MODE_SHIFT; 558 break; 559 case 1: 560 clk_ctl |= SGTL5000_RATE_MODE_DIV_1 << SGTL5000_RATE_MODE_SHIFT; 561 break; 562 default: 563 return -EINVAL; 564 } 565 566 /* set the sys_fs according to frame rate */ 567 switch (sys_fs) { 568 case 32000: 569 clk_ctl |= SGTL5000_SYS_FS_32k << SGTL5000_SYS_FS_SHIFT; 570 break; 571 case 44100: 572 clk_ctl |= SGTL5000_SYS_FS_44_1k << SGTL5000_SYS_FS_SHIFT; 573 break; 574 case 48000: 575 clk_ctl |= SGTL5000_SYS_FS_48k << SGTL5000_SYS_FS_SHIFT; 576 break; 577 case 96000: 578 clk_ctl |= SGTL5000_SYS_FS_96k << SGTL5000_SYS_FS_SHIFT; 579 break; 580 default: 581 dev_err(codec->dev, "frame rate %d not supported\n", 582 frame_rate); 583 return -EINVAL; 584 } 585 586 /* 587 * calculate the divider of mclk/sample_freq, 588 * factor of freq =96k can only be 256, since mclk in range (12m,27m) 589 */ 590 switch (sgtl5000->sysclk / sys_fs) { 591 case 256: 592 clk_ctl |= SGTL5000_MCLK_FREQ_256FS << 593 SGTL5000_MCLK_FREQ_SHIFT; 594 break; 595 case 384: 596 clk_ctl |= SGTL5000_MCLK_FREQ_384FS << 597 SGTL5000_MCLK_FREQ_SHIFT; 598 break; 599 case 512: 600 clk_ctl |= SGTL5000_MCLK_FREQ_512FS << 601 SGTL5000_MCLK_FREQ_SHIFT; 602 break; 603 default: 604 /* if mclk not satisify the divider, use pll */ 605 if (sgtl5000->master) { 606 clk_ctl |= SGTL5000_MCLK_FREQ_PLL << 607 SGTL5000_MCLK_FREQ_SHIFT; 608 } else { 609 dev_err(codec->dev, 610 "PLL not supported in slave mode\n"); 611 return -EINVAL; 612 } 613 } 614 615 /* if using pll, please check manual 6.4.2 for detail */ 616 if ((clk_ctl & SGTL5000_MCLK_FREQ_MASK) == SGTL5000_MCLK_FREQ_PLL) { 617 u64 out, t; 618 int div2; 619 int pll_ctl; 620 unsigned int in, int_div, frac_div; 621 622 if (sgtl5000->sysclk > 17000000) { 623 div2 = 1; 624 in = sgtl5000->sysclk / 2; 625 } else { 626 div2 = 0; 627 in = sgtl5000->sysclk; 628 } 629 if (sys_fs == 44100) 630 out = 180633600; 631 else 632 out = 196608000; 633 t = do_div(out, in); 634 int_div = out; 635 t *= 2048; 636 do_div(t, in); 637 frac_div = t; 638 pll_ctl = int_div << SGTL5000_PLL_INT_DIV_SHIFT | 639 frac_div << SGTL5000_PLL_FRAC_DIV_SHIFT; 640 641 snd_soc_write(codec, SGTL5000_CHIP_PLL_CTRL, pll_ctl); 642 if (div2) 643 snd_soc_update_bits(codec, 644 SGTL5000_CHIP_CLK_TOP_CTRL, 645 SGTL5000_INPUT_FREQ_DIV2, 646 SGTL5000_INPUT_FREQ_DIV2); 647 else 648 snd_soc_update_bits(codec, 649 SGTL5000_CHIP_CLK_TOP_CTRL, 650 SGTL5000_INPUT_FREQ_DIV2, 651 0); 652 653 /* power up pll */ 654 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER, 655 SGTL5000_PLL_POWERUP | SGTL5000_VCOAMP_POWERUP, 656 SGTL5000_PLL_POWERUP | SGTL5000_VCOAMP_POWERUP); 657 } else { 658 /* power down pll */ 659 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER, 660 SGTL5000_PLL_POWERUP | SGTL5000_VCOAMP_POWERUP, 661 0); 662 } 663 664 /* if using pll, clk_ctrl must be set after pll power up */ 665 snd_soc_write(codec, SGTL5000_CHIP_CLK_CTRL, clk_ctl); 666 667 return 0; 668 } 669 670 /* 671 * Set PCM DAI bit size and sample rate. 672 * input: params_rate, params_fmt 673 */ 674 static int sgtl5000_pcm_hw_params(struct snd_pcm_substream *substream, 675 struct snd_pcm_hw_params *params, 676 struct snd_soc_dai *dai) 677 { 678 struct snd_soc_codec *codec = dai->codec; 679 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); 680 int channels = params_channels(params); 681 int i2s_ctl = 0; 682 int stereo; 683 int ret; 684 685 /* sysclk should already set */ 686 if (!sgtl5000->sysclk) { 687 dev_err(codec->dev, "%s: set sysclk first!\n", __func__); 688 return -EFAULT; 689 } 690 691 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 692 stereo = SGTL5000_DAC_STEREO; 693 else 694 stereo = SGTL5000_ADC_STEREO; 695 696 /* set mono to save power */ 697 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER, stereo, 698 channels == 1 ? 0 : stereo); 699 700 /* set codec clock base on lrclk */ 701 ret = sgtl5000_set_clock(codec, params_rate(params)); 702 if (ret) 703 return ret; 704 705 /* set i2s data format */ 706 switch (params_format(params)) { 707 case SNDRV_PCM_FORMAT_S16_LE: 708 if (sgtl5000->fmt == SND_SOC_DAIFMT_RIGHT_J) 709 return -EINVAL; 710 i2s_ctl |= SGTL5000_I2S_DLEN_16 << SGTL5000_I2S_DLEN_SHIFT; 711 i2s_ctl |= SGTL5000_I2S_SCLKFREQ_32FS << 712 SGTL5000_I2S_SCLKFREQ_SHIFT; 713 break; 714 case SNDRV_PCM_FORMAT_S20_3LE: 715 i2s_ctl |= SGTL5000_I2S_DLEN_20 << SGTL5000_I2S_DLEN_SHIFT; 716 i2s_ctl |= SGTL5000_I2S_SCLKFREQ_64FS << 717 SGTL5000_I2S_SCLKFREQ_SHIFT; 718 break; 719 case SNDRV_PCM_FORMAT_S24_LE: 720 i2s_ctl |= SGTL5000_I2S_DLEN_24 << SGTL5000_I2S_DLEN_SHIFT; 721 i2s_ctl |= SGTL5000_I2S_SCLKFREQ_64FS << 722 SGTL5000_I2S_SCLKFREQ_SHIFT; 723 break; 724 case SNDRV_PCM_FORMAT_S32_LE: 725 if (sgtl5000->fmt == SND_SOC_DAIFMT_RIGHT_J) 726 return -EINVAL; 727 i2s_ctl |= SGTL5000_I2S_DLEN_32 << SGTL5000_I2S_DLEN_SHIFT; 728 i2s_ctl |= SGTL5000_I2S_SCLKFREQ_64FS << 729 SGTL5000_I2S_SCLKFREQ_SHIFT; 730 break; 731 default: 732 return -EINVAL; 733 } 734 735 snd_soc_update_bits(codec, SGTL5000_CHIP_I2S_CTRL, 736 SGTL5000_I2S_DLEN_MASK | SGTL5000_I2S_SCLKFREQ_MASK, 737 i2s_ctl); 738 739 return 0; 740 } 741 742 #ifdef CONFIG_REGULATOR 743 static int ldo_regulator_is_enabled(struct regulator_dev *dev) 744 { 745 struct ldo_regulator *ldo = rdev_get_drvdata(dev); 746 747 return ldo->enabled; 748 } 749 750 static int ldo_regulator_enable(struct regulator_dev *dev) 751 { 752 struct ldo_regulator *ldo = rdev_get_drvdata(dev); 753 struct snd_soc_codec *codec = (struct snd_soc_codec *)ldo->codec_data; 754 int reg; 755 756 if (ldo_regulator_is_enabled(dev)) 757 return 0; 758 759 /* set regulator value firstly */ 760 reg = (1600 - ldo->voltage / 1000) / 50; 761 reg = clamp(reg, 0x0, 0xf); 762 763 /* amend the voltage value, unit: uV */ 764 ldo->voltage = (1600 - reg * 50) * 1000; 765 766 /* set voltage to register */ 767 snd_soc_update_bits(codec, SGTL5000_CHIP_LINREG_CTRL, 768 SGTL5000_LINREG_VDDD_MASK, reg); 769 770 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER, 771 SGTL5000_LINEREG_D_POWERUP, 772 SGTL5000_LINEREG_D_POWERUP); 773 774 /* when internal ldo enabled, simple digital power can be disabled */ 775 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER, 776 SGTL5000_LINREG_SIMPLE_POWERUP, 777 0); 778 779 ldo->enabled = 1; 780 return 0; 781 } 782 783 static int ldo_regulator_disable(struct regulator_dev *dev) 784 { 785 struct ldo_regulator *ldo = rdev_get_drvdata(dev); 786 struct snd_soc_codec *codec = (struct snd_soc_codec *)ldo->codec_data; 787 788 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER, 789 SGTL5000_LINEREG_D_POWERUP, 790 0); 791 792 /* clear voltage info */ 793 snd_soc_update_bits(codec, SGTL5000_CHIP_LINREG_CTRL, 794 SGTL5000_LINREG_VDDD_MASK, 0); 795 796 ldo->enabled = 0; 797 798 return 0; 799 } 800 801 static int ldo_regulator_get_voltage(struct regulator_dev *dev) 802 { 803 struct ldo_regulator *ldo = rdev_get_drvdata(dev); 804 805 return ldo->voltage; 806 } 807 808 static struct regulator_ops ldo_regulator_ops = { 809 .is_enabled = ldo_regulator_is_enabled, 810 .enable = ldo_regulator_enable, 811 .disable = ldo_regulator_disable, 812 .get_voltage = ldo_regulator_get_voltage, 813 }; 814 815 static int ldo_regulator_register(struct snd_soc_codec *codec, 816 struct regulator_init_data *init_data, 817 int voltage) 818 { 819 struct ldo_regulator *ldo; 820 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); 821 struct regulator_config config = { }; 822 823 ldo = kzalloc(sizeof(struct ldo_regulator), GFP_KERNEL); 824 825 if (!ldo) { 826 dev_err(codec->dev, "failed to allocate ldo_regulator\n"); 827 return -ENOMEM; 828 } 829 830 ldo->desc.name = kstrdup(dev_name(codec->dev), GFP_KERNEL); 831 if (!ldo->desc.name) { 832 kfree(ldo); 833 dev_err(codec->dev, "failed to allocate decs name memory\n"); 834 return -ENOMEM; 835 } 836 837 ldo->desc.type = REGULATOR_VOLTAGE; 838 ldo->desc.owner = THIS_MODULE; 839 ldo->desc.ops = &ldo_regulator_ops; 840 ldo->desc.n_voltages = 1; 841 842 ldo->codec_data = codec; 843 ldo->voltage = voltage; 844 845 config.dev = codec->dev; 846 config.driver_data = ldo; 847 config.init_data = init_data; 848 849 ldo->dev = regulator_register(&ldo->desc, &config); 850 if (IS_ERR(ldo->dev)) { 851 int ret = PTR_ERR(ldo->dev); 852 853 dev_err(codec->dev, "failed to register regulator\n"); 854 kfree(ldo->desc.name); 855 kfree(ldo); 856 857 return ret; 858 } 859 sgtl5000->ldo = ldo; 860 861 return 0; 862 } 863 864 static int ldo_regulator_remove(struct snd_soc_codec *codec) 865 { 866 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); 867 struct ldo_regulator *ldo = sgtl5000->ldo; 868 869 if (!ldo) 870 return 0; 871 872 regulator_unregister(ldo->dev); 873 kfree(ldo->desc.name); 874 kfree(ldo); 875 876 return 0; 877 } 878 #else 879 static int ldo_regulator_register(struct snd_soc_codec *codec, 880 struct regulator_init_data *init_data, 881 int voltage) 882 { 883 dev_err(codec->dev, "this setup needs regulator support in the kernel\n"); 884 return -EINVAL; 885 } 886 887 static int ldo_regulator_remove(struct snd_soc_codec *codec) 888 { 889 return 0; 890 } 891 #endif 892 893 /* 894 * set dac bias 895 * common state changes: 896 * startup: 897 * off --> standby --> prepare --> on 898 * standby --> prepare --> on 899 * 900 * stop: 901 * on --> prepare --> standby 902 */ 903 static int sgtl5000_set_bias_level(struct snd_soc_codec *codec, 904 enum snd_soc_bias_level level) 905 { 906 int ret; 907 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); 908 909 switch (level) { 910 case SND_SOC_BIAS_ON: 911 case SND_SOC_BIAS_PREPARE: 912 break; 913 case SND_SOC_BIAS_STANDBY: 914 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) { 915 ret = regulator_bulk_enable( 916 ARRAY_SIZE(sgtl5000->supplies), 917 sgtl5000->supplies); 918 if (ret) 919 return ret; 920 udelay(10); 921 922 regcache_cache_only(sgtl5000->regmap, false); 923 924 ret = regcache_sync(sgtl5000->regmap); 925 if (ret != 0) { 926 dev_err(codec->dev, 927 "Failed to restore cache: %d\n", ret); 928 929 regcache_cache_only(sgtl5000->regmap, true); 930 regulator_bulk_disable(ARRAY_SIZE(sgtl5000->supplies), 931 sgtl5000->supplies); 932 933 return ret; 934 } 935 } 936 937 break; 938 case SND_SOC_BIAS_OFF: 939 regcache_cache_only(sgtl5000->regmap, true); 940 regulator_bulk_disable(ARRAY_SIZE(sgtl5000->supplies), 941 sgtl5000->supplies); 942 break; 943 } 944 945 codec->dapm.bias_level = level; 946 return 0; 947 } 948 949 #define SGTL5000_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ 950 SNDRV_PCM_FMTBIT_S20_3LE |\ 951 SNDRV_PCM_FMTBIT_S24_LE |\ 952 SNDRV_PCM_FMTBIT_S32_LE) 953 954 static const struct snd_soc_dai_ops sgtl5000_ops = { 955 .hw_params = sgtl5000_pcm_hw_params, 956 .digital_mute = sgtl5000_digital_mute, 957 .set_fmt = sgtl5000_set_dai_fmt, 958 .set_sysclk = sgtl5000_set_dai_sysclk, 959 }; 960 961 static struct snd_soc_dai_driver sgtl5000_dai = { 962 .name = "sgtl5000", 963 .playback = { 964 .stream_name = "Playback", 965 .channels_min = 1, 966 .channels_max = 2, 967 /* 968 * only support 8~48K + 96K, 969 * TODO modify hw_param to support more 970 */ 971 .rates = SNDRV_PCM_RATE_8000_48000 | SNDRV_PCM_RATE_96000, 972 .formats = SGTL5000_FORMATS, 973 }, 974 .capture = { 975 .stream_name = "Capture", 976 .channels_min = 1, 977 .channels_max = 2, 978 .rates = SNDRV_PCM_RATE_8000_48000 | SNDRV_PCM_RATE_96000, 979 .formats = SGTL5000_FORMATS, 980 }, 981 .ops = &sgtl5000_ops, 982 .symmetric_rates = 1, 983 }; 984 985 static bool sgtl5000_volatile(struct device *dev, unsigned int reg) 986 { 987 switch (reg) { 988 case SGTL5000_CHIP_ID: 989 case SGTL5000_CHIP_ADCDAC_CTRL: 990 case SGTL5000_CHIP_ANA_STATUS: 991 return true; 992 } 993 994 return false; 995 } 996 997 static bool sgtl5000_readable(struct device *dev, unsigned int reg) 998 { 999 switch (reg) { 1000 case SGTL5000_CHIP_ID: 1001 case SGTL5000_CHIP_DIG_POWER: 1002 case SGTL5000_CHIP_CLK_CTRL: 1003 case SGTL5000_CHIP_I2S_CTRL: 1004 case SGTL5000_CHIP_SSS_CTRL: 1005 case SGTL5000_CHIP_ADCDAC_CTRL: 1006 case SGTL5000_CHIP_DAC_VOL: 1007 case SGTL5000_CHIP_PAD_STRENGTH: 1008 case SGTL5000_CHIP_ANA_ADC_CTRL: 1009 case SGTL5000_CHIP_ANA_HP_CTRL: 1010 case SGTL5000_CHIP_ANA_CTRL: 1011 case SGTL5000_CHIP_LINREG_CTRL: 1012 case SGTL5000_CHIP_REF_CTRL: 1013 case SGTL5000_CHIP_MIC_CTRL: 1014 case SGTL5000_CHIP_LINE_OUT_CTRL: 1015 case SGTL5000_CHIP_LINE_OUT_VOL: 1016 case SGTL5000_CHIP_ANA_POWER: 1017 case SGTL5000_CHIP_PLL_CTRL: 1018 case SGTL5000_CHIP_CLK_TOP_CTRL: 1019 case SGTL5000_CHIP_ANA_STATUS: 1020 case SGTL5000_CHIP_SHORT_CTRL: 1021 case SGTL5000_CHIP_ANA_TEST2: 1022 case SGTL5000_DAP_CTRL: 1023 case SGTL5000_DAP_PEQ: 1024 case SGTL5000_DAP_BASS_ENHANCE: 1025 case SGTL5000_DAP_BASS_ENHANCE_CTRL: 1026 case SGTL5000_DAP_AUDIO_EQ: 1027 case SGTL5000_DAP_SURROUND: 1028 case SGTL5000_DAP_FLT_COEF_ACCESS: 1029 case SGTL5000_DAP_COEF_WR_B0_MSB: 1030 case SGTL5000_DAP_COEF_WR_B0_LSB: 1031 case SGTL5000_DAP_EQ_BASS_BAND0: 1032 case SGTL5000_DAP_EQ_BASS_BAND1: 1033 case SGTL5000_DAP_EQ_BASS_BAND2: 1034 case SGTL5000_DAP_EQ_BASS_BAND3: 1035 case SGTL5000_DAP_EQ_BASS_BAND4: 1036 case SGTL5000_DAP_MAIN_CHAN: 1037 case SGTL5000_DAP_MIX_CHAN: 1038 case SGTL5000_DAP_AVC_CTRL: 1039 case SGTL5000_DAP_AVC_THRESHOLD: 1040 case SGTL5000_DAP_AVC_ATTACK: 1041 case SGTL5000_DAP_AVC_DECAY: 1042 case SGTL5000_DAP_COEF_WR_B1_MSB: 1043 case SGTL5000_DAP_COEF_WR_B1_LSB: 1044 case SGTL5000_DAP_COEF_WR_B2_MSB: 1045 case SGTL5000_DAP_COEF_WR_B2_LSB: 1046 case SGTL5000_DAP_COEF_WR_A1_MSB: 1047 case SGTL5000_DAP_COEF_WR_A1_LSB: 1048 case SGTL5000_DAP_COEF_WR_A2_MSB: 1049 case SGTL5000_DAP_COEF_WR_A2_LSB: 1050 return true; 1051 1052 default: 1053 return false; 1054 } 1055 } 1056 1057 #ifdef CONFIG_SUSPEND 1058 static int sgtl5000_suspend(struct snd_soc_codec *codec) 1059 { 1060 sgtl5000_set_bias_level(codec, SND_SOC_BIAS_OFF); 1061 1062 return 0; 1063 } 1064 1065 /* 1066 * restore all sgtl5000 registers, 1067 * since a big hole between dap and regular registers, 1068 * we will restore them respectively. 1069 */ 1070 static int sgtl5000_restore_regs(struct snd_soc_codec *codec) 1071 { 1072 u16 *cache = codec->reg_cache; 1073 u16 reg; 1074 1075 /* restore regular registers */ 1076 for (reg = 0; reg <= SGTL5000_CHIP_SHORT_CTRL; reg += 2) { 1077 1078 /* These regs should restore in particular order */ 1079 if (reg == SGTL5000_CHIP_ANA_POWER || 1080 reg == SGTL5000_CHIP_CLK_CTRL || 1081 reg == SGTL5000_CHIP_LINREG_CTRL || 1082 reg == SGTL5000_CHIP_LINE_OUT_CTRL || 1083 reg == SGTL5000_CHIP_REF_CTRL) 1084 continue; 1085 1086 snd_soc_write(codec, reg, cache[reg]); 1087 } 1088 1089 /* restore dap registers */ 1090 for (reg = SGTL5000_DAP_REG_OFFSET; reg < SGTL5000_MAX_REG_OFFSET; reg += 2) 1091 snd_soc_write(codec, reg, cache[reg]); 1092 1093 /* 1094 * restore these regs according to the power setting sequence in 1095 * sgtl5000_set_power_regs() and clock setting sequence in 1096 * sgtl5000_set_clock(). 1097 * 1098 * The order of restore is: 1099 * 1. SGTL5000_CHIP_CLK_CTRL MCLK_FREQ bits (1:0) should be restore after 1100 * SGTL5000_CHIP_ANA_POWER PLL bits set 1101 * 2. SGTL5000_CHIP_LINREG_CTRL should be set before 1102 * SGTL5000_CHIP_ANA_POWER LINREG_D restored 1103 * 3. SGTL5000_CHIP_REF_CTRL controls Analog Ground Voltage, 1104 * prefer to resotre it after SGTL5000_CHIP_ANA_POWER restored 1105 */ 1106 snd_soc_write(codec, SGTL5000_CHIP_LINREG_CTRL, 1107 cache[SGTL5000_CHIP_LINREG_CTRL]); 1108 1109 snd_soc_write(codec, SGTL5000_CHIP_ANA_POWER, 1110 cache[SGTL5000_CHIP_ANA_POWER]); 1111 1112 snd_soc_write(codec, SGTL5000_CHIP_CLK_CTRL, 1113 cache[SGTL5000_CHIP_CLK_CTRL]); 1114 1115 snd_soc_write(codec, SGTL5000_CHIP_REF_CTRL, 1116 cache[SGTL5000_CHIP_REF_CTRL]); 1117 1118 snd_soc_write(codec, SGTL5000_CHIP_LINE_OUT_CTRL, 1119 cache[SGTL5000_CHIP_LINE_OUT_CTRL]); 1120 return 0; 1121 } 1122 1123 static int sgtl5000_resume(struct snd_soc_codec *codec) 1124 { 1125 /* Bring the codec back up to standby to enable regulators */ 1126 sgtl5000_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 1127 1128 /* Restore registers by cached in memory */ 1129 sgtl5000_restore_regs(codec); 1130 return 0; 1131 } 1132 #else 1133 #define sgtl5000_suspend NULL 1134 #define sgtl5000_resume NULL 1135 #endif /* CONFIG_SUSPEND */ 1136 1137 /* 1138 * sgtl5000 has 3 internal power supplies: 1139 * 1. VAG, normally set to vdda/2 1140 * 2. chargepump, set to different value 1141 * according to voltage of vdda and vddio 1142 * 3. line out VAG, normally set to vddio/2 1143 * 1144 * and should be set according to: 1145 * 1. vddd provided by external or not 1146 * 2. vdda and vddio voltage value. > 3.1v or not 1147 * 3. chip revision >=0x11 or not. If >=0x11, not use external vddd. 1148 */ 1149 static int sgtl5000_set_power_regs(struct snd_soc_codec *codec) 1150 { 1151 int vddd; 1152 int vdda; 1153 int vddio; 1154 u16 ana_pwr; 1155 u16 lreg_ctrl; 1156 int vag; 1157 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); 1158 1159 vdda = regulator_get_voltage(sgtl5000->supplies[VDDA].consumer); 1160 vddio = regulator_get_voltage(sgtl5000->supplies[VDDIO].consumer); 1161 vddd = regulator_get_voltage(sgtl5000->supplies[VDDD].consumer); 1162 1163 vdda = vdda / 1000; 1164 vddio = vddio / 1000; 1165 vddd = vddd / 1000; 1166 1167 if (vdda <= 0 || vddio <= 0 || vddd < 0) { 1168 dev_err(codec->dev, "regulator voltage not set correctly\n"); 1169 1170 return -EINVAL; 1171 } 1172 1173 /* according to datasheet, maximum voltage of supplies */ 1174 if (vdda > 3600 || vddio > 3600 || vddd > 1980) { 1175 dev_err(codec->dev, 1176 "exceed max voltage vdda %dmV vddio %dmV vddd %dmV\n", 1177 vdda, vddio, vddd); 1178 1179 return -EINVAL; 1180 } 1181 1182 /* reset value */ 1183 ana_pwr = snd_soc_read(codec, SGTL5000_CHIP_ANA_POWER); 1184 ana_pwr |= SGTL5000_DAC_STEREO | 1185 SGTL5000_ADC_STEREO | 1186 SGTL5000_REFTOP_POWERUP; 1187 lreg_ctrl = snd_soc_read(codec, SGTL5000_CHIP_LINREG_CTRL); 1188 1189 if (vddio < 3100 && vdda < 3100) { 1190 /* enable internal oscillator used for charge pump */ 1191 snd_soc_update_bits(codec, SGTL5000_CHIP_CLK_TOP_CTRL, 1192 SGTL5000_INT_OSC_EN, 1193 SGTL5000_INT_OSC_EN); 1194 /* Enable VDDC charge pump */ 1195 ana_pwr |= SGTL5000_VDDC_CHRGPMP_POWERUP; 1196 } else if (vddio >= 3100 && vdda >= 3100) { 1197 /* 1198 * if vddio and vddd > 3.1v, 1199 * charge pump should be clean before set ana_pwr 1200 */ 1201 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER, 1202 SGTL5000_VDDC_CHRGPMP_POWERUP, 0); 1203 1204 /* VDDC use VDDIO rail */ 1205 lreg_ctrl |= SGTL5000_VDDC_ASSN_OVRD; 1206 lreg_ctrl |= SGTL5000_VDDC_MAN_ASSN_VDDIO << 1207 SGTL5000_VDDC_MAN_ASSN_SHIFT; 1208 } 1209 1210 snd_soc_write(codec, SGTL5000_CHIP_LINREG_CTRL, lreg_ctrl); 1211 1212 snd_soc_write(codec, SGTL5000_CHIP_ANA_POWER, ana_pwr); 1213 1214 /* set voltage to register */ 1215 snd_soc_update_bits(codec, SGTL5000_CHIP_LINREG_CTRL, 1216 SGTL5000_LINREG_VDDD_MASK, 0x8); 1217 1218 /* 1219 * if vddd linear reg has been enabled, 1220 * simple digital supply should be clear to get 1221 * proper VDDD voltage. 1222 */ 1223 if (ana_pwr & SGTL5000_LINEREG_D_POWERUP) 1224 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER, 1225 SGTL5000_LINREG_SIMPLE_POWERUP, 1226 0); 1227 else 1228 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER, 1229 SGTL5000_LINREG_SIMPLE_POWERUP | 1230 SGTL5000_STARTUP_POWERUP, 1231 0); 1232 1233 /* 1234 * set ADC/DAC VAG to vdda / 2, 1235 * should stay in range (0.8v, 1.575v) 1236 */ 1237 vag = vdda / 2; 1238 if (vag <= SGTL5000_ANA_GND_BASE) 1239 vag = 0; 1240 else if (vag >= SGTL5000_ANA_GND_BASE + SGTL5000_ANA_GND_STP * 1241 (SGTL5000_ANA_GND_MASK >> SGTL5000_ANA_GND_SHIFT)) 1242 vag = SGTL5000_ANA_GND_MASK >> SGTL5000_ANA_GND_SHIFT; 1243 else 1244 vag = (vag - SGTL5000_ANA_GND_BASE) / SGTL5000_ANA_GND_STP; 1245 1246 snd_soc_update_bits(codec, SGTL5000_CHIP_REF_CTRL, 1247 SGTL5000_ANA_GND_MASK, vag << SGTL5000_ANA_GND_SHIFT); 1248 1249 /* set line out VAG to vddio / 2, in range (0.8v, 1.675v) */ 1250 vag = vddio / 2; 1251 if (vag <= SGTL5000_LINE_OUT_GND_BASE) 1252 vag = 0; 1253 else if (vag >= SGTL5000_LINE_OUT_GND_BASE + 1254 SGTL5000_LINE_OUT_GND_STP * SGTL5000_LINE_OUT_GND_MAX) 1255 vag = SGTL5000_LINE_OUT_GND_MAX; 1256 else 1257 vag = (vag - SGTL5000_LINE_OUT_GND_BASE) / 1258 SGTL5000_LINE_OUT_GND_STP; 1259 1260 snd_soc_update_bits(codec, SGTL5000_CHIP_LINE_OUT_CTRL, 1261 SGTL5000_LINE_OUT_CURRENT_MASK | 1262 SGTL5000_LINE_OUT_GND_MASK, 1263 vag << SGTL5000_LINE_OUT_GND_SHIFT | 1264 SGTL5000_LINE_OUT_CURRENT_360u << 1265 SGTL5000_LINE_OUT_CURRENT_SHIFT); 1266 1267 return 0; 1268 } 1269 1270 static int sgtl5000_replace_vddd_with_ldo(struct snd_soc_codec *codec) 1271 { 1272 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); 1273 int ret; 1274 1275 /* set internal ldo to 1.2v */ 1276 ret = ldo_regulator_register(codec, &ldo_init_data, LDO_VOLTAGE); 1277 if (ret) { 1278 dev_err(codec->dev, 1279 "Failed to register vddd internal supplies: %d\n", ret); 1280 return ret; 1281 } 1282 1283 sgtl5000->supplies[VDDD].supply = LDO_CONSUMER_NAME; 1284 1285 ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(sgtl5000->supplies), 1286 sgtl5000->supplies); 1287 1288 if (ret) { 1289 ldo_regulator_remove(codec); 1290 dev_err(codec->dev, "Failed to request supplies: %d\n", ret); 1291 return ret; 1292 } 1293 1294 dev_info(codec->dev, "Using internal LDO instead of VDDD\n"); 1295 return 0; 1296 } 1297 1298 static int sgtl5000_enable_regulators(struct snd_soc_codec *codec) 1299 { 1300 int reg; 1301 int ret; 1302 int rev; 1303 int i; 1304 int external_vddd = 0; 1305 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); 1306 1307 for (i = 0; i < ARRAY_SIZE(sgtl5000->supplies); i++) 1308 sgtl5000->supplies[i].supply = supply_names[i]; 1309 1310 ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(sgtl5000->supplies), 1311 sgtl5000->supplies); 1312 if (!ret) 1313 external_vddd = 1; 1314 else { 1315 ret = sgtl5000_replace_vddd_with_ldo(codec); 1316 if (ret) 1317 return ret; 1318 } 1319 1320 ret = regulator_bulk_enable(ARRAY_SIZE(sgtl5000->supplies), 1321 sgtl5000->supplies); 1322 if (ret) 1323 goto err_regulator_free; 1324 1325 /* wait for all power rails bring up */ 1326 udelay(10); 1327 1328 /* 1329 * workaround for revision 0x11 and later, 1330 * roll back to use internal LDO 1331 */ 1332 1333 ret = regmap_read(sgtl5000->regmap, SGTL5000_CHIP_ID, ®); 1334 if (ret) 1335 goto err_regulator_disable; 1336 1337 rev = (reg & SGTL5000_REVID_MASK) >> SGTL5000_REVID_SHIFT; 1338 1339 if (external_vddd && rev >= 0x11) { 1340 /* disable all regulator first */ 1341 regulator_bulk_disable(ARRAY_SIZE(sgtl5000->supplies), 1342 sgtl5000->supplies); 1343 /* free VDDD regulator */ 1344 regulator_bulk_free(ARRAY_SIZE(sgtl5000->supplies), 1345 sgtl5000->supplies); 1346 1347 ret = sgtl5000_replace_vddd_with_ldo(codec); 1348 if (ret) 1349 return ret; 1350 1351 ret = regulator_bulk_enable(ARRAY_SIZE(sgtl5000->supplies), 1352 sgtl5000->supplies); 1353 if (ret) 1354 goto err_regulator_free; 1355 1356 /* wait for all power rails bring up */ 1357 udelay(10); 1358 } 1359 1360 return 0; 1361 1362 err_regulator_disable: 1363 regulator_bulk_disable(ARRAY_SIZE(sgtl5000->supplies), 1364 sgtl5000->supplies); 1365 err_regulator_free: 1366 regulator_bulk_free(ARRAY_SIZE(sgtl5000->supplies), 1367 sgtl5000->supplies); 1368 if (external_vddd) 1369 ldo_regulator_remove(codec); 1370 return ret; 1371 1372 } 1373 1374 static int sgtl5000_probe(struct snd_soc_codec *codec) 1375 { 1376 int ret; 1377 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); 1378 1379 /* setup i2c data ops */ 1380 codec->control_data = sgtl5000->regmap; 1381 ret = snd_soc_codec_set_cache_io(codec, 16, 16, SND_SOC_REGMAP); 1382 if (ret < 0) { 1383 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret); 1384 return ret; 1385 } 1386 1387 ret = sgtl5000_enable_regulators(codec); 1388 if (ret) 1389 return ret; 1390 1391 /* power up sgtl5000 */ 1392 ret = sgtl5000_set_power_regs(codec); 1393 if (ret) 1394 goto err; 1395 1396 /* enable small pop, introduce 400ms delay in turning off */ 1397 snd_soc_update_bits(codec, SGTL5000_CHIP_REF_CTRL, 1398 SGTL5000_SMALL_POP, 1399 SGTL5000_SMALL_POP); 1400 1401 /* disable short cut detector */ 1402 snd_soc_write(codec, SGTL5000_CHIP_SHORT_CTRL, 0); 1403 1404 /* 1405 * set i2s as default input of sound switch 1406 * TODO: add sound switch to control and dapm widge. 1407 */ 1408 snd_soc_write(codec, SGTL5000_CHIP_SSS_CTRL, 1409 SGTL5000_DAC_SEL_I2S_IN << SGTL5000_DAC_SEL_SHIFT); 1410 snd_soc_write(codec, SGTL5000_CHIP_DIG_POWER, 1411 SGTL5000_ADC_EN | SGTL5000_DAC_EN); 1412 1413 /* enable dac volume ramp by default */ 1414 snd_soc_write(codec, SGTL5000_CHIP_ADCDAC_CTRL, 1415 SGTL5000_DAC_VOL_RAMP_EN | 1416 SGTL5000_DAC_MUTE_RIGHT | 1417 SGTL5000_DAC_MUTE_LEFT); 1418 1419 snd_soc_write(codec, SGTL5000_CHIP_PAD_STRENGTH, 0x015f); 1420 1421 snd_soc_write(codec, SGTL5000_CHIP_ANA_CTRL, 1422 SGTL5000_HP_ZCD_EN | 1423 SGTL5000_ADC_ZCD_EN); 1424 1425 snd_soc_write(codec, SGTL5000_CHIP_MIC_CTRL, 2); 1426 1427 /* 1428 * disable DAP 1429 * TODO: 1430 * Enable DAP in kcontrol and dapm. 1431 */ 1432 snd_soc_write(codec, SGTL5000_DAP_CTRL, 0); 1433 1434 /* leading to standby state */ 1435 ret = sgtl5000_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 1436 if (ret) 1437 goto err; 1438 1439 return 0; 1440 1441 err: 1442 regulator_bulk_disable(ARRAY_SIZE(sgtl5000->supplies), 1443 sgtl5000->supplies); 1444 regulator_bulk_free(ARRAY_SIZE(sgtl5000->supplies), 1445 sgtl5000->supplies); 1446 ldo_regulator_remove(codec); 1447 1448 return ret; 1449 } 1450 1451 static int sgtl5000_remove(struct snd_soc_codec *codec) 1452 { 1453 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); 1454 1455 sgtl5000_set_bias_level(codec, SND_SOC_BIAS_OFF); 1456 1457 regulator_bulk_disable(ARRAY_SIZE(sgtl5000->supplies), 1458 sgtl5000->supplies); 1459 regulator_bulk_free(ARRAY_SIZE(sgtl5000->supplies), 1460 sgtl5000->supplies); 1461 ldo_regulator_remove(codec); 1462 1463 return 0; 1464 } 1465 1466 static struct snd_soc_codec_driver sgtl5000_driver = { 1467 .probe = sgtl5000_probe, 1468 .remove = sgtl5000_remove, 1469 .suspend = sgtl5000_suspend, 1470 .resume = sgtl5000_resume, 1471 .set_bias_level = sgtl5000_set_bias_level, 1472 .controls = sgtl5000_snd_controls, 1473 .num_controls = ARRAY_SIZE(sgtl5000_snd_controls), 1474 .dapm_widgets = sgtl5000_dapm_widgets, 1475 .num_dapm_widgets = ARRAY_SIZE(sgtl5000_dapm_widgets), 1476 .dapm_routes = sgtl5000_dapm_routes, 1477 .num_dapm_routes = ARRAY_SIZE(sgtl5000_dapm_routes), 1478 }; 1479 1480 static const struct regmap_config sgtl5000_regmap = { 1481 .reg_bits = 16, 1482 .val_bits = 16, 1483 1484 .max_register = SGTL5000_MAX_REG_OFFSET, 1485 .volatile_reg = sgtl5000_volatile, 1486 .readable_reg = sgtl5000_readable, 1487 1488 .cache_type = REGCACHE_RBTREE, 1489 .reg_defaults = sgtl5000_reg_defaults, 1490 .num_reg_defaults = ARRAY_SIZE(sgtl5000_reg_defaults), 1491 }; 1492 1493 /* 1494 * Write all the default values from sgtl5000_reg_defaults[] array into the 1495 * sgtl5000 registers, to make sure we always start with the sane registers 1496 * values as stated in the datasheet. 1497 * 1498 * Since sgtl5000 does not have a reset line, nor a reset command in software, 1499 * we follow this approach to guarantee we always start from the default values 1500 * and avoid problems like, not being able to probe after an audio playback 1501 * followed by a system reset or a 'reboot' command in Linux 1502 */ 1503 static int sgtl5000_fill_defaults(struct sgtl5000_priv *sgtl5000) 1504 { 1505 int i, ret, val, index; 1506 1507 for (i = 0; i < ARRAY_SIZE(sgtl5000_reg_defaults); i++) { 1508 val = sgtl5000_reg_defaults[i].def; 1509 index = sgtl5000_reg_defaults[i].reg; 1510 ret = regmap_write(sgtl5000->regmap, index, val); 1511 if (ret) 1512 return ret; 1513 } 1514 1515 return 0; 1516 } 1517 1518 static int sgtl5000_i2c_probe(struct i2c_client *client, 1519 const struct i2c_device_id *id) 1520 { 1521 struct sgtl5000_priv *sgtl5000; 1522 int ret, reg, rev; 1523 1524 sgtl5000 = devm_kzalloc(&client->dev, sizeof(struct sgtl5000_priv), 1525 GFP_KERNEL); 1526 if (!sgtl5000) 1527 return -ENOMEM; 1528 1529 sgtl5000->regmap = devm_regmap_init_i2c(client, &sgtl5000_regmap); 1530 if (IS_ERR(sgtl5000->regmap)) { 1531 ret = PTR_ERR(sgtl5000->regmap); 1532 dev_err(&client->dev, "Failed to allocate regmap: %d\n", ret); 1533 return ret; 1534 } 1535 1536 sgtl5000->mclk = devm_clk_get(&client->dev, NULL); 1537 if (IS_ERR(sgtl5000->mclk)) { 1538 ret = PTR_ERR(sgtl5000->mclk); 1539 dev_err(&client->dev, "Failed to get mclock: %d\n", ret); 1540 /* Defer the probe to see if the clk will be provided later */ 1541 if (ret == -ENOENT) 1542 return -EPROBE_DEFER; 1543 return ret; 1544 } 1545 1546 ret = clk_prepare_enable(sgtl5000->mclk); 1547 if (ret) 1548 return ret; 1549 1550 /* read chip information */ 1551 ret = regmap_read(sgtl5000->regmap, SGTL5000_CHIP_ID, ®); 1552 if (ret) 1553 goto disable_clk; 1554 1555 if (((reg & SGTL5000_PARTID_MASK) >> SGTL5000_PARTID_SHIFT) != 1556 SGTL5000_PARTID_PART_ID) { 1557 dev_err(&client->dev, 1558 "Device with ID register %x is not a sgtl5000\n", reg); 1559 ret = -ENODEV; 1560 goto disable_clk; 1561 } 1562 1563 rev = (reg & SGTL5000_REVID_MASK) >> SGTL5000_REVID_SHIFT; 1564 dev_info(&client->dev, "sgtl5000 revision 0x%x\n", rev); 1565 1566 i2c_set_clientdata(client, sgtl5000); 1567 1568 /* Ensure sgtl5000 will start with sane register values */ 1569 ret = sgtl5000_fill_defaults(sgtl5000); 1570 if (ret) 1571 goto disable_clk; 1572 1573 ret = snd_soc_register_codec(&client->dev, 1574 &sgtl5000_driver, &sgtl5000_dai, 1); 1575 if (ret) 1576 goto disable_clk; 1577 1578 return 0; 1579 1580 disable_clk: 1581 clk_disable_unprepare(sgtl5000->mclk); 1582 return ret; 1583 } 1584 1585 static int sgtl5000_i2c_remove(struct i2c_client *client) 1586 { 1587 struct sgtl5000_priv *sgtl5000 = i2c_get_clientdata(client); 1588 1589 snd_soc_unregister_codec(&client->dev); 1590 clk_disable_unprepare(sgtl5000->mclk); 1591 return 0; 1592 } 1593 1594 static const struct i2c_device_id sgtl5000_id[] = { 1595 {"sgtl5000", 0}, 1596 {}, 1597 }; 1598 1599 MODULE_DEVICE_TABLE(i2c, sgtl5000_id); 1600 1601 static const struct of_device_id sgtl5000_dt_ids[] = { 1602 { .compatible = "fsl,sgtl5000", }, 1603 { /* sentinel */ } 1604 }; 1605 MODULE_DEVICE_TABLE(of, sgtl5000_dt_ids); 1606 1607 static struct i2c_driver sgtl5000_i2c_driver = { 1608 .driver = { 1609 .name = "sgtl5000", 1610 .owner = THIS_MODULE, 1611 .of_match_table = sgtl5000_dt_ids, 1612 }, 1613 .probe = sgtl5000_i2c_probe, 1614 .remove = sgtl5000_i2c_remove, 1615 .id_table = sgtl5000_id, 1616 }; 1617 1618 module_i2c_driver(sgtl5000_i2c_driver); 1619 1620 MODULE_DESCRIPTION("Freescale SGTL5000 ALSA SoC Codec Driver"); 1621 MODULE_AUTHOR("Zeng Zhaoming <zengzm.kernel@gmail.com>"); 1622 MODULE_LICENSE("GPL"); 1623