xref: /openbmc/linux/sound/soc/codecs/sgtl5000.c (revision d2999e1b)
1 /*
2  * sgtl5000.c  --  SGTL5000 ALSA SoC Audio driver
3  *
4  * Copyright 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License version 2 as
8  * published by the Free Software Foundation.
9  */
10 
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/init.h>
14 #include <linux/delay.h>
15 #include <linux/slab.h>
16 #include <linux/pm.h>
17 #include <linux/i2c.h>
18 #include <linux/clk.h>
19 #include <linux/regmap.h>
20 #include <linux/regulator/driver.h>
21 #include <linux/regulator/machine.h>
22 #include <linux/regulator/consumer.h>
23 #include <linux/of_device.h>
24 #include <sound/core.h>
25 #include <sound/tlv.h>
26 #include <sound/pcm.h>
27 #include <sound/pcm_params.h>
28 #include <sound/soc.h>
29 #include <sound/soc-dapm.h>
30 #include <sound/initval.h>
31 
32 #include "sgtl5000.h"
33 
34 #define SGTL5000_DAP_REG_OFFSET	0x0100
35 #define SGTL5000_MAX_REG_OFFSET	0x013A
36 
37 /* default value of sgtl5000 registers */
38 static const struct reg_default sgtl5000_reg_defaults[] = {
39 	{ SGTL5000_CHIP_DIG_POWER,		0x0000 },
40 	{ SGTL5000_CHIP_CLK_CTRL,		0x0008 },
41 	{ SGTL5000_CHIP_I2S_CTRL,		0x0010 },
42 	{ SGTL5000_CHIP_SSS_CTRL,		0x0010 },
43 	{ SGTL5000_CHIP_ADCDAC_CTRL,		0x020c },
44 	{ SGTL5000_CHIP_DAC_VOL,		0x3c3c },
45 	{ SGTL5000_CHIP_PAD_STRENGTH,		0x015f },
46 	{ SGTL5000_CHIP_ANA_ADC_CTRL,		0x0000 },
47 	{ SGTL5000_CHIP_ANA_HP_CTRL,		0x1818 },
48 	{ SGTL5000_CHIP_ANA_CTRL,		0x0111 },
49 	{ SGTL5000_CHIP_LINREG_CTRL,		0x0000 },
50 	{ SGTL5000_CHIP_REF_CTRL,		0x0000 },
51 	{ SGTL5000_CHIP_MIC_CTRL,		0x0000 },
52 	{ SGTL5000_CHIP_LINE_OUT_CTRL,		0x0000 },
53 	{ SGTL5000_CHIP_LINE_OUT_VOL,		0x0404 },
54 	{ SGTL5000_CHIP_ANA_POWER,		0x7060 },
55 	{ SGTL5000_CHIP_PLL_CTRL,		0x5000 },
56 	{ SGTL5000_CHIP_CLK_TOP_CTRL,		0x0000 },
57 	{ SGTL5000_CHIP_ANA_STATUS,		0x0000 },
58 	{ SGTL5000_CHIP_SHORT_CTRL,		0x0000 },
59 	{ SGTL5000_CHIP_ANA_TEST2,		0x0000 },
60 	{ SGTL5000_DAP_CTRL,			0x0000 },
61 	{ SGTL5000_DAP_PEQ,			0x0000 },
62 	{ SGTL5000_DAP_BASS_ENHANCE,		0x0040 },
63 	{ SGTL5000_DAP_BASS_ENHANCE_CTRL,	0x051f },
64 	{ SGTL5000_DAP_AUDIO_EQ,		0x0000 },
65 	{ SGTL5000_DAP_SURROUND,		0x0040 },
66 	{ SGTL5000_DAP_EQ_BASS_BAND0,		0x002f },
67 	{ SGTL5000_DAP_EQ_BASS_BAND1,		0x002f },
68 	{ SGTL5000_DAP_EQ_BASS_BAND2,		0x002f },
69 	{ SGTL5000_DAP_EQ_BASS_BAND3,		0x002f },
70 	{ SGTL5000_DAP_EQ_BASS_BAND4,		0x002f },
71 	{ SGTL5000_DAP_MAIN_CHAN,		0x8000 },
72 	{ SGTL5000_DAP_MIX_CHAN,		0x0000 },
73 	{ SGTL5000_DAP_AVC_CTRL,		0x0510 },
74 	{ SGTL5000_DAP_AVC_THRESHOLD,		0x1473 },
75 	{ SGTL5000_DAP_AVC_ATTACK,		0x0028 },
76 	{ SGTL5000_DAP_AVC_DECAY,		0x0050 },
77 };
78 
79 /* regulator supplies for sgtl5000, VDDD is an optional external supply */
80 enum sgtl5000_regulator_supplies {
81 	VDDA,
82 	VDDIO,
83 	VDDD,
84 	SGTL5000_SUPPLY_NUM
85 };
86 
87 /* vddd is optional supply */
88 static const char *supply_names[SGTL5000_SUPPLY_NUM] = {
89 	"VDDA",
90 	"VDDIO",
91 	"VDDD"
92 };
93 
94 #define LDO_CONSUMER_NAME	"VDDD_LDO"
95 #define LDO_VOLTAGE		1200000
96 
97 static struct regulator_consumer_supply ldo_consumer[] = {
98 	REGULATOR_SUPPLY(LDO_CONSUMER_NAME, NULL),
99 };
100 
101 static struct regulator_init_data ldo_init_data = {
102 	.constraints = {
103 		.min_uV                 = 1200000,
104 		.max_uV                 = 1200000,
105 		.valid_modes_mask       = REGULATOR_MODE_NORMAL,
106 		.valid_ops_mask         = REGULATOR_CHANGE_STATUS,
107 	},
108 	.num_consumer_supplies = 1,
109 	.consumer_supplies = &ldo_consumer[0],
110 };
111 
112 /*
113  * sgtl5000 internal ldo regulator,
114  * enabled when VDDD not provided
115  */
116 struct ldo_regulator {
117 	struct regulator_desc desc;
118 	struct regulator_dev *dev;
119 	int voltage;
120 	void *codec_data;
121 	bool enabled;
122 };
123 
124 /* sgtl5000 private structure in codec */
125 struct sgtl5000_priv {
126 	int sysclk;	/* sysclk rate */
127 	int master;	/* i2s master or not */
128 	int fmt;	/* i2s data format */
129 	struct regulator_bulk_data supplies[SGTL5000_SUPPLY_NUM];
130 	struct ldo_regulator *ldo;
131 	struct regmap *regmap;
132 	struct clk *mclk;
133 	int revision;
134 };
135 
136 /*
137  * mic_bias power on/off share the same register bits with
138  * output impedance of mic bias, when power on mic bias, we
139  * need reclaim it to impedance value.
140  * 0x0 = Powered off
141  * 0x1 = 2Kohm
142  * 0x2 = 4Kohm
143  * 0x3 = 8Kohm
144  */
145 static int mic_bias_event(struct snd_soc_dapm_widget *w,
146 	struct snd_kcontrol *kcontrol, int event)
147 {
148 	switch (event) {
149 	case SND_SOC_DAPM_POST_PMU:
150 		/* change mic bias resistor to 4Kohm */
151 		snd_soc_update_bits(w->codec, SGTL5000_CHIP_MIC_CTRL,
152 				SGTL5000_BIAS_R_MASK,
153 				SGTL5000_BIAS_R_4k << SGTL5000_BIAS_R_SHIFT);
154 		break;
155 
156 	case SND_SOC_DAPM_PRE_PMD:
157 		snd_soc_update_bits(w->codec, SGTL5000_CHIP_MIC_CTRL,
158 				SGTL5000_BIAS_R_MASK, 0);
159 		break;
160 	}
161 	return 0;
162 }
163 
164 /*
165  * As manual described, ADC/DAC only works when VAG powerup,
166  * So enabled VAG before ADC/DAC up.
167  * In power down case, we need wait 400ms when vag fully ramped down.
168  */
169 static int power_vag_event(struct snd_soc_dapm_widget *w,
170 	struct snd_kcontrol *kcontrol, int event)
171 {
172 	const u32 mask = SGTL5000_DAC_POWERUP | SGTL5000_ADC_POWERUP;
173 
174 	switch (event) {
175 	case SND_SOC_DAPM_POST_PMU:
176 		snd_soc_update_bits(w->codec, SGTL5000_CHIP_ANA_POWER,
177 			SGTL5000_VAG_POWERUP, SGTL5000_VAG_POWERUP);
178 		break;
179 
180 	case SND_SOC_DAPM_PRE_PMD:
181 		/*
182 		 * Don't clear VAG_POWERUP, when both DAC and ADC are
183 		 * operational to prevent inadvertently starving the
184 		 * other one of them.
185 		 */
186 		if ((snd_soc_read(w->codec, SGTL5000_CHIP_ANA_POWER) &
187 				mask) != mask) {
188 			snd_soc_update_bits(w->codec, SGTL5000_CHIP_ANA_POWER,
189 				SGTL5000_VAG_POWERUP, 0);
190 			msleep(400);
191 		}
192 		break;
193 	default:
194 		break;
195 	}
196 
197 	return 0;
198 }
199 
200 /* input sources for ADC */
201 static const char *adc_mux_text[] = {
202 	"MIC_IN", "LINE_IN"
203 };
204 
205 static SOC_ENUM_SINGLE_DECL(adc_enum,
206 			    SGTL5000_CHIP_ANA_CTRL, 2,
207 			    adc_mux_text);
208 
209 static const struct snd_kcontrol_new adc_mux =
210 SOC_DAPM_ENUM("Capture Mux", adc_enum);
211 
212 /* input sources for DAC */
213 static const char *dac_mux_text[] = {
214 	"DAC", "LINE_IN"
215 };
216 
217 static SOC_ENUM_SINGLE_DECL(dac_enum,
218 			    SGTL5000_CHIP_ANA_CTRL, 6,
219 			    dac_mux_text);
220 
221 static const struct snd_kcontrol_new dac_mux =
222 SOC_DAPM_ENUM("Headphone Mux", dac_enum);
223 
224 static const struct snd_soc_dapm_widget sgtl5000_dapm_widgets[] = {
225 	SND_SOC_DAPM_INPUT("LINE_IN"),
226 	SND_SOC_DAPM_INPUT("MIC_IN"),
227 
228 	SND_SOC_DAPM_OUTPUT("HP_OUT"),
229 	SND_SOC_DAPM_OUTPUT("LINE_OUT"),
230 
231 	SND_SOC_DAPM_SUPPLY("Mic Bias", SGTL5000_CHIP_MIC_CTRL, 8, 0,
232 			    mic_bias_event,
233 			    SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
234 
235 	SND_SOC_DAPM_PGA("HP", SGTL5000_CHIP_ANA_POWER, 4, 0, NULL, 0),
236 	SND_SOC_DAPM_PGA("LO", SGTL5000_CHIP_ANA_POWER, 0, 0, NULL, 0),
237 
238 	SND_SOC_DAPM_MUX("Capture Mux", SND_SOC_NOPM, 0, 0, &adc_mux),
239 	SND_SOC_DAPM_MUX("Headphone Mux", SND_SOC_NOPM, 0, 0, &dac_mux),
240 
241 	/* aif for i2s input */
242 	SND_SOC_DAPM_AIF_IN("AIFIN", "Playback",
243 				0, SGTL5000_CHIP_DIG_POWER,
244 				0, 0),
245 
246 	/* aif for i2s output */
247 	SND_SOC_DAPM_AIF_OUT("AIFOUT", "Capture",
248 				0, SGTL5000_CHIP_DIG_POWER,
249 				1, 0),
250 
251 	SND_SOC_DAPM_ADC("ADC", "Capture", SGTL5000_CHIP_ANA_POWER, 1, 0),
252 	SND_SOC_DAPM_DAC("DAC", "Playback", SGTL5000_CHIP_ANA_POWER, 3, 0),
253 
254 	SND_SOC_DAPM_PRE("VAG_POWER_PRE", power_vag_event),
255 	SND_SOC_DAPM_POST("VAG_POWER_POST", power_vag_event),
256 };
257 
258 /* routes for sgtl5000 */
259 static const struct snd_soc_dapm_route sgtl5000_dapm_routes[] = {
260 	{"Capture Mux", "LINE_IN", "LINE_IN"},	/* line_in --> adc_mux */
261 	{"Capture Mux", "MIC_IN", "MIC_IN"},	/* mic_in --> adc_mux */
262 
263 	{"ADC", NULL, "Capture Mux"},		/* adc_mux --> adc */
264 	{"AIFOUT", NULL, "ADC"},		/* adc --> i2s_out */
265 
266 	{"DAC", NULL, "AIFIN"},			/* i2s-->dac,skip audio mux */
267 	{"Headphone Mux", "DAC", "DAC"},	/* dac --> hp_mux */
268 	{"LO", NULL, "DAC"},			/* dac --> line_out */
269 
270 	{"Headphone Mux", "LINE_IN", "LINE_IN"},/* line_in --> hp_mux */
271 	{"HP", NULL, "Headphone Mux"},		/* hp_mux --> hp */
272 
273 	{"LINE_OUT", NULL, "LO"},
274 	{"HP_OUT", NULL, "HP"},
275 };
276 
277 /* custom function to fetch info of PCM playback volume */
278 static int dac_info_volsw(struct snd_kcontrol *kcontrol,
279 			  struct snd_ctl_elem_info *uinfo)
280 {
281 	uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
282 	uinfo->count = 2;
283 	uinfo->value.integer.min = 0;
284 	uinfo->value.integer.max = 0xfc - 0x3c;
285 	return 0;
286 }
287 
288 /*
289  * custom function to get of PCM playback volume
290  *
291  * dac volume register
292  * 15-------------8-7--------------0
293  * | R channel vol | L channel vol |
294  *  -------------------------------
295  *
296  * PCM volume with 0.5017 dB steps from 0 to -90 dB
297  *
298  * register values map to dB
299  * 0x3B and less = Reserved
300  * 0x3C = 0 dB
301  * 0x3D = -0.5 dB
302  * 0xF0 = -90 dB
303  * 0xFC and greater = Muted
304  *
305  * register value map to userspace value
306  *
307  * register value	0x3c(0dB)	  0xf0(-90dB)0xfc
308  *			------------------------------
309  * userspace value	0xc0			     0
310  */
311 static int dac_get_volsw(struct snd_kcontrol *kcontrol,
312 			 struct snd_ctl_elem_value *ucontrol)
313 {
314 	struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
315 	int reg;
316 	int l;
317 	int r;
318 
319 	reg = snd_soc_read(codec, SGTL5000_CHIP_DAC_VOL);
320 
321 	/* get left channel volume */
322 	l = (reg & SGTL5000_DAC_VOL_LEFT_MASK) >> SGTL5000_DAC_VOL_LEFT_SHIFT;
323 
324 	/* get right channel volume */
325 	r = (reg & SGTL5000_DAC_VOL_RIGHT_MASK) >> SGTL5000_DAC_VOL_RIGHT_SHIFT;
326 
327 	/* make sure value fall in (0x3c,0xfc) */
328 	l = clamp(l, 0x3c, 0xfc);
329 	r = clamp(r, 0x3c, 0xfc);
330 
331 	/* invert it and map to userspace value */
332 	l = 0xfc - l;
333 	r = 0xfc - r;
334 
335 	ucontrol->value.integer.value[0] = l;
336 	ucontrol->value.integer.value[1] = r;
337 
338 	return 0;
339 }
340 
341 /*
342  * custom function to put of PCM playback volume
343  *
344  * dac volume register
345  * 15-------------8-7--------------0
346  * | R channel vol | L channel vol |
347  *  -------------------------------
348  *
349  * PCM volume with 0.5017 dB steps from 0 to -90 dB
350  *
351  * register values map to dB
352  * 0x3B and less = Reserved
353  * 0x3C = 0 dB
354  * 0x3D = -0.5 dB
355  * 0xF0 = -90 dB
356  * 0xFC and greater = Muted
357  *
358  * userspace value map to register value
359  *
360  * userspace value	0xc0			     0
361  *			------------------------------
362  * register value	0x3c(0dB)	0xf0(-90dB)0xfc
363  */
364 static int dac_put_volsw(struct snd_kcontrol *kcontrol,
365 			 struct snd_ctl_elem_value *ucontrol)
366 {
367 	struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
368 	int reg;
369 	int l;
370 	int r;
371 
372 	l = ucontrol->value.integer.value[0];
373 	r = ucontrol->value.integer.value[1];
374 
375 	/* make sure userspace volume fall in (0, 0xfc-0x3c) */
376 	l = clamp(l, 0, 0xfc - 0x3c);
377 	r = clamp(r, 0, 0xfc - 0x3c);
378 
379 	/* invert it, get the value can be set to register */
380 	l = 0xfc - l;
381 	r = 0xfc - r;
382 
383 	/* shift to get the register value */
384 	reg = l << SGTL5000_DAC_VOL_LEFT_SHIFT |
385 		r << SGTL5000_DAC_VOL_RIGHT_SHIFT;
386 
387 	snd_soc_write(codec, SGTL5000_CHIP_DAC_VOL, reg);
388 
389 	return 0;
390 }
391 
392 static const DECLARE_TLV_DB_SCALE(capture_6db_attenuate, -600, 600, 0);
393 
394 /* tlv for mic gain, 0db 20db 30db 40db */
395 static const unsigned int mic_gain_tlv[] = {
396 	TLV_DB_RANGE_HEAD(2),
397 	0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
398 	1, 3, TLV_DB_SCALE_ITEM(2000, 1000, 0),
399 };
400 
401 /* tlv for hp volume, -51.5db to 12.0db, step .5db */
402 static const DECLARE_TLV_DB_SCALE(headphone_volume, -5150, 50, 0);
403 
404 static const struct snd_kcontrol_new sgtl5000_snd_controls[] = {
405 	/* SOC_DOUBLE_S8_TLV with invert */
406 	{
407 		.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
408 		.name = "PCM Playback Volume",
409 		.access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |
410 			SNDRV_CTL_ELEM_ACCESS_READWRITE,
411 		.info = dac_info_volsw,
412 		.get = dac_get_volsw,
413 		.put = dac_put_volsw,
414 	},
415 
416 	SOC_DOUBLE("Capture Volume", SGTL5000_CHIP_ANA_ADC_CTRL, 0, 4, 0xf, 0),
417 	SOC_SINGLE_TLV("Capture Attenuate Switch (-6dB)",
418 			SGTL5000_CHIP_ANA_ADC_CTRL,
419 			8, 1, 0, capture_6db_attenuate),
420 	SOC_SINGLE("Capture ZC Switch", SGTL5000_CHIP_ANA_CTRL, 1, 1, 0),
421 
422 	SOC_DOUBLE_TLV("Headphone Playback Volume",
423 			SGTL5000_CHIP_ANA_HP_CTRL,
424 			0, 8,
425 			0x7f, 1,
426 			headphone_volume),
427 	SOC_SINGLE("Headphone Playback ZC Switch", SGTL5000_CHIP_ANA_CTRL,
428 			5, 1, 0),
429 
430 	SOC_SINGLE_TLV("Mic Volume", SGTL5000_CHIP_MIC_CTRL,
431 			0, 3, 0, mic_gain_tlv),
432 };
433 
434 /* mute the codec used by alsa core */
435 static int sgtl5000_digital_mute(struct snd_soc_dai *codec_dai, int mute)
436 {
437 	struct snd_soc_codec *codec = codec_dai->codec;
438 	u16 adcdac_ctrl = SGTL5000_DAC_MUTE_LEFT | SGTL5000_DAC_MUTE_RIGHT;
439 
440 	snd_soc_update_bits(codec, SGTL5000_CHIP_ADCDAC_CTRL,
441 			adcdac_ctrl, mute ? adcdac_ctrl : 0);
442 
443 	return 0;
444 }
445 
446 /* set codec format */
447 static int sgtl5000_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
448 {
449 	struct snd_soc_codec *codec = codec_dai->codec;
450 	struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
451 	u16 i2sctl = 0;
452 
453 	sgtl5000->master = 0;
454 	/*
455 	 * i2s clock and frame master setting.
456 	 * ONLY support:
457 	 *  - clock and frame slave,
458 	 *  - clock and frame master
459 	 */
460 	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
461 	case SND_SOC_DAIFMT_CBS_CFS:
462 		break;
463 	case SND_SOC_DAIFMT_CBM_CFM:
464 		i2sctl |= SGTL5000_I2S_MASTER;
465 		sgtl5000->master = 1;
466 		break;
467 	default:
468 		return -EINVAL;
469 	}
470 
471 	/* setting i2s data format */
472 	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
473 	case SND_SOC_DAIFMT_DSP_A:
474 		i2sctl |= SGTL5000_I2S_MODE_PCM;
475 		break;
476 	case SND_SOC_DAIFMT_DSP_B:
477 		i2sctl |= SGTL5000_I2S_MODE_PCM;
478 		i2sctl |= SGTL5000_I2S_LRALIGN;
479 		break;
480 	case SND_SOC_DAIFMT_I2S:
481 		i2sctl |= SGTL5000_I2S_MODE_I2S_LJ;
482 		break;
483 	case SND_SOC_DAIFMT_RIGHT_J:
484 		i2sctl |= SGTL5000_I2S_MODE_RJ;
485 		i2sctl |= SGTL5000_I2S_LRPOL;
486 		break;
487 	case SND_SOC_DAIFMT_LEFT_J:
488 		i2sctl |= SGTL5000_I2S_MODE_I2S_LJ;
489 		i2sctl |= SGTL5000_I2S_LRALIGN;
490 		break;
491 	default:
492 		return -EINVAL;
493 	}
494 
495 	sgtl5000->fmt = fmt & SND_SOC_DAIFMT_FORMAT_MASK;
496 
497 	/* Clock inversion */
498 	switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
499 	case SND_SOC_DAIFMT_NB_NF:
500 		break;
501 	case SND_SOC_DAIFMT_IB_NF:
502 		i2sctl |= SGTL5000_I2S_SCLK_INV;
503 		break;
504 	default:
505 		return -EINVAL;
506 	}
507 
508 	snd_soc_write(codec, SGTL5000_CHIP_I2S_CTRL, i2sctl);
509 
510 	return 0;
511 }
512 
513 /* set codec sysclk */
514 static int sgtl5000_set_dai_sysclk(struct snd_soc_dai *codec_dai,
515 				   int clk_id, unsigned int freq, int dir)
516 {
517 	struct snd_soc_codec *codec = codec_dai->codec;
518 	struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
519 
520 	switch (clk_id) {
521 	case SGTL5000_SYSCLK:
522 		sgtl5000->sysclk = freq;
523 		break;
524 	default:
525 		return -EINVAL;
526 	}
527 
528 	return 0;
529 }
530 
531 /*
532  * set clock according to i2s frame clock,
533  * sgtl5000 provide 2 clock sources.
534  * 1. sys_mclk. sample freq can only configure to
535  *	1/256, 1/384, 1/512 of sys_mclk.
536  * 2. pll. can derive any audio clocks.
537  *
538  * clock setting rules:
539  * 1. in slave mode, only sys_mclk can use.
540  * 2. as constraint by sys_mclk, sample freq should
541  *	set to 32k, 44.1k and above.
542  * 3. using sys_mclk prefer to pll to save power.
543  */
544 static int sgtl5000_set_clock(struct snd_soc_codec *codec, int frame_rate)
545 {
546 	struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
547 	int clk_ctl = 0;
548 	int sys_fs;	/* sample freq */
549 
550 	/*
551 	 * sample freq should be divided by frame clock,
552 	 * if frame clock lower than 44.1khz, sample feq should set to
553 	 * 32khz or 44.1khz.
554 	 */
555 	switch (frame_rate) {
556 	case 8000:
557 	case 16000:
558 		sys_fs = 32000;
559 		break;
560 	case 11025:
561 	case 22050:
562 		sys_fs = 44100;
563 		break;
564 	default:
565 		sys_fs = frame_rate;
566 		break;
567 	}
568 
569 	/* set divided factor of frame clock */
570 	switch (sys_fs / frame_rate) {
571 	case 4:
572 		clk_ctl |= SGTL5000_RATE_MODE_DIV_4 << SGTL5000_RATE_MODE_SHIFT;
573 		break;
574 	case 2:
575 		clk_ctl |= SGTL5000_RATE_MODE_DIV_2 << SGTL5000_RATE_MODE_SHIFT;
576 		break;
577 	case 1:
578 		clk_ctl |= SGTL5000_RATE_MODE_DIV_1 << SGTL5000_RATE_MODE_SHIFT;
579 		break;
580 	default:
581 		return -EINVAL;
582 	}
583 
584 	/* set the sys_fs according to frame rate */
585 	switch (sys_fs) {
586 	case 32000:
587 		clk_ctl |= SGTL5000_SYS_FS_32k << SGTL5000_SYS_FS_SHIFT;
588 		break;
589 	case 44100:
590 		clk_ctl |= SGTL5000_SYS_FS_44_1k << SGTL5000_SYS_FS_SHIFT;
591 		break;
592 	case 48000:
593 		clk_ctl |= SGTL5000_SYS_FS_48k << SGTL5000_SYS_FS_SHIFT;
594 		break;
595 	case 96000:
596 		clk_ctl |= SGTL5000_SYS_FS_96k << SGTL5000_SYS_FS_SHIFT;
597 		break;
598 	default:
599 		dev_err(codec->dev, "frame rate %d not supported\n",
600 			frame_rate);
601 		return -EINVAL;
602 	}
603 
604 	/*
605 	 * calculate the divider of mclk/sample_freq,
606 	 * factor of freq =96k can only be 256, since mclk in range (12m,27m)
607 	 */
608 	switch (sgtl5000->sysclk / sys_fs) {
609 	case 256:
610 		clk_ctl |= SGTL5000_MCLK_FREQ_256FS <<
611 			SGTL5000_MCLK_FREQ_SHIFT;
612 		break;
613 	case 384:
614 		clk_ctl |= SGTL5000_MCLK_FREQ_384FS <<
615 			SGTL5000_MCLK_FREQ_SHIFT;
616 		break;
617 	case 512:
618 		clk_ctl |= SGTL5000_MCLK_FREQ_512FS <<
619 			SGTL5000_MCLK_FREQ_SHIFT;
620 		break;
621 	default:
622 		/* if mclk not satisify the divider, use pll */
623 		if (sgtl5000->master) {
624 			clk_ctl |= SGTL5000_MCLK_FREQ_PLL <<
625 				SGTL5000_MCLK_FREQ_SHIFT;
626 		} else {
627 			dev_err(codec->dev,
628 				"PLL not supported in slave mode\n");
629 			return -EINVAL;
630 		}
631 	}
632 
633 	/* if using pll, please check manual 6.4.2 for detail */
634 	if ((clk_ctl & SGTL5000_MCLK_FREQ_MASK) == SGTL5000_MCLK_FREQ_PLL) {
635 		u64 out, t;
636 		int div2;
637 		int pll_ctl;
638 		unsigned int in, int_div, frac_div;
639 
640 		if (sgtl5000->sysclk > 17000000) {
641 			div2 = 1;
642 			in = sgtl5000->sysclk / 2;
643 		} else {
644 			div2 = 0;
645 			in = sgtl5000->sysclk;
646 		}
647 		if (sys_fs == 44100)
648 			out = 180633600;
649 		else
650 			out = 196608000;
651 		t = do_div(out, in);
652 		int_div = out;
653 		t *= 2048;
654 		do_div(t, in);
655 		frac_div = t;
656 		pll_ctl = int_div << SGTL5000_PLL_INT_DIV_SHIFT |
657 		    frac_div << SGTL5000_PLL_FRAC_DIV_SHIFT;
658 
659 		snd_soc_write(codec, SGTL5000_CHIP_PLL_CTRL, pll_ctl);
660 		if (div2)
661 			snd_soc_update_bits(codec,
662 				SGTL5000_CHIP_CLK_TOP_CTRL,
663 				SGTL5000_INPUT_FREQ_DIV2,
664 				SGTL5000_INPUT_FREQ_DIV2);
665 		else
666 			snd_soc_update_bits(codec,
667 				SGTL5000_CHIP_CLK_TOP_CTRL,
668 				SGTL5000_INPUT_FREQ_DIV2,
669 				0);
670 
671 		/* power up pll */
672 		snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
673 			SGTL5000_PLL_POWERUP | SGTL5000_VCOAMP_POWERUP,
674 			SGTL5000_PLL_POWERUP | SGTL5000_VCOAMP_POWERUP);
675 
676 		/* if using pll, clk_ctrl must be set after pll power up */
677 		snd_soc_write(codec, SGTL5000_CHIP_CLK_CTRL, clk_ctl);
678 	} else {
679 		/* otherwise, clk_ctrl must be set before pll power down */
680 		snd_soc_write(codec, SGTL5000_CHIP_CLK_CTRL, clk_ctl);
681 
682 		/* power down pll */
683 		snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
684 			SGTL5000_PLL_POWERUP | SGTL5000_VCOAMP_POWERUP,
685 			0);
686 	}
687 
688 	return 0;
689 }
690 
691 /*
692  * Set PCM DAI bit size and sample rate.
693  * input: params_rate, params_fmt
694  */
695 static int sgtl5000_pcm_hw_params(struct snd_pcm_substream *substream,
696 				  struct snd_pcm_hw_params *params,
697 				  struct snd_soc_dai *dai)
698 {
699 	struct snd_soc_codec *codec = dai->codec;
700 	struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
701 	int channels = params_channels(params);
702 	int i2s_ctl = 0;
703 	int stereo;
704 	int ret;
705 
706 	/* sysclk should already set */
707 	if (!sgtl5000->sysclk) {
708 		dev_err(codec->dev, "%s: set sysclk first!\n", __func__);
709 		return -EFAULT;
710 	}
711 
712 	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
713 		stereo = SGTL5000_DAC_STEREO;
714 	else
715 		stereo = SGTL5000_ADC_STEREO;
716 
717 	/* set mono to save power */
718 	snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER, stereo,
719 			channels == 1 ? 0 : stereo);
720 
721 	/* set codec clock base on lrclk */
722 	ret = sgtl5000_set_clock(codec, params_rate(params));
723 	if (ret)
724 		return ret;
725 
726 	/* set i2s data format */
727 	switch (params_format(params)) {
728 	case SNDRV_PCM_FORMAT_S16_LE:
729 		if (sgtl5000->fmt == SND_SOC_DAIFMT_RIGHT_J)
730 			return -EINVAL;
731 		i2s_ctl |= SGTL5000_I2S_DLEN_16 << SGTL5000_I2S_DLEN_SHIFT;
732 		i2s_ctl |= SGTL5000_I2S_SCLKFREQ_32FS <<
733 		    SGTL5000_I2S_SCLKFREQ_SHIFT;
734 		break;
735 	case SNDRV_PCM_FORMAT_S20_3LE:
736 		i2s_ctl |= SGTL5000_I2S_DLEN_20 << SGTL5000_I2S_DLEN_SHIFT;
737 		i2s_ctl |= SGTL5000_I2S_SCLKFREQ_64FS <<
738 		    SGTL5000_I2S_SCLKFREQ_SHIFT;
739 		break;
740 	case SNDRV_PCM_FORMAT_S24_LE:
741 		i2s_ctl |= SGTL5000_I2S_DLEN_24 << SGTL5000_I2S_DLEN_SHIFT;
742 		i2s_ctl |= SGTL5000_I2S_SCLKFREQ_64FS <<
743 		    SGTL5000_I2S_SCLKFREQ_SHIFT;
744 		break;
745 	case SNDRV_PCM_FORMAT_S32_LE:
746 		if (sgtl5000->fmt == SND_SOC_DAIFMT_RIGHT_J)
747 			return -EINVAL;
748 		i2s_ctl |= SGTL5000_I2S_DLEN_32 << SGTL5000_I2S_DLEN_SHIFT;
749 		i2s_ctl |= SGTL5000_I2S_SCLKFREQ_64FS <<
750 		    SGTL5000_I2S_SCLKFREQ_SHIFT;
751 		break;
752 	default:
753 		return -EINVAL;
754 	}
755 
756 	snd_soc_update_bits(codec, SGTL5000_CHIP_I2S_CTRL,
757 			    SGTL5000_I2S_DLEN_MASK | SGTL5000_I2S_SCLKFREQ_MASK,
758 			    i2s_ctl);
759 
760 	return 0;
761 }
762 
763 #ifdef CONFIG_REGULATOR
764 static int ldo_regulator_is_enabled(struct regulator_dev *dev)
765 {
766 	struct ldo_regulator *ldo = rdev_get_drvdata(dev);
767 
768 	return ldo->enabled;
769 }
770 
771 static int ldo_regulator_enable(struct regulator_dev *dev)
772 {
773 	struct ldo_regulator *ldo = rdev_get_drvdata(dev);
774 	struct snd_soc_codec *codec = (struct snd_soc_codec *)ldo->codec_data;
775 	int reg;
776 
777 	if (ldo_regulator_is_enabled(dev))
778 		return 0;
779 
780 	/* set regulator value firstly */
781 	reg = (1600 - ldo->voltage / 1000) / 50;
782 	reg = clamp(reg, 0x0, 0xf);
783 
784 	/* amend the voltage value, unit: uV */
785 	ldo->voltage = (1600 - reg * 50) * 1000;
786 
787 	/* set voltage to register */
788 	snd_soc_update_bits(codec, SGTL5000_CHIP_LINREG_CTRL,
789 				SGTL5000_LINREG_VDDD_MASK, reg);
790 
791 	snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
792 				SGTL5000_LINEREG_D_POWERUP,
793 				SGTL5000_LINEREG_D_POWERUP);
794 
795 	/* when internal ldo enabled, simple digital power can be disabled */
796 	snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
797 				SGTL5000_LINREG_SIMPLE_POWERUP,
798 				0);
799 
800 	ldo->enabled = 1;
801 	return 0;
802 }
803 
804 static int ldo_regulator_disable(struct regulator_dev *dev)
805 {
806 	struct ldo_regulator *ldo = rdev_get_drvdata(dev);
807 	struct snd_soc_codec *codec = (struct snd_soc_codec *)ldo->codec_data;
808 
809 	snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
810 				SGTL5000_LINEREG_D_POWERUP,
811 				0);
812 
813 	/* clear voltage info */
814 	snd_soc_update_bits(codec, SGTL5000_CHIP_LINREG_CTRL,
815 				SGTL5000_LINREG_VDDD_MASK, 0);
816 
817 	ldo->enabled = 0;
818 
819 	return 0;
820 }
821 
822 static int ldo_regulator_get_voltage(struct regulator_dev *dev)
823 {
824 	struct ldo_regulator *ldo = rdev_get_drvdata(dev);
825 
826 	return ldo->voltage;
827 }
828 
829 static struct regulator_ops ldo_regulator_ops = {
830 	.is_enabled = ldo_regulator_is_enabled,
831 	.enable = ldo_regulator_enable,
832 	.disable = ldo_regulator_disable,
833 	.get_voltage = ldo_regulator_get_voltage,
834 };
835 
836 static int ldo_regulator_register(struct snd_soc_codec *codec,
837 				struct regulator_init_data *init_data,
838 				int voltage)
839 {
840 	struct ldo_regulator *ldo;
841 	struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
842 	struct regulator_config config = { };
843 
844 	ldo = kzalloc(sizeof(struct ldo_regulator), GFP_KERNEL);
845 
846 	if (!ldo) {
847 		dev_err(codec->dev, "failed to allocate ldo_regulator\n");
848 		return -ENOMEM;
849 	}
850 
851 	ldo->desc.name = kstrdup(dev_name(codec->dev), GFP_KERNEL);
852 	if (!ldo->desc.name) {
853 		kfree(ldo);
854 		dev_err(codec->dev, "failed to allocate decs name memory\n");
855 		return -ENOMEM;
856 	}
857 
858 	ldo->desc.type  = REGULATOR_VOLTAGE;
859 	ldo->desc.owner = THIS_MODULE;
860 	ldo->desc.ops   = &ldo_regulator_ops;
861 	ldo->desc.n_voltages = 1;
862 
863 	ldo->codec_data = codec;
864 	ldo->voltage = voltage;
865 
866 	config.dev = codec->dev;
867 	config.driver_data = ldo;
868 	config.init_data = init_data;
869 
870 	ldo->dev = regulator_register(&ldo->desc, &config);
871 	if (IS_ERR(ldo->dev)) {
872 		int ret = PTR_ERR(ldo->dev);
873 
874 		dev_err(codec->dev, "failed to register regulator\n");
875 		kfree(ldo->desc.name);
876 		kfree(ldo);
877 
878 		return ret;
879 	}
880 	sgtl5000->ldo = ldo;
881 
882 	return 0;
883 }
884 
885 static int ldo_regulator_remove(struct snd_soc_codec *codec)
886 {
887 	struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
888 	struct ldo_regulator *ldo = sgtl5000->ldo;
889 
890 	if (!ldo)
891 		return 0;
892 
893 	regulator_unregister(ldo->dev);
894 	kfree(ldo->desc.name);
895 	kfree(ldo);
896 
897 	return 0;
898 }
899 #else
900 static int ldo_regulator_register(struct snd_soc_codec *codec,
901 				struct regulator_init_data *init_data,
902 				int voltage)
903 {
904 	dev_err(codec->dev, "this setup needs regulator support in the kernel\n");
905 	return -EINVAL;
906 }
907 
908 static int ldo_regulator_remove(struct snd_soc_codec *codec)
909 {
910 	return 0;
911 }
912 #endif
913 
914 /*
915  * set dac bias
916  * common state changes:
917  * startup:
918  * off --> standby --> prepare --> on
919  * standby --> prepare --> on
920  *
921  * stop:
922  * on --> prepare --> standby
923  */
924 static int sgtl5000_set_bias_level(struct snd_soc_codec *codec,
925 				   enum snd_soc_bias_level level)
926 {
927 	int ret;
928 	struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
929 
930 	switch (level) {
931 	case SND_SOC_BIAS_ON:
932 	case SND_SOC_BIAS_PREPARE:
933 		break;
934 	case SND_SOC_BIAS_STANDBY:
935 		if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
936 			ret = regulator_bulk_enable(
937 						ARRAY_SIZE(sgtl5000->supplies),
938 						sgtl5000->supplies);
939 			if (ret)
940 				return ret;
941 			udelay(10);
942 
943 			regcache_cache_only(sgtl5000->regmap, false);
944 
945 			ret = regcache_sync(sgtl5000->regmap);
946 			if (ret != 0) {
947 				dev_err(codec->dev,
948 					"Failed to restore cache: %d\n", ret);
949 
950 				regcache_cache_only(sgtl5000->regmap, true);
951 				regulator_bulk_disable(ARRAY_SIZE(sgtl5000->supplies),
952 						       sgtl5000->supplies);
953 
954 				return ret;
955 			}
956 		}
957 
958 		break;
959 	case SND_SOC_BIAS_OFF:
960 		regcache_cache_only(sgtl5000->regmap, true);
961 		regulator_bulk_disable(ARRAY_SIZE(sgtl5000->supplies),
962 					sgtl5000->supplies);
963 		break;
964 	}
965 
966 	codec->dapm.bias_level = level;
967 	return 0;
968 }
969 
970 #define SGTL5000_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
971 			SNDRV_PCM_FMTBIT_S20_3LE |\
972 			SNDRV_PCM_FMTBIT_S24_LE |\
973 			SNDRV_PCM_FMTBIT_S32_LE)
974 
975 static const struct snd_soc_dai_ops sgtl5000_ops = {
976 	.hw_params = sgtl5000_pcm_hw_params,
977 	.digital_mute = sgtl5000_digital_mute,
978 	.set_fmt = sgtl5000_set_dai_fmt,
979 	.set_sysclk = sgtl5000_set_dai_sysclk,
980 };
981 
982 static struct snd_soc_dai_driver sgtl5000_dai = {
983 	.name = "sgtl5000",
984 	.playback = {
985 		.stream_name = "Playback",
986 		.channels_min = 1,
987 		.channels_max = 2,
988 		/*
989 		 * only support 8~48K + 96K,
990 		 * TODO modify hw_param to support more
991 		 */
992 		.rates = SNDRV_PCM_RATE_8000_48000 | SNDRV_PCM_RATE_96000,
993 		.formats = SGTL5000_FORMATS,
994 	},
995 	.capture = {
996 		.stream_name = "Capture",
997 		.channels_min = 1,
998 		.channels_max = 2,
999 		.rates = SNDRV_PCM_RATE_8000_48000 | SNDRV_PCM_RATE_96000,
1000 		.formats = SGTL5000_FORMATS,
1001 	},
1002 	.ops = &sgtl5000_ops,
1003 	.symmetric_rates = 1,
1004 };
1005 
1006 static bool sgtl5000_volatile(struct device *dev, unsigned int reg)
1007 {
1008 	switch (reg) {
1009 	case SGTL5000_CHIP_ID:
1010 	case SGTL5000_CHIP_ADCDAC_CTRL:
1011 	case SGTL5000_CHIP_ANA_STATUS:
1012 		return true;
1013 	}
1014 
1015 	return false;
1016 }
1017 
1018 static bool sgtl5000_readable(struct device *dev, unsigned int reg)
1019 {
1020 	switch (reg) {
1021 	case SGTL5000_CHIP_ID:
1022 	case SGTL5000_CHIP_DIG_POWER:
1023 	case SGTL5000_CHIP_CLK_CTRL:
1024 	case SGTL5000_CHIP_I2S_CTRL:
1025 	case SGTL5000_CHIP_SSS_CTRL:
1026 	case SGTL5000_CHIP_ADCDAC_CTRL:
1027 	case SGTL5000_CHIP_DAC_VOL:
1028 	case SGTL5000_CHIP_PAD_STRENGTH:
1029 	case SGTL5000_CHIP_ANA_ADC_CTRL:
1030 	case SGTL5000_CHIP_ANA_HP_CTRL:
1031 	case SGTL5000_CHIP_ANA_CTRL:
1032 	case SGTL5000_CHIP_LINREG_CTRL:
1033 	case SGTL5000_CHIP_REF_CTRL:
1034 	case SGTL5000_CHIP_MIC_CTRL:
1035 	case SGTL5000_CHIP_LINE_OUT_CTRL:
1036 	case SGTL5000_CHIP_LINE_OUT_VOL:
1037 	case SGTL5000_CHIP_ANA_POWER:
1038 	case SGTL5000_CHIP_PLL_CTRL:
1039 	case SGTL5000_CHIP_CLK_TOP_CTRL:
1040 	case SGTL5000_CHIP_ANA_STATUS:
1041 	case SGTL5000_CHIP_SHORT_CTRL:
1042 	case SGTL5000_CHIP_ANA_TEST2:
1043 	case SGTL5000_DAP_CTRL:
1044 	case SGTL5000_DAP_PEQ:
1045 	case SGTL5000_DAP_BASS_ENHANCE:
1046 	case SGTL5000_DAP_BASS_ENHANCE_CTRL:
1047 	case SGTL5000_DAP_AUDIO_EQ:
1048 	case SGTL5000_DAP_SURROUND:
1049 	case SGTL5000_DAP_FLT_COEF_ACCESS:
1050 	case SGTL5000_DAP_COEF_WR_B0_MSB:
1051 	case SGTL5000_DAP_COEF_WR_B0_LSB:
1052 	case SGTL5000_DAP_EQ_BASS_BAND0:
1053 	case SGTL5000_DAP_EQ_BASS_BAND1:
1054 	case SGTL5000_DAP_EQ_BASS_BAND2:
1055 	case SGTL5000_DAP_EQ_BASS_BAND3:
1056 	case SGTL5000_DAP_EQ_BASS_BAND4:
1057 	case SGTL5000_DAP_MAIN_CHAN:
1058 	case SGTL5000_DAP_MIX_CHAN:
1059 	case SGTL5000_DAP_AVC_CTRL:
1060 	case SGTL5000_DAP_AVC_THRESHOLD:
1061 	case SGTL5000_DAP_AVC_ATTACK:
1062 	case SGTL5000_DAP_AVC_DECAY:
1063 	case SGTL5000_DAP_COEF_WR_B1_MSB:
1064 	case SGTL5000_DAP_COEF_WR_B1_LSB:
1065 	case SGTL5000_DAP_COEF_WR_B2_MSB:
1066 	case SGTL5000_DAP_COEF_WR_B2_LSB:
1067 	case SGTL5000_DAP_COEF_WR_A1_MSB:
1068 	case SGTL5000_DAP_COEF_WR_A1_LSB:
1069 	case SGTL5000_DAP_COEF_WR_A2_MSB:
1070 	case SGTL5000_DAP_COEF_WR_A2_LSB:
1071 		return true;
1072 
1073 	default:
1074 		return false;
1075 	}
1076 }
1077 
1078 #ifdef CONFIG_SUSPEND
1079 static int sgtl5000_suspend(struct snd_soc_codec *codec)
1080 {
1081 	sgtl5000_set_bias_level(codec, SND_SOC_BIAS_OFF);
1082 
1083 	return 0;
1084 }
1085 
1086 static int sgtl5000_resume(struct snd_soc_codec *codec)
1087 {
1088 	/* Bring the codec back up to standby to enable regulators */
1089 	sgtl5000_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1090 
1091 	return 0;
1092 }
1093 #else
1094 #define sgtl5000_suspend NULL
1095 #define sgtl5000_resume  NULL
1096 #endif	/* CONFIG_SUSPEND */
1097 
1098 /*
1099  * sgtl5000 has 3 internal power supplies:
1100  * 1. VAG, normally set to vdda/2
1101  * 2. chargepump, set to different value
1102  *	according to voltage of vdda and vddio
1103  * 3. line out VAG, normally set to vddio/2
1104  *
1105  * and should be set according to:
1106  * 1. vddd provided by external or not
1107  * 2. vdda and vddio voltage value. > 3.1v or not
1108  * 3. chip revision >=0x11 or not. If >=0x11, not use external vddd.
1109  */
1110 static int sgtl5000_set_power_regs(struct snd_soc_codec *codec)
1111 {
1112 	int vddd;
1113 	int vdda;
1114 	int vddio;
1115 	u16 ana_pwr;
1116 	u16 lreg_ctrl;
1117 	int vag;
1118 	struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
1119 
1120 	vdda  = regulator_get_voltage(sgtl5000->supplies[VDDA].consumer);
1121 	vddio = regulator_get_voltage(sgtl5000->supplies[VDDIO].consumer);
1122 	vddd  = regulator_get_voltage(sgtl5000->supplies[VDDD].consumer);
1123 
1124 	vdda  = vdda / 1000;
1125 	vddio = vddio / 1000;
1126 	vddd  = vddd / 1000;
1127 
1128 	if (vdda <= 0 || vddio <= 0 || vddd < 0) {
1129 		dev_err(codec->dev, "regulator voltage not set correctly\n");
1130 
1131 		return -EINVAL;
1132 	}
1133 
1134 	/* according to datasheet, maximum voltage of supplies */
1135 	if (vdda > 3600 || vddio > 3600 || vddd > 1980) {
1136 		dev_err(codec->dev,
1137 			"exceed max voltage vdda %dmV vddio %dmV vddd %dmV\n",
1138 			vdda, vddio, vddd);
1139 
1140 		return -EINVAL;
1141 	}
1142 
1143 	/* reset value */
1144 	ana_pwr = snd_soc_read(codec, SGTL5000_CHIP_ANA_POWER);
1145 	ana_pwr |= SGTL5000_DAC_STEREO |
1146 			SGTL5000_ADC_STEREO |
1147 			SGTL5000_REFTOP_POWERUP;
1148 	lreg_ctrl = snd_soc_read(codec, SGTL5000_CHIP_LINREG_CTRL);
1149 
1150 	if (vddio < 3100 && vdda < 3100) {
1151 		/* enable internal oscillator used for charge pump */
1152 		snd_soc_update_bits(codec, SGTL5000_CHIP_CLK_TOP_CTRL,
1153 					SGTL5000_INT_OSC_EN,
1154 					SGTL5000_INT_OSC_EN);
1155 		/* Enable VDDC charge pump */
1156 		ana_pwr |= SGTL5000_VDDC_CHRGPMP_POWERUP;
1157 	} else if (vddio >= 3100 && vdda >= 3100) {
1158 		/*
1159 		 * if vddio and vddd > 3.1v,
1160 		 * charge pump should be clean before set ana_pwr
1161 		 */
1162 		snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
1163 				SGTL5000_VDDC_CHRGPMP_POWERUP, 0);
1164 
1165 		/* VDDC use VDDIO rail */
1166 		lreg_ctrl |= SGTL5000_VDDC_ASSN_OVRD;
1167 		lreg_ctrl |= SGTL5000_VDDC_MAN_ASSN_VDDIO <<
1168 			    SGTL5000_VDDC_MAN_ASSN_SHIFT;
1169 	}
1170 
1171 	snd_soc_write(codec, SGTL5000_CHIP_LINREG_CTRL, lreg_ctrl);
1172 
1173 	snd_soc_write(codec, SGTL5000_CHIP_ANA_POWER, ana_pwr);
1174 
1175 	/* set voltage to register */
1176 	snd_soc_update_bits(codec, SGTL5000_CHIP_LINREG_CTRL,
1177 				SGTL5000_LINREG_VDDD_MASK, 0x8);
1178 
1179 	/*
1180 	 * if vddd linear reg has been enabled,
1181 	 * simple digital supply should be clear to get
1182 	 * proper VDDD voltage.
1183 	 */
1184 	if (ana_pwr & SGTL5000_LINEREG_D_POWERUP)
1185 		snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
1186 				SGTL5000_LINREG_SIMPLE_POWERUP,
1187 				0);
1188 	else
1189 		snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
1190 				SGTL5000_LINREG_SIMPLE_POWERUP |
1191 				SGTL5000_STARTUP_POWERUP,
1192 				0);
1193 
1194 	/*
1195 	 * set ADC/DAC VAG to vdda / 2,
1196 	 * should stay in range (0.8v, 1.575v)
1197 	 */
1198 	vag = vdda / 2;
1199 	if (vag <= SGTL5000_ANA_GND_BASE)
1200 		vag = 0;
1201 	else if (vag >= SGTL5000_ANA_GND_BASE + SGTL5000_ANA_GND_STP *
1202 		 (SGTL5000_ANA_GND_MASK >> SGTL5000_ANA_GND_SHIFT))
1203 		vag = SGTL5000_ANA_GND_MASK >> SGTL5000_ANA_GND_SHIFT;
1204 	else
1205 		vag = (vag - SGTL5000_ANA_GND_BASE) / SGTL5000_ANA_GND_STP;
1206 
1207 	snd_soc_update_bits(codec, SGTL5000_CHIP_REF_CTRL,
1208 			SGTL5000_ANA_GND_MASK, vag << SGTL5000_ANA_GND_SHIFT);
1209 
1210 	/* set line out VAG to vddio / 2, in range (0.8v, 1.675v) */
1211 	vag = vddio / 2;
1212 	if (vag <= SGTL5000_LINE_OUT_GND_BASE)
1213 		vag = 0;
1214 	else if (vag >= SGTL5000_LINE_OUT_GND_BASE +
1215 		SGTL5000_LINE_OUT_GND_STP * SGTL5000_LINE_OUT_GND_MAX)
1216 		vag = SGTL5000_LINE_OUT_GND_MAX;
1217 	else
1218 		vag = (vag - SGTL5000_LINE_OUT_GND_BASE) /
1219 		    SGTL5000_LINE_OUT_GND_STP;
1220 
1221 	snd_soc_update_bits(codec, SGTL5000_CHIP_LINE_OUT_CTRL,
1222 			SGTL5000_LINE_OUT_CURRENT_MASK |
1223 			SGTL5000_LINE_OUT_GND_MASK,
1224 			vag << SGTL5000_LINE_OUT_GND_SHIFT |
1225 			SGTL5000_LINE_OUT_CURRENT_360u <<
1226 				SGTL5000_LINE_OUT_CURRENT_SHIFT);
1227 
1228 	return 0;
1229 }
1230 
1231 static int sgtl5000_replace_vddd_with_ldo(struct snd_soc_codec *codec)
1232 {
1233 	struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
1234 	int ret;
1235 
1236 	/* set internal ldo to 1.2v */
1237 	ret = ldo_regulator_register(codec, &ldo_init_data, LDO_VOLTAGE);
1238 	if (ret) {
1239 		dev_err(codec->dev,
1240 			"Failed to register vddd internal supplies: %d\n", ret);
1241 		return ret;
1242 	}
1243 
1244 	sgtl5000->supplies[VDDD].supply = LDO_CONSUMER_NAME;
1245 
1246 	dev_info(codec->dev, "Using internal LDO instead of VDDD\n");
1247 	return 0;
1248 }
1249 
1250 static int sgtl5000_enable_regulators(struct snd_soc_codec *codec)
1251 {
1252 	int ret;
1253 	int i;
1254 	int external_vddd = 0;
1255 	struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
1256 	struct regulator *vddd;
1257 
1258 	for (i = 0; i < ARRAY_SIZE(sgtl5000->supplies); i++)
1259 		sgtl5000->supplies[i].supply = supply_names[i];
1260 
1261 	/* External VDDD only works before revision 0x11 */
1262 	if (sgtl5000->revision < 0x11) {
1263 		vddd = regulator_get_optional(codec->dev, "VDDD");
1264 		if (IS_ERR(vddd)) {
1265 			/* See if it's just not registered yet */
1266 			if (PTR_ERR(vddd) == -EPROBE_DEFER)
1267 				return -EPROBE_DEFER;
1268 		} else {
1269 			external_vddd = 1;
1270 			regulator_put(vddd);
1271 		}
1272 	}
1273 
1274 	if (!external_vddd) {
1275 		ret = sgtl5000_replace_vddd_with_ldo(codec);
1276 		if (ret)
1277 			return ret;
1278 	}
1279 
1280 	ret = devm_regulator_bulk_get(codec->dev, ARRAY_SIZE(sgtl5000->supplies),
1281 				 sgtl5000->supplies);
1282 	if (ret)
1283 		goto err_ldo_remove;
1284 
1285 	ret = regulator_bulk_enable(ARRAY_SIZE(sgtl5000->supplies),
1286 					sgtl5000->supplies);
1287 	if (ret)
1288 		goto err_ldo_remove;
1289 
1290 	/* wait for all power rails bring up */
1291 	udelay(10);
1292 
1293 	return 0;
1294 
1295 err_ldo_remove:
1296 	if (!external_vddd)
1297 		ldo_regulator_remove(codec);
1298 	return ret;
1299 
1300 }
1301 
1302 static int sgtl5000_probe(struct snd_soc_codec *codec)
1303 {
1304 	int ret;
1305 	struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
1306 
1307 	ret = sgtl5000_enable_regulators(codec);
1308 	if (ret)
1309 		return ret;
1310 
1311 	/* power up sgtl5000 */
1312 	ret = sgtl5000_set_power_regs(codec);
1313 	if (ret)
1314 		goto err;
1315 
1316 	/* enable small pop, introduce 400ms delay in turning off */
1317 	snd_soc_update_bits(codec, SGTL5000_CHIP_REF_CTRL,
1318 				SGTL5000_SMALL_POP,
1319 				SGTL5000_SMALL_POP);
1320 
1321 	/* disable short cut detector */
1322 	snd_soc_write(codec, SGTL5000_CHIP_SHORT_CTRL, 0);
1323 
1324 	/*
1325 	 * set i2s as default input of sound switch
1326 	 * TODO: add sound switch to control and dapm widge.
1327 	 */
1328 	snd_soc_write(codec, SGTL5000_CHIP_SSS_CTRL,
1329 			SGTL5000_DAC_SEL_I2S_IN << SGTL5000_DAC_SEL_SHIFT);
1330 	snd_soc_write(codec, SGTL5000_CHIP_DIG_POWER,
1331 			SGTL5000_ADC_EN | SGTL5000_DAC_EN);
1332 
1333 	/* enable dac volume ramp by default */
1334 	snd_soc_write(codec, SGTL5000_CHIP_ADCDAC_CTRL,
1335 			SGTL5000_DAC_VOL_RAMP_EN |
1336 			SGTL5000_DAC_MUTE_RIGHT |
1337 			SGTL5000_DAC_MUTE_LEFT);
1338 
1339 	snd_soc_write(codec, SGTL5000_CHIP_PAD_STRENGTH, 0x015f);
1340 
1341 	snd_soc_write(codec, SGTL5000_CHIP_ANA_CTRL,
1342 			SGTL5000_HP_ZCD_EN |
1343 			SGTL5000_ADC_ZCD_EN);
1344 
1345 	snd_soc_write(codec, SGTL5000_CHIP_MIC_CTRL, 2);
1346 
1347 	/*
1348 	 * disable DAP
1349 	 * TODO:
1350 	 * Enable DAP in kcontrol and dapm.
1351 	 */
1352 	snd_soc_write(codec, SGTL5000_DAP_CTRL, 0);
1353 
1354 	/* leading to standby state */
1355 	ret = sgtl5000_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1356 	if (ret)
1357 		goto err;
1358 
1359 	return 0;
1360 
1361 err:
1362 	regulator_bulk_disable(ARRAY_SIZE(sgtl5000->supplies),
1363 						sgtl5000->supplies);
1364 	ldo_regulator_remove(codec);
1365 
1366 	return ret;
1367 }
1368 
1369 static int sgtl5000_remove(struct snd_soc_codec *codec)
1370 {
1371 	struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
1372 
1373 	sgtl5000_set_bias_level(codec, SND_SOC_BIAS_OFF);
1374 
1375 	regulator_bulk_disable(ARRAY_SIZE(sgtl5000->supplies),
1376 						sgtl5000->supplies);
1377 	ldo_regulator_remove(codec);
1378 
1379 	return 0;
1380 }
1381 
1382 static struct snd_soc_codec_driver sgtl5000_driver = {
1383 	.probe = sgtl5000_probe,
1384 	.remove = sgtl5000_remove,
1385 	.suspend = sgtl5000_suspend,
1386 	.resume = sgtl5000_resume,
1387 	.set_bias_level = sgtl5000_set_bias_level,
1388 	.controls = sgtl5000_snd_controls,
1389 	.num_controls = ARRAY_SIZE(sgtl5000_snd_controls),
1390 	.dapm_widgets = sgtl5000_dapm_widgets,
1391 	.num_dapm_widgets = ARRAY_SIZE(sgtl5000_dapm_widgets),
1392 	.dapm_routes = sgtl5000_dapm_routes,
1393 	.num_dapm_routes = ARRAY_SIZE(sgtl5000_dapm_routes),
1394 };
1395 
1396 static const struct regmap_config sgtl5000_regmap = {
1397 	.reg_bits = 16,
1398 	.val_bits = 16,
1399 	.reg_stride = 2,
1400 
1401 	.max_register = SGTL5000_MAX_REG_OFFSET,
1402 	.volatile_reg = sgtl5000_volatile,
1403 	.readable_reg = sgtl5000_readable,
1404 
1405 	.cache_type = REGCACHE_RBTREE,
1406 	.reg_defaults = sgtl5000_reg_defaults,
1407 	.num_reg_defaults = ARRAY_SIZE(sgtl5000_reg_defaults),
1408 };
1409 
1410 /*
1411  * Write all the default values from sgtl5000_reg_defaults[] array into the
1412  * sgtl5000 registers, to make sure we always start with the sane registers
1413  * values as stated in the datasheet.
1414  *
1415  * Since sgtl5000 does not have a reset line, nor a reset command in software,
1416  * we follow this approach to guarantee we always start from the default values
1417  * and avoid problems like, not being able to probe after an audio playback
1418  * followed by a system reset or a 'reboot' command in Linux
1419  */
1420 static int sgtl5000_fill_defaults(struct sgtl5000_priv *sgtl5000)
1421 {
1422 	int i, ret, val, index;
1423 
1424 	for (i = 0; i < ARRAY_SIZE(sgtl5000_reg_defaults); i++) {
1425 		val = sgtl5000_reg_defaults[i].def;
1426 		index = sgtl5000_reg_defaults[i].reg;
1427 		ret = regmap_write(sgtl5000->regmap, index, val);
1428 		if (ret)
1429 			return ret;
1430 	}
1431 
1432 	return 0;
1433 }
1434 
1435 static int sgtl5000_i2c_probe(struct i2c_client *client,
1436 			      const struct i2c_device_id *id)
1437 {
1438 	struct sgtl5000_priv *sgtl5000;
1439 	int ret, reg, rev;
1440 
1441 	sgtl5000 = devm_kzalloc(&client->dev, sizeof(struct sgtl5000_priv),
1442 								GFP_KERNEL);
1443 	if (!sgtl5000)
1444 		return -ENOMEM;
1445 
1446 	sgtl5000->regmap = devm_regmap_init_i2c(client, &sgtl5000_regmap);
1447 	if (IS_ERR(sgtl5000->regmap)) {
1448 		ret = PTR_ERR(sgtl5000->regmap);
1449 		dev_err(&client->dev, "Failed to allocate regmap: %d\n", ret);
1450 		return ret;
1451 	}
1452 
1453 	sgtl5000->mclk = devm_clk_get(&client->dev, NULL);
1454 	if (IS_ERR(sgtl5000->mclk)) {
1455 		ret = PTR_ERR(sgtl5000->mclk);
1456 		dev_err(&client->dev, "Failed to get mclock: %d\n", ret);
1457 		/* Defer the probe to see if the clk will be provided later */
1458 		if (ret == -ENOENT)
1459 			return -EPROBE_DEFER;
1460 		return ret;
1461 	}
1462 
1463 	ret = clk_prepare_enable(sgtl5000->mclk);
1464 	if (ret)
1465 		return ret;
1466 
1467 	/* read chip information */
1468 	ret = regmap_read(sgtl5000->regmap, SGTL5000_CHIP_ID, &reg);
1469 	if (ret)
1470 		goto disable_clk;
1471 
1472 	if (((reg & SGTL5000_PARTID_MASK) >> SGTL5000_PARTID_SHIFT) !=
1473 	    SGTL5000_PARTID_PART_ID) {
1474 		dev_err(&client->dev,
1475 			"Device with ID register %x is not a sgtl5000\n", reg);
1476 		ret = -ENODEV;
1477 		goto disable_clk;
1478 	}
1479 
1480 	rev = (reg & SGTL5000_REVID_MASK) >> SGTL5000_REVID_SHIFT;
1481 	dev_info(&client->dev, "sgtl5000 revision 0x%x\n", rev);
1482 	sgtl5000->revision = rev;
1483 
1484 	i2c_set_clientdata(client, sgtl5000);
1485 
1486 	/* Ensure sgtl5000 will start with sane register values */
1487 	ret = sgtl5000_fill_defaults(sgtl5000);
1488 	if (ret)
1489 		goto disable_clk;
1490 
1491 	ret = snd_soc_register_codec(&client->dev,
1492 			&sgtl5000_driver, &sgtl5000_dai, 1);
1493 	if (ret)
1494 		goto disable_clk;
1495 
1496 	return 0;
1497 
1498 disable_clk:
1499 	clk_disable_unprepare(sgtl5000->mclk);
1500 	return ret;
1501 }
1502 
1503 static int sgtl5000_i2c_remove(struct i2c_client *client)
1504 {
1505 	struct sgtl5000_priv *sgtl5000 = i2c_get_clientdata(client);
1506 
1507 	snd_soc_unregister_codec(&client->dev);
1508 	clk_disable_unprepare(sgtl5000->mclk);
1509 	return 0;
1510 }
1511 
1512 static const struct i2c_device_id sgtl5000_id[] = {
1513 	{"sgtl5000", 0},
1514 	{},
1515 };
1516 
1517 MODULE_DEVICE_TABLE(i2c, sgtl5000_id);
1518 
1519 static const struct of_device_id sgtl5000_dt_ids[] = {
1520 	{ .compatible = "fsl,sgtl5000", },
1521 	{ /* sentinel */ }
1522 };
1523 MODULE_DEVICE_TABLE(of, sgtl5000_dt_ids);
1524 
1525 static struct i2c_driver sgtl5000_i2c_driver = {
1526 	.driver = {
1527 		   .name = "sgtl5000",
1528 		   .owner = THIS_MODULE,
1529 		   .of_match_table = sgtl5000_dt_ids,
1530 		   },
1531 	.probe = sgtl5000_i2c_probe,
1532 	.remove = sgtl5000_i2c_remove,
1533 	.id_table = sgtl5000_id,
1534 };
1535 
1536 module_i2c_driver(sgtl5000_i2c_driver);
1537 
1538 MODULE_DESCRIPTION("Freescale SGTL5000 ALSA SoC Codec Driver");
1539 MODULE_AUTHOR("Zeng Zhaoming <zengzm.kernel@gmail.com>");
1540 MODULE_LICENSE("GPL");
1541