1 /* 2 * sgtl5000.c -- SGTL5000 ALSA SoC Audio driver 3 * 4 * Copyright 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11 #include <linux/module.h> 12 #include <linux/moduleparam.h> 13 #include <linux/init.h> 14 #include <linux/delay.h> 15 #include <linux/slab.h> 16 #include <linux/pm.h> 17 #include <linux/i2c.h> 18 #include <linux/clk.h> 19 #include <linux/log2.h> 20 #include <linux/regmap.h> 21 #include <linux/regulator/driver.h> 22 #include <linux/regulator/machine.h> 23 #include <linux/regulator/consumer.h> 24 #include <linux/of_device.h> 25 #include <sound/core.h> 26 #include <sound/tlv.h> 27 #include <sound/pcm.h> 28 #include <sound/pcm_params.h> 29 #include <sound/soc.h> 30 #include <sound/soc-dapm.h> 31 #include <sound/initval.h> 32 33 #include "sgtl5000.h" 34 35 #define SGTL5000_DAP_REG_OFFSET 0x0100 36 #define SGTL5000_MAX_REG_OFFSET 0x013A 37 38 /* default value of sgtl5000 registers */ 39 static const struct reg_default sgtl5000_reg_defaults[] = { 40 { SGTL5000_CHIP_DIG_POWER, 0x0000 }, 41 { SGTL5000_CHIP_I2S_CTRL, 0x0010 }, 42 { SGTL5000_CHIP_SSS_CTRL, 0x0010 }, 43 { SGTL5000_CHIP_ADCDAC_CTRL, 0x020c }, 44 { SGTL5000_CHIP_DAC_VOL, 0x3c3c }, 45 { SGTL5000_CHIP_PAD_STRENGTH, 0x015f }, 46 { SGTL5000_CHIP_ANA_ADC_CTRL, 0x0000 }, 47 { SGTL5000_CHIP_ANA_HP_CTRL, 0x1818 }, 48 { SGTL5000_CHIP_ANA_CTRL, 0x0111 }, 49 { SGTL5000_CHIP_REF_CTRL, 0x0000 }, 50 { SGTL5000_CHIP_MIC_CTRL, 0x0000 }, 51 { SGTL5000_CHIP_LINE_OUT_CTRL, 0x0000 }, 52 { SGTL5000_CHIP_LINE_OUT_VOL, 0x0404 }, 53 { SGTL5000_CHIP_PLL_CTRL, 0x5000 }, 54 { SGTL5000_CHIP_CLK_TOP_CTRL, 0x0000 }, 55 { SGTL5000_CHIP_ANA_STATUS, 0x0000 }, 56 { SGTL5000_CHIP_SHORT_CTRL, 0x0000 }, 57 { SGTL5000_CHIP_ANA_TEST2, 0x0000 }, 58 { SGTL5000_DAP_CTRL, 0x0000 }, 59 { SGTL5000_DAP_PEQ, 0x0000 }, 60 { SGTL5000_DAP_BASS_ENHANCE, 0x0040 }, 61 { SGTL5000_DAP_BASS_ENHANCE_CTRL, 0x051f }, 62 { SGTL5000_DAP_AUDIO_EQ, 0x0000 }, 63 { SGTL5000_DAP_SURROUND, 0x0040 }, 64 { SGTL5000_DAP_EQ_BASS_BAND0, 0x002f }, 65 { SGTL5000_DAP_EQ_BASS_BAND1, 0x002f }, 66 { SGTL5000_DAP_EQ_BASS_BAND2, 0x002f }, 67 { SGTL5000_DAP_EQ_BASS_BAND3, 0x002f }, 68 { SGTL5000_DAP_EQ_BASS_BAND4, 0x002f }, 69 { SGTL5000_DAP_MAIN_CHAN, 0x8000 }, 70 { SGTL5000_DAP_MIX_CHAN, 0x0000 }, 71 { SGTL5000_DAP_AVC_CTRL, 0x0510 }, 72 { SGTL5000_DAP_AVC_THRESHOLD, 0x1473 }, 73 { SGTL5000_DAP_AVC_ATTACK, 0x0028 }, 74 { SGTL5000_DAP_AVC_DECAY, 0x0050 }, 75 }; 76 77 /* regulator supplies for sgtl5000, VDDD is an optional external supply */ 78 enum sgtl5000_regulator_supplies { 79 VDDA, 80 VDDIO, 81 VDDD, 82 SGTL5000_SUPPLY_NUM 83 }; 84 85 /* vddd is optional supply */ 86 static const char *supply_names[SGTL5000_SUPPLY_NUM] = { 87 "VDDA", 88 "VDDIO", 89 "VDDD" 90 }; 91 92 #define LDO_VOLTAGE 1200000 93 #define LINREG_VDDD ((1600 - LDO_VOLTAGE / 1000) / 50) 94 95 enum sgtl5000_micbias_resistor { 96 SGTL5000_MICBIAS_OFF = 0, 97 SGTL5000_MICBIAS_2K = 2, 98 SGTL5000_MICBIAS_4K = 4, 99 SGTL5000_MICBIAS_8K = 8, 100 }; 101 102 /* sgtl5000 private structure in codec */ 103 struct sgtl5000_priv { 104 int sysclk; /* sysclk rate */ 105 int master; /* i2s master or not */ 106 int fmt; /* i2s data format */ 107 struct regulator_bulk_data supplies[SGTL5000_SUPPLY_NUM]; 108 int num_supplies; 109 struct regmap *regmap; 110 struct clk *mclk; 111 int revision; 112 u8 micbias_resistor; 113 u8 micbias_voltage; 114 }; 115 116 /* 117 * mic_bias power on/off share the same register bits with 118 * output impedance of mic bias, when power on mic bias, we 119 * need reclaim it to impedance value. 120 * 0x0 = Powered off 121 * 0x1 = 2Kohm 122 * 0x2 = 4Kohm 123 * 0x3 = 8Kohm 124 */ 125 static int mic_bias_event(struct snd_soc_dapm_widget *w, 126 struct snd_kcontrol *kcontrol, int event) 127 { 128 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); 129 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); 130 131 switch (event) { 132 case SND_SOC_DAPM_POST_PMU: 133 /* change mic bias resistor */ 134 snd_soc_update_bits(codec, SGTL5000_CHIP_MIC_CTRL, 135 SGTL5000_BIAS_R_MASK, 136 sgtl5000->micbias_resistor << SGTL5000_BIAS_R_SHIFT); 137 break; 138 139 case SND_SOC_DAPM_PRE_PMD: 140 snd_soc_update_bits(codec, SGTL5000_CHIP_MIC_CTRL, 141 SGTL5000_BIAS_R_MASK, 0); 142 break; 143 } 144 return 0; 145 } 146 147 /* 148 * As manual described, ADC/DAC only works when VAG powerup, 149 * So enabled VAG before ADC/DAC up. 150 * In power down case, we need wait 400ms when vag fully ramped down. 151 */ 152 static int power_vag_event(struct snd_soc_dapm_widget *w, 153 struct snd_kcontrol *kcontrol, int event) 154 { 155 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); 156 const u32 mask = SGTL5000_DAC_POWERUP | SGTL5000_ADC_POWERUP; 157 158 switch (event) { 159 case SND_SOC_DAPM_POST_PMU: 160 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER, 161 SGTL5000_VAG_POWERUP, SGTL5000_VAG_POWERUP); 162 msleep(400); 163 break; 164 165 case SND_SOC_DAPM_PRE_PMD: 166 /* 167 * Don't clear VAG_POWERUP, when both DAC and ADC are 168 * operational to prevent inadvertently starving the 169 * other one of them. 170 */ 171 if ((snd_soc_read(codec, SGTL5000_CHIP_ANA_POWER) & 172 mask) != mask) { 173 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER, 174 SGTL5000_VAG_POWERUP, 0); 175 msleep(400); 176 } 177 break; 178 default: 179 break; 180 } 181 182 return 0; 183 } 184 185 /* input sources for ADC */ 186 static const char *adc_mux_text[] = { 187 "MIC_IN", "LINE_IN" 188 }; 189 190 static SOC_ENUM_SINGLE_DECL(adc_enum, 191 SGTL5000_CHIP_ANA_CTRL, 2, 192 adc_mux_text); 193 194 static const struct snd_kcontrol_new adc_mux = 195 SOC_DAPM_ENUM("Capture Mux", adc_enum); 196 197 /* input sources for DAC */ 198 static const char *dac_mux_text[] = { 199 "DAC", "LINE_IN" 200 }; 201 202 static SOC_ENUM_SINGLE_DECL(dac_enum, 203 SGTL5000_CHIP_ANA_CTRL, 6, 204 dac_mux_text); 205 206 static const struct snd_kcontrol_new dac_mux = 207 SOC_DAPM_ENUM("Headphone Mux", dac_enum); 208 209 static const struct snd_soc_dapm_widget sgtl5000_dapm_widgets[] = { 210 SND_SOC_DAPM_INPUT("LINE_IN"), 211 SND_SOC_DAPM_INPUT("MIC_IN"), 212 213 SND_SOC_DAPM_OUTPUT("HP_OUT"), 214 SND_SOC_DAPM_OUTPUT("LINE_OUT"), 215 216 SND_SOC_DAPM_SUPPLY("Mic Bias", SGTL5000_CHIP_MIC_CTRL, 8, 0, 217 mic_bias_event, 218 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 219 220 SND_SOC_DAPM_PGA("HP", SGTL5000_CHIP_ANA_POWER, 4, 0, NULL, 0), 221 SND_SOC_DAPM_PGA("LO", SGTL5000_CHIP_ANA_POWER, 0, 0, NULL, 0), 222 223 SND_SOC_DAPM_MUX("Capture Mux", SND_SOC_NOPM, 0, 0, &adc_mux), 224 SND_SOC_DAPM_MUX("Headphone Mux", SND_SOC_NOPM, 0, 0, &dac_mux), 225 226 /* aif for i2s input */ 227 SND_SOC_DAPM_AIF_IN("AIFIN", "Playback", 228 0, SGTL5000_CHIP_DIG_POWER, 229 0, 0), 230 231 /* aif for i2s output */ 232 SND_SOC_DAPM_AIF_OUT("AIFOUT", "Capture", 233 0, SGTL5000_CHIP_DIG_POWER, 234 1, 0), 235 236 SND_SOC_DAPM_ADC("ADC", "Capture", SGTL5000_CHIP_ANA_POWER, 1, 0), 237 SND_SOC_DAPM_DAC("DAC", "Playback", SGTL5000_CHIP_ANA_POWER, 3, 0), 238 239 SND_SOC_DAPM_PRE("VAG_POWER_PRE", power_vag_event), 240 SND_SOC_DAPM_POST("VAG_POWER_POST", power_vag_event), 241 }; 242 243 /* routes for sgtl5000 */ 244 static const struct snd_soc_dapm_route sgtl5000_dapm_routes[] = { 245 {"Capture Mux", "LINE_IN", "LINE_IN"}, /* line_in --> adc_mux */ 246 {"Capture Mux", "MIC_IN", "MIC_IN"}, /* mic_in --> adc_mux */ 247 248 {"ADC", NULL, "Capture Mux"}, /* adc_mux --> adc */ 249 {"AIFOUT", NULL, "ADC"}, /* adc --> i2s_out */ 250 251 {"DAC", NULL, "AIFIN"}, /* i2s-->dac,skip audio mux */ 252 {"Headphone Mux", "DAC", "DAC"}, /* dac --> hp_mux */ 253 {"LO", NULL, "DAC"}, /* dac --> line_out */ 254 255 {"Headphone Mux", "LINE_IN", "LINE_IN"},/* line_in --> hp_mux */ 256 {"HP", NULL, "Headphone Mux"}, /* hp_mux --> hp */ 257 258 {"LINE_OUT", NULL, "LO"}, 259 {"HP_OUT", NULL, "HP"}, 260 }; 261 262 /* custom function to fetch info of PCM playback volume */ 263 static int dac_info_volsw(struct snd_kcontrol *kcontrol, 264 struct snd_ctl_elem_info *uinfo) 265 { 266 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 267 uinfo->count = 2; 268 uinfo->value.integer.min = 0; 269 uinfo->value.integer.max = 0xfc - 0x3c; 270 return 0; 271 } 272 273 /* 274 * custom function to get of PCM playback volume 275 * 276 * dac volume register 277 * 15-------------8-7--------------0 278 * | R channel vol | L channel vol | 279 * ------------------------------- 280 * 281 * PCM volume with 0.5017 dB steps from 0 to -90 dB 282 * 283 * register values map to dB 284 * 0x3B and less = Reserved 285 * 0x3C = 0 dB 286 * 0x3D = -0.5 dB 287 * 0xF0 = -90 dB 288 * 0xFC and greater = Muted 289 * 290 * register value map to userspace value 291 * 292 * register value 0x3c(0dB) 0xf0(-90dB)0xfc 293 * ------------------------------ 294 * userspace value 0xc0 0 295 */ 296 static int dac_get_volsw(struct snd_kcontrol *kcontrol, 297 struct snd_ctl_elem_value *ucontrol) 298 { 299 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); 300 int reg; 301 int l; 302 int r; 303 304 reg = snd_soc_read(codec, SGTL5000_CHIP_DAC_VOL); 305 306 /* get left channel volume */ 307 l = (reg & SGTL5000_DAC_VOL_LEFT_MASK) >> SGTL5000_DAC_VOL_LEFT_SHIFT; 308 309 /* get right channel volume */ 310 r = (reg & SGTL5000_DAC_VOL_RIGHT_MASK) >> SGTL5000_DAC_VOL_RIGHT_SHIFT; 311 312 /* make sure value fall in (0x3c,0xfc) */ 313 l = clamp(l, 0x3c, 0xfc); 314 r = clamp(r, 0x3c, 0xfc); 315 316 /* invert it and map to userspace value */ 317 l = 0xfc - l; 318 r = 0xfc - r; 319 320 ucontrol->value.integer.value[0] = l; 321 ucontrol->value.integer.value[1] = r; 322 323 return 0; 324 } 325 326 /* 327 * custom function to put of PCM playback volume 328 * 329 * dac volume register 330 * 15-------------8-7--------------0 331 * | R channel vol | L channel vol | 332 * ------------------------------- 333 * 334 * PCM volume with 0.5017 dB steps from 0 to -90 dB 335 * 336 * register values map to dB 337 * 0x3B and less = Reserved 338 * 0x3C = 0 dB 339 * 0x3D = -0.5 dB 340 * 0xF0 = -90 dB 341 * 0xFC and greater = Muted 342 * 343 * userspace value map to register value 344 * 345 * userspace value 0xc0 0 346 * ------------------------------ 347 * register value 0x3c(0dB) 0xf0(-90dB)0xfc 348 */ 349 static int dac_put_volsw(struct snd_kcontrol *kcontrol, 350 struct snd_ctl_elem_value *ucontrol) 351 { 352 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); 353 int reg; 354 int l; 355 int r; 356 357 l = ucontrol->value.integer.value[0]; 358 r = ucontrol->value.integer.value[1]; 359 360 /* make sure userspace volume fall in (0, 0xfc-0x3c) */ 361 l = clamp(l, 0, 0xfc - 0x3c); 362 r = clamp(r, 0, 0xfc - 0x3c); 363 364 /* invert it, get the value can be set to register */ 365 l = 0xfc - l; 366 r = 0xfc - r; 367 368 /* shift to get the register value */ 369 reg = l << SGTL5000_DAC_VOL_LEFT_SHIFT | 370 r << SGTL5000_DAC_VOL_RIGHT_SHIFT; 371 372 snd_soc_write(codec, SGTL5000_CHIP_DAC_VOL, reg); 373 374 return 0; 375 } 376 377 static const DECLARE_TLV_DB_SCALE(capture_6db_attenuate, -600, 600, 0); 378 379 /* tlv for mic gain, 0db 20db 30db 40db */ 380 static const DECLARE_TLV_DB_RANGE(mic_gain_tlv, 381 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0), 382 1, 3, TLV_DB_SCALE_ITEM(2000, 1000, 0) 383 ); 384 385 /* tlv for hp volume, -51.5db to 12.0db, step .5db */ 386 static const DECLARE_TLV_DB_SCALE(headphone_volume, -5150, 50, 0); 387 388 /* tlv for lineout volume, 31 steps of .5db each */ 389 static const DECLARE_TLV_DB_SCALE(lineout_volume, -1550, 50, 0); 390 391 static const struct snd_kcontrol_new sgtl5000_snd_controls[] = { 392 /* SOC_DOUBLE_S8_TLV with invert */ 393 { 394 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 395 .name = "PCM Playback Volume", 396 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ | 397 SNDRV_CTL_ELEM_ACCESS_READWRITE, 398 .info = dac_info_volsw, 399 .get = dac_get_volsw, 400 .put = dac_put_volsw, 401 }, 402 403 SOC_DOUBLE("Capture Volume", SGTL5000_CHIP_ANA_ADC_CTRL, 0, 4, 0xf, 0), 404 SOC_SINGLE_TLV("Capture Attenuate Switch (-6dB)", 405 SGTL5000_CHIP_ANA_ADC_CTRL, 406 8, 1, 0, capture_6db_attenuate), 407 SOC_SINGLE("Capture ZC Switch", SGTL5000_CHIP_ANA_CTRL, 1, 1, 0), 408 409 SOC_DOUBLE_TLV("Headphone Playback Volume", 410 SGTL5000_CHIP_ANA_HP_CTRL, 411 0, 8, 412 0x7f, 1, 413 headphone_volume), 414 SOC_SINGLE("Headphone Playback ZC Switch", SGTL5000_CHIP_ANA_CTRL, 415 5, 1, 0), 416 417 SOC_SINGLE_TLV("Mic Volume", SGTL5000_CHIP_MIC_CTRL, 418 0, 3, 0, mic_gain_tlv), 419 420 SOC_DOUBLE_TLV("Lineout Playback Volume", 421 SGTL5000_CHIP_LINE_OUT_VOL, 422 SGTL5000_LINE_OUT_VOL_LEFT_SHIFT, 423 SGTL5000_LINE_OUT_VOL_RIGHT_SHIFT, 424 0x1f, 1, 425 lineout_volume), 426 }; 427 428 /* mute the codec used by alsa core */ 429 static int sgtl5000_digital_mute(struct snd_soc_dai *codec_dai, int mute) 430 { 431 struct snd_soc_codec *codec = codec_dai->codec; 432 u16 adcdac_ctrl = SGTL5000_DAC_MUTE_LEFT | SGTL5000_DAC_MUTE_RIGHT; 433 434 snd_soc_update_bits(codec, SGTL5000_CHIP_ADCDAC_CTRL, 435 adcdac_ctrl, mute ? adcdac_ctrl : 0); 436 437 return 0; 438 } 439 440 /* set codec format */ 441 static int sgtl5000_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt) 442 { 443 struct snd_soc_codec *codec = codec_dai->codec; 444 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); 445 u16 i2sctl = 0; 446 447 sgtl5000->master = 0; 448 /* 449 * i2s clock and frame master setting. 450 * ONLY support: 451 * - clock and frame slave, 452 * - clock and frame master 453 */ 454 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 455 case SND_SOC_DAIFMT_CBS_CFS: 456 break; 457 case SND_SOC_DAIFMT_CBM_CFM: 458 i2sctl |= SGTL5000_I2S_MASTER; 459 sgtl5000->master = 1; 460 break; 461 default: 462 return -EINVAL; 463 } 464 465 /* setting i2s data format */ 466 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 467 case SND_SOC_DAIFMT_DSP_A: 468 i2sctl |= SGTL5000_I2S_MODE_PCM << SGTL5000_I2S_MODE_SHIFT; 469 break; 470 case SND_SOC_DAIFMT_DSP_B: 471 i2sctl |= SGTL5000_I2S_MODE_PCM << SGTL5000_I2S_MODE_SHIFT; 472 i2sctl |= SGTL5000_I2S_LRALIGN; 473 break; 474 case SND_SOC_DAIFMT_I2S: 475 i2sctl |= SGTL5000_I2S_MODE_I2S_LJ << SGTL5000_I2S_MODE_SHIFT; 476 break; 477 case SND_SOC_DAIFMT_RIGHT_J: 478 i2sctl |= SGTL5000_I2S_MODE_RJ << SGTL5000_I2S_MODE_SHIFT; 479 i2sctl |= SGTL5000_I2S_LRPOL; 480 break; 481 case SND_SOC_DAIFMT_LEFT_J: 482 i2sctl |= SGTL5000_I2S_MODE_I2S_LJ << SGTL5000_I2S_MODE_SHIFT; 483 i2sctl |= SGTL5000_I2S_LRALIGN; 484 break; 485 default: 486 return -EINVAL; 487 } 488 489 sgtl5000->fmt = fmt & SND_SOC_DAIFMT_FORMAT_MASK; 490 491 /* Clock inversion */ 492 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 493 case SND_SOC_DAIFMT_NB_NF: 494 break; 495 case SND_SOC_DAIFMT_IB_NF: 496 i2sctl |= SGTL5000_I2S_SCLK_INV; 497 break; 498 default: 499 return -EINVAL; 500 } 501 502 snd_soc_write(codec, SGTL5000_CHIP_I2S_CTRL, i2sctl); 503 504 return 0; 505 } 506 507 /* set codec sysclk */ 508 static int sgtl5000_set_dai_sysclk(struct snd_soc_dai *codec_dai, 509 int clk_id, unsigned int freq, int dir) 510 { 511 struct snd_soc_codec *codec = codec_dai->codec; 512 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); 513 514 switch (clk_id) { 515 case SGTL5000_SYSCLK: 516 sgtl5000->sysclk = freq; 517 break; 518 default: 519 return -EINVAL; 520 } 521 522 return 0; 523 } 524 525 /* 526 * set clock according to i2s frame clock, 527 * sgtl5000 provides 2 clock sources: 528 * 1. sys_mclk: sample freq can only be configured to 529 * 1/256, 1/384, 1/512 of sys_mclk. 530 * 2. pll: can derive any audio clocks. 531 * 532 * clock setting rules: 533 * 1. in slave mode, only sys_mclk can be used 534 * 2. as constraint by sys_mclk, sample freq should be set to 32 kHz, 44.1 kHz 535 * and above. 536 * 3. usage of sys_mclk is preferred over pll to save power. 537 */ 538 static int sgtl5000_set_clock(struct snd_soc_codec *codec, int frame_rate) 539 { 540 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); 541 int clk_ctl = 0; 542 int sys_fs; /* sample freq */ 543 544 /* 545 * sample freq should be divided by frame clock, 546 * if frame clock is lower than 44.1 kHz, sample freq should be set to 547 * 32 kHz or 44.1 kHz. 548 */ 549 switch (frame_rate) { 550 case 8000: 551 case 16000: 552 sys_fs = 32000; 553 break; 554 case 11025: 555 case 22050: 556 sys_fs = 44100; 557 break; 558 default: 559 sys_fs = frame_rate; 560 break; 561 } 562 563 /* set divided factor of frame clock */ 564 switch (sys_fs / frame_rate) { 565 case 4: 566 clk_ctl |= SGTL5000_RATE_MODE_DIV_4 << SGTL5000_RATE_MODE_SHIFT; 567 break; 568 case 2: 569 clk_ctl |= SGTL5000_RATE_MODE_DIV_2 << SGTL5000_RATE_MODE_SHIFT; 570 break; 571 case 1: 572 clk_ctl |= SGTL5000_RATE_MODE_DIV_1 << SGTL5000_RATE_MODE_SHIFT; 573 break; 574 default: 575 return -EINVAL; 576 } 577 578 /* set the sys_fs according to frame rate */ 579 switch (sys_fs) { 580 case 32000: 581 clk_ctl |= SGTL5000_SYS_FS_32k << SGTL5000_SYS_FS_SHIFT; 582 break; 583 case 44100: 584 clk_ctl |= SGTL5000_SYS_FS_44_1k << SGTL5000_SYS_FS_SHIFT; 585 break; 586 case 48000: 587 clk_ctl |= SGTL5000_SYS_FS_48k << SGTL5000_SYS_FS_SHIFT; 588 break; 589 case 96000: 590 clk_ctl |= SGTL5000_SYS_FS_96k << SGTL5000_SYS_FS_SHIFT; 591 break; 592 default: 593 dev_err(codec->dev, "frame rate %d not supported\n", 594 frame_rate); 595 return -EINVAL; 596 } 597 598 /* 599 * calculate the divider of mclk/sample_freq, 600 * factor of freq = 96 kHz can only be 256, since mclk is in the range 601 * of 8 MHz - 27 MHz 602 */ 603 switch (sgtl5000->sysclk / frame_rate) { 604 case 256: 605 clk_ctl |= SGTL5000_MCLK_FREQ_256FS << 606 SGTL5000_MCLK_FREQ_SHIFT; 607 break; 608 case 384: 609 clk_ctl |= SGTL5000_MCLK_FREQ_384FS << 610 SGTL5000_MCLK_FREQ_SHIFT; 611 break; 612 case 512: 613 clk_ctl |= SGTL5000_MCLK_FREQ_512FS << 614 SGTL5000_MCLK_FREQ_SHIFT; 615 break; 616 default: 617 /* if mclk does not satisfy the divider, use pll */ 618 if (sgtl5000->master) { 619 clk_ctl |= SGTL5000_MCLK_FREQ_PLL << 620 SGTL5000_MCLK_FREQ_SHIFT; 621 } else { 622 dev_err(codec->dev, 623 "PLL not supported in slave mode\n"); 624 dev_err(codec->dev, "%d ratio is not supported. " 625 "SYS_MCLK needs to be 256, 384 or 512 * fs\n", 626 sgtl5000->sysclk / frame_rate); 627 return -EINVAL; 628 } 629 } 630 631 /* if using pll, please check manual 6.4.2 for detail */ 632 if ((clk_ctl & SGTL5000_MCLK_FREQ_MASK) == SGTL5000_MCLK_FREQ_PLL) { 633 u64 out, t; 634 int div2; 635 int pll_ctl; 636 unsigned int in, int_div, frac_div; 637 638 if (sgtl5000->sysclk > 17000000) { 639 div2 = 1; 640 in = sgtl5000->sysclk / 2; 641 } else { 642 div2 = 0; 643 in = sgtl5000->sysclk; 644 } 645 if (sys_fs == 44100) 646 out = 180633600; 647 else 648 out = 196608000; 649 t = do_div(out, in); 650 int_div = out; 651 t *= 2048; 652 do_div(t, in); 653 frac_div = t; 654 pll_ctl = int_div << SGTL5000_PLL_INT_DIV_SHIFT | 655 frac_div << SGTL5000_PLL_FRAC_DIV_SHIFT; 656 657 snd_soc_write(codec, SGTL5000_CHIP_PLL_CTRL, pll_ctl); 658 if (div2) 659 snd_soc_update_bits(codec, 660 SGTL5000_CHIP_CLK_TOP_CTRL, 661 SGTL5000_INPUT_FREQ_DIV2, 662 SGTL5000_INPUT_FREQ_DIV2); 663 else 664 snd_soc_update_bits(codec, 665 SGTL5000_CHIP_CLK_TOP_CTRL, 666 SGTL5000_INPUT_FREQ_DIV2, 667 0); 668 669 /* power up pll */ 670 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER, 671 SGTL5000_PLL_POWERUP | SGTL5000_VCOAMP_POWERUP, 672 SGTL5000_PLL_POWERUP | SGTL5000_VCOAMP_POWERUP); 673 674 /* if using pll, clk_ctrl must be set after pll power up */ 675 snd_soc_write(codec, SGTL5000_CHIP_CLK_CTRL, clk_ctl); 676 } else { 677 /* otherwise, clk_ctrl must be set before pll power down */ 678 snd_soc_write(codec, SGTL5000_CHIP_CLK_CTRL, clk_ctl); 679 680 /* power down pll */ 681 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER, 682 SGTL5000_PLL_POWERUP | SGTL5000_VCOAMP_POWERUP, 683 0); 684 } 685 686 return 0; 687 } 688 689 /* 690 * Set PCM DAI bit size and sample rate. 691 * input: params_rate, params_fmt 692 */ 693 static int sgtl5000_pcm_hw_params(struct snd_pcm_substream *substream, 694 struct snd_pcm_hw_params *params, 695 struct snd_soc_dai *dai) 696 { 697 struct snd_soc_codec *codec = dai->codec; 698 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); 699 int channels = params_channels(params); 700 int i2s_ctl = 0; 701 int stereo; 702 int ret; 703 704 /* sysclk should already set */ 705 if (!sgtl5000->sysclk) { 706 dev_err(codec->dev, "%s: set sysclk first!\n", __func__); 707 return -EFAULT; 708 } 709 710 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 711 stereo = SGTL5000_DAC_STEREO; 712 else 713 stereo = SGTL5000_ADC_STEREO; 714 715 /* set mono to save power */ 716 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER, stereo, 717 channels == 1 ? 0 : stereo); 718 719 /* set codec clock base on lrclk */ 720 ret = sgtl5000_set_clock(codec, params_rate(params)); 721 if (ret) 722 return ret; 723 724 /* set i2s data format */ 725 switch (params_width(params)) { 726 case 16: 727 if (sgtl5000->fmt == SND_SOC_DAIFMT_RIGHT_J) 728 return -EINVAL; 729 i2s_ctl |= SGTL5000_I2S_DLEN_16 << SGTL5000_I2S_DLEN_SHIFT; 730 i2s_ctl |= SGTL5000_I2S_SCLKFREQ_32FS << 731 SGTL5000_I2S_SCLKFREQ_SHIFT; 732 break; 733 case 20: 734 i2s_ctl |= SGTL5000_I2S_DLEN_20 << SGTL5000_I2S_DLEN_SHIFT; 735 i2s_ctl |= SGTL5000_I2S_SCLKFREQ_64FS << 736 SGTL5000_I2S_SCLKFREQ_SHIFT; 737 break; 738 case 24: 739 i2s_ctl |= SGTL5000_I2S_DLEN_24 << SGTL5000_I2S_DLEN_SHIFT; 740 i2s_ctl |= SGTL5000_I2S_SCLKFREQ_64FS << 741 SGTL5000_I2S_SCLKFREQ_SHIFT; 742 break; 743 case 32: 744 if (sgtl5000->fmt == SND_SOC_DAIFMT_RIGHT_J) 745 return -EINVAL; 746 i2s_ctl |= SGTL5000_I2S_DLEN_32 << SGTL5000_I2S_DLEN_SHIFT; 747 i2s_ctl |= SGTL5000_I2S_SCLKFREQ_64FS << 748 SGTL5000_I2S_SCLKFREQ_SHIFT; 749 break; 750 default: 751 return -EINVAL; 752 } 753 754 snd_soc_update_bits(codec, SGTL5000_CHIP_I2S_CTRL, 755 SGTL5000_I2S_DLEN_MASK | SGTL5000_I2S_SCLKFREQ_MASK, 756 i2s_ctl); 757 758 return 0; 759 } 760 761 /* 762 * set dac bias 763 * common state changes: 764 * startup: 765 * off --> standby --> prepare --> on 766 * standby --> prepare --> on 767 * 768 * stop: 769 * on --> prepare --> standby 770 */ 771 static int sgtl5000_set_bias_level(struct snd_soc_codec *codec, 772 enum snd_soc_bias_level level) 773 { 774 switch (level) { 775 case SND_SOC_BIAS_ON: 776 case SND_SOC_BIAS_PREPARE: 777 case SND_SOC_BIAS_STANDBY: 778 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER, 779 SGTL5000_REFTOP_POWERUP, 780 SGTL5000_REFTOP_POWERUP); 781 break; 782 case SND_SOC_BIAS_OFF: 783 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER, 784 SGTL5000_REFTOP_POWERUP, 0); 785 break; 786 } 787 788 return 0; 789 } 790 791 #define SGTL5000_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ 792 SNDRV_PCM_FMTBIT_S20_3LE |\ 793 SNDRV_PCM_FMTBIT_S24_LE |\ 794 SNDRV_PCM_FMTBIT_S32_LE) 795 796 static const struct snd_soc_dai_ops sgtl5000_ops = { 797 .hw_params = sgtl5000_pcm_hw_params, 798 .digital_mute = sgtl5000_digital_mute, 799 .set_fmt = sgtl5000_set_dai_fmt, 800 .set_sysclk = sgtl5000_set_dai_sysclk, 801 }; 802 803 static struct snd_soc_dai_driver sgtl5000_dai = { 804 .name = "sgtl5000", 805 .playback = { 806 .stream_name = "Playback", 807 .channels_min = 1, 808 .channels_max = 2, 809 /* 810 * only support 8~48K + 96K, 811 * TODO modify hw_param to support more 812 */ 813 .rates = SNDRV_PCM_RATE_8000_48000 | SNDRV_PCM_RATE_96000, 814 .formats = SGTL5000_FORMATS, 815 }, 816 .capture = { 817 .stream_name = "Capture", 818 .channels_min = 1, 819 .channels_max = 2, 820 .rates = SNDRV_PCM_RATE_8000_48000 | SNDRV_PCM_RATE_96000, 821 .formats = SGTL5000_FORMATS, 822 }, 823 .ops = &sgtl5000_ops, 824 .symmetric_rates = 1, 825 }; 826 827 static bool sgtl5000_volatile(struct device *dev, unsigned int reg) 828 { 829 switch (reg) { 830 case SGTL5000_CHIP_ID: 831 case SGTL5000_CHIP_ADCDAC_CTRL: 832 case SGTL5000_CHIP_ANA_STATUS: 833 return true; 834 } 835 836 return false; 837 } 838 839 static bool sgtl5000_readable(struct device *dev, unsigned int reg) 840 { 841 switch (reg) { 842 case SGTL5000_CHIP_ID: 843 case SGTL5000_CHIP_DIG_POWER: 844 case SGTL5000_CHIP_CLK_CTRL: 845 case SGTL5000_CHIP_I2S_CTRL: 846 case SGTL5000_CHIP_SSS_CTRL: 847 case SGTL5000_CHIP_ADCDAC_CTRL: 848 case SGTL5000_CHIP_DAC_VOL: 849 case SGTL5000_CHIP_PAD_STRENGTH: 850 case SGTL5000_CHIP_ANA_ADC_CTRL: 851 case SGTL5000_CHIP_ANA_HP_CTRL: 852 case SGTL5000_CHIP_ANA_CTRL: 853 case SGTL5000_CHIP_LINREG_CTRL: 854 case SGTL5000_CHIP_REF_CTRL: 855 case SGTL5000_CHIP_MIC_CTRL: 856 case SGTL5000_CHIP_LINE_OUT_CTRL: 857 case SGTL5000_CHIP_LINE_OUT_VOL: 858 case SGTL5000_CHIP_ANA_POWER: 859 case SGTL5000_CHIP_PLL_CTRL: 860 case SGTL5000_CHIP_CLK_TOP_CTRL: 861 case SGTL5000_CHIP_ANA_STATUS: 862 case SGTL5000_CHIP_SHORT_CTRL: 863 case SGTL5000_CHIP_ANA_TEST2: 864 case SGTL5000_DAP_CTRL: 865 case SGTL5000_DAP_PEQ: 866 case SGTL5000_DAP_BASS_ENHANCE: 867 case SGTL5000_DAP_BASS_ENHANCE_CTRL: 868 case SGTL5000_DAP_AUDIO_EQ: 869 case SGTL5000_DAP_SURROUND: 870 case SGTL5000_DAP_FLT_COEF_ACCESS: 871 case SGTL5000_DAP_COEF_WR_B0_MSB: 872 case SGTL5000_DAP_COEF_WR_B0_LSB: 873 case SGTL5000_DAP_EQ_BASS_BAND0: 874 case SGTL5000_DAP_EQ_BASS_BAND1: 875 case SGTL5000_DAP_EQ_BASS_BAND2: 876 case SGTL5000_DAP_EQ_BASS_BAND3: 877 case SGTL5000_DAP_EQ_BASS_BAND4: 878 case SGTL5000_DAP_MAIN_CHAN: 879 case SGTL5000_DAP_MIX_CHAN: 880 case SGTL5000_DAP_AVC_CTRL: 881 case SGTL5000_DAP_AVC_THRESHOLD: 882 case SGTL5000_DAP_AVC_ATTACK: 883 case SGTL5000_DAP_AVC_DECAY: 884 case SGTL5000_DAP_COEF_WR_B1_MSB: 885 case SGTL5000_DAP_COEF_WR_B1_LSB: 886 case SGTL5000_DAP_COEF_WR_B2_MSB: 887 case SGTL5000_DAP_COEF_WR_B2_LSB: 888 case SGTL5000_DAP_COEF_WR_A1_MSB: 889 case SGTL5000_DAP_COEF_WR_A1_LSB: 890 case SGTL5000_DAP_COEF_WR_A2_MSB: 891 case SGTL5000_DAP_COEF_WR_A2_LSB: 892 return true; 893 894 default: 895 return false; 896 } 897 } 898 899 /* 900 * This precalculated table contains all (vag_val * 100 / lo_calcntrl) results 901 * to select an appropriate lo_vol_* in SGTL5000_CHIP_LINE_OUT_VOL 902 * The calculatation was done for all possible register values which 903 * is the array index and the following formula: 10^((idx−15)/40) * 100 904 */ 905 static const u8 vol_quot_table[] = { 906 42, 45, 47, 50, 53, 56, 60, 63, 907 67, 71, 75, 79, 84, 89, 94, 100, 908 106, 112, 119, 126, 133, 141, 150, 158, 909 168, 178, 188, 200, 211, 224, 237, 251 910 }; 911 912 /* 913 * sgtl5000 has 3 internal power supplies: 914 * 1. VAG, normally set to vdda/2 915 * 2. charge pump, set to different value 916 * according to voltage of vdda and vddio 917 * 3. line out VAG, normally set to vddio/2 918 * 919 * and should be set according to: 920 * 1. vddd provided by external or not 921 * 2. vdda and vddio voltage value. > 3.1v or not 922 */ 923 static int sgtl5000_set_power_regs(struct snd_soc_codec *codec) 924 { 925 int vddd; 926 int vdda; 927 int vddio; 928 u16 ana_pwr; 929 u16 lreg_ctrl; 930 int vag; 931 int lo_vag; 932 int vol_quot; 933 int lo_vol; 934 size_t i; 935 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); 936 937 vdda = regulator_get_voltage(sgtl5000->supplies[VDDA].consumer); 938 vddio = regulator_get_voltage(sgtl5000->supplies[VDDIO].consumer); 939 vddd = (sgtl5000->num_supplies > VDDD) 940 ? regulator_get_voltage(sgtl5000->supplies[VDDD].consumer) 941 : LDO_VOLTAGE; 942 943 vdda = vdda / 1000; 944 vddio = vddio / 1000; 945 vddd = vddd / 1000; 946 947 if (vdda <= 0 || vddio <= 0 || vddd < 0) { 948 dev_err(codec->dev, "regulator voltage not set correctly\n"); 949 950 return -EINVAL; 951 } 952 953 /* according to datasheet, maximum voltage of supplies */ 954 if (vdda > 3600 || vddio > 3600 || vddd > 1980) { 955 dev_err(codec->dev, 956 "exceed max voltage vdda %dmV vddio %dmV vddd %dmV\n", 957 vdda, vddio, vddd); 958 959 return -EINVAL; 960 } 961 962 /* reset value */ 963 ana_pwr = snd_soc_read(codec, SGTL5000_CHIP_ANA_POWER); 964 ana_pwr |= SGTL5000_DAC_STEREO | 965 SGTL5000_ADC_STEREO | 966 SGTL5000_REFTOP_POWERUP; 967 lreg_ctrl = snd_soc_read(codec, SGTL5000_CHIP_LINREG_CTRL); 968 969 if (vddio < 3100 && vdda < 3100) { 970 /* enable internal oscillator used for charge pump */ 971 snd_soc_update_bits(codec, SGTL5000_CHIP_CLK_TOP_CTRL, 972 SGTL5000_INT_OSC_EN, 973 SGTL5000_INT_OSC_EN); 974 /* Enable VDDC charge pump */ 975 ana_pwr |= SGTL5000_VDDC_CHRGPMP_POWERUP; 976 } else if (vddio >= 3100 && vdda >= 3100) { 977 ana_pwr &= ~SGTL5000_VDDC_CHRGPMP_POWERUP; 978 /* VDDC use VDDIO rail */ 979 lreg_ctrl |= SGTL5000_VDDC_ASSN_OVRD; 980 lreg_ctrl |= SGTL5000_VDDC_MAN_ASSN_VDDIO << 981 SGTL5000_VDDC_MAN_ASSN_SHIFT; 982 } 983 984 snd_soc_write(codec, SGTL5000_CHIP_LINREG_CTRL, lreg_ctrl); 985 986 snd_soc_write(codec, SGTL5000_CHIP_ANA_POWER, ana_pwr); 987 988 /* 989 * set ADC/DAC VAG to vdda / 2, 990 * should stay in range (0.8v, 1.575v) 991 */ 992 vag = vdda / 2; 993 if (vag <= SGTL5000_ANA_GND_BASE) 994 vag = 0; 995 else if (vag >= SGTL5000_ANA_GND_BASE + SGTL5000_ANA_GND_STP * 996 (SGTL5000_ANA_GND_MASK >> SGTL5000_ANA_GND_SHIFT)) 997 vag = SGTL5000_ANA_GND_MASK >> SGTL5000_ANA_GND_SHIFT; 998 else 999 vag = (vag - SGTL5000_ANA_GND_BASE) / SGTL5000_ANA_GND_STP; 1000 1001 snd_soc_update_bits(codec, SGTL5000_CHIP_REF_CTRL, 1002 SGTL5000_ANA_GND_MASK, vag << SGTL5000_ANA_GND_SHIFT); 1003 1004 /* set line out VAG to vddio / 2, in range (0.8v, 1.675v) */ 1005 lo_vag = vddio / 2; 1006 if (lo_vag <= SGTL5000_LINE_OUT_GND_BASE) 1007 lo_vag = 0; 1008 else if (lo_vag >= SGTL5000_LINE_OUT_GND_BASE + 1009 SGTL5000_LINE_OUT_GND_STP * SGTL5000_LINE_OUT_GND_MAX) 1010 lo_vag = SGTL5000_LINE_OUT_GND_MAX; 1011 else 1012 lo_vag = (lo_vag - SGTL5000_LINE_OUT_GND_BASE) / 1013 SGTL5000_LINE_OUT_GND_STP; 1014 1015 snd_soc_update_bits(codec, SGTL5000_CHIP_LINE_OUT_CTRL, 1016 SGTL5000_LINE_OUT_CURRENT_MASK | 1017 SGTL5000_LINE_OUT_GND_MASK, 1018 lo_vag << SGTL5000_LINE_OUT_GND_SHIFT | 1019 SGTL5000_LINE_OUT_CURRENT_360u << 1020 SGTL5000_LINE_OUT_CURRENT_SHIFT); 1021 1022 /* 1023 * Set lineout output level in range (0..31) 1024 * the same value is used for right and left channel 1025 * 1026 * Searching for a suitable index solving this formula: 1027 * idx = 40 * log10(vag_val / lo_cagcntrl) + 15 1028 */ 1029 vol_quot = (vag * 100) / lo_vag; 1030 lo_vol = 0; 1031 for (i = 0; i < ARRAY_SIZE(vol_quot_table); i++) { 1032 if (vol_quot >= vol_quot_table[i]) 1033 lo_vol = i; 1034 else 1035 break; 1036 } 1037 1038 snd_soc_update_bits(codec, SGTL5000_CHIP_LINE_OUT_VOL, 1039 SGTL5000_LINE_OUT_VOL_RIGHT_MASK | 1040 SGTL5000_LINE_OUT_VOL_LEFT_MASK, 1041 lo_vol << SGTL5000_LINE_OUT_VOL_RIGHT_SHIFT | 1042 lo_vol << SGTL5000_LINE_OUT_VOL_LEFT_SHIFT); 1043 1044 return 0; 1045 } 1046 1047 static int sgtl5000_enable_regulators(struct i2c_client *client) 1048 { 1049 int ret; 1050 int i; 1051 int external_vddd = 0; 1052 struct regulator *vddd; 1053 struct sgtl5000_priv *sgtl5000 = i2c_get_clientdata(client); 1054 1055 for (i = 0; i < ARRAY_SIZE(sgtl5000->supplies); i++) 1056 sgtl5000->supplies[i].supply = supply_names[i]; 1057 1058 vddd = regulator_get_optional(&client->dev, "VDDD"); 1059 if (IS_ERR(vddd)) { 1060 /* See if it's just not registered yet */ 1061 if (PTR_ERR(vddd) == -EPROBE_DEFER) 1062 return -EPROBE_DEFER; 1063 } else { 1064 external_vddd = 1; 1065 regulator_put(vddd); 1066 } 1067 1068 sgtl5000->num_supplies = ARRAY_SIZE(sgtl5000->supplies) 1069 - 1 + external_vddd; 1070 ret = regulator_bulk_get(&client->dev, sgtl5000->num_supplies, 1071 sgtl5000->supplies); 1072 if (ret) 1073 return ret; 1074 1075 ret = regulator_bulk_enable(sgtl5000->num_supplies, 1076 sgtl5000->supplies); 1077 if (!ret) 1078 usleep_range(10, 20); 1079 else 1080 regulator_bulk_free(sgtl5000->num_supplies, 1081 sgtl5000->supplies); 1082 1083 return ret; 1084 } 1085 1086 static int sgtl5000_probe(struct snd_soc_codec *codec) 1087 { 1088 int ret; 1089 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); 1090 1091 /* power up sgtl5000 */ 1092 ret = sgtl5000_set_power_regs(codec); 1093 if (ret) 1094 goto err; 1095 1096 /* enable small pop, introduce 400ms delay in turning off */ 1097 snd_soc_update_bits(codec, SGTL5000_CHIP_REF_CTRL, 1098 SGTL5000_SMALL_POP, 1); 1099 1100 /* disable short cut detector */ 1101 snd_soc_write(codec, SGTL5000_CHIP_SHORT_CTRL, 0); 1102 1103 /* 1104 * set i2s as default input of sound switch 1105 * TODO: add sound switch to control and dapm widge. 1106 */ 1107 snd_soc_write(codec, SGTL5000_CHIP_SSS_CTRL, 1108 SGTL5000_DAC_SEL_I2S_IN << SGTL5000_DAC_SEL_SHIFT); 1109 snd_soc_write(codec, SGTL5000_CHIP_DIG_POWER, 1110 SGTL5000_ADC_EN | SGTL5000_DAC_EN); 1111 1112 /* enable dac volume ramp by default */ 1113 snd_soc_write(codec, SGTL5000_CHIP_ADCDAC_CTRL, 1114 SGTL5000_DAC_VOL_RAMP_EN | 1115 SGTL5000_DAC_MUTE_RIGHT | 1116 SGTL5000_DAC_MUTE_LEFT); 1117 1118 snd_soc_write(codec, SGTL5000_CHIP_PAD_STRENGTH, 0x015f); 1119 1120 snd_soc_write(codec, SGTL5000_CHIP_ANA_CTRL, 1121 SGTL5000_HP_ZCD_EN | 1122 SGTL5000_ADC_ZCD_EN); 1123 1124 snd_soc_update_bits(codec, SGTL5000_CHIP_MIC_CTRL, 1125 SGTL5000_BIAS_R_MASK, 1126 sgtl5000->micbias_resistor << SGTL5000_BIAS_R_SHIFT); 1127 1128 snd_soc_update_bits(codec, SGTL5000_CHIP_MIC_CTRL, 1129 SGTL5000_BIAS_VOLT_MASK, 1130 sgtl5000->micbias_voltage << SGTL5000_BIAS_VOLT_SHIFT); 1131 /* 1132 * disable DAP 1133 * TODO: 1134 * Enable DAP in kcontrol and dapm. 1135 */ 1136 snd_soc_write(codec, SGTL5000_DAP_CTRL, 0); 1137 1138 return 0; 1139 1140 err: 1141 return ret; 1142 } 1143 1144 static int sgtl5000_remove(struct snd_soc_codec *codec) 1145 { 1146 return 0; 1147 } 1148 1149 static struct snd_soc_codec_driver sgtl5000_driver = { 1150 .probe = sgtl5000_probe, 1151 .remove = sgtl5000_remove, 1152 .set_bias_level = sgtl5000_set_bias_level, 1153 .suspend_bias_off = true, 1154 .controls = sgtl5000_snd_controls, 1155 .num_controls = ARRAY_SIZE(sgtl5000_snd_controls), 1156 .dapm_widgets = sgtl5000_dapm_widgets, 1157 .num_dapm_widgets = ARRAY_SIZE(sgtl5000_dapm_widgets), 1158 .dapm_routes = sgtl5000_dapm_routes, 1159 .num_dapm_routes = ARRAY_SIZE(sgtl5000_dapm_routes), 1160 }; 1161 1162 static const struct regmap_config sgtl5000_regmap = { 1163 .reg_bits = 16, 1164 .val_bits = 16, 1165 .reg_stride = 2, 1166 1167 .max_register = SGTL5000_MAX_REG_OFFSET, 1168 .volatile_reg = sgtl5000_volatile, 1169 .readable_reg = sgtl5000_readable, 1170 1171 .cache_type = REGCACHE_RBTREE, 1172 .reg_defaults = sgtl5000_reg_defaults, 1173 .num_reg_defaults = ARRAY_SIZE(sgtl5000_reg_defaults), 1174 }; 1175 1176 /* 1177 * Write all the default values from sgtl5000_reg_defaults[] array into the 1178 * sgtl5000 registers, to make sure we always start with the sane registers 1179 * values as stated in the datasheet. 1180 * 1181 * Since sgtl5000 does not have a reset line, nor a reset command in software, 1182 * we follow this approach to guarantee we always start from the default values 1183 * and avoid problems like, not being able to probe after an audio playback 1184 * followed by a system reset or a 'reboot' command in Linux 1185 */ 1186 static void sgtl5000_fill_defaults(struct i2c_client *client) 1187 { 1188 struct sgtl5000_priv *sgtl5000 = i2c_get_clientdata(client); 1189 int i, ret, val, index; 1190 1191 for (i = 0; i < ARRAY_SIZE(sgtl5000_reg_defaults); i++) { 1192 val = sgtl5000_reg_defaults[i].def; 1193 index = sgtl5000_reg_defaults[i].reg; 1194 ret = regmap_write(sgtl5000->regmap, index, val); 1195 if (ret) 1196 dev_err(&client->dev, 1197 "%s: error %d setting reg 0x%02x to 0x%04x\n", 1198 __func__, ret, index, val); 1199 } 1200 } 1201 1202 static int sgtl5000_i2c_probe(struct i2c_client *client, 1203 const struct i2c_device_id *id) 1204 { 1205 struct sgtl5000_priv *sgtl5000; 1206 int ret, reg, rev; 1207 struct device_node *np = client->dev.of_node; 1208 u32 value; 1209 u16 ana_pwr; 1210 1211 sgtl5000 = devm_kzalloc(&client->dev, sizeof(*sgtl5000), GFP_KERNEL); 1212 if (!sgtl5000) 1213 return -ENOMEM; 1214 1215 i2c_set_clientdata(client, sgtl5000); 1216 1217 ret = sgtl5000_enable_regulators(client); 1218 if (ret) 1219 return ret; 1220 1221 sgtl5000->regmap = devm_regmap_init_i2c(client, &sgtl5000_regmap); 1222 if (IS_ERR(sgtl5000->regmap)) { 1223 ret = PTR_ERR(sgtl5000->regmap); 1224 dev_err(&client->dev, "Failed to allocate regmap: %d\n", ret); 1225 goto disable_regs; 1226 } 1227 1228 sgtl5000->mclk = devm_clk_get(&client->dev, NULL); 1229 if (IS_ERR(sgtl5000->mclk)) { 1230 ret = PTR_ERR(sgtl5000->mclk); 1231 dev_err(&client->dev, "Failed to get mclock: %d\n", ret); 1232 /* Defer the probe to see if the clk will be provided later */ 1233 if (ret == -ENOENT) 1234 ret = -EPROBE_DEFER; 1235 goto disable_regs; 1236 } 1237 1238 ret = clk_prepare_enable(sgtl5000->mclk); 1239 if (ret) { 1240 dev_err(&client->dev, "Error enabling clock %d\n", ret); 1241 goto disable_regs; 1242 } 1243 1244 /* Need 8 clocks before I2C accesses */ 1245 udelay(1); 1246 1247 /* read chip information */ 1248 ret = regmap_read(sgtl5000->regmap, SGTL5000_CHIP_ID, ®); 1249 if (ret) { 1250 dev_err(&client->dev, "Error reading chip id %d\n", ret); 1251 goto disable_clk; 1252 } 1253 1254 if (((reg & SGTL5000_PARTID_MASK) >> SGTL5000_PARTID_SHIFT) != 1255 SGTL5000_PARTID_PART_ID) { 1256 dev_err(&client->dev, 1257 "Device with ID register %x is not a sgtl5000\n", reg); 1258 ret = -ENODEV; 1259 goto disable_clk; 1260 } 1261 1262 rev = (reg & SGTL5000_REVID_MASK) >> SGTL5000_REVID_SHIFT; 1263 dev_info(&client->dev, "sgtl5000 revision 0x%x\n", rev); 1264 sgtl5000->revision = rev; 1265 1266 /* reconfigure the clocks in case we're using the PLL */ 1267 ret = regmap_write(sgtl5000->regmap, 1268 SGTL5000_CHIP_CLK_CTRL, 1269 SGTL5000_CHIP_CLK_CTRL_DEFAULT); 1270 if (ret) 1271 dev_err(&client->dev, 1272 "Error %d initializing CHIP_CLK_CTRL\n", ret); 1273 1274 /* Follow section 2.2.1.1 of AN3663 */ 1275 ana_pwr = SGTL5000_ANA_POWER_DEFAULT; 1276 if (sgtl5000->num_supplies <= VDDD) { 1277 /* internal VDDD at 1.2V */ 1278 ret = regmap_update_bits(sgtl5000->regmap, 1279 SGTL5000_CHIP_LINREG_CTRL, 1280 SGTL5000_LINREG_VDDD_MASK, 1281 LINREG_VDDD); 1282 if (ret) 1283 dev_err(&client->dev, 1284 "Error %d setting LINREG_VDDD\n", ret); 1285 1286 ana_pwr |= SGTL5000_LINEREG_D_POWERUP; 1287 dev_info(&client->dev, 1288 "Using internal LDO instead of VDDD: check ER1\n"); 1289 } else { 1290 /* using external LDO for VDDD 1291 * Clear startup powerup and simple powerup 1292 * bits to save power 1293 */ 1294 ana_pwr &= ~(SGTL5000_STARTUP_POWERUP 1295 | SGTL5000_LINREG_SIMPLE_POWERUP); 1296 dev_dbg(&client->dev, "Using external VDDD\n"); 1297 } 1298 ret = regmap_write(sgtl5000->regmap, SGTL5000_CHIP_ANA_POWER, ana_pwr); 1299 if (ret) 1300 dev_err(&client->dev, 1301 "Error %d setting CHIP_ANA_POWER to %04x\n", 1302 ret, ana_pwr); 1303 1304 if (np) { 1305 if (!of_property_read_u32(np, 1306 "micbias-resistor-k-ohms", &value)) { 1307 switch (value) { 1308 case SGTL5000_MICBIAS_OFF: 1309 sgtl5000->micbias_resistor = 0; 1310 break; 1311 case SGTL5000_MICBIAS_2K: 1312 sgtl5000->micbias_resistor = 1; 1313 break; 1314 case SGTL5000_MICBIAS_4K: 1315 sgtl5000->micbias_resistor = 2; 1316 break; 1317 case SGTL5000_MICBIAS_8K: 1318 sgtl5000->micbias_resistor = 3; 1319 break; 1320 default: 1321 sgtl5000->micbias_resistor = 2; 1322 dev_err(&client->dev, 1323 "Unsuitable MicBias resistor\n"); 1324 } 1325 } else { 1326 /* default is 4Kohms */ 1327 sgtl5000->micbias_resistor = 2; 1328 } 1329 if (!of_property_read_u32(np, 1330 "micbias-voltage-m-volts", &value)) { 1331 /* 1250mV => 0 */ 1332 /* steps of 250mV */ 1333 if ((value >= 1250) && (value <= 3000)) 1334 sgtl5000->micbias_voltage = (value / 250) - 5; 1335 else { 1336 sgtl5000->micbias_voltage = 0; 1337 dev_err(&client->dev, 1338 "Unsuitable MicBias voltage\n"); 1339 } 1340 } else { 1341 sgtl5000->micbias_voltage = 0; 1342 } 1343 } 1344 1345 /* Ensure sgtl5000 will start with sane register values */ 1346 sgtl5000_fill_defaults(client); 1347 1348 ret = snd_soc_register_codec(&client->dev, 1349 &sgtl5000_driver, &sgtl5000_dai, 1); 1350 if (ret) 1351 goto disable_clk; 1352 1353 return 0; 1354 1355 disable_clk: 1356 clk_disable_unprepare(sgtl5000->mclk); 1357 1358 disable_regs: 1359 regulator_bulk_disable(sgtl5000->num_supplies, sgtl5000->supplies); 1360 regulator_bulk_free(sgtl5000->num_supplies, sgtl5000->supplies); 1361 1362 return ret; 1363 } 1364 1365 static int sgtl5000_i2c_remove(struct i2c_client *client) 1366 { 1367 struct sgtl5000_priv *sgtl5000 = i2c_get_clientdata(client); 1368 1369 snd_soc_unregister_codec(&client->dev); 1370 clk_disable_unprepare(sgtl5000->mclk); 1371 regulator_bulk_disable(sgtl5000->num_supplies, sgtl5000->supplies); 1372 regulator_bulk_free(sgtl5000->num_supplies, sgtl5000->supplies); 1373 1374 return 0; 1375 } 1376 1377 static const struct i2c_device_id sgtl5000_id[] = { 1378 {"sgtl5000", 0}, 1379 {}, 1380 }; 1381 1382 MODULE_DEVICE_TABLE(i2c, sgtl5000_id); 1383 1384 static const struct of_device_id sgtl5000_dt_ids[] = { 1385 { .compatible = "fsl,sgtl5000", }, 1386 { /* sentinel */ } 1387 }; 1388 MODULE_DEVICE_TABLE(of, sgtl5000_dt_ids); 1389 1390 static struct i2c_driver sgtl5000_i2c_driver = { 1391 .driver = { 1392 .name = "sgtl5000", 1393 .of_match_table = sgtl5000_dt_ids, 1394 }, 1395 .probe = sgtl5000_i2c_probe, 1396 .remove = sgtl5000_i2c_remove, 1397 .id_table = sgtl5000_id, 1398 }; 1399 1400 module_i2c_driver(sgtl5000_i2c_driver); 1401 1402 MODULE_DESCRIPTION("Freescale SGTL5000 ALSA SoC Codec Driver"); 1403 MODULE_AUTHOR("Zeng Zhaoming <zengzm.kernel@gmail.com>"); 1404 MODULE_LICENSE("GPL"); 1405