1 /* 2 * sgtl5000.c -- SGTL5000 ALSA SoC Audio driver 3 * 4 * Copyright 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11 #include <linux/module.h> 12 #include <linux/moduleparam.h> 13 #include <linux/init.h> 14 #include <linux/delay.h> 15 #include <linux/slab.h> 16 #include <linux/pm.h> 17 #include <linux/i2c.h> 18 #include <linux/clk.h> 19 #include <linux/regulator/driver.h> 20 #include <linux/regulator/machine.h> 21 #include <linux/regulator/consumer.h> 22 #include <linux/of_device.h> 23 #include <sound/core.h> 24 #include <sound/tlv.h> 25 #include <sound/pcm.h> 26 #include <sound/pcm_params.h> 27 #include <sound/soc.h> 28 #include <sound/soc-dapm.h> 29 #include <sound/initval.h> 30 31 #include "sgtl5000.h" 32 33 #define SGTL5000_DAP_REG_OFFSET 0x0100 34 #define SGTL5000_MAX_REG_OFFSET 0x013A 35 36 /* default value of sgtl5000 registers */ 37 static const u16 sgtl5000_regs[SGTL5000_MAX_REG_OFFSET] = { 38 [SGTL5000_CHIP_CLK_CTRL] = 0x0008, 39 [SGTL5000_CHIP_I2S_CTRL] = 0x0010, 40 [SGTL5000_CHIP_SSS_CTRL] = 0x0008, 41 [SGTL5000_CHIP_DAC_VOL] = 0x3c3c, 42 [SGTL5000_CHIP_PAD_STRENGTH] = 0x015f, 43 [SGTL5000_CHIP_ANA_HP_CTRL] = 0x1818, 44 [SGTL5000_CHIP_ANA_CTRL] = 0x0111, 45 [SGTL5000_CHIP_LINE_OUT_VOL] = 0x0404, 46 [SGTL5000_CHIP_ANA_POWER] = 0x7060, 47 [SGTL5000_CHIP_PLL_CTRL] = 0x5000, 48 [SGTL5000_DAP_BASS_ENHANCE] = 0x0040, 49 [SGTL5000_DAP_BASS_ENHANCE_CTRL] = 0x051f, 50 [SGTL5000_DAP_SURROUND] = 0x0040, 51 [SGTL5000_DAP_EQ_BASS_BAND0] = 0x002f, 52 [SGTL5000_DAP_EQ_BASS_BAND1] = 0x002f, 53 [SGTL5000_DAP_EQ_BASS_BAND2] = 0x002f, 54 [SGTL5000_DAP_EQ_BASS_BAND3] = 0x002f, 55 [SGTL5000_DAP_EQ_BASS_BAND4] = 0x002f, 56 [SGTL5000_DAP_MAIN_CHAN] = 0x8000, 57 [SGTL5000_DAP_AVC_CTRL] = 0x0510, 58 [SGTL5000_DAP_AVC_THRESHOLD] = 0x1473, 59 [SGTL5000_DAP_AVC_ATTACK] = 0x0028, 60 [SGTL5000_DAP_AVC_DECAY] = 0x0050, 61 }; 62 63 /* regulator supplies for sgtl5000, VDDD is an optional external supply */ 64 enum sgtl5000_regulator_supplies { 65 VDDA, 66 VDDIO, 67 VDDD, 68 SGTL5000_SUPPLY_NUM 69 }; 70 71 /* vddd is optional supply */ 72 static const char *supply_names[SGTL5000_SUPPLY_NUM] = { 73 "VDDA", 74 "VDDIO", 75 "VDDD" 76 }; 77 78 #define LDO_CONSUMER_NAME "VDDD_LDO" 79 #define LDO_VOLTAGE 1200000 80 81 static struct regulator_consumer_supply ldo_consumer[] = { 82 REGULATOR_SUPPLY(LDO_CONSUMER_NAME, NULL), 83 }; 84 85 static struct regulator_init_data ldo_init_data = { 86 .constraints = { 87 .min_uV = 850000, 88 .max_uV = 1600000, 89 .valid_modes_mask = REGULATOR_MODE_NORMAL, 90 .valid_ops_mask = REGULATOR_CHANGE_STATUS, 91 }, 92 .num_consumer_supplies = 1, 93 .consumer_supplies = &ldo_consumer[0], 94 }; 95 96 /* 97 * sgtl5000 internal ldo regulator, 98 * enabled when VDDD not provided 99 */ 100 struct ldo_regulator { 101 struct regulator_desc desc; 102 struct regulator_dev *dev; 103 int voltage; 104 void *codec_data; 105 bool enabled; 106 }; 107 108 /* sgtl5000 private structure in codec */ 109 struct sgtl5000_priv { 110 int sysclk; /* sysclk rate */ 111 int master; /* i2s master or not */ 112 int fmt; /* i2s data format */ 113 struct regulator_bulk_data supplies[SGTL5000_SUPPLY_NUM]; 114 struct ldo_regulator *ldo; 115 }; 116 117 /* 118 * mic_bias power on/off share the same register bits with 119 * output impedance of mic bias, when power on mic bias, we 120 * need reclaim it to impedance value. 121 * 0x0 = Powered off 122 * 0x1 = 2Kohm 123 * 0x2 = 4Kohm 124 * 0x3 = 8Kohm 125 */ 126 static int mic_bias_event(struct snd_soc_dapm_widget *w, 127 struct snd_kcontrol *kcontrol, int event) 128 { 129 switch (event) { 130 case SND_SOC_DAPM_POST_PMU: 131 /* change mic bias resistor to 4Kohm */ 132 snd_soc_update_bits(w->codec, SGTL5000_CHIP_MIC_CTRL, 133 SGTL5000_BIAS_R_MASK, 134 SGTL5000_BIAS_R_4k << SGTL5000_BIAS_R_SHIFT); 135 break; 136 137 case SND_SOC_DAPM_PRE_PMD: 138 snd_soc_update_bits(w->codec, SGTL5000_CHIP_MIC_CTRL, 139 SGTL5000_BIAS_R_MASK, 0); 140 break; 141 } 142 return 0; 143 } 144 145 /* 146 * As manual described, ADC/DAC only works when VAG powerup, 147 * So enabled VAG before ADC/DAC up. 148 * In power down case, we need wait 400ms when vag fully ramped down. 149 */ 150 static int power_vag_event(struct snd_soc_dapm_widget *w, 151 struct snd_kcontrol *kcontrol, int event) 152 { 153 switch (event) { 154 case SND_SOC_DAPM_PRE_PMU: 155 snd_soc_update_bits(w->codec, SGTL5000_CHIP_ANA_POWER, 156 SGTL5000_VAG_POWERUP, SGTL5000_VAG_POWERUP); 157 break; 158 159 case SND_SOC_DAPM_POST_PMD: 160 snd_soc_update_bits(w->codec, SGTL5000_CHIP_ANA_POWER, 161 SGTL5000_VAG_POWERUP, 0); 162 msleep(400); 163 break; 164 default: 165 break; 166 } 167 168 return 0; 169 } 170 171 /* input sources for ADC */ 172 static const char *adc_mux_text[] = { 173 "MIC_IN", "LINE_IN" 174 }; 175 176 static const struct soc_enum adc_enum = 177 SOC_ENUM_SINGLE(SGTL5000_CHIP_ANA_CTRL, 2, 2, adc_mux_text); 178 179 static const struct snd_kcontrol_new adc_mux = 180 SOC_DAPM_ENUM("Capture Mux", adc_enum); 181 182 /* input sources for DAC */ 183 static const char *dac_mux_text[] = { 184 "DAC", "LINE_IN" 185 }; 186 187 static const struct soc_enum dac_enum = 188 SOC_ENUM_SINGLE(SGTL5000_CHIP_ANA_CTRL, 6, 2, dac_mux_text); 189 190 static const struct snd_kcontrol_new dac_mux = 191 SOC_DAPM_ENUM("Headphone Mux", dac_enum); 192 193 static const struct snd_soc_dapm_widget sgtl5000_dapm_widgets[] = { 194 SND_SOC_DAPM_INPUT("LINE_IN"), 195 SND_SOC_DAPM_INPUT("MIC_IN"), 196 197 SND_SOC_DAPM_OUTPUT("HP_OUT"), 198 SND_SOC_DAPM_OUTPUT("LINE_OUT"), 199 200 SND_SOC_DAPM_MICBIAS_E("Mic Bias", SGTL5000_CHIP_MIC_CTRL, 8, 0, 201 mic_bias_event, 202 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 203 204 SND_SOC_DAPM_PGA("HP", SGTL5000_CHIP_ANA_POWER, 4, 0, NULL, 0), 205 SND_SOC_DAPM_PGA("LO", SGTL5000_CHIP_ANA_POWER, 0, 0, NULL, 0), 206 207 SND_SOC_DAPM_MUX("Capture Mux", SND_SOC_NOPM, 0, 0, &adc_mux), 208 SND_SOC_DAPM_MUX("Headphone Mux", SND_SOC_NOPM, 0, 0, &dac_mux), 209 210 /* aif for i2s input */ 211 SND_SOC_DAPM_AIF_IN("AIFIN", "Playback", 212 0, SGTL5000_CHIP_DIG_POWER, 213 0, 0), 214 215 /* aif for i2s output */ 216 SND_SOC_DAPM_AIF_OUT("AIFOUT", "Capture", 217 0, SGTL5000_CHIP_DIG_POWER, 218 1, 0), 219 220 SND_SOC_DAPM_SUPPLY("VAG_POWER", SGTL5000_CHIP_ANA_POWER, 7, 0, 221 power_vag_event, 222 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 223 224 SND_SOC_DAPM_ADC("ADC", "Capture", SGTL5000_CHIP_ANA_POWER, 1, 0), 225 SND_SOC_DAPM_DAC("DAC", "Playback", SGTL5000_CHIP_ANA_POWER, 3, 0), 226 }; 227 228 /* routes for sgtl5000 */ 229 static const struct snd_soc_dapm_route sgtl5000_dapm_routes[] = { 230 {"Capture Mux", "LINE_IN", "LINE_IN"}, /* line_in --> adc_mux */ 231 {"Capture Mux", "MIC_IN", "MIC_IN"}, /* mic_in --> adc_mux */ 232 233 {"ADC", NULL, "VAG_POWER"}, 234 {"ADC", NULL, "Capture Mux"}, /* adc_mux --> adc */ 235 {"AIFOUT", NULL, "ADC"}, /* adc --> i2s_out */ 236 237 {"DAC", NULL, "VAG_POWER"}, 238 {"DAC", NULL, "AIFIN"}, /* i2s-->dac,skip audio mux */ 239 {"Headphone Mux", "DAC", "DAC"}, /* dac --> hp_mux */ 240 {"LO", NULL, "DAC"}, /* dac --> line_out */ 241 242 {"Headphone Mux", "LINE_IN", "LINE_IN"},/* line_in --> hp_mux */ 243 {"HP", NULL, "Headphone Mux"}, /* hp_mux --> hp */ 244 245 {"LINE_OUT", NULL, "LO"}, 246 {"HP_OUT", NULL, "HP"}, 247 }; 248 249 /* custom function to fetch info of PCM playback volume */ 250 static int dac_info_volsw(struct snd_kcontrol *kcontrol, 251 struct snd_ctl_elem_info *uinfo) 252 { 253 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 254 uinfo->count = 2; 255 uinfo->value.integer.min = 0; 256 uinfo->value.integer.max = 0xfc - 0x3c; 257 return 0; 258 } 259 260 /* 261 * custom function to get of PCM playback volume 262 * 263 * dac volume register 264 * 15-------------8-7--------------0 265 * | R channel vol | L channel vol | 266 * ------------------------------- 267 * 268 * PCM volume with 0.5017 dB steps from 0 to -90 dB 269 * 270 * register values map to dB 271 * 0x3B and less = Reserved 272 * 0x3C = 0 dB 273 * 0x3D = -0.5 dB 274 * 0xF0 = -90 dB 275 * 0xFC and greater = Muted 276 * 277 * register value map to userspace value 278 * 279 * register value 0x3c(0dB) 0xf0(-90dB)0xfc 280 * ------------------------------ 281 * userspace value 0xc0 0 282 */ 283 static int dac_get_volsw(struct snd_kcontrol *kcontrol, 284 struct snd_ctl_elem_value *ucontrol) 285 { 286 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 287 int reg; 288 int l; 289 int r; 290 291 reg = snd_soc_read(codec, SGTL5000_CHIP_DAC_VOL); 292 293 /* get left channel volume */ 294 l = (reg & SGTL5000_DAC_VOL_LEFT_MASK) >> SGTL5000_DAC_VOL_LEFT_SHIFT; 295 296 /* get right channel volume */ 297 r = (reg & SGTL5000_DAC_VOL_RIGHT_MASK) >> SGTL5000_DAC_VOL_RIGHT_SHIFT; 298 299 /* make sure value fall in (0x3c,0xfc) */ 300 l = clamp(l, 0x3c, 0xfc); 301 r = clamp(r, 0x3c, 0xfc); 302 303 /* invert it and map to userspace value */ 304 l = 0xfc - l; 305 r = 0xfc - r; 306 307 ucontrol->value.integer.value[0] = l; 308 ucontrol->value.integer.value[1] = r; 309 310 return 0; 311 } 312 313 /* 314 * custom function to put of PCM playback volume 315 * 316 * dac volume register 317 * 15-------------8-7--------------0 318 * | R channel vol | L channel vol | 319 * ------------------------------- 320 * 321 * PCM volume with 0.5017 dB steps from 0 to -90 dB 322 * 323 * register values map to dB 324 * 0x3B and less = Reserved 325 * 0x3C = 0 dB 326 * 0x3D = -0.5 dB 327 * 0xF0 = -90 dB 328 * 0xFC and greater = Muted 329 * 330 * userspace value map to register value 331 * 332 * userspace value 0xc0 0 333 * ------------------------------ 334 * register value 0x3c(0dB) 0xf0(-90dB)0xfc 335 */ 336 static int dac_put_volsw(struct snd_kcontrol *kcontrol, 337 struct snd_ctl_elem_value *ucontrol) 338 { 339 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 340 int reg; 341 int l; 342 int r; 343 344 l = ucontrol->value.integer.value[0]; 345 r = ucontrol->value.integer.value[1]; 346 347 /* make sure userspace volume fall in (0, 0xfc-0x3c) */ 348 l = clamp(l, 0, 0xfc - 0x3c); 349 r = clamp(r, 0, 0xfc - 0x3c); 350 351 /* invert it, get the value can be set to register */ 352 l = 0xfc - l; 353 r = 0xfc - r; 354 355 /* shift to get the register value */ 356 reg = l << SGTL5000_DAC_VOL_LEFT_SHIFT | 357 r << SGTL5000_DAC_VOL_RIGHT_SHIFT; 358 359 snd_soc_write(codec, SGTL5000_CHIP_DAC_VOL, reg); 360 361 return 0; 362 } 363 364 static const DECLARE_TLV_DB_SCALE(capture_6db_attenuate, -600, 600, 0); 365 366 /* tlv for mic gain, 0db 20db 30db 40db */ 367 static const unsigned int mic_gain_tlv[] = { 368 TLV_DB_RANGE_HEAD(2), 369 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0), 370 1, 3, TLV_DB_SCALE_ITEM(2000, 1000, 0), 371 }; 372 373 /* tlv for hp volume, -51.5db to 12.0db, step .5db */ 374 static const DECLARE_TLV_DB_SCALE(headphone_volume, -5150, 50, 0); 375 376 static const struct snd_kcontrol_new sgtl5000_snd_controls[] = { 377 /* SOC_DOUBLE_S8_TLV with invert */ 378 { 379 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 380 .name = "PCM Playback Volume", 381 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ | 382 SNDRV_CTL_ELEM_ACCESS_READWRITE, 383 .info = dac_info_volsw, 384 .get = dac_get_volsw, 385 .put = dac_put_volsw, 386 }, 387 388 SOC_DOUBLE("Capture Volume", SGTL5000_CHIP_ANA_ADC_CTRL, 0, 4, 0xf, 0), 389 SOC_SINGLE_TLV("Capture Attenuate Switch (-6dB)", 390 SGTL5000_CHIP_ANA_ADC_CTRL, 391 8, 2, 0, capture_6db_attenuate), 392 SOC_SINGLE("Capture ZC Switch", SGTL5000_CHIP_ANA_CTRL, 1, 1, 0), 393 394 SOC_DOUBLE_TLV("Headphone Playback Volume", 395 SGTL5000_CHIP_ANA_HP_CTRL, 396 0, 8, 397 0x7f, 1, 398 headphone_volume), 399 SOC_SINGLE("Headphone Playback ZC Switch", SGTL5000_CHIP_ANA_CTRL, 400 5, 1, 0), 401 402 SOC_SINGLE_TLV("Mic Volume", SGTL5000_CHIP_MIC_CTRL, 403 0, 4, 0, mic_gain_tlv), 404 }; 405 406 /* mute the codec used by alsa core */ 407 static int sgtl5000_digital_mute(struct snd_soc_dai *codec_dai, int mute) 408 { 409 struct snd_soc_codec *codec = codec_dai->codec; 410 u16 adcdac_ctrl = SGTL5000_DAC_MUTE_LEFT | SGTL5000_DAC_MUTE_RIGHT; 411 412 snd_soc_update_bits(codec, SGTL5000_CHIP_ADCDAC_CTRL, 413 adcdac_ctrl, mute ? adcdac_ctrl : 0); 414 415 return 0; 416 } 417 418 /* set codec format */ 419 static int sgtl5000_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt) 420 { 421 struct snd_soc_codec *codec = codec_dai->codec; 422 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); 423 u16 i2sctl = 0; 424 425 sgtl5000->master = 0; 426 /* 427 * i2s clock and frame master setting. 428 * ONLY support: 429 * - clock and frame slave, 430 * - clock and frame master 431 */ 432 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 433 case SND_SOC_DAIFMT_CBS_CFS: 434 break; 435 case SND_SOC_DAIFMT_CBM_CFM: 436 i2sctl |= SGTL5000_I2S_MASTER; 437 sgtl5000->master = 1; 438 break; 439 default: 440 return -EINVAL; 441 } 442 443 /* setting i2s data format */ 444 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 445 case SND_SOC_DAIFMT_DSP_A: 446 i2sctl |= SGTL5000_I2S_MODE_PCM; 447 break; 448 case SND_SOC_DAIFMT_DSP_B: 449 i2sctl |= SGTL5000_I2S_MODE_PCM; 450 i2sctl |= SGTL5000_I2S_LRALIGN; 451 break; 452 case SND_SOC_DAIFMT_I2S: 453 i2sctl |= SGTL5000_I2S_MODE_I2S_LJ; 454 break; 455 case SND_SOC_DAIFMT_RIGHT_J: 456 i2sctl |= SGTL5000_I2S_MODE_RJ; 457 i2sctl |= SGTL5000_I2S_LRPOL; 458 break; 459 case SND_SOC_DAIFMT_LEFT_J: 460 i2sctl |= SGTL5000_I2S_MODE_I2S_LJ; 461 i2sctl |= SGTL5000_I2S_LRALIGN; 462 break; 463 default: 464 return -EINVAL; 465 } 466 467 sgtl5000->fmt = fmt & SND_SOC_DAIFMT_FORMAT_MASK; 468 469 /* Clock inversion */ 470 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 471 case SND_SOC_DAIFMT_NB_NF: 472 break; 473 case SND_SOC_DAIFMT_IB_NF: 474 i2sctl |= SGTL5000_I2S_SCLK_INV; 475 break; 476 default: 477 return -EINVAL; 478 } 479 480 snd_soc_write(codec, SGTL5000_CHIP_I2S_CTRL, i2sctl); 481 482 return 0; 483 } 484 485 /* set codec sysclk */ 486 static int sgtl5000_set_dai_sysclk(struct snd_soc_dai *codec_dai, 487 int clk_id, unsigned int freq, int dir) 488 { 489 struct snd_soc_codec *codec = codec_dai->codec; 490 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); 491 492 switch (clk_id) { 493 case SGTL5000_SYSCLK: 494 sgtl5000->sysclk = freq; 495 break; 496 default: 497 return -EINVAL; 498 } 499 500 return 0; 501 } 502 503 /* 504 * set clock according to i2s frame clock, 505 * sgtl5000 provide 2 clock sources. 506 * 1. sys_mclk. sample freq can only configure to 507 * 1/256, 1/384, 1/512 of sys_mclk. 508 * 2. pll. can derive any audio clocks. 509 * 510 * clock setting rules: 511 * 1. in slave mode, only sys_mclk can use. 512 * 2. as constraint by sys_mclk, sample freq should 513 * set to 32k, 44.1k and above. 514 * 3. using sys_mclk prefer to pll to save power. 515 */ 516 static int sgtl5000_set_clock(struct snd_soc_codec *codec, int frame_rate) 517 { 518 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); 519 int clk_ctl = 0; 520 int sys_fs; /* sample freq */ 521 522 /* 523 * sample freq should be divided by frame clock, 524 * if frame clock lower than 44.1khz, sample feq should set to 525 * 32khz or 44.1khz. 526 */ 527 switch (frame_rate) { 528 case 8000: 529 case 16000: 530 sys_fs = 32000; 531 break; 532 case 11025: 533 case 22050: 534 sys_fs = 44100; 535 break; 536 default: 537 sys_fs = frame_rate; 538 break; 539 } 540 541 /* set divided factor of frame clock */ 542 switch (sys_fs / frame_rate) { 543 case 4: 544 clk_ctl |= SGTL5000_RATE_MODE_DIV_4 << SGTL5000_RATE_MODE_SHIFT; 545 break; 546 case 2: 547 clk_ctl |= SGTL5000_RATE_MODE_DIV_2 << SGTL5000_RATE_MODE_SHIFT; 548 break; 549 case 1: 550 clk_ctl |= SGTL5000_RATE_MODE_DIV_1 << SGTL5000_RATE_MODE_SHIFT; 551 break; 552 default: 553 return -EINVAL; 554 } 555 556 /* set the sys_fs according to frame rate */ 557 switch (sys_fs) { 558 case 32000: 559 clk_ctl |= SGTL5000_SYS_FS_32k << SGTL5000_SYS_FS_SHIFT; 560 break; 561 case 44100: 562 clk_ctl |= SGTL5000_SYS_FS_44_1k << SGTL5000_SYS_FS_SHIFT; 563 break; 564 case 48000: 565 clk_ctl |= SGTL5000_SYS_FS_48k << SGTL5000_SYS_FS_SHIFT; 566 break; 567 case 96000: 568 clk_ctl |= SGTL5000_SYS_FS_96k << SGTL5000_SYS_FS_SHIFT; 569 break; 570 default: 571 dev_err(codec->dev, "frame rate %d not supported\n", 572 frame_rate); 573 return -EINVAL; 574 } 575 576 /* 577 * calculate the divider of mclk/sample_freq, 578 * factor of freq =96k can only be 256, since mclk in range (12m,27m) 579 */ 580 switch (sgtl5000->sysclk / sys_fs) { 581 case 256: 582 clk_ctl |= SGTL5000_MCLK_FREQ_256FS << 583 SGTL5000_MCLK_FREQ_SHIFT; 584 break; 585 case 384: 586 clk_ctl |= SGTL5000_MCLK_FREQ_384FS << 587 SGTL5000_MCLK_FREQ_SHIFT; 588 break; 589 case 512: 590 clk_ctl |= SGTL5000_MCLK_FREQ_512FS << 591 SGTL5000_MCLK_FREQ_SHIFT; 592 break; 593 default: 594 /* if mclk not satisify the divider, use pll */ 595 if (sgtl5000->master) { 596 clk_ctl |= SGTL5000_MCLK_FREQ_PLL << 597 SGTL5000_MCLK_FREQ_SHIFT; 598 } else { 599 dev_err(codec->dev, 600 "PLL not supported in slave mode\n"); 601 return -EINVAL; 602 } 603 } 604 605 /* if using pll, please check manual 6.4.2 for detail */ 606 if ((clk_ctl & SGTL5000_MCLK_FREQ_MASK) == SGTL5000_MCLK_FREQ_PLL) { 607 u64 out, t; 608 int div2; 609 int pll_ctl; 610 unsigned int in, int_div, frac_div; 611 612 if (sgtl5000->sysclk > 17000000) { 613 div2 = 1; 614 in = sgtl5000->sysclk / 2; 615 } else { 616 div2 = 0; 617 in = sgtl5000->sysclk; 618 } 619 if (sys_fs == 44100) 620 out = 180633600; 621 else 622 out = 196608000; 623 t = do_div(out, in); 624 int_div = out; 625 t *= 2048; 626 do_div(t, in); 627 frac_div = t; 628 pll_ctl = int_div << SGTL5000_PLL_INT_DIV_SHIFT | 629 frac_div << SGTL5000_PLL_FRAC_DIV_SHIFT; 630 631 snd_soc_write(codec, SGTL5000_CHIP_PLL_CTRL, pll_ctl); 632 if (div2) 633 snd_soc_update_bits(codec, 634 SGTL5000_CHIP_CLK_TOP_CTRL, 635 SGTL5000_INPUT_FREQ_DIV2, 636 SGTL5000_INPUT_FREQ_DIV2); 637 else 638 snd_soc_update_bits(codec, 639 SGTL5000_CHIP_CLK_TOP_CTRL, 640 SGTL5000_INPUT_FREQ_DIV2, 641 0); 642 643 /* power up pll */ 644 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER, 645 SGTL5000_PLL_POWERUP | SGTL5000_VCOAMP_POWERUP, 646 SGTL5000_PLL_POWERUP | SGTL5000_VCOAMP_POWERUP); 647 } else { 648 /* power down pll */ 649 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER, 650 SGTL5000_PLL_POWERUP | SGTL5000_VCOAMP_POWERUP, 651 0); 652 } 653 654 /* if using pll, clk_ctrl must be set after pll power up */ 655 snd_soc_write(codec, SGTL5000_CHIP_CLK_CTRL, clk_ctl); 656 657 return 0; 658 } 659 660 /* 661 * Set PCM DAI bit size and sample rate. 662 * input: params_rate, params_fmt 663 */ 664 static int sgtl5000_pcm_hw_params(struct snd_pcm_substream *substream, 665 struct snd_pcm_hw_params *params, 666 struct snd_soc_dai *dai) 667 { 668 struct snd_soc_pcm_runtime *rtd = substream->private_data; 669 struct snd_soc_codec *codec = rtd->codec; 670 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); 671 int channels = params_channels(params); 672 int i2s_ctl = 0; 673 int stereo; 674 int ret; 675 676 /* sysclk should already set */ 677 if (!sgtl5000->sysclk) { 678 dev_err(codec->dev, "%s: set sysclk first!\n", __func__); 679 return -EFAULT; 680 } 681 682 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 683 stereo = SGTL5000_DAC_STEREO; 684 else 685 stereo = SGTL5000_ADC_STEREO; 686 687 /* set mono to save power */ 688 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER, stereo, 689 channels == 1 ? 0 : stereo); 690 691 /* set codec clock base on lrclk */ 692 ret = sgtl5000_set_clock(codec, params_rate(params)); 693 if (ret) 694 return ret; 695 696 /* set i2s data format */ 697 switch (params_format(params)) { 698 case SNDRV_PCM_FORMAT_S16_LE: 699 if (sgtl5000->fmt == SND_SOC_DAIFMT_RIGHT_J) 700 return -EINVAL; 701 i2s_ctl |= SGTL5000_I2S_DLEN_16 << SGTL5000_I2S_DLEN_SHIFT; 702 i2s_ctl |= SGTL5000_I2S_SCLKFREQ_32FS << 703 SGTL5000_I2S_SCLKFREQ_SHIFT; 704 break; 705 case SNDRV_PCM_FORMAT_S20_3LE: 706 i2s_ctl |= SGTL5000_I2S_DLEN_20 << SGTL5000_I2S_DLEN_SHIFT; 707 i2s_ctl |= SGTL5000_I2S_SCLKFREQ_64FS << 708 SGTL5000_I2S_SCLKFREQ_SHIFT; 709 break; 710 case SNDRV_PCM_FORMAT_S24_LE: 711 i2s_ctl |= SGTL5000_I2S_DLEN_24 << SGTL5000_I2S_DLEN_SHIFT; 712 i2s_ctl |= SGTL5000_I2S_SCLKFREQ_64FS << 713 SGTL5000_I2S_SCLKFREQ_SHIFT; 714 break; 715 case SNDRV_PCM_FORMAT_S32_LE: 716 if (sgtl5000->fmt == SND_SOC_DAIFMT_RIGHT_J) 717 return -EINVAL; 718 i2s_ctl |= SGTL5000_I2S_DLEN_32 << SGTL5000_I2S_DLEN_SHIFT; 719 i2s_ctl |= SGTL5000_I2S_SCLKFREQ_64FS << 720 SGTL5000_I2S_SCLKFREQ_SHIFT; 721 break; 722 default: 723 return -EINVAL; 724 } 725 726 snd_soc_update_bits(codec, SGTL5000_CHIP_I2S_CTRL, 727 SGTL5000_I2S_DLEN_MASK | SGTL5000_I2S_SCLKFREQ_MASK, 728 i2s_ctl); 729 730 return 0; 731 } 732 733 #ifdef CONFIG_REGULATOR 734 static int ldo_regulator_is_enabled(struct regulator_dev *dev) 735 { 736 struct ldo_regulator *ldo = rdev_get_drvdata(dev); 737 738 return ldo->enabled; 739 } 740 741 static int ldo_regulator_enable(struct regulator_dev *dev) 742 { 743 struct ldo_regulator *ldo = rdev_get_drvdata(dev); 744 struct snd_soc_codec *codec = (struct snd_soc_codec *)ldo->codec_data; 745 int reg; 746 747 if (ldo_regulator_is_enabled(dev)) 748 return 0; 749 750 /* set regulator value firstly */ 751 reg = (1600 - ldo->voltage / 1000) / 50; 752 reg = clamp(reg, 0x0, 0xf); 753 754 /* amend the voltage value, unit: uV */ 755 ldo->voltage = (1600 - reg * 50) * 1000; 756 757 /* set voltage to register */ 758 snd_soc_update_bits(codec, SGTL5000_CHIP_LINREG_CTRL, 759 SGTL5000_LINREG_VDDD_MASK, reg); 760 761 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER, 762 SGTL5000_LINEREG_D_POWERUP, 763 SGTL5000_LINEREG_D_POWERUP); 764 765 /* when internal ldo enabled, simple digital power can be disabled */ 766 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER, 767 SGTL5000_LINREG_SIMPLE_POWERUP, 768 0); 769 770 ldo->enabled = 1; 771 return 0; 772 } 773 774 static int ldo_regulator_disable(struct regulator_dev *dev) 775 { 776 struct ldo_regulator *ldo = rdev_get_drvdata(dev); 777 struct snd_soc_codec *codec = (struct snd_soc_codec *)ldo->codec_data; 778 779 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER, 780 SGTL5000_LINEREG_D_POWERUP, 781 0); 782 783 /* clear voltage info */ 784 snd_soc_update_bits(codec, SGTL5000_CHIP_LINREG_CTRL, 785 SGTL5000_LINREG_VDDD_MASK, 0); 786 787 ldo->enabled = 0; 788 789 return 0; 790 } 791 792 static int ldo_regulator_get_voltage(struct regulator_dev *dev) 793 { 794 struct ldo_regulator *ldo = rdev_get_drvdata(dev); 795 796 return ldo->voltage; 797 } 798 799 static struct regulator_ops ldo_regulator_ops = { 800 .is_enabled = ldo_regulator_is_enabled, 801 .enable = ldo_regulator_enable, 802 .disable = ldo_regulator_disable, 803 .get_voltage = ldo_regulator_get_voltage, 804 }; 805 806 static int ldo_regulator_register(struct snd_soc_codec *codec, 807 struct regulator_init_data *init_data, 808 int voltage) 809 { 810 struct ldo_regulator *ldo; 811 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); 812 813 ldo = kzalloc(sizeof(struct ldo_regulator), GFP_KERNEL); 814 815 if (!ldo) { 816 dev_err(codec->dev, "failed to allocate ldo_regulator\n"); 817 return -ENOMEM; 818 } 819 820 ldo->desc.name = kstrdup(dev_name(codec->dev), GFP_KERNEL); 821 if (!ldo->desc.name) { 822 kfree(ldo); 823 dev_err(codec->dev, "failed to allocate decs name memory\n"); 824 return -ENOMEM; 825 } 826 827 ldo->desc.type = REGULATOR_VOLTAGE; 828 ldo->desc.owner = THIS_MODULE; 829 ldo->desc.ops = &ldo_regulator_ops; 830 ldo->desc.n_voltages = 1; 831 832 ldo->codec_data = codec; 833 ldo->voltage = voltage; 834 835 ldo->dev = regulator_register(&ldo->desc, codec->dev, 836 init_data, ldo, NULL); 837 if (IS_ERR(ldo->dev)) { 838 int ret = PTR_ERR(ldo->dev); 839 840 dev_err(codec->dev, "failed to register regulator\n"); 841 kfree(ldo->desc.name); 842 kfree(ldo); 843 844 return ret; 845 } 846 sgtl5000->ldo = ldo; 847 848 return 0; 849 } 850 851 static int ldo_regulator_remove(struct snd_soc_codec *codec) 852 { 853 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); 854 struct ldo_regulator *ldo = sgtl5000->ldo; 855 856 if (!ldo) 857 return 0; 858 859 regulator_unregister(ldo->dev); 860 kfree(ldo->desc.name); 861 kfree(ldo); 862 863 return 0; 864 } 865 #else 866 static int ldo_regulator_register(struct snd_soc_codec *codec, 867 struct regulator_init_data *init_data, 868 int voltage) 869 { 870 dev_err(codec->dev, "this setup needs regulator support in the kernel\n"); 871 return -EINVAL; 872 } 873 874 static int ldo_regulator_remove(struct snd_soc_codec *codec) 875 { 876 return 0; 877 } 878 #endif 879 880 /* 881 * set dac bias 882 * common state changes: 883 * startup: 884 * off --> standby --> prepare --> on 885 * standby --> prepare --> on 886 * 887 * stop: 888 * on --> prepare --> standby 889 */ 890 static int sgtl5000_set_bias_level(struct snd_soc_codec *codec, 891 enum snd_soc_bias_level level) 892 { 893 int ret; 894 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); 895 896 switch (level) { 897 case SND_SOC_BIAS_ON: 898 case SND_SOC_BIAS_PREPARE: 899 break; 900 case SND_SOC_BIAS_STANDBY: 901 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) { 902 ret = regulator_bulk_enable( 903 ARRAY_SIZE(sgtl5000->supplies), 904 sgtl5000->supplies); 905 if (ret) 906 return ret; 907 udelay(10); 908 } 909 910 break; 911 case SND_SOC_BIAS_OFF: 912 regulator_bulk_disable(ARRAY_SIZE(sgtl5000->supplies), 913 sgtl5000->supplies); 914 break; 915 } 916 917 codec->dapm.bias_level = level; 918 return 0; 919 } 920 921 #define SGTL5000_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ 922 SNDRV_PCM_FMTBIT_S20_3LE |\ 923 SNDRV_PCM_FMTBIT_S24_LE |\ 924 SNDRV_PCM_FMTBIT_S32_LE) 925 926 static const struct snd_soc_dai_ops sgtl5000_ops = { 927 .hw_params = sgtl5000_pcm_hw_params, 928 .digital_mute = sgtl5000_digital_mute, 929 .set_fmt = sgtl5000_set_dai_fmt, 930 .set_sysclk = sgtl5000_set_dai_sysclk, 931 }; 932 933 static struct snd_soc_dai_driver sgtl5000_dai = { 934 .name = "sgtl5000", 935 .playback = { 936 .stream_name = "Playback", 937 .channels_min = 1, 938 .channels_max = 2, 939 /* 940 * only support 8~48K + 96K, 941 * TODO modify hw_param to support more 942 */ 943 .rates = SNDRV_PCM_RATE_8000_48000 | SNDRV_PCM_RATE_96000, 944 .formats = SGTL5000_FORMATS, 945 }, 946 .capture = { 947 .stream_name = "Capture", 948 .channels_min = 1, 949 .channels_max = 2, 950 .rates = SNDRV_PCM_RATE_8000_48000 | SNDRV_PCM_RATE_96000, 951 .formats = SGTL5000_FORMATS, 952 }, 953 .ops = &sgtl5000_ops, 954 .symmetric_rates = 1, 955 }; 956 957 static int sgtl5000_volatile_register(struct snd_soc_codec *codec, 958 unsigned int reg) 959 { 960 switch (reg) { 961 case SGTL5000_CHIP_ID: 962 case SGTL5000_CHIP_ADCDAC_CTRL: 963 case SGTL5000_CHIP_ANA_STATUS: 964 return 1; 965 } 966 967 return 0; 968 } 969 970 #ifdef CONFIG_SUSPEND 971 static int sgtl5000_suspend(struct snd_soc_codec *codec) 972 { 973 sgtl5000_set_bias_level(codec, SND_SOC_BIAS_OFF); 974 975 return 0; 976 } 977 978 /* 979 * restore all sgtl5000 registers, 980 * since a big hole between dap and regular registers, 981 * we will restore them respectively. 982 */ 983 static int sgtl5000_restore_regs(struct snd_soc_codec *codec) 984 { 985 u16 *cache = codec->reg_cache; 986 u16 reg; 987 988 /* restore regular registers */ 989 for (reg = 0; reg <= SGTL5000_CHIP_SHORT_CTRL; reg += 2) { 990 991 /* These regs should restore in particular order */ 992 if (reg == SGTL5000_CHIP_ANA_POWER || 993 reg == SGTL5000_CHIP_CLK_CTRL || 994 reg == SGTL5000_CHIP_LINREG_CTRL || 995 reg == SGTL5000_CHIP_LINE_OUT_CTRL || 996 reg == SGTL5000_CHIP_REF_CTRL) 997 continue; 998 999 snd_soc_write(codec, reg, cache[reg]); 1000 } 1001 1002 /* restore dap registers */ 1003 for (reg = SGTL5000_DAP_REG_OFFSET; reg < SGTL5000_MAX_REG_OFFSET; reg += 2) 1004 snd_soc_write(codec, reg, cache[reg]); 1005 1006 /* 1007 * restore these regs according to the power setting sequence in 1008 * sgtl5000_set_power_regs() and clock setting sequence in 1009 * sgtl5000_set_clock(). 1010 * 1011 * The order of restore is: 1012 * 1. SGTL5000_CHIP_CLK_CTRL MCLK_FREQ bits (1:0) should be restore after 1013 * SGTL5000_CHIP_ANA_POWER PLL bits set 1014 * 2. SGTL5000_CHIP_LINREG_CTRL should be set before 1015 * SGTL5000_CHIP_ANA_POWER LINREG_D restored 1016 * 3. SGTL5000_CHIP_REF_CTRL controls Analog Ground Voltage, 1017 * prefer to resotre it after SGTL5000_CHIP_ANA_POWER restored 1018 */ 1019 snd_soc_write(codec, SGTL5000_CHIP_LINREG_CTRL, 1020 cache[SGTL5000_CHIP_LINREG_CTRL]); 1021 1022 snd_soc_write(codec, SGTL5000_CHIP_ANA_POWER, 1023 cache[SGTL5000_CHIP_ANA_POWER]); 1024 1025 snd_soc_write(codec, SGTL5000_CHIP_CLK_CTRL, 1026 cache[SGTL5000_CHIP_CLK_CTRL]); 1027 1028 snd_soc_write(codec, SGTL5000_CHIP_REF_CTRL, 1029 cache[SGTL5000_CHIP_REF_CTRL]); 1030 1031 snd_soc_write(codec, SGTL5000_CHIP_LINE_OUT_CTRL, 1032 cache[SGTL5000_CHIP_LINE_OUT_CTRL]); 1033 return 0; 1034 } 1035 1036 static int sgtl5000_resume(struct snd_soc_codec *codec) 1037 { 1038 /* Bring the codec back up to standby to enable regulators */ 1039 sgtl5000_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 1040 1041 /* Restore registers by cached in memory */ 1042 sgtl5000_restore_regs(codec); 1043 return 0; 1044 } 1045 #else 1046 #define sgtl5000_suspend NULL 1047 #define sgtl5000_resume NULL 1048 #endif /* CONFIG_SUSPEND */ 1049 1050 /* 1051 * sgtl5000 has 3 internal power supplies: 1052 * 1. VAG, normally set to vdda/2 1053 * 2. chargepump, set to different value 1054 * according to voltage of vdda and vddio 1055 * 3. line out VAG, normally set to vddio/2 1056 * 1057 * and should be set according to: 1058 * 1. vddd provided by external or not 1059 * 2. vdda and vddio voltage value. > 3.1v or not 1060 * 3. chip revision >=0x11 or not. If >=0x11, not use external vddd. 1061 */ 1062 static int sgtl5000_set_power_regs(struct snd_soc_codec *codec) 1063 { 1064 int vddd; 1065 int vdda; 1066 int vddio; 1067 u16 ana_pwr; 1068 u16 lreg_ctrl; 1069 int vag; 1070 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); 1071 1072 vdda = regulator_get_voltage(sgtl5000->supplies[VDDA].consumer); 1073 vddio = regulator_get_voltage(sgtl5000->supplies[VDDIO].consumer); 1074 vddd = regulator_get_voltage(sgtl5000->supplies[VDDD].consumer); 1075 1076 vdda = vdda / 1000; 1077 vddio = vddio / 1000; 1078 vddd = vddd / 1000; 1079 1080 if (vdda <= 0 || vddio <= 0 || vddd < 0) { 1081 dev_err(codec->dev, "regulator voltage not set correctly\n"); 1082 1083 return -EINVAL; 1084 } 1085 1086 /* according to datasheet, maximum voltage of supplies */ 1087 if (vdda > 3600 || vddio > 3600 || vddd > 1980) { 1088 dev_err(codec->dev, 1089 "exceed max voltage vdda %dmV vddio %dmV vddd %dmV\n", 1090 vdda, vddio, vddd); 1091 1092 return -EINVAL; 1093 } 1094 1095 /* reset value */ 1096 ana_pwr = snd_soc_read(codec, SGTL5000_CHIP_ANA_POWER); 1097 ana_pwr |= SGTL5000_DAC_STEREO | 1098 SGTL5000_ADC_STEREO | 1099 SGTL5000_REFTOP_POWERUP; 1100 lreg_ctrl = snd_soc_read(codec, SGTL5000_CHIP_LINREG_CTRL); 1101 1102 if (vddio < 3100 && vdda < 3100) { 1103 /* enable internal oscillator used for charge pump */ 1104 snd_soc_update_bits(codec, SGTL5000_CHIP_CLK_TOP_CTRL, 1105 SGTL5000_INT_OSC_EN, 1106 SGTL5000_INT_OSC_EN); 1107 /* Enable VDDC charge pump */ 1108 ana_pwr |= SGTL5000_VDDC_CHRGPMP_POWERUP; 1109 } else if (vddio >= 3100 && vdda >= 3100) { 1110 /* 1111 * if vddio and vddd > 3.1v, 1112 * charge pump should be clean before set ana_pwr 1113 */ 1114 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER, 1115 SGTL5000_VDDC_CHRGPMP_POWERUP, 0); 1116 1117 /* VDDC use VDDIO rail */ 1118 lreg_ctrl |= SGTL5000_VDDC_ASSN_OVRD; 1119 lreg_ctrl |= SGTL5000_VDDC_MAN_ASSN_VDDIO << 1120 SGTL5000_VDDC_MAN_ASSN_SHIFT; 1121 } 1122 1123 snd_soc_write(codec, SGTL5000_CHIP_LINREG_CTRL, lreg_ctrl); 1124 1125 snd_soc_write(codec, SGTL5000_CHIP_ANA_POWER, ana_pwr); 1126 1127 /* set voltage to register */ 1128 snd_soc_update_bits(codec, SGTL5000_CHIP_LINREG_CTRL, 1129 SGTL5000_LINREG_VDDD_MASK, 0x8); 1130 1131 /* 1132 * if vddd linear reg has been enabled, 1133 * simple digital supply should be clear to get 1134 * proper VDDD voltage. 1135 */ 1136 if (ana_pwr & SGTL5000_LINEREG_D_POWERUP) 1137 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER, 1138 SGTL5000_LINREG_SIMPLE_POWERUP, 1139 0); 1140 else 1141 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER, 1142 SGTL5000_LINREG_SIMPLE_POWERUP | 1143 SGTL5000_STARTUP_POWERUP, 1144 0); 1145 1146 /* 1147 * set ADC/DAC VAG to vdda / 2, 1148 * should stay in range (0.8v, 1.575v) 1149 */ 1150 vag = vdda / 2; 1151 if (vag <= SGTL5000_ANA_GND_BASE) 1152 vag = 0; 1153 else if (vag >= SGTL5000_ANA_GND_BASE + SGTL5000_ANA_GND_STP * 1154 (SGTL5000_ANA_GND_MASK >> SGTL5000_ANA_GND_SHIFT)) 1155 vag = SGTL5000_ANA_GND_MASK >> SGTL5000_ANA_GND_SHIFT; 1156 else 1157 vag = (vag - SGTL5000_ANA_GND_BASE) / SGTL5000_ANA_GND_STP; 1158 1159 snd_soc_update_bits(codec, SGTL5000_CHIP_REF_CTRL, 1160 SGTL5000_ANA_GND_MASK, vag << SGTL5000_ANA_GND_SHIFT); 1161 1162 /* set line out VAG to vddio / 2, in range (0.8v, 1.675v) */ 1163 vag = vddio / 2; 1164 if (vag <= SGTL5000_LINE_OUT_GND_BASE) 1165 vag = 0; 1166 else if (vag >= SGTL5000_LINE_OUT_GND_BASE + 1167 SGTL5000_LINE_OUT_GND_STP * SGTL5000_LINE_OUT_GND_MAX) 1168 vag = SGTL5000_LINE_OUT_GND_MAX; 1169 else 1170 vag = (vag - SGTL5000_LINE_OUT_GND_BASE) / 1171 SGTL5000_LINE_OUT_GND_STP; 1172 1173 snd_soc_update_bits(codec, SGTL5000_CHIP_LINE_OUT_CTRL, 1174 SGTL5000_LINE_OUT_CURRENT_MASK | 1175 SGTL5000_LINE_OUT_GND_MASK, 1176 vag << SGTL5000_LINE_OUT_GND_SHIFT | 1177 SGTL5000_LINE_OUT_CURRENT_360u << 1178 SGTL5000_LINE_OUT_CURRENT_SHIFT); 1179 1180 return 0; 1181 } 1182 1183 static int sgtl5000_replace_vddd_with_ldo(struct snd_soc_codec *codec) 1184 { 1185 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); 1186 int ret; 1187 1188 /* set internal ldo to 1.2v */ 1189 ret = ldo_regulator_register(codec, &ldo_init_data, LDO_VOLTAGE); 1190 if (ret) { 1191 dev_err(codec->dev, 1192 "Failed to register vddd internal supplies: %d\n", ret); 1193 return ret; 1194 } 1195 1196 sgtl5000->supplies[VDDD].supply = LDO_CONSUMER_NAME; 1197 1198 ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(sgtl5000->supplies), 1199 sgtl5000->supplies); 1200 1201 if (ret) { 1202 ldo_regulator_remove(codec); 1203 dev_err(codec->dev, "Failed to request supplies: %d\n", ret); 1204 return ret; 1205 } 1206 1207 dev_info(codec->dev, "Using internal LDO instead of VDDD\n"); 1208 return 0; 1209 } 1210 1211 static int sgtl5000_enable_regulators(struct snd_soc_codec *codec) 1212 { 1213 u16 reg; 1214 int ret; 1215 int rev; 1216 int i; 1217 int external_vddd = 0; 1218 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); 1219 1220 for (i = 0; i < ARRAY_SIZE(sgtl5000->supplies); i++) 1221 sgtl5000->supplies[i].supply = supply_names[i]; 1222 1223 ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(sgtl5000->supplies), 1224 sgtl5000->supplies); 1225 if (!ret) 1226 external_vddd = 1; 1227 else { 1228 ret = sgtl5000_replace_vddd_with_ldo(codec); 1229 if (ret) 1230 return ret; 1231 } 1232 1233 ret = regulator_bulk_enable(ARRAY_SIZE(sgtl5000->supplies), 1234 sgtl5000->supplies); 1235 if (ret) 1236 goto err_regulator_free; 1237 1238 /* wait for all power rails bring up */ 1239 udelay(10); 1240 1241 /* read chip information */ 1242 reg = snd_soc_read(codec, SGTL5000_CHIP_ID); 1243 if (((reg & SGTL5000_PARTID_MASK) >> SGTL5000_PARTID_SHIFT) != 1244 SGTL5000_PARTID_PART_ID) { 1245 dev_err(codec->dev, 1246 "Device with ID register %x is not a sgtl5000\n", reg); 1247 ret = -ENODEV; 1248 goto err_regulator_disable; 1249 } 1250 1251 rev = (reg & SGTL5000_REVID_MASK) >> SGTL5000_REVID_SHIFT; 1252 dev_info(codec->dev, "sgtl5000 revision 0x%x\n", rev); 1253 1254 /* 1255 * workaround for revision 0x11 and later, 1256 * roll back to use internal LDO 1257 */ 1258 if (external_vddd && rev >= 0x11) { 1259 /* disable all regulator first */ 1260 regulator_bulk_disable(ARRAY_SIZE(sgtl5000->supplies), 1261 sgtl5000->supplies); 1262 /* free VDDD regulator */ 1263 regulator_bulk_free(ARRAY_SIZE(sgtl5000->supplies), 1264 sgtl5000->supplies); 1265 1266 ret = sgtl5000_replace_vddd_with_ldo(codec); 1267 if (ret) 1268 return ret; 1269 1270 ret = regulator_bulk_enable(ARRAY_SIZE(sgtl5000->supplies), 1271 sgtl5000->supplies); 1272 if (ret) 1273 goto err_regulator_free; 1274 1275 /* wait for all power rails bring up */ 1276 udelay(10); 1277 } 1278 1279 return 0; 1280 1281 err_regulator_disable: 1282 regulator_bulk_disable(ARRAY_SIZE(sgtl5000->supplies), 1283 sgtl5000->supplies); 1284 err_regulator_free: 1285 regulator_bulk_free(ARRAY_SIZE(sgtl5000->supplies), 1286 sgtl5000->supplies); 1287 if (external_vddd) 1288 ldo_regulator_remove(codec); 1289 return ret; 1290 1291 } 1292 1293 static int sgtl5000_probe(struct snd_soc_codec *codec) 1294 { 1295 int ret; 1296 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); 1297 1298 /* setup i2c data ops */ 1299 ret = snd_soc_codec_set_cache_io(codec, 16, 16, SND_SOC_I2C); 1300 if (ret < 0) { 1301 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret); 1302 return ret; 1303 } 1304 1305 ret = sgtl5000_enable_regulators(codec); 1306 if (ret) 1307 return ret; 1308 1309 /* power up sgtl5000 */ 1310 ret = sgtl5000_set_power_regs(codec); 1311 if (ret) 1312 goto err; 1313 1314 /* enable small pop, introduce 400ms delay in turning off */ 1315 snd_soc_update_bits(codec, SGTL5000_CHIP_REF_CTRL, 1316 SGTL5000_SMALL_POP, 1317 SGTL5000_SMALL_POP); 1318 1319 /* disable short cut detector */ 1320 snd_soc_write(codec, SGTL5000_CHIP_SHORT_CTRL, 0); 1321 1322 /* 1323 * set i2s as default input of sound switch 1324 * TODO: add sound switch to control and dapm widge. 1325 */ 1326 snd_soc_write(codec, SGTL5000_CHIP_SSS_CTRL, 1327 SGTL5000_DAC_SEL_I2S_IN << SGTL5000_DAC_SEL_SHIFT); 1328 snd_soc_write(codec, SGTL5000_CHIP_DIG_POWER, 1329 SGTL5000_ADC_EN | SGTL5000_DAC_EN); 1330 1331 /* enable dac volume ramp by default */ 1332 snd_soc_write(codec, SGTL5000_CHIP_ADCDAC_CTRL, 1333 SGTL5000_DAC_VOL_RAMP_EN | 1334 SGTL5000_DAC_MUTE_RIGHT | 1335 SGTL5000_DAC_MUTE_LEFT); 1336 1337 snd_soc_write(codec, SGTL5000_CHIP_PAD_STRENGTH, 0x015f); 1338 1339 snd_soc_write(codec, SGTL5000_CHIP_ANA_CTRL, 1340 SGTL5000_HP_ZCD_EN | 1341 SGTL5000_ADC_ZCD_EN); 1342 1343 snd_soc_write(codec, SGTL5000_CHIP_MIC_CTRL, 0); 1344 1345 /* 1346 * disable DAP 1347 * TODO: 1348 * Enable DAP in kcontrol and dapm. 1349 */ 1350 snd_soc_write(codec, SGTL5000_DAP_CTRL, 0); 1351 1352 /* leading to standby state */ 1353 ret = sgtl5000_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 1354 if (ret) 1355 goto err; 1356 1357 snd_soc_dapm_new_widgets(&codec->dapm); 1358 1359 return 0; 1360 1361 err: 1362 regulator_bulk_disable(ARRAY_SIZE(sgtl5000->supplies), 1363 sgtl5000->supplies); 1364 regulator_bulk_free(ARRAY_SIZE(sgtl5000->supplies), 1365 sgtl5000->supplies); 1366 ldo_regulator_remove(codec); 1367 1368 return ret; 1369 } 1370 1371 static int sgtl5000_remove(struct snd_soc_codec *codec) 1372 { 1373 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); 1374 1375 sgtl5000_set_bias_level(codec, SND_SOC_BIAS_OFF); 1376 1377 regulator_bulk_disable(ARRAY_SIZE(sgtl5000->supplies), 1378 sgtl5000->supplies); 1379 regulator_bulk_free(ARRAY_SIZE(sgtl5000->supplies), 1380 sgtl5000->supplies); 1381 ldo_regulator_remove(codec); 1382 1383 return 0; 1384 } 1385 1386 static struct snd_soc_codec_driver sgtl5000_driver = { 1387 .probe = sgtl5000_probe, 1388 .remove = sgtl5000_remove, 1389 .suspend = sgtl5000_suspend, 1390 .resume = sgtl5000_resume, 1391 .set_bias_level = sgtl5000_set_bias_level, 1392 .reg_cache_size = ARRAY_SIZE(sgtl5000_regs), 1393 .reg_word_size = sizeof(u16), 1394 .reg_cache_step = 2, 1395 .reg_cache_default = sgtl5000_regs, 1396 .volatile_register = sgtl5000_volatile_register, 1397 .controls = sgtl5000_snd_controls, 1398 .num_controls = ARRAY_SIZE(sgtl5000_snd_controls), 1399 .dapm_widgets = sgtl5000_dapm_widgets, 1400 .num_dapm_widgets = ARRAY_SIZE(sgtl5000_dapm_widgets), 1401 .dapm_routes = sgtl5000_dapm_routes, 1402 .num_dapm_routes = ARRAY_SIZE(sgtl5000_dapm_routes), 1403 }; 1404 1405 static __devinit int sgtl5000_i2c_probe(struct i2c_client *client, 1406 const struct i2c_device_id *id) 1407 { 1408 struct sgtl5000_priv *sgtl5000; 1409 int ret; 1410 1411 sgtl5000 = devm_kzalloc(&client->dev, sizeof(struct sgtl5000_priv), 1412 GFP_KERNEL); 1413 if (!sgtl5000) 1414 return -ENOMEM; 1415 1416 i2c_set_clientdata(client, sgtl5000); 1417 1418 ret = snd_soc_register_codec(&client->dev, 1419 &sgtl5000_driver, &sgtl5000_dai, 1); 1420 return ret; 1421 } 1422 1423 static __devexit int sgtl5000_i2c_remove(struct i2c_client *client) 1424 { 1425 snd_soc_unregister_codec(&client->dev); 1426 1427 return 0; 1428 } 1429 1430 static const struct i2c_device_id sgtl5000_id[] = { 1431 {"sgtl5000", 0}, 1432 {}, 1433 }; 1434 1435 MODULE_DEVICE_TABLE(i2c, sgtl5000_id); 1436 1437 static const struct of_device_id sgtl5000_dt_ids[] = { 1438 { .compatible = "fsl,sgtl5000", }, 1439 { /* sentinel */ } 1440 }; 1441 MODULE_DEVICE_TABLE(of, sgtl5000_dt_ids); 1442 1443 static struct i2c_driver sgtl5000_i2c_driver = { 1444 .driver = { 1445 .name = "sgtl5000", 1446 .owner = THIS_MODULE, 1447 .of_match_table = sgtl5000_dt_ids, 1448 }, 1449 .probe = sgtl5000_i2c_probe, 1450 .remove = __devexit_p(sgtl5000_i2c_remove), 1451 .id_table = sgtl5000_id, 1452 }; 1453 1454 static int __init sgtl5000_modinit(void) 1455 { 1456 return i2c_add_driver(&sgtl5000_i2c_driver); 1457 } 1458 module_init(sgtl5000_modinit); 1459 1460 static void __exit sgtl5000_exit(void) 1461 { 1462 i2c_del_driver(&sgtl5000_i2c_driver); 1463 } 1464 module_exit(sgtl5000_exit); 1465 1466 MODULE_DESCRIPTION("Freescale SGTL5000 ALSA SoC Codec Driver"); 1467 MODULE_AUTHOR("Zeng Zhaoming <zengzm.kernel@gmail.com>"); 1468 MODULE_LICENSE("GPL"); 1469