1 /* 2 * sgtl5000.c -- SGTL5000 ALSA SoC Audio driver 3 * 4 * Copyright 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11 #include <linux/module.h> 12 #include <linux/moduleparam.h> 13 #include <linux/init.h> 14 #include <linux/delay.h> 15 #include <linux/slab.h> 16 #include <linux/pm.h> 17 #include <linux/i2c.h> 18 #include <linux/clk.h> 19 #include <linux/regmap.h> 20 #include <linux/regulator/driver.h> 21 #include <linux/regulator/machine.h> 22 #include <linux/regulator/consumer.h> 23 #include <linux/of_device.h> 24 #include <sound/core.h> 25 #include <sound/tlv.h> 26 #include <sound/pcm.h> 27 #include <sound/pcm_params.h> 28 #include <sound/soc.h> 29 #include <sound/soc-dapm.h> 30 #include <sound/initval.h> 31 32 #include "sgtl5000.h" 33 34 #define SGTL5000_DAP_REG_OFFSET 0x0100 35 #define SGTL5000_MAX_REG_OFFSET 0x013A 36 37 /* default value of sgtl5000 registers */ 38 static const struct reg_default sgtl5000_reg_defaults[] = { 39 { SGTL5000_CHIP_CLK_CTRL, 0x0008 }, 40 { SGTL5000_CHIP_I2S_CTRL, 0x0010 }, 41 { SGTL5000_CHIP_SSS_CTRL, 0x0010 }, 42 { SGTL5000_CHIP_DAC_VOL, 0x3c3c }, 43 { SGTL5000_CHIP_PAD_STRENGTH, 0x015f }, 44 { SGTL5000_CHIP_ANA_HP_CTRL, 0x1818 }, 45 { SGTL5000_CHIP_ANA_CTRL, 0x0111 }, 46 { SGTL5000_CHIP_LINE_OUT_VOL, 0x0404 }, 47 { SGTL5000_CHIP_ANA_POWER, 0x7060 }, 48 { SGTL5000_CHIP_PLL_CTRL, 0x5000 }, 49 { SGTL5000_DAP_BASS_ENHANCE, 0x0040 }, 50 { SGTL5000_DAP_BASS_ENHANCE_CTRL, 0x051f }, 51 { SGTL5000_DAP_SURROUND, 0x0040 }, 52 { SGTL5000_DAP_EQ_BASS_BAND0, 0x002f }, 53 { SGTL5000_DAP_EQ_BASS_BAND1, 0x002f }, 54 { SGTL5000_DAP_EQ_BASS_BAND2, 0x002f }, 55 { SGTL5000_DAP_EQ_BASS_BAND3, 0x002f }, 56 { SGTL5000_DAP_EQ_BASS_BAND4, 0x002f }, 57 { SGTL5000_DAP_MAIN_CHAN, 0x8000 }, 58 { SGTL5000_DAP_AVC_CTRL, 0x0510 }, 59 { SGTL5000_DAP_AVC_THRESHOLD, 0x1473 }, 60 { SGTL5000_DAP_AVC_ATTACK, 0x0028 }, 61 { SGTL5000_DAP_AVC_DECAY, 0x0050 }, 62 }; 63 64 /* regulator supplies for sgtl5000, VDDD is an optional external supply */ 65 enum sgtl5000_regulator_supplies { 66 VDDA, 67 VDDIO, 68 VDDD, 69 SGTL5000_SUPPLY_NUM 70 }; 71 72 /* vddd is optional supply */ 73 static const char *supply_names[SGTL5000_SUPPLY_NUM] = { 74 "VDDA", 75 "VDDIO", 76 "VDDD" 77 }; 78 79 #define LDO_CONSUMER_NAME "VDDD_LDO" 80 #define LDO_VOLTAGE 1200000 81 82 static struct regulator_consumer_supply ldo_consumer[] = { 83 REGULATOR_SUPPLY(LDO_CONSUMER_NAME, NULL), 84 }; 85 86 static struct regulator_init_data ldo_init_data = { 87 .constraints = { 88 .min_uV = 1200000, 89 .max_uV = 1200000, 90 .valid_modes_mask = REGULATOR_MODE_NORMAL, 91 .valid_ops_mask = REGULATOR_CHANGE_STATUS, 92 }, 93 .num_consumer_supplies = 1, 94 .consumer_supplies = &ldo_consumer[0], 95 }; 96 97 /* 98 * sgtl5000 internal ldo regulator, 99 * enabled when VDDD not provided 100 */ 101 struct ldo_regulator { 102 struct regulator_desc desc; 103 struct regulator_dev *dev; 104 int voltage; 105 void *codec_data; 106 bool enabled; 107 }; 108 109 /* sgtl5000 private structure in codec */ 110 struct sgtl5000_priv { 111 int sysclk; /* sysclk rate */ 112 int master; /* i2s master or not */ 113 int fmt; /* i2s data format */ 114 struct regulator_bulk_data supplies[SGTL5000_SUPPLY_NUM]; 115 struct ldo_regulator *ldo; 116 struct regmap *regmap; 117 struct clk *mclk; 118 int revision; 119 }; 120 121 /* 122 * mic_bias power on/off share the same register bits with 123 * output impedance of mic bias, when power on mic bias, we 124 * need reclaim it to impedance value. 125 * 0x0 = Powered off 126 * 0x1 = 2Kohm 127 * 0x2 = 4Kohm 128 * 0x3 = 8Kohm 129 */ 130 static int mic_bias_event(struct snd_soc_dapm_widget *w, 131 struct snd_kcontrol *kcontrol, int event) 132 { 133 switch (event) { 134 case SND_SOC_DAPM_POST_PMU: 135 /* change mic bias resistor to 4Kohm */ 136 snd_soc_update_bits(w->codec, SGTL5000_CHIP_MIC_CTRL, 137 SGTL5000_BIAS_R_MASK, 138 SGTL5000_BIAS_R_4k << SGTL5000_BIAS_R_SHIFT); 139 break; 140 141 case SND_SOC_DAPM_PRE_PMD: 142 snd_soc_update_bits(w->codec, SGTL5000_CHIP_MIC_CTRL, 143 SGTL5000_BIAS_R_MASK, 0); 144 break; 145 } 146 return 0; 147 } 148 149 /* 150 * As manual described, ADC/DAC only works when VAG powerup, 151 * So enabled VAG before ADC/DAC up. 152 * In power down case, we need wait 400ms when vag fully ramped down. 153 */ 154 static int power_vag_event(struct snd_soc_dapm_widget *w, 155 struct snd_kcontrol *kcontrol, int event) 156 { 157 const u32 mask = SGTL5000_DAC_POWERUP | SGTL5000_ADC_POWERUP; 158 159 switch (event) { 160 case SND_SOC_DAPM_POST_PMU: 161 snd_soc_update_bits(w->codec, SGTL5000_CHIP_ANA_POWER, 162 SGTL5000_VAG_POWERUP, SGTL5000_VAG_POWERUP); 163 break; 164 165 case SND_SOC_DAPM_PRE_PMD: 166 /* 167 * Don't clear VAG_POWERUP, when both DAC and ADC are 168 * operational to prevent inadvertently starving the 169 * other one of them. 170 */ 171 if ((snd_soc_read(w->codec, SGTL5000_CHIP_ANA_POWER) & 172 mask) != mask) { 173 snd_soc_update_bits(w->codec, SGTL5000_CHIP_ANA_POWER, 174 SGTL5000_VAG_POWERUP, 0); 175 msleep(400); 176 } 177 break; 178 default: 179 break; 180 } 181 182 return 0; 183 } 184 185 /* input sources for ADC */ 186 static const char *adc_mux_text[] = { 187 "MIC_IN", "LINE_IN" 188 }; 189 190 static const struct soc_enum adc_enum = 191 SOC_ENUM_SINGLE(SGTL5000_CHIP_ANA_CTRL, 2, 2, adc_mux_text); 192 193 static const struct snd_kcontrol_new adc_mux = 194 SOC_DAPM_ENUM("Capture Mux", adc_enum); 195 196 /* input sources for DAC */ 197 static const char *dac_mux_text[] = { 198 "DAC", "LINE_IN" 199 }; 200 201 static const struct soc_enum dac_enum = 202 SOC_ENUM_SINGLE(SGTL5000_CHIP_ANA_CTRL, 6, 2, dac_mux_text); 203 204 static const struct snd_kcontrol_new dac_mux = 205 SOC_DAPM_ENUM("Headphone Mux", dac_enum); 206 207 static const struct snd_soc_dapm_widget sgtl5000_dapm_widgets[] = { 208 SND_SOC_DAPM_INPUT("LINE_IN"), 209 SND_SOC_DAPM_INPUT("MIC_IN"), 210 211 SND_SOC_DAPM_OUTPUT("HP_OUT"), 212 SND_SOC_DAPM_OUTPUT("LINE_OUT"), 213 214 SND_SOC_DAPM_SUPPLY("Mic Bias", SGTL5000_CHIP_MIC_CTRL, 8, 0, 215 mic_bias_event, 216 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 217 218 SND_SOC_DAPM_PGA("HP", SGTL5000_CHIP_ANA_POWER, 4, 0, NULL, 0), 219 SND_SOC_DAPM_PGA("LO", SGTL5000_CHIP_ANA_POWER, 0, 0, NULL, 0), 220 221 SND_SOC_DAPM_MUX("Capture Mux", SND_SOC_NOPM, 0, 0, &adc_mux), 222 SND_SOC_DAPM_MUX("Headphone Mux", SND_SOC_NOPM, 0, 0, &dac_mux), 223 224 /* aif for i2s input */ 225 SND_SOC_DAPM_AIF_IN("AIFIN", "Playback", 226 0, SGTL5000_CHIP_DIG_POWER, 227 0, 0), 228 229 /* aif for i2s output */ 230 SND_SOC_DAPM_AIF_OUT("AIFOUT", "Capture", 231 0, SGTL5000_CHIP_DIG_POWER, 232 1, 0), 233 234 SND_SOC_DAPM_ADC("ADC", "Capture", SGTL5000_CHIP_ANA_POWER, 1, 0), 235 SND_SOC_DAPM_DAC("DAC", "Playback", SGTL5000_CHIP_ANA_POWER, 3, 0), 236 237 SND_SOC_DAPM_PRE("VAG_POWER_PRE", power_vag_event), 238 SND_SOC_DAPM_POST("VAG_POWER_POST", power_vag_event), 239 }; 240 241 /* routes for sgtl5000 */ 242 static const struct snd_soc_dapm_route sgtl5000_dapm_routes[] = { 243 {"Capture Mux", "LINE_IN", "LINE_IN"}, /* line_in --> adc_mux */ 244 {"Capture Mux", "MIC_IN", "MIC_IN"}, /* mic_in --> adc_mux */ 245 246 {"ADC", NULL, "Capture Mux"}, /* adc_mux --> adc */ 247 {"AIFOUT", NULL, "ADC"}, /* adc --> i2s_out */ 248 249 {"DAC", NULL, "AIFIN"}, /* i2s-->dac,skip audio mux */ 250 {"Headphone Mux", "DAC", "DAC"}, /* dac --> hp_mux */ 251 {"LO", NULL, "DAC"}, /* dac --> line_out */ 252 253 {"Headphone Mux", "LINE_IN", "LINE_IN"},/* line_in --> hp_mux */ 254 {"HP", NULL, "Headphone Mux"}, /* hp_mux --> hp */ 255 256 {"LINE_OUT", NULL, "LO"}, 257 {"HP_OUT", NULL, "HP"}, 258 }; 259 260 /* custom function to fetch info of PCM playback volume */ 261 static int dac_info_volsw(struct snd_kcontrol *kcontrol, 262 struct snd_ctl_elem_info *uinfo) 263 { 264 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 265 uinfo->count = 2; 266 uinfo->value.integer.min = 0; 267 uinfo->value.integer.max = 0xfc - 0x3c; 268 return 0; 269 } 270 271 /* 272 * custom function to get of PCM playback volume 273 * 274 * dac volume register 275 * 15-------------8-7--------------0 276 * | R channel vol | L channel vol | 277 * ------------------------------- 278 * 279 * PCM volume with 0.5017 dB steps from 0 to -90 dB 280 * 281 * register values map to dB 282 * 0x3B and less = Reserved 283 * 0x3C = 0 dB 284 * 0x3D = -0.5 dB 285 * 0xF0 = -90 dB 286 * 0xFC and greater = Muted 287 * 288 * register value map to userspace value 289 * 290 * register value 0x3c(0dB) 0xf0(-90dB)0xfc 291 * ------------------------------ 292 * userspace value 0xc0 0 293 */ 294 static int dac_get_volsw(struct snd_kcontrol *kcontrol, 295 struct snd_ctl_elem_value *ucontrol) 296 { 297 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 298 int reg; 299 int l; 300 int r; 301 302 reg = snd_soc_read(codec, SGTL5000_CHIP_DAC_VOL); 303 304 /* get left channel volume */ 305 l = (reg & SGTL5000_DAC_VOL_LEFT_MASK) >> SGTL5000_DAC_VOL_LEFT_SHIFT; 306 307 /* get right channel volume */ 308 r = (reg & SGTL5000_DAC_VOL_RIGHT_MASK) >> SGTL5000_DAC_VOL_RIGHT_SHIFT; 309 310 /* make sure value fall in (0x3c,0xfc) */ 311 l = clamp(l, 0x3c, 0xfc); 312 r = clamp(r, 0x3c, 0xfc); 313 314 /* invert it and map to userspace value */ 315 l = 0xfc - l; 316 r = 0xfc - r; 317 318 ucontrol->value.integer.value[0] = l; 319 ucontrol->value.integer.value[1] = r; 320 321 return 0; 322 } 323 324 /* 325 * custom function to put of PCM playback volume 326 * 327 * dac volume register 328 * 15-------------8-7--------------0 329 * | R channel vol | L channel vol | 330 * ------------------------------- 331 * 332 * PCM volume with 0.5017 dB steps from 0 to -90 dB 333 * 334 * register values map to dB 335 * 0x3B and less = Reserved 336 * 0x3C = 0 dB 337 * 0x3D = -0.5 dB 338 * 0xF0 = -90 dB 339 * 0xFC and greater = Muted 340 * 341 * userspace value map to register value 342 * 343 * userspace value 0xc0 0 344 * ------------------------------ 345 * register value 0x3c(0dB) 0xf0(-90dB)0xfc 346 */ 347 static int dac_put_volsw(struct snd_kcontrol *kcontrol, 348 struct snd_ctl_elem_value *ucontrol) 349 { 350 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 351 int reg; 352 int l; 353 int r; 354 355 l = ucontrol->value.integer.value[0]; 356 r = ucontrol->value.integer.value[1]; 357 358 /* make sure userspace volume fall in (0, 0xfc-0x3c) */ 359 l = clamp(l, 0, 0xfc - 0x3c); 360 r = clamp(r, 0, 0xfc - 0x3c); 361 362 /* invert it, get the value can be set to register */ 363 l = 0xfc - l; 364 r = 0xfc - r; 365 366 /* shift to get the register value */ 367 reg = l << SGTL5000_DAC_VOL_LEFT_SHIFT | 368 r << SGTL5000_DAC_VOL_RIGHT_SHIFT; 369 370 snd_soc_write(codec, SGTL5000_CHIP_DAC_VOL, reg); 371 372 return 0; 373 } 374 375 static const DECLARE_TLV_DB_SCALE(capture_6db_attenuate, -600, 600, 0); 376 377 /* tlv for mic gain, 0db 20db 30db 40db */ 378 static const unsigned int mic_gain_tlv[] = { 379 TLV_DB_RANGE_HEAD(2), 380 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0), 381 1, 3, TLV_DB_SCALE_ITEM(2000, 1000, 0), 382 }; 383 384 /* tlv for hp volume, -51.5db to 12.0db, step .5db */ 385 static const DECLARE_TLV_DB_SCALE(headphone_volume, -5150, 50, 0); 386 387 static const struct snd_kcontrol_new sgtl5000_snd_controls[] = { 388 /* SOC_DOUBLE_S8_TLV with invert */ 389 { 390 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 391 .name = "PCM Playback Volume", 392 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ | 393 SNDRV_CTL_ELEM_ACCESS_READWRITE, 394 .info = dac_info_volsw, 395 .get = dac_get_volsw, 396 .put = dac_put_volsw, 397 }, 398 399 SOC_DOUBLE("Capture Volume", SGTL5000_CHIP_ANA_ADC_CTRL, 0, 4, 0xf, 0), 400 SOC_SINGLE_TLV("Capture Attenuate Switch (-6dB)", 401 SGTL5000_CHIP_ANA_ADC_CTRL, 402 8, 1, 0, capture_6db_attenuate), 403 SOC_SINGLE("Capture ZC Switch", SGTL5000_CHIP_ANA_CTRL, 1, 1, 0), 404 405 SOC_DOUBLE_TLV("Headphone Playback Volume", 406 SGTL5000_CHIP_ANA_HP_CTRL, 407 0, 8, 408 0x7f, 1, 409 headphone_volume), 410 SOC_SINGLE("Headphone Playback ZC Switch", SGTL5000_CHIP_ANA_CTRL, 411 5, 1, 0), 412 413 SOC_SINGLE_TLV("Mic Volume", SGTL5000_CHIP_MIC_CTRL, 414 0, 3, 0, mic_gain_tlv), 415 }; 416 417 /* mute the codec used by alsa core */ 418 static int sgtl5000_digital_mute(struct snd_soc_dai *codec_dai, int mute) 419 { 420 struct snd_soc_codec *codec = codec_dai->codec; 421 u16 adcdac_ctrl = SGTL5000_DAC_MUTE_LEFT | SGTL5000_DAC_MUTE_RIGHT; 422 423 snd_soc_update_bits(codec, SGTL5000_CHIP_ADCDAC_CTRL, 424 adcdac_ctrl, mute ? adcdac_ctrl : 0); 425 426 return 0; 427 } 428 429 /* set codec format */ 430 static int sgtl5000_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt) 431 { 432 struct snd_soc_codec *codec = codec_dai->codec; 433 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); 434 u16 i2sctl = 0; 435 436 sgtl5000->master = 0; 437 /* 438 * i2s clock and frame master setting. 439 * ONLY support: 440 * - clock and frame slave, 441 * - clock and frame master 442 */ 443 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 444 case SND_SOC_DAIFMT_CBS_CFS: 445 break; 446 case SND_SOC_DAIFMT_CBM_CFM: 447 i2sctl |= SGTL5000_I2S_MASTER; 448 sgtl5000->master = 1; 449 break; 450 default: 451 return -EINVAL; 452 } 453 454 /* setting i2s data format */ 455 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 456 case SND_SOC_DAIFMT_DSP_A: 457 i2sctl |= SGTL5000_I2S_MODE_PCM; 458 break; 459 case SND_SOC_DAIFMT_DSP_B: 460 i2sctl |= SGTL5000_I2S_MODE_PCM; 461 i2sctl |= SGTL5000_I2S_LRALIGN; 462 break; 463 case SND_SOC_DAIFMT_I2S: 464 i2sctl |= SGTL5000_I2S_MODE_I2S_LJ; 465 break; 466 case SND_SOC_DAIFMT_RIGHT_J: 467 i2sctl |= SGTL5000_I2S_MODE_RJ; 468 i2sctl |= SGTL5000_I2S_LRPOL; 469 break; 470 case SND_SOC_DAIFMT_LEFT_J: 471 i2sctl |= SGTL5000_I2S_MODE_I2S_LJ; 472 i2sctl |= SGTL5000_I2S_LRALIGN; 473 break; 474 default: 475 return -EINVAL; 476 } 477 478 sgtl5000->fmt = fmt & SND_SOC_DAIFMT_FORMAT_MASK; 479 480 /* Clock inversion */ 481 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 482 case SND_SOC_DAIFMT_NB_NF: 483 break; 484 case SND_SOC_DAIFMT_IB_NF: 485 i2sctl |= SGTL5000_I2S_SCLK_INV; 486 break; 487 default: 488 return -EINVAL; 489 } 490 491 snd_soc_write(codec, SGTL5000_CHIP_I2S_CTRL, i2sctl); 492 493 return 0; 494 } 495 496 /* set codec sysclk */ 497 static int sgtl5000_set_dai_sysclk(struct snd_soc_dai *codec_dai, 498 int clk_id, unsigned int freq, int dir) 499 { 500 struct snd_soc_codec *codec = codec_dai->codec; 501 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); 502 503 switch (clk_id) { 504 case SGTL5000_SYSCLK: 505 sgtl5000->sysclk = freq; 506 break; 507 default: 508 return -EINVAL; 509 } 510 511 return 0; 512 } 513 514 /* 515 * set clock according to i2s frame clock, 516 * sgtl5000 provide 2 clock sources. 517 * 1. sys_mclk. sample freq can only configure to 518 * 1/256, 1/384, 1/512 of sys_mclk. 519 * 2. pll. can derive any audio clocks. 520 * 521 * clock setting rules: 522 * 1. in slave mode, only sys_mclk can use. 523 * 2. as constraint by sys_mclk, sample freq should 524 * set to 32k, 44.1k and above. 525 * 3. using sys_mclk prefer to pll to save power. 526 */ 527 static int sgtl5000_set_clock(struct snd_soc_codec *codec, int frame_rate) 528 { 529 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); 530 int clk_ctl = 0; 531 int sys_fs; /* sample freq */ 532 533 /* 534 * sample freq should be divided by frame clock, 535 * if frame clock lower than 44.1khz, sample feq should set to 536 * 32khz or 44.1khz. 537 */ 538 switch (frame_rate) { 539 case 8000: 540 case 16000: 541 sys_fs = 32000; 542 break; 543 case 11025: 544 case 22050: 545 sys_fs = 44100; 546 break; 547 default: 548 sys_fs = frame_rate; 549 break; 550 } 551 552 /* set divided factor of frame clock */ 553 switch (sys_fs / frame_rate) { 554 case 4: 555 clk_ctl |= SGTL5000_RATE_MODE_DIV_4 << SGTL5000_RATE_MODE_SHIFT; 556 break; 557 case 2: 558 clk_ctl |= SGTL5000_RATE_MODE_DIV_2 << SGTL5000_RATE_MODE_SHIFT; 559 break; 560 case 1: 561 clk_ctl |= SGTL5000_RATE_MODE_DIV_1 << SGTL5000_RATE_MODE_SHIFT; 562 break; 563 default: 564 return -EINVAL; 565 } 566 567 /* set the sys_fs according to frame rate */ 568 switch (sys_fs) { 569 case 32000: 570 clk_ctl |= SGTL5000_SYS_FS_32k << SGTL5000_SYS_FS_SHIFT; 571 break; 572 case 44100: 573 clk_ctl |= SGTL5000_SYS_FS_44_1k << SGTL5000_SYS_FS_SHIFT; 574 break; 575 case 48000: 576 clk_ctl |= SGTL5000_SYS_FS_48k << SGTL5000_SYS_FS_SHIFT; 577 break; 578 case 96000: 579 clk_ctl |= SGTL5000_SYS_FS_96k << SGTL5000_SYS_FS_SHIFT; 580 break; 581 default: 582 dev_err(codec->dev, "frame rate %d not supported\n", 583 frame_rate); 584 return -EINVAL; 585 } 586 587 /* 588 * calculate the divider of mclk/sample_freq, 589 * factor of freq =96k can only be 256, since mclk in range (12m,27m) 590 */ 591 switch (sgtl5000->sysclk / sys_fs) { 592 case 256: 593 clk_ctl |= SGTL5000_MCLK_FREQ_256FS << 594 SGTL5000_MCLK_FREQ_SHIFT; 595 break; 596 case 384: 597 clk_ctl |= SGTL5000_MCLK_FREQ_384FS << 598 SGTL5000_MCLK_FREQ_SHIFT; 599 break; 600 case 512: 601 clk_ctl |= SGTL5000_MCLK_FREQ_512FS << 602 SGTL5000_MCLK_FREQ_SHIFT; 603 break; 604 default: 605 /* if mclk not satisify the divider, use pll */ 606 if (sgtl5000->master) { 607 clk_ctl |= SGTL5000_MCLK_FREQ_PLL << 608 SGTL5000_MCLK_FREQ_SHIFT; 609 } else { 610 dev_err(codec->dev, 611 "PLL not supported in slave mode\n"); 612 return -EINVAL; 613 } 614 } 615 616 /* if using pll, please check manual 6.4.2 for detail */ 617 if ((clk_ctl & SGTL5000_MCLK_FREQ_MASK) == SGTL5000_MCLK_FREQ_PLL) { 618 u64 out, t; 619 int div2; 620 int pll_ctl; 621 unsigned int in, int_div, frac_div; 622 623 if (sgtl5000->sysclk > 17000000) { 624 div2 = 1; 625 in = sgtl5000->sysclk / 2; 626 } else { 627 div2 = 0; 628 in = sgtl5000->sysclk; 629 } 630 if (sys_fs == 44100) 631 out = 180633600; 632 else 633 out = 196608000; 634 t = do_div(out, in); 635 int_div = out; 636 t *= 2048; 637 do_div(t, in); 638 frac_div = t; 639 pll_ctl = int_div << SGTL5000_PLL_INT_DIV_SHIFT | 640 frac_div << SGTL5000_PLL_FRAC_DIV_SHIFT; 641 642 snd_soc_write(codec, SGTL5000_CHIP_PLL_CTRL, pll_ctl); 643 if (div2) 644 snd_soc_update_bits(codec, 645 SGTL5000_CHIP_CLK_TOP_CTRL, 646 SGTL5000_INPUT_FREQ_DIV2, 647 SGTL5000_INPUT_FREQ_DIV2); 648 else 649 snd_soc_update_bits(codec, 650 SGTL5000_CHIP_CLK_TOP_CTRL, 651 SGTL5000_INPUT_FREQ_DIV2, 652 0); 653 654 /* power up pll */ 655 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER, 656 SGTL5000_PLL_POWERUP | SGTL5000_VCOAMP_POWERUP, 657 SGTL5000_PLL_POWERUP | SGTL5000_VCOAMP_POWERUP); 658 659 /* if using pll, clk_ctrl must be set after pll power up */ 660 snd_soc_write(codec, SGTL5000_CHIP_CLK_CTRL, clk_ctl); 661 } else { 662 /* otherwise, clk_ctrl must be set before pll power down */ 663 snd_soc_write(codec, SGTL5000_CHIP_CLK_CTRL, clk_ctl); 664 665 /* power down pll */ 666 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER, 667 SGTL5000_PLL_POWERUP | SGTL5000_VCOAMP_POWERUP, 668 0); 669 } 670 671 return 0; 672 } 673 674 /* 675 * Set PCM DAI bit size and sample rate. 676 * input: params_rate, params_fmt 677 */ 678 static int sgtl5000_pcm_hw_params(struct snd_pcm_substream *substream, 679 struct snd_pcm_hw_params *params, 680 struct snd_soc_dai *dai) 681 { 682 struct snd_soc_codec *codec = dai->codec; 683 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); 684 int channels = params_channels(params); 685 int i2s_ctl = 0; 686 int stereo; 687 int ret; 688 689 /* sysclk should already set */ 690 if (!sgtl5000->sysclk) { 691 dev_err(codec->dev, "%s: set sysclk first!\n", __func__); 692 return -EFAULT; 693 } 694 695 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 696 stereo = SGTL5000_DAC_STEREO; 697 else 698 stereo = SGTL5000_ADC_STEREO; 699 700 /* set mono to save power */ 701 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER, stereo, 702 channels == 1 ? 0 : stereo); 703 704 /* set codec clock base on lrclk */ 705 ret = sgtl5000_set_clock(codec, params_rate(params)); 706 if (ret) 707 return ret; 708 709 /* set i2s data format */ 710 switch (params_format(params)) { 711 case SNDRV_PCM_FORMAT_S16_LE: 712 if (sgtl5000->fmt == SND_SOC_DAIFMT_RIGHT_J) 713 return -EINVAL; 714 i2s_ctl |= SGTL5000_I2S_DLEN_16 << SGTL5000_I2S_DLEN_SHIFT; 715 i2s_ctl |= SGTL5000_I2S_SCLKFREQ_32FS << 716 SGTL5000_I2S_SCLKFREQ_SHIFT; 717 break; 718 case SNDRV_PCM_FORMAT_S20_3LE: 719 i2s_ctl |= SGTL5000_I2S_DLEN_20 << SGTL5000_I2S_DLEN_SHIFT; 720 i2s_ctl |= SGTL5000_I2S_SCLKFREQ_64FS << 721 SGTL5000_I2S_SCLKFREQ_SHIFT; 722 break; 723 case SNDRV_PCM_FORMAT_S24_LE: 724 i2s_ctl |= SGTL5000_I2S_DLEN_24 << SGTL5000_I2S_DLEN_SHIFT; 725 i2s_ctl |= SGTL5000_I2S_SCLKFREQ_64FS << 726 SGTL5000_I2S_SCLKFREQ_SHIFT; 727 break; 728 case SNDRV_PCM_FORMAT_S32_LE: 729 if (sgtl5000->fmt == SND_SOC_DAIFMT_RIGHT_J) 730 return -EINVAL; 731 i2s_ctl |= SGTL5000_I2S_DLEN_32 << SGTL5000_I2S_DLEN_SHIFT; 732 i2s_ctl |= SGTL5000_I2S_SCLKFREQ_64FS << 733 SGTL5000_I2S_SCLKFREQ_SHIFT; 734 break; 735 default: 736 return -EINVAL; 737 } 738 739 snd_soc_update_bits(codec, SGTL5000_CHIP_I2S_CTRL, 740 SGTL5000_I2S_DLEN_MASK | SGTL5000_I2S_SCLKFREQ_MASK, 741 i2s_ctl); 742 743 return 0; 744 } 745 746 #ifdef CONFIG_REGULATOR 747 static int ldo_regulator_is_enabled(struct regulator_dev *dev) 748 { 749 struct ldo_regulator *ldo = rdev_get_drvdata(dev); 750 751 return ldo->enabled; 752 } 753 754 static int ldo_regulator_enable(struct regulator_dev *dev) 755 { 756 struct ldo_regulator *ldo = rdev_get_drvdata(dev); 757 struct snd_soc_codec *codec = (struct snd_soc_codec *)ldo->codec_data; 758 int reg; 759 760 if (ldo_regulator_is_enabled(dev)) 761 return 0; 762 763 /* set regulator value firstly */ 764 reg = (1600 - ldo->voltage / 1000) / 50; 765 reg = clamp(reg, 0x0, 0xf); 766 767 /* amend the voltage value, unit: uV */ 768 ldo->voltage = (1600 - reg * 50) * 1000; 769 770 /* set voltage to register */ 771 snd_soc_update_bits(codec, SGTL5000_CHIP_LINREG_CTRL, 772 SGTL5000_LINREG_VDDD_MASK, reg); 773 774 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER, 775 SGTL5000_LINEREG_D_POWERUP, 776 SGTL5000_LINEREG_D_POWERUP); 777 778 /* when internal ldo enabled, simple digital power can be disabled */ 779 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER, 780 SGTL5000_LINREG_SIMPLE_POWERUP, 781 0); 782 783 ldo->enabled = 1; 784 return 0; 785 } 786 787 static int ldo_regulator_disable(struct regulator_dev *dev) 788 { 789 struct ldo_regulator *ldo = rdev_get_drvdata(dev); 790 struct snd_soc_codec *codec = (struct snd_soc_codec *)ldo->codec_data; 791 792 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER, 793 SGTL5000_LINEREG_D_POWERUP, 794 0); 795 796 /* clear voltage info */ 797 snd_soc_update_bits(codec, SGTL5000_CHIP_LINREG_CTRL, 798 SGTL5000_LINREG_VDDD_MASK, 0); 799 800 ldo->enabled = 0; 801 802 return 0; 803 } 804 805 static int ldo_regulator_get_voltage(struct regulator_dev *dev) 806 { 807 struct ldo_regulator *ldo = rdev_get_drvdata(dev); 808 809 return ldo->voltage; 810 } 811 812 static struct regulator_ops ldo_regulator_ops = { 813 .is_enabled = ldo_regulator_is_enabled, 814 .enable = ldo_regulator_enable, 815 .disable = ldo_regulator_disable, 816 .get_voltage = ldo_regulator_get_voltage, 817 }; 818 819 static int ldo_regulator_register(struct snd_soc_codec *codec, 820 struct regulator_init_data *init_data, 821 int voltage) 822 { 823 struct ldo_regulator *ldo; 824 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); 825 struct regulator_config config = { }; 826 827 ldo = kzalloc(sizeof(struct ldo_regulator), GFP_KERNEL); 828 829 if (!ldo) { 830 dev_err(codec->dev, "failed to allocate ldo_regulator\n"); 831 return -ENOMEM; 832 } 833 834 ldo->desc.name = kstrdup(dev_name(codec->dev), GFP_KERNEL); 835 if (!ldo->desc.name) { 836 kfree(ldo); 837 dev_err(codec->dev, "failed to allocate decs name memory\n"); 838 return -ENOMEM; 839 } 840 841 ldo->desc.type = REGULATOR_VOLTAGE; 842 ldo->desc.owner = THIS_MODULE; 843 ldo->desc.ops = &ldo_regulator_ops; 844 ldo->desc.n_voltages = 1; 845 846 ldo->codec_data = codec; 847 ldo->voltage = voltage; 848 849 config.dev = codec->dev; 850 config.driver_data = ldo; 851 config.init_data = init_data; 852 853 ldo->dev = regulator_register(&ldo->desc, &config); 854 if (IS_ERR(ldo->dev)) { 855 int ret = PTR_ERR(ldo->dev); 856 857 dev_err(codec->dev, "failed to register regulator\n"); 858 kfree(ldo->desc.name); 859 kfree(ldo); 860 861 return ret; 862 } 863 sgtl5000->ldo = ldo; 864 865 return 0; 866 } 867 868 static int ldo_regulator_remove(struct snd_soc_codec *codec) 869 { 870 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); 871 struct ldo_regulator *ldo = sgtl5000->ldo; 872 873 if (!ldo) 874 return 0; 875 876 regulator_unregister(ldo->dev); 877 kfree(ldo->desc.name); 878 kfree(ldo); 879 880 return 0; 881 } 882 #else 883 static int ldo_regulator_register(struct snd_soc_codec *codec, 884 struct regulator_init_data *init_data, 885 int voltage) 886 { 887 dev_err(codec->dev, "this setup needs regulator support in the kernel\n"); 888 return -EINVAL; 889 } 890 891 static int ldo_regulator_remove(struct snd_soc_codec *codec) 892 { 893 return 0; 894 } 895 #endif 896 897 /* 898 * set dac bias 899 * common state changes: 900 * startup: 901 * off --> standby --> prepare --> on 902 * standby --> prepare --> on 903 * 904 * stop: 905 * on --> prepare --> standby 906 */ 907 static int sgtl5000_set_bias_level(struct snd_soc_codec *codec, 908 enum snd_soc_bias_level level) 909 { 910 int ret; 911 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); 912 913 switch (level) { 914 case SND_SOC_BIAS_ON: 915 case SND_SOC_BIAS_PREPARE: 916 break; 917 case SND_SOC_BIAS_STANDBY: 918 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) { 919 ret = regulator_bulk_enable( 920 ARRAY_SIZE(sgtl5000->supplies), 921 sgtl5000->supplies); 922 if (ret) 923 return ret; 924 udelay(10); 925 926 regcache_cache_only(sgtl5000->regmap, false); 927 928 ret = regcache_sync(sgtl5000->regmap); 929 if (ret != 0) { 930 dev_err(codec->dev, 931 "Failed to restore cache: %d\n", ret); 932 933 regcache_cache_only(sgtl5000->regmap, true); 934 regulator_bulk_disable(ARRAY_SIZE(sgtl5000->supplies), 935 sgtl5000->supplies); 936 937 return ret; 938 } 939 } 940 941 break; 942 case SND_SOC_BIAS_OFF: 943 regcache_cache_only(sgtl5000->regmap, true); 944 regulator_bulk_disable(ARRAY_SIZE(sgtl5000->supplies), 945 sgtl5000->supplies); 946 break; 947 } 948 949 codec->dapm.bias_level = level; 950 return 0; 951 } 952 953 #define SGTL5000_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ 954 SNDRV_PCM_FMTBIT_S20_3LE |\ 955 SNDRV_PCM_FMTBIT_S24_LE |\ 956 SNDRV_PCM_FMTBIT_S32_LE) 957 958 static const struct snd_soc_dai_ops sgtl5000_ops = { 959 .hw_params = sgtl5000_pcm_hw_params, 960 .digital_mute = sgtl5000_digital_mute, 961 .set_fmt = sgtl5000_set_dai_fmt, 962 .set_sysclk = sgtl5000_set_dai_sysclk, 963 }; 964 965 static struct snd_soc_dai_driver sgtl5000_dai = { 966 .name = "sgtl5000", 967 .playback = { 968 .stream_name = "Playback", 969 .channels_min = 1, 970 .channels_max = 2, 971 /* 972 * only support 8~48K + 96K, 973 * TODO modify hw_param to support more 974 */ 975 .rates = SNDRV_PCM_RATE_8000_48000 | SNDRV_PCM_RATE_96000, 976 .formats = SGTL5000_FORMATS, 977 }, 978 .capture = { 979 .stream_name = "Capture", 980 .channels_min = 1, 981 .channels_max = 2, 982 .rates = SNDRV_PCM_RATE_8000_48000 | SNDRV_PCM_RATE_96000, 983 .formats = SGTL5000_FORMATS, 984 }, 985 .ops = &sgtl5000_ops, 986 .symmetric_rates = 1, 987 }; 988 989 static bool sgtl5000_volatile(struct device *dev, unsigned int reg) 990 { 991 switch (reg) { 992 case SGTL5000_CHIP_ID: 993 case SGTL5000_CHIP_ADCDAC_CTRL: 994 case SGTL5000_CHIP_ANA_STATUS: 995 return true; 996 } 997 998 return false; 999 } 1000 1001 static bool sgtl5000_readable(struct device *dev, unsigned int reg) 1002 { 1003 switch (reg) { 1004 case SGTL5000_CHIP_ID: 1005 case SGTL5000_CHIP_DIG_POWER: 1006 case SGTL5000_CHIP_CLK_CTRL: 1007 case SGTL5000_CHIP_I2S_CTRL: 1008 case SGTL5000_CHIP_SSS_CTRL: 1009 case SGTL5000_CHIP_ADCDAC_CTRL: 1010 case SGTL5000_CHIP_DAC_VOL: 1011 case SGTL5000_CHIP_PAD_STRENGTH: 1012 case SGTL5000_CHIP_ANA_ADC_CTRL: 1013 case SGTL5000_CHIP_ANA_HP_CTRL: 1014 case SGTL5000_CHIP_ANA_CTRL: 1015 case SGTL5000_CHIP_LINREG_CTRL: 1016 case SGTL5000_CHIP_REF_CTRL: 1017 case SGTL5000_CHIP_MIC_CTRL: 1018 case SGTL5000_CHIP_LINE_OUT_CTRL: 1019 case SGTL5000_CHIP_LINE_OUT_VOL: 1020 case SGTL5000_CHIP_ANA_POWER: 1021 case SGTL5000_CHIP_PLL_CTRL: 1022 case SGTL5000_CHIP_CLK_TOP_CTRL: 1023 case SGTL5000_CHIP_ANA_STATUS: 1024 case SGTL5000_CHIP_SHORT_CTRL: 1025 case SGTL5000_CHIP_ANA_TEST2: 1026 case SGTL5000_DAP_CTRL: 1027 case SGTL5000_DAP_PEQ: 1028 case SGTL5000_DAP_BASS_ENHANCE: 1029 case SGTL5000_DAP_BASS_ENHANCE_CTRL: 1030 case SGTL5000_DAP_AUDIO_EQ: 1031 case SGTL5000_DAP_SURROUND: 1032 case SGTL5000_DAP_FLT_COEF_ACCESS: 1033 case SGTL5000_DAP_COEF_WR_B0_MSB: 1034 case SGTL5000_DAP_COEF_WR_B0_LSB: 1035 case SGTL5000_DAP_EQ_BASS_BAND0: 1036 case SGTL5000_DAP_EQ_BASS_BAND1: 1037 case SGTL5000_DAP_EQ_BASS_BAND2: 1038 case SGTL5000_DAP_EQ_BASS_BAND3: 1039 case SGTL5000_DAP_EQ_BASS_BAND4: 1040 case SGTL5000_DAP_MAIN_CHAN: 1041 case SGTL5000_DAP_MIX_CHAN: 1042 case SGTL5000_DAP_AVC_CTRL: 1043 case SGTL5000_DAP_AVC_THRESHOLD: 1044 case SGTL5000_DAP_AVC_ATTACK: 1045 case SGTL5000_DAP_AVC_DECAY: 1046 case SGTL5000_DAP_COEF_WR_B1_MSB: 1047 case SGTL5000_DAP_COEF_WR_B1_LSB: 1048 case SGTL5000_DAP_COEF_WR_B2_MSB: 1049 case SGTL5000_DAP_COEF_WR_B2_LSB: 1050 case SGTL5000_DAP_COEF_WR_A1_MSB: 1051 case SGTL5000_DAP_COEF_WR_A1_LSB: 1052 case SGTL5000_DAP_COEF_WR_A2_MSB: 1053 case SGTL5000_DAP_COEF_WR_A2_LSB: 1054 return true; 1055 1056 default: 1057 return false; 1058 } 1059 } 1060 1061 #ifdef CONFIG_SUSPEND 1062 static int sgtl5000_suspend(struct snd_soc_codec *codec) 1063 { 1064 sgtl5000_set_bias_level(codec, SND_SOC_BIAS_OFF); 1065 1066 return 0; 1067 } 1068 1069 /* 1070 * restore all sgtl5000 registers, 1071 * since a big hole between dap and regular registers, 1072 * we will restore them respectively. 1073 */ 1074 static int sgtl5000_restore_regs(struct snd_soc_codec *codec) 1075 { 1076 u16 *cache = codec->reg_cache; 1077 u16 reg; 1078 1079 /* restore regular registers */ 1080 for (reg = 0; reg <= SGTL5000_CHIP_SHORT_CTRL; reg += 2) { 1081 1082 /* These regs should restore in particular order */ 1083 if (reg == SGTL5000_CHIP_ANA_POWER || 1084 reg == SGTL5000_CHIP_CLK_CTRL || 1085 reg == SGTL5000_CHIP_LINREG_CTRL || 1086 reg == SGTL5000_CHIP_LINE_OUT_CTRL || 1087 reg == SGTL5000_CHIP_REF_CTRL) 1088 continue; 1089 1090 snd_soc_write(codec, reg, cache[reg]); 1091 } 1092 1093 /* restore dap registers */ 1094 for (reg = SGTL5000_DAP_REG_OFFSET; reg < SGTL5000_MAX_REG_OFFSET; reg += 2) 1095 snd_soc_write(codec, reg, cache[reg]); 1096 1097 /* 1098 * restore these regs according to the power setting sequence in 1099 * sgtl5000_set_power_regs() and clock setting sequence in 1100 * sgtl5000_set_clock(). 1101 * 1102 * The order of restore is: 1103 * 1. SGTL5000_CHIP_CLK_CTRL MCLK_FREQ bits (1:0) should be restore after 1104 * SGTL5000_CHIP_ANA_POWER PLL bits set 1105 * 2. SGTL5000_CHIP_LINREG_CTRL should be set before 1106 * SGTL5000_CHIP_ANA_POWER LINREG_D restored 1107 * 3. SGTL5000_CHIP_REF_CTRL controls Analog Ground Voltage, 1108 * prefer to resotre it after SGTL5000_CHIP_ANA_POWER restored 1109 */ 1110 snd_soc_write(codec, SGTL5000_CHIP_LINREG_CTRL, 1111 cache[SGTL5000_CHIP_LINREG_CTRL]); 1112 1113 snd_soc_write(codec, SGTL5000_CHIP_ANA_POWER, 1114 cache[SGTL5000_CHIP_ANA_POWER]); 1115 1116 snd_soc_write(codec, SGTL5000_CHIP_CLK_CTRL, 1117 cache[SGTL5000_CHIP_CLK_CTRL]); 1118 1119 snd_soc_write(codec, SGTL5000_CHIP_REF_CTRL, 1120 cache[SGTL5000_CHIP_REF_CTRL]); 1121 1122 snd_soc_write(codec, SGTL5000_CHIP_LINE_OUT_CTRL, 1123 cache[SGTL5000_CHIP_LINE_OUT_CTRL]); 1124 return 0; 1125 } 1126 1127 static int sgtl5000_resume(struct snd_soc_codec *codec) 1128 { 1129 /* Bring the codec back up to standby to enable regulators */ 1130 sgtl5000_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 1131 1132 /* Restore registers by cached in memory */ 1133 sgtl5000_restore_regs(codec); 1134 return 0; 1135 } 1136 #else 1137 #define sgtl5000_suspend NULL 1138 #define sgtl5000_resume NULL 1139 #endif /* CONFIG_SUSPEND */ 1140 1141 /* 1142 * sgtl5000 has 3 internal power supplies: 1143 * 1. VAG, normally set to vdda/2 1144 * 2. chargepump, set to different value 1145 * according to voltage of vdda and vddio 1146 * 3. line out VAG, normally set to vddio/2 1147 * 1148 * and should be set according to: 1149 * 1. vddd provided by external or not 1150 * 2. vdda and vddio voltage value. > 3.1v or not 1151 * 3. chip revision >=0x11 or not. If >=0x11, not use external vddd. 1152 */ 1153 static int sgtl5000_set_power_regs(struct snd_soc_codec *codec) 1154 { 1155 int vddd; 1156 int vdda; 1157 int vddio; 1158 u16 ana_pwr; 1159 u16 lreg_ctrl; 1160 int vag; 1161 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); 1162 1163 vdda = regulator_get_voltage(sgtl5000->supplies[VDDA].consumer); 1164 vddio = regulator_get_voltage(sgtl5000->supplies[VDDIO].consumer); 1165 vddd = regulator_get_voltage(sgtl5000->supplies[VDDD].consumer); 1166 1167 vdda = vdda / 1000; 1168 vddio = vddio / 1000; 1169 vddd = vddd / 1000; 1170 1171 if (vdda <= 0 || vddio <= 0 || vddd < 0) { 1172 dev_err(codec->dev, "regulator voltage not set correctly\n"); 1173 1174 return -EINVAL; 1175 } 1176 1177 /* according to datasheet, maximum voltage of supplies */ 1178 if (vdda > 3600 || vddio > 3600 || vddd > 1980) { 1179 dev_err(codec->dev, 1180 "exceed max voltage vdda %dmV vddio %dmV vddd %dmV\n", 1181 vdda, vddio, vddd); 1182 1183 return -EINVAL; 1184 } 1185 1186 /* reset value */ 1187 ana_pwr = snd_soc_read(codec, SGTL5000_CHIP_ANA_POWER); 1188 ana_pwr |= SGTL5000_DAC_STEREO | 1189 SGTL5000_ADC_STEREO | 1190 SGTL5000_REFTOP_POWERUP; 1191 lreg_ctrl = snd_soc_read(codec, SGTL5000_CHIP_LINREG_CTRL); 1192 1193 if (vddio < 3100 && vdda < 3100) { 1194 /* enable internal oscillator used for charge pump */ 1195 snd_soc_update_bits(codec, SGTL5000_CHIP_CLK_TOP_CTRL, 1196 SGTL5000_INT_OSC_EN, 1197 SGTL5000_INT_OSC_EN); 1198 /* Enable VDDC charge pump */ 1199 ana_pwr |= SGTL5000_VDDC_CHRGPMP_POWERUP; 1200 } else if (vddio >= 3100 && vdda >= 3100) { 1201 /* 1202 * if vddio and vddd > 3.1v, 1203 * charge pump should be clean before set ana_pwr 1204 */ 1205 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER, 1206 SGTL5000_VDDC_CHRGPMP_POWERUP, 0); 1207 1208 /* VDDC use VDDIO rail */ 1209 lreg_ctrl |= SGTL5000_VDDC_ASSN_OVRD; 1210 lreg_ctrl |= SGTL5000_VDDC_MAN_ASSN_VDDIO << 1211 SGTL5000_VDDC_MAN_ASSN_SHIFT; 1212 } 1213 1214 snd_soc_write(codec, SGTL5000_CHIP_LINREG_CTRL, lreg_ctrl); 1215 1216 snd_soc_write(codec, SGTL5000_CHIP_ANA_POWER, ana_pwr); 1217 1218 /* set voltage to register */ 1219 snd_soc_update_bits(codec, SGTL5000_CHIP_LINREG_CTRL, 1220 SGTL5000_LINREG_VDDD_MASK, 0x8); 1221 1222 /* 1223 * if vddd linear reg has been enabled, 1224 * simple digital supply should be clear to get 1225 * proper VDDD voltage. 1226 */ 1227 if (ana_pwr & SGTL5000_LINEREG_D_POWERUP) 1228 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER, 1229 SGTL5000_LINREG_SIMPLE_POWERUP, 1230 0); 1231 else 1232 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER, 1233 SGTL5000_LINREG_SIMPLE_POWERUP | 1234 SGTL5000_STARTUP_POWERUP, 1235 0); 1236 1237 /* 1238 * set ADC/DAC VAG to vdda / 2, 1239 * should stay in range (0.8v, 1.575v) 1240 */ 1241 vag = vdda / 2; 1242 if (vag <= SGTL5000_ANA_GND_BASE) 1243 vag = 0; 1244 else if (vag >= SGTL5000_ANA_GND_BASE + SGTL5000_ANA_GND_STP * 1245 (SGTL5000_ANA_GND_MASK >> SGTL5000_ANA_GND_SHIFT)) 1246 vag = SGTL5000_ANA_GND_MASK >> SGTL5000_ANA_GND_SHIFT; 1247 else 1248 vag = (vag - SGTL5000_ANA_GND_BASE) / SGTL5000_ANA_GND_STP; 1249 1250 snd_soc_update_bits(codec, SGTL5000_CHIP_REF_CTRL, 1251 SGTL5000_ANA_GND_MASK, vag << SGTL5000_ANA_GND_SHIFT); 1252 1253 /* set line out VAG to vddio / 2, in range (0.8v, 1.675v) */ 1254 vag = vddio / 2; 1255 if (vag <= SGTL5000_LINE_OUT_GND_BASE) 1256 vag = 0; 1257 else if (vag >= SGTL5000_LINE_OUT_GND_BASE + 1258 SGTL5000_LINE_OUT_GND_STP * SGTL5000_LINE_OUT_GND_MAX) 1259 vag = SGTL5000_LINE_OUT_GND_MAX; 1260 else 1261 vag = (vag - SGTL5000_LINE_OUT_GND_BASE) / 1262 SGTL5000_LINE_OUT_GND_STP; 1263 1264 snd_soc_update_bits(codec, SGTL5000_CHIP_LINE_OUT_CTRL, 1265 SGTL5000_LINE_OUT_CURRENT_MASK | 1266 SGTL5000_LINE_OUT_GND_MASK, 1267 vag << SGTL5000_LINE_OUT_GND_SHIFT | 1268 SGTL5000_LINE_OUT_CURRENT_360u << 1269 SGTL5000_LINE_OUT_CURRENT_SHIFT); 1270 1271 return 0; 1272 } 1273 1274 static int sgtl5000_replace_vddd_with_ldo(struct snd_soc_codec *codec) 1275 { 1276 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); 1277 int ret; 1278 1279 /* set internal ldo to 1.2v */ 1280 ret = ldo_regulator_register(codec, &ldo_init_data, LDO_VOLTAGE); 1281 if (ret) { 1282 dev_err(codec->dev, 1283 "Failed to register vddd internal supplies: %d\n", ret); 1284 return ret; 1285 } 1286 1287 sgtl5000->supplies[VDDD].supply = LDO_CONSUMER_NAME; 1288 1289 dev_info(codec->dev, "Using internal LDO instead of VDDD\n"); 1290 return 0; 1291 } 1292 1293 static int sgtl5000_enable_regulators(struct snd_soc_codec *codec) 1294 { 1295 int ret; 1296 int i; 1297 int external_vddd = 0; 1298 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); 1299 struct regulator *vddd; 1300 1301 for (i = 0; i < ARRAY_SIZE(sgtl5000->supplies); i++) 1302 sgtl5000->supplies[i].supply = supply_names[i]; 1303 1304 /* External VDDD only works before revision 0x11 */ 1305 if (sgtl5000->revision < 0x11) { 1306 vddd = regulator_get_optional(codec->dev, "VDDD"); 1307 if (IS_ERR(vddd)) { 1308 /* See if it's just not registered yet */ 1309 if (PTR_ERR(vddd) == -EPROBE_DEFER) 1310 return -EPROBE_DEFER; 1311 } else { 1312 external_vddd = 1; 1313 regulator_put(vddd); 1314 } 1315 } 1316 1317 if (!external_vddd) { 1318 ret = sgtl5000_replace_vddd_with_ldo(codec); 1319 if (ret) 1320 return ret; 1321 } 1322 1323 ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(sgtl5000->supplies), 1324 sgtl5000->supplies); 1325 if (ret) 1326 goto err_ldo_remove; 1327 1328 ret = regulator_bulk_enable(ARRAY_SIZE(sgtl5000->supplies), 1329 sgtl5000->supplies); 1330 if (ret) 1331 goto err_regulator_free; 1332 1333 /* wait for all power rails bring up */ 1334 udelay(10); 1335 1336 return 0; 1337 1338 err_regulator_free: 1339 regulator_bulk_free(ARRAY_SIZE(sgtl5000->supplies), 1340 sgtl5000->supplies); 1341 err_ldo_remove: 1342 if (!external_vddd) 1343 ldo_regulator_remove(codec); 1344 return ret; 1345 1346 } 1347 1348 static int sgtl5000_probe(struct snd_soc_codec *codec) 1349 { 1350 int ret; 1351 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); 1352 1353 /* setup i2c data ops */ 1354 codec->control_data = sgtl5000->regmap; 1355 ret = snd_soc_codec_set_cache_io(codec, 16, 16, SND_SOC_REGMAP); 1356 if (ret < 0) { 1357 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret); 1358 return ret; 1359 } 1360 1361 ret = sgtl5000_enable_regulators(codec); 1362 if (ret) 1363 return ret; 1364 1365 /* power up sgtl5000 */ 1366 ret = sgtl5000_set_power_regs(codec); 1367 if (ret) 1368 goto err; 1369 1370 /* enable small pop, introduce 400ms delay in turning off */ 1371 snd_soc_update_bits(codec, SGTL5000_CHIP_REF_CTRL, 1372 SGTL5000_SMALL_POP, 1373 SGTL5000_SMALL_POP); 1374 1375 /* disable short cut detector */ 1376 snd_soc_write(codec, SGTL5000_CHIP_SHORT_CTRL, 0); 1377 1378 /* 1379 * set i2s as default input of sound switch 1380 * TODO: add sound switch to control and dapm widge. 1381 */ 1382 snd_soc_write(codec, SGTL5000_CHIP_SSS_CTRL, 1383 SGTL5000_DAC_SEL_I2S_IN << SGTL5000_DAC_SEL_SHIFT); 1384 snd_soc_write(codec, SGTL5000_CHIP_DIG_POWER, 1385 SGTL5000_ADC_EN | SGTL5000_DAC_EN); 1386 1387 /* enable dac volume ramp by default */ 1388 snd_soc_write(codec, SGTL5000_CHIP_ADCDAC_CTRL, 1389 SGTL5000_DAC_VOL_RAMP_EN | 1390 SGTL5000_DAC_MUTE_RIGHT | 1391 SGTL5000_DAC_MUTE_LEFT); 1392 1393 snd_soc_write(codec, SGTL5000_CHIP_PAD_STRENGTH, 0x015f); 1394 1395 snd_soc_write(codec, SGTL5000_CHIP_ANA_CTRL, 1396 SGTL5000_HP_ZCD_EN | 1397 SGTL5000_ADC_ZCD_EN); 1398 1399 snd_soc_write(codec, SGTL5000_CHIP_MIC_CTRL, 2); 1400 1401 /* 1402 * disable DAP 1403 * TODO: 1404 * Enable DAP in kcontrol and dapm. 1405 */ 1406 snd_soc_write(codec, SGTL5000_DAP_CTRL, 0); 1407 1408 /* leading to standby state */ 1409 ret = sgtl5000_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 1410 if (ret) 1411 goto err; 1412 1413 return 0; 1414 1415 err: 1416 regulator_bulk_disable(ARRAY_SIZE(sgtl5000->supplies), 1417 sgtl5000->supplies); 1418 regulator_bulk_free(ARRAY_SIZE(sgtl5000->supplies), 1419 sgtl5000->supplies); 1420 ldo_regulator_remove(codec); 1421 1422 return ret; 1423 } 1424 1425 static int sgtl5000_remove(struct snd_soc_codec *codec) 1426 { 1427 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); 1428 1429 sgtl5000_set_bias_level(codec, SND_SOC_BIAS_OFF); 1430 1431 regulator_bulk_disable(ARRAY_SIZE(sgtl5000->supplies), 1432 sgtl5000->supplies); 1433 regulator_bulk_free(ARRAY_SIZE(sgtl5000->supplies), 1434 sgtl5000->supplies); 1435 ldo_regulator_remove(codec); 1436 1437 return 0; 1438 } 1439 1440 static struct snd_soc_codec_driver sgtl5000_driver = { 1441 .probe = sgtl5000_probe, 1442 .remove = sgtl5000_remove, 1443 .suspend = sgtl5000_suspend, 1444 .resume = sgtl5000_resume, 1445 .set_bias_level = sgtl5000_set_bias_level, 1446 .controls = sgtl5000_snd_controls, 1447 .num_controls = ARRAY_SIZE(sgtl5000_snd_controls), 1448 .dapm_widgets = sgtl5000_dapm_widgets, 1449 .num_dapm_widgets = ARRAY_SIZE(sgtl5000_dapm_widgets), 1450 .dapm_routes = sgtl5000_dapm_routes, 1451 .num_dapm_routes = ARRAY_SIZE(sgtl5000_dapm_routes), 1452 }; 1453 1454 static const struct regmap_config sgtl5000_regmap = { 1455 .reg_bits = 16, 1456 .val_bits = 16, 1457 .reg_stride = 2, 1458 1459 .max_register = SGTL5000_MAX_REG_OFFSET, 1460 .volatile_reg = sgtl5000_volatile, 1461 .readable_reg = sgtl5000_readable, 1462 1463 .cache_type = REGCACHE_RBTREE, 1464 .reg_defaults = sgtl5000_reg_defaults, 1465 .num_reg_defaults = ARRAY_SIZE(sgtl5000_reg_defaults), 1466 }; 1467 1468 /* 1469 * Write all the default values from sgtl5000_reg_defaults[] array into the 1470 * sgtl5000 registers, to make sure we always start with the sane registers 1471 * values as stated in the datasheet. 1472 * 1473 * Since sgtl5000 does not have a reset line, nor a reset command in software, 1474 * we follow this approach to guarantee we always start from the default values 1475 * and avoid problems like, not being able to probe after an audio playback 1476 * followed by a system reset or a 'reboot' command in Linux 1477 */ 1478 static int sgtl5000_fill_defaults(struct sgtl5000_priv *sgtl5000) 1479 { 1480 int i, ret, val, index; 1481 1482 for (i = 0; i < ARRAY_SIZE(sgtl5000_reg_defaults); i++) { 1483 val = sgtl5000_reg_defaults[i].def; 1484 index = sgtl5000_reg_defaults[i].reg; 1485 ret = regmap_write(sgtl5000->regmap, index, val); 1486 if (ret) 1487 return ret; 1488 } 1489 1490 return 0; 1491 } 1492 1493 static int sgtl5000_i2c_probe(struct i2c_client *client, 1494 const struct i2c_device_id *id) 1495 { 1496 struct sgtl5000_priv *sgtl5000; 1497 int ret, reg, rev; 1498 1499 sgtl5000 = devm_kzalloc(&client->dev, sizeof(struct sgtl5000_priv), 1500 GFP_KERNEL); 1501 if (!sgtl5000) 1502 return -ENOMEM; 1503 1504 sgtl5000->regmap = devm_regmap_init_i2c(client, &sgtl5000_regmap); 1505 if (IS_ERR(sgtl5000->regmap)) { 1506 ret = PTR_ERR(sgtl5000->regmap); 1507 dev_err(&client->dev, "Failed to allocate regmap: %d\n", ret); 1508 return ret; 1509 } 1510 1511 sgtl5000->mclk = devm_clk_get(&client->dev, NULL); 1512 if (IS_ERR(sgtl5000->mclk)) { 1513 ret = PTR_ERR(sgtl5000->mclk); 1514 dev_err(&client->dev, "Failed to get mclock: %d\n", ret); 1515 /* Defer the probe to see if the clk will be provided later */ 1516 if (ret == -ENOENT) 1517 return -EPROBE_DEFER; 1518 return ret; 1519 } 1520 1521 ret = clk_prepare_enable(sgtl5000->mclk); 1522 if (ret) 1523 return ret; 1524 1525 /* read chip information */ 1526 ret = regmap_read(sgtl5000->regmap, SGTL5000_CHIP_ID, ®); 1527 if (ret) 1528 goto disable_clk; 1529 1530 if (((reg & SGTL5000_PARTID_MASK) >> SGTL5000_PARTID_SHIFT) != 1531 SGTL5000_PARTID_PART_ID) { 1532 dev_err(&client->dev, 1533 "Device with ID register %x is not a sgtl5000\n", reg); 1534 ret = -ENODEV; 1535 goto disable_clk; 1536 } 1537 1538 rev = (reg & SGTL5000_REVID_MASK) >> SGTL5000_REVID_SHIFT; 1539 dev_info(&client->dev, "sgtl5000 revision 0x%x\n", rev); 1540 sgtl5000->revision = rev; 1541 1542 i2c_set_clientdata(client, sgtl5000); 1543 1544 /* Ensure sgtl5000 will start with sane register values */ 1545 ret = sgtl5000_fill_defaults(sgtl5000); 1546 if (ret) 1547 goto disable_clk; 1548 1549 ret = snd_soc_register_codec(&client->dev, 1550 &sgtl5000_driver, &sgtl5000_dai, 1); 1551 if (ret) 1552 goto disable_clk; 1553 1554 return 0; 1555 1556 disable_clk: 1557 clk_disable_unprepare(sgtl5000->mclk); 1558 return ret; 1559 } 1560 1561 static int sgtl5000_i2c_remove(struct i2c_client *client) 1562 { 1563 struct sgtl5000_priv *sgtl5000 = i2c_get_clientdata(client); 1564 1565 snd_soc_unregister_codec(&client->dev); 1566 clk_disable_unprepare(sgtl5000->mclk); 1567 return 0; 1568 } 1569 1570 static const struct i2c_device_id sgtl5000_id[] = { 1571 {"sgtl5000", 0}, 1572 {}, 1573 }; 1574 1575 MODULE_DEVICE_TABLE(i2c, sgtl5000_id); 1576 1577 static const struct of_device_id sgtl5000_dt_ids[] = { 1578 { .compatible = "fsl,sgtl5000", }, 1579 { /* sentinel */ } 1580 }; 1581 MODULE_DEVICE_TABLE(of, sgtl5000_dt_ids); 1582 1583 static struct i2c_driver sgtl5000_i2c_driver = { 1584 .driver = { 1585 .name = "sgtl5000", 1586 .owner = THIS_MODULE, 1587 .of_match_table = sgtl5000_dt_ids, 1588 }, 1589 .probe = sgtl5000_i2c_probe, 1590 .remove = sgtl5000_i2c_remove, 1591 .id_table = sgtl5000_id, 1592 }; 1593 1594 module_i2c_driver(sgtl5000_i2c_driver); 1595 1596 MODULE_DESCRIPTION("Freescale SGTL5000 ALSA SoC Codec Driver"); 1597 MODULE_AUTHOR("Zeng Zhaoming <zengzm.kernel@gmail.com>"); 1598 MODULE_LICENSE("GPL"); 1599