1 /* 2 * sgtl5000.c -- SGTL5000 ALSA SoC Audio driver 3 * 4 * Copyright 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11 #include <linux/module.h> 12 #include <linux/moduleparam.h> 13 #include <linux/init.h> 14 #include <linux/delay.h> 15 #include <linux/slab.h> 16 #include <linux/pm.h> 17 #include <linux/i2c.h> 18 #include <linux/clk.h> 19 #include <linux/regmap.h> 20 #include <linux/regulator/driver.h> 21 #include <linux/regulator/machine.h> 22 #include <linux/regulator/consumer.h> 23 #include <linux/of_device.h> 24 #include <sound/core.h> 25 #include <sound/tlv.h> 26 #include <sound/pcm.h> 27 #include <sound/pcm_params.h> 28 #include <sound/soc.h> 29 #include <sound/soc-dapm.h> 30 #include <sound/initval.h> 31 32 #include "sgtl5000.h" 33 34 #define SGTL5000_DAP_REG_OFFSET 0x0100 35 #define SGTL5000_MAX_REG_OFFSET 0x013A 36 37 /* default value of sgtl5000 registers */ 38 static const struct reg_default sgtl5000_reg_defaults[] = { 39 { SGTL5000_CHIP_CLK_CTRL, 0x0008 }, 40 { SGTL5000_CHIP_I2S_CTRL, 0x0010 }, 41 { SGTL5000_CHIP_SSS_CTRL, 0x0010 }, 42 { SGTL5000_CHIP_DAC_VOL, 0x3c3c }, 43 { SGTL5000_CHIP_PAD_STRENGTH, 0x015f }, 44 { SGTL5000_CHIP_ANA_HP_CTRL, 0x1818 }, 45 { SGTL5000_CHIP_ANA_CTRL, 0x0111 }, 46 { SGTL5000_CHIP_LINE_OUT_VOL, 0x0404 }, 47 { SGTL5000_CHIP_ANA_POWER, 0x7060 }, 48 { SGTL5000_CHIP_PLL_CTRL, 0x5000 }, 49 { SGTL5000_DAP_BASS_ENHANCE, 0x0040 }, 50 { SGTL5000_DAP_BASS_ENHANCE_CTRL, 0x051f }, 51 { SGTL5000_DAP_SURROUND, 0x0040 }, 52 { SGTL5000_DAP_EQ_BASS_BAND0, 0x002f }, 53 { SGTL5000_DAP_EQ_BASS_BAND1, 0x002f }, 54 { SGTL5000_DAP_EQ_BASS_BAND2, 0x002f }, 55 { SGTL5000_DAP_EQ_BASS_BAND3, 0x002f }, 56 { SGTL5000_DAP_EQ_BASS_BAND4, 0x002f }, 57 { SGTL5000_DAP_MAIN_CHAN, 0x8000 }, 58 { SGTL5000_DAP_AVC_CTRL, 0x0510 }, 59 { SGTL5000_DAP_AVC_THRESHOLD, 0x1473 }, 60 { SGTL5000_DAP_AVC_ATTACK, 0x0028 }, 61 { SGTL5000_DAP_AVC_DECAY, 0x0050 }, 62 }; 63 64 /* regulator supplies for sgtl5000, VDDD is an optional external supply */ 65 enum sgtl5000_regulator_supplies { 66 VDDA, 67 VDDIO, 68 VDDD, 69 SGTL5000_SUPPLY_NUM 70 }; 71 72 /* vddd is optional supply */ 73 static const char *supply_names[SGTL5000_SUPPLY_NUM] = { 74 "VDDA", 75 "VDDIO", 76 "VDDD" 77 }; 78 79 #define LDO_CONSUMER_NAME "VDDD_LDO" 80 #define LDO_VOLTAGE 1200000 81 82 static struct regulator_consumer_supply ldo_consumer[] = { 83 REGULATOR_SUPPLY(LDO_CONSUMER_NAME, NULL), 84 }; 85 86 static struct regulator_init_data ldo_init_data = { 87 .constraints = { 88 .min_uV = 1200000, 89 .max_uV = 1200000, 90 .valid_modes_mask = REGULATOR_MODE_NORMAL, 91 .valid_ops_mask = REGULATOR_CHANGE_STATUS, 92 }, 93 .num_consumer_supplies = 1, 94 .consumer_supplies = &ldo_consumer[0], 95 }; 96 97 /* 98 * sgtl5000 internal ldo regulator, 99 * enabled when VDDD not provided 100 */ 101 struct ldo_regulator { 102 struct regulator_desc desc; 103 struct regulator_dev *dev; 104 int voltage; 105 void *codec_data; 106 bool enabled; 107 }; 108 109 /* sgtl5000 private structure in codec */ 110 struct sgtl5000_priv { 111 int sysclk; /* sysclk rate */ 112 int master; /* i2s master or not */ 113 int fmt; /* i2s data format */ 114 struct regulator_bulk_data supplies[SGTL5000_SUPPLY_NUM]; 115 struct ldo_regulator *ldo; 116 struct regmap *regmap; 117 struct clk *mclk; 118 }; 119 120 /* 121 * mic_bias power on/off share the same register bits with 122 * output impedance of mic bias, when power on mic bias, we 123 * need reclaim it to impedance value. 124 * 0x0 = Powered off 125 * 0x1 = 2Kohm 126 * 0x2 = 4Kohm 127 * 0x3 = 8Kohm 128 */ 129 static int mic_bias_event(struct snd_soc_dapm_widget *w, 130 struct snd_kcontrol *kcontrol, int event) 131 { 132 switch (event) { 133 case SND_SOC_DAPM_POST_PMU: 134 /* change mic bias resistor to 4Kohm */ 135 snd_soc_update_bits(w->codec, SGTL5000_CHIP_MIC_CTRL, 136 SGTL5000_BIAS_R_MASK, 137 SGTL5000_BIAS_R_4k << SGTL5000_BIAS_R_SHIFT); 138 break; 139 140 case SND_SOC_DAPM_PRE_PMD: 141 snd_soc_update_bits(w->codec, SGTL5000_CHIP_MIC_CTRL, 142 SGTL5000_BIAS_R_MASK, 0); 143 break; 144 } 145 return 0; 146 } 147 148 /* 149 * As manual described, ADC/DAC only works when VAG powerup, 150 * So enabled VAG before ADC/DAC up. 151 * In power down case, we need wait 400ms when vag fully ramped down. 152 */ 153 static int power_vag_event(struct snd_soc_dapm_widget *w, 154 struct snd_kcontrol *kcontrol, int event) 155 { 156 switch (event) { 157 case SND_SOC_DAPM_POST_PMU: 158 snd_soc_update_bits(w->codec, SGTL5000_CHIP_ANA_POWER, 159 SGTL5000_VAG_POWERUP, SGTL5000_VAG_POWERUP); 160 break; 161 162 case SND_SOC_DAPM_PRE_PMD: 163 snd_soc_update_bits(w->codec, SGTL5000_CHIP_ANA_POWER, 164 SGTL5000_VAG_POWERUP, 0); 165 msleep(400); 166 break; 167 default: 168 break; 169 } 170 171 return 0; 172 } 173 174 /* input sources for ADC */ 175 static const char *adc_mux_text[] = { 176 "MIC_IN", "LINE_IN" 177 }; 178 179 static const struct soc_enum adc_enum = 180 SOC_ENUM_SINGLE(SGTL5000_CHIP_ANA_CTRL, 2, 2, adc_mux_text); 181 182 static const struct snd_kcontrol_new adc_mux = 183 SOC_DAPM_ENUM("Capture Mux", adc_enum); 184 185 /* input sources for DAC */ 186 static const char *dac_mux_text[] = { 187 "DAC", "LINE_IN" 188 }; 189 190 static const struct soc_enum dac_enum = 191 SOC_ENUM_SINGLE(SGTL5000_CHIP_ANA_CTRL, 6, 2, dac_mux_text); 192 193 static const struct snd_kcontrol_new dac_mux = 194 SOC_DAPM_ENUM("Headphone Mux", dac_enum); 195 196 static const struct snd_soc_dapm_widget sgtl5000_dapm_widgets[] = { 197 SND_SOC_DAPM_INPUT("LINE_IN"), 198 SND_SOC_DAPM_INPUT("MIC_IN"), 199 200 SND_SOC_DAPM_OUTPUT("HP_OUT"), 201 SND_SOC_DAPM_OUTPUT("LINE_OUT"), 202 203 SND_SOC_DAPM_SUPPLY("Mic Bias", SGTL5000_CHIP_MIC_CTRL, 8, 0, 204 mic_bias_event, 205 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 206 207 SND_SOC_DAPM_PGA("HP", SGTL5000_CHIP_ANA_POWER, 4, 0, NULL, 0), 208 SND_SOC_DAPM_PGA("LO", SGTL5000_CHIP_ANA_POWER, 0, 0, NULL, 0), 209 210 SND_SOC_DAPM_MUX("Capture Mux", SND_SOC_NOPM, 0, 0, &adc_mux), 211 SND_SOC_DAPM_MUX("Headphone Mux", SND_SOC_NOPM, 0, 0, &dac_mux), 212 213 /* aif for i2s input */ 214 SND_SOC_DAPM_AIF_IN("AIFIN", "Playback", 215 0, SGTL5000_CHIP_DIG_POWER, 216 0, 0), 217 218 /* aif for i2s output */ 219 SND_SOC_DAPM_AIF_OUT("AIFOUT", "Capture", 220 0, SGTL5000_CHIP_DIG_POWER, 221 1, 0), 222 223 SND_SOC_DAPM_ADC("ADC", "Capture", SGTL5000_CHIP_ANA_POWER, 1, 0), 224 SND_SOC_DAPM_DAC("DAC", "Playback", SGTL5000_CHIP_ANA_POWER, 3, 0), 225 226 SND_SOC_DAPM_PRE("VAG_POWER_PRE", power_vag_event), 227 SND_SOC_DAPM_POST("VAG_POWER_POST", power_vag_event), 228 }; 229 230 /* routes for sgtl5000 */ 231 static const struct snd_soc_dapm_route sgtl5000_dapm_routes[] = { 232 {"Capture Mux", "LINE_IN", "LINE_IN"}, /* line_in --> adc_mux */ 233 {"Capture Mux", "MIC_IN", "MIC_IN"}, /* mic_in --> adc_mux */ 234 235 {"ADC", NULL, "Capture Mux"}, /* adc_mux --> adc */ 236 {"AIFOUT", NULL, "ADC"}, /* adc --> i2s_out */ 237 238 {"DAC", NULL, "AIFIN"}, /* i2s-->dac,skip audio mux */ 239 {"Headphone Mux", "DAC", "DAC"}, /* dac --> hp_mux */ 240 {"LO", NULL, "DAC"}, /* dac --> line_out */ 241 242 {"Headphone Mux", "LINE_IN", "LINE_IN"},/* line_in --> hp_mux */ 243 {"HP", NULL, "Headphone Mux"}, /* hp_mux --> hp */ 244 245 {"LINE_OUT", NULL, "LO"}, 246 {"HP_OUT", NULL, "HP"}, 247 }; 248 249 /* custom function to fetch info of PCM playback volume */ 250 static int dac_info_volsw(struct snd_kcontrol *kcontrol, 251 struct snd_ctl_elem_info *uinfo) 252 { 253 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 254 uinfo->count = 2; 255 uinfo->value.integer.min = 0; 256 uinfo->value.integer.max = 0xfc - 0x3c; 257 return 0; 258 } 259 260 /* 261 * custom function to get of PCM playback volume 262 * 263 * dac volume register 264 * 15-------------8-7--------------0 265 * | R channel vol | L channel vol | 266 * ------------------------------- 267 * 268 * PCM volume with 0.5017 dB steps from 0 to -90 dB 269 * 270 * register values map to dB 271 * 0x3B and less = Reserved 272 * 0x3C = 0 dB 273 * 0x3D = -0.5 dB 274 * 0xF0 = -90 dB 275 * 0xFC and greater = Muted 276 * 277 * register value map to userspace value 278 * 279 * register value 0x3c(0dB) 0xf0(-90dB)0xfc 280 * ------------------------------ 281 * userspace value 0xc0 0 282 */ 283 static int dac_get_volsw(struct snd_kcontrol *kcontrol, 284 struct snd_ctl_elem_value *ucontrol) 285 { 286 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 287 int reg; 288 int l; 289 int r; 290 291 reg = snd_soc_read(codec, SGTL5000_CHIP_DAC_VOL); 292 293 /* get left channel volume */ 294 l = (reg & SGTL5000_DAC_VOL_LEFT_MASK) >> SGTL5000_DAC_VOL_LEFT_SHIFT; 295 296 /* get right channel volume */ 297 r = (reg & SGTL5000_DAC_VOL_RIGHT_MASK) >> SGTL5000_DAC_VOL_RIGHT_SHIFT; 298 299 /* make sure value fall in (0x3c,0xfc) */ 300 l = clamp(l, 0x3c, 0xfc); 301 r = clamp(r, 0x3c, 0xfc); 302 303 /* invert it and map to userspace value */ 304 l = 0xfc - l; 305 r = 0xfc - r; 306 307 ucontrol->value.integer.value[0] = l; 308 ucontrol->value.integer.value[1] = r; 309 310 return 0; 311 } 312 313 /* 314 * custom function to put of PCM playback volume 315 * 316 * dac volume register 317 * 15-------------8-7--------------0 318 * | R channel vol | L channel vol | 319 * ------------------------------- 320 * 321 * PCM volume with 0.5017 dB steps from 0 to -90 dB 322 * 323 * register values map to dB 324 * 0x3B and less = Reserved 325 * 0x3C = 0 dB 326 * 0x3D = -0.5 dB 327 * 0xF0 = -90 dB 328 * 0xFC and greater = Muted 329 * 330 * userspace value map to register value 331 * 332 * userspace value 0xc0 0 333 * ------------------------------ 334 * register value 0x3c(0dB) 0xf0(-90dB)0xfc 335 */ 336 static int dac_put_volsw(struct snd_kcontrol *kcontrol, 337 struct snd_ctl_elem_value *ucontrol) 338 { 339 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 340 int reg; 341 int l; 342 int r; 343 344 l = ucontrol->value.integer.value[0]; 345 r = ucontrol->value.integer.value[1]; 346 347 /* make sure userspace volume fall in (0, 0xfc-0x3c) */ 348 l = clamp(l, 0, 0xfc - 0x3c); 349 r = clamp(r, 0, 0xfc - 0x3c); 350 351 /* invert it, get the value can be set to register */ 352 l = 0xfc - l; 353 r = 0xfc - r; 354 355 /* shift to get the register value */ 356 reg = l << SGTL5000_DAC_VOL_LEFT_SHIFT | 357 r << SGTL5000_DAC_VOL_RIGHT_SHIFT; 358 359 snd_soc_write(codec, SGTL5000_CHIP_DAC_VOL, reg); 360 361 return 0; 362 } 363 364 static const DECLARE_TLV_DB_SCALE(capture_6db_attenuate, -600, 600, 0); 365 366 /* tlv for mic gain, 0db 20db 30db 40db */ 367 static const unsigned int mic_gain_tlv[] = { 368 TLV_DB_RANGE_HEAD(2), 369 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0), 370 1, 3, TLV_DB_SCALE_ITEM(2000, 1000, 0), 371 }; 372 373 /* tlv for hp volume, -51.5db to 12.0db, step .5db */ 374 static const DECLARE_TLV_DB_SCALE(headphone_volume, -5150, 50, 0); 375 376 static const struct snd_kcontrol_new sgtl5000_snd_controls[] = { 377 /* SOC_DOUBLE_S8_TLV with invert */ 378 { 379 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 380 .name = "PCM Playback Volume", 381 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ | 382 SNDRV_CTL_ELEM_ACCESS_READWRITE, 383 .info = dac_info_volsw, 384 .get = dac_get_volsw, 385 .put = dac_put_volsw, 386 }, 387 388 SOC_DOUBLE("Capture Volume", SGTL5000_CHIP_ANA_ADC_CTRL, 0, 4, 0xf, 0), 389 SOC_SINGLE_TLV("Capture Attenuate Switch (-6dB)", 390 SGTL5000_CHIP_ANA_ADC_CTRL, 391 8, 2, 0, capture_6db_attenuate), 392 SOC_SINGLE("Capture ZC Switch", SGTL5000_CHIP_ANA_CTRL, 1, 1, 0), 393 394 SOC_DOUBLE_TLV("Headphone Playback Volume", 395 SGTL5000_CHIP_ANA_HP_CTRL, 396 0, 8, 397 0x7f, 1, 398 headphone_volume), 399 SOC_SINGLE("Headphone Playback ZC Switch", SGTL5000_CHIP_ANA_CTRL, 400 5, 1, 0), 401 402 SOC_SINGLE_TLV("Mic Volume", SGTL5000_CHIP_MIC_CTRL, 403 0, 3, 0, mic_gain_tlv), 404 }; 405 406 /* mute the codec used by alsa core */ 407 static int sgtl5000_digital_mute(struct snd_soc_dai *codec_dai, int mute) 408 { 409 struct snd_soc_codec *codec = codec_dai->codec; 410 u16 adcdac_ctrl = SGTL5000_DAC_MUTE_LEFT | SGTL5000_DAC_MUTE_RIGHT; 411 412 snd_soc_update_bits(codec, SGTL5000_CHIP_ADCDAC_CTRL, 413 adcdac_ctrl, mute ? adcdac_ctrl : 0); 414 415 return 0; 416 } 417 418 /* set codec format */ 419 static int sgtl5000_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt) 420 { 421 struct snd_soc_codec *codec = codec_dai->codec; 422 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); 423 u16 i2sctl = 0; 424 425 sgtl5000->master = 0; 426 /* 427 * i2s clock and frame master setting. 428 * ONLY support: 429 * - clock and frame slave, 430 * - clock and frame master 431 */ 432 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 433 case SND_SOC_DAIFMT_CBS_CFS: 434 break; 435 case SND_SOC_DAIFMT_CBM_CFM: 436 i2sctl |= SGTL5000_I2S_MASTER; 437 sgtl5000->master = 1; 438 break; 439 default: 440 return -EINVAL; 441 } 442 443 /* setting i2s data format */ 444 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 445 case SND_SOC_DAIFMT_DSP_A: 446 i2sctl |= SGTL5000_I2S_MODE_PCM; 447 break; 448 case SND_SOC_DAIFMT_DSP_B: 449 i2sctl |= SGTL5000_I2S_MODE_PCM; 450 i2sctl |= SGTL5000_I2S_LRALIGN; 451 break; 452 case SND_SOC_DAIFMT_I2S: 453 i2sctl |= SGTL5000_I2S_MODE_I2S_LJ; 454 break; 455 case SND_SOC_DAIFMT_RIGHT_J: 456 i2sctl |= SGTL5000_I2S_MODE_RJ; 457 i2sctl |= SGTL5000_I2S_LRPOL; 458 break; 459 case SND_SOC_DAIFMT_LEFT_J: 460 i2sctl |= SGTL5000_I2S_MODE_I2S_LJ; 461 i2sctl |= SGTL5000_I2S_LRALIGN; 462 break; 463 default: 464 return -EINVAL; 465 } 466 467 sgtl5000->fmt = fmt & SND_SOC_DAIFMT_FORMAT_MASK; 468 469 /* Clock inversion */ 470 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 471 case SND_SOC_DAIFMT_NB_NF: 472 break; 473 case SND_SOC_DAIFMT_IB_NF: 474 i2sctl |= SGTL5000_I2S_SCLK_INV; 475 break; 476 default: 477 return -EINVAL; 478 } 479 480 snd_soc_write(codec, SGTL5000_CHIP_I2S_CTRL, i2sctl); 481 482 return 0; 483 } 484 485 /* set codec sysclk */ 486 static int sgtl5000_set_dai_sysclk(struct snd_soc_dai *codec_dai, 487 int clk_id, unsigned int freq, int dir) 488 { 489 struct snd_soc_codec *codec = codec_dai->codec; 490 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); 491 492 switch (clk_id) { 493 case SGTL5000_SYSCLK: 494 sgtl5000->sysclk = freq; 495 break; 496 default: 497 return -EINVAL; 498 } 499 500 return 0; 501 } 502 503 /* 504 * set clock according to i2s frame clock, 505 * sgtl5000 provide 2 clock sources. 506 * 1. sys_mclk. sample freq can only configure to 507 * 1/256, 1/384, 1/512 of sys_mclk. 508 * 2. pll. can derive any audio clocks. 509 * 510 * clock setting rules: 511 * 1. in slave mode, only sys_mclk can use. 512 * 2. as constraint by sys_mclk, sample freq should 513 * set to 32k, 44.1k and above. 514 * 3. using sys_mclk prefer to pll to save power. 515 */ 516 static int sgtl5000_set_clock(struct snd_soc_codec *codec, int frame_rate) 517 { 518 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); 519 int clk_ctl = 0; 520 int sys_fs; /* sample freq */ 521 522 /* 523 * sample freq should be divided by frame clock, 524 * if frame clock lower than 44.1khz, sample feq should set to 525 * 32khz or 44.1khz. 526 */ 527 switch (frame_rate) { 528 case 8000: 529 case 16000: 530 sys_fs = 32000; 531 break; 532 case 11025: 533 case 22050: 534 sys_fs = 44100; 535 break; 536 default: 537 sys_fs = frame_rate; 538 break; 539 } 540 541 /* set divided factor of frame clock */ 542 switch (sys_fs / frame_rate) { 543 case 4: 544 clk_ctl |= SGTL5000_RATE_MODE_DIV_4 << SGTL5000_RATE_MODE_SHIFT; 545 break; 546 case 2: 547 clk_ctl |= SGTL5000_RATE_MODE_DIV_2 << SGTL5000_RATE_MODE_SHIFT; 548 break; 549 case 1: 550 clk_ctl |= SGTL5000_RATE_MODE_DIV_1 << SGTL5000_RATE_MODE_SHIFT; 551 break; 552 default: 553 return -EINVAL; 554 } 555 556 /* set the sys_fs according to frame rate */ 557 switch (sys_fs) { 558 case 32000: 559 clk_ctl |= SGTL5000_SYS_FS_32k << SGTL5000_SYS_FS_SHIFT; 560 break; 561 case 44100: 562 clk_ctl |= SGTL5000_SYS_FS_44_1k << SGTL5000_SYS_FS_SHIFT; 563 break; 564 case 48000: 565 clk_ctl |= SGTL5000_SYS_FS_48k << SGTL5000_SYS_FS_SHIFT; 566 break; 567 case 96000: 568 clk_ctl |= SGTL5000_SYS_FS_96k << SGTL5000_SYS_FS_SHIFT; 569 break; 570 default: 571 dev_err(codec->dev, "frame rate %d not supported\n", 572 frame_rate); 573 return -EINVAL; 574 } 575 576 /* 577 * calculate the divider of mclk/sample_freq, 578 * factor of freq =96k can only be 256, since mclk in range (12m,27m) 579 */ 580 switch (sgtl5000->sysclk / sys_fs) { 581 case 256: 582 clk_ctl |= SGTL5000_MCLK_FREQ_256FS << 583 SGTL5000_MCLK_FREQ_SHIFT; 584 break; 585 case 384: 586 clk_ctl |= SGTL5000_MCLK_FREQ_384FS << 587 SGTL5000_MCLK_FREQ_SHIFT; 588 break; 589 case 512: 590 clk_ctl |= SGTL5000_MCLK_FREQ_512FS << 591 SGTL5000_MCLK_FREQ_SHIFT; 592 break; 593 default: 594 /* if mclk not satisify the divider, use pll */ 595 if (sgtl5000->master) { 596 clk_ctl |= SGTL5000_MCLK_FREQ_PLL << 597 SGTL5000_MCLK_FREQ_SHIFT; 598 } else { 599 dev_err(codec->dev, 600 "PLL not supported in slave mode\n"); 601 return -EINVAL; 602 } 603 } 604 605 /* if using pll, please check manual 6.4.2 for detail */ 606 if ((clk_ctl & SGTL5000_MCLK_FREQ_MASK) == SGTL5000_MCLK_FREQ_PLL) { 607 u64 out, t; 608 int div2; 609 int pll_ctl; 610 unsigned int in, int_div, frac_div; 611 612 if (sgtl5000->sysclk > 17000000) { 613 div2 = 1; 614 in = sgtl5000->sysclk / 2; 615 } else { 616 div2 = 0; 617 in = sgtl5000->sysclk; 618 } 619 if (sys_fs == 44100) 620 out = 180633600; 621 else 622 out = 196608000; 623 t = do_div(out, in); 624 int_div = out; 625 t *= 2048; 626 do_div(t, in); 627 frac_div = t; 628 pll_ctl = int_div << SGTL5000_PLL_INT_DIV_SHIFT | 629 frac_div << SGTL5000_PLL_FRAC_DIV_SHIFT; 630 631 snd_soc_write(codec, SGTL5000_CHIP_PLL_CTRL, pll_ctl); 632 if (div2) 633 snd_soc_update_bits(codec, 634 SGTL5000_CHIP_CLK_TOP_CTRL, 635 SGTL5000_INPUT_FREQ_DIV2, 636 SGTL5000_INPUT_FREQ_DIV2); 637 else 638 snd_soc_update_bits(codec, 639 SGTL5000_CHIP_CLK_TOP_CTRL, 640 SGTL5000_INPUT_FREQ_DIV2, 641 0); 642 643 /* power up pll */ 644 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER, 645 SGTL5000_PLL_POWERUP | SGTL5000_VCOAMP_POWERUP, 646 SGTL5000_PLL_POWERUP | SGTL5000_VCOAMP_POWERUP); 647 } else { 648 /* power down pll */ 649 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER, 650 SGTL5000_PLL_POWERUP | SGTL5000_VCOAMP_POWERUP, 651 0); 652 } 653 654 /* if using pll, clk_ctrl must be set after pll power up */ 655 snd_soc_write(codec, SGTL5000_CHIP_CLK_CTRL, clk_ctl); 656 657 return 0; 658 } 659 660 /* 661 * Set PCM DAI bit size and sample rate. 662 * input: params_rate, params_fmt 663 */ 664 static int sgtl5000_pcm_hw_params(struct snd_pcm_substream *substream, 665 struct snd_pcm_hw_params *params, 666 struct snd_soc_dai *dai) 667 { 668 struct snd_soc_codec *codec = dai->codec; 669 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); 670 int channels = params_channels(params); 671 int i2s_ctl = 0; 672 int stereo; 673 int ret; 674 675 /* sysclk should already set */ 676 if (!sgtl5000->sysclk) { 677 dev_err(codec->dev, "%s: set sysclk first!\n", __func__); 678 return -EFAULT; 679 } 680 681 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 682 stereo = SGTL5000_DAC_STEREO; 683 else 684 stereo = SGTL5000_ADC_STEREO; 685 686 /* set mono to save power */ 687 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER, stereo, 688 channels == 1 ? 0 : stereo); 689 690 /* set codec clock base on lrclk */ 691 ret = sgtl5000_set_clock(codec, params_rate(params)); 692 if (ret) 693 return ret; 694 695 /* set i2s data format */ 696 switch (params_format(params)) { 697 case SNDRV_PCM_FORMAT_S16_LE: 698 if (sgtl5000->fmt == SND_SOC_DAIFMT_RIGHT_J) 699 return -EINVAL; 700 i2s_ctl |= SGTL5000_I2S_DLEN_16 << SGTL5000_I2S_DLEN_SHIFT; 701 i2s_ctl |= SGTL5000_I2S_SCLKFREQ_32FS << 702 SGTL5000_I2S_SCLKFREQ_SHIFT; 703 break; 704 case SNDRV_PCM_FORMAT_S20_3LE: 705 i2s_ctl |= SGTL5000_I2S_DLEN_20 << SGTL5000_I2S_DLEN_SHIFT; 706 i2s_ctl |= SGTL5000_I2S_SCLKFREQ_64FS << 707 SGTL5000_I2S_SCLKFREQ_SHIFT; 708 break; 709 case SNDRV_PCM_FORMAT_S24_LE: 710 i2s_ctl |= SGTL5000_I2S_DLEN_24 << SGTL5000_I2S_DLEN_SHIFT; 711 i2s_ctl |= SGTL5000_I2S_SCLKFREQ_64FS << 712 SGTL5000_I2S_SCLKFREQ_SHIFT; 713 break; 714 case SNDRV_PCM_FORMAT_S32_LE: 715 if (sgtl5000->fmt == SND_SOC_DAIFMT_RIGHT_J) 716 return -EINVAL; 717 i2s_ctl |= SGTL5000_I2S_DLEN_32 << SGTL5000_I2S_DLEN_SHIFT; 718 i2s_ctl |= SGTL5000_I2S_SCLKFREQ_64FS << 719 SGTL5000_I2S_SCLKFREQ_SHIFT; 720 break; 721 default: 722 return -EINVAL; 723 } 724 725 snd_soc_update_bits(codec, SGTL5000_CHIP_I2S_CTRL, 726 SGTL5000_I2S_DLEN_MASK | SGTL5000_I2S_SCLKFREQ_MASK, 727 i2s_ctl); 728 729 return 0; 730 } 731 732 #ifdef CONFIG_REGULATOR 733 static int ldo_regulator_is_enabled(struct regulator_dev *dev) 734 { 735 struct ldo_regulator *ldo = rdev_get_drvdata(dev); 736 737 return ldo->enabled; 738 } 739 740 static int ldo_regulator_enable(struct regulator_dev *dev) 741 { 742 struct ldo_regulator *ldo = rdev_get_drvdata(dev); 743 struct snd_soc_codec *codec = (struct snd_soc_codec *)ldo->codec_data; 744 int reg; 745 746 if (ldo_regulator_is_enabled(dev)) 747 return 0; 748 749 /* set regulator value firstly */ 750 reg = (1600 - ldo->voltage / 1000) / 50; 751 reg = clamp(reg, 0x0, 0xf); 752 753 /* amend the voltage value, unit: uV */ 754 ldo->voltage = (1600 - reg * 50) * 1000; 755 756 /* set voltage to register */ 757 snd_soc_update_bits(codec, SGTL5000_CHIP_LINREG_CTRL, 758 SGTL5000_LINREG_VDDD_MASK, reg); 759 760 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER, 761 SGTL5000_LINEREG_D_POWERUP, 762 SGTL5000_LINEREG_D_POWERUP); 763 764 /* when internal ldo enabled, simple digital power can be disabled */ 765 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER, 766 SGTL5000_LINREG_SIMPLE_POWERUP, 767 0); 768 769 ldo->enabled = 1; 770 return 0; 771 } 772 773 static int ldo_regulator_disable(struct regulator_dev *dev) 774 { 775 struct ldo_regulator *ldo = rdev_get_drvdata(dev); 776 struct snd_soc_codec *codec = (struct snd_soc_codec *)ldo->codec_data; 777 778 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER, 779 SGTL5000_LINEREG_D_POWERUP, 780 0); 781 782 /* clear voltage info */ 783 snd_soc_update_bits(codec, SGTL5000_CHIP_LINREG_CTRL, 784 SGTL5000_LINREG_VDDD_MASK, 0); 785 786 ldo->enabled = 0; 787 788 return 0; 789 } 790 791 static int ldo_regulator_get_voltage(struct regulator_dev *dev) 792 { 793 struct ldo_regulator *ldo = rdev_get_drvdata(dev); 794 795 return ldo->voltage; 796 } 797 798 static struct regulator_ops ldo_regulator_ops = { 799 .is_enabled = ldo_regulator_is_enabled, 800 .enable = ldo_regulator_enable, 801 .disable = ldo_regulator_disable, 802 .get_voltage = ldo_regulator_get_voltage, 803 }; 804 805 static int ldo_regulator_register(struct snd_soc_codec *codec, 806 struct regulator_init_data *init_data, 807 int voltage) 808 { 809 struct ldo_regulator *ldo; 810 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); 811 struct regulator_config config = { }; 812 813 ldo = kzalloc(sizeof(struct ldo_regulator), GFP_KERNEL); 814 815 if (!ldo) { 816 dev_err(codec->dev, "failed to allocate ldo_regulator\n"); 817 return -ENOMEM; 818 } 819 820 ldo->desc.name = kstrdup(dev_name(codec->dev), GFP_KERNEL); 821 if (!ldo->desc.name) { 822 kfree(ldo); 823 dev_err(codec->dev, "failed to allocate decs name memory\n"); 824 return -ENOMEM; 825 } 826 827 ldo->desc.type = REGULATOR_VOLTAGE; 828 ldo->desc.owner = THIS_MODULE; 829 ldo->desc.ops = &ldo_regulator_ops; 830 ldo->desc.n_voltages = 1; 831 832 ldo->codec_data = codec; 833 ldo->voltage = voltage; 834 835 config.dev = codec->dev; 836 config.driver_data = ldo; 837 config.init_data = init_data; 838 839 ldo->dev = regulator_register(&ldo->desc, &config); 840 if (IS_ERR(ldo->dev)) { 841 int ret = PTR_ERR(ldo->dev); 842 843 dev_err(codec->dev, "failed to register regulator\n"); 844 kfree(ldo->desc.name); 845 kfree(ldo); 846 847 return ret; 848 } 849 sgtl5000->ldo = ldo; 850 851 return 0; 852 } 853 854 static int ldo_regulator_remove(struct snd_soc_codec *codec) 855 { 856 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); 857 struct ldo_regulator *ldo = sgtl5000->ldo; 858 859 if (!ldo) 860 return 0; 861 862 regulator_unregister(ldo->dev); 863 kfree(ldo->desc.name); 864 kfree(ldo); 865 866 return 0; 867 } 868 #else 869 static int ldo_regulator_register(struct snd_soc_codec *codec, 870 struct regulator_init_data *init_data, 871 int voltage) 872 { 873 dev_err(codec->dev, "this setup needs regulator support in the kernel\n"); 874 return -EINVAL; 875 } 876 877 static int ldo_regulator_remove(struct snd_soc_codec *codec) 878 { 879 return 0; 880 } 881 #endif 882 883 /* 884 * set dac bias 885 * common state changes: 886 * startup: 887 * off --> standby --> prepare --> on 888 * standby --> prepare --> on 889 * 890 * stop: 891 * on --> prepare --> standby 892 */ 893 static int sgtl5000_set_bias_level(struct snd_soc_codec *codec, 894 enum snd_soc_bias_level level) 895 { 896 int ret; 897 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); 898 899 switch (level) { 900 case SND_SOC_BIAS_ON: 901 case SND_SOC_BIAS_PREPARE: 902 break; 903 case SND_SOC_BIAS_STANDBY: 904 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) { 905 ret = regulator_bulk_enable( 906 ARRAY_SIZE(sgtl5000->supplies), 907 sgtl5000->supplies); 908 if (ret) 909 return ret; 910 udelay(10); 911 912 regcache_cache_only(sgtl5000->regmap, false); 913 914 ret = regcache_sync(sgtl5000->regmap); 915 if (ret != 0) { 916 dev_err(codec->dev, 917 "Failed to restore cache: %d\n", ret); 918 919 regcache_cache_only(sgtl5000->regmap, true); 920 regulator_bulk_disable(ARRAY_SIZE(sgtl5000->supplies), 921 sgtl5000->supplies); 922 923 return ret; 924 } 925 } 926 927 break; 928 case SND_SOC_BIAS_OFF: 929 regcache_cache_only(sgtl5000->regmap, true); 930 regulator_bulk_disable(ARRAY_SIZE(sgtl5000->supplies), 931 sgtl5000->supplies); 932 break; 933 } 934 935 codec->dapm.bias_level = level; 936 return 0; 937 } 938 939 #define SGTL5000_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ 940 SNDRV_PCM_FMTBIT_S20_3LE |\ 941 SNDRV_PCM_FMTBIT_S24_LE |\ 942 SNDRV_PCM_FMTBIT_S32_LE) 943 944 static const struct snd_soc_dai_ops sgtl5000_ops = { 945 .hw_params = sgtl5000_pcm_hw_params, 946 .digital_mute = sgtl5000_digital_mute, 947 .set_fmt = sgtl5000_set_dai_fmt, 948 .set_sysclk = sgtl5000_set_dai_sysclk, 949 }; 950 951 static struct snd_soc_dai_driver sgtl5000_dai = { 952 .name = "sgtl5000", 953 .playback = { 954 .stream_name = "Playback", 955 .channels_min = 1, 956 .channels_max = 2, 957 /* 958 * only support 8~48K + 96K, 959 * TODO modify hw_param to support more 960 */ 961 .rates = SNDRV_PCM_RATE_8000_48000 | SNDRV_PCM_RATE_96000, 962 .formats = SGTL5000_FORMATS, 963 }, 964 .capture = { 965 .stream_name = "Capture", 966 .channels_min = 1, 967 .channels_max = 2, 968 .rates = SNDRV_PCM_RATE_8000_48000 | SNDRV_PCM_RATE_96000, 969 .formats = SGTL5000_FORMATS, 970 }, 971 .ops = &sgtl5000_ops, 972 .symmetric_rates = 1, 973 }; 974 975 static bool sgtl5000_volatile(struct device *dev, unsigned int reg) 976 { 977 switch (reg) { 978 case SGTL5000_CHIP_ID: 979 case SGTL5000_CHIP_ADCDAC_CTRL: 980 case SGTL5000_CHIP_ANA_STATUS: 981 return true; 982 } 983 984 return false; 985 } 986 987 static bool sgtl5000_readable(struct device *dev, unsigned int reg) 988 { 989 switch (reg) { 990 case SGTL5000_CHIP_ID: 991 case SGTL5000_CHIP_DIG_POWER: 992 case SGTL5000_CHIP_CLK_CTRL: 993 case SGTL5000_CHIP_I2S_CTRL: 994 case SGTL5000_CHIP_SSS_CTRL: 995 case SGTL5000_CHIP_ADCDAC_CTRL: 996 case SGTL5000_CHIP_DAC_VOL: 997 case SGTL5000_CHIP_PAD_STRENGTH: 998 case SGTL5000_CHIP_ANA_ADC_CTRL: 999 case SGTL5000_CHIP_ANA_HP_CTRL: 1000 case SGTL5000_CHIP_ANA_CTRL: 1001 case SGTL5000_CHIP_LINREG_CTRL: 1002 case SGTL5000_CHIP_REF_CTRL: 1003 case SGTL5000_CHIP_MIC_CTRL: 1004 case SGTL5000_CHIP_LINE_OUT_CTRL: 1005 case SGTL5000_CHIP_LINE_OUT_VOL: 1006 case SGTL5000_CHIP_ANA_POWER: 1007 case SGTL5000_CHIP_PLL_CTRL: 1008 case SGTL5000_CHIP_CLK_TOP_CTRL: 1009 case SGTL5000_CHIP_ANA_STATUS: 1010 case SGTL5000_CHIP_SHORT_CTRL: 1011 case SGTL5000_CHIP_ANA_TEST2: 1012 case SGTL5000_DAP_CTRL: 1013 case SGTL5000_DAP_PEQ: 1014 case SGTL5000_DAP_BASS_ENHANCE: 1015 case SGTL5000_DAP_BASS_ENHANCE_CTRL: 1016 case SGTL5000_DAP_AUDIO_EQ: 1017 case SGTL5000_DAP_SURROUND: 1018 case SGTL5000_DAP_FLT_COEF_ACCESS: 1019 case SGTL5000_DAP_COEF_WR_B0_MSB: 1020 case SGTL5000_DAP_COEF_WR_B0_LSB: 1021 case SGTL5000_DAP_EQ_BASS_BAND0: 1022 case SGTL5000_DAP_EQ_BASS_BAND1: 1023 case SGTL5000_DAP_EQ_BASS_BAND2: 1024 case SGTL5000_DAP_EQ_BASS_BAND3: 1025 case SGTL5000_DAP_EQ_BASS_BAND4: 1026 case SGTL5000_DAP_MAIN_CHAN: 1027 case SGTL5000_DAP_MIX_CHAN: 1028 case SGTL5000_DAP_AVC_CTRL: 1029 case SGTL5000_DAP_AVC_THRESHOLD: 1030 case SGTL5000_DAP_AVC_ATTACK: 1031 case SGTL5000_DAP_AVC_DECAY: 1032 case SGTL5000_DAP_COEF_WR_B1_MSB: 1033 case SGTL5000_DAP_COEF_WR_B1_LSB: 1034 case SGTL5000_DAP_COEF_WR_B2_MSB: 1035 case SGTL5000_DAP_COEF_WR_B2_LSB: 1036 case SGTL5000_DAP_COEF_WR_A1_MSB: 1037 case SGTL5000_DAP_COEF_WR_A1_LSB: 1038 case SGTL5000_DAP_COEF_WR_A2_MSB: 1039 case SGTL5000_DAP_COEF_WR_A2_LSB: 1040 return true; 1041 1042 default: 1043 return false; 1044 } 1045 } 1046 1047 #ifdef CONFIG_SUSPEND 1048 static int sgtl5000_suspend(struct snd_soc_codec *codec) 1049 { 1050 sgtl5000_set_bias_level(codec, SND_SOC_BIAS_OFF); 1051 1052 return 0; 1053 } 1054 1055 /* 1056 * restore all sgtl5000 registers, 1057 * since a big hole between dap and regular registers, 1058 * we will restore them respectively. 1059 */ 1060 static int sgtl5000_restore_regs(struct snd_soc_codec *codec) 1061 { 1062 u16 *cache = codec->reg_cache; 1063 u16 reg; 1064 1065 /* restore regular registers */ 1066 for (reg = 0; reg <= SGTL5000_CHIP_SHORT_CTRL; reg += 2) { 1067 1068 /* These regs should restore in particular order */ 1069 if (reg == SGTL5000_CHIP_ANA_POWER || 1070 reg == SGTL5000_CHIP_CLK_CTRL || 1071 reg == SGTL5000_CHIP_LINREG_CTRL || 1072 reg == SGTL5000_CHIP_LINE_OUT_CTRL || 1073 reg == SGTL5000_CHIP_REF_CTRL) 1074 continue; 1075 1076 snd_soc_write(codec, reg, cache[reg]); 1077 } 1078 1079 /* restore dap registers */ 1080 for (reg = SGTL5000_DAP_REG_OFFSET; reg < SGTL5000_MAX_REG_OFFSET; reg += 2) 1081 snd_soc_write(codec, reg, cache[reg]); 1082 1083 /* 1084 * restore these regs according to the power setting sequence in 1085 * sgtl5000_set_power_regs() and clock setting sequence in 1086 * sgtl5000_set_clock(). 1087 * 1088 * The order of restore is: 1089 * 1. SGTL5000_CHIP_CLK_CTRL MCLK_FREQ bits (1:0) should be restore after 1090 * SGTL5000_CHIP_ANA_POWER PLL bits set 1091 * 2. SGTL5000_CHIP_LINREG_CTRL should be set before 1092 * SGTL5000_CHIP_ANA_POWER LINREG_D restored 1093 * 3. SGTL5000_CHIP_REF_CTRL controls Analog Ground Voltage, 1094 * prefer to resotre it after SGTL5000_CHIP_ANA_POWER restored 1095 */ 1096 snd_soc_write(codec, SGTL5000_CHIP_LINREG_CTRL, 1097 cache[SGTL5000_CHIP_LINREG_CTRL]); 1098 1099 snd_soc_write(codec, SGTL5000_CHIP_ANA_POWER, 1100 cache[SGTL5000_CHIP_ANA_POWER]); 1101 1102 snd_soc_write(codec, SGTL5000_CHIP_CLK_CTRL, 1103 cache[SGTL5000_CHIP_CLK_CTRL]); 1104 1105 snd_soc_write(codec, SGTL5000_CHIP_REF_CTRL, 1106 cache[SGTL5000_CHIP_REF_CTRL]); 1107 1108 snd_soc_write(codec, SGTL5000_CHIP_LINE_OUT_CTRL, 1109 cache[SGTL5000_CHIP_LINE_OUT_CTRL]); 1110 return 0; 1111 } 1112 1113 static int sgtl5000_resume(struct snd_soc_codec *codec) 1114 { 1115 /* Bring the codec back up to standby to enable regulators */ 1116 sgtl5000_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 1117 1118 /* Restore registers by cached in memory */ 1119 sgtl5000_restore_regs(codec); 1120 return 0; 1121 } 1122 #else 1123 #define sgtl5000_suspend NULL 1124 #define sgtl5000_resume NULL 1125 #endif /* CONFIG_SUSPEND */ 1126 1127 /* 1128 * sgtl5000 has 3 internal power supplies: 1129 * 1. VAG, normally set to vdda/2 1130 * 2. chargepump, set to different value 1131 * according to voltage of vdda and vddio 1132 * 3. line out VAG, normally set to vddio/2 1133 * 1134 * and should be set according to: 1135 * 1. vddd provided by external or not 1136 * 2. vdda and vddio voltage value. > 3.1v or not 1137 * 3. chip revision >=0x11 or not. If >=0x11, not use external vddd. 1138 */ 1139 static int sgtl5000_set_power_regs(struct snd_soc_codec *codec) 1140 { 1141 int vddd; 1142 int vdda; 1143 int vddio; 1144 u16 ana_pwr; 1145 u16 lreg_ctrl; 1146 int vag; 1147 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); 1148 1149 vdda = regulator_get_voltage(sgtl5000->supplies[VDDA].consumer); 1150 vddio = regulator_get_voltage(sgtl5000->supplies[VDDIO].consumer); 1151 vddd = regulator_get_voltage(sgtl5000->supplies[VDDD].consumer); 1152 1153 vdda = vdda / 1000; 1154 vddio = vddio / 1000; 1155 vddd = vddd / 1000; 1156 1157 if (vdda <= 0 || vddio <= 0 || vddd < 0) { 1158 dev_err(codec->dev, "regulator voltage not set correctly\n"); 1159 1160 return -EINVAL; 1161 } 1162 1163 /* according to datasheet, maximum voltage of supplies */ 1164 if (vdda > 3600 || vddio > 3600 || vddd > 1980) { 1165 dev_err(codec->dev, 1166 "exceed max voltage vdda %dmV vddio %dmV vddd %dmV\n", 1167 vdda, vddio, vddd); 1168 1169 return -EINVAL; 1170 } 1171 1172 /* reset value */ 1173 ana_pwr = snd_soc_read(codec, SGTL5000_CHIP_ANA_POWER); 1174 ana_pwr |= SGTL5000_DAC_STEREO | 1175 SGTL5000_ADC_STEREO | 1176 SGTL5000_REFTOP_POWERUP; 1177 lreg_ctrl = snd_soc_read(codec, SGTL5000_CHIP_LINREG_CTRL); 1178 1179 if (vddio < 3100 && vdda < 3100) { 1180 /* enable internal oscillator used for charge pump */ 1181 snd_soc_update_bits(codec, SGTL5000_CHIP_CLK_TOP_CTRL, 1182 SGTL5000_INT_OSC_EN, 1183 SGTL5000_INT_OSC_EN); 1184 /* Enable VDDC charge pump */ 1185 ana_pwr |= SGTL5000_VDDC_CHRGPMP_POWERUP; 1186 } else if (vddio >= 3100 && vdda >= 3100) { 1187 /* 1188 * if vddio and vddd > 3.1v, 1189 * charge pump should be clean before set ana_pwr 1190 */ 1191 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER, 1192 SGTL5000_VDDC_CHRGPMP_POWERUP, 0); 1193 1194 /* VDDC use VDDIO rail */ 1195 lreg_ctrl |= SGTL5000_VDDC_ASSN_OVRD; 1196 lreg_ctrl |= SGTL5000_VDDC_MAN_ASSN_VDDIO << 1197 SGTL5000_VDDC_MAN_ASSN_SHIFT; 1198 } 1199 1200 snd_soc_write(codec, SGTL5000_CHIP_LINREG_CTRL, lreg_ctrl); 1201 1202 snd_soc_write(codec, SGTL5000_CHIP_ANA_POWER, ana_pwr); 1203 1204 /* set voltage to register */ 1205 snd_soc_update_bits(codec, SGTL5000_CHIP_LINREG_CTRL, 1206 SGTL5000_LINREG_VDDD_MASK, 0x8); 1207 1208 /* 1209 * if vddd linear reg has been enabled, 1210 * simple digital supply should be clear to get 1211 * proper VDDD voltage. 1212 */ 1213 if (ana_pwr & SGTL5000_LINEREG_D_POWERUP) 1214 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER, 1215 SGTL5000_LINREG_SIMPLE_POWERUP, 1216 0); 1217 else 1218 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER, 1219 SGTL5000_LINREG_SIMPLE_POWERUP | 1220 SGTL5000_STARTUP_POWERUP, 1221 0); 1222 1223 /* 1224 * set ADC/DAC VAG to vdda / 2, 1225 * should stay in range (0.8v, 1.575v) 1226 */ 1227 vag = vdda / 2; 1228 if (vag <= SGTL5000_ANA_GND_BASE) 1229 vag = 0; 1230 else if (vag >= SGTL5000_ANA_GND_BASE + SGTL5000_ANA_GND_STP * 1231 (SGTL5000_ANA_GND_MASK >> SGTL5000_ANA_GND_SHIFT)) 1232 vag = SGTL5000_ANA_GND_MASK >> SGTL5000_ANA_GND_SHIFT; 1233 else 1234 vag = (vag - SGTL5000_ANA_GND_BASE) / SGTL5000_ANA_GND_STP; 1235 1236 snd_soc_update_bits(codec, SGTL5000_CHIP_REF_CTRL, 1237 SGTL5000_ANA_GND_MASK, vag << SGTL5000_ANA_GND_SHIFT); 1238 1239 /* set line out VAG to vddio / 2, in range (0.8v, 1.675v) */ 1240 vag = vddio / 2; 1241 if (vag <= SGTL5000_LINE_OUT_GND_BASE) 1242 vag = 0; 1243 else if (vag >= SGTL5000_LINE_OUT_GND_BASE + 1244 SGTL5000_LINE_OUT_GND_STP * SGTL5000_LINE_OUT_GND_MAX) 1245 vag = SGTL5000_LINE_OUT_GND_MAX; 1246 else 1247 vag = (vag - SGTL5000_LINE_OUT_GND_BASE) / 1248 SGTL5000_LINE_OUT_GND_STP; 1249 1250 snd_soc_update_bits(codec, SGTL5000_CHIP_LINE_OUT_CTRL, 1251 SGTL5000_LINE_OUT_CURRENT_MASK | 1252 SGTL5000_LINE_OUT_GND_MASK, 1253 vag << SGTL5000_LINE_OUT_GND_SHIFT | 1254 SGTL5000_LINE_OUT_CURRENT_360u << 1255 SGTL5000_LINE_OUT_CURRENT_SHIFT); 1256 1257 return 0; 1258 } 1259 1260 static int sgtl5000_replace_vddd_with_ldo(struct snd_soc_codec *codec) 1261 { 1262 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); 1263 int ret; 1264 1265 /* set internal ldo to 1.2v */ 1266 ret = ldo_regulator_register(codec, &ldo_init_data, LDO_VOLTAGE); 1267 if (ret) { 1268 dev_err(codec->dev, 1269 "Failed to register vddd internal supplies: %d\n", ret); 1270 return ret; 1271 } 1272 1273 sgtl5000->supplies[VDDD].supply = LDO_CONSUMER_NAME; 1274 1275 ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(sgtl5000->supplies), 1276 sgtl5000->supplies); 1277 1278 if (ret) { 1279 ldo_regulator_remove(codec); 1280 dev_err(codec->dev, "Failed to request supplies: %d\n", ret); 1281 return ret; 1282 } 1283 1284 dev_info(codec->dev, "Using internal LDO instead of VDDD\n"); 1285 return 0; 1286 } 1287 1288 static int sgtl5000_enable_regulators(struct snd_soc_codec *codec) 1289 { 1290 int reg; 1291 int ret; 1292 int rev; 1293 int i; 1294 int external_vddd = 0; 1295 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); 1296 1297 for (i = 0; i < ARRAY_SIZE(sgtl5000->supplies); i++) 1298 sgtl5000->supplies[i].supply = supply_names[i]; 1299 1300 ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(sgtl5000->supplies), 1301 sgtl5000->supplies); 1302 if (!ret) 1303 external_vddd = 1; 1304 else { 1305 ret = sgtl5000_replace_vddd_with_ldo(codec); 1306 if (ret) 1307 return ret; 1308 } 1309 1310 ret = regulator_bulk_enable(ARRAY_SIZE(sgtl5000->supplies), 1311 sgtl5000->supplies); 1312 if (ret) 1313 goto err_regulator_free; 1314 1315 /* wait for all power rails bring up */ 1316 udelay(10); 1317 1318 /* 1319 * workaround for revision 0x11 and later, 1320 * roll back to use internal LDO 1321 */ 1322 1323 ret = regmap_read(sgtl5000->regmap, SGTL5000_CHIP_ID, ®); 1324 if (ret) 1325 goto err_regulator_disable; 1326 1327 rev = (reg & SGTL5000_REVID_MASK) >> SGTL5000_REVID_SHIFT; 1328 1329 if (external_vddd && rev >= 0x11) { 1330 /* disable all regulator first */ 1331 regulator_bulk_disable(ARRAY_SIZE(sgtl5000->supplies), 1332 sgtl5000->supplies); 1333 /* free VDDD regulator */ 1334 regulator_bulk_free(ARRAY_SIZE(sgtl5000->supplies), 1335 sgtl5000->supplies); 1336 1337 ret = sgtl5000_replace_vddd_with_ldo(codec); 1338 if (ret) 1339 return ret; 1340 1341 ret = regulator_bulk_enable(ARRAY_SIZE(sgtl5000->supplies), 1342 sgtl5000->supplies); 1343 if (ret) 1344 goto err_regulator_free; 1345 1346 /* wait for all power rails bring up */ 1347 udelay(10); 1348 } 1349 1350 return 0; 1351 1352 err_regulator_disable: 1353 regulator_bulk_disable(ARRAY_SIZE(sgtl5000->supplies), 1354 sgtl5000->supplies); 1355 err_regulator_free: 1356 regulator_bulk_free(ARRAY_SIZE(sgtl5000->supplies), 1357 sgtl5000->supplies); 1358 if (external_vddd) 1359 ldo_regulator_remove(codec); 1360 return ret; 1361 1362 } 1363 1364 static int sgtl5000_probe(struct snd_soc_codec *codec) 1365 { 1366 int ret; 1367 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); 1368 1369 /* setup i2c data ops */ 1370 codec->control_data = sgtl5000->regmap; 1371 ret = snd_soc_codec_set_cache_io(codec, 16, 16, SND_SOC_REGMAP); 1372 if (ret < 0) { 1373 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret); 1374 return ret; 1375 } 1376 1377 ret = sgtl5000_enable_regulators(codec); 1378 if (ret) 1379 return ret; 1380 1381 /* power up sgtl5000 */ 1382 ret = sgtl5000_set_power_regs(codec); 1383 if (ret) 1384 goto err; 1385 1386 /* enable small pop, introduce 400ms delay in turning off */ 1387 snd_soc_update_bits(codec, SGTL5000_CHIP_REF_CTRL, 1388 SGTL5000_SMALL_POP, 1389 SGTL5000_SMALL_POP); 1390 1391 /* disable short cut detector */ 1392 snd_soc_write(codec, SGTL5000_CHIP_SHORT_CTRL, 0); 1393 1394 /* 1395 * set i2s as default input of sound switch 1396 * TODO: add sound switch to control and dapm widge. 1397 */ 1398 snd_soc_write(codec, SGTL5000_CHIP_SSS_CTRL, 1399 SGTL5000_DAC_SEL_I2S_IN << SGTL5000_DAC_SEL_SHIFT); 1400 snd_soc_write(codec, SGTL5000_CHIP_DIG_POWER, 1401 SGTL5000_ADC_EN | SGTL5000_DAC_EN); 1402 1403 /* enable dac volume ramp by default */ 1404 snd_soc_write(codec, SGTL5000_CHIP_ADCDAC_CTRL, 1405 SGTL5000_DAC_VOL_RAMP_EN | 1406 SGTL5000_DAC_MUTE_RIGHT | 1407 SGTL5000_DAC_MUTE_LEFT); 1408 1409 snd_soc_write(codec, SGTL5000_CHIP_PAD_STRENGTH, 0x015f); 1410 1411 snd_soc_write(codec, SGTL5000_CHIP_ANA_CTRL, 1412 SGTL5000_HP_ZCD_EN | 1413 SGTL5000_ADC_ZCD_EN); 1414 1415 snd_soc_write(codec, SGTL5000_CHIP_MIC_CTRL, 2); 1416 1417 /* 1418 * disable DAP 1419 * TODO: 1420 * Enable DAP in kcontrol and dapm. 1421 */ 1422 snd_soc_write(codec, SGTL5000_DAP_CTRL, 0); 1423 1424 /* leading to standby state */ 1425 ret = sgtl5000_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 1426 if (ret) 1427 goto err; 1428 1429 return 0; 1430 1431 err: 1432 regulator_bulk_disable(ARRAY_SIZE(sgtl5000->supplies), 1433 sgtl5000->supplies); 1434 regulator_bulk_free(ARRAY_SIZE(sgtl5000->supplies), 1435 sgtl5000->supplies); 1436 ldo_regulator_remove(codec); 1437 1438 return ret; 1439 } 1440 1441 static int sgtl5000_remove(struct snd_soc_codec *codec) 1442 { 1443 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); 1444 1445 sgtl5000_set_bias_level(codec, SND_SOC_BIAS_OFF); 1446 1447 regulator_bulk_disable(ARRAY_SIZE(sgtl5000->supplies), 1448 sgtl5000->supplies); 1449 regulator_bulk_free(ARRAY_SIZE(sgtl5000->supplies), 1450 sgtl5000->supplies); 1451 ldo_regulator_remove(codec); 1452 1453 return 0; 1454 } 1455 1456 static struct snd_soc_codec_driver sgtl5000_driver = { 1457 .probe = sgtl5000_probe, 1458 .remove = sgtl5000_remove, 1459 .suspend = sgtl5000_suspend, 1460 .resume = sgtl5000_resume, 1461 .set_bias_level = sgtl5000_set_bias_level, 1462 .controls = sgtl5000_snd_controls, 1463 .num_controls = ARRAY_SIZE(sgtl5000_snd_controls), 1464 .dapm_widgets = sgtl5000_dapm_widgets, 1465 .num_dapm_widgets = ARRAY_SIZE(sgtl5000_dapm_widgets), 1466 .dapm_routes = sgtl5000_dapm_routes, 1467 .num_dapm_routes = ARRAY_SIZE(sgtl5000_dapm_routes), 1468 }; 1469 1470 static const struct regmap_config sgtl5000_regmap = { 1471 .reg_bits = 16, 1472 .val_bits = 16, 1473 1474 .max_register = SGTL5000_MAX_REG_OFFSET, 1475 .volatile_reg = sgtl5000_volatile, 1476 .readable_reg = sgtl5000_readable, 1477 1478 .cache_type = REGCACHE_RBTREE, 1479 .reg_defaults = sgtl5000_reg_defaults, 1480 .num_reg_defaults = ARRAY_SIZE(sgtl5000_reg_defaults), 1481 }; 1482 1483 /* 1484 * Write all the default values from sgtl5000_reg_defaults[] array into the 1485 * sgtl5000 registers, to make sure we always start with the sane registers 1486 * values as stated in the datasheet. 1487 * 1488 * Since sgtl5000 does not have a reset line, nor a reset command in software, 1489 * we follow this approach to guarantee we always start from the default values 1490 * and avoid problems like, not being able to probe after an audio playback 1491 * followed by a system reset or a 'reboot' command in Linux 1492 */ 1493 static int sgtl5000_fill_defaults(struct sgtl5000_priv *sgtl5000) 1494 { 1495 int i, ret, val, index; 1496 1497 for (i = 0; i < ARRAY_SIZE(sgtl5000_reg_defaults); i++) { 1498 val = sgtl5000_reg_defaults[i].def; 1499 index = sgtl5000_reg_defaults[i].reg; 1500 ret = regmap_write(sgtl5000->regmap, index, val); 1501 if (ret) 1502 return ret; 1503 } 1504 1505 return 0; 1506 } 1507 1508 static int sgtl5000_i2c_probe(struct i2c_client *client, 1509 const struct i2c_device_id *id) 1510 { 1511 struct sgtl5000_priv *sgtl5000; 1512 int ret, reg, rev; 1513 1514 sgtl5000 = devm_kzalloc(&client->dev, sizeof(struct sgtl5000_priv), 1515 GFP_KERNEL); 1516 if (!sgtl5000) 1517 return -ENOMEM; 1518 1519 sgtl5000->regmap = devm_regmap_init_i2c(client, &sgtl5000_regmap); 1520 if (IS_ERR(sgtl5000->regmap)) { 1521 ret = PTR_ERR(sgtl5000->regmap); 1522 dev_err(&client->dev, "Failed to allocate regmap: %d\n", ret); 1523 return ret; 1524 } 1525 1526 sgtl5000->mclk = devm_clk_get(&client->dev, NULL); 1527 if (IS_ERR(sgtl5000->mclk)) { 1528 ret = PTR_ERR(sgtl5000->mclk); 1529 dev_err(&client->dev, "Failed to get mclock: %d\n", ret); 1530 return ret; 1531 } 1532 1533 ret = clk_prepare_enable(sgtl5000->mclk); 1534 if (ret) 1535 return ret; 1536 1537 /* read chip information */ 1538 ret = regmap_read(sgtl5000->regmap, SGTL5000_CHIP_ID, ®); 1539 if (ret) 1540 goto disable_clk; 1541 1542 if (((reg & SGTL5000_PARTID_MASK) >> SGTL5000_PARTID_SHIFT) != 1543 SGTL5000_PARTID_PART_ID) { 1544 dev_err(&client->dev, 1545 "Device with ID register %x is not a sgtl5000\n", reg); 1546 ret = -ENODEV; 1547 goto disable_clk; 1548 } 1549 1550 rev = (reg & SGTL5000_REVID_MASK) >> SGTL5000_REVID_SHIFT; 1551 dev_info(&client->dev, "sgtl5000 revision 0x%x\n", rev); 1552 1553 i2c_set_clientdata(client, sgtl5000); 1554 1555 /* Ensure sgtl5000 will start with sane register values */ 1556 ret = sgtl5000_fill_defaults(sgtl5000); 1557 if (ret) 1558 goto disable_clk; 1559 1560 ret = snd_soc_register_codec(&client->dev, 1561 &sgtl5000_driver, &sgtl5000_dai, 1); 1562 if (ret) 1563 goto disable_clk; 1564 1565 return 0; 1566 1567 disable_clk: 1568 clk_disable_unprepare(sgtl5000->mclk); 1569 return ret; 1570 } 1571 1572 static int sgtl5000_i2c_remove(struct i2c_client *client) 1573 { 1574 struct sgtl5000_priv *sgtl5000 = i2c_get_clientdata(client); 1575 1576 snd_soc_unregister_codec(&client->dev); 1577 clk_disable_unprepare(sgtl5000->mclk); 1578 return 0; 1579 } 1580 1581 static const struct i2c_device_id sgtl5000_id[] = { 1582 {"sgtl5000", 0}, 1583 {}, 1584 }; 1585 1586 MODULE_DEVICE_TABLE(i2c, sgtl5000_id); 1587 1588 static const struct of_device_id sgtl5000_dt_ids[] = { 1589 { .compatible = "fsl,sgtl5000", }, 1590 { /* sentinel */ } 1591 }; 1592 MODULE_DEVICE_TABLE(of, sgtl5000_dt_ids); 1593 1594 static struct i2c_driver sgtl5000_i2c_driver = { 1595 .driver = { 1596 .name = "sgtl5000", 1597 .owner = THIS_MODULE, 1598 .of_match_table = sgtl5000_dt_ids, 1599 }, 1600 .probe = sgtl5000_i2c_probe, 1601 .remove = sgtl5000_i2c_remove, 1602 .id_table = sgtl5000_id, 1603 }; 1604 1605 module_i2c_driver(sgtl5000_i2c_driver); 1606 1607 MODULE_DESCRIPTION("Freescale SGTL5000 ALSA SoC Codec Driver"); 1608 MODULE_AUTHOR("Zeng Zhaoming <zengzm.kernel@gmail.com>"); 1609 MODULE_LICENSE("GPL"); 1610