1 /* 2 * sgtl5000.c -- SGTL5000 ALSA SoC Audio driver 3 * 4 * Copyright 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11 #include <linux/module.h> 12 #include <linux/moduleparam.h> 13 #include <linux/init.h> 14 #include <linux/delay.h> 15 #include <linux/slab.h> 16 #include <linux/pm.h> 17 #include <linux/i2c.h> 18 #include <linux/clk.h> 19 #include <linux/log2.h> 20 #include <linux/regmap.h> 21 #include <linux/regulator/driver.h> 22 #include <linux/regulator/machine.h> 23 #include <linux/regulator/consumer.h> 24 #include <linux/of_device.h> 25 #include <sound/core.h> 26 #include <sound/tlv.h> 27 #include <sound/pcm.h> 28 #include <sound/pcm_params.h> 29 #include <sound/soc.h> 30 #include <sound/soc-dapm.h> 31 #include <sound/initval.h> 32 33 #include "sgtl5000.h" 34 35 #define SGTL5000_DAP_REG_OFFSET 0x0100 36 #define SGTL5000_MAX_REG_OFFSET 0x013A 37 38 /* default value of sgtl5000 registers */ 39 static const struct reg_default sgtl5000_reg_defaults[] = { 40 { SGTL5000_CHIP_DIG_POWER, 0x0000 }, 41 { SGTL5000_CHIP_I2S_CTRL, 0x0010 }, 42 { SGTL5000_CHIP_SSS_CTRL, 0x0010 }, 43 { SGTL5000_CHIP_ADCDAC_CTRL, 0x020c }, 44 { SGTL5000_CHIP_DAC_VOL, 0x3c3c }, 45 { SGTL5000_CHIP_PAD_STRENGTH, 0x015f }, 46 { SGTL5000_CHIP_ANA_ADC_CTRL, 0x0000 }, 47 { SGTL5000_CHIP_ANA_HP_CTRL, 0x1818 }, 48 { SGTL5000_CHIP_ANA_CTRL, 0x0111 }, 49 { SGTL5000_CHIP_REF_CTRL, 0x0000 }, 50 { SGTL5000_CHIP_MIC_CTRL, 0x0000 }, 51 { SGTL5000_CHIP_LINE_OUT_CTRL, 0x0000 }, 52 { SGTL5000_CHIP_LINE_OUT_VOL, 0x0404 }, 53 { SGTL5000_CHIP_PLL_CTRL, 0x5000 }, 54 { SGTL5000_CHIP_CLK_TOP_CTRL, 0x0000 }, 55 { SGTL5000_CHIP_ANA_STATUS, 0x0000 }, 56 { SGTL5000_CHIP_SHORT_CTRL, 0x0000 }, 57 { SGTL5000_CHIP_ANA_TEST2, 0x0000 }, 58 { SGTL5000_DAP_CTRL, 0x0000 }, 59 { SGTL5000_DAP_PEQ, 0x0000 }, 60 { SGTL5000_DAP_BASS_ENHANCE, 0x0040 }, 61 { SGTL5000_DAP_BASS_ENHANCE_CTRL, 0x051f }, 62 { SGTL5000_DAP_AUDIO_EQ, 0x0000 }, 63 { SGTL5000_DAP_SURROUND, 0x0040 }, 64 { SGTL5000_DAP_EQ_BASS_BAND0, 0x002f }, 65 { SGTL5000_DAP_EQ_BASS_BAND1, 0x002f }, 66 { SGTL5000_DAP_EQ_BASS_BAND2, 0x002f }, 67 { SGTL5000_DAP_EQ_BASS_BAND3, 0x002f }, 68 { SGTL5000_DAP_EQ_BASS_BAND4, 0x002f }, 69 { SGTL5000_DAP_MAIN_CHAN, 0x8000 }, 70 { SGTL5000_DAP_MIX_CHAN, 0x0000 }, 71 { SGTL5000_DAP_AVC_CTRL, 0x0510 }, 72 { SGTL5000_DAP_AVC_THRESHOLD, 0x1473 }, 73 { SGTL5000_DAP_AVC_ATTACK, 0x0028 }, 74 { SGTL5000_DAP_AVC_DECAY, 0x0050 }, 75 }; 76 77 /* AVC: Threshold dB -> register: pre-calculated values */ 78 static const u16 avc_thr_db2reg[97] = { 79 0x5168, 0x488E, 0x40AA, 0x39A1, 0x335D, 0x2DC7, 0x28CC, 0x245D, 0x2068, 80 0x1CE2, 0x19BE, 0x16F1, 0x1472, 0x1239, 0x103E, 0x0E7A, 0x0CE6, 0x0B7F, 81 0x0A3F, 0x0922, 0x0824, 0x0741, 0x0677, 0x05C3, 0x0522, 0x0493, 0x0414, 82 0x03A2, 0x033D, 0x02E3, 0x0293, 0x024B, 0x020B, 0x01D2, 0x019F, 0x0172, 83 0x014A, 0x0126, 0x0106, 0x00E9, 0x00D0, 0x00B9, 0x00A5, 0x0093, 0x0083, 84 0x0075, 0x0068, 0x005D, 0x0052, 0x0049, 0x0041, 0x003A, 0x0034, 0x002E, 85 0x0029, 0x0025, 0x0021, 0x001D, 0x001A, 0x0017, 0x0014, 0x0012, 0x0010, 86 0x000E, 0x000D, 0x000B, 0x000A, 0x0009, 0x0008, 0x0007, 0x0006, 0x0005, 87 0x0005, 0x0004, 0x0004, 0x0003, 0x0003, 0x0002, 0x0002, 0x0002, 0x0002, 88 0x0001, 0x0001, 0x0001, 0x0001, 0x0001, 0x0001, 0x0000, 0x0000, 0x0000, 89 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000}; 90 91 /* regulator supplies for sgtl5000, VDDD is an optional external supply */ 92 enum sgtl5000_regulator_supplies { 93 VDDA, 94 VDDIO, 95 VDDD, 96 SGTL5000_SUPPLY_NUM 97 }; 98 99 /* vddd is optional supply */ 100 static const char *supply_names[SGTL5000_SUPPLY_NUM] = { 101 "VDDA", 102 "VDDIO", 103 "VDDD" 104 }; 105 106 #define LDO_VOLTAGE 1200000 107 #define LINREG_VDDD ((1600 - LDO_VOLTAGE / 1000) / 50) 108 109 enum sgtl5000_micbias_resistor { 110 SGTL5000_MICBIAS_OFF = 0, 111 SGTL5000_MICBIAS_2K = 2, 112 SGTL5000_MICBIAS_4K = 4, 113 SGTL5000_MICBIAS_8K = 8, 114 }; 115 116 enum { 117 I2S_LRCLK_STRENGTH_DISABLE, 118 I2S_LRCLK_STRENGTH_LOW, 119 I2S_LRCLK_STRENGTH_MEDIUM, 120 I2S_LRCLK_STRENGTH_HIGH, 121 }; 122 123 /* sgtl5000 private structure in codec */ 124 struct sgtl5000_priv { 125 int sysclk; /* sysclk rate */ 126 int master; /* i2s master or not */ 127 int fmt; /* i2s data format */ 128 struct regulator_bulk_data supplies[SGTL5000_SUPPLY_NUM]; 129 int num_supplies; 130 struct regmap *regmap; 131 struct clk *mclk; 132 int revision; 133 u8 micbias_resistor; 134 u8 micbias_voltage; 135 u8 lrclk_strength; 136 }; 137 138 /* 139 * mic_bias power on/off share the same register bits with 140 * output impedance of mic bias, when power on mic bias, we 141 * need reclaim it to impedance value. 142 * 0x0 = Powered off 143 * 0x1 = 2Kohm 144 * 0x2 = 4Kohm 145 * 0x3 = 8Kohm 146 */ 147 static int mic_bias_event(struct snd_soc_dapm_widget *w, 148 struct snd_kcontrol *kcontrol, int event) 149 { 150 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 151 struct sgtl5000_priv *sgtl5000 = snd_soc_component_get_drvdata(component); 152 153 switch (event) { 154 case SND_SOC_DAPM_POST_PMU: 155 /* change mic bias resistor */ 156 snd_soc_component_update_bits(component, SGTL5000_CHIP_MIC_CTRL, 157 SGTL5000_BIAS_R_MASK, 158 sgtl5000->micbias_resistor << SGTL5000_BIAS_R_SHIFT); 159 break; 160 161 case SND_SOC_DAPM_PRE_PMD: 162 snd_soc_component_update_bits(component, SGTL5000_CHIP_MIC_CTRL, 163 SGTL5000_BIAS_R_MASK, 0); 164 break; 165 } 166 return 0; 167 } 168 169 /* 170 * As manual described, ADC/DAC only works when VAG powerup, 171 * So enabled VAG before ADC/DAC up. 172 * In power down case, we need wait 400ms when vag fully ramped down. 173 */ 174 static int power_vag_event(struct snd_soc_dapm_widget *w, 175 struct snd_kcontrol *kcontrol, int event) 176 { 177 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 178 const u32 mask = SGTL5000_DAC_POWERUP | SGTL5000_ADC_POWERUP; 179 180 switch (event) { 181 case SND_SOC_DAPM_POST_PMU: 182 snd_soc_component_update_bits(component, SGTL5000_CHIP_ANA_POWER, 183 SGTL5000_VAG_POWERUP, SGTL5000_VAG_POWERUP); 184 msleep(400); 185 break; 186 187 case SND_SOC_DAPM_PRE_PMD: 188 /* 189 * Don't clear VAG_POWERUP, when both DAC and ADC are 190 * operational to prevent inadvertently starving the 191 * other one of them. 192 */ 193 if ((snd_soc_component_read32(component, SGTL5000_CHIP_ANA_POWER) & 194 mask) != mask) { 195 snd_soc_component_update_bits(component, SGTL5000_CHIP_ANA_POWER, 196 SGTL5000_VAG_POWERUP, 0); 197 msleep(400); 198 } 199 break; 200 default: 201 break; 202 } 203 204 return 0; 205 } 206 207 /* input sources for ADC */ 208 static const char *adc_mux_text[] = { 209 "MIC_IN", "LINE_IN" 210 }; 211 212 static SOC_ENUM_SINGLE_DECL(adc_enum, 213 SGTL5000_CHIP_ANA_CTRL, 2, 214 adc_mux_text); 215 216 static const struct snd_kcontrol_new adc_mux = 217 SOC_DAPM_ENUM("Capture Mux", adc_enum); 218 219 /* input sources for headphone */ 220 static const char *hp_mux_text[] = { 221 "DAC", "LINE_IN" 222 }; 223 224 static SOC_ENUM_SINGLE_DECL(hp_enum, 225 SGTL5000_CHIP_ANA_CTRL, 6, 226 hp_mux_text); 227 228 static const struct snd_kcontrol_new hp_mux = 229 SOC_DAPM_ENUM("Headphone Mux", hp_enum); 230 231 /* input sources for DAC */ 232 static const char *dac_mux_text[] = { 233 "ADC", "I2S", "Rsvrd", "DAP" 234 }; 235 236 static SOC_ENUM_SINGLE_DECL(dac_enum, 237 SGTL5000_CHIP_SSS_CTRL, SGTL5000_DAC_SEL_SHIFT, 238 dac_mux_text); 239 240 static const struct snd_kcontrol_new dac_mux = 241 SOC_DAPM_ENUM("Digital Input Mux", dac_enum); 242 243 /* input sources for DAP */ 244 static const char *dap_mux_text[] = { 245 "ADC", "I2S" 246 }; 247 248 static SOC_ENUM_SINGLE_DECL(dap_enum, 249 SGTL5000_CHIP_SSS_CTRL, SGTL5000_DAP_SEL_SHIFT, 250 dap_mux_text); 251 252 static const struct snd_kcontrol_new dap_mux = 253 SOC_DAPM_ENUM("DAP Mux", dap_enum); 254 255 /* input sources for DAP mix */ 256 static const char *dapmix_mux_text[] = { 257 "ADC", "I2S" 258 }; 259 260 static SOC_ENUM_SINGLE_DECL(dapmix_enum, 261 SGTL5000_CHIP_SSS_CTRL, SGTL5000_DAP_MIX_SEL_SHIFT, 262 dapmix_mux_text); 263 264 static const struct snd_kcontrol_new dapmix_mux = 265 SOC_DAPM_ENUM("DAP MIX Mux", dapmix_enum); 266 267 268 static const struct snd_soc_dapm_widget sgtl5000_dapm_widgets[] = { 269 SND_SOC_DAPM_INPUT("LINE_IN"), 270 SND_SOC_DAPM_INPUT("MIC_IN"), 271 272 SND_SOC_DAPM_OUTPUT("HP_OUT"), 273 SND_SOC_DAPM_OUTPUT("LINE_OUT"), 274 275 SND_SOC_DAPM_SUPPLY("Mic Bias", SGTL5000_CHIP_MIC_CTRL, 8, 0, 276 mic_bias_event, 277 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 278 279 SND_SOC_DAPM_PGA("HP", SGTL5000_CHIP_ANA_POWER, 4, 0, NULL, 0), 280 SND_SOC_DAPM_PGA("LO", SGTL5000_CHIP_ANA_POWER, 0, 0, NULL, 0), 281 282 SND_SOC_DAPM_MUX("Capture Mux", SND_SOC_NOPM, 0, 0, &adc_mux), 283 SND_SOC_DAPM_MUX("Headphone Mux", SND_SOC_NOPM, 0, 0, &hp_mux), 284 SND_SOC_DAPM_MUX("Digital Input Mux", SND_SOC_NOPM, 0, 0, &dac_mux), 285 SND_SOC_DAPM_MUX("DAP Mux", SGTL5000_DAP_CTRL, 0, 0, &dap_mux), 286 SND_SOC_DAPM_MUX("DAP MIX Mux", SGTL5000_DAP_CTRL, 4, 0, &dapmix_mux), 287 SND_SOC_DAPM_MIXER("DAP", SGTL5000_CHIP_DIG_POWER, 4, 0, NULL, 0), 288 289 290 /* aif for i2s input */ 291 SND_SOC_DAPM_AIF_IN("AIFIN", "Playback", 292 0, SGTL5000_CHIP_DIG_POWER, 293 0, 0), 294 295 /* aif for i2s output */ 296 SND_SOC_DAPM_AIF_OUT("AIFOUT", "Capture", 297 0, SGTL5000_CHIP_DIG_POWER, 298 1, 0), 299 300 SND_SOC_DAPM_ADC("ADC", "Capture", SGTL5000_CHIP_ANA_POWER, 1, 0), 301 SND_SOC_DAPM_DAC("DAC", "Playback", SGTL5000_CHIP_ANA_POWER, 3, 0), 302 303 SND_SOC_DAPM_PRE("VAG_POWER_PRE", power_vag_event), 304 SND_SOC_DAPM_POST("VAG_POWER_POST", power_vag_event), 305 }; 306 307 /* routes for sgtl5000 */ 308 static const struct snd_soc_dapm_route sgtl5000_dapm_routes[] = { 309 {"Capture Mux", "LINE_IN", "LINE_IN"}, /* line_in --> adc_mux */ 310 {"Capture Mux", "MIC_IN", "MIC_IN"}, /* mic_in --> adc_mux */ 311 312 {"ADC", NULL, "Capture Mux"}, /* adc_mux --> adc */ 313 {"AIFOUT", NULL, "ADC"}, /* adc --> i2s_out */ 314 315 {"DAP Mux", "ADC", "ADC"}, /* adc --> DAP mux */ 316 {"DAP Mux", NULL, "AIFIN"}, /* i2s --> DAP mux */ 317 {"DAP", NULL, "DAP Mux"}, /* DAP mux --> dap */ 318 319 {"DAP MIX Mux", "ADC", "ADC"}, /* adc --> DAP MIX mux */ 320 {"DAP MIX Mux", NULL, "AIFIN"}, /* i2s --> DAP MIX mux */ 321 {"DAP", NULL, "DAP MIX Mux"}, /* DAP MIX mux --> dap */ 322 323 {"Digital Input Mux", "ADC", "ADC"}, /* adc --> audio mux */ 324 {"Digital Input Mux", NULL, "AIFIN"}, /* i2s --> audio mux */ 325 {"Digital Input Mux", NULL, "DAP"}, /* dap --> audio mux */ 326 {"DAC", NULL, "Digital Input Mux"}, /* audio mux --> dac */ 327 328 {"Headphone Mux", "DAC", "DAC"}, /* dac --> hp_mux */ 329 {"LO", NULL, "DAC"}, /* dac --> line_out */ 330 331 {"Headphone Mux", "LINE_IN", "LINE_IN"},/* line_in --> hp_mux */ 332 {"HP", NULL, "Headphone Mux"}, /* hp_mux --> hp */ 333 334 {"LINE_OUT", NULL, "LO"}, 335 {"HP_OUT", NULL, "HP"}, 336 }; 337 338 /* custom function to fetch info of PCM playback volume */ 339 static int dac_info_volsw(struct snd_kcontrol *kcontrol, 340 struct snd_ctl_elem_info *uinfo) 341 { 342 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 343 uinfo->count = 2; 344 uinfo->value.integer.min = 0; 345 uinfo->value.integer.max = 0xfc - 0x3c; 346 return 0; 347 } 348 349 /* 350 * custom function to get of PCM playback volume 351 * 352 * dac volume register 353 * 15-------------8-7--------------0 354 * | R channel vol | L channel vol | 355 * ------------------------------- 356 * 357 * PCM volume with 0.5017 dB steps from 0 to -90 dB 358 * 359 * register values map to dB 360 * 0x3B and less = Reserved 361 * 0x3C = 0 dB 362 * 0x3D = -0.5 dB 363 * 0xF0 = -90 dB 364 * 0xFC and greater = Muted 365 * 366 * register value map to userspace value 367 * 368 * register value 0x3c(0dB) 0xf0(-90dB)0xfc 369 * ------------------------------ 370 * userspace value 0xc0 0 371 */ 372 static int dac_get_volsw(struct snd_kcontrol *kcontrol, 373 struct snd_ctl_elem_value *ucontrol) 374 { 375 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 376 int reg; 377 int l; 378 int r; 379 380 reg = snd_soc_component_read32(component, SGTL5000_CHIP_DAC_VOL); 381 382 /* get left channel volume */ 383 l = (reg & SGTL5000_DAC_VOL_LEFT_MASK) >> SGTL5000_DAC_VOL_LEFT_SHIFT; 384 385 /* get right channel volume */ 386 r = (reg & SGTL5000_DAC_VOL_RIGHT_MASK) >> SGTL5000_DAC_VOL_RIGHT_SHIFT; 387 388 /* make sure value fall in (0x3c,0xfc) */ 389 l = clamp(l, 0x3c, 0xfc); 390 r = clamp(r, 0x3c, 0xfc); 391 392 /* invert it and map to userspace value */ 393 l = 0xfc - l; 394 r = 0xfc - r; 395 396 ucontrol->value.integer.value[0] = l; 397 ucontrol->value.integer.value[1] = r; 398 399 return 0; 400 } 401 402 /* 403 * custom function to put of PCM playback volume 404 * 405 * dac volume register 406 * 15-------------8-7--------------0 407 * | R channel vol | L channel vol | 408 * ------------------------------- 409 * 410 * PCM volume with 0.5017 dB steps from 0 to -90 dB 411 * 412 * register values map to dB 413 * 0x3B and less = Reserved 414 * 0x3C = 0 dB 415 * 0x3D = -0.5 dB 416 * 0xF0 = -90 dB 417 * 0xFC and greater = Muted 418 * 419 * userspace value map to register value 420 * 421 * userspace value 0xc0 0 422 * ------------------------------ 423 * register value 0x3c(0dB) 0xf0(-90dB)0xfc 424 */ 425 static int dac_put_volsw(struct snd_kcontrol *kcontrol, 426 struct snd_ctl_elem_value *ucontrol) 427 { 428 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 429 int reg; 430 int l; 431 int r; 432 433 l = ucontrol->value.integer.value[0]; 434 r = ucontrol->value.integer.value[1]; 435 436 /* make sure userspace volume fall in (0, 0xfc-0x3c) */ 437 l = clamp(l, 0, 0xfc - 0x3c); 438 r = clamp(r, 0, 0xfc - 0x3c); 439 440 /* invert it, get the value can be set to register */ 441 l = 0xfc - l; 442 r = 0xfc - r; 443 444 /* shift to get the register value */ 445 reg = l << SGTL5000_DAC_VOL_LEFT_SHIFT | 446 r << SGTL5000_DAC_VOL_RIGHT_SHIFT; 447 448 snd_soc_component_write(component, SGTL5000_CHIP_DAC_VOL, reg); 449 450 return 0; 451 } 452 453 /* 454 * custom function to get AVC threshold 455 * 456 * The threshold dB is calculated by rearranging the calculation from the 457 * avc_put_threshold function: register_value = 10^(dB/20) * 0.636 * 2^15 ==> 458 * dB = ( fls(register_value) - 14.347 ) * 6.02 459 * 460 * As this calculation is expensive and the threshold dB values may not exeed 461 * 0 to 96 we use pre-calculated values. 462 */ 463 static int avc_get_threshold(struct snd_kcontrol *kcontrol, 464 struct snd_ctl_elem_value *ucontrol) 465 { 466 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 467 int db, i; 468 u16 reg = snd_soc_component_read32(component, SGTL5000_DAP_AVC_THRESHOLD); 469 470 /* register value 0 => -96dB */ 471 if (!reg) { 472 ucontrol->value.integer.value[0] = 96; 473 ucontrol->value.integer.value[1] = 96; 474 return 0; 475 } 476 477 /* get dB from register value (rounded down) */ 478 for (i = 0; avc_thr_db2reg[i] > reg; i++) 479 ; 480 db = i; 481 482 ucontrol->value.integer.value[0] = db; 483 ucontrol->value.integer.value[1] = db; 484 485 return 0; 486 } 487 488 /* 489 * custom function to put AVC threshold 490 * 491 * The register value is calculated by following formula: 492 * register_value = 10^(dB/20) * 0.636 * 2^15 493 * As this calculation is expensive and the threshold dB values may not exeed 494 * 0 to 96 we use pre-calculated values. 495 */ 496 static int avc_put_threshold(struct snd_kcontrol *kcontrol, 497 struct snd_ctl_elem_value *ucontrol) 498 { 499 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 500 int db; 501 u16 reg; 502 503 db = (int)ucontrol->value.integer.value[0]; 504 if (db < 0 || db > 96) 505 return -EINVAL; 506 reg = avc_thr_db2reg[db]; 507 snd_soc_component_write(component, SGTL5000_DAP_AVC_THRESHOLD, reg); 508 509 return 0; 510 } 511 512 static const DECLARE_TLV_DB_SCALE(capture_6db_attenuate, -600, 600, 0); 513 514 /* tlv for mic gain, 0db 20db 30db 40db */ 515 static const DECLARE_TLV_DB_RANGE(mic_gain_tlv, 516 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0), 517 1, 3, TLV_DB_SCALE_ITEM(2000, 1000, 0) 518 ); 519 520 /* tlv for DAP channels, 0% - 100% - 200% */ 521 static const DECLARE_TLV_DB_SCALE(dap_volume, 0, 1, 0); 522 523 /* tlv for bass bands, -11.75db to 12.0db, step .25db */ 524 static const DECLARE_TLV_DB_SCALE(bass_band, -1175, 25, 0); 525 526 /* tlv for hp volume, -51.5db to 12.0db, step .5db */ 527 static const DECLARE_TLV_DB_SCALE(headphone_volume, -5150, 50, 0); 528 529 /* tlv for lineout volume, 31 steps of .5db each */ 530 static const DECLARE_TLV_DB_SCALE(lineout_volume, -1550, 50, 0); 531 532 /* tlv for dap avc max gain, 0db, 6db, 12db */ 533 static const DECLARE_TLV_DB_SCALE(avc_max_gain, 0, 600, 0); 534 535 /* tlv for dap avc threshold, */ 536 static const DECLARE_TLV_DB_MINMAX(avc_threshold, 0, 9600); 537 538 static const struct snd_kcontrol_new sgtl5000_snd_controls[] = { 539 /* SOC_DOUBLE_S8_TLV with invert */ 540 { 541 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 542 .name = "PCM Playback Volume", 543 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ | 544 SNDRV_CTL_ELEM_ACCESS_READWRITE, 545 .info = dac_info_volsw, 546 .get = dac_get_volsw, 547 .put = dac_put_volsw, 548 }, 549 550 SOC_DOUBLE("Capture Volume", SGTL5000_CHIP_ANA_ADC_CTRL, 0, 4, 0xf, 0), 551 SOC_SINGLE_TLV("Capture Attenuate Switch (-6dB)", 552 SGTL5000_CHIP_ANA_ADC_CTRL, 553 8, 1, 0, capture_6db_attenuate), 554 SOC_SINGLE("Capture ZC Switch", SGTL5000_CHIP_ANA_CTRL, 1, 1, 0), 555 556 SOC_DOUBLE_TLV("Headphone Playback Volume", 557 SGTL5000_CHIP_ANA_HP_CTRL, 558 0, 8, 559 0x7f, 1, 560 headphone_volume), 561 SOC_SINGLE("Headphone Playback Switch", SGTL5000_CHIP_ANA_CTRL, 562 4, 1, 1), 563 SOC_SINGLE("Headphone Playback ZC Switch", SGTL5000_CHIP_ANA_CTRL, 564 5, 1, 0), 565 566 SOC_SINGLE_TLV("Mic Volume", SGTL5000_CHIP_MIC_CTRL, 567 0, 3, 0, mic_gain_tlv), 568 569 SOC_DOUBLE_TLV("Lineout Playback Volume", 570 SGTL5000_CHIP_LINE_OUT_VOL, 571 SGTL5000_LINE_OUT_VOL_LEFT_SHIFT, 572 SGTL5000_LINE_OUT_VOL_RIGHT_SHIFT, 573 0x1f, 1, 574 lineout_volume), 575 SOC_SINGLE("Lineout Playback Switch", SGTL5000_CHIP_ANA_CTRL, 8, 1, 1), 576 577 SOC_SINGLE_TLV("DAP Main channel", SGTL5000_DAP_MAIN_CHAN, 578 0, 0xffff, 0, dap_volume), 579 580 SOC_SINGLE_TLV("DAP Mix channel", SGTL5000_DAP_MIX_CHAN, 581 0, 0xffff, 0, dap_volume), 582 /* Automatic Volume Control (DAP AVC) */ 583 SOC_SINGLE("AVC Switch", SGTL5000_DAP_AVC_CTRL, 0, 1, 0), 584 SOC_SINGLE("AVC Hard Limiter Switch", SGTL5000_DAP_AVC_CTRL, 5, 1, 0), 585 SOC_SINGLE_TLV("AVC Max Gain Volume", SGTL5000_DAP_AVC_CTRL, 12, 2, 0, 586 avc_max_gain), 587 SOC_SINGLE("AVC Integrator Response", SGTL5000_DAP_AVC_CTRL, 8, 3, 0), 588 SOC_SINGLE_EXT_TLV("AVC Threshold Volume", SGTL5000_DAP_AVC_THRESHOLD, 589 0, 96, 0, avc_get_threshold, avc_put_threshold, 590 avc_threshold), 591 592 SOC_SINGLE_TLV("BASS 0", SGTL5000_DAP_EQ_BASS_BAND0, 593 0, 0x5F, 0, bass_band), 594 595 SOC_SINGLE_TLV("BASS 1", SGTL5000_DAP_EQ_BASS_BAND1, 596 0, 0x5F, 0, bass_band), 597 598 SOC_SINGLE_TLV("BASS 2", SGTL5000_DAP_EQ_BASS_BAND2, 599 0, 0x5F, 0, bass_band), 600 601 SOC_SINGLE_TLV("BASS 3", SGTL5000_DAP_EQ_BASS_BAND3, 602 0, 0x5F, 0, bass_band), 603 604 SOC_SINGLE_TLV("BASS 4", SGTL5000_DAP_EQ_BASS_BAND4, 605 0, 0x5F, 0, bass_band), 606 }; 607 608 /* mute the codec used by alsa core */ 609 static int sgtl5000_digital_mute(struct snd_soc_dai *codec_dai, int mute) 610 { 611 struct snd_soc_component *component = codec_dai->component; 612 u16 i2s_pwr = SGTL5000_I2S_IN_POWERUP; 613 614 /* 615 * During 'digital mute' do not mute DAC 616 * because LINE_IN would be muted aswell. We want to mute 617 * only I2S block - this can be done by powering it off 618 */ 619 snd_soc_component_update_bits(component, SGTL5000_CHIP_DIG_POWER, 620 i2s_pwr, mute ? 0 : i2s_pwr); 621 622 return 0; 623 } 624 625 /* set codec format */ 626 static int sgtl5000_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt) 627 { 628 struct snd_soc_component *component = codec_dai->component; 629 struct sgtl5000_priv *sgtl5000 = snd_soc_component_get_drvdata(component); 630 u16 i2sctl = 0; 631 632 sgtl5000->master = 0; 633 /* 634 * i2s clock and frame master setting. 635 * ONLY support: 636 * - clock and frame slave, 637 * - clock and frame master 638 */ 639 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 640 case SND_SOC_DAIFMT_CBS_CFS: 641 break; 642 case SND_SOC_DAIFMT_CBM_CFM: 643 i2sctl |= SGTL5000_I2S_MASTER; 644 sgtl5000->master = 1; 645 break; 646 default: 647 return -EINVAL; 648 } 649 650 /* setting i2s data format */ 651 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 652 case SND_SOC_DAIFMT_DSP_A: 653 i2sctl |= SGTL5000_I2S_MODE_PCM << SGTL5000_I2S_MODE_SHIFT; 654 break; 655 case SND_SOC_DAIFMT_DSP_B: 656 i2sctl |= SGTL5000_I2S_MODE_PCM << SGTL5000_I2S_MODE_SHIFT; 657 i2sctl |= SGTL5000_I2S_LRALIGN; 658 break; 659 case SND_SOC_DAIFMT_I2S: 660 i2sctl |= SGTL5000_I2S_MODE_I2S_LJ << SGTL5000_I2S_MODE_SHIFT; 661 break; 662 case SND_SOC_DAIFMT_RIGHT_J: 663 i2sctl |= SGTL5000_I2S_MODE_RJ << SGTL5000_I2S_MODE_SHIFT; 664 i2sctl |= SGTL5000_I2S_LRPOL; 665 break; 666 case SND_SOC_DAIFMT_LEFT_J: 667 i2sctl |= SGTL5000_I2S_MODE_I2S_LJ << SGTL5000_I2S_MODE_SHIFT; 668 i2sctl |= SGTL5000_I2S_LRALIGN; 669 break; 670 default: 671 return -EINVAL; 672 } 673 674 sgtl5000->fmt = fmt & SND_SOC_DAIFMT_FORMAT_MASK; 675 676 /* Clock inversion */ 677 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 678 case SND_SOC_DAIFMT_NB_NF: 679 break; 680 case SND_SOC_DAIFMT_IB_NF: 681 i2sctl |= SGTL5000_I2S_SCLK_INV; 682 break; 683 default: 684 return -EINVAL; 685 } 686 687 snd_soc_component_write(component, SGTL5000_CHIP_I2S_CTRL, i2sctl); 688 689 return 0; 690 } 691 692 /* set codec sysclk */ 693 static int sgtl5000_set_dai_sysclk(struct snd_soc_dai *codec_dai, 694 int clk_id, unsigned int freq, int dir) 695 { 696 struct snd_soc_component *component = codec_dai->component; 697 struct sgtl5000_priv *sgtl5000 = snd_soc_component_get_drvdata(component); 698 699 switch (clk_id) { 700 case SGTL5000_SYSCLK: 701 sgtl5000->sysclk = freq; 702 break; 703 default: 704 return -EINVAL; 705 } 706 707 return 0; 708 } 709 710 /* 711 * set clock according to i2s frame clock, 712 * sgtl5000 provides 2 clock sources: 713 * 1. sys_mclk: sample freq can only be configured to 714 * 1/256, 1/384, 1/512 of sys_mclk. 715 * 2. pll: can derive any audio clocks. 716 * 717 * clock setting rules: 718 * 1. in slave mode, only sys_mclk can be used 719 * 2. as constraint by sys_mclk, sample freq should be set to 32 kHz, 44.1 kHz 720 * and above. 721 * 3. usage of sys_mclk is preferred over pll to save power. 722 */ 723 static int sgtl5000_set_clock(struct snd_soc_component *component, int frame_rate) 724 { 725 struct sgtl5000_priv *sgtl5000 = snd_soc_component_get_drvdata(component); 726 int clk_ctl = 0; 727 int sys_fs; /* sample freq */ 728 729 /* 730 * sample freq should be divided by frame clock, 731 * if frame clock is lower than 44.1 kHz, sample freq should be set to 732 * 32 kHz or 44.1 kHz. 733 */ 734 switch (frame_rate) { 735 case 8000: 736 case 16000: 737 sys_fs = 32000; 738 break; 739 case 11025: 740 case 22050: 741 sys_fs = 44100; 742 break; 743 default: 744 sys_fs = frame_rate; 745 break; 746 } 747 748 /* set divided factor of frame clock */ 749 switch (sys_fs / frame_rate) { 750 case 4: 751 clk_ctl |= SGTL5000_RATE_MODE_DIV_4 << SGTL5000_RATE_MODE_SHIFT; 752 break; 753 case 2: 754 clk_ctl |= SGTL5000_RATE_MODE_DIV_2 << SGTL5000_RATE_MODE_SHIFT; 755 break; 756 case 1: 757 clk_ctl |= SGTL5000_RATE_MODE_DIV_1 << SGTL5000_RATE_MODE_SHIFT; 758 break; 759 default: 760 return -EINVAL; 761 } 762 763 /* set the sys_fs according to frame rate */ 764 switch (sys_fs) { 765 case 32000: 766 clk_ctl |= SGTL5000_SYS_FS_32k << SGTL5000_SYS_FS_SHIFT; 767 break; 768 case 44100: 769 clk_ctl |= SGTL5000_SYS_FS_44_1k << SGTL5000_SYS_FS_SHIFT; 770 break; 771 case 48000: 772 clk_ctl |= SGTL5000_SYS_FS_48k << SGTL5000_SYS_FS_SHIFT; 773 break; 774 case 96000: 775 clk_ctl |= SGTL5000_SYS_FS_96k << SGTL5000_SYS_FS_SHIFT; 776 break; 777 default: 778 dev_err(component->dev, "frame rate %d not supported\n", 779 frame_rate); 780 return -EINVAL; 781 } 782 783 /* 784 * calculate the divider of mclk/sample_freq, 785 * factor of freq = 96 kHz can only be 256, since mclk is in the range 786 * of 8 MHz - 27 MHz 787 */ 788 switch (sgtl5000->sysclk / frame_rate) { 789 case 256: 790 clk_ctl |= SGTL5000_MCLK_FREQ_256FS << 791 SGTL5000_MCLK_FREQ_SHIFT; 792 break; 793 case 384: 794 clk_ctl |= SGTL5000_MCLK_FREQ_384FS << 795 SGTL5000_MCLK_FREQ_SHIFT; 796 break; 797 case 512: 798 clk_ctl |= SGTL5000_MCLK_FREQ_512FS << 799 SGTL5000_MCLK_FREQ_SHIFT; 800 break; 801 default: 802 /* if mclk does not satisfy the divider, use pll */ 803 if (sgtl5000->master) { 804 clk_ctl |= SGTL5000_MCLK_FREQ_PLL << 805 SGTL5000_MCLK_FREQ_SHIFT; 806 } else { 807 dev_err(component->dev, 808 "PLL not supported in slave mode\n"); 809 dev_err(component->dev, "%d ratio is not supported. " 810 "SYS_MCLK needs to be 256, 384 or 512 * fs\n", 811 sgtl5000->sysclk / frame_rate); 812 return -EINVAL; 813 } 814 } 815 816 /* if using pll, please check manual 6.4.2 for detail */ 817 if ((clk_ctl & SGTL5000_MCLK_FREQ_MASK) == SGTL5000_MCLK_FREQ_PLL) { 818 u64 out, t; 819 int div2; 820 int pll_ctl; 821 unsigned int in, int_div, frac_div; 822 823 if (sgtl5000->sysclk > 17000000) { 824 div2 = 1; 825 in = sgtl5000->sysclk / 2; 826 } else { 827 div2 = 0; 828 in = sgtl5000->sysclk; 829 } 830 if (sys_fs == 44100) 831 out = 180633600; 832 else 833 out = 196608000; 834 t = do_div(out, in); 835 int_div = out; 836 t *= 2048; 837 do_div(t, in); 838 frac_div = t; 839 pll_ctl = int_div << SGTL5000_PLL_INT_DIV_SHIFT | 840 frac_div << SGTL5000_PLL_FRAC_DIV_SHIFT; 841 842 snd_soc_component_write(component, SGTL5000_CHIP_PLL_CTRL, pll_ctl); 843 if (div2) 844 snd_soc_component_update_bits(component, 845 SGTL5000_CHIP_CLK_TOP_CTRL, 846 SGTL5000_INPUT_FREQ_DIV2, 847 SGTL5000_INPUT_FREQ_DIV2); 848 else 849 snd_soc_component_update_bits(component, 850 SGTL5000_CHIP_CLK_TOP_CTRL, 851 SGTL5000_INPUT_FREQ_DIV2, 852 0); 853 854 /* power up pll */ 855 snd_soc_component_update_bits(component, SGTL5000_CHIP_ANA_POWER, 856 SGTL5000_PLL_POWERUP | SGTL5000_VCOAMP_POWERUP, 857 SGTL5000_PLL_POWERUP | SGTL5000_VCOAMP_POWERUP); 858 859 /* if using pll, clk_ctrl must be set after pll power up */ 860 snd_soc_component_write(component, SGTL5000_CHIP_CLK_CTRL, clk_ctl); 861 } else { 862 /* otherwise, clk_ctrl must be set before pll power down */ 863 snd_soc_component_write(component, SGTL5000_CHIP_CLK_CTRL, clk_ctl); 864 865 /* power down pll */ 866 snd_soc_component_update_bits(component, SGTL5000_CHIP_ANA_POWER, 867 SGTL5000_PLL_POWERUP | SGTL5000_VCOAMP_POWERUP, 868 0); 869 } 870 871 return 0; 872 } 873 874 /* 875 * Set PCM DAI bit size and sample rate. 876 * input: params_rate, params_fmt 877 */ 878 static int sgtl5000_pcm_hw_params(struct snd_pcm_substream *substream, 879 struct snd_pcm_hw_params *params, 880 struct snd_soc_dai *dai) 881 { 882 struct snd_soc_component *component = dai->component; 883 struct sgtl5000_priv *sgtl5000 = snd_soc_component_get_drvdata(component); 884 int channels = params_channels(params); 885 int i2s_ctl = 0; 886 int stereo; 887 int ret; 888 889 /* sysclk should already set */ 890 if (!sgtl5000->sysclk) { 891 dev_err(component->dev, "%s: set sysclk first!\n", __func__); 892 return -EFAULT; 893 } 894 895 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 896 stereo = SGTL5000_DAC_STEREO; 897 else 898 stereo = SGTL5000_ADC_STEREO; 899 900 /* set mono to save power */ 901 snd_soc_component_update_bits(component, SGTL5000_CHIP_ANA_POWER, stereo, 902 channels == 1 ? 0 : stereo); 903 904 /* set codec clock base on lrclk */ 905 ret = sgtl5000_set_clock(component, params_rate(params)); 906 if (ret) 907 return ret; 908 909 /* set i2s data format */ 910 switch (params_width(params)) { 911 case 16: 912 if (sgtl5000->fmt == SND_SOC_DAIFMT_RIGHT_J) 913 return -EINVAL; 914 i2s_ctl |= SGTL5000_I2S_DLEN_16 << SGTL5000_I2S_DLEN_SHIFT; 915 i2s_ctl |= SGTL5000_I2S_SCLKFREQ_32FS << 916 SGTL5000_I2S_SCLKFREQ_SHIFT; 917 break; 918 case 20: 919 i2s_ctl |= SGTL5000_I2S_DLEN_20 << SGTL5000_I2S_DLEN_SHIFT; 920 i2s_ctl |= SGTL5000_I2S_SCLKFREQ_64FS << 921 SGTL5000_I2S_SCLKFREQ_SHIFT; 922 break; 923 case 24: 924 i2s_ctl |= SGTL5000_I2S_DLEN_24 << SGTL5000_I2S_DLEN_SHIFT; 925 i2s_ctl |= SGTL5000_I2S_SCLKFREQ_64FS << 926 SGTL5000_I2S_SCLKFREQ_SHIFT; 927 break; 928 case 32: 929 if (sgtl5000->fmt == SND_SOC_DAIFMT_RIGHT_J) 930 return -EINVAL; 931 i2s_ctl |= SGTL5000_I2S_DLEN_32 << SGTL5000_I2S_DLEN_SHIFT; 932 i2s_ctl |= SGTL5000_I2S_SCLKFREQ_64FS << 933 SGTL5000_I2S_SCLKFREQ_SHIFT; 934 break; 935 default: 936 return -EINVAL; 937 } 938 939 snd_soc_component_update_bits(component, SGTL5000_CHIP_I2S_CTRL, 940 SGTL5000_I2S_DLEN_MASK | SGTL5000_I2S_SCLKFREQ_MASK, 941 i2s_ctl); 942 943 return 0; 944 } 945 946 /* 947 * set dac bias 948 * common state changes: 949 * startup: 950 * off --> standby --> prepare --> on 951 * standby --> prepare --> on 952 * 953 * stop: 954 * on --> prepare --> standby 955 */ 956 static int sgtl5000_set_bias_level(struct snd_soc_component *component, 957 enum snd_soc_bias_level level) 958 { 959 struct sgtl5000_priv *sgtl = snd_soc_component_get_drvdata(component); 960 int ret; 961 962 switch (level) { 963 case SND_SOC_BIAS_ON: 964 case SND_SOC_BIAS_PREPARE: 965 case SND_SOC_BIAS_STANDBY: 966 regcache_cache_only(sgtl->regmap, false); 967 ret = regcache_sync(sgtl->regmap); 968 if (ret) { 969 regcache_cache_only(sgtl->regmap, true); 970 return ret; 971 } 972 973 snd_soc_component_update_bits(component, SGTL5000_CHIP_ANA_POWER, 974 SGTL5000_REFTOP_POWERUP, 975 SGTL5000_REFTOP_POWERUP); 976 break; 977 case SND_SOC_BIAS_OFF: 978 regcache_cache_only(sgtl->regmap, true); 979 snd_soc_component_update_bits(component, SGTL5000_CHIP_ANA_POWER, 980 SGTL5000_REFTOP_POWERUP, 0); 981 break; 982 } 983 984 return 0; 985 } 986 987 #define SGTL5000_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ 988 SNDRV_PCM_FMTBIT_S20_3LE |\ 989 SNDRV_PCM_FMTBIT_S24_LE |\ 990 SNDRV_PCM_FMTBIT_S32_LE) 991 992 static const struct snd_soc_dai_ops sgtl5000_ops = { 993 .hw_params = sgtl5000_pcm_hw_params, 994 .digital_mute = sgtl5000_digital_mute, 995 .set_fmt = sgtl5000_set_dai_fmt, 996 .set_sysclk = sgtl5000_set_dai_sysclk, 997 }; 998 999 static struct snd_soc_dai_driver sgtl5000_dai = { 1000 .name = "sgtl5000", 1001 .playback = { 1002 .stream_name = "Playback", 1003 .channels_min = 1, 1004 .channels_max = 2, 1005 /* 1006 * only support 8~48K + 96K, 1007 * TODO modify hw_param to support more 1008 */ 1009 .rates = SNDRV_PCM_RATE_8000_48000 | SNDRV_PCM_RATE_96000, 1010 .formats = SGTL5000_FORMATS, 1011 }, 1012 .capture = { 1013 .stream_name = "Capture", 1014 .channels_min = 1, 1015 .channels_max = 2, 1016 .rates = SNDRV_PCM_RATE_8000_48000 | SNDRV_PCM_RATE_96000, 1017 .formats = SGTL5000_FORMATS, 1018 }, 1019 .ops = &sgtl5000_ops, 1020 .symmetric_rates = 1, 1021 }; 1022 1023 static bool sgtl5000_volatile(struct device *dev, unsigned int reg) 1024 { 1025 switch (reg) { 1026 case SGTL5000_CHIP_ID: 1027 case SGTL5000_CHIP_ADCDAC_CTRL: 1028 case SGTL5000_CHIP_ANA_STATUS: 1029 return true; 1030 } 1031 1032 return false; 1033 } 1034 1035 static bool sgtl5000_readable(struct device *dev, unsigned int reg) 1036 { 1037 switch (reg) { 1038 case SGTL5000_CHIP_ID: 1039 case SGTL5000_CHIP_DIG_POWER: 1040 case SGTL5000_CHIP_CLK_CTRL: 1041 case SGTL5000_CHIP_I2S_CTRL: 1042 case SGTL5000_CHIP_SSS_CTRL: 1043 case SGTL5000_CHIP_ADCDAC_CTRL: 1044 case SGTL5000_CHIP_DAC_VOL: 1045 case SGTL5000_CHIP_PAD_STRENGTH: 1046 case SGTL5000_CHIP_ANA_ADC_CTRL: 1047 case SGTL5000_CHIP_ANA_HP_CTRL: 1048 case SGTL5000_CHIP_ANA_CTRL: 1049 case SGTL5000_CHIP_LINREG_CTRL: 1050 case SGTL5000_CHIP_REF_CTRL: 1051 case SGTL5000_CHIP_MIC_CTRL: 1052 case SGTL5000_CHIP_LINE_OUT_CTRL: 1053 case SGTL5000_CHIP_LINE_OUT_VOL: 1054 case SGTL5000_CHIP_ANA_POWER: 1055 case SGTL5000_CHIP_PLL_CTRL: 1056 case SGTL5000_CHIP_CLK_TOP_CTRL: 1057 case SGTL5000_CHIP_ANA_STATUS: 1058 case SGTL5000_CHIP_SHORT_CTRL: 1059 case SGTL5000_CHIP_ANA_TEST2: 1060 case SGTL5000_DAP_CTRL: 1061 case SGTL5000_DAP_PEQ: 1062 case SGTL5000_DAP_BASS_ENHANCE: 1063 case SGTL5000_DAP_BASS_ENHANCE_CTRL: 1064 case SGTL5000_DAP_AUDIO_EQ: 1065 case SGTL5000_DAP_SURROUND: 1066 case SGTL5000_DAP_FLT_COEF_ACCESS: 1067 case SGTL5000_DAP_COEF_WR_B0_MSB: 1068 case SGTL5000_DAP_COEF_WR_B0_LSB: 1069 case SGTL5000_DAP_EQ_BASS_BAND0: 1070 case SGTL5000_DAP_EQ_BASS_BAND1: 1071 case SGTL5000_DAP_EQ_BASS_BAND2: 1072 case SGTL5000_DAP_EQ_BASS_BAND3: 1073 case SGTL5000_DAP_EQ_BASS_BAND4: 1074 case SGTL5000_DAP_MAIN_CHAN: 1075 case SGTL5000_DAP_MIX_CHAN: 1076 case SGTL5000_DAP_AVC_CTRL: 1077 case SGTL5000_DAP_AVC_THRESHOLD: 1078 case SGTL5000_DAP_AVC_ATTACK: 1079 case SGTL5000_DAP_AVC_DECAY: 1080 case SGTL5000_DAP_COEF_WR_B1_MSB: 1081 case SGTL5000_DAP_COEF_WR_B1_LSB: 1082 case SGTL5000_DAP_COEF_WR_B2_MSB: 1083 case SGTL5000_DAP_COEF_WR_B2_LSB: 1084 case SGTL5000_DAP_COEF_WR_A1_MSB: 1085 case SGTL5000_DAP_COEF_WR_A1_LSB: 1086 case SGTL5000_DAP_COEF_WR_A2_MSB: 1087 case SGTL5000_DAP_COEF_WR_A2_LSB: 1088 return true; 1089 1090 default: 1091 return false; 1092 } 1093 } 1094 1095 /* 1096 * This precalculated table contains all (vag_val * 100 / lo_calcntrl) results 1097 * to select an appropriate lo_vol_* in SGTL5000_CHIP_LINE_OUT_VOL 1098 * The calculatation was done for all possible register values which 1099 * is the array index and the following formula: 10^((idx−15)/40) * 100 1100 */ 1101 static const u8 vol_quot_table[] = { 1102 42, 45, 47, 50, 53, 56, 60, 63, 1103 67, 71, 75, 79, 84, 89, 94, 100, 1104 106, 112, 119, 126, 133, 141, 150, 158, 1105 168, 178, 188, 200, 211, 224, 237, 251 1106 }; 1107 1108 /* 1109 * sgtl5000 has 3 internal power supplies: 1110 * 1. VAG, normally set to vdda/2 1111 * 2. charge pump, set to different value 1112 * according to voltage of vdda and vddio 1113 * 3. line out VAG, normally set to vddio/2 1114 * 1115 * and should be set according to: 1116 * 1. vddd provided by external or not 1117 * 2. vdda and vddio voltage value. > 3.1v or not 1118 */ 1119 static int sgtl5000_set_power_regs(struct snd_soc_component *component) 1120 { 1121 int vddd; 1122 int vdda; 1123 int vddio; 1124 u16 ana_pwr; 1125 u16 lreg_ctrl; 1126 int vag; 1127 int lo_vag; 1128 int vol_quot; 1129 int lo_vol; 1130 size_t i; 1131 struct sgtl5000_priv *sgtl5000 = snd_soc_component_get_drvdata(component); 1132 1133 vdda = regulator_get_voltage(sgtl5000->supplies[VDDA].consumer); 1134 vddio = regulator_get_voltage(sgtl5000->supplies[VDDIO].consumer); 1135 vddd = (sgtl5000->num_supplies > VDDD) 1136 ? regulator_get_voltage(sgtl5000->supplies[VDDD].consumer) 1137 : LDO_VOLTAGE; 1138 1139 vdda = vdda / 1000; 1140 vddio = vddio / 1000; 1141 vddd = vddd / 1000; 1142 1143 if (vdda <= 0 || vddio <= 0 || vddd < 0) { 1144 dev_err(component->dev, "regulator voltage not set correctly\n"); 1145 1146 return -EINVAL; 1147 } 1148 1149 /* according to datasheet, maximum voltage of supplies */ 1150 if (vdda > 3600 || vddio > 3600 || vddd > 1980) { 1151 dev_err(component->dev, 1152 "exceed max voltage vdda %dmV vddio %dmV vddd %dmV\n", 1153 vdda, vddio, vddd); 1154 1155 return -EINVAL; 1156 } 1157 1158 /* reset value */ 1159 ana_pwr = snd_soc_component_read32(component, SGTL5000_CHIP_ANA_POWER); 1160 ana_pwr |= SGTL5000_DAC_STEREO | 1161 SGTL5000_ADC_STEREO | 1162 SGTL5000_REFTOP_POWERUP; 1163 lreg_ctrl = snd_soc_component_read32(component, SGTL5000_CHIP_LINREG_CTRL); 1164 1165 if (vddio < 3100 && vdda < 3100) { 1166 /* enable internal oscillator used for charge pump */ 1167 snd_soc_component_update_bits(component, SGTL5000_CHIP_CLK_TOP_CTRL, 1168 SGTL5000_INT_OSC_EN, 1169 SGTL5000_INT_OSC_EN); 1170 /* Enable VDDC charge pump */ 1171 ana_pwr |= SGTL5000_VDDC_CHRGPMP_POWERUP; 1172 } else if (vddio >= 3100 && vdda >= 3100) { 1173 ana_pwr &= ~SGTL5000_VDDC_CHRGPMP_POWERUP; 1174 /* VDDC use VDDIO rail */ 1175 lreg_ctrl |= SGTL5000_VDDC_ASSN_OVRD; 1176 lreg_ctrl |= SGTL5000_VDDC_MAN_ASSN_VDDIO << 1177 SGTL5000_VDDC_MAN_ASSN_SHIFT; 1178 } 1179 1180 snd_soc_component_write(component, SGTL5000_CHIP_LINREG_CTRL, lreg_ctrl); 1181 1182 snd_soc_component_write(component, SGTL5000_CHIP_ANA_POWER, ana_pwr); 1183 1184 /* 1185 * set ADC/DAC VAG to vdda / 2, 1186 * should stay in range (0.8v, 1.575v) 1187 */ 1188 vag = vdda / 2; 1189 if (vag <= SGTL5000_ANA_GND_BASE) 1190 vag = 0; 1191 else if (vag >= SGTL5000_ANA_GND_BASE + SGTL5000_ANA_GND_STP * 1192 (SGTL5000_ANA_GND_MASK >> SGTL5000_ANA_GND_SHIFT)) 1193 vag = SGTL5000_ANA_GND_MASK >> SGTL5000_ANA_GND_SHIFT; 1194 else 1195 vag = (vag - SGTL5000_ANA_GND_BASE) / SGTL5000_ANA_GND_STP; 1196 1197 snd_soc_component_update_bits(component, SGTL5000_CHIP_REF_CTRL, 1198 SGTL5000_ANA_GND_MASK, vag << SGTL5000_ANA_GND_SHIFT); 1199 1200 /* set line out VAG to vddio / 2, in range (0.8v, 1.675v) */ 1201 lo_vag = vddio / 2; 1202 if (lo_vag <= SGTL5000_LINE_OUT_GND_BASE) 1203 lo_vag = 0; 1204 else if (lo_vag >= SGTL5000_LINE_OUT_GND_BASE + 1205 SGTL5000_LINE_OUT_GND_STP * SGTL5000_LINE_OUT_GND_MAX) 1206 lo_vag = SGTL5000_LINE_OUT_GND_MAX; 1207 else 1208 lo_vag = (lo_vag - SGTL5000_LINE_OUT_GND_BASE) / 1209 SGTL5000_LINE_OUT_GND_STP; 1210 1211 snd_soc_component_update_bits(component, SGTL5000_CHIP_LINE_OUT_CTRL, 1212 SGTL5000_LINE_OUT_CURRENT_MASK | 1213 SGTL5000_LINE_OUT_GND_MASK, 1214 lo_vag << SGTL5000_LINE_OUT_GND_SHIFT | 1215 SGTL5000_LINE_OUT_CURRENT_360u << 1216 SGTL5000_LINE_OUT_CURRENT_SHIFT); 1217 1218 /* 1219 * Set lineout output level in range (0..31) 1220 * the same value is used for right and left channel 1221 * 1222 * Searching for a suitable index solving this formula: 1223 * idx = 40 * log10(vag_val / lo_cagcntrl) + 15 1224 */ 1225 vol_quot = (vag * 100) / lo_vag; 1226 lo_vol = 0; 1227 for (i = 0; i < ARRAY_SIZE(vol_quot_table); i++) { 1228 if (vol_quot >= vol_quot_table[i]) 1229 lo_vol = i; 1230 else 1231 break; 1232 } 1233 1234 snd_soc_component_update_bits(component, SGTL5000_CHIP_LINE_OUT_VOL, 1235 SGTL5000_LINE_OUT_VOL_RIGHT_MASK | 1236 SGTL5000_LINE_OUT_VOL_LEFT_MASK, 1237 lo_vol << SGTL5000_LINE_OUT_VOL_RIGHT_SHIFT | 1238 lo_vol << SGTL5000_LINE_OUT_VOL_LEFT_SHIFT); 1239 1240 return 0; 1241 } 1242 1243 static int sgtl5000_enable_regulators(struct i2c_client *client) 1244 { 1245 int ret; 1246 int i; 1247 int external_vddd = 0; 1248 struct regulator *vddd; 1249 struct sgtl5000_priv *sgtl5000 = i2c_get_clientdata(client); 1250 1251 for (i = 0; i < ARRAY_SIZE(sgtl5000->supplies); i++) 1252 sgtl5000->supplies[i].supply = supply_names[i]; 1253 1254 vddd = regulator_get_optional(&client->dev, "VDDD"); 1255 if (IS_ERR(vddd)) { 1256 /* See if it's just not registered yet */ 1257 if (PTR_ERR(vddd) == -EPROBE_DEFER) 1258 return -EPROBE_DEFER; 1259 } else { 1260 external_vddd = 1; 1261 regulator_put(vddd); 1262 } 1263 1264 sgtl5000->num_supplies = ARRAY_SIZE(sgtl5000->supplies) 1265 - 1 + external_vddd; 1266 ret = regulator_bulk_get(&client->dev, sgtl5000->num_supplies, 1267 sgtl5000->supplies); 1268 if (ret) 1269 return ret; 1270 1271 ret = regulator_bulk_enable(sgtl5000->num_supplies, 1272 sgtl5000->supplies); 1273 if (!ret) 1274 usleep_range(10, 20); 1275 else 1276 regulator_bulk_free(sgtl5000->num_supplies, 1277 sgtl5000->supplies); 1278 1279 return ret; 1280 } 1281 1282 static int sgtl5000_probe(struct snd_soc_component *component) 1283 { 1284 int ret; 1285 u16 reg; 1286 struct sgtl5000_priv *sgtl5000 = snd_soc_component_get_drvdata(component); 1287 1288 /* power up sgtl5000 */ 1289 ret = sgtl5000_set_power_regs(component); 1290 if (ret) 1291 goto err; 1292 1293 /* enable small pop, introduce 400ms delay in turning off */ 1294 snd_soc_component_update_bits(component, SGTL5000_CHIP_REF_CTRL, 1295 SGTL5000_SMALL_POP, 1); 1296 1297 /* disable short cut detector */ 1298 snd_soc_component_write(component, SGTL5000_CHIP_SHORT_CTRL, 0); 1299 1300 snd_soc_component_write(component, SGTL5000_CHIP_DIG_POWER, 1301 SGTL5000_ADC_EN | SGTL5000_DAC_EN); 1302 1303 /* enable dac volume ramp by default */ 1304 snd_soc_component_write(component, SGTL5000_CHIP_ADCDAC_CTRL, 1305 SGTL5000_DAC_VOL_RAMP_EN | 1306 SGTL5000_DAC_MUTE_RIGHT | 1307 SGTL5000_DAC_MUTE_LEFT); 1308 1309 reg = ((sgtl5000->lrclk_strength) << SGTL5000_PAD_I2S_LRCLK_SHIFT | 0x5f); 1310 snd_soc_component_write(component, SGTL5000_CHIP_PAD_STRENGTH, reg); 1311 1312 snd_soc_component_write(component, SGTL5000_CHIP_ANA_CTRL, 1313 SGTL5000_HP_ZCD_EN | 1314 SGTL5000_ADC_ZCD_EN); 1315 1316 snd_soc_component_update_bits(component, SGTL5000_CHIP_MIC_CTRL, 1317 SGTL5000_BIAS_R_MASK, 1318 sgtl5000->micbias_resistor << SGTL5000_BIAS_R_SHIFT); 1319 1320 snd_soc_component_update_bits(component, SGTL5000_CHIP_MIC_CTRL, 1321 SGTL5000_BIAS_VOLT_MASK, 1322 sgtl5000->micbias_voltage << SGTL5000_BIAS_VOLT_SHIFT); 1323 /* 1324 * enable DAP Graphic EQ 1325 * TODO: 1326 * Add control for changing between PEQ/Tone Control/GEQ 1327 */ 1328 snd_soc_component_write(component, SGTL5000_DAP_AUDIO_EQ, SGTL5000_DAP_SEL_GEQ); 1329 1330 /* Unmute DAC after start */ 1331 snd_soc_component_update_bits(component, SGTL5000_CHIP_ADCDAC_CTRL, 1332 SGTL5000_DAC_MUTE_LEFT | SGTL5000_DAC_MUTE_RIGHT, 0); 1333 1334 return 0; 1335 1336 err: 1337 return ret; 1338 } 1339 1340 static const struct snd_soc_component_driver sgtl5000_driver = { 1341 .probe = sgtl5000_probe, 1342 .set_bias_level = sgtl5000_set_bias_level, 1343 .controls = sgtl5000_snd_controls, 1344 .num_controls = ARRAY_SIZE(sgtl5000_snd_controls), 1345 .dapm_widgets = sgtl5000_dapm_widgets, 1346 .num_dapm_widgets = ARRAY_SIZE(sgtl5000_dapm_widgets), 1347 .dapm_routes = sgtl5000_dapm_routes, 1348 .num_dapm_routes = ARRAY_SIZE(sgtl5000_dapm_routes), 1349 .suspend_bias_off = 1, 1350 .idle_bias_on = 1, 1351 .use_pmdown_time = 1, 1352 .endianness = 1, 1353 .non_legacy_dai_naming = 1, 1354 }; 1355 1356 static const struct regmap_config sgtl5000_regmap = { 1357 .reg_bits = 16, 1358 .val_bits = 16, 1359 .reg_stride = 2, 1360 1361 .max_register = SGTL5000_MAX_REG_OFFSET, 1362 .volatile_reg = sgtl5000_volatile, 1363 .readable_reg = sgtl5000_readable, 1364 1365 .cache_type = REGCACHE_RBTREE, 1366 .reg_defaults = sgtl5000_reg_defaults, 1367 .num_reg_defaults = ARRAY_SIZE(sgtl5000_reg_defaults), 1368 }; 1369 1370 /* 1371 * Write all the default values from sgtl5000_reg_defaults[] array into the 1372 * sgtl5000 registers, to make sure we always start with the sane registers 1373 * values as stated in the datasheet. 1374 * 1375 * Since sgtl5000 does not have a reset line, nor a reset command in software, 1376 * we follow this approach to guarantee we always start from the default values 1377 * and avoid problems like, not being able to probe after an audio playback 1378 * followed by a system reset or a 'reboot' command in Linux 1379 */ 1380 static void sgtl5000_fill_defaults(struct i2c_client *client) 1381 { 1382 struct sgtl5000_priv *sgtl5000 = i2c_get_clientdata(client); 1383 int i, ret, val, index; 1384 1385 for (i = 0; i < ARRAY_SIZE(sgtl5000_reg_defaults); i++) { 1386 val = sgtl5000_reg_defaults[i].def; 1387 index = sgtl5000_reg_defaults[i].reg; 1388 ret = regmap_write(sgtl5000->regmap, index, val); 1389 if (ret) 1390 dev_err(&client->dev, 1391 "%s: error %d setting reg 0x%02x to 0x%04x\n", 1392 __func__, ret, index, val); 1393 } 1394 } 1395 1396 static int sgtl5000_i2c_probe(struct i2c_client *client, 1397 const struct i2c_device_id *id) 1398 { 1399 struct sgtl5000_priv *sgtl5000; 1400 int ret, reg, rev; 1401 struct device_node *np = client->dev.of_node; 1402 u32 value; 1403 u16 ana_pwr; 1404 1405 sgtl5000 = devm_kzalloc(&client->dev, sizeof(*sgtl5000), GFP_KERNEL); 1406 if (!sgtl5000) 1407 return -ENOMEM; 1408 1409 i2c_set_clientdata(client, sgtl5000); 1410 1411 ret = sgtl5000_enable_regulators(client); 1412 if (ret) 1413 return ret; 1414 1415 sgtl5000->regmap = devm_regmap_init_i2c(client, &sgtl5000_regmap); 1416 if (IS_ERR(sgtl5000->regmap)) { 1417 ret = PTR_ERR(sgtl5000->regmap); 1418 dev_err(&client->dev, "Failed to allocate regmap: %d\n", ret); 1419 goto disable_regs; 1420 } 1421 1422 sgtl5000->mclk = devm_clk_get(&client->dev, NULL); 1423 if (IS_ERR(sgtl5000->mclk)) { 1424 ret = PTR_ERR(sgtl5000->mclk); 1425 /* Defer the probe to see if the clk will be provided later */ 1426 if (ret == -ENOENT) 1427 ret = -EPROBE_DEFER; 1428 1429 if (ret != -EPROBE_DEFER) 1430 dev_err(&client->dev, "Failed to get mclock: %d\n", 1431 ret); 1432 goto disable_regs; 1433 } 1434 1435 ret = clk_prepare_enable(sgtl5000->mclk); 1436 if (ret) { 1437 dev_err(&client->dev, "Error enabling clock %d\n", ret); 1438 goto disable_regs; 1439 } 1440 1441 /* Need 8 clocks before I2C accesses */ 1442 udelay(1); 1443 1444 /* read chip information */ 1445 ret = regmap_read(sgtl5000->regmap, SGTL5000_CHIP_ID, ®); 1446 if (ret) { 1447 dev_err(&client->dev, "Error reading chip id %d\n", ret); 1448 goto disable_clk; 1449 } 1450 1451 if (((reg & SGTL5000_PARTID_MASK) >> SGTL5000_PARTID_SHIFT) != 1452 SGTL5000_PARTID_PART_ID) { 1453 dev_err(&client->dev, 1454 "Device with ID register %x is not a sgtl5000\n", reg); 1455 ret = -ENODEV; 1456 goto disable_clk; 1457 } 1458 1459 rev = (reg & SGTL5000_REVID_MASK) >> SGTL5000_REVID_SHIFT; 1460 dev_info(&client->dev, "sgtl5000 revision 0x%x\n", rev); 1461 sgtl5000->revision = rev; 1462 1463 /* reconfigure the clocks in case we're using the PLL */ 1464 ret = regmap_write(sgtl5000->regmap, 1465 SGTL5000_CHIP_CLK_CTRL, 1466 SGTL5000_CHIP_CLK_CTRL_DEFAULT); 1467 if (ret) 1468 dev_err(&client->dev, 1469 "Error %d initializing CHIP_CLK_CTRL\n", ret); 1470 1471 /* Follow section 2.2.1.1 of AN3663 */ 1472 ana_pwr = SGTL5000_ANA_POWER_DEFAULT; 1473 if (sgtl5000->num_supplies <= VDDD) { 1474 /* internal VDDD at 1.2V */ 1475 ret = regmap_update_bits(sgtl5000->regmap, 1476 SGTL5000_CHIP_LINREG_CTRL, 1477 SGTL5000_LINREG_VDDD_MASK, 1478 LINREG_VDDD); 1479 if (ret) 1480 dev_err(&client->dev, 1481 "Error %d setting LINREG_VDDD\n", ret); 1482 1483 ana_pwr |= SGTL5000_LINEREG_D_POWERUP; 1484 dev_info(&client->dev, 1485 "Using internal LDO instead of VDDD: check ER1 erratum\n"); 1486 } else { 1487 /* using external LDO for VDDD 1488 * Clear startup powerup and simple powerup 1489 * bits to save power 1490 */ 1491 ana_pwr &= ~(SGTL5000_STARTUP_POWERUP 1492 | SGTL5000_LINREG_SIMPLE_POWERUP); 1493 dev_dbg(&client->dev, "Using external VDDD\n"); 1494 } 1495 ret = regmap_write(sgtl5000->regmap, SGTL5000_CHIP_ANA_POWER, ana_pwr); 1496 if (ret) 1497 dev_err(&client->dev, 1498 "Error %d setting CHIP_ANA_POWER to %04x\n", 1499 ret, ana_pwr); 1500 1501 if (np) { 1502 if (!of_property_read_u32(np, 1503 "micbias-resistor-k-ohms", &value)) { 1504 switch (value) { 1505 case SGTL5000_MICBIAS_OFF: 1506 sgtl5000->micbias_resistor = 0; 1507 break; 1508 case SGTL5000_MICBIAS_2K: 1509 sgtl5000->micbias_resistor = 1; 1510 break; 1511 case SGTL5000_MICBIAS_4K: 1512 sgtl5000->micbias_resistor = 2; 1513 break; 1514 case SGTL5000_MICBIAS_8K: 1515 sgtl5000->micbias_resistor = 3; 1516 break; 1517 default: 1518 sgtl5000->micbias_resistor = 2; 1519 dev_err(&client->dev, 1520 "Unsuitable MicBias resistor\n"); 1521 } 1522 } else { 1523 /* default is 4Kohms */ 1524 sgtl5000->micbias_resistor = 2; 1525 } 1526 if (!of_property_read_u32(np, 1527 "micbias-voltage-m-volts", &value)) { 1528 /* 1250mV => 0 */ 1529 /* steps of 250mV */ 1530 if ((value >= 1250) && (value <= 3000)) 1531 sgtl5000->micbias_voltage = (value / 250) - 5; 1532 else { 1533 sgtl5000->micbias_voltage = 0; 1534 dev_err(&client->dev, 1535 "Unsuitable MicBias voltage\n"); 1536 } 1537 } else { 1538 sgtl5000->micbias_voltage = 0; 1539 } 1540 } 1541 1542 sgtl5000->lrclk_strength = I2S_LRCLK_STRENGTH_LOW; 1543 if (!of_property_read_u32(np, "lrclk-strength", &value)) { 1544 if (value > I2S_LRCLK_STRENGTH_HIGH) 1545 value = I2S_LRCLK_STRENGTH_LOW; 1546 sgtl5000->lrclk_strength = value; 1547 } 1548 1549 /* Ensure sgtl5000 will start with sane register values */ 1550 sgtl5000_fill_defaults(client); 1551 1552 ret = devm_snd_soc_register_component(&client->dev, 1553 &sgtl5000_driver, &sgtl5000_dai, 1); 1554 if (ret) 1555 goto disable_clk; 1556 1557 return 0; 1558 1559 disable_clk: 1560 clk_disable_unprepare(sgtl5000->mclk); 1561 1562 disable_regs: 1563 regulator_bulk_disable(sgtl5000->num_supplies, sgtl5000->supplies); 1564 regulator_bulk_free(sgtl5000->num_supplies, sgtl5000->supplies); 1565 1566 return ret; 1567 } 1568 1569 static int sgtl5000_i2c_remove(struct i2c_client *client) 1570 { 1571 struct sgtl5000_priv *sgtl5000 = i2c_get_clientdata(client); 1572 1573 clk_disable_unprepare(sgtl5000->mclk); 1574 regulator_bulk_disable(sgtl5000->num_supplies, sgtl5000->supplies); 1575 regulator_bulk_free(sgtl5000->num_supplies, sgtl5000->supplies); 1576 1577 return 0; 1578 } 1579 1580 static const struct i2c_device_id sgtl5000_id[] = { 1581 {"sgtl5000", 0}, 1582 {}, 1583 }; 1584 1585 MODULE_DEVICE_TABLE(i2c, sgtl5000_id); 1586 1587 static const struct of_device_id sgtl5000_dt_ids[] = { 1588 { .compatible = "fsl,sgtl5000", }, 1589 { /* sentinel */ } 1590 }; 1591 MODULE_DEVICE_TABLE(of, sgtl5000_dt_ids); 1592 1593 static struct i2c_driver sgtl5000_i2c_driver = { 1594 .driver = { 1595 .name = "sgtl5000", 1596 .of_match_table = sgtl5000_dt_ids, 1597 }, 1598 .probe = sgtl5000_i2c_probe, 1599 .remove = sgtl5000_i2c_remove, 1600 .id_table = sgtl5000_id, 1601 }; 1602 1603 module_i2c_driver(sgtl5000_i2c_driver); 1604 1605 MODULE_DESCRIPTION("Freescale SGTL5000 ALSA SoC Codec Driver"); 1606 MODULE_AUTHOR("Zeng Zhaoming <zengzm.kernel@gmail.com>"); 1607 MODULE_LICENSE("GPL"); 1608