1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * rt715.c -- rt715 ALSA SoC audio driver 4 * 5 * Copyright(c) 2019 Realtek Semiconductor Corp. 6 * 7 * ALC715 ASoC Codec Driver based Intel Dummy SdW codec driver 8 * 9 */ 10 11 #include <linux/module.h> 12 #include <linux/kernel.h> 13 #include <linux/init.h> 14 #include <linux/delay.h> 15 #include <linux/i2c.h> 16 #include <linux/pm_runtime.h> 17 #include <linux/pm.h> 18 #include <linux/soundwire/sdw.h> 19 #include <linux/gpio.h> 20 #include <linux/regmap.h> 21 #include <linux/slab.h> 22 #include <linux/platform_device.h> 23 #include <linux/regulator/consumer.h> 24 #include <linux/gpio/consumer.h> 25 #include <linux/of.h> 26 #include <linux/of_gpio.h> 27 #include <linux/of_device.h> 28 #include <sound/core.h> 29 #include <sound/pcm.h> 30 #include <sound/pcm_params.h> 31 #include <sound/sdw.h> 32 #include <sound/soc.h> 33 #include <sound/soc-dapm.h> 34 #include <sound/initval.h> 35 #include <sound/tlv.h> 36 #include <sound/hda_verbs.h> 37 38 #include "rt715.h" 39 40 static int rt715_index_write(struct regmap *regmap, unsigned int reg, 41 unsigned int value) 42 { 43 int ret; 44 unsigned int addr = ((RT715_PRIV_INDEX_W_H) << 8) | reg; 45 46 ret = regmap_write(regmap, addr, value); 47 if (ret < 0) { 48 pr_err("Failed to set private value: %08x <= %04x %d\n", ret, 49 addr, value); 50 } 51 52 return ret; 53 } 54 55 static void rt715_get_gain(struct rt715_priv *rt715, unsigned int addr_h, 56 unsigned int addr_l, unsigned int val_h, 57 unsigned int *r_val, unsigned int *l_val) 58 { 59 int ret; 60 /* R Channel */ 61 *r_val = val_h << 8; 62 ret = regmap_read(rt715->regmap, addr_l, r_val); 63 if (ret < 0) 64 pr_err("Failed to get R channel gain.\n"); 65 66 /* L Channel */ 67 val_h |= 0x20; 68 *l_val = val_h << 8; 69 ret = regmap_read(rt715->regmap, addr_h, l_val); 70 if (ret < 0) 71 pr_err("Failed to get L channel gain.\n"); 72 } 73 74 /* For Verb-Set Amplifier Gain (Verb ID = 3h) */ 75 static int rt715_set_amp_gain_put(struct snd_kcontrol *kcontrol, 76 struct snd_ctl_elem_value *ucontrol) 77 { 78 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 79 struct snd_soc_dapm_context *dapm = 80 snd_soc_component_get_dapm(component); 81 struct soc_mixer_control *mc = 82 (struct soc_mixer_control *)kcontrol->private_value; 83 struct rt715_priv *rt715 = snd_soc_component_get_drvdata(component); 84 unsigned int addr_h, addr_l, val_h, val_ll, val_lr; 85 unsigned int read_ll, read_rl, i; 86 unsigned int k_vol_changed = 0; 87 88 for (i = 0; i < 2; i++) { 89 if (ucontrol->value.integer.value[i] != rt715->kctl_2ch_vol_ori[i]) { 90 k_vol_changed = 1; 91 break; 92 } 93 } 94 95 /* Can't use update bit function, so read the original value first */ 96 addr_h = mc->reg; 97 addr_l = mc->rreg; 98 99 if (mc->shift == RT715_DIR_OUT_SFT) /* output */ 100 val_h = 0x80; 101 else /* input */ 102 val_h = 0x0; 103 104 rt715_get_gain(rt715, addr_h, addr_l, val_h, &read_rl, &read_ll); 105 106 if (dapm->bias_level <= SND_SOC_BIAS_STANDBY) 107 regmap_write(rt715->regmap, 108 RT715_SET_AUDIO_POWER_STATE, AC_PWRST_D0); 109 110 /* L Channel */ 111 rt715->kctl_2ch_vol_ori[0] = ucontrol->value.integer.value[0]; 112 /* for gain */ 113 val_ll = ((ucontrol->value.integer.value[0]) & 0x7f); 114 if (val_ll > mc->max) 115 val_ll = mc->max; 116 /* keep mute status */ 117 val_ll |= read_ll & 0x80; 118 119 /* R Channel */ 120 rt715->kctl_2ch_vol_ori[1] = ucontrol->value.integer.value[1]; 121 /* for gain */ 122 val_lr = ((ucontrol->value.integer.value[1]) & 0x7f); 123 if (val_lr > mc->max) 124 val_lr = mc->max; 125 /* keep mute status */ 126 val_lr |= read_rl & 0x80; 127 128 for (i = 0; i < 3; i++) { /* retry 3 times at most */ 129 130 if (val_ll == val_lr) { 131 /* Set both L/R channels at the same time */ 132 val_h = (1 << mc->shift) | (3 << 4); 133 regmap_write(rt715->regmap, addr_h, 134 (val_h << 8) | val_ll); 135 regmap_write(rt715->regmap, addr_l, 136 (val_h << 8) | val_ll); 137 } else { 138 /* Lch*/ 139 val_h = (1 << mc->shift) | (1 << 5); 140 regmap_write(rt715->regmap, addr_h, 141 (val_h << 8) | val_ll); 142 /* Rch */ 143 val_h = (1 << mc->shift) | (1 << 4); 144 regmap_write(rt715->regmap, addr_l, 145 (val_h << 8) | val_lr); 146 } 147 /* check result */ 148 if (mc->shift == RT715_DIR_OUT_SFT) /* output */ 149 val_h = 0x80; 150 else /* input */ 151 val_h = 0x0; 152 153 rt715_get_gain(rt715, addr_h, addr_l, val_h, 154 &read_rl, &read_ll); 155 if (read_rl == val_lr && read_ll == val_ll) 156 break; 157 } 158 159 /* D0:power on state, D3: power saving mode */ 160 if (dapm->bias_level <= SND_SOC_BIAS_STANDBY) 161 regmap_write(rt715->regmap, 162 RT715_SET_AUDIO_POWER_STATE, AC_PWRST_D3); 163 return k_vol_changed; 164 } 165 166 static int rt715_set_amp_gain_get(struct snd_kcontrol *kcontrol, 167 struct snd_ctl_elem_value *ucontrol) 168 { 169 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 170 struct rt715_priv *rt715 = snd_soc_component_get_drvdata(component); 171 struct soc_mixer_control *mc = 172 (struct soc_mixer_control *)kcontrol->private_value; 173 unsigned int addr_h, addr_l, val_h; 174 unsigned int read_ll, read_rl; 175 176 addr_h = mc->reg; 177 addr_l = mc->rreg; 178 if (mc->shift == RT715_DIR_OUT_SFT) /* output */ 179 val_h = 0x80; 180 else /* input */ 181 val_h = 0x0; 182 183 rt715_get_gain(rt715, addr_h, addr_l, val_h, &read_rl, &read_ll); 184 185 if (mc->invert) { 186 /* for mute status */ 187 read_ll = !(read_ll & 0x80); 188 read_rl = !(read_rl & 0x80); 189 } else { 190 /* for gain */ 191 read_ll = read_ll & 0x7f; 192 read_rl = read_rl & 0x7f; 193 } 194 ucontrol->value.integer.value[0] = read_ll; 195 ucontrol->value.integer.value[1] = read_rl; 196 197 return 0; 198 } 199 200 static int rt715_set_main_switch_put(struct snd_kcontrol *kcontrol, 201 struct snd_ctl_elem_value *ucontrol) 202 { 203 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 204 struct snd_soc_dapm_context *dapm = 205 snd_soc_component_get_dapm(component); 206 struct rt715_priv *rt715 = snd_soc_component_get_drvdata(component); 207 static const unsigned int capture_reg_H[] = { 208 RT715_SET_GAIN_MIC_ADC_H, RT715_SET_GAIN_LINE_ADC_H, 209 RT715_SET_GAIN_MIX_ADC_H, RT715_SET_GAIN_MIX_ADC2_H }; 210 static const unsigned int capture_reg_L[] = { 211 RT715_SET_GAIN_MIC_ADC_L, RT715_SET_GAIN_LINE_ADC_L, 212 RT715_SET_GAIN_MIX_ADC_L, RT715_SET_GAIN_MIX_ADC2_L }; 213 unsigned int addr_h, addr_l, val_h = 0x0, val_ll, val_lr; 214 unsigned int k_shift = RT715_DIR_IN_SFT, k_changed = 0; 215 unsigned int read_ll, read_rl, i, j, loop_cnt = 4; 216 217 for (i = 0; i < 8; i++) { 218 if (ucontrol->value.integer.value[i] != rt715->kctl_8ch_switch_ori[i]) 219 k_changed = 1; 220 } 221 222 for (j = 0; j < loop_cnt; j++) { 223 /* Can't use update bit function, so read the original value first */ 224 addr_h = capture_reg_H[j]; 225 addr_l = capture_reg_L[j]; 226 rt715_get_gain(rt715, addr_h, addr_l, val_h, &read_rl, &read_ll); 227 228 if (dapm->bias_level <= SND_SOC_BIAS_STANDBY) 229 regmap_write(rt715->regmap, 230 RT715_SET_AUDIO_POWER_STATE, AC_PWRST_D0); 231 232 /* L Channel */ 233 /* for mute */ 234 rt715->kctl_8ch_switch_ori[j * 2] = 235 ucontrol->value.integer.value[j * 2]; 236 val_ll = (!ucontrol->value.integer.value[j * 2]) << 7; 237 /* keep gain */ 238 val_ll |= read_ll & 0x7f; 239 240 /* R Channel */ 241 /* for mute */ 242 rt715->kctl_8ch_switch_ori[j * 2 + 1] = 243 ucontrol->value.integer.value[j * 2 + 1]; 244 val_lr = (!ucontrol->value.integer.value[j * 2 + 1]) << 7; 245 /* keep gain */ 246 val_lr |= read_rl & 0x7f; 247 248 for (i = 0; i < 3; i++) { /* retry 3 times at most */ 249 250 if (val_ll == val_lr) { 251 /* Set both L/R channels at the same time */ 252 val_h = (1 << k_shift) | (3 << 4); 253 regmap_write(rt715->regmap, addr_h, 254 (val_h << 8) | val_ll); 255 regmap_write(rt715->regmap, addr_l, 256 (val_h << 8) | val_ll); 257 } else { 258 /* Lch*/ 259 val_h = (1 << k_shift) | (1 << 5); 260 regmap_write(rt715->regmap, addr_h, 261 (val_h << 8) | val_ll); 262 /* Rch */ 263 val_h = (1 << k_shift) | (1 << 4); 264 regmap_write(rt715->regmap, addr_l, 265 (val_h << 8) | val_lr); 266 } 267 val_h = 0x0; 268 rt715_get_gain(rt715, addr_h, addr_l, val_h, 269 &read_rl, &read_ll); 270 if (read_rl == val_lr && read_ll == val_ll) 271 break; 272 } 273 } 274 275 /* D0:power on state, D3: power saving mode */ 276 if (dapm->bias_level <= SND_SOC_BIAS_STANDBY) 277 regmap_write(rt715->regmap, 278 RT715_SET_AUDIO_POWER_STATE, AC_PWRST_D3); 279 return k_changed; 280 } 281 282 static int rt715_set_main_switch_get(struct snd_kcontrol *kcontrol, 283 struct snd_ctl_elem_value *ucontrol) 284 { 285 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 286 struct rt715_priv *rt715 = snd_soc_component_get_drvdata(component); 287 static const unsigned int capture_reg_H[] = { 288 RT715_SET_GAIN_MIC_ADC_H, RT715_SET_GAIN_LINE_ADC_H, 289 RT715_SET_GAIN_MIX_ADC_H, RT715_SET_GAIN_MIX_ADC2_H }; 290 static const unsigned int capture_reg_L[] = { 291 RT715_SET_GAIN_MIC_ADC_L, RT715_SET_GAIN_LINE_ADC_L, 292 RT715_SET_GAIN_MIX_ADC_L, RT715_SET_GAIN_MIX_ADC2_L }; 293 unsigned int addr_h, addr_l, val_h = 0x0, i, loop_cnt = 4; 294 unsigned int read_ll, read_rl; 295 296 for (i = 0; i < loop_cnt; i++) { 297 addr_h = capture_reg_H[i]; 298 addr_l = capture_reg_L[i]; 299 rt715_get_gain(rt715, addr_h, addr_l, val_h, &read_rl, &read_ll); 300 301 ucontrol->value.integer.value[i * 2] = !(read_ll & 0x80); 302 ucontrol->value.integer.value[i * 2 + 1] = !(read_rl & 0x80); 303 } 304 305 return 0; 306 } 307 308 static int rt715_set_main_vol_put(struct snd_kcontrol *kcontrol, 309 struct snd_ctl_elem_value *ucontrol) 310 { 311 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 312 struct snd_soc_dapm_context *dapm = 313 snd_soc_component_get_dapm(component); 314 struct rt715_priv *rt715 = snd_soc_component_get_drvdata(component); 315 static const unsigned int capture_reg_H[] = { 316 RT715_SET_GAIN_MIC_ADC_H, RT715_SET_GAIN_LINE_ADC_H, 317 RT715_SET_GAIN_MIX_ADC_H, RT715_SET_GAIN_MIX_ADC2_H }; 318 static const unsigned int capture_reg_L[] = { 319 RT715_SET_GAIN_MIC_ADC_L, RT715_SET_GAIN_LINE_ADC_L, 320 RT715_SET_GAIN_MIX_ADC_L, RT715_SET_GAIN_MIX_ADC2_L}; 321 unsigned int addr_h, addr_l, val_h = 0x0, val_ll, val_lr; 322 unsigned int read_ll, read_rl, i, j, loop_cnt = 4, k_changed = 0; 323 unsigned int k_shift = RT715_DIR_IN_SFT, k_max = 0x3f; 324 325 for (i = 0; i < 8; i++) { 326 if (ucontrol->value.integer.value[i] != rt715->kctl_8ch_vol_ori[i]) 327 k_changed = 1; 328 } 329 330 for (j = 0; j < loop_cnt; j++) { 331 addr_h = capture_reg_H[j]; 332 addr_l = capture_reg_L[j]; 333 rt715_get_gain(rt715, addr_h, addr_l, val_h, &read_rl, &read_ll); 334 335 if (dapm->bias_level <= SND_SOC_BIAS_STANDBY) 336 regmap_write(rt715->regmap, 337 RT715_SET_AUDIO_POWER_STATE, AC_PWRST_D0); 338 339 /* L Channel */ 340 /* for gain */ 341 rt715->kctl_8ch_vol_ori[j * 2] = ucontrol->value.integer.value[j * 2]; 342 val_ll = ((ucontrol->value.integer.value[j * 2]) & 0x7f); 343 if (val_ll > k_max) 344 val_ll = k_max; 345 /* keep mute status */ 346 val_ll |= read_ll & 0x80; 347 348 /* R Channel */ 349 /* for gain */ 350 rt715->kctl_8ch_vol_ori[j * 2 + 1] = 351 ucontrol->value.integer.value[j * 2 + 1]; 352 val_lr = ((ucontrol->value.integer.value[j * 2 + 1]) & 0x7f); 353 if (val_lr > k_max) 354 val_lr = k_max; 355 /* keep mute status */ 356 val_lr |= read_rl & 0x80; 357 358 for (i = 0; i < 3; i++) { /* retry 3 times at most */ 359 if (val_ll == val_lr) { 360 /* Set both L/R channels at the same time */ 361 val_h = (1 << k_shift) | (3 << 4); 362 regmap_write(rt715->regmap, addr_h, 363 (val_h << 8) | val_ll); 364 regmap_write(rt715->regmap, addr_l, 365 (val_h << 8) | val_ll); 366 } else { 367 /* Lch*/ 368 val_h = (1 << k_shift) | (1 << 5); 369 regmap_write(rt715->regmap, addr_h, 370 (val_h << 8) | val_ll); 371 /* Rch */ 372 val_h = (1 << k_shift) | (1 << 4); 373 regmap_write(rt715->regmap, addr_l, 374 (val_h << 8) | val_lr); 375 } 376 val_h = 0x0; 377 rt715_get_gain(rt715, addr_h, addr_l, val_h, 378 &read_rl, &read_ll); 379 if (read_rl == val_lr && read_ll == val_ll) 380 break; 381 } 382 } 383 384 /* D0:power on state, D3: power saving mode */ 385 if (dapm->bias_level <= SND_SOC_BIAS_STANDBY) 386 regmap_write(rt715->regmap, 387 RT715_SET_AUDIO_POWER_STATE, AC_PWRST_D3); 388 return k_changed; 389 } 390 391 static int rt715_set_main_vol_get(struct snd_kcontrol *kcontrol, 392 struct snd_ctl_elem_value *ucontrol) 393 { 394 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 395 struct rt715_priv *rt715 = snd_soc_component_get_drvdata(component); 396 static const unsigned int capture_reg_H[] = { 397 RT715_SET_GAIN_MIC_ADC_H, RT715_SET_GAIN_LINE_ADC_H, 398 RT715_SET_GAIN_MIX_ADC_H, RT715_SET_GAIN_MIX_ADC2_H }; 399 static const unsigned int capture_reg_L[] = { 400 RT715_SET_GAIN_MIC_ADC_L, RT715_SET_GAIN_LINE_ADC_L, 401 RT715_SET_GAIN_MIX_ADC_L, RT715_SET_GAIN_MIX_ADC2_L }; 402 unsigned int addr_h, addr_l, val_h = 0x0, i, loop_cnt = 4; 403 unsigned int read_ll, read_rl; 404 405 for (i = 0; i < loop_cnt; i++) { 406 addr_h = capture_reg_H[i]; 407 addr_l = capture_reg_L[i]; 408 rt715_get_gain(rt715, addr_h, addr_l, val_h, &read_rl, &read_ll); 409 410 ucontrol->value.integer.value[i * 2] = read_ll & 0x7f; 411 ucontrol->value.integer.value[i * 2 + 1] = read_rl & 0x7f; 412 } 413 414 return 0; 415 } 416 417 static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -1725, 75, 0); 418 static const DECLARE_TLV_DB_SCALE(mic_vol_tlv, 0, 1000, 0); 419 420 static int rt715_switch_info(struct snd_kcontrol *kcontrol, 421 struct snd_ctl_elem_info *uinfo) 422 { 423 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN; 424 uinfo->count = 8; 425 uinfo->value.integer.min = 0; 426 uinfo->value.integer.max = 1; 427 return 0; 428 } 429 430 static int rt715_vol_info(struct snd_kcontrol *kcontrol, 431 struct snd_ctl_elem_info *uinfo) 432 { 433 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 434 uinfo->count = 8; 435 uinfo->value.integer.min = 0; 436 uinfo->value.integer.max = 0x3f; 437 return 0; 438 } 439 440 #define SOC_DOUBLE_R_EXT(xname, reg_left, reg_right, xshift, xmax, xinvert,\ 441 xhandler_get, xhandler_put) \ 442 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \ 443 .info = snd_soc_info_volsw, \ 444 .get = xhandler_get, .put = xhandler_put, \ 445 .private_value = SOC_DOUBLE_R_VALUE(reg_left, reg_right, xshift, \ 446 xmax, xinvert) } 447 448 #define RT715_MAIN_SWITCH_EXT(xname, xhandler_get, xhandler_put) \ 449 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \ 450 .info = rt715_switch_info, \ 451 .get = xhandler_get, .put = xhandler_put, \ 452 } 453 454 #define RT715_MAIN_VOL_EXT_TLV(xname, xhandler_get, xhandler_put, tlv_array) \ 455 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \ 456 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ | \ 457 SNDRV_CTL_ELEM_ACCESS_READWRITE, \ 458 .tlv.p = (tlv_array), \ 459 .info = rt715_vol_info, \ 460 .get = xhandler_get, .put = xhandler_put, \ 461 } 462 463 static const struct snd_kcontrol_new rt715_snd_controls[] = { 464 /* Capture switch */ 465 RT715_MAIN_SWITCH_EXT("Capture Switch", 466 rt715_set_main_switch_get, rt715_set_main_switch_put), 467 /* Volume Control */ 468 RT715_MAIN_VOL_EXT_TLV("Capture Volume", 469 rt715_set_main_vol_get, rt715_set_main_vol_put, in_vol_tlv), 470 /* MIC Boost Control */ 471 SOC_DOUBLE_R_EXT_TLV("DMIC1 Boost", RT715_SET_GAIN_DMIC1_H, 472 RT715_SET_GAIN_DMIC1_L, RT715_DIR_IN_SFT, 3, 0, 473 rt715_set_amp_gain_get, rt715_set_amp_gain_put, 474 mic_vol_tlv), 475 SOC_DOUBLE_R_EXT_TLV("DMIC2 Boost", RT715_SET_GAIN_DMIC2_H, 476 RT715_SET_GAIN_DMIC2_L, RT715_DIR_IN_SFT, 3, 0, 477 rt715_set_amp_gain_get, rt715_set_amp_gain_put, 478 mic_vol_tlv), 479 SOC_DOUBLE_R_EXT_TLV("DMIC3 Boost", RT715_SET_GAIN_DMIC3_H, 480 RT715_SET_GAIN_DMIC3_L, RT715_DIR_IN_SFT, 3, 0, 481 rt715_set_amp_gain_get, rt715_set_amp_gain_put, 482 mic_vol_tlv), 483 SOC_DOUBLE_R_EXT_TLV("DMIC4 Boost", RT715_SET_GAIN_DMIC4_H, 484 RT715_SET_GAIN_DMIC4_L, RT715_DIR_IN_SFT, 3, 0, 485 rt715_set_amp_gain_get, rt715_set_amp_gain_put, 486 mic_vol_tlv), 487 SOC_DOUBLE_R_EXT_TLV("MIC1 Boost", RT715_SET_GAIN_MIC1_H, 488 RT715_SET_GAIN_MIC1_L, RT715_DIR_IN_SFT, 3, 0, 489 rt715_set_amp_gain_get, rt715_set_amp_gain_put, 490 mic_vol_tlv), 491 SOC_DOUBLE_R_EXT_TLV("MIC2 Boost", RT715_SET_GAIN_MIC2_H, 492 RT715_SET_GAIN_MIC2_L, RT715_DIR_IN_SFT, 3, 0, 493 rt715_set_amp_gain_get, rt715_set_amp_gain_put, 494 mic_vol_tlv), 495 SOC_DOUBLE_R_EXT_TLV("LINE1 Boost", RT715_SET_GAIN_LINE1_H, 496 RT715_SET_GAIN_LINE1_L, RT715_DIR_IN_SFT, 3, 0, 497 rt715_set_amp_gain_get, rt715_set_amp_gain_put, 498 mic_vol_tlv), 499 SOC_DOUBLE_R_EXT_TLV("LINE2 Boost", RT715_SET_GAIN_LINE2_H, 500 RT715_SET_GAIN_LINE2_L, RT715_DIR_IN_SFT, 3, 0, 501 rt715_set_amp_gain_get, rt715_set_amp_gain_put, 502 mic_vol_tlv), 503 }; 504 505 static int rt715_mux_get(struct snd_kcontrol *kcontrol, 506 struct snd_ctl_elem_value *ucontrol) 507 { 508 struct snd_soc_component *component = 509 snd_soc_dapm_kcontrol_component(kcontrol); 510 struct rt715_priv *rt715 = snd_soc_component_get_drvdata(component); 511 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 512 unsigned int reg, val; 513 int ret; 514 515 /* nid = e->reg, vid = 0xf01 */ 516 reg = RT715_VERB_SET_CONNECT_SEL | e->reg; 517 ret = regmap_read(rt715->regmap, reg, &val); 518 if (ret < 0) { 519 dev_err(component->dev, "%s: sdw read failed: %d\n", 520 __func__, ret); 521 return ret; 522 } 523 524 /* 525 * The first two indices of ADC Mux 24/25 are routed to the same 526 * hardware source. ie, ADC Mux 24 0/1 will both connect to MIC2. 527 * To have a unique set of inputs, we skip the index1 of the muxes. 528 */ 529 if ((e->reg == RT715_MUX_IN3 || e->reg == RT715_MUX_IN4) && (val > 0)) 530 val -= 1; 531 ucontrol->value.enumerated.item[0] = val; 532 533 return 0; 534 } 535 536 static int rt715_mux_put(struct snd_kcontrol *kcontrol, 537 struct snd_ctl_elem_value *ucontrol) 538 { 539 struct snd_soc_component *component = 540 snd_soc_dapm_kcontrol_component(kcontrol); 541 struct snd_soc_dapm_context *dapm = 542 snd_soc_dapm_kcontrol_dapm(kcontrol); 543 struct rt715_priv *rt715 = snd_soc_component_get_drvdata(component); 544 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 545 unsigned int *item = ucontrol->value.enumerated.item; 546 unsigned int val, val2 = 0, change, reg; 547 int ret; 548 549 if (item[0] >= e->items) 550 return -EINVAL; 551 552 /* Verb ID = 0x701h, nid = e->reg */ 553 val = snd_soc_enum_item_to_val(e, item[0]) << e->shift_l; 554 555 reg = RT715_VERB_SET_CONNECT_SEL | e->reg; 556 ret = regmap_read(rt715->regmap, reg, &val2); 557 if (ret < 0) { 558 dev_err(component->dev, "%s: sdw read failed: %d\n", 559 __func__, ret); 560 return ret; 561 } 562 563 if (val == val2) 564 change = 0; 565 else 566 change = 1; 567 568 if (change) { 569 reg = RT715_VERB_SET_CONNECT_SEL | e->reg; 570 regmap_write(rt715->regmap, reg, val); 571 } 572 573 snd_soc_dapm_mux_update_power(dapm, kcontrol, 574 item[0], e, NULL); 575 576 return change; 577 } 578 579 static const char * const adc_22_23_mux_text[] = { 580 "MIC1", 581 "MIC2", 582 "LINE1", 583 "LINE2", 584 "DMIC1", 585 "DMIC2", 586 "DMIC3", 587 "DMIC4", 588 }; 589 590 /* 591 * Due to mux design for nid 24 (MUX_IN3)/25 (MUX_IN4), connection index 0 and 592 * 1 will be connected to the same dmic source, therefore we skip index 1 to 593 * avoid misunderstanding on usage of dapm routing. 594 */ 595 static const unsigned int rt715_adc_24_25_values[] = { 596 0, 597 2, 598 3, 599 4, 600 5, 601 }; 602 603 static const char * const adc_24_mux_text[] = { 604 "MIC2", 605 "DMIC1", 606 "DMIC2", 607 "DMIC3", 608 "DMIC4", 609 }; 610 611 static const char * const adc_25_mux_text[] = { 612 "MIC1", 613 "DMIC1", 614 "DMIC2", 615 "DMIC3", 616 "DMIC4", 617 }; 618 619 static SOC_ENUM_SINGLE_DECL( 620 rt715_adc22_enum, RT715_MUX_IN1, 0, adc_22_23_mux_text); 621 622 static SOC_ENUM_SINGLE_DECL( 623 rt715_adc23_enum, RT715_MUX_IN2, 0, adc_22_23_mux_text); 624 625 static SOC_VALUE_ENUM_SINGLE_DECL(rt715_adc24_enum, 626 RT715_MUX_IN3, 0, 0xf, 627 adc_24_mux_text, rt715_adc_24_25_values); 628 629 static SOC_VALUE_ENUM_SINGLE_DECL(rt715_adc25_enum, 630 RT715_MUX_IN4, 0, 0xf, 631 adc_25_mux_text, rt715_adc_24_25_values); 632 633 static const struct snd_kcontrol_new rt715_adc22_mux = 634 SOC_DAPM_ENUM_EXT("ADC 22 Mux", rt715_adc22_enum, 635 rt715_mux_get, rt715_mux_put); 636 637 static const struct snd_kcontrol_new rt715_adc23_mux = 638 SOC_DAPM_ENUM_EXT("ADC 23 Mux", rt715_adc23_enum, 639 rt715_mux_get, rt715_mux_put); 640 641 static const struct snd_kcontrol_new rt715_adc24_mux = 642 SOC_DAPM_ENUM_EXT("ADC 24 Mux", rt715_adc24_enum, 643 rt715_mux_get, rt715_mux_put); 644 645 static const struct snd_kcontrol_new rt715_adc25_mux = 646 SOC_DAPM_ENUM_EXT("ADC 25 Mux", rt715_adc25_enum, 647 rt715_mux_get, rt715_mux_put); 648 649 static const struct snd_soc_dapm_widget rt715_dapm_widgets[] = { 650 SND_SOC_DAPM_INPUT("DMIC1"), 651 SND_SOC_DAPM_INPUT("DMIC2"), 652 SND_SOC_DAPM_INPUT("DMIC3"), 653 SND_SOC_DAPM_INPUT("DMIC4"), 654 SND_SOC_DAPM_INPUT("MIC1"), 655 SND_SOC_DAPM_INPUT("MIC2"), 656 SND_SOC_DAPM_INPUT("LINE1"), 657 SND_SOC_DAPM_INPUT("LINE2"), 658 SND_SOC_DAPM_ADC("ADC 07", NULL, RT715_SET_STREAMID_MIC_ADC, 4, 0), 659 SND_SOC_DAPM_ADC("ADC 08", NULL, RT715_SET_STREAMID_LINE_ADC, 4, 0), 660 SND_SOC_DAPM_ADC("ADC 09", NULL, RT715_SET_STREAMID_MIX_ADC, 4, 0), 661 SND_SOC_DAPM_ADC("ADC 27", NULL, RT715_SET_STREAMID_MIX_ADC2, 4, 0), 662 SND_SOC_DAPM_MUX("ADC 22 Mux", SND_SOC_NOPM, 0, 0, 663 &rt715_adc22_mux), 664 SND_SOC_DAPM_MUX("ADC 23 Mux", SND_SOC_NOPM, 0, 0, 665 &rt715_adc23_mux), 666 SND_SOC_DAPM_MUX("ADC 24 Mux", SND_SOC_NOPM, 0, 0, 667 &rt715_adc24_mux), 668 SND_SOC_DAPM_MUX("ADC 25 Mux", SND_SOC_NOPM, 0, 0, 669 &rt715_adc25_mux), 670 SND_SOC_DAPM_AIF_OUT("DP4TX", "DP4 Capture", 0, SND_SOC_NOPM, 0, 0), 671 SND_SOC_DAPM_AIF_OUT("DP6TX", "DP6 Capture", 0, SND_SOC_NOPM, 0, 0), 672 }; 673 674 static const struct snd_soc_dapm_route rt715_audio_map[] = { 675 {"DP6TX", NULL, "ADC 09"}, 676 {"DP6TX", NULL, "ADC 08"}, 677 {"DP4TX", NULL, "ADC 07"}, 678 {"DP4TX", NULL, "ADC 27"}, 679 {"ADC 09", NULL, "ADC 22 Mux"}, 680 {"ADC 08", NULL, "ADC 23 Mux"}, 681 {"ADC 07", NULL, "ADC 24 Mux"}, 682 {"ADC 27", NULL, "ADC 25 Mux"}, 683 {"ADC 22 Mux", "MIC1", "MIC1"}, 684 {"ADC 22 Mux", "MIC2", "MIC2"}, 685 {"ADC 22 Mux", "LINE1", "LINE1"}, 686 {"ADC 22 Mux", "LINE2", "LINE2"}, 687 {"ADC 22 Mux", "DMIC1", "DMIC1"}, 688 {"ADC 22 Mux", "DMIC2", "DMIC2"}, 689 {"ADC 22 Mux", "DMIC3", "DMIC3"}, 690 {"ADC 22 Mux", "DMIC4", "DMIC4"}, 691 {"ADC 23 Mux", "MIC1", "MIC1"}, 692 {"ADC 23 Mux", "MIC2", "MIC2"}, 693 {"ADC 23 Mux", "LINE1", "LINE1"}, 694 {"ADC 23 Mux", "LINE2", "LINE2"}, 695 {"ADC 23 Mux", "DMIC1", "DMIC1"}, 696 {"ADC 23 Mux", "DMIC2", "DMIC2"}, 697 {"ADC 23 Mux", "DMIC3", "DMIC3"}, 698 {"ADC 23 Mux", "DMIC4", "DMIC4"}, 699 {"ADC 24 Mux", "MIC2", "MIC2"}, 700 {"ADC 24 Mux", "DMIC1", "DMIC1"}, 701 {"ADC 24 Mux", "DMIC2", "DMIC2"}, 702 {"ADC 24 Mux", "DMIC3", "DMIC3"}, 703 {"ADC 24 Mux", "DMIC4", "DMIC4"}, 704 {"ADC 25 Mux", "MIC1", "MIC1"}, 705 {"ADC 25 Mux", "DMIC1", "DMIC1"}, 706 {"ADC 25 Mux", "DMIC2", "DMIC2"}, 707 {"ADC 25 Mux", "DMIC3", "DMIC3"}, 708 {"ADC 25 Mux", "DMIC4", "DMIC4"}, 709 }; 710 711 static int rt715_set_bias_level(struct snd_soc_component *component, 712 enum snd_soc_bias_level level) 713 { 714 struct snd_soc_dapm_context *dapm = 715 snd_soc_component_get_dapm(component); 716 struct rt715_priv *rt715 = snd_soc_component_get_drvdata(component); 717 718 switch (level) { 719 case SND_SOC_BIAS_PREPARE: 720 if (dapm->bias_level == SND_SOC_BIAS_STANDBY) { 721 regmap_write(rt715->regmap, 722 RT715_SET_AUDIO_POWER_STATE, 723 AC_PWRST_D0); 724 msleep(RT715_POWER_UP_DELAY_MS); 725 } 726 break; 727 728 case SND_SOC_BIAS_STANDBY: 729 regmap_write(rt715->regmap, 730 RT715_SET_AUDIO_POWER_STATE, 731 AC_PWRST_D3); 732 break; 733 734 default: 735 break; 736 } 737 dapm->bias_level = level; 738 return 0; 739 } 740 741 static int rt715_probe(struct snd_soc_component *component) 742 { 743 int ret; 744 745 ret = pm_runtime_resume(component->dev); 746 if (ret < 0 && ret != -EACCES) 747 return ret; 748 749 return 0; 750 } 751 752 static const struct snd_soc_component_driver soc_codec_dev_rt715 = { 753 .probe = rt715_probe, 754 .set_bias_level = rt715_set_bias_level, 755 .controls = rt715_snd_controls, 756 .num_controls = ARRAY_SIZE(rt715_snd_controls), 757 .dapm_widgets = rt715_dapm_widgets, 758 .num_dapm_widgets = ARRAY_SIZE(rt715_dapm_widgets), 759 .dapm_routes = rt715_audio_map, 760 .num_dapm_routes = ARRAY_SIZE(rt715_audio_map), 761 .endianness = 1, 762 }; 763 764 static int rt715_set_sdw_stream(struct snd_soc_dai *dai, void *sdw_stream, 765 int direction) 766 { 767 768 snd_soc_dai_dma_data_set(dai, direction, sdw_stream); 769 770 return 0; 771 } 772 773 static void rt715_shutdown(struct snd_pcm_substream *substream, 774 struct snd_soc_dai *dai) 775 776 { 777 snd_soc_dai_set_dma_data(dai, substream, NULL); 778 } 779 780 static int rt715_pcm_hw_params(struct snd_pcm_substream *substream, 781 struct snd_pcm_hw_params *params, 782 struct snd_soc_dai *dai) 783 { 784 struct snd_soc_component *component = dai->component; 785 struct rt715_priv *rt715 = snd_soc_component_get_drvdata(component); 786 struct sdw_stream_config stream_config = {0}; 787 struct sdw_port_config port_config = {0}; 788 struct sdw_stream_runtime *sdw_stream; 789 int retval; 790 unsigned int val = 0; 791 792 sdw_stream = snd_soc_dai_get_dma_data(dai, substream); 793 794 if (!sdw_stream) 795 return -EINVAL; 796 797 if (!rt715->slave) 798 return -EINVAL; 799 800 snd_sdw_params_to_config(substream, params, &stream_config, &port_config); 801 802 switch (dai->id) { 803 case RT715_AIF1: 804 port_config.num = 6; 805 rt715_index_write(rt715->regmap, RT715_SDW_INPUT_SEL, 0xa500); 806 break; 807 case RT715_AIF2: 808 port_config.num = 4; 809 rt715_index_write(rt715->regmap, RT715_SDW_INPUT_SEL, 0xa000); 810 break; 811 default: 812 dev_err(component->dev, "Invalid DAI id %d\n", dai->id); 813 return -EINVAL; 814 } 815 816 retval = sdw_stream_add_slave(rt715->slave, &stream_config, 817 &port_config, 1, sdw_stream); 818 if (retval) { 819 dev_err(dai->dev, "Unable to configure port\n"); 820 return retval; 821 } 822 823 switch (params_rate(params)) { 824 /* bit 14 0:48K 1:44.1K */ 825 /* bit 15 Stream Type 0:PCM 1:Non-PCM, should always be PCM */ 826 case 44100: 827 val |= 0x40 << 8; 828 break; 829 case 48000: 830 val |= 0x0 << 8; 831 break; 832 default: 833 dev_err(component->dev, "Unsupported sample rate %d\n", 834 params_rate(params)); 835 return -EINVAL; 836 } 837 838 if (params_channels(params) <= 16) { 839 /* bit 3:0 Number of Channel */ 840 val |= (params_channels(params) - 1); 841 } else { 842 dev_err(component->dev, "Unsupported channels %d\n", 843 params_channels(params)); 844 return -EINVAL; 845 } 846 847 switch (params_width(params)) { 848 /* bit 6:4 Bits per Sample */ 849 case 8: 850 break; 851 case 16: 852 val |= (0x1 << 4); 853 break; 854 case 20: 855 val |= (0x2 << 4); 856 break; 857 case 24: 858 val |= (0x3 << 4); 859 break; 860 case 32: 861 val |= (0x4 << 4); 862 break; 863 default: 864 return -EINVAL; 865 } 866 867 regmap_write(rt715->regmap, RT715_MIC_ADC_FORMAT_H, val); 868 regmap_write(rt715->regmap, RT715_MIC_LINE_FORMAT_H, val); 869 regmap_write(rt715->regmap, RT715_MIX_ADC_FORMAT_H, val); 870 regmap_write(rt715->regmap, RT715_MIX_ADC2_FORMAT_H, val); 871 872 return retval; 873 } 874 875 static int rt715_pcm_hw_free(struct snd_pcm_substream *substream, 876 struct snd_soc_dai *dai) 877 { 878 struct snd_soc_component *component = dai->component; 879 struct rt715_priv *rt715 = snd_soc_component_get_drvdata(component); 880 struct sdw_stream_runtime *sdw_stream = 881 snd_soc_dai_get_dma_data(dai, substream); 882 883 if (!rt715->slave) 884 return -EINVAL; 885 886 sdw_stream_remove_slave(rt715->slave, sdw_stream); 887 return 0; 888 } 889 890 #define RT715_STEREO_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000) 891 #define RT715_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ 892 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8) 893 894 static const struct snd_soc_dai_ops rt715_ops = { 895 .hw_params = rt715_pcm_hw_params, 896 .hw_free = rt715_pcm_hw_free, 897 .set_stream = rt715_set_sdw_stream, 898 .shutdown = rt715_shutdown, 899 }; 900 901 static struct snd_soc_dai_driver rt715_dai[] = { 902 { 903 .name = "rt715-aif1", 904 .id = RT715_AIF1, 905 .capture = { 906 .stream_name = "DP6 Capture", 907 .channels_min = 1, 908 .channels_max = 2, 909 .rates = RT715_STEREO_RATES, 910 .formats = RT715_FORMATS, 911 }, 912 .ops = &rt715_ops, 913 }, 914 { 915 .name = "rt715-aif2", 916 .id = RT715_AIF2, 917 .capture = { 918 .stream_name = "DP4 Capture", 919 .channels_min = 1, 920 .channels_max = 2, 921 .rates = RT715_STEREO_RATES, 922 .formats = RT715_FORMATS, 923 }, 924 .ops = &rt715_ops, 925 }, 926 }; 927 928 /* Bus clock frequency */ 929 #define RT715_CLK_FREQ_9600000HZ 9600000 930 #define RT715_CLK_FREQ_12000000HZ 12000000 931 #define RT715_CLK_FREQ_6000000HZ 6000000 932 #define RT715_CLK_FREQ_4800000HZ 4800000 933 #define RT715_CLK_FREQ_2400000HZ 2400000 934 #define RT715_CLK_FREQ_12288000HZ 12288000 935 936 int rt715_clock_config(struct device *dev) 937 { 938 struct rt715_priv *rt715 = dev_get_drvdata(dev); 939 unsigned int clk_freq, value; 940 941 clk_freq = (rt715->params.curr_dr_freq >> 1); 942 943 switch (clk_freq) { 944 case RT715_CLK_FREQ_12000000HZ: 945 value = 0x0; 946 break; 947 case RT715_CLK_FREQ_6000000HZ: 948 value = 0x1; 949 break; 950 case RT715_CLK_FREQ_9600000HZ: 951 value = 0x2; 952 break; 953 case RT715_CLK_FREQ_4800000HZ: 954 value = 0x3; 955 break; 956 case RT715_CLK_FREQ_2400000HZ: 957 value = 0x4; 958 break; 959 case RT715_CLK_FREQ_12288000HZ: 960 value = 0x5; 961 break; 962 default: 963 return -EINVAL; 964 } 965 966 regmap_write(rt715->regmap, 0xe0, value); 967 regmap_write(rt715->regmap, 0xf0, value); 968 969 return 0; 970 } 971 972 int rt715_init(struct device *dev, struct regmap *sdw_regmap, 973 struct regmap *regmap, struct sdw_slave *slave) 974 { 975 struct rt715_priv *rt715; 976 int ret; 977 978 rt715 = devm_kzalloc(dev, sizeof(*rt715), GFP_KERNEL); 979 if (!rt715) 980 return -ENOMEM; 981 982 dev_set_drvdata(dev, rt715); 983 rt715->slave = slave; 984 rt715->regmap = regmap; 985 rt715->sdw_regmap = sdw_regmap; 986 987 /* 988 * Mark hw_init to false 989 * HW init will be performed when device reports present 990 */ 991 rt715->hw_init = false; 992 rt715->first_hw_init = false; 993 994 ret = devm_snd_soc_register_component(dev, 995 &soc_codec_dev_rt715, 996 rt715_dai, 997 ARRAY_SIZE(rt715_dai)); 998 999 return ret; 1000 } 1001 1002 int rt715_io_init(struct device *dev, struct sdw_slave *slave) 1003 { 1004 struct rt715_priv *rt715 = dev_get_drvdata(dev); 1005 1006 if (rt715->hw_init) 1007 return 0; 1008 1009 /* 1010 * PM runtime is only enabled when a Slave reports as Attached 1011 */ 1012 if (!rt715->first_hw_init) { 1013 /* set autosuspend parameters */ 1014 pm_runtime_set_autosuspend_delay(&slave->dev, 3000); 1015 pm_runtime_use_autosuspend(&slave->dev); 1016 1017 /* update count of parent 'active' children */ 1018 pm_runtime_set_active(&slave->dev); 1019 1020 /* make sure the device does not suspend immediately */ 1021 pm_runtime_mark_last_busy(&slave->dev); 1022 1023 pm_runtime_enable(&slave->dev); 1024 } 1025 1026 pm_runtime_get_noresume(&slave->dev); 1027 1028 /* Mute nid=08h/09h */ 1029 regmap_write(rt715->regmap, RT715_SET_GAIN_LINE_ADC_H, 0xb080); 1030 regmap_write(rt715->regmap, RT715_SET_GAIN_MIX_ADC_H, 0xb080); 1031 /* Mute nid=07h/27h */ 1032 regmap_write(rt715->regmap, RT715_SET_GAIN_MIC_ADC_H, 0xb080); 1033 regmap_write(rt715->regmap, RT715_SET_GAIN_MIX_ADC2_H, 0xb080); 1034 1035 /* Set Pin Widget */ 1036 regmap_write(rt715->regmap, RT715_SET_PIN_DMIC1, 0x20); 1037 regmap_write(rt715->regmap, RT715_SET_PIN_DMIC2, 0x20); 1038 regmap_write(rt715->regmap, RT715_SET_PIN_DMIC3, 0x20); 1039 regmap_write(rt715->regmap, RT715_SET_PIN_DMIC4, 0x20); 1040 /* Set Converter Stream */ 1041 regmap_write(rt715->regmap, RT715_SET_STREAMID_LINE_ADC, 0x10); 1042 regmap_write(rt715->regmap, RT715_SET_STREAMID_MIX_ADC, 0x10); 1043 regmap_write(rt715->regmap, RT715_SET_STREAMID_MIC_ADC, 0x10); 1044 regmap_write(rt715->regmap, RT715_SET_STREAMID_MIX_ADC2, 0x10); 1045 /* Set Configuration Default */ 1046 regmap_write(rt715->regmap, RT715_SET_DMIC1_CONFIG_DEFAULT1, 0xd0); 1047 regmap_write(rt715->regmap, RT715_SET_DMIC1_CONFIG_DEFAULT2, 0x11); 1048 regmap_write(rt715->regmap, RT715_SET_DMIC1_CONFIG_DEFAULT3, 0xa1); 1049 regmap_write(rt715->regmap, RT715_SET_DMIC1_CONFIG_DEFAULT4, 0x81); 1050 regmap_write(rt715->regmap, RT715_SET_DMIC2_CONFIG_DEFAULT1, 0xd1); 1051 regmap_write(rt715->regmap, RT715_SET_DMIC2_CONFIG_DEFAULT2, 0x11); 1052 regmap_write(rt715->regmap, RT715_SET_DMIC2_CONFIG_DEFAULT3, 0xa1); 1053 regmap_write(rt715->regmap, RT715_SET_DMIC2_CONFIG_DEFAULT4, 0x81); 1054 regmap_write(rt715->regmap, RT715_SET_DMIC3_CONFIG_DEFAULT1, 0xd0); 1055 regmap_write(rt715->regmap, RT715_SET_DMIC3_CONFIG_DEFAULT2, 0x11); 1056 regmap_write(rt715->regmap, RT715_SET_DMIC3_CONFIG_DEFAULT3, 0xa1); 1057 regmap_write(rt715->regmap, RT715_SET_DMIC3_CONFIG_DEFAULT4, 0x81); 1058 regmap_write(rt715->regmap, RT715_SET_DMIC4_CONFIG_DEFAULT1, 0xd1); 1059 regmap_write(rt715->regmap, RT715_SET_DMIC4_CONFIG_DEFAULT2, 0x11); 1060 regmap_write(rt715->regmap, RT715_SET_DMIC4_CONFIG_DEFAULT3, 0xa1); 1061 regmap_write(rt715->regmap, RT715_SET_DMIC4_CONFIG_DEFAULT4, 0x81); 1062 1063 /* Finish Initial Settings, set power to D3 */ 1064 regmap_write(rt715->regmap, RT715_SET_AUDIO_POWER_STATE, AC_PWRST_D3); 1065 1066 if (rt715->first_hw_init) 1067 regcache_mark_dirty(rt715->regmap); 1068 else 1069 rt715->first_hw_init = true; 1070 1071 /* Mark Slave initialization complete */ 1072 rt715->hw_init = true; 1073 1074 pm_runtime_mark_last_busy(&slave->dev); 1075 pm_runtime_put_autosuspend(&slave->dev); 1076 1077 return 0; 1078 } 1079 1080 MODULE_DESCRIPTION("ASoC rt715 driver"); 1081 MODULE_DESCRIPTION("ASoC rt715 driver SDW"); 1082 MODULE_AUTHOR("Jack Yu <jack.yu@realtek.com>"); 1083 MODULE_LICENSE("GPL v2"); 1084