xref: /openbmc/linux/sound/soc/codecs/rt715.c (revision 02d89917)
1  // SPDX-License-Identifier: GPL-2.0
2  /*
3   * rt715.c -- rt715 ALSA SoC audio driver
4   *
5   * Copyright(c) 2019 Realtek Semiconductor Corp.
6   *
7   * ALC715 ASoC Codec Driver based Intel Dummy SdW codec driver
8   *
9   */
10  
11  #include <linux/module.h>
12  #include <linux/kernel.h>
13  #include <linux/init.h>
14  #include <linux/delay.h>
15  #include <linux/i2c.h>
16  #include <linux/pm_runtime.h>
17  #include <linux/pm.h>
18  #include <linux/soundwire/sdw.h>
19  #include <linux/regmap.h>
20  #include <linux/slab.h>
21  #include <linux/platform_device.h>
22  #include <linux/regulator/consumer.h>
23  #include <linux/of.h>
24  #include <linux/of_device.h>
25  #include <sound/core.h>
26  #include <sound/pcm.h>
27  #include <sound/pcm_params.h>
28  #include <sound/sdw.h>
29  #include <sound/soc.h>
30  #include <sound/soc-dapm.h>
31  #include <sound/initval.h>
32  #include <sound/tlv.h>
33  #include <sound/hda_verbs.h>
34  
35  #include "rt715.h"
36  
37  static int rt715_index_write(struct regmap *regmap, unsigned int reg,
38  		unsigned int value)
39  {
40  	int ret;
41  	unsigned int addr = ((RT715_PRIV_INDEX_W_H) << 8) | reg;
42  
43  	ret = regmap_write(regmap, addr, value);
44  	if (ret < 0) {
45  		pr_err("Failed to set private value: %08x <= %04x %d\n", ret,
46  			addr, value);
47  	}
48  
49  	return ret;
50  }
51  
52  static int rt715_index_write_nid(struct regmap *regmap,
53  		unsigned int nid, unsigned int reg, unsigned int value)
54  {
55  	int ret;
56  	unsigned int addr = ((RT715_PRIV_INDEX_W_H_2 | nid) << 8) | reg;
57  
58  	ret = regmap_write(regmap, addr, value);
59  	if (ret < 0)
60  		pr_err("Failed to set private value: %06x <= %04x ret=%d\n",
61  			addr, value, ret);
62  
63  	return ret;
64  }
65  
66  static int rt715_index_read_nid(struct regmap *regmap,
67  		unsigned int nid, unsigned int reg, unsigned int *value)
68  {
69  	int ret;
70  	unsigned int addr = ((RT715_PRIV_INDEX_W_H_2 | nid) << 8) | reg;
71  
72  	*value = 0;
73  	ret = regmap_read(regmap, addr, value);
74  	if (ret < 0)
75  		pr_err("Failed to get private value: %06x => %04x ret=%d\n",
76  			addr, *value, ret);
77  
78  	return ret;
79  }
80  
81  static int rt715_index_update_bits(struct regmap *regmap, unsigned int nid,
82  			unsigned int reg, unsigned int mask, unsigned int val)
83  {
84  	unsigned int tmp, orig;
85  	int ret;
86  
87  	ret = rt715_index_read_nid(regmap, nid, reg, &orig);
88  	if (ret < 0)
89  		return ret;
90  
91  	tmp = orig & ~mask;
92  	tmp |= val & mask;
93  
94  	return rt715_index_write_nid(regmap, nid, reg, tmp);
95  }
96  
97  static void rt715_reset(struct regmap *regmap)
98  {
99  	regmap_write(regmap, RT715_FUNC_RESET, 0);
100  	rt715_index_update_bits(regmap, RT715_VENDOR_REGISTERS,
101  		RT715_VD_CLEAR_CTRL, RT715_CLEAR_HIDDEN_REG,
102  		RT715_CLEAR_HIDDEN_REG);
103  }
104  
105  
106  static void rt715_get_gain(struct rt715_priv *rt715, unsigned int addr_h,
107  				unsigned int addr_l, unsigned int val_h,
108  				unsigned int *r_val, unsigned int *l_val)
109  {
110  	int ret;
111  	/* R Channel */
112  	*r_val = val_h << 8;
113  	ret = regmap_read(rt715->regmap, addr_l, r_val);
114  	if (ret < 0)
115  		pr_err("Failed to get R channel gain.\n");
116  
117  	/* L Channel */
118  	val_h |= 0x20;
119  	*l_val = val_h << 8;
120  	ret = regmap_read(rt715->regmap, addr_h, l_val);
121  	if (ret < 0)
122  		pr_err("Failed to get L channel gain.\n");
123  }
124  
125  /* For Verb-Set Amplifier Gain (Verb ID = 3h) */
126  static int rt715_set_amp_gain_put(struct snd_kcontrol *kcontrol,
127  					struct snd_ctl_elem_value *ucontrol)
128  {
129  	struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
130  	struct snd_soc_dapm_context *dapm =
131  		snd_soc_component_get_dapm(component);
132  	struct soc_mixer_control *mc =
133  		(struct soc_mixer_control *)kcontrol->private_value;
134  	struct rt715_priv *rt715 = snd_soc_component_get_drvdata(component);
135  	unsigned int addr_h, addr_l, val_h, val_ll, val_lr;
136  	unsigned int read_ll, read_rl, i;
137  	unsigned int k_vol_changed = 0;
138  
139  	for (i = 0; i < 2; i++) {
140  		if (ucontrol->value.integer.value[i] != rt715->kctl_2ch_vol_ori[i]) {
141  			k_vol_changed = 1;
142  			break;
143  		}
144  	}
145  
146  	/* Can't use update bit function, so read the original value first */
147  	addr_h = mc->reg;
148  	addr_l = mc->rreg;
149  
150  	if (mc->shift == RT715_DIR_OUT_SFT) /* output */
151  		val_h = 0x80;
152  	else /* input */
153  		val_h = 0x0;
154  
155  	rt715_get_gain(rt715, addr_h, addr_l, val_h, &read_rl, &read_ll);
156  
157  	if (dapm->bias_level <= SND_SOC_BIAS_STANDBY)
158  		regmap_write(rt715->regmap,
159  				RT715_SET_AUDIO_POWER_STATE, AC_PWRST_D0);
160  
161  	/* L Channel */
162  	rt715->kctl_2ch_vol_ori[0] = ucontrol->value.integer.value[0];
163  	/* for gain */
164  	val_ll = ((ucontrol->value.integer.value[0]) & 0x7f);
165  	if (val_ll > mc->max)
166  		val_ll = mc->max;
167  	/* keep mute status */
168  	val_ll |= read_ll & 0x80;
169  
170  	/* R Channel */
171  	rt715->kctl_2ch_vol_ori[1] = ucontrol->value.integer.value[1];
172  	/* for gain */
173  	val_lr = ((ucontrol->value.integer.value[1]) & 0x7f);
174  	if (val_lr > mc->max)
175  		val_lr = mc->max;
176  	/* keep mute status */
177  	val_lr |= read_rl & 0x80;
178  
179  	for (i = 0; i < 3; i++) { /* retry 3 times at most */
180  
181  		if (val_ll == val_lr) {
182  			/* Set both L/R channels at the same time */
183  			val_h = (1 << mc->shift) | (3 << 4);
184  			regmap_write(rt715->regmap, addr_h,
185  				(val_h << 8) | val_ll);
186  			regmap_write(rt715->regmap, addr_l,
187  				(val_h << 8) | val_ll);
188  		} else {
189  			/* Lch*/
190  			val_h = (1 << mc->shift) | (1 << 5);
191  			regmap_write(rt715->regmap, addr_h,
192  				(val_h << 8) | val_ll);
193  			/* Rch */
194  			val_h = (1 << mc->shift) | (1 << 4);
195  			regmap_write(rt715->regmap, addr_l,
196  				(val_h << 8) | val_lr);
197  		}
198  		/* check result */
199  		if (mc->shift == RT715_DIR_OUT_SFT) /* output */
200  			val_h = 0x80;
201  		else /* input */
202  			val_h = 0x0;
203  
204  		rt715_get_gain(rt715, addr_h, addr_l, val_h,
205  				&read_rl, &read_ll);
206  		if (read_rl == val_lr && read_ll == val_ll)
207  			break;
208  	}
209  
210  	/* D0:power on state, D3: power saving mode */
211  	if (dapm->bias_level <= SND_SOC_BIAS_STANDBY)
212  		regmap_write(rt715->regmap,
213  				RT715_SET_AUDIO_POWER_STATE, AC_PWRST_D3);
214  	return k_vol_changed;
215  }
216  
217  static int rt715_set_amp_gain_get(struct snd_kcontrol *kcontrol,
218  				  struct snd_ctl_elem_value *ucontrol)
219  {
220  	struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
221  	struct rt715_priv *rt715 = snd_soc_component_get_drvdata(component);
222  	struct soc_mixer_control *mc =
223  		(struct soc_mixer_control *)kcontrol->private_value;
224  	unsigned int addr_h, addr_l, val_h;
225  	unsigned int read_ll, read_rl;
226  
227  	addr_h = mc->reg;
228  	addr_l = mc->rreg;
229  	if (mc->shift == RT715_DIR_OUT_SFT) /* output */
230  		val_h = 0x80;
231  	else /* input */
232  		val_h = 0x0;
233  
234  	rt715_get_gain(rt715, addr_h, addr_l, val_h, &read_rl, &read_ll);
235  
236  	if (mc->invert) {
237  		/* for mute status */
238  		read_ll = !(read_ll & 0x80);
239  		read_rl = !(read_rl & 0x80);
240  	} else {
241  		/* for gain */
242  		read_ll = read_ll & 0x7f;
243  		read_rl = read_rl & 0x7f;
244  	}
245  	ucontrol->value.integer.value[0] = read_ll;
246  	ucontrol->value.integer.value[1] = read_rl;
247  
248  	return 0;
249  }
250  
251  static int rt715_set_main_switch_put(struct snd_kcontrol *kcontrol,
252  					struct snd_ctl_elem_value *ucontrol)
253  {
254  	struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
255  	struct snd_soc_dapm_context *dapm =
256  		snd_soc_component_get_dapm(component);
257  	struct rt715_priv *rt715 = snd_soc_component_get_drvdata(component);
258  	static const unsigned int capture_reg_H[] = {
259  		RT715_SET_GAIN_MIC_ADC_H, RT715_SET_GAIN_LINE_ADC_H,
260  		RT715_SET_GAIN_MIX_ADC_H, RT715_SET_GAIN_MIX_ADC2_H };
261  	static const unsigned int capture_reg_L[] = {
262  		RT715_SET_GAIN_MIC_ADC_L, RT715_SET_GAIN_LINE_ADC_L,
263  		RT715_SET_GAIN_MIX_ADC_L, RT715_SET_GAIN_MIX_ADC2_L };
264  	unsigned int addr_h, addr_l, val_h = 0x0, val_ll, val_lr;
265  	unsigned int k_shift = RT715_DIR_IN_SFT, k_changed = 0;
266  	unsigned int read_ll, read_rl, i, j, loop_cnt = 4;
267  
268  	for (i = 0; i < 8; i++) {
269  		if (ucontrol->value.integer.value[i] != rt715->kctl_8ch_switch_ori[i])
270  			k_changed = 1;
271  	}
272  
273  	for (j = 0; j < loop_cnt; j++) {
274  		/* Can't use update bit function, so read the original value first */
275  		addr_h = capture_reg_H[j];
276  		addr_l = capture_reg_L[j];
277  		rt715_get_gain(rt715, addr_h, addr_l, val_h, &read_rl, &read_ll);
278  
279  		if (dapm->bias_level <= SND_SOC_BIAS_STANDBY)
280  			regmap_write(rt715->regmap,
281  					RT715_SET_AUDIO_POWER_STATE, AC_PWRST_D0);
282  
283  		/* L Channel */
284  		/* for mute */
285  		rt715->kctl_8ch_switch_ori[j * 2] =
286  			ucontrol->value.integer.value[j * 2];
287  		val_ll = (!ucontrol->value.integer.value[j * 2]) << 7;
288  		/* keep gain */
289  		val_ll |= read_ll & 0x7f;
290  
291  		/* R Channel */
292  		/* for mute */
293  		rt715->kctl_8ch_switch_ori[j * 2 + 1] =
294  			ucontrol->value.integer.value[j * 2 + 1];
295  		val_lr = (!ucontrol->value.integer.value[j * 2 + 1]) << 7;
296  		/* keep gain */
297  		val_lr |= read_rl & 0x7f;
298  
299  		for (i = 0; i < 3; i++) { /* retry 3 times at most */
300  
301  			if (val_ll == val_lr) {
302  				/* Set both L/R channels at the same time */
303  				val_h = (1 << k_shift) | (3 << 4);
304  				regmap_write(rt715->regmap, addr_h,
305  					(val_h << 8) | val_ll);
306  				regmap_write(rt715->regmap, addr_l,
307  					(val_h << 8) | val_ll);
308  			} else {
309  				/* Lch*/
310  				val_h = (1 << k_shift) | (1 << 5);
311  				regmap_write(rt715->regmap, addr_h,
312  					(val_h << 8) | val_ll);
313  				/* Rch */
314  				val_h = (1 << k_shift) | (1 << 4);
315  				regmap_write(rt715->regmap, addr_l,
316  					(val_h << 8) | val_lr);
317  			}
318  			val_h = 0x0;
319  			rt715_get_gain(rt715, addr_h, addr_l, val_h,
320  					&read_rl, &read_ll);
321  			if (read_rl == val_lr && read_ll == val_ll)
322  				break;
323  		}
324  	}
325  
326  	/* D0:power on state, D3: power saving mode */
327  	if (dapm->bias_level <= SND_SOC_BIAS_STANDBY)
328  		regmap_write(rt715->regmap,
329  				RT715_SET_AUDIO_POWER_STATE, AC_PWRST_D3);
330  	return k_changed;
331  }
332  
333  static int rt715_set_main_switch_get(struct snd_kcontrol *kcontrol,
334  				  struct snd_ctl_elem_value *ucontrol)
335  {
336  	struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
337  	struct rt715_priv *rt715 = snd_soc_component_get_drvdata(component);
338  	static const unsigned int capture_reg_H[] = {
339  		RT715_SET_GAIN_MIC_ADC_H, RT715_SET_GAIN_LINE_ADC_H,
340  		RT715_SET_GAIN_MIX_ADC_H, RT715_SET_GAIN_MIX_ADC2_H };
341  	static const unsigned int capture_reg_L[] = {
342  		RT715_SET_GAIN_MIC_ADC_L, RT715_SET_GAIN_LINE_ADC_L,
343  		RT715_SET_GAIN_MIX_ADC_L, RT715_SET_GAIN_MIX_ADC2_L };
344  	unsigned int addr_h, addr_l, val_h = 0x0, i, loop_cnt = 4;
345  	unsigned int read_ll, read_rl;
346  
347  	for (i = 0; i < loop_cnt; i++) {
348  		addr_h = capture_reg_H[i];
349  		addr_l = capture_reg_L[i];
350  		rt715_get_gain(rt715, addr_h, addr_l, val_h, &read_rl, &read_ll);
351  
352  		ucontrol->value.integer.value[i * 2] = !(read_ll & 0x80);
353  		ucontrol->value.integer.value[i * 2 + 1] = !(read_rl & 0x80);
354  	}
355  
356  	return 0;
357  }
358  
359  static int rt715_set_main_vol_put(struct snd_kcontrol *kcontrol,
360  					struct snd_ctl_elem_value *ucontrol)
361  {
362  	struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
363  	struct snd_soc_dapm_context *dapm =
364  		snd_soc_component_get_dapm(component);
365  	struct rt715_priv *rt715 = snd_soc_component_get_drvdata(component);
366  	static const unsigned int capture_reg_H[] = {
367  		RT715_SET_GAIN_MIC_ADC_H, RT715_SET_GAIN_LINE_ADC_H,
368  		RT715_SET_GAIN_MIX_ADC_H, RT715_SET_GAIN_MIX_ADC2_H };
369  	static const unsigned int capture_reg_L[] = {
370  		RT715_SET_GAIN_MIC_ADC_L, RT715_SET_GAIN_LINE_ADC_L,
371  		RT715_SET_GAIN_MIX_ADC_L, RT715_SET_GAIN_MIX_ADC2_L};
372  	unsigned int addr_h, addr_l, val_h = 0x0, val_ll, val_lr;
373  	unsigned int read_ll, read_rl, i, j, loop_cnt = 4, k_changed = 0;
374  	unsigned int k_shift = RT715_DIR_IN_SFT, k_max = 0x3f;
375  
376  	for (i = 0; i < 8; i++) {
377  		if (ucontrol->value.integer.value[i] != rt715->kctl_8ch_vol_ori[i])
378  			k_changed = 1;
379  	}
380  
381  	for (j = 0; j < loop_cnt; j++) {
382  		addr_h = capture_reg_H[j];
383  		addr_l = capture_reg_L[j];
384  		rt715_get_gain(rt715, addr_h, addr_l, val_h, &read_rl, &read_ll);
385  
386  		if (dapm->bias_level <= SND_SOC_BIAS_STANDBY)
387  			regmap_write(rt715->regmap,
388  					RT715_SET_AUDIO_POWER_STATE, AC_PWRST_D0);
389  
390  		/* L Channel */
391  		/* for gain */
392  		rt715->kctl_8ch_vol_ori[j * 2] = ucontrol->value.integer.value[j * 2];
393  		val_ll = ((ucontrol->value.integer.value[j * 2]) & 0x7f);
394  		if (val_ll > k_max)
395  			val_ll = k_max;
396  		/* keep mute status */
397  		val_ll |= read_ll & 0x80;
398  
399  		/* R Channel */
400  		/* for gain */
401  		rt715->kctl_8ch_vol_ori[j * 2 + 1] =
402  			ucontrol->value.integer.value[j * 2 + 1];
403  		val_lr = ((ucontrol->value.integer.value[j * 2 + 1]) & 0x7f);
404  		if (val_lr > k_max)
405  			val_lr = k_max;
406  		/* keep mute status */
407  		val_lr |= read_rl & 0x80;
408  
409  		for (i = 0; i < 3; i++) { /* retry 3 times at most */
410  			if (val_ll == val_lr) {
411  				/* Set both L/R channels at the same time */
412  				val_h = (1 << k_shift) | (3 << 4);
413  				regmap_write(rt715->regmap, addr_h,
414  					(val_h << 8) | val_ll);
415  				regmap_write(rt715->regmap, addr_l,
416  					(val_h << 8) | val_ll);
417  			} else {
418  				/* Lch*/
419  				val_h = (1 << k_shift) | (1 << 5);
420  				regmap_write(rt715->regmap, addr_h,
421  					(val_h << 8) | val_ll);
422  				/* Rch */
423  				val_h = (1 << k_shift) | (1 << 4);
424  				regmap_write(rt715->regmap, addr_l,
425  					(val_h << 8) | val_lr);
426  			}
427  			val_h = 0x0;
428  			rt715_get_gain(rt715, addr_h, addr_l, val_h,
429  					&read_rl, &read_ll);
430  			if (read_rl == val_lr && read_ll == val_ll)
431  				break;
432  		}
433  	}
434  
435  	/* D0:power on state, D3: power saving mode */
436  	if (dapm->bias_level <= SND_SOC_BIAS_STANDBY)
437  		regmap_write(rt715->regmap,
438  				RT715_SET_AUDIO_POWER_STATE, AC_PWRST_D3);
439  	return k_changed;
440  }
441  
442  static int rt715_set_main_vol_get(struct snd_kcontrol *kcontrol,
443  				  struct snd_ctl_elem_value *ucontrol)
444  {
445  	struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
446  	struct rt715_priv *rt715 = snd_soc_component_get_drvdata(component);
447  	static const unsigned int capture_reg_H[] = {
448  		RT715_SET_GAIN_MIC_ADC_H, RT715_SET_GAIN_LINE_ADC_H,
449  		RT715_SET_GAIN_MIX_ADC_H, RT715_SET_GAIN_MIX_ADC2_H };
450  	static const unsigned int capture_reg_L[] = {
451  		RT715_SET_GAIN_MIC_ADC_L, RT715_SET_GAIN_LINE_ADC_L,
452  		RT715_SET_GAIN_MIX_ADC_L, RT715_SET_GAIN_MIX_ADC2_L };
453  	unsigned int addr_h, addr_l, val_h = 0x0, i, loop_cnt = 4;
454  	unsigned int read_ll, read_rl;
455  
456  	for (i = 0; i < loop_cnt; i++) {
457  		addr_h = capture_reg_H[i];
458  		addr_l = capture_reg_L[i];
459  		rt715_get_gain(rt715, addr_h, addr_l, val_h, &read_rl, &read_ll);
460  
461  		ucontrol->value.integer.value[i * 2] = read_ll & 0x7f;
462  		ucontrol->value.integer.value[i * 2 + 1] = read_rl & 0x7f;
463  	}
464  
465  	return 0;
466  }
467  
468  static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -1725, 75, 0);
469  static const DECLARE_TLV_DB_SCALE(mic_vol_tlv, 0, 1000, 0);
470  
471  static int rt715_switch_info(struct snd_kcontrol *kcontrol,
472  	struct snd_ctl_elem_info *uinfo)
473  {
474  	uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
475  	uinfo->count = 8;
476  	uinfo->value.integer.min = 0;
477  	uinfo->value.integer.max = 1;
478  	return 0;
479  }
480  
481  static int rt715_vol_info(struct snd_kcontrol *kcontrol,
482  	struct snd_ctl_elem_info *uinfo)
483  {
484  	uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
485  	uinfo->count = 8;
486  	uinfo->value.integer.min = 0;
487  	uinfo->value.integer.max = 0x3f;
488  	return 0;
489  }
490  
491  #define SOC_DOUBLE_R_EXT(xname, reg_left, reg_right, xshift, xmax, xinvert,\
492  	 xhandler_get, xhandler_put) \
493  {	.iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
494  	.info = snd_soc_info_volsw, \
495  	.get = xhandler_get, .put = xhandler_put, \
496  	.private_value = SOC_DOUBLE_R_VALUE(reg_left, reg_right, xshift, \
497  					    xmax, xinvert) }
498  
499  #define RT715_MAIN_SWITCH_EXT(xname, xhandler_get, xhandler_put) \
500  {	.iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
501  	.info = rt715_switch_info, \
502  	.get = xhandler_get, .put = xhandler_put, \
503  }
504  
505  #define RT715_MAIN_VOL_EXT_TLV(xname, xhandler_get, xhandler_put, tlv_array) \
506  {	.iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
507  	.access = SNDRV_CTL_ELEM_ACCESS_TLV_READ | \
508  		 SNDRV_CTL_ELEM_ACCESS_READWRITE, \
509  	.tlv.p = (tlv_array), \
510  	.info = rt715_vol_info, \
511  	.get = xhandler_get, .put = xhandler_put, \
512  }
513  
514  static const struct snd_kcontrol_new rt715_snd_controls[] = {
515  	/* Capture switch */
516  	RT715_MAIN_SWITCH_EXT("Capture Switch",
517  			rt715_set_main_switch_get, rt715_set_main_switch_put),
518  	/* Volume Control */
519  	RT715_MAIN_VOL_EXT_TLV("Capture Volume",
520  			rt715_set_main_vol_get, rt715_set_main_vol_put, in_vol_tlv),
521  	/* MIC Boost Control */
522  	SOC_DOUBLE_R_EXT_TLV("DMIC1 Boost", RT715_SET_GAIN_DMIC1_H,
523  			RT715_SET_GAIN_DMIC1_L, RT715_DIR_IN_SFT, 3, 0,
524  			rt715_set_amp_gain_get, rt715_set_amp_gain_put,
525  			mic_vol_tlv),
526  	SOC_DOUBLE_R_EXT_TLV("DMIC2 Boost", RT715_SET_GAIN_DMIC2_H,
527  			RT715_SET_GAIN_DMIC2_L, RT715_DIR_IN_SFT, 3, 0,
528  			rt715_set_amp_gain_get, rt715_set_amp_gain_put,
529  			mic_vol_tlv),
530  	SOC_DOUBLE_R_EXT_TLV("DMIC3 Boost", RT715_SET_GAIN_DMIC3_H,
531  			RT715_SET_GAIN_DMIC3_L, RT715_DIR_IN_SFT, 3, 0,
532  			rt715_set_amp_gain_get, rt715_set_amp_gain_put,
533  			mic_vol_tlv),
534  	SOC_DOUBLE_R_EXT_TLV("DMIC4 Boost", RT715_SET_GAIN_DMIC4_H,
535  			RT715_SET_GAIN_DMIC4_L, RT715_DIR_IN_SFT, 3, 0,
536  			rt715_set_amp_gain_get, rt715_set_amp_gain_put,
537  			mic_vol_tlv),
538  	SOC_DOUBLE_R_EXT_TLV("MIC1 Boost", RT715_SET_GAIN_MIC1_H,
539  			RT715_SET_GAIN_MIC1_L, RT715_DIR_IN_SFT, 3, 0,
540  			rt715_set_amp_gain_get, rt715_set_amp_gain_put,
541  			mic_vol_tlv),
542  	SOC_DOUBLE_R_EXT_TLV("MIC2 Boost", RT715_SET_GAIN_MIC2_H,
543  			RT715_SET_GAIN_MIC2_L, RT715_DIR_IN_SFT, 3, 0,
544  			rt715_set_amp_gain_get, rt715_set_amp_gain_put,
545  			mic_vol_tlv),
546  	SOC_DOUBLE_R_EXT_TLV("LINE1 Boost", RT715_SET_GAIN_LINE1_H,
547  			RT715_SET_GAIN_LINE1_L, RT715_DIR_IN_SFT, 3, 0,
548  			rt715_set_amp_gain_get, rt715_set_amp_gain_put,
549  			mic_vol_tlv),
550  	SOC_DOUBLE_R_EXT_TLV("LINE2 Boost", RT715_SET_GAIN_LINE2_H,
551  			RT715_SET_GAIN_LINE2_L, RT715_DIR_IN_SFT, 3, 0,
552  			rt715_set_amp_gain_get, rt715_set_amp_gain_put,
553  			mic_vol_tlv),
554  };
555  
556  static int rt715_mux_get(struct snd_kcontrol *kcontrol,
557  			struct snd_ctl_elem_value *ucontrol)
558  {
559  	struct snd_soc_component *component =
560  		snd_soc_dapm_kcontrol_component(kcontrol);
561  	struct rt715_priv *rt715 = snd_soc_component_get_drvdata(component);
562  	struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
563  	unsigned int reg, val;
564  	int ret;
565  
566  	/* nid = e->reg, vid = 0xf01 */
567  	reg = RT715_VERB_SET_CONNECT_SEL | e->reg;
568  	ret = regmap_read(rt715->regmap, reg, &val);
569  	if (ret < 0) {
570  		dev_err(component->dev, "%s: sdw read failed: %d\n",
571  			__func__, ret);
572  		return ret;
573  	}
574  
575  	/*
576  	 * The first two indices of ADC Mux 24/25 are routed to the same
577  	 * hardware source. ie, ADC Mux 24 0/1 will both connect to MIC2.
578  	 * To have a unique set of inputs, we skip the index1 of the muxes.
579  	 */
580  	if ((e->reg == RT715_MUX_IN3 || e->reg == RT715_MUX_IN4) && (val > 0))
581  		val -= 1;
582  	ucontrol->value.enumerated.item[0] = val;
583  
584  	return 0;
585  }
586  
587  static int rt715_mux_put(struct snd_kcontrol *kcontrol,
588  			struct snd_ctl_elem_value *ucontrol)
589  {
590  	struct snd_soc_component *component =
591  		snd_soc_dapm_kcontrol_component(kcontrol);
592  	struct snd_soc_dapm_context *dapm =
593  				snd_soc_dapm_kcontrol_dapm(kcontrol);
594  	struct rt715_priv *rt715 = snd_soc_component_get_drvdata(component);
595  	struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
596  	unsigned int *item = ucontrol->value.enumerated.item;
597  	unsigned int val, val2 = 0, change, reg;
598  	int ret;
599  
600  	if (item[0] >= e->items)
601  		return -EINVAL;
602  
603  	/* Verb ID = 0x701h, nid = e->reg */
604  	val = snd_soc_enum_item_to_val(e, item[0]) << e->shift_l;
605  
606  	reg = RT715_VERB_SET_CONNECT_SEL | e->reg;
607  	ret = regmap_read(rt715->regmap, reg, &val2);
608  	if (ret < 0) {
609  		dev_err(component->dev, "%s: sdw read failed: %d\n",
610  			__func__, ret);
611  		return ret;
612  	}
613  
614  	if (val == val2)
615  		change = 0;
616  	else
617  		change = 1;
618  
619  	if (change) {
620  		reg = RT715_VERB_SET_CONNECT_SEL | e->reg;
621  		regmap_write(rt715->regmap, reg, val);
622  	}
623  
624  	snd_soc_dapm_mux_update_power(dapm, kcontrol,
625  						item[0], e, NULL);
626  
627  	return change;
628  }
629  
630  static const char * const adc_22_23_mux_text[] = {
631  	"MIC1",
632  	"MIC2",
633  	"LINE1",
634  	"LINE2",
635  	"DMIC1",
636  	"DMIC2",
637  	"DMIC3",
638  	"DMIC4",
639  };
640  
641  /*
642   * Due to mux design for nid 24 (MUX_IN3)/25 (MUX_IN4), connection index 0 and
643   * 1 will be connected to the same dmic source, therefore we skip index 1 to
644   * avoid misunderstanding on usage of dapm routing.
645   */
646  static const unsigned int rt715_adc_24_25_values[] = {
647  	0,
648  	2,
649  	3,
650  	4,
651  	5,
652  };
653  
654  static const char * const adc_24_mux_text[] = {
655  	"MIC2",
656  	"DMIC1",
657  	"DMIC2",
658  	"DMIC3",
659  	"DMIC4",
660  };
661  
662  static const char * const adc_25_mux_text[] = {
663  	"MIC1",
664  	"DMIC1",
665  	"DMIC2",
666  	"DMIC3",
667  	"DMIC4",
668  };
669  
670  static SOC_ENUM_SINGLE_DECL(
671  	rt715_adc22_enum, RT715_MUX_IN1, 0, adc_22_23_mux_text);
672  
673  static SOC_ENUM_SINGLE_DECL(
674  	rt715_adc23_enum, RT715_MUX_IN2, 0, adc_22_23_mux_text);
675  
676  static SOC_VALUE_ENUM_SINGLE_DECL(rt715_adc24_enum,
677  	RT715_MUX_IN3, 0, 0xf,
678  	adc_24_mux_text, rt715_adc_24_25_values);
679  
680  static SOC_VALUE_ENUM_SINGLE_DECL(rt715_adc25_enum,
681  	RT715_MUX_IN4, 0, 0xf,
682  	adc_25_mux_text, rt715_adc_24_25_values);
683  
684  static const struct snd_kcontrol_new rt715_adc22_mux =
685  	SOC_DAPM_ENUM_EXT("ADC 22 Mux", rt715_adc22_enum,
686  			rt715_mux_get, rt715_mux_put);
687  
688  static const struct snd_kcontrol_new rt715_adc23_mux =
689  	SOC_DAPM_ENUM_EXT("ADC 23 Mux", rt715_adc23_enum,
690  			rt715_mux_get, rt715_mux_put);
691  
692  static const struct snd_kcontrol_new rt715_adc24_mux =
693  	SOC_DAPM_ENUM_EXT("ADC 24 Mux", rt715_adc24_enum,
694  			rt715_mux_get, rt715_mux_put);
695  
696  static const struct snd_kcontrol_new rt715_adc25_mux =
697  	SOC_DAPM_ENUM_EXT("ADC 25 Mux", rt715_adc25_enum,
698  			rt715_mux_get, rt715_mux_put);
699  
700  static const struct snd_soc_dapm_widget rt715_dapm_widgets[] = {
701  	SND_SOC_DAPM_INPUT("DMIC1"),
702  	SND_SOC_DAPM_INPUT("DMIC2"),
703  	SND_SOC_DAPM_INPUT("DMIC3"),
704  	SND_SOC_DAPM_INPUT("DMIC4"),
705  	SND_SOC_DAPM_INPUT("MIC1"),
706  	SND_SOC_DAPM_INPUT("MIC2"),
707  	SND_SOC_DAPM_INPUT("LINE1"),
708  	SND_SOC_DAPM_INPUT("LINE2"),
709  	SND_SOC_DAPM_ADC("ADC 07", NULL, RT715_SET_STREAMID_MIC_ADC, 4, 0),
710  	SND_SOC_DAPM_ADC("ADC 08", NULL, RT715_SET_STREAMID_LINE_ADC, 4, 0),
711  	SND_SOC_DAPM_ADC("ADC 09", NULL, RT715_SET_STREAMID_MIX_ADC, 4, 0),
712  	SND_SOC_DAPM_ADC("ADC 27", NULL, RT715_SET_STREAMID_MIX_ADC2, 4, 0),
713  	SND_SOC_DAPM_MUX("ADC 22 Mux", SND_SOC_NOPM, 0, 0,
714  		&rt715_adc22_mux),
715  	SND_SOC_DAPM_MUX("ADC 23 Mux", SND_SOC_NOPM, 0, 0,
716  		&rt715_adc23_mux),
717  	SND_SOC_DAPM_MUX("ADC 24 Mux", SND_SOC_NOPM, 0, 0,
718  		&rt715_adc24_mux),
719  	SND_SOC_DAPM_MUX("ADC 25 Mux", SND_SOC_NOPM, 0, 0,
720  		&rt715_adc25_mux),
721  	SND_SOC_DAPM_AIF_OUT("DP4TX", "DP4 Capture", 0, SND_SOC_NOPM, 0, 0),
722  	SND_SOC_DAPM_AIF_OUT("DP6TX", "DP6 Capture", 0, SND_SOC_NOPM, 0, 0),
723  };
724  
725  static const struct snd_soc_dapm_route rt715_audio_map[] = {
726  	{"DP6TX", NULL, "ADC 09"},
727  	{"DP6TX", NULL, "ADC 08"},
728  	{"DP4TX", NULL, "ADC 07"},
729  	{"DP4TX", NULL, "ADC 27"},
730  	{"ADC 09", NULL, "ADC 22 Mux"},
731  	{"ADC 08", NULL, "ADC 23 Mux"},
732  	{"ADC 07", NULL, "ADC 24 Mux"},
733  	{"ADC 27", NULL, "ADC 25 Mux"},
734  	{"ADC 22 Mux", "MIC1", "MIC1"},
735  	{"ADC 22 Mux", "MIC2", "MIC2"},
736  	{"ADC 22 Mux", "LINE1", "LINE1"},
737  	{"ADC 22 Mux", "LINE2", "LINE2"},
738  	{"ADC 22 Mux", "DMIC1", "DMIC1"},
739  	{"ADC 22 Mux", "DMIC2", "DMIC2"},
740  	{"ADC 22 Mux", "DMIC3", "DMIC3"},
741  	{"ADC 22 Mux", "DMIC4", "DMIC4"},
742  	{"ADC 23 Mux", "MIC1", "MIC1"},
743  	{"ADC 23 Mux", "MIC2", "MIC2"},
744  	{"ADC 23 Mux", "LINE1", "LINE1"},
745  	{"ADC 23 Mux", "LINE2", "LINE2"},
746  	{"ADC 23 Mux", "DMIC1", "DMIC1"},
747  	{"ADC 23 Mux", "DMIC2", "DMIC2"},
748  	{"ADC 23 Mux", "DMIC3", "DMIC3"},
749  	{"ADC 23 Mux", "DMIC4", "DMIC4"},
750  	{"ADC 24 Mux", "MIC2", "MIC2"},
751  	{"ADC 24 Mux", "DMIC1", "DMIC1"},
752  	{"ADC 24 Mux", "DMIC2", "DMIC2"},
753  	{"ADC 24 Mux", "DMIC3", "DMIC3"},
754  	{"ADC 24 Mux", "DMIC4", "DMIC4"},
755  	{"ADC 25 Mux", "MIC1", "MIC1"},
756  	{"ADC 25 Mux", "DMIC1", "DMIC1"},
757  	{"ADC 25 Mux", "DMIC2", "DMIC2"},
758  	{"ADC 25 Mux", "DMIC3", "DMIC3"},
759  	{"ADC 25 Mux", "DMIC4", "DMIC4"},
760  };
761  
762  static int rt715_set_bias_level(struct snd_soc_component *component,
763  				enum snd_soc_bias_level level)
764  {
765  	struct snd_soc_dapm_context *dapm =
766  		snd_soc_component_get_dapm(component);
767  	struct rt715_priv *rt715 = snd_soc_component_get_drvdata(component);
768  
769  	switch (level) {
770  	case SND_SOC_BIAS_PREPARE:
771  		if (dapm->bias_level == SND_SOC_BIAS_STANDBY) {
772  			regmap_write(rt715->regmap,
773  						RT715_SET_AUDIO_POWER_STATE,
774  						AC_PWRST_D0);
775  			msleep(RT715_POWER_UP_DELAY_MS);
776  		}
777  		break;
778  
779  	case SND_SOC_BIAS_STANDBY:
780  		regmap_write(rt715->regmap,
781  					RT715_SET_AUDIO_POWER_STATE,
782  					AC_PWRST_D3);
783  		break;
784  
785  	default:
786  		break;
787  	}
788  	dapm->bias_level = level;
789  	return 0;
790  }
791  
792  static int rt715_probe(struct snd_soc_component *component)
793  {
794  	struct rt715_priv *rt715 = snd_soc_component_get_drvdata(component);
795  	int ret;
796  
797  	if (!rt715->first_hw_init)
798  		return 0;
799  
800  	ret = pm_runtime_resume(component->dev);
801  	if (ret < 0 && ret != -EACCES)
802  		return ret;
803  
804  	return 0;
805  }
806  
807  static const struct snd_soc_component_driver soc_codec_dev_rt715 = {
808  	.probe = rt715_probe,
809  	.set_bias_level = rt715_set_bias_level,
810  	.controls = rt715_snd_controls,
811  	.num_controls = ARRAY_SIZE(rt715_snd_controls),
812  	.dapm_widgets = rt715_dapm_widgets,
813  	.num_dapm_widgets = ARRAY_SIZE(rt715_dapm_widgets),
814  	.dapm_routes = rt715_audio_map,
815  	.num_dapm_routes = ARRAY_SIZE(rt715_audio_map),
816  	.endianness = 1,
817  };
818  
819  static int rt715_set_sdw_stream(struct snd_soc_dai *dai, void *sdw_stream,
820  				int direction)
821  {
822  
823  	snd_soc_dai_dma_data_set(dai, direction, sdw_stream);
824  
825  	return 0;
826  }
827  
828  static void rt715_shutdown(struct snd_pcm_substream *substream,
829  				struct snd_soc_dai *dai)
830  
831  {
832  	snd_soc_dai_set_dma_data(dai, substream, NULL);
833  }
834  
835  static int rt715_pcm_hw_params(struct snd_pcm_substream *substream,
836  				struct snd_pcm_hw_params *params,
837  				struct snd_soc_dai *dai)
838  {
839  	struct snd_soc_component *component = dai->component;
840  	struct rt715_priv *rt715 = snd_soc_component_get_drvdata(component);
841  	struct sdw_stream_config stream_config = {0};
842  	struct sdw_port_config port_config = {0};
843  	struct sdw_stream_runtime *sdw_stream;
844  	int retval;
845  	unsigned int val = 0;
846  
847  	sdw_stream = snd_soc_dai_get_dma_data(dai, substream);
848  
849  	if (!sdw_stream)
850  		return -EINVAL;
851  
852  	if (!rt715->slave)
853  		return -EINVAL;
854  
855  	snd_sdw_params_to_config(substream, params, &stream_config, &port_config);
856  
857  	switch (dai->id) {
858  	case RT715_AIF1:
859  		port_config.num = 6;
860  		rt715_index_write(rt715->regmap, RT715_SDW_INPUT_SEL, 0xa500);
861  		break;
862  	case RT715_AIF2:
863  		port_config.num = 4;
864  		rt715_index_write(rt715->regmap, RT715_SDW_INPUT_SEL, 0xa000);
865  		break;
866  	default:
867  		dev_err(component->dev, "Invalid DAI id %d\n", dai->id);
868  		return -EINVAL;
869  	}
870  
871  	retval = sdw_stream_add_slave(rt715->slave, &stream_config,
872  					&port_config, 1, sdw_stream);
873  	if (retval) {
874  		dev_err(dai->dev, "Unable to configure port\n");
875  		return retval;
876  	}
877  
878  	switch (params_rate(params)) {
879  	/* bit 14 0:48K 1:44.1K */
880  	/* bit 15 Stream Type 0:PCM 1:Non-PCM, should always be PCM */
881  	case 44100:
882  		val |= 0x40 << 8;
883  		break;
884  	case 48000:
885  		val |= 0x0 << 8;
886  		break;
887  	default:
888  		dev_err(component->dev, "Unsupported sample rate %d\n",
889  			params_rate(params));
890  		return -EINVAL;
891  	}
892  
893  	if (params_channels(params) <= 16) {
894  		/* bit 3:0 Number of Channel */
895  		val |= (params_channels(params) - 1);
896  	} else {
897  		dev_err(component->dev, "Unsupported channels %d\n",
898  			params_channels(params));
899  		return -EINVAL;
900  	}
901  
902  	switch (params_width(params)) {
903  	/* bit 6:4 Bits per Sample */
904  	case 8:
905  		break;
906  	case 16:
907  		val |= (0x1 << 4);
908  		break;
909  	case 20:
910  		val |= (0x2 << 4);
911  		break;
912  	case 24:
913  		val |= (0x3 << 4);
914  		break;
915  	case 32:
916  		val |= (0x4 << 4);
917  		break;
918  	default:
919  		return -EINVAL;
920  	}
921  
922  	regmap_write(rt715->regmap, RT715_MIC_ADC_FORMAT_H, val);
923  	regmap_write(rt715->regmap, RT715_MIC_LINE_FORMAT_H, val);
924  	regmap_write(rt715->regmap, RT715_MIX_ADC_FORMAT_H, val);
925  	regmap_write(rt715->regmap, RT715_MIX_ADC2_FORMAT_H, val);
926  
927  	return retval;
928  }
929  
930  static int rt715_pcm_hw_free(struct snd_pcm_substream *substream,
931  				struct snd_soc_dai *dai)
932  {
933  	struct snd_soc_component *component = dai->component;
934  	struct rt715_priv *rt715 = snd_soc_component_get_drvdata(component);
935  	struct sdw_stream_runtime *sdw_stream =
936  		snd_soc_dai_get_dma_data(dai, substream);
937  
938  	if (!rt715->slave)
939  		return -EINVAL;
940  
941  	sdw_stream_remove_slave(rt715->slave, sdw_stream);
942  	return 0;
943  }
944  
945  #define RT715_STEREO_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000)
946  #define RT715_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
947  			SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
948  
949  static const struct snd_soc_dai_ops rt715_ops = {
950  	.hw_params	= rt715_pcm_hw_params,
951  	.hw_free	= rt715_pcm_hw_free,
952  	.set_stream	= rt715_set_sdw_stream,
953  	.shutdown	= rt715_shutdown,
954  };
955  
956  static struct snd_soc_dai_driver rt715_dai[] = {
957  	{
958  		.name = "rt715-aif1",
959  		.id = RT715_AIF1,
960  		.capture = {
961  			.stream_name = "DP6 Capture",
962  			.channels_min = 1,
963  			.channels_max = 2,
964  			.rates = RT715_STEREO_RATES,
965  			.formats = RT715_FORMATS,
966  		},
967  		.ops = &rt715_ops,
968  	},
969  	{
970  		.name = "rt715-aif2",
971  		.id = RT715_AIF2,
972  		.capture = {
973  			.stream_name = "DP4 Capture",
974  			.channels_min = 1,
975  			.channels_max = 2,
976  			.rates = RT715_STEREO_RATES,
977  			.formats = RT715_FORMATS,
978  		},
979  		.ops = &rt715_ops,
980  	},
981  };
982  
983  /* Bus clock frequency */
984  #define RT715_CLK_FREQ_9600000HZ 9600000
985  #define RT715_CLK_FREQ_12000000HZ 12000000
986  #define RT715_CLK_FREQ_6000000HZ 6000000
987  #define RT715_CLK_FREQ_4800000HZ 4800000
988  #define RT715_CLK_FREQ_2400000HZ 2400000
989  #define RT715_CLK_FREQ_12288000HZ 12288000
990  
991  int rt715_clock_config(struct device *dev)
992  {
993  	struct rt715_priv *rt715 = dev_get_drvdata(dev);
994  	unsigned int clk_freq, value;
995  
996  	clk_freq = (rt715->params.curr_dr_freq >> 1);
997  
998  	switch (clk_freq) {
999  	case RT715_CLK_FREQ_12000000HZ:
1000  		value = 0x0;
1001  		break;
1002  	case RT715_CLK_FREQ_6000000HZ:
1003  		value = 0x1;
1004  		break;
1005  	case RT715_CLK_FREQ_9600000HZ:
1006  		value = 0x2;
1007  		break;
1008  	case RT715_CLK_FREQ_4800000HZ:
1009  		value = 0x3;
1010  		break;
1011  	case RT715_CLK_FREQ_2400000HZ:
1012  		value = 0x4;
1013  		break;
1014  	case RT715_CLK_FREQ_12288000HZ:
1015  		value = 0x5;
1016  		break;
1017  	default:
1018  		return -EINVAL;
1019  	}
1020  
1021  	regmap_write(rt715->regmap, 0xe0, value);
1022  	regmap_write(rt715->regmap, 0xf0, value);
1023  
1024  	return 0;
1025  }
1026  
1027  int rt715_init(struct device *dev, struct regmap *sdw_regmap,
1028  	struct regmap *regmap, struct sdw_slave *slave)
1029  {
1030  	struct rt715_priv *rt715;
1031  	int ret;
1032  
1033  	rt715 = devm_kzalloc(dev, sizeof(*rt715), GFP_KERNEL);
1034  	if (!rt715)
1035  		return -ENOMEM;
1036  
1037  	dev_set_drvdata(dev, rt715);
1038  	rt715->slave = slave;
1039  	rt715->regmap = regmap;
1040  	rt715->sdw_regmap = sdw_regmap;
1041  
1042  	regcache_cache_only(rt715->regmap, true);
1043  
1044  	/*
1045  	 * Mark hw_init to false
1046  	 * HW init will be performed when device reports present
1047  	 */
1048  	rt715->hw_init = false;
1049  	rt715->first_hw_init = false;
1050  
1051  	ret = devm_snd_soc_register_component(dev,
1052  						&soc_codec_dev_rt715,
1053  						rt715_dai,
1054  						ARRAY_SIZE(rt715_dai));
1055  	if (ret < 0)
1056  		return ret;
1057  
1058  	/* set autosuspend parameters */
1059  	pm_runtime_set_autosuspend_delay(dev, 3000);
1060  	pm_runtime_use_autosuspend(dev);
1061  
1062  	/* make sure the device does not suspend immediately */
1063  	pm_runtime_mark_last_busy(dev);
1064  
1065  	pm_runtime_enable(dev);
1066  
1067  	/* important note: the device is NOT tagged as 'active' and will remain
1068  	 * 'suspended' until the hardware is enumerated/initialized. This is required
1069  	 * to make sure the ASoC framework use of pm_runtime_get_sync() does not silently
1070  	 * fail with -EACCESS because of race conditions between card creation and enumeration
1071  	 */
1072  
1073  	return 0;
1074  }
1075  
1076  int rt715_io_init(struct device *dev, struct sdw_slave *slave)
1077  {
1078  	struct rt715_priv *rt715 = dev_get_drvdata(dev);
1079  
1080  	if (rt715->hw_init)
1081  		return 0;
1082  
1083  	regcache_cache_only(rt715->regmap, false);
1084  
1085  	/*
1086  	 *  PM runtime status is marked as 'active' only when a Slave reports as Attached
1087  	 */
1088  	if (!rt715->first_hw_init)
1089  		/* update count of parent 'active' children */
1090  		pm_runtime_set_active(&slave->dev);
1091  
1092  	pm_runtime_get_noresume(&slave->dev);
1093  
1094  	rt715_reset(rt715->regmap);
1095  
1096  	/* Mute nid=08h/09h */
1097  	regmap_write(rt715->regmap, RT715_SET_GAIN_LINE_ADC_H, 0xb080);
1098  	regmap_write(rt715->regmap, RT715_SET_GAIN_MIX_ADC_H, 0xb080);
1099  	/* Mute nid=07h/27h */
1100  	regmap_write(rt715->regmap, RT715_SET_GAIN_MIC_ADC_H, 0xb080);
1101  	regmap_write(rt715->regmap, RT715_SET_GAIN_MIX_ADC2_H, 0xb080);
1102  
1103  	/* Set Pin Widget */
1104  	regmap_write(rt715->regmap, RT715_SET_PIN_DMIC1, 0x20);
1105  	regmap_write(rt715->regmap, RT715_SET_PIN_DMIC2, 0x20);
1106  	regmap_write(rt715->regmap, RT715_SET_PIN_DMIC3, 0x20);
1107  	regmap_write(rt715->regmap, RT715_SET_PIN_DMIC4, 0x20);
1108  	/* Set Converter Stream */
1109  	regmap_write(rt715->regmap, RT715_SET_STREAMID_LINE_ADC, 0x10);
1110  	regmap_write(rt715->regmap, RT715_SET_STREAMID_MIX_ADC, 0x10);
1111  	regmap_write(rt715->regmap, RT715_SET_STREAMID_MIC_ADC, 0x10);
1112  	regmap_write(rt715->regmap, RT715_SET_STREAMID_MIX_ADC2, 0x10);
1113  	/* Set Configuration Default */
1114  	regmap_write(rt715->regmap, RT715_SET_DMIC1_CONFIG_DEFAULT1, 0xd0);
1115  	regmap_write(rt715->regmap, RT715_SET_DMIC1_CONFIG_DEFAULT2, 0x11);
1116  	regmap_write(rt715->regmap, RT715_SET_DMIC1_CONFIG_DEFAULT3, 0xa1);
1117  	regmap_write(rt715->regmap, RT715_SET_DMIC1_CONFIG_DEFAULT4, 0x81);
1118  	regmap_write(rt715->regmap, RT715_SET_DMIC2_CONFIG_DEFAULT1, 0xd1);
1119  	regmap_write(rt715->regmap, RT715_SET_DMIC2_CONFIG_DEFAULT2, 0x11);
1120  	regmap_write(rt715->regmap, RT715_SET_DMIC2_CONFIG_DEFAULT3, 0xa1);
1121  	regmap_write(rt715->regmap, RT715_SET_DMIC2_CONFIG_DEFAULT4, 0x81);
1122  	regmap_write(rt715->regmap, RT715_SET_DMIC3_CONFIG_DEFAULT1, 0xd0);
1123  	regmap_write(rt715->regmap, RT715_SET_DMIC3_CONFIG_DEFAULT2, 0x11);
1124  	regmap_write(rt715->regmap, RT715_SET_DMIC3_CONFIG_DEFAULT3, 0xa1);
1125  	regmap_write(rt715->regmap, RT715_SET_DMIC3_CONFIG_DEFAULT4, 0x81);
1126  	regmap_write(rt715->regmap, RT715_SET_DMIC4_CONFIG_DEFAULT1, 0xd1);
1127  	regmap_write(rt715->regmap, RT715_SET_DMIC4_CONFIG_DEFAULT2, 0x11);
1128  	regmap_write(rt715->regmap, RT715_SET_DMIC4_CONFIG_DEFAULT3, 0xa1);
1129  	regmap_write(rt715->regmap, RT715_SET_DMIC4_CONFIG_DEFAULT4, 0x81);
1130  
1131  	/* Finish Initial Settings, set power to D3 */
1132  	regmap_write(rt715->regmap, RT715_SET_AUDIO_POWER_STATE, AC_PWRST_D3);
1133  
1134  	if (rt715->first_hw_init)
1135  		regcache_mark_dirty(rt715->regmap);
1136  	else
1137  		rt715->first_hw_init = true;
1138  
1139  	/* Mark Slave initialization complete */
1140  	rt715->hw_init = true;
1141  
1142  	pm_runtime_mark_last_busy(&slave->dev);
1143  	pm_runtime_put_autosuspend(&slave->dev);
1144  
1145  	return 0;
1146  }
1147  
1148  MODULE_DESCRIPTION("ASoC rt715 driver");
1149  MODULE_DESCRIPTION("ASoC rt715 driver SDW");
1150  MODULE_AUTHOR("Jack Yu <jack.yu@realtek.com>");
1151  MODULE_LICENSE("GPL v2");
1152