1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * rt715-sdca.h -- RT715 ALSA SoC audio driver header 4 * 5 * Copyright(c) 2020 Realtek Semiconductor Corp. 6 */ 7 8 #ifndef __RT715_SDCA_H__ 9 #define __RT715_SDCA_H__ 10 11 #include <linux/regmap.h> 12 #include <linux/soundwire/sdw.h> 13 #include <linux/soundwire/sdw_type.h> 14 #include <sound/soc.h> 15 #include <linux/workqueue.h> 16 #include <linux/device.h> 17 18 struct rt715_sdca_priv { 19 struct regmap *regmap; 20 struct regmap *mbq_regmap; 21 struct snd_soc_codec *codec; 22 struct sdw_slave *slave; 23 struct delayed_work adc_mute_work; 24 int dbg_nid; 25 int dbg_vid; 26 int dbg_payload; 27 enum sdw_slave_status status; 28 struct sdw_bus_params params; 29 bool hw_init; 30 bool first_init; 31 int l_is_unmute; 32 int r_is_unmute; 33 int hw_sdw_ver; 34 int kctl_switch_orig[4]; 35 int kctl_2ch_orig[2]; 36 int kctl_4ch_orig[4]; 37 int kctl_8ch_orig[8]; 38 }; 39 40 struct rt715_sdw_stream_data { 41 struct sdw_stream_runtime *sdw_stream; 42 }; 43 44 struct rt715_sdca_kcontrol_private { 45 unsigned int reg_base; 46 unsigned int count; 47 unsigned int max; 48 unsigned int shift; 49 unsigned int invert; 50 }; 51 52 /* MIPI Register */ 53 #define RT715_INT_CTRL 0x005a 54 #define RT715_INT_MASK 0x005e 55 56 /* NID */ 57 #define RT715_AUDIO_FUNCTION_GROUP 0x01 58 #define RT715_MIC_ADC 0x07 59 #define RT715_LINE_ADC 0x08 60 #define RT715_MIX_ADC 0x09 61 #define RT715_DMIC1 0x12 62 #define RT715_DMIC2 0x13 63 #define RT715_MIC1 0x18 64 #define RT715_MIC2 0x19 65 #define RT715_LINE1 0x1a 66 #define RT715_LINE2 0x1b 67 #define RT715_DMIC3 0x1d 68 #define RT715_DMIC4 0x29 69 #define RT715_VENDOR_REG 0x20 70 #define RT715_MUX_IN1 0x22 71 #define RT715_MUX_IN2 0x23 72 #define RT715_MUX_IN3 0x24 73 #define RT715_MUX_IN4 0x25 74 #define RT715_MIX_ADC2 0x27 75 #define RT715_INLINE_CMD 0x55 76 #define RT715_VENDOR_HDA_CTL 0x61 77 78 /* Index (NID:20h) */ 79 #define RT715_PRODUCT_NUM 0x0 80 #define RT715_IRQ_CTRL 0x2b 81 #define RT715_AD_FUNC_EN 0x36 82 #define RT715_REV_1 0x37 83 #define RT715_SDW_INPUT_SEL 0x39 84 #define RT715_EXT_DMIC_CLK_CTRL2 0x54 85 86 /* Index (NID:61h) */ 87 #define RT715_HDA_LEGACY_MUX_CTL1 0x00 88 89 /* SDCA (Function) */ 90 #define FUN_JACK_CODEC 0x01 91 #define FUN_MIC_ARRAY 0x02 92 #define FUN_HID 0x03 93 /* SDCA (Entity) */ 94 #define RT715_SDCA_ST_EN 0x00 95 #define RT715_SDCA_CS_FREQ_IND_EN 0x01 96 #define RT715_SDCA_FU_ADC8_9_VOL 0x02 97 #define RT715_SDCA_SMPU_TRIG_ST_EN 0x05 98 #define RT715_SDCA_FU_ADC10_11_VOL 0x06 99 #define RT715_SDCA_FU_ADC7_27_VOL 0x0a 100 #define RT715_SDCA_FU_AMIC_GAIN_EN 0x0c 101 #define RT715_SDCA_FU_DMIC_GAIN_EN 0x0e 102 #define RT715_SDCA_CX_CLK_SEL_EN 0x10 103 #define RT715_SDCA_CREQ_POW_EN 0x18 104 /* SDCA (Control) */ 105 #define RT715_SDCA_ST_CTRL 0x00 106 #define RT715_SDCA_CX_CLK_SEL_CTRL 0x01 107 #define RT715_SDCA_REQ_POW_CTRL 0x01 108 #define RT715_SDCA_FU_MUTE_CTRL 0x01 109 #define RT715_SDCA_FU_VOL_CTRL 0x02 110 #define RT715_SDCA_FU_DMIC_GAIN_CTRL 0x0b 111 #define RT715_SDCA_FREQ_IND_CTRL 0x10 112 #define RT715_SDCA_SMPU_TRIG_EN_CTRL 0x10 113 #define RT715_SDCA_SMPU_TRIG_ST_CTRL 0x11 114 /* SDCA (Channel) */ 115 #define CH_00 0x00 116 #define CH_01 0x01 117 #define CH_02 0x02 118 #define CH_03 0x03 119 #define CH_04 0x04 120 #define CH_05 0x05 121 #define CH_06 0x06 122 #define CH_07 0x07 123 #define CH_08 0x08 124 125 #define RT715_SDCA_DB_STEP 375 126 127 enum { 128 RT715_AIF1, 129 RT715_AIF2, 130 }; 131 132 int rt715_sdca_io_init(struct device *dev, struct sdw_slave *slave); 133 int rt715_sdca_init(struct device *dev, struct regmap *mbq_regmap, 134 struct regmap *regmap, struct sdw_slave *slave); 135 136 #endif /* __RT715_SDCA_H__ */ 137