1 // SPDX-License-Identifier: GPL-2.0-only 2 // 3 // rt5682s.c -- RT5682I-VS ALSA SoC audio component driver 4 // 5 // Copyright 2021 Realtek Semiconductor Corp. 6 // Author: Derek Fang <derek.fang@realtek.com> 7 // 8 9 #include <linux/module.h> 10 #include <linux/moduleparam.h> 11 #include <linux/init.h> 12 #include <linux/delay.h> 13 #include <linux/pm.h> 14 #include <linux/pm_runtime.h> 15 #include <linux/i2c.h> 16 #include <linux/platform_device.h> 17 #include <linux/spi/spi.h> 18 #include <linux/acpi.h> 19 #include <linux/gpio.h> 20 #include <linux/of_gpio.h> 21 #include <linux/mutex.h> 22 #include <sound/core.h> 23 #include <sound/pcm.h> 24 #include <sound/pcm_params.h> 25 #include <sound/jack.h> 26 #include <sound/soc.h> 27 #include <sound/soc-dapm.h> 28 #include <sound/initval.h> 29 #include <sound/tlv.h> 30 #include <sound/rt5682s.h> 31 32 #include "rt5682s.h" 33 34 #define DEVICE_ID 0x6749 35 36 static const struct rt5682s_platform_data i2s_default_platform_data = { 37 .dmic1_data_pin = RT5682S_DMIC1_DATA_GPIO2, 38 .dmic1_clk_pin = RT5682S_DMIC1_CLK_GPIO3, 39 .jd_src = RT5682S_JD1, 40 .dai_clk_names[RT5682S_DAI_WCLK_IDX] = "rt5682-dai-wclk", 41 .dai_clk_names[RT5682S_DAI_BCLK_IDX] = "rt5682-dai-bclk", 42 }; 43 44 static const char *rt5682s_supply_names[RT5682S_NUM_SUPPLIES] = { 45 "AVDD", 46 "MICVDD", 47 }; 48 49 static const struct reg_sequence patch_list[] = { 50 {RT5682S_I2C_CTRL, 0x0007}, 51 {RT5682S_DIG_IN_CTRL_1, 0x0000}, 52 {RT5682S_CHOP_DAC_2, 0x2020}, 53 {RT5682S_VREF_REC_OP_FB_CAP_CTRL_2, 0x0101}, 54 {RT5682S_VREF_REC_OP_FB_CAP_CTRL_1, 0x80c0}, 55 {RT5682S_HP_CALIB_CTRL_9, 0x0002}, 56 {RT5682S_DEPOP_1, 0x0000}, 57 {RT5682S_HP_CHARGE_PUMP_2, 0x3c15}, 58 {RT5682S_DAC1_DIG_VOL, 0xfefe}, 59 {RT5682S_SAR_IL_CMD_2, 0xac00}, 60 {RT5682S_SAR_IL_CMD_3, 0x024c}, 61 {RT5682S_CBJ_CTRL_6, 0x0804}, 62 }; 63 64 static void rt5682s_apply_patch_list(struct rt5682s_priv *rt5682s, 65 struct device *dev) 66 { 67 int ret; 68 69 ret = regmap_multi_reg_write(rt5682s->regmap, patch_list, ARRAY_SIZE(patch_list)); 70 if (ret) 71 dev_warn(dev, "Failed to apply regmap patch: %d\n", ret); 72 } 73 74 static const struct reg_default rt5682s_reg[] = { 75 {0x0002, 0x8080}, 76 {0x0003, 0x0001}, 77 {0x0005, 0x0000}, 78 {0x0006, 0x0000}, 79 {0x0008, 0x8007}, 80 {0x000b, 0x0000}, 81 {0x000f, 0x4000}, 82 {0x0010, 0x4040}, 83 {0x0011, 0x0000}, 84 {0x0012, 0x0000}, 85 {0x0013, 0x1200}, 86 {0x0014, 0x200a}, 87 {0x0015, 0x0404}, 88 {0x0016, 0x0404}, 89 {0x0017, 0x05a4}, 90 {0x0019, 0xffff}, 91 {0x001c, 0x2f2f}, 92 {0x001f, 0x0000}, 93 {0x0022, 0x5757}, 94 {0x0023, 0x0039}, 95 {0x0024, 0x000b}, 96 {0x0026, 0xc0c4}, 97 {0x0029, 0x8080}, 98 {0x002a, 0xa0a0}, 99 {0x002b, 0x0300}, 100 {0x0030, 0x0000}, 101 {0x003c, 0x08c0}, 102 {0x0044, 0x1818}, 103 {0x004b, 0x00c0}, 104 {0x004c, 0x0000}, 105 {0x004d, 0x0000}, 106 {0x0061, 0x00c0}, 107 {0x0062, 0x008a}, 108 {0x0063, 0x0800}, 109 {0x0064, 0x0000}, 110 {0x0065, 0x0000}, 111 {0x0066, 0x0030}, 112 {0x0067, 0x000c}, 113 {0x0068, 0x0000}, 114 {0x0069, 0x0000}, 115 {0x006a, 0x0000}, 116 {0x006b, 0x0000}, 117 {0x006c, 0x0000}, 118 {0x006d, 0x2200}, 119 {0x006e, 0x0810}, 120 {0x006f, 0xe4de}, 121 {0x0070, 0x3320}, 122 {0x0071, 0x0000}, 123 {0x0073, 0x0000}, 124 {0x0074, 0x0000}, 125 {0x0075, 0x0002}, 126 {0x0076, 0x0001}, 127 {0x0079, 0x0000}, 128 {0x007a, 0x0000}, 129 {0x007b, 0x0000}, 130 {0x007c, 0x0100}, 131 {0x007e, 0x0000}, 132 {0x007f, 0x0000}, 133 {0x0080, 0x0000}, 134 {0x0083, 0x0000}, 135 {0x0084, 0x0000}, 136 {0x0085, 0x0000}, 137 {0x0086, 0x0005}, 138 {0x0087, 0x0000}, 139 {0x0088, 0x0000}, 140 {0x008c, 0x0003}, 141 {0x008e, 0x0060}, 142 {0x008f, 0x4da1}, 143 {0x0091, 0x1c15}, 144 {0x0092, 0x0425}, 145 {0x0093, 0x0000}, 146 {0x0094, 0x0080}, 147 {0x0095, 0x008f}, 148 {0x0096, 0x0000}, 149 {0x0097, 0x0000}, 150 {0x0098, 0x0000}, 151 {0x0099, 0x0000}, 152 {0x009a, 0x0000}, 153 {0x009b, 0x0000}, 154 {0x009c, 0x0000}, 155 {0x009d, 0x0000}, 156 {0x009e, 0x0000}, 157 {0x009f, 0x0009}, 158 {0x00a0, 0x0000}, 159 {0x00a3, 0x0002}, 160 {0x00a4, 0x0001}, 161 {0x00b6, 0x0000}, 162 {0x00b7, 0x0000}, 163 {0x00b8, 0x0000}, 164 {0x00b9, 0x0002}, 165 {0x00be, 0x0000}, 166 {0x00c0, 0x0160}, 167 {0x00c1, 0x82a0}, 168 {0x00c2, 0x0000}, 169 {0x00d0, 0x0000}, 170 {0x00d2, 0x3300}, 171 {0x00d3, 0x2200}, 172 {0x00d4, 0x0000}, 173 {0x00d9, 0x0000}, 174 {0x00da, 0x0000}, 175 {0x00db, 0x0000}, 176 {0x00dc, 0x00c0}, 177 {0x00dd, 0x2220}, 178 {0x00de, 0x3131}, 179 {0x00df, 0x3131}, 180 {0x00e0, 0x3131}, 181 {0x00e2, 0x0000}, 182 {0x00e3, 0x4000}, 183 {0x00e4, 0x0aa0}, 184 {0x00e5, 0x3131}, 185 {0x00e6, 0x3131}, 186 {0x00e7, 0x3131}, 187 {0x00e8, 0x3131}, 188 {0x00ea, 0xb320}, 189 {0x00eb, 0x0000}, 190 {0x00f0, 0x0000}, 191 {0x00f6, 0x0000}, 192 {0x00fa, 0x0000}, 193 {0x00fb, 0x0000}, 194 {0x00fc, 0x0000}, 195 {0x00fd, 0x0000}, 196 {0x00fe, 0x10ec}, 197 {0x00ff, 0x6749}, 198 {0x0100, 0xa000}, 199 {0x010b, 0x0066}, 200 {0x010c, 0x6666}, 201 {0x010d, 0x2202}, 202 {0x010e, 0x6666}, 203 {0x010f, 0xa800}, 204 {0x0110, 0x0006}, 205 {0x0111, 0x0460}, 206 {0x0112, 0x2000}, 207 {0x0113, 0x0200}, 208 {0x0117, 0x8000}, 209 {0x0118, 0x0303}, 210 {0x0125, 0x0020}, 211 {0x0132, 0x5026}, 212 {0x0136, 0x8000}, 213 {0x0139, 0x0005}, 214 {0x013a, 0x3030}, 215 {0x013b, 0xa000}, 216 {0x013c, 0x4110}, 217 {0x013f, 0x0000}, 218 {0x0145, 0x0022}, 219 {0x0146, 0x0000}, 220 {0x0147, 0x0000}, 221 {0x0148, 0x0000}, 222 {0x0156, 0x0022}, 223 {0x0157, 0x0303}, 224 {0x0158, 0x2222}, 225 {0x0159, 0x0000}, 226 {0x0160, 0x4ec0}, 227 {0x0161, 0x0080}, 228 {0x0162, 0x0200}, 229 {0x0163, 0x0800}, 230 {0x0164, 0x0000}, 231 {0x0165, 0x0000}, 232 {0x0166, 0x0000}, 233 {0x0167, 0x000f}, 234 {0x0168, 0x000f}, 235 {0x0169, 0x0001}, 236 {0x0190, 0x4131}, 237 {0x0194, 0x0000}, 238 {0x0195, 0x0000}, 239 {0x0197, 0x0022}, 240 {0x0198, 0x0000}, 241 {0x0199, 0x0000}, 242 {0x01ac, 0x0000}, 243 {0x01ad, 0x0000}, 244 {0x01ae, 0x0000}, 245 {0x01af, 0x2000}, 246 {0x01b0, 0x0000}, 247 {0x01b1, 0x0000}, 248 {0x01b2, 0x0000}, 249 {0x01b3, 0x0017}, 250 {0x01b4, 0x004b}, 251 {0x01b5, 0x0000}, 252 {0x01b6, 0x03e8}, 253 {0x01b7, 0x0000}, 254 {0x01b8, 0x0000}, 255 {0x01b9, 0x0400}, 256 {0x01ba, 0xb5b6}, 257 {0x01bb, 0x9124}, 258 {0x01bc, 0x4924}, 259 {0x01bd, 0x0009}, 260 {0x01be, 0x0018}, 261 {0x01bf, 0x002a}, 262 {0x01c0, 0x004c}, 263 {0x01c1, 0x0097}, 264 {0x01c2, 0x01c3}, 265 {0x01c3, 0x03e9}, 266 {0x01c4, 0x1389}, 267 {0x01c5, 0xc351}, 268 {0x01c6, 0x02a0}, 269 {0x01c7, 0x0b0f}, 270 {0x01c8, 0x402f}, 271 {0x01c9, 0x0702}, 272 {0x01ca, 0x0000}, 273 {0x01cb, 0x0000}, 274 {0x01cc, 0x5757}, 275 {0x01cd, 0x5757}, 276 {0x01ce, 0x5757}, 277 {0x01cf, 0x5757}, 278 {0x01d0, 0x5757}, 279 {0x01d1, 0x5757}, 280 {0x01d2, 0x5757}, 281 {0x01d3, 0x5757}, 282 {0x01d4, 0x5757}, 283 {0x01d5, 0x5757}, 284 {0x01d6, 0x0000}, 285 {0x01d7, 0x0000}, 286 {0x01d8, 0x0162}, 287 {0x01d9, 0x0007}, 288 {0x01da, 0x0000}, 289 {0x01db, 0x0004}, 290 {0x01dc, 0x0000}, 291 {0x01de, 0x7c00}, 292 {0x01df, 0x0020}, 293 {0x01e0, 0x04c1}, 294 {0x01e1, 0x0000}, 295 {0x01e2, 0x0000}, 296 {0x01e3, 0x0000}, 297 {0x01e4, 0x0000}, 298 {0x01e5, 0x0000}, 299 {0x01e6, 0x0001}, 300 {0x01e7, 0x0000}, 301 {0x01e8, 0x0000}, 302 {0x01eb, 0x0000}, 303 {0x01ec, 0x0000}, 304 {0x01ed, 0x0000}, 305 {0x01ee, 0x0000}, 306 {0x01ef, 0x0000}, 307 {0x01f0, 0x0000}, 308 {0x01f1, 0x0000}, 309 {0x01f2, 0x0000}, 310 {0x01f3, 0x0000}, 311 {0x01f4, 0x0000}, 312 {0x0210, 0x6297}, 313 {0x0211, 0xa004}, 314 {0x0212, 0x0365}, 315 {0x0213, 0xf7ff}, 316 {0x0214, 0xf24c}, 317 {0x0215, 0x0102}, 318 {0x0216, 0x00a3}, 319 {0x0217, 0x0048}, 320 {0x0218, 0xa2c0}, 321 {0x0219, 0x0400}, 322 {0x021a, 0x00c8}, 323 {0x021b, 0x00c0}, 324 {0x021c, 0x0000}, 325 {0x021d, 0x024c}, 326 {0x02fa, 0x0000}, 327 {0x02fb, 0x0000}, 328 {0x02fc, 0x0000}, 329 {0x03fe, 0x0000}, 330 {0x03ff, 0x0000}, 331 {0x0500, 0x0000}, 332 {0x0600, 0x0000}, 333 {0x0610, 0x6666}, 334 {0x0611, 0xa9aa}, 335 {0x0620, 0x6666}, 336 {0x0621, 0xa9aa}, 337 {0x0630, 0x6666}, 338 {0x0631, 0xa9aa}, 339 {0x0640, 0x6666}, 340 {0x0641, 0xa9aa}, 341 {0x07fa, 0x0000}, 342 {0x08fa, 0x0000}, 343 {0x08fb, 0x0000}, 344 {0x0d00, 0x0000}, 345 {0x1100, 0x0000}, 346 {0x1101, 0x0000}, 347 {0x1102, 0x0000}, 348 {0x1103, 0x0000}, 349 {0x1104, 0x0000}, 350 {0x1105, 0x0000}, 351 {0x1106, 0x0000}, 352 {0x1107, 0x0000}, 353 {0x1108, 0x0000}, 354 {0x1109, 0x0000}, 355 {0x110a, 0x0000}, 356 {0x110b, 0x0000}, 357 {0x110c, 0x0000}, 358 {0x1111, 0x0000}, 359 {0x1112, 0x0000}, 360 {0x1113, 0x0000}, 361 {0x1114, 0x0000}, 362 {0x1115, 0x0000}, 363 {0x1116, 0x0000}, 364 {0x1117, 0x0000}, 365 {0x1118, 0x0000}, 366 {0x1119, 0x0000}, 367 {0x111a, 0x0000}, 368 {0x111b, 0x0000}, 369 {0x111c, 0x0000}, 370 {0x1401, 0x0404}, 371 {0x1402, 0x0007}, 372 {0x1403, 0x0365}, 373 {0x1404, 0x0210}, 374 {0x1405, 0x0365}, 375 {0x1406, 0x0210}, 376 {0x1407, 0x0000}, 377 {0x1408, 0x0000}, 378 {0x1409, 0x0000}, 379 {0x140a, 0x0000}, 380 {0x140b, 0x0000}, 381 {0x140c, 0x0000}, 382 {0x140d, 0x0000}, 383 {0x140e, 0x0000}, 384 {0x140f, 0x0000}, 385 {0x1410, 0x0000}, 386 {0x1411, 0x0000}, 387 {0x1801, 0x0004}, 388 {0x1802, 0x0000}, 389 {0x1803, 0x0000}, 390 {0x1804, 0x0000}, 391 {0x1805, 0x00ff}, 392 {0x2c00, 0x0000}, 393 {0x3400, 0x0200}, 394 {0x3404, 0x0000}, 395 {0x3405, 0x0000}, 396 {0x3406, 0x0000}, 397 {0x3407, 0x0000}, 398 {0x3408, 0x0000}, 399 {0x3409, 0x0000}, 400 {0x340a, 0x0000}, 401 {0x340b, 0x0000}, 402 {0x340c, 0x0000}, 403 {0x340d, 0x0000}, 404 {0x340e, 0x0000}, 405 {0x340f, 0x0000}, 406 {0x3410, 0x0000}, 407 {0x3411, 0x0000}, 408 {0x3412, 0x0000}, 409 {0x3413, 0x0000}, 410 {0x3414, 0x0000}, 411 {0x3415, 0x0000}, 412 {0x3424, 0x0000}, 413 {0x3425, 0x0000}, 414 {0x3426, 0x0000}, 415 {0x3427, 0x0000}, 416 {0x3428, 0x0000}, 417 {0x3429, 0x0000}, 418 {0x342a, 0x0000}, 419 {0x342b, 0x0000}, 420 {0x342c, 0x0000}, 421 {0x342d, 0x0000}, 422 {0x342e, 0x0000}, 423 {0x342f, 0x0000}, 424 {0x3430, 0x0000}, 425 {0x3431, 0x0000}, 426 {0x3432, 0x0000}, 427 {0x3433, 0x0000}, 428 {0x3434, 0x0000}, 429 {0x3435, 0x0000}, 430 {0x3440, 0x6319}, 431 {0x3441, 0x3771}, 432 {0x3500, 0x0002}, 433 {0x3501, 0x5728}, 434 {0x3b00, 0x3010}, 435 {0x3b01, 0x3300}, 436 {0x3b02, 0x2200}, 437 {0x3b03, 0x0100}, 438 }; 439 440 static bool rt5682s_volatile_register(struct device *dev, unsigned int reg) 441 { 442 switch (reg) { 443 case RT5682S_RESET: 444 case RT5682S_CBJ_CTRL_2: 445 case RT5682S_I2S1_F_DIV_CTRL_2: 446 case RT5682S_I2S2_F_DIV_CTRL_2: 447 case RT5682S_INT_ST_1: 448 case RT5682S_GPIO_ST: 449 case RT5682S_IL_CMD_1: 450 case RT5682S_4BTN_IL_CMD_1: 451 case RT5682S_AJD1_CTRL: 452 case RT5682S_VERSION_ID...RT5682S_DEVICE_ID: 453 case RT5682S_STO_NG2_CTRL_1: 454 case RT5682S_STO_NG2_CTRL_5...RT5682S_STO_NG2_CTRL_7: 455 case RT5682S_STO1_DAC_SIL_DET: 456 case RT5682S_HP_IMP_SENS_CTRL_1...RT5682S_HP_IMP_SENS_CTRL_4: 457 case RT5682S_HP_IMP_SENS_CTRL_13: 458 case RT5682S_HP_IMP_SENS_CTRL_14: 459 case RT5682S_HP_IMP_SENS_CTRL_43...RT5682S_HP_IMP_SENS_CTRL_46: 460 case RT5682S_HP_CALIB_CTRL_1: 461 case RT5682S_HP_CALIB_CTRL_10: 462 case RT5682S_HP_CALIB_ST_1...RT5682S_HP_CALIB_ST_11: 463 case RT5682S_SAR_IL_CMD_2...RT5682S_SAR_IL_CMD_5: 464 case RT5682S_SAR_IL_CMD_10: 465 case RT5682S_SAR_IL_CMD_11: 466 case RT5682S_VERSION_ID_HIDE: 467 case RT5682S_VERSION_ID_CUS: 468 case RT5682S_I2C_TRANS_CTRL: 469 case RT5682S_DMIC_FLOAT_DET: 470 case RT5682S_HA_CMP_OP_1: 471 case RT5682S_NEW_CBJ_DET_CTL_10...RT5682S_NEW_CBJ_DET_CTL_16: 472 case RT5682S_CLK_SW_TEST_1: 473 case RT5682S_CLK_SW_TEST_2: 474 case RT5682S_EFUSE_READ_1...RT5682S_EFUSE_READ_18: 475 case RT5682S_PILOT_DIG_CTL_1: 476 return true; 477 default: 478 return false; 479 } 480 } 481 482 static bool rt5682s_readable_register(struct device *dev, unsigned int reg) 483 { 484 switch (reg) { 485 case RT5682S_RESET: 486 case RT5682S_VERSION_ID: 487 case RT5682S_VENDOR_ID: 488 case RT5682S_DEVICE_ID: 489 case RT5682S_HP_CTRL_1: 490 case RT5682S_HP_CTRL_2: 491 case RT5682S_HPL_GAIN: 492 case RT5682S_HPR_GAIN: 493 case RT5682S_I2C_CTRL: 494 case RT5682S_CBJ_BST_CTRL: 495 case RT5682S_CBJ_DET_CTRL: 496 case RT5682S_CBJ_CTRL_1...RT5682S_CBJ_CTRL_8: 497 case RT5682S_DAC1_DIG_VOL: 498 case RT5682S_STO1_ADC_DIG_VOL: 499 case RT5682S_STO1_ADC_BOOST: 500 case RT5682S_HP_IMP_GAIN_1: 501 case RT5682S_HP_IMP_GAIN_2: 502 case RT5682S_SIDETONE_CTRL: 503 case RT5682S_STO1_ADC_MIXER: 504 case RT5682S_AD_DA_MIXER: 505 case RT5682S_STO1_DAC_MIXER: 506 case RT5682S_A_DAC1_MUX: 507 case RT5682S_DIG_INF2_DATA: 508 case RT5682S_REC_MIXER: 509 case RT5682S_CAL_REC: 510 case RT5682S_HP_ANA_OST_CTRL_1...RT5682S_HP_ANA_OST_CTRL_3: 511 case RT5682S_PWR_DIG_1...RT5682S_PWR_MIXER: 512 case RT5682S_MB_CTRL: 513 case RT5682S_CLK_GATE_TCON_1...RT5682S_CLK_GATE_TCON_3: 514 case RT5682S_CLK_DET...RT5682S_LPF_AD_DMIC: 515 case RT5682S_I2S1_SDP: 516 case RT5682S_I2S2_SDP: 517 case RT5682S_ADDA_CLK_1: 518 case RT5682S_ADDA_CLK_2: 519 case RT5682S_I2S1_F_DIV_CTRL_1: 520 case RT5682S_I2S1_F_DIV_CTRL_2: 521 case RT5682S_TDM_CTRL: 522 case RT5682S_TDM_ADDA_CTRL_1: 523 case RT5682S_TDM_ADDA_CTRL_2: 524 case RT5682S_DATA_SEL_CTRL_1: 525 case RT5682S_TDM_TCON_CTRL_1: 526 case RT5682S_TDM_TCON_CTRL_2: 527 case RT5682S_GLB_CLK: 528 case RT5682S_PLL_TRACK_1...RT5682S_PLL_TRACK_6: 529 case RT5682S_PLL_TRACK_11: 530 case RT5682S_DEPOP_1: 531 case RT5682S_HP_CHARGE_PUMP_1: 532 case RT5682S_HP_CHARGE_PUMP_2: 533 case RT5682S_HP_CHARGE_PUMP_3: 534 case RT5682S_MICBIAS_1...RT5682S_MICBIAS_3: 535 case RT5682S_PLL_TRACK_12...RT5682S_PLL_CTRL_7: 536 case RT5682S_RC_CLK_CTRL: 537 case RT5682S_I2S2_M_CLK_CTRL_1: 538 case RT5682S_I2S2_F_DIV_CTRL_1: 539 case RT5682S_I2S2_F_DIV_CTRL_2: 540 case RT5682S_IRQ_CTRL_1...RT5682S_IRQ_CTRL_4: 541 case RT5682S_INT_ST_1: 542 case RT5682S_GPIO_CTRL_1: 543 case RT5682S_GPIO_CTRL_2: 544 case RT5682S_GPIO_ST: 545 case RT5682S_HP_AMP_DET_CTRL_1: 546 case RT5682S_MID_HP_AMP_DET: 547 case RT5682S_LOW_HP_AMP_DET: 548 case RT5682S_DELAY_BUF_CTRL: 549 case RT5682S_SV_ZCD_1: 550 case RT5682S_SV_ZCD_2: 551 case RT5682S_IL_CMD_1...RT5682S_IL_CMD_6: 552 case RT5682S_4BTN_IL_CMD_1...RT5682S_4BTN_IL_CMD_7: 553 case RT5682S_ADC_STO1_HP_CTRL_1: 554 case RT5682S_ADC_STO1_HP_CTRL_2: 555 case RT5682S_AJD1_CTRL: 556 case RT5682S_JD_CTRL_1: 557 case RT5682S_DUMMY_1...RT5682S_DUMMY_3: 558 case RT5682S_DAC_ADC_DIG_VOL1: 559 case RT5682S_BIAS_CUR_CTRL_2...RT5682S_BIAS_CUR_CTRL_10: 560 case RT5682S_VREF_REC_OP_FB_CAP_CTRL_1: 561 case RT5682S_VREF_REC_OP_FB_CAP_CTRL_2: 562 case RT5682S_CHARGE_PUMP_1: 563 case RT5682S_DIG_IN_CTRL_1: 564 case RT5682S_PAD_DRIVING_CTRL: 565 case RT5682S_CHOP_DAC_1: 566 case RT5682S_CHOP_DAC_2: 567 case RT5682S_CHOP_ADC: 568 case RT5682S_CALIB_ADC_CTRL: 569 case RT5682S_VOL_TEST: 570 case RT5682S_SPKVDD_DET_ST: 571 case RT5682S_TEST_MODE_CTRL_1...RT5682S_TEST_MODE_CTRL_4: 572 case RT5682S_PLL_INTERNAL_1...RT5682S_PLL_INTERNAL_4: 573 case RT5682S_STO_NG2_CTRL_1...RT5682S_STO_NG2_CTRL_10: 574 case RT5682S_STO1_DAC_SIL_DET: 575 case RT5682S_SIL_PSV_CTRL1: 576 case RT5682S_SIL_PSV_CTRL2: 577 case RT5682S_SIL_PSV_CTRL3: 578 case RT5682S_SIL_PSV_CTRL4: 579 case RT5682S_SIL_PSV_CTRL5: 580 case RT5682S_HP_IMP_SENS_CTRL_1...RT5682S_HP_IMP_SENS_CTRL_46: 581 case RT5682S_HP_LOGIC_CTRL_1...RT5682S_HP_LOGIC_CTRL_3: 582 case RT5682S_HP_CALIB_CTRL_1...RT5682S_HP_CALIB_CTRL_11: 583 case RT5682S_HP_CALIB_ST_1...RT5682S_HP_CALIB_ST_11: 584 case RT5682S_SAR_IL_CMD_1...RT5682S_SAR_IL_CMD_14: 585 case RT5682S_DUMMY_4...RT5682S_DUMMY_6: 586 case RT5682S_VERSION_ID_HIDE: 587 case RT5682S_VERSION_ID_CUS: 588 case RT5682S_SCAN_CTL: 589 case RT5682S_HP_AMP_DET: 590 case RT5682S_BIAS_CUR_CTRL_11: 591 case RT5682S_BIAS_CUR_CTRL_12: 592 case RT5682S_BIAS_CUR_CTRL_13: 593 case RT5682S_BIAS_CUR_CTRL_14: 594 case RT5682S_BIAS_CUR_CTRL_15: 595 case RT5682S_BIAS_CUR_CTRL_16: 596 case RT5682S_BIAS_CUR_CTRL_17: 597 case RT5682S_BIAS_CUR_CTRL_18: 598 case RT5682S_I2C_TRANS_CTRL: 599 case RT5682S_DUMMY_7: 600 case RT5682S_DUMMY_8: 601 case RT5682S_DMIC_FLOAT_DET: 602 case RT5682S_HA_CMP_OP_1...RT5682S_HA_CMP_OP_13: 603 case RT5682S_HA_CMP_OP_14...RT5682S_HA_CMP_OP_25: 604 case RT5682S_NEW_CBJ_DET_CTL_1...RT5682S_NEW_CBJ_DET_CTL_16: 605 case RT5682S_DA_FILTER_1...RT5682S_DA_FILTER_5: 606 case RT5682S_CLK_SW_TEST_1: 607 case RT5682S_CLK_SW_TEST_2: 608 case RT5682S_CLK_SW_TEST_3...RT5682S_CLK_SW_TEST_14: 609 case RT5682S_EFUSE_MANU_WRITE_1...RT5682S_EFUSE_MANU_WRITE_6: 610 case RT5682S_EFUSE_READ_1...RT5682S_EFUSE_READ_18: 611 case RT5682S_EFUSE_TIMING_CTL_1: 612 case RT5682S_EFUSE_TIMING_CTL_2: 613 case RT5682S_PILOT_DIG_CTL_1: 614 case RT5682S_PILOT_DIG_CTL_2: 615 case RT5682S_HP_AMP_DET_CTL_1...RT5682S_HP_AMP_DET_CTL_4: 616 return true; 617 default: 618 return false; 619 } 620 } 621 622 static void rt5682s_reset(struct rt5682s_priv *rt5682s) 623 { 624 regmap_write(rt5682s->regmap, RT5682S_RESET, 0); 625 } 626 627 static int rt5682s_button_detect(struct snd_soc_component *component) 628 { 629 int btn_type, val; 630 631 val = snd_soc_component_read(component, RT5682S_4BTN_IL_CMD_1); 632 btn_type = val & 0xfff0; 633 snd_soc_component_write(component, RT5682S_4BTN_IL_CMD_1, val); 634 dev_dbg(component->dev, "%s btn_type=%x\n", __func__, btn_type); 635 snd_soc_component_update_bits(component, RT5682S_SAR_IL_CMD_2, 636 RT5682S_SAR_ADC_PSV_MASK, RT5682S_SAR_ADC_PSV_ENTRY); 637 638 return btn_type; 639 } 640 641 enum { 642 SAR_PWR_OFF, 643 SAR_PWR_NORMAL, 644 SAR_PWR_SAVING, 645 }; 646 647 static void rt5682s_sar_power_mode(struct snd_soc_component *component, 648 int mode, int jd_step) 649 { 650 struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component); 651 652 mutex_lock(&rt5682s->sar_mutex); 653 654 switch (mode) { 655 case SAR_PWR_SAVING: 656 snd_soc_component_update_bits(component, RT5682S_CBJ_CTRL_3, 657 RT5682S_CBJ_IN_BUF_MASK, RT5682S_CBJ_IN_BUF_DIS); 658 snd_soc_component_update_bits(component, RT5682S_CBJ_CTRL_1, 659 RT5682S_MB1_PATH_MASK | RT5682S_MB2_PATH_MASK, 660 RT5682S_CTRL_MB1_REG | RT5682S_CTRL_MB2_REG); 661 snd_soc_component_update_bits(component, RT5682S_SAR_IL_CMD_1, 662 RT5682S_SAR_BUTDET_MASK | RT5682S_SAR_BUTDET_POW_MASK | 663 RT5682S_SAR_SEL_MB1_2_CTL_MASK, RT5682S_SAR_BUTDET_DIS | 664 RT5682S_SAR_BUTDET_POW_SAV | RT5682S_SAR_SEL_MB1_2_MANU); 665 usleep_range(5000, 5500); 666 snd_soc_component_update_bits(component, RT5682S_SAR_IL_CMD_1, 667 RT5682S_SAR_BUTDET_MASK, RT5682S_SAR_BUTDET_EN); 668 usleep_range(5000, 5500); 669 snd_soc_component_update_bits(component, RT5682S_SAR_IL_CMD_2, 670 RT5682S_SAR_ADC_PSV_MASK, RT5682S_SAR_ADC_PSV_ENTRY); 671 break; 672 case SAR_PWR_NORMAL: 673 snd_soc_component_update_bits(component, RT5682S_CBJ_CTRL_3, 674 RT5682S_CBJ_IN_BUF_MASK, RT5682S_CBJ_IN_BUF_EN); 675 snd_soc_component_update_bits(component, RT5682S_CBJ_CTRL_1, 676 RT5682S_MB1_PATH_MASK | RT5682S_MB2_PATH_MASK, 677 RT5682S_CTRL_MB1_FSM | RT5682S_CTRL_MB2_FSM); 678 if (!jd_step) { 679 snd_soc_component_update_bits(component, RT5682S_SAR_IL_CMD_1, 680 RT5682S_SAR_SEL_MB1_2_CTL_MASK, RT5682S_SAR_SEL_MB1_2_AUTO); 681 usleep_range(5000, 5500); 682 snd_soc_component_update_bits(component, RT5682S_SAR_IL_CMD_1, 683 RT5682S_SAR_BUTDET_MASK | RT5682S_SAR_BUTDET_POW_MASK, 684 RT5682S_SAR_BUTDET_EN | RT5682S_SAR_BUTDET_POW_NORM); 685 } 686 break; 687 case SAR_PWR_OFF: 688 snd_soc_component_update_bits(component, RT5682S_SAR_IL_CMD_1, 689 RT5682S_SAR_BUTDET_MASK | RT5682S_SAR_BUTDET_POW_MASK | 690 RT5682S_SAR_SEL_MB1_2_CTL_MASK, RT5682S_SAR_BUTDET_DIS | 691 RT5682S_SAR_BUTDET_POW_SAV | RT5682S_SAR_SEL_MB1_2_MANU); 692 break; 693 default: 694 dev_err(component->dev, "Invalid SAR Power mode: %d\n", mode); 695 break; 696 } 697 698 mutex_unlock(&rt5682s->sar_mutex); 699 } 700 701 static void rt5682s_enable_push_button_irq(struct snd_soc_component *component) 702 { 703 snd_soc_component_update_bits(component, RT5682S_SAR_IL_CMD_13, 704 RT5682S_SAR_SOUR_MASK, RT5682S_SAR_SOUR_BTN); 705 snd_soc_component_write(component, RT5682S_IL_CMD_1, 0x0040); 706 snd_soc_component_update_bits(component, RT5682S_4BTN_IL_CMD_2, 707 RT5682S_4BTN_IL_MASK | RT5682S_4BTN_IL_RST_MASK, 708 RT5682S_4BTN_IL_EN | RT5682S_4BTN_IL_NOR); 709 snd_soc_component_update_bits(component, RT5682S_IRQ_CTRL_3, 710 RT5682S_IL_IRQ_MASK, RT5682S_IL_IRQ_EN); 711 } 712 713 static void rt5682s_disable_push_button_irq(struct snd_soc_component *component) 714 { 715 snd_soc_component_update_bits(component, RT5682S_IRQ_CTRL_3, 716 RT5682S_IL_IRQ_MASK, RT5682S_IL_IRQ_DIS); 717 snd_soc_component_update_bits(component, RT5682S_4BTN_IL_CMD_2, 718 RT5682S_4BTN_IL_MASK, RT5682S_4BTN_IL_DIS); 719 snd_soc_component_update_bits(component, RT5682S_SAR_IL_CMD_13, 720 RT5682S_SAR_SOUR_MASK, RT5682S_SAR_SOUR_TYPE); 721 } 722 723 /** 724 * rt5682s_headset_detect - Detect headset. 725 * @component: SoC audio component device. 726 * @jack_insert: Jack insert or not. 727 * 728 * Detect whether is headset or not when jack inserted. 729 * 730 * Returns detect status. 731 */ 732 static int rt5682s_headset_detect(struct snd_soc_component *component, int jack_insert) 733 { 734 unsigned int val, count; 735 int jack_type = 0; 736 737 if (jack_insert) { 738 rt5682s_disable_push_button_irq(component); 739 snd_soc_component_update_bits(component, RT5682S_PWR_ANLG_1, 740 RT5682S_PWR_VREF1 | RT5682S_PWR_VREF2 | RT5682S_PWR_MB, 741 RT5682S_PWR_VREF1 | RT5682S_PWR_VREF2 | RT5682S_PWR_MB); 742 snd_soc_component_update_bits(component, RT5682S_PWR_ANLG_1, 743 RT5682S_PWR_FV1 | RT5682S_PWR_FV2, 0); 744 usleep_range(15000, 20000); 745 snd_soc_component_update_bits(component, RT5682S_PWR_ANLG_1, 746 RT5682S_PWR_FV1 | RT5682S_PWR_FV2, 747 RT5682S_PWR_FV1 | RT5682S_PWR_FV2); 748 snd_soc_component_update_bits(component, RT5682S_PWR_ANLG_3, 749 RT5682S_PWR_CBJ, RT5682S_PWR_CBJ); 750 snd_soc_component_write(component, RT5682S_SAR_IL_CMD_3, 0x0365); 751 snd_soc_component_update_bits(component, RT5682S_HP_CHARGE_PUMP_2, 752 RT5682S_OSW_L_MASK | RT5682S_OSW_R_MASK, 753 RT5682S_OSW_L_DIS | RT5682S_OSW_R_DIS); 754 snd_soc_component_update_bits(component, RT5682S_SAR_IL_CMD_13, 755 RT5682S_SAR_SOUR_MASK, RT5682S_SAR_SOUR_TYPE); 756 rt5682s_sar_power_mode(component, SAR_PWR_NORMAL, 1); 757 snd_soc_component_update_bits(component, RT5682S_CBJ_CTRL_1, 758 RT5682S_TRIG_JD_MASK, RT5682S_TRIG_JD_LOW); 759 usleep_range(45000, 50000); 760 snd_soc_component_update_bits(component, RT5682S_CBJ_CTRL_1, 761 RT5682S_TRIG_JD_MASK, RT5682S_TRIG_JD_HIGH); 762 763 count = 0; 764 do { 765 usleep_range(10000, 15000); 766 val = snd_soc_component_read(component, RT5682S_CBJ_CTRL_2) 767 & RT5682S_JACK_TYPE_MASK; 768 count++; 769 } while (val == 0 && count < 50); 770 771 dev_dbg(component->dev, "%s, val=%d, count=%d\n", __func__, val, count); 772 773 switch (val) { 774 case 0x1: 775 case 0x2: 776 jack_type = SND_JACK_HEADSET; 777 snd_soc_component_write(component, RT5682S_SAR_IL_CMD_3, 0x024c); 778 snd_soc_component_update_bits(component, RT5682S_CBJ_CTRL_1, 779 RT5682S_FAST_OFF_MASK, RT5682S_FAST_OFF_EN); 780 snd_soc_component_update_bits(component, RT5682S_SAR_IL_CMD_1, 781 RT5682S_SAR_SEL_MB1_2_MASK, val << RT5682S_SAR_SEL_MB1_2_SFT); 782 if (!snd_soc_dapm_get_pin_status(&component->dapm, "SAR")) 783 rt5682s_sar_power_mode(component, SAR_PWR_SAVING, 1); 784 rt5682s_enable_push_button_irq(component); 785 break; 786 default: 787 jack_type = SND_JACK_HEADPHONE; 788 break; 789 } 790 snd_soc_component_update_bits(component, RT5682S_HP_CHARGE_PUMP_2, 791 RT5682S_OSW_L_MASK | RT5682S_OSW_R_MASK, 792 RT5682S_OSW_L_EN | RT5682S_OSW_R_EN); 793 usleep_range(35000, 40000); 794 } else { 795 rt5682s_sar_power_mode(component, SAR_PWR_OFF, 1); 796 rt5682s_disable_push_button_irq(component); 797 snd_soc_component_update_bits(component, RT5682S_CBJ_CTRL_1, 798 RT5682S_TRIG_JD_MASK, RT5682S_TRIG_JD_LOW); 799 800 if (!snd_soc_dapm_get_pin_status(&component->dapm, "MICBIAS")) 801 snd_soc_component_update_bits(component, 802 RT5682S_PWR_ANLG_1, RT5682S_PWR_MB, 0); 803 if (!snd_soc_dapm_get_pin_status(&component->dapm, "Vref2")) 804 snd_soc_component_update_bits(component, 805 RT5682S_PWR_ANLG_1, RT5682S_PWR_VREF2, 0); 806 807 snd_soc_component_update_bits(component, RT5682S_PWR_ANLG_3, 808 RT5682S_PWR_CBJ, 0); 809 snd_soc_component_update_bits(component, RT5682S_CBJ_CTRL_1, 810 RT5682S_FAST_OFF_MASK, RT5682S_FAST_OFF_DIS); 811 snd_soc_component_update_bits(component, RT5682S_CBJ_CTRL_3, 812 RT5682S_CBJ_IN_BUF_MASK, RT5682S_CBJ_IN_BUF_DIS); 813 jack_type = 0; 814 } 815 816 dev_dbg(component->dev, "jack_type = %d\n", jack_type); 817 818 return jack_type; 819 } 820 821 static void rt5682s_jack_detect_handler(struct work_struct *work) 822 { 823 struct rt5682s_priv *rt5682s = 824 container_of(work, struct rt5682s_priv, jack_detect_work.work); 825 int val, btn_type; 826 827 while (!rt5682s->component) 828 usleep_range(10000, 15000); 829 830 while (!rt5682s->component->card->instantiated) 831 usleep_range(10000, 15000); 832 833 mutex_lock(&rt5682s->jdet_mutex); 834 mutex_lock(&rt5682s->calibrate_mutex); 835 836 val = snd_soc_component_read(rt5682s->component, RT5682S_AJD1_CTRL) 837 & RT5682S_JDH_RS_MASK; 838 if (!val) { 839 /* jack in */ 840 if (rt5682s->jack_type == 0) { 841 /* jack was out, report jack type */ 842 rt5682s->jack_type = rt5682s_headset_detect(rt5682s->component, 1); 843 rt5682s->irq_work_delay_time = 0; 844 } else if ((rt5682s->jack_type & SND_JACK_HEADSET) == SND_JACK_HEADSET) { 845 /* jack is already in, report button event */ 846 rt5682s->jack_type = SND_JACK_HEADSET; 847 btn_type = rt5682s_button_detect(rt5682s->component); 848 /** 849 * rt5682s can report three kinds of button behavior, 850 * one click, double click and hold. However, 851 * currently we will report button pressed/released 852 * event. So all the three button behaviors are 853 * treated as button pressed. 854 */ 855 switch (btn_type) { 856 case 0x8000: 857 case 0x4000: 858 case 0x2000: 859 rt5682s->jack_type |= SND_JACK_BTN_0; 860 break; 861 case 0x1000: 862 case 0x0800: 863 case 0x0400: 864 rt5682s->jack_type |= SND_JACK_BTN_1; 865 break; 866 case 0x0200: 867 case 0x0100: 868 case 0x0080: 869 rt5682s->jack_type |= SND_JACK_BTN_2; 870 break; 871 case 0x0040: 872 case 0x0020: 873 case 0x0010: 874 rt5682s->jack_type |= SND_JACK_BTN_3; 875 break; 876 case 0x0000: /* unpressed */ 877 break; 878 default: 879 dev_err(rt5682s->component->dev, 880 "Unexpected button code 0x%04x\n", btn_type); 881 break; 882 } 883 } 884 } else { 885 /* jack out */ 886 rt5682s->jack_type = rt5682s_headset_detect(rt5682s->component, 0); 887 rt5682s->irq_work_delay_time = 50; 888 } 889 890 snd_soc_jack_report(rt5682s->hs_jack, rt5682s->jack_type, 891 SND_JACK_HEADSET | SND_JACK_BTN_0 | SND_JACK_BTN_1 | 892 SND_JACK_BTN_2 | SND_JACK_BTN_3); 893 894 if (rt5682s->jack_type & (SND_JACK_BTN_0 | SND_JACK_BTN_1 | 895 SND_JACK_BTN_2 | SND_JACK_BTN_3)) 896 schedule_delayed_work(&rt5682s->jd_check_work, 0); 897 else 898 cancel_delayed_work_sync(&rt5682s->jd_check_work); 899 900 mutex_unlock(&rt5682s->calibrate_mutex); 901 mutex_unlock(&rt5682s->jdet_mutex); 902 } 903 904 static void rt5682s_jd_check_handler(struct work_struct *work) 905 { 906 struct rt5682s_priv *rt5682s = 907 container_of(work, struct rt5682s_priv, jd_check_work.work); 908 909 if (snd_soc_component_read(rt5682s->component, RT5682S_AJD1_CTRL) 910 & RT5682S_JDH_RS_MASK) { 911 /* jack out */ 912 rt5682s->jack_type = rt5682s_headset_detect(rt5682s->component, 0); 913 914 snd_soc_jack_report(rt5682s->hs_jack, rt5682s->jack_type, 915 SND_JACK_HEADSET | SND_JACK_BTN_0 | SND_JACK_BTN_1 | 916 SND_JACK_BTN_2 | SND_JACK_BTN_3); 917 } else { 918 schedule_delayed_work(&rt5682s->jd_check_work, 500); 919 } 920 } 921 922 static irqreturn_t rt5682s_irq(int irq, void *data) 923 { 924 struct rt5682s_priv *rt5682s = data; 925 926 mod_delayed_work(system_power_efficient_wq, &rt5682s->jack_detect_work, 927 msecs_to_jiffies(rt5682s->irq_work_delay_time)); 928 929 return IRQ_HANDLED; 930 } 931 932 static int rt5682s_set_jack_detect(struct snd_soc_component *component, 933 struct snd_soc_jack *hs_jack, void *data) 934 { 935 struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component); 936 int btndet_delay = 16; 937 938 rt5682s->hs_jack = hs_jack; 939 940 if (!hs_jack) { 941 regmap_update_bits(rt5682s->regmap, RT5682S_IRQ_CTRL_2, 942 RT5682S_JD1_EN_MASK, RT5682S_JD1_DIS); 943 regmap_update_bits(rt5682s->regmap, RT5682S_RC_CLK_CTRL, 944 RT5682S_POW_JDH, 0); 945 cancel_delayed_work_sync(&rt5682s->jack_detect_work); 946 947 return 0; 948 } 949 950 switch (rt5682s->pdata.jd_src) { 951 case RT5682S_JD1: 952 regmap_update_bits(rt5682s->regmap, RT5682S_CBJ_CTRL_5, 953 RT5682S_JD_FAST_OFF_SRC_MASK, RT5682S_JD_FAST_OFF_SRC_JDH); 954 regmap_update_bits(rt5682s->regmap, RT5682S_CBJ_CTRL_2, 955 RT5682S_EXT_JD_SRC, RT5682S_EXT_JD_SRC_MANUAL); 956 regmap_update_bits(rt5682s->regmap, RT5682S_CBJ_CTRL_1, 957 RT5682S_EMB_JD_MASK | RT5682S_DET_TYPE | 958 RT5682S_POL_FAST_OFF_MASK | RT5682S_MIC_CAP_MASK, 959 RT5682S_EMB_JD_EN | RT5682S_DET_TYPE | 960 RT5682S_POL_FAST_OFF_HIGH | RT5682S_MIC_CAP_HS); 961 regmap_update_bits(rt5682s->regmap, RT5682S_SAR_IL_CMD_1, 962 RT5682S_SAR_POW_MASK, RT5682S_SAR_POW_EN); 963 regmap_update_bits(rt5682s->regmap, RT5682S_GPIO_CTRL_1, 964 RT5682S_GP1_PIN_MASK, RT5682S_GP1_PIN_IRQ); 965 regmap_update_bits(rt5682s->regmap, RT5682S_PWR_ANLG_3, 966 RT5682S_PWR_BGLDO, RT5682S_PWR_BGLDO); 967 regmap_update_bits(rt5682s->regmap, RT5682S_PWR_ANLG_2, 968 RT5682S_PWR_JD_MASK, RT5682S_PWR_JD_ENABLE); 969 regmap_update_bits(rt5682s->regmap, RT5682S_RC_CLK_CTRL, 970 RT5682S_POW_IRQ | RT5682S_POW_JDH, RT5682S_POW_IRQ | RT5682S_POW_JDH); 971 regmap_update_bits(rt5682s->regmap, RT5682S_IRQ_CTRL_2, 972 RT5682S_JD1_EN_MASK | RT5682S_JD1_POL_MASK, 973 RT5682S_JD1_EN | RT5682S_JD1_POL_NOR); 974 regmap_update_bits(rt5682s->regmap, RT5682S_4BTN_IL_CMD_4, 975 RT5682S_4BTN_IL_HOLD_WIN_MASK | RT5682S_4BTN_IL_CLICK_WIN_MASK, 976 (btndet_delay << RT5682S_4BTN_IL_HOLD_WIN_SFT | btndet_delay)); 977 regmap_update_bits(rt5682s->regmap, RT5682S_4BTN_IL_CMD_5, 978 RT5682S_4BTN_IL_HOLD_WIN_MASK | RT5682S_4BTN_IL_CLICK_WIN_MASK, 979 (btndet_delay << RT5682S_4BTN_IL_HOLD_WIN_SFT | btndet_delay)); 980 regmap_update_bits(rt5682s->regmap, RT5682S_4BTN_IL_CMD_6, 981 RT5682S_4BTN_IL_HOLD_WIN_MASK | RT5682S_4BTN_IL_CLICK_WIN_MASK, 982 (btndet_delay << RT5682S_4BTN_IL_HOLD_WIN_SFT | btndet_delay)); 983 regmap_update_bits(rt5682s->regmap, RT5682S_4BTN_IL_CMD_7, 984 RT5682S_4BTN_IL_HOLD_WIN_MASK | RT5682S_4BTN_IL_CLICK_WIN_MASK, 985 (btndet_delay << RT5682S_4BTN_IL_HOLD_WIN_SFT | btndet_delay)); 986 987 mod_delayed_work(system_power_efficient_wq, 988 &rt5682s->jack_detect_work, msecs_to_jiffies(250)); 989 break; 990 991 case RT5682S_JD_NULL: 992 regmap_update_bits(rt5682s->regmap, RT5682S_IRQ_CTRL_2, 993 RT5682S_JD1_EN_MASK, RT5682S_JD1_DIS); 994 regmap_update_bits(rt5682s->regmap, RT5682S_RC_CLK_CTRL, 995 RT5682S_POW_JDH, 0); 996 break; 997 998 default: 999 dev_warn(component->dev, "Wrong JD source\n"); 1000 break; 1001 } 1002 1003 return 0; 1004 } 1005 1006 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -9562, 75, 0); 1007 static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0); 1008 static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0); 1009 static const DECLARE_TLV_DB_SCALE(cbj_bst_tlv, -1200, 150, 0); 1010 1011 static const struct snd_kcontrol_new rt5682s_snd_controls[] = { 1012 /* DAC Digital Volume */ 1013 SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5682S_DAC1_DIG_VOL, 1014 RT5682S_L_VOL_SFT + 1, RT5682S_R_VOL_SFT + 1, 127, 0, dac_vol_tlv), 1015 1016 /* CBJ Boost Volume */ 1017 SOC_SINGLE_TLV("CBJ Boost Volume", RT5682S_REC_MIXER, 1018 RT5682S_BST_CBJ_SFT, 35, 0, cbj_bst_tlv), 1019 1020 /* ADC Digital Volume Control */ 1021 SOC_DOUBLE("STO1 ADC Capture Switch", RT5682S_STO1_ADC_DIG_VOL, 1022 RT5682S_L_MUTE_SFT, RT5682S_R_MUTE_SFT, 1, 1), 1023 SOC_DOUBLE_TLV("STO1 ADC Capture Volume", RT5682S_STO1_ADC_DIG_VOL, 1024 RT5682S_L_VOL_SFT + 1, RT5682S_R_VOL_SFT + 1, 63, 0, adc_vol_tlv), 1025 1026 /* ADC Boost Volume Control */ 1027 SOC_DOUBLE_TLV("STO1 ADC Boost Gain Volume", RT5682S_STO1_ADC_BOOST, 1028 RT5682S_STO1_ADC_L_BST_SFT, RT5682S_STO1_ADC_R_BST_SFT, 3, 0, adc_bst_tlv), 1029 }; 1030 1031 /** 1032 * rt5682s_sel_asrc_clk_src - select ASRC clock source for a set of filters 1033 * @component: SoC audio component device. 1034 * @filter_mask: mask of filters. 1035 * @clk_src: clock source 1036 * 1037 * The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5682S can 1038 * only support standard 32fs or 64fs i2s format, ASRC should be enabled to 1039 * support special i2s clock format such as Intel's 100fs(100 * sampling rate). 1040 * ASRC function will track i2s clock and generate a corresponding system clock 1041 * for codec. This function provides an API to select the clock source for a 1042 * set of filters specified by the mask. And the component driver will turn on 1043 * ASRC for these filters if ASRC is selected as their clock source. 1044 */ 1045 int rt5682s_sel_asrc_clk_src(struct snd_soc_component *component, 1046 unsigned int filter_mask, unsigned int clk_src) 1047 { 1048 switch (clk_src) { 1049 case RT5682S_CLK_SEL_SYS: 1050 case RT5682S_CLK_SEL_I2S1_ASRC: 1051 case RT5682S_CLK_SEL_I2S2_ASRC: 1052 break; 1053 1054 default: 1055 return -EINVAL; 1056 } 1057 1058 if (filter_mask & RT5682S_DA_STEREO1_FILTER) { 1059 snd_soc_component_update_bits(component, RT5682S_PLL_TRACK_2, 1060 RT5682S_FILTER_CLK_SEL_MASK, clk_src << RT5682S_FILTER_CLK_SEL_SFT); 1061 } 1062 1063 if (filter_mask & RT5682S_AD_STEREO1_FILTER) { 1064 snd_soc_component_update_bits(component, RT5682S_PLL_TRACK_3, 1065 RT5682S_FILTER_CLK_SEL_MASK, clk_src << RT5682S_FILTER_CLK_SEL_SFT); 1066 } 1067 1068 snd_soc_component_update_bits(component, RT5682S_PLL_TRACK_11, 1069 RT5682S_ASRCIN_AUTO_CLKOUT_MASK, RT5682S_ASRCIN_AUTO_CLKOUT_EN); 1070 1071 return 0; 1072 } 1073 EXPORT_SYMBOL_GPL(rt5682s_sel_asrc_clk_src); 1074 1075 static int rt5682s_div_sel(struct rt5682s_priv *rt5682s, 1076 int target, const int div[], int size) 1077 { 1078 int i; 1079 1080 if (rt5682s->sysclk < target) { 1081 dev_err(rt5682s->component->dev, 1082 "sysclk rate %d is too low\n", rt5682s->sysclk); 1083 return 0; 1084 } 1085 1086 for (i = 0; i < size - 1; i++) { 1087 dev_dbg(rt5682s->component->dev, "div[%d]=%d\n", i, div[i]); 1088 if (target * div[i] == rt5682s->sysclk) 1089 return i; 1090 if (target * div[i + 1] > rt5682s->sysclk) { 1091 dev_dbg(rt5682s->component->dev, 1092 "can't find div for sysclk %d\n", rt5682s->sysclk); 1093 return i; 1094 } 1095 } 1096 1097 if (target * div[i] < rt5682s->sysclk) 1098 dev_err(rt5682s->component->dev, 1099 "sysclk rate %d is too high\n", rt5682s->sysclk); 1100 1101 return size - 1; 1102 } 1103 1104 static int get_clk_info(int sclk, int rate) 1105 { 1106 int i; 1107 static const int pd[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32, 48}; 1108 1109 if (sclk <= 0 || rate <= 0) 1110 return -EINVAL; 1111 1112 rate = rate << 8; 1113 for (i = 0; i < ARRAY_SIZE(pd); i++) 1114 if (sclk == rate * pd[i]) 1115 return i; 1116 1117 return -EINVAL; 1118 } 1119 1120 /** 1121 * set_dmic_clk - Set parameter of dmic. 1122 * 1123 * @w: DAPM widget. 1124 * @kcontrol: The kcontrol of this widget. 1125 * @event: Event id. 1126 * 1127 * Choose dmic clock between 1MHz and 3MHz. 1128 * It is better for clock to approximate 3MHz. 1129 */ 1130 static int set_dmic_clk(struct snd_soc_dapm_widget *w, 1131 struct snd_kcontrol *kcontrol, int event) 1132 { 1133 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1134 struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component); 1135 int idx, dmic_clk_rate = 3072000; 1136 static const int div[] = {2, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, 128}; 1137 1138 if (rt5682s->pdata.dmic_clk_rate) 1139 dmic_clk_rate = rt5682s->pdata.dmic_clk_rate; 1140 1141 idx = rt5682s_div_sel(rt5682s, dmic_clk_rate, div, ARRAY_SIZE(div)); 1142 1143 snd_soc_component_update_bits(component, RT5682S_DMIC_CTRL_1, 1144 RT5682S_DMIC_CLK_MASK, idx << RT5682S_DMIC_CLK_SFT); 1145 1146 return 0; 1147 } 1148 1149 static int set_filter_clk(struct snd_soc_dapm_widget *w, 1150 struct snd_kcontrol *kcontrol, int event) 1151 { 1152 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1153 struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component); 1154 int ref, val, reg, idx; 1155 static const int div_f[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32, 48}; 1156 static const int div_o[] = {1, 2, 4, 6, 8, 12, 16, 24, 32, 48}; 1157 1158 val = snd_soc_component_read(component, RT5682S_GPIO_CTRL_1) 1159 & RT5682S_GP4_PIN_MASK; 1160 1161 if (w->shift == RT5682S_PWR_ADC_S1F_BIT && val == RT5682S_GP4_PIN_ADCDAT2) 1162 ref = 256 * rt5682s->lrck[RT5682S_AIF2]; 1163 else 1164 ref = 256 * rt5682s->lrck[RT5682S_AIF1]; 1165 1166 idx = rt5682s_div_sel(rt5682s, ref, div_f, ARRAY_SIZE(div_f)); 1167 1168 if (w->shift == RT5682S_PWR_ADC_S1F_BIT) 1169 reg = RT5682S_PLL_TRACK_3; 1170 else 1171 reg = RT5682S_PLL_TRACK_2; 1172 1173 snd_soc_component_update_bits(component, reg, 1174 RT5682S_FILTER_CLK_DIV_MASK, idx << RT5682S_FILTER_CLK_DIV_SFT); 1175 1176 /* select over sample rate */ 1177 for (idx = 0; idx < ARRAY_SIZE(div_o); idx++) { 1178 if (rt5682s->sysclk <= 12288000 * div_o[idx]) 1179 break; 1180 } 1181 1182 snd_soc_component_update_bits(component, RT5682S_ADDA_CLK_1, 1183 RT5682S_ADC_OSR_MASK | RT5682S_DAC_OSR_MASK, 1184 (idx << RT5682S_ADC_OSR_SFT) | (idx << RT5682S_DAC_OSR_SFT)); 1185 1186 return 0; 1187 } 1188 1189 static int set_dmic_power(struct snd_soc_dapm_widget *w, 1190 struct snd_kcontrol *kcontrol, int event) 1191 { 1192 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1193 struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component); 1194 unsigned int delay = 50, val; 1195 1196 if (rt5682s->pdata.dmic_delay) 1197 delay = rt5682s->pdata.dmic_delay; 1198 1199 switch (event) { 1200 case SND_SOC_DAPM_POST_PMU: 1201 val = (snd_soc_component_read(component, RT5682S_GLB_CLK) 1202 & RT5682S_SCLK_SRC_MASK) >> RT5682S_SCLK_SRC_SFT; 1203 if (val == RT5682S_CLK_SRC_PLL1 || val == RT5682S_CLK_SRC_PLL2) 1204 snd_soc_component_update_bits(component, RT5682S_PWR_ANLG_1, 1205 RT5682S_PWR_VREF2 | RT5682S_PWR_MB, 1206 RT5682S_PWR_VREF2 | RT5682S_PWR_MB); 1207 1208 /*Add delay to avoid pop noise*/ 1209 msleep(delay); 1210 break; 1211 1212 case SND_SOC_DAPM_POST_PMD: 1213 if (!rt5682s->jack_type) { 1214 if (!snd_soc_dapm_get_pin_status(w->dapm, "MICBIAS")) 1215 snd_soc_component_update_bits(component, 1216 RT5682S_PWR_ANLG_1, RT5682S_PWR_MB, 0); 1217 if (!snd_soc_dapm_get_pin_status(w->dapm, "Vref2")) 1218 snd_soc_component_update_bits(component, 1219 RT5682S_PWR_ANLG_1, RT5682S_PWR_VREF2, 0); 1220 } 1221 break; 1222 } 1223 1224 return 0; 1225 } 1226 1227 static int set_i2s_clk(struct snd_soc_dapm_widget *w, 1228 struct snd_kcontrol *kcontrol, int event) 1229 { 1230 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1231 struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component); 1232 int pre_div, id; 1233 unsigned int reg, mask, sft; 1234 1235 if (event != SND_SOC_DAPM_PRE_PMU) 1236 return 0; 1237 1238 if (w->shift == RT5682S_PWR_I2S2_BIT) { 1239 id = RT5682S_AIF2; 1240 reg = RT5682S_I2S2_M_CLK_CTRL_1; 1241 mask = RT5682S_I2S2_M_D_MASK; 1242 sft = RT5682S_I2S2_M_D_SFT; 1243 } else { 1244 id = RT5682S_AIF1; 1245 reg = RT5682S_ADDA_CLK_1; 1246 mask = RT5682S_I2S_M_D_MASK; 1247 sft = RT5682S_I2S_M_D_SFT; 1248 } 1249 1250 if (!rt5682s->master[id]) 1251 return 0; 1252 1253 pre_div = get_clk_info(rt5682s->sysclk, rt5682s->lrck[id]); 1254 if (pre_div < 0) { 1255 dev_err(component->dev, "get pre_div failed\n"); 1256 return -EINVAL; 1257 } 1258 1259 dev_dbg(component->dev, "lrck is %dHz and pre_div is %d for iis %d master\n", 1260 rt5682s->lrck[id], pre_div, id); 1261 snd_soc_component_update_bits(component, reg, mask, pre_div << sft); 1262 1263 return 0; 1264 } 1265 1266 static int is_sys_clk_from_plla(struct snd_soc_dapm_widget *w, 1267 struct snd_soc_dapm_widget *sink) 1268 { 1269 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1270 struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component); 1271 1272 if ((rt5682s->sysclk_src == RT5682S_CLK_SRC_PLL1) || 1273 (rt5682s->sysclk_src == RT5682S_CLK_SRC_PLL2 && rt5682s->pll_comb == USE_PLLAB)) 1274 return 1; 1275 1276 return 0; 1277 } 1278 1279 static int is_sys_clk_from_pllb(struct snd_soc_dapm_widget *w, 1280 struct snd_soc_dapm_widget *sink) 1281 { 1282 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1283 struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component); 1284 1285 if (rt5682s->sysclk_src == RT5682S_CLK_SRC_PLL2) 1286 return 1; 1287 1288 return 0; 1289 } 1290 1291 static int is_using_asrc(struct snd_soc_dapm_widget *w, 1292 struct snd_soc_dapm_widget *sink) 1293 { 1294 unsigned int reg, sft, val; 1295 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1296 1297 switch (w->shift) { 1298 case RT5682S_ADC_STO1_ASRC_SFT: 1299 reg = RT5682S_PLL_TRACK_3; 1300 sft = RT5682S_FILTER_CLK_SEL_SFT; 1301 break; 1302 case RT5682S_DAC_STO1_ASRC_SFT: 1303 reg = RT5682S_PLL_TRACK_2; 1304 sft = RT5682S_FILTER_CLK_SEL_SFT; 1305 break; 1306 default: 1307 return 0; 1308 } 1309 1310 val = (snd_soc_component_read(component, reg) >> sft) & 0xf; 1311 switch (val) { 1312 case RT5682S_CLK_SEL_I2S1_ASRC: 1313 case RT5682S_CLK_SEL_I2S2_ASRC: 1314 return 1; 1315 default: 1316 return 0; 1317 } 1318 } 1319 1320 static int rt5682s_hp_amp_event(struct snd_soc_dapm_widget *w, 1321 struct snd_kcontrol *kcontrol, int event) 1322 { 1323 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1324 struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component); 1325 1326 switch (event) { 1327 case SND_SOC_DAPM_POST_PMU: 1328 snd_soc_component_update_bits(component, RT5682S_DEPOP_1, 1329 RT5682S_OUT_HP_L_EN | RT5682S_OUT_HP_R_EN, 1330 RT5682S_OUT_HP_L_EN | RT5682S_OUT_HP_R_EN); 1331 usleep_range(15000, 20000); 1332 snd_soc_component_update_bits(component, RT5682S_DEPOP_1, 1333 RT5682S_LDO_PUMP_EN | RT5682S_PUMP_EN | 1334 RT5682S_CAPLESS_L_EN | RT5682S_CAPLESS_R_EN, 1335 RT5682S_LDO_PUMP_EN | RT5682S_PUMP_EN | 1336 RT5682S_CAPLESS_L_EN | RT5682S_CAPLESS_R_EN); 1337 snd_soc_component_write(component, RT5682S_BIAS_CUR_CTRL_11, 0x6666); 1338 snd_soc_component_write(component, RT5682S_BIAS_CUR_CTRL_12, 0xa82a); 1339 1340 mutex_lock(&rt5682s->jdet_mutex); 1341 1342 snd_soc_component_update_bits(component, RT5682S_HP_CTRL_2, 1343 RT5682S_HPO_L_PATH_MASK | RT5682S_HPO_R_PATH_MASK | 1344 RT5682S_HPO_SEL_IP_EN_SW, RT5682S_HPO_L_PATH_EN | 1345 RT5682S_HPO_R_PATH_EN | RT5682S_HPO_IP_EN_GATING); 1346 usleep_range(5000, 10000); 1347 snd_soc_component_update_bits(component, RT5682S_HP_AMP_DET_CTL_1, 1348 RT5682S_CP_SW_SIZE_MASK, RT5682S_CP_SW_SIZE_L | RT5682S_CP_SW_SIZE_S); 1349 1350 mutex_unlock(&rt5682s->jdet_mutex); 1351 break; 1352 1353 case SND_SOC_DAPM_POST_PMD: 1354 snd_soc_component_update_bits(component, RT5682S_HP_CTRL_2, 1355 RT5682S_HPO_L_PATH_MASK | RT5682S_HPO_R_PATH_MASK | 1356 RT5682S_HPO_SEL_IP_EN_SW, 0); 1357 snd_soc_component_update_bits(component, RT5682S_HP_AMP_DET_CTL_1, 1358 RT5682S_CP_SW_SIZE_MASK, RT5682S_CP_SW_SIZE_M); 1359 snd_soc_component_update_bits(component, RT5682S_DEPOP_1, 1360 RT5682S_LDO_PUMP_EN | RT5682S_PUMP_EN | 1361 RT5682S_CAPLESS_L_EN | RT5682S_CAPLESS_R_EN, 0); 1362 snd_soc_component_update_bits(component, RT5682S_DEPOP_1, 1363 RT5682S_OUT_HP_L_EN | RT5682S_OUT_HP_R_EN, 0); 1364 break; 1365 } 1366 1367 return 0; 1368 } 1369 1370 static int sar_power_event(struct snd_soc_dapm_widget *w, 1371 struct snd_kcontrol *kcontrol, int event) 1372 { 1373 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1374 struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component); 1375 1376 if ((rt5682s->jack_type & SND_JACK_HEADSET) != SND_JACK_HEADSET) 1377 return 0; 1378 1379 switch (event) { 1380 case SND_SOC_DAPM_PRE_PMU: 1381 rt5682s_sar_power_mode(component, SAR_PWR_NORMAL, 0); 1382 break; 1383 case SND_SOC_DAPM_POST_PMD: 1384 rt5682s_sar_power_mode(component, SAR_PWR_SAVING, 0); 1385 break; 1386 } 1387 1388 return 0; 1389 } 1390 1391 /* Interface data select */ 1392 static const char * const rt5682s_data_select[] = { 1393 "L/R", "R/L", "L/L", "R/R" 1394 }; 1395 1396 static SOC_ENUM_SINGLE_DECL(rt5682s_if2_adc_enum, RT5682S_DIG_INF2_DATA, 1397 RT5682S_IF2_ADC_SEL_SFT, rt5682s_data_select); 1398 1399 static SOC_ENUM_SINGLE_DECL(rt5682s_if1_01_adc_enum, RT5682S_TDM_ADDA_CTRL_1, 1400 RT5682S_IF1_ADC1_SEL_SFT, rt5682s_data_select); 1401 1402 static SOC_ENUM_SINGLE_DECL(rt5682s_if1_23_adc_enum, RT5682S_TDM_ADDA_CTRL_1, 1403 RT5682S_IF1_ADC2_SEL_SFT, rt5682s_data_select); 1404 1405 static SOC_ENUM_SINGLE_DECL(rt5682s_if1_45_adc_enum, RT5682S_TDM_ADDA_CTRL_1, 1406 RT5682S_IF1_ADC3_SEL_SFT, rt5682s_data_select); 1407 1408 static SOC_ENUM_SINGLE_DECL(rt5682s_if1_67_adc_enum, RT5682S_TDM_ADDA_CTRL_1, 1409 RT5682S_IF1_ADC4_SEL_SFT, rt5682s_data_select); 1410 1411 static const struct snd_kcontrol_new rt5682s_if2_adc_swap_mux = 1412 SOC_DAPM_ENUM("IF2 ADC Swap Mux", rt5682s_if2_adc_enum); 1413 1414 static const struct snd_kcontrol_new rt5682s_if1_01_adc_swap_mux = 1415 SOC_DAPM_ENUM("IF1 01 ADC Swap Mux", rt5682s_if1_01_adc_enum); 1416 1417 static const struct snd_kcontrol_new rt5682s_if1_23_adc_swap_mux = 1418 SOC_DAPM_ENUM("IF1 23 ADC Swap Mux", rt5682s_if1_23_adc_enum); 1419 1420 static const struct snd_kcontrol_new rt5682s_if1_45_adc_swap_mux = 1421 SOC_DAPM_ENUM("IF1 45 ADC Swap Mux", rt5682s_if1_45_adc_enum); 1422 1423 static const struct snd_kcontrol_new rt5682s_if1_67_adc_swap_mux = 1424 SOC_DAPM_ENUM("IF1 67 ADC Swap Mux", rt5682s_if1_67_adc_enum); 1425 1426 /* Digital Mixer */ 1427 static const struct snd_kcontrol_new rt5682s_sto1_adc_l_mix[] = { 1428 SOC_DAPM_SINGLE("ADC1 Switch", RT5682S_STO1_ADC_MIXER, 1429 RT5682S_M_STO1_ADC_L1_SFT, 1, 1), 1430 SOC_DAPM_SINGLE("ADC2 Switch", RT5682S_STO1_ADC_MIXER, 1431 RT5682S_M_STO1_ADC_L2_SFT, 1, 1), 1432 }; 1433 1434 static const struct snd_kcontrol_new rt5682s_sto1_adc_r_mix[] = { 1435 SOC_DAPM_SINGLE("ADC1 Switch", RT5682S_STO1_ADC_MIXER, 1436 RT5682S_M_STO1_ADC_R1_SFT, 1, 1), 1437 SOC_DAPM_SINGLE("ADC2 Switch", RT5682S_STO1_ADC_MIXER, 1438 RT5682S_M_STO1_ADC_R2_SFT, 1, 1), 1439 }; 1440 1441 static const struct snd_kcontrol_new rt5682s_dac_l_mix[] = { 1442 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5682S_AD_DA_MIXER, 1443 RT5682S_M_ADCMIX_L_SFT, 1, 1), 1444 SOC_DAPM_SINGLE("DAC1 Switch", RT5682S_AD_DA_MIXER, 1445 RT5682S_M_DAC1_L_SFT, 1, 1), 1446 }; 1447 1448 static const struct snd_kcontrol_new rt5682s_dac_r_mix[] = { 1449 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5682S_AD_DA_MIXER, 1450 RT5682S_M_ADCMIX_R_SFT, 1, 1), 1451 SOC_DAPM_SINGLE("DAC1 Switch", RT5682S_AD_DA_MIXER, 1452 RT5682S_M_DAC1_R_SFT, 1, 1), 1453 }; 1454 1455 static const struct snd_kcontrol_new rt5682s_sto1_dac_l_mix[] = { 1456 SOC_DAPM_SINGLE("DAC L1 Switch", RT5682S_STO1_DAC_MIXER, 1457 RT5682S_M_DAC_L1_STO_L_SFT, 1, 1), 1458 SOC_DAPM_SINGLE("DAC R1 Switch", RT5682S_STO1_DAC_MIXER, 1459 RT5682S_M_DAC_R1_STO_L_SFT, 1, 1), 1460 }; 1461 1462 static const struct snd_kcontrol_new rt5682s_sto1_dac_r_mix[] = { 1463 SOC_DAPM_SINGLE("DAC L1 Switch", RT5682S_STO1_DAC_MIXER, 1464 RT5682S_M_DAC_L1_STO_R_SFT, 1, 1), 1465 SOC_DAPM_SINGLE("DAC R1 Switch", RT5682S_STO1_DAC_MIXER, 1466 RT5682S_M_DAC_R1_STO_R_SFT, 1, 1), 1467 }; 1468 1469 /* Analog Input Mixer */ 1470 static const struct snd_kcontrol_new rt5682s_rec1_l_mix[] = { 1471 SOC_DAPM_SINGLE("CBJ Switch", RT5682S_REC_MIXER, 1472 RT5682S_M_CBJ_RM1_L_SFT, 1, 1), 1473 }; 1474 1475 static const struct snd_kcontrol_new rt5682s_rec1_r_mix[] = { 1476 SOC_DAPM_SINGLE("CBJ Switch", RT5682S_REC_MIXER, 1477 RT5682S_M_CBJ_RM1_R_SFT, 1, 1), 1478 }; 1479 1480 /* STO1 ADC1 Source */ 1481 /* MX-26 [13] [5] */ 1482 static const char * const rt5682s_sto1_adc1_src[] = { 1483 "DAC MIX", "ADC" 1484 }; 1485 1486 static SOC_ENUM_SINGLE_DECL(rt5682s_sto1_adc1l_enum, RT5682S_STO1_ADC_MIXER, 1487 RT5682S_STO1_ADC1L_SRC_SFT, rt5682s_sto1_adc1_src); 1488 1489 static const struct snd_kcontrol_new rt5682s_sto1_adc1l_mux = 1490 SOC_DAPM_ENUM("Stereo1 ADC1L Source", rt5682s_sto1_adc1l_enum); 1491 1492 static SOC_ENUM_SINGLE_DECL(rt5682s_sto1_adc1r_enum, RT5682S_STO1_ADC_MIXER, 1493 RT5682S_STO1_ADC1R_SRC_SFT, rt5682s_sto1_adc1_src); 1494 1495 static const struct snd_kcontrol_new rt5682s_sto1_adc1r_mux = 1496 SOC_DAPM_ENUM("Stereo1 ADC1L Source", rt5682s_sto1_adc1r_enum); 1497 1498 /* STO1 ADC Source */ 1499 /* MX-26 [11:10] [3:2] */ 1500 static const char * const rt5682s_sto1_adc_src[] = { 1501 "ADC1 L", "ADC1 R" 1502 }; 1503 1504 static SOC_ENUM_SINGLE_DECL(rt5682s_sto1_adcl_enum, RT5682S_STO1_ADC_MIXER, 1505 RT5682S_STO1_ADCL_SRC_SFT, rt5682s_sto1_adc_src); 1506 1507 static const struct snd_kcontrol_new rt5682s_sto1_adcl_mux = 1508 SOC_DAPM_ENUM("Stereo1 ADCL Source", rt5682s_sto1_adcl_enum); 1509 1510 static SOC_ENUM_SINGLE_DECL(rt5682s_sto1_adcr_enum, RT5682S_STO1_ADC_MIXER, 1511 RT5682S_STO1_ADCR_SRC_SFT, rt5682s_sto1_adc_src); 1512 1513 static const struct snd_kcontrol_new rt5682s_sto1_adcr_mux = 1514 SOC_DAPM_ENUM("Stereo1 ADCR Source", rt5682s_sto1_adcr_enum); 1515 1516 /* STO1 ADC2 Source */ 1517 /* MX-26 [12] [4] */ 1518 static const char * const rt5682s_sto1_adc2_src[] = { 1519 "DAC MIX", "DMIC" 1520 }; 1521 1522 static SOC_ENUM_SINGLE_DECL(rt5682s_sto1_adc2l_enum, RT5682S_STO1_ADC_MIXER, 1523 RT5682S_STO1_ADC2L_SRC_SFT, rt5682s_sto1_adc2_src); 1524 1525 static const struct snd_kcontrol_new rt5682s_sto1_adc2l_mux = 1526 SOC_DAPM_ENUM("Stereo1 ADC2L Source", rt5682s_sto1_adc2l_enum); 1527 1528 static SOC_ENUM_SINGLE_DECL(rt5682s_sto1_adc2r_enum, RT5682S_STO1_ADC_MIXER, 1529 RT5682S_STO1_ADC2R_SRC_SFT, rt5682s_sto1_adc2_src); 1530 1531 static const struct snd_kcontrol_new rt5682s_sto1_adc2r_mux = 1532 SOC_DAPM_ENUM("Stereo1 ADC2R Source", rt5682s_sto1_adc2r_enum); 1533 1534 /* MX-79 [6:4] I2S1 ADC data location */ 1535 static const unsigned int rt5682s_if1_adc_slot_values[] = { 1536 0, 2, 4, 6, 1537 }; 1538 1539 static const char * const rt5682s_if1_adc_slot_src[] = { 1540 "Slot 0", "Slot 2", "Slot 4", "Slot 6" 1541 }; 1542 1543 static SOC_VALUE_ENUM_SINGLE_DECL(rt5682s_if1_adc_slot_enum, 1544 RT5682S_TDM_CTRL, RT5682S_TDM_ADC_LCA_SFT, RT5682S_TDM_ADC_LCA_MASK, 1545 rt5682s_if1_adc_slot_src, rt5682s_if1_adc_slot_values); 1546 1547 static const struct snd_kcontrol_new rt5682s_if1_adc_slot_mux = 1548 SOC_DAPM_ENUM("IF1 ADC Slot location", rt5682s_if1_adc_slot_enum); 1549 1550 /* Analog DAC L1 Source, Analog DAC R1 Source*/ 1551 /* MX-2B [4], MX-2B [0]*/ 1552 static const char * const rt5682s_alg_dac1_src[] = { 1553 "Stereo1 DAC Mixer", "DAC1" 1554 }; 1555 1556 static SOC_ENUM_SINGLE_DECL(rt5682s_alg_dac_l1_enum, RT5682S_A_DAC1_MUX, 1557 RT5682S_A_DACL1_SFT, rt5682s_alg_dac1_src); 1558 1559 static const struct snd_kcontrol_new rt5682s_alg_dac_l1_mux = 1560 SOC_DAPM_ENUM("Analog DAC L1 Source", rt5682s_alg_dac_l1_enum); 1561 1562 static SOC_ENUM_SINGLE_DECL(rt5682s_alg_dac_r1_enum, RT5682S_A_DAC1_MUX, 1563 RT5682S_A_DACR1_SFT, rt5682s_alg_dac1_src); 1564 1565 static const struct snd_kcontrol_new rt5682s_alg_dac_r1_mux = 1566 SOC_DAPM_ENUM("Analog DAC R1 Source", rt5682s_alg_dac_r1_enum); 1567 1568 static const unsigned int rt5682s_adcdat_pin_values[] = { 1569 1, 3, 1570 }; 1571 1572 static const char * const rt5682s_adcdat_pin_select[] = { 1573 "ADCDAT1", "ADCDAT2", 1574 }; 1575 1576 static SOC_VALUE_ENUM_SINGLE_DECL(rt5682s_adcdat_pin_enum, 1577 RT5682S_GPIO_CTRL_1, RT5682S_GP4_PIN_SFT, RT5682S_GP4_PIN_MASK, 1578 rt5682s_adcdat_pin_select, rt5682s_adcdat_pin_values); 1579 1580 static const struct snd_kcontrol_new rt5682s_adcdat_pin_ctrl = 1581 SOC_DAPM_ENUM("ADCDAT", rt5682s_adcdat_pin_enum); 1582 1583 static const struct snd_soc_dapm_widget rt5682s_dapm_widgets[] = { 1584 SND_SOC_DAPM_SUPPLY("LDO MB1", RT5682S_PWR_ANLG_3, 1585 RT5682S_PWR_LDO_MB1_BIT, 0, NULL, 0), 1586 SND_SOC_DAPM_SUPPLY("LDO MB2", RT5682S_PWR_ANLG_3, 1587 RT5682S_PWR_LDO_MB2_BIT, 0, NULL, 0), 1588 SND_SOC_DAPM_SUPPLY("LDO", RT5682S_PWR_ANLG_3, 1589 RT5682S_PWR_LDO_BIT, 0, NULL, 0), 1590 SND_SOC_DAPM_SUPPLY("Vref2", SND_SOC_NOPM, 0, 0, NULL, 0), 1591 SND_SOC_DAPM_SUPPLY("MICBIAS", SND_SOC_NOPM, 0, 0, NULL, 0), 1592 1593 /* PLL Powers */ 1594 SND_SOC_DAPM_SUPPLY_S("PLLA_LDO", 0, RT5682S_PWR_ANLG_3, 1595 RT5682S_PWR_LDO_PLLA_BIT, 0, NULL, 0), 1596 SND_SOC_DAPM_SUPPLY_S("PLLB_LDO", 0, RT5682S_PWR_ANLG_3, 1597 RT5682S_PWR_LDO_PLLB_BIT, 0, NULL, 0), 1598 SND_SOC_DAPM_SUPPLY_S("PLLA_BIAS", 0, RT5682S_PWR_ANLG_3, 1599 RT5682S_PWR_BIAS_PLLA_BIT, 0, NULL, 0), 1600 SND_SOC_DAPM_SUPPLY_S("PLLB_BIAS", 0, RT5682S_PWR_ANLG_3, 1601 RT5682S_PWR_BIAS_PLLB_BIT, 0, NULL, 0), 1602 SND_SOC_DAPM_SUPPLY_S("PLLA", 0, RT5682S_PWR_ANLG_3, 1603 RT5682S_PWR_PLLA_BIT, 0, NULL, 0), 1604 SND_SOC_DAPM_SUPPLY_S("PLLB", 0, RT5682S_PWR_ANLG_3, 1605 RT5682S_PWR_PLLB_BIT, 0, set_filter_clk, SND_SOC_DAPM_PRE_PMU), 1606 SND_SOC_DAPM_SUPPLY_S("PLLA_RST", 1, RT5682S_PWR_ANLG_3, 1607 RT5682S_RSTB_PLLA_BIT, 0, NULL, 0), 1608 SND_SOC_DAPM_SUPPLY_S("PLLB_RST", 1, RT5682S_PWR_ANLG_3, 1609 RT5682S_RSTB_PLLB_BIT, 0, NULL, 0), 1610 1611 /* ASRC */ 1612 SND_SOC_DAPM_SUPPLY_S("DAC STO1 ASRC", 1, RT5682S_PLL_TRACK_1, 1613 RT5682S_DAC_STO1_ASRC_SFT, 0, NULL, 0), 1614 SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5682S_PLL_TRACK_1, 1615 RT5682S_ADC_STO1_ASRC_SFT, 0, NULL, 0), 1616 SND_SOC_DAPM_SUPPLY_S("AD ASRC", 1, RT5682S_PLL_TRACK_1, 1617 RT5682S_AD_ASRC_SFT, 0, NULL, 0), 1618 SND_SOC_DAPM_SUPPLY_S("DA ASRC", 1, RT5682S_PLL_TRACK_1, 1619 RT5682S_DA_ASRC_SFT, 0, NULL, 0), 1620 SND_SOC_DAPM_SUPPLY_S("DMIC ASRC", 1, RT5682S_PLL_TRACK_1, 1621 RT5682S_DMIC_ASRC_SFT, 0, NULL, 0), 1622 1623 /* Input Side */ 1624 SND_SOC_DAPM_SUPPLY("MICBIAS1", RT5682S_PWR_ANLG_2, 1625 RT5682S_PWR_MB1_BIT, 0, NULL, 0), 1626 SND_SOC_DAPM_SUPPLY("MICBIAS2", RT5682S_PWR_ANLG_2, 1627 RT5682S_PWR_MB2_BIT, 0, NULL, 0), 1628 1629 /* Input Lines */ 1630 SND_SOC_DAPM_INPUT("DMIC L1"), 1631 SND_SOC_DAPM_INPUT("DMIC R1"), 1632 1633 SND_SOC_DAPM_INPUT("IN1P"), 1634 1635 SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0, 1636 set_dmic_clk, SND_SOC_DAPM_PRE_PMU), 1637 SND_SOC_DAPM_SUPPLY("DMIC1 Power", RT5682S_DMIC_CTRL_1, RT5682S_DMIC_1_EN_SFT, 0, 1638 set_dmic_power, SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 1639 1640 /* Boost */ 1641 SND_SOC_DAPM_PGA("BST1 CBJ", SND_SOC_NOPM, 0, 0, NULL, 0), 1642 1643 /* REC Mixer */ 1644 SND_SOC_DAPM_MIXER("RECMIX1L", SND_SOC_NOPM, 0, 0, rt5682s_rec1_l_mix, 1645 ARRAY_SIZE(rt5682s_rec1_l_mix)), 1646 SND_SOC_DAPM_MIXER("RECMIX1R", SND_SOC_NOPM, 0, 0, rt5682s_rec1_r_mix, 1647 ARRAY_SIZE(rt5682s_rec1_r_mix)), 1648 SND_SOC_DAPM_SUPPLY("RECMIX1L Power", RT5682S_CAL_REC, 1649 RT5682S_PWR_RM1_L_BIT, 0, NULL, 0), 1650 SND_SOC_DAPM_SUPPLY("RECMIX1R Power", RT5682S_CAL_REC, 1651 RT5682S_PWR_RM1_R_BIT, 0, NULL, 0), 1652 1653 /* ADCs */ 1654 SND_SOC_DAPM_ADC("ADC1 L", NULL, SND_SOC_NOPM, 0, 0), 1655 SND_SOC_DAPM_ADC("ADC1 R", NULL, SND_SOC_NOPM, 0, 0), 1656 1657 SND_SOC_DAPM_SUPPLY("ADC1 L Power", RT5682S_PWR_DIG_1, 1658 RT5682S_PWR_ADC_L1_BIT, 0, NULL, 0), 1659 SND_SOC_DAPM_SUPPLY("ADC1 R Power", RT5682S_PWR_DIG_1, 1660 RT5682S_PWR_ADC_R1_BIT, 0, NULL, 0), 1661 SND_SOC_DAPM_SUPPLY("ADC1 clock", RT5682S_CHOP_ADC, 1662 RT5682S_CKGEN_ADC1_SFT, 0, NULL, 0), 1663 1664 /* ADC Mux */ 1665 SND_SOC_DAPM_MUX("Stereo1 ADC L1 Mux", SND_SOC_NOPM, 0, 0, 1666 &rt5682s_sto1_adc1l_mux), 1667 SND_SOC_DAPM_MUX("Stereo1 ADC R1 Mux", SND_SOC_NOPM, 0, 0, 1668 &rt5682s_sto1_adc1r_mux), 1669 SND_SOC_DAPM_MUX("Stereo1 ADC L2 Mux", SND_SOC_NOPM, 0, 0, 1670 &rt5682s_sto1_adc2l_mux), 1671 SND_SOC_DAPM_MUX("Stereo1 ADC R2 Mux", SND_SOC_NOPM, 0, 0, 1672 &rt5682s_sto1_adc2r_mux), 1673 SND_SOC_DAPM_MUX("Stereo1 ADC L Mux", SND_SOC_NOPM, 0, 0, 1674 &rt5682s_sto1_adcl_mux), 1675 SND_SOC_DAPM_MUX("Stereo1 ADC R Mux", SND_SOC_NOPM, 0, 0, 1676 &rt5682s_sto1_adcr_mux), 1677 SND_SOC_DAPM_MUX("IF1_ADC Mux", SND_SOC_NOPM, 0, 0, 1678 &rt5682s_if1_adc_slot_mux), 1679 1680 /* ADC Mixer */ 1681 SND_SOC_DAPM_SUPPLY("ADC Stereo1 Filter", RT5682S_PWR_DIG_2, 1682 RT5682S_PWR_ADC_S1F_BIT, 0, set_filter_clk, SND_SOC_DAPM_PRE_PMU), 1683 SND_SOC_DAPM_MIXER("Stereo1 ADC MIXL", RT5682S_STO1_ADC_DIG_VOL, 1684 RT5682S_L_MUTE_SFT, 1, rt5682s_sto1_adc_l_mix, 1685 ARRAY_SIZE(rt5682s_sto1_adc_l_mix)), 1686 SND_SOC_DAPM_MIXER("Stereo1 ADC MIXR", RT5682S_STO1_ADC_DIG_VOL, 1687 RT5682S_R_MUTE_SFT, 1, rt5682s_sto1_adc_r_mix, 1688 ARRAY_SIZE(rt5682s_sto1_adc_r_mix)), 1689 1690 /* ADC PGA */ 1691 SND_SOC_DAPM_PGA("Stereo1 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 1692 1693 /* Digital Interface */ 1694 SND_SOC_DAPM_SUPPLY("I2S1", RT5682S_PWR_DIG_1, RT5682S_PWR_I2S1_BIT, 1695 0, set_i2s_clk, SND_SOC_DAPM_PRE_PMU), 1696 SND_SOC_DAPM_SUPPLY("I2S2", RT5682S_PWR_DIG_1, RT5682S_PWR_I2S2_BIT, 1697 0, set_i2s_clk, SND_SOC_DAPM_PRE_PMU), 1698 SND_SOC_DAPM_PGA("IF1 DAC1 L", SND_SOC_NOPM, 0, 0, NULL, 0), 1699 SND_SOC_DAPM_PGA("IF1 DAC1 R", SND_SOC_NOPM, 0, 0, NULL, 0), 1700 1701 /* Digital Interface Select */ 1702 SND_SOC_DAPM_MUX("IF1 01 ADC Swap Mux", SND_SOC_NOPM, 0, 0, 1703 &rt5682s_if1_01_adc_swap_mux), 1704 SND_SOC_DAPM_MUX("IF1 23 ADC Swap Mux", SND_SOC_NOPM, 0, 0, 1705 &rt5682s_if1_23_adc_swap_mux), 1706 SND_SOC_DAPM_MUX("IF1 45 ADC Swap Mux", SND_SOC_NOPM, 0, 0, 1707 &rt5682s_if1_45_adc_swap_mux), 1708 SND_SOC_DAPM_MUX("IF1 67 ADC Swap Mux", SND_SOC_NOPM, 0, 0, 1709 &rt5682s_if1_67_adc_swap_mux), 1710 SND_SOC_DAPM_MUX("IF2 ADC Swap Mux", SND_SOC_NOPM, 0, 0, 1711 &rt5682s_if2_adc_swap_mux), 1712 1713 SND_SOC_DAPM_MUX("ADCDAT Mux", SND_SOC_NOPM, 0, 0, &rt5682s_adcdat_pin_ctrl), 1714 1715 /* Audio Interface */ 1716 SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, RT5682S_I2S1_SDP, 1717 RT5682S_SEL_ADCDAT_SFT, 1), 1718 SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, RT5682S_I2S2_SDP, 1719 RT5682S_I2S2_PIN_CFG_SFT, 1), 1720 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0), 1721 1722 /* Output Side */ 1723 /* DAC mixer before sound effect */ 1724 SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0, 1725 rt5682s_dac_l_mix, ARRAY_SIZE(rt5682s_dac_l_mix)), 1726 SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0, 1727 rt5682s_dac_r_mix, ARRAY_SIZE(rt5682s_dac_r_mix)), 1728 1729 /* DAC channel Mux */ 1730 SND_SOC_DAPM_MUX("DAC L1 Source", SND_SOC_NOPM, 0, 0, &rt5682s_alg_dac_l1_mux), 1731 SND_SOC_DAPM_MUX("DAC R1 Source", SND_SOC_NOPM, 0, 0, &rt5682s_alg_dac_r1_mux), 1732 1733 /* DAC Mixer */ 1734 SND_SOC_DAPM_SUPPLY("DAC Stereo1 Filter", RT5682S_PWR_DIG_2, 1735 RT5682S_PWR_DAC_S1F_BIT, 0, set_filter_clk, SND_SOC_DAPM_PRE_PMU), 1736 SND_SOC_DAPM_MIXER("Stereo1 DAC MIXL", SND_SOC_NOPM, 0, 0, 1737 rt5682s_sto1_dac_l_mix, ARRAY_SIZE(rt5682s_sto1_dac_l_mix)), 1738 SND_SOC_DAPM_MIXER("Stereo1 DAC MIXR", SND_SOC_NOPM, 0, 0, 1739 rt5682s_sto1_dac_r_mix, ARRAY_SIZE(rt5682s_sto1_dac_r_mix)), 1740 1741 /* DACs */ 1742 SND_SOC_DAPM_DAC("DAC L1", NULL, RT5682S_PWR_DIG_1, RT5682S_PWR_DAC_L1_BIT, 0), 1743 SND_SOC_DAPM_DAC("DAC R1", NULL, RT5682S_PWR_DIG_1, RT5682S_PWR_DAC_R1_BIT, 0), 1744 1745 /* HPO */ 1746 SND_SOC_DAPM_PGA_S("HP Amp", 1, SND_SOC_NOPM, 0, 0, rt5682s_hp_amp_event, 1747 SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_POST_PMU), 1748 1749 /* CLK DET */ 1750 SND_SOC_DAPM_SUPPLY("CLKDET SYS", RT5682S_CLK_DET, 1751 RT5682S_SYS_CLK_DET_SFT, 0, NULL, 0), 1752 SND_SOC_DAPM_SUPPLY("CLKDET PLL1", RT5682S_CLK_DET, 1753 RT5682S_PLL1_CLK_DET_SFT, 0, NULL, 0), 1754 SND_SOC_DAPM_SUPPLY("MCLK0 DET PWR", RT5682S_PWR_ANLG_2, 1755 RT5682S_PWR_MCLK0_WD_BIT, 0, NULL, 0), 1756 1757 /* SAR */ 1758 SND_SOC_DAPM_SUPPLY("SAR", SND_SOC_NOPM, 0, 0, sar_power_event, 1759 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 1760 1761 /* Output Lines */ 1762 SND_SOC_DAPM_OUTPUT("HPOL"), 1763 SND_SOC_DAPM_OUTPUT("HPOR"), 1764 }; 1765 1766 static const struct snd_soc_dapm_route rt5682s_dapm_routes[] = { 1767 /*PLL*/ 1768 {"ADC Stereo1 Filter", NULL, "PLLA", is_sys_clk_from_plla}, 1769 {"ADC Stereo1 Filter", NULL, "PLLB", is_sys_clk_from_pllb}, 1770 {"DAC Stereo1 Filter", NULL, "PLLA", is_sys_clk_from_plla}, 1771 {"DAC Stereo1 Filter", NULL, "PLLB", is_sys_clk_from_pllb}, 1772 {"PLLA", NULL, "PLLA_LDO"}, 1773 {"PLLA", NULL, "PLLA_BIAS"}, 1774 {"PLLA", NULL, "PLLA_RST"}, 1775 {"PLLB", NULL, "PLLB_LDO"}, 1776 {"PLLB", NULL, "PLLB_BIAS"}, 1777 {"PLLB", NULL, "PLLB_RST"}, 1778 1779 /*ASRC*/ 1780 {"ADC Stereo1 Filter", NULL, "ADC STO1 ASRC", is_using_asrc}, 1781 {"DAC Stereo1 Filter", NULL, "DAC STO1 ASRC", is_using_asrc}, 1782 {"ADC STO1 ASRC", NULL, "AD ASRC"}, 1783 {"ADC STO1 ASRC", NULL, "DA ASRC"}, 1784 {"DAC STO1 ASRC", NULL, "AD ASRC"}, 1785 {"DAC STO1 ASRC", NULL, "DA ASRC"}, 1786 1787 {"CLKDET SYS", NULL, "MCLK0 DET PWR"}, 1788 1789 {"BST1 CBJ", NULL, "IN1P"}, 1790 {"BST1 CBJ", NULL, "SAR"}, 1791 1792 {"RECMIX1L", "CBJ Switch", "BST1 CBJ"}, 1793 {"RECMIX1L", NULL, "RECMIX1L Power"}, 1794 {"RECMIX1R", "CBJ Switch", "BST1 CBJ"}, 1795 {"RECMIX1R", NULL, "RECMIX1R Power"}, 1796 1797 {"ADC1 L", NULL, "RECMIX1L"}, 1798 {"ADC1 L", NULL, "ADC1 L Power"}, 1799 {"ADC1 L", NULL, "ADC1 clock"}, 1800 {"ADC1 R", NULL, "RECMIX1R"}, 1801 {"ADC1 R", NULL, "ADC1 R Power"}, 1802 {"ADC1 R", NULL, "ADC1 clock"}, 1803 1804 {"DMIC L1", NULL, "DMIC CLK"}, 1805 {"DMIC L1", NULL, "DMIC1 Power"}, 1806 {"DMIC R1", NULL, "DMIC CLK"}, 1807 {"DMIC R1", NULL, "DMIC1 Power"}, 1808 {"DMIC CLK", NULL, "DMIC ASRC"}, 1809 1810 {"Stereo1 ADC L Mux", "ADC1 L", "ADC1 L"}, 1811 {"Stereo1 ADC L Mux", "ADC1 R", "ADC1 R"}, 1812 {"Stereo1 ADC R Mux", "ADC1 L", "ADC1 L"}, 1813 {"Stereo1 ADC R Mux", "ADC1 R", "ADC1 R"}, 1814 1815 {"Stereo1 ADC L1 Mux", "ADC", "Stereo1 ADC L Mux"}, 1816 {"Stereo1 ADC L1 Mux", "DAC MIX", "Stereo1 DAC MIXL"}, 1817 {"Stereo1 ADC L2 Mux", "DMIC", "DMIC L1"}, 1818 {"Stereo1 ADC L2 Mux", "DAC MIX", "Stereo1 DAC MIXL"}, 1819 1820 {"Stereo1 ADC R1 Mux", "ADC", "Stereo1 ADC R Mux"}, 1821 {"Stereo1 ADC R1 Mux", "DAC MIX", "Stereo1 DAC MIXR"}, 1822 {"Stereo1 ADC R2 Mux", "DMIC", "DMIC R1"}, 1823 {"Stereo1 ADC R2 Mux", "DAC MIX", "Stereo1 DAC MIXR"}, 1824 1825 {"Stereo1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC L1 Mux"}, 1826 {"Stereo1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC L2 Mux"}, 1827 {"Stereo1 ADC MIXL", NULL, "ADC Stereo1 Filter"}, 1828 1829 {"Stereo1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC R1 Mux"}, 1830 {"Stereo1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC R2 Mux"}, 1831 {"Stereo1 ADC MIXR", NULL, "ADC Stereo1 Filter"}, 1832 1833 {"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXL"}, 1834 {"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXR"}, 1835 1836 {"IF1 01 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"}, 1837 {"IF1 01 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"}, 1838 {"IF1 01 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"}, 1839 {"IF1 01 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"}, 1840 {"IF1 23 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"}, 1841 {"IF1 23 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"}, 1842 {"IF1 23 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"}, 1843 {"IF1 23 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"}, 1844 {"IF1 45 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"}, 1845 {"IF1 45 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"}, 1846 {"IF1 45 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"}, 1847 {"IF1 45 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"}, 1848 {"IF1 67 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"}, 1849 {"IF1 67 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"}, 1850 {"IF1 67 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"}, 1851 {"IF1 67 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"}, 1852 1853 {"IF1_ADC Mux", "Slot 0", "IF1 01 ADC Swap Mux"}, 1854 {"IF1_ADC Mux", "Slot 2", "IF1 23 ADC Swap Mux"}, 1855 {"IF1_ADC Mux", "Slot 4", "IF1 45 ADC Swap Mux"}, 1856 {"IF1_ADC Mux", "Slot 6", "IF1 67 ADC Swap Mux"}, 1857 {"ADCDAT Mux", "ADCDAT1", "IF1_ADC Mux"}, 1858 {"AIF1TX", NULL, "I2S1"}, 1859 {"AIF1TX", NULL, "ADCDAT Mux"}, 1860 {"IF2 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"}, 1861 {"IF2 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"}, 1862 {"IF2 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"}, 1863 {"IF2 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"}, 1864 {"ADCDAT Mux", "ADCDAT2", "IF2 ADC Swap Mux"}, 1865 {"AIF2TX", NULL, "ADCDAT Mux"}, 1866 1867 {"IF1 DAC1 L", NULL, "AIF1RX"}, 1868 {"IF1 DAC1 L", NULL, "I2S1"}, 1869 {"IF1 DAC1 L", NULL, "DAC Stereo1 Filter"}, 1870 {"IF1 DAC1 R", NULL, "AIF1RX"}, 1871 {"IF1 DAC1 R", NULL, "I2S1"}, 1872 {"IF1 DAC1 R", NULL, "DAC Stereo1 Filter"}, 1873 1874 {"DAC1 MIXL", "Stereo ADC Switch", "Stereo1 ADC MIXL"}, 1875 {"DAC1 MIXL", "DAC1 Switch", "IF1 DAC1 L"}, 1876 {"DAC1 MIXR", "Stereo ADC Switch", "Stereo1 ADC MIXR"}, 1877 {"DAC1 MIXR", "DAC1 Switch", "IF1 DAC1 R"}, 1878 1879 {"Stereo1 DAC MIXL", "DAC L1 Switch", "DAC1 MIXL"}, 1880 {"Stereo1 DAC MIXL", "DAC R1 Switch", "DAC1 MIXR"}, 1881 1882 {"Stereo1 DAC MIXR", "DAC R1 Switch", "DAC1 MIXR"}, 1883 {"Stereo1 DAC MIXR", "DAC L1 Switch", "DAC1 MIXL"}, 1884 1885 {"DAC L1 Source", "DAC1", "DAC1 MIXL"}, 1886 {"DAC L1 Source", "Stereo1 DAC Mixer", "Stereo1 DAC MIXL"}, 1887 {"DAC R1 Source", "DAC1", "DAC1 MIXR"}, 1888 {"DAC R1 Source", "Stereo1 DAC Mixer", "Stereo1 DAC MIXR"}, 1889 1890 {"DAC L1", NULL, "DAC L1 Source"}, 1891 {"DAC R1", NULL, "DAC R1 Source"}, 1892 1893 {"HP Amp", NULL, "DAC L1"}, 1894 {"HP Amp", NULL, "DAC R1"}, 1895 {"HP Amp", NULL, "CLKDET SYS"}, 1896 {"HP Amp", NULL, "SAR"}, 1897 1898 {"HPOL", NULL, "HP Amp"}, 1899 {"HPOR", NULL, "HP Amp"}, 1900 }; 1901 1902 static int rt5682s_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask, 1903 unsigned int rx_mask, int slots, int slot_width) 1904 { 1905 struct snd_soc_component *component = dai->component; 1906 unsigned int cl, val = 0; 1907 1908 if (tx_mask || rx_mask) 1909 snd_soc_component_update_bits(component, 1910 RT5682S_TDM_ADDA_CTRL_2, RT5682S_TDM_EN, RT5682S_TDM_EN); 1911 else 1912 snd_soc_component_update_bits(component, 1913 RT5682S_TDM_ADDA_CTRL_2, RT5682S_TDM_EN, 0); 1914 1915 switch (slots) { 1916 case 4: 1917 val |= RT5682S_TDM_TX_CH_4; 1918 val |= RT5682S_TDM_RX_CH_4; 1919 break; 1920 case 6: 1921 val |= RT5682S_TDM_TX_CH_6; 1922 val |= RT5682S_TDM_RX_CH_6; 1923 break; 1924 case 8: 1925 val |= RT5682S_TDM_TX_CH_8; 1926 val |= RT5682S_TDM_RX_CH_8; 1927 break; 1928 case 2: 1929 break; 1930 default: 1931 return -EINVAL; 1932 } 1933 1934 snd_soc_component_update_bits(component, RT5682S_TDM_CTRL, 1935 RT5682S_TDM_TX_CH_MASK | RT5682S_TDM_RX_CH_MASK, val); 1936 1937 switch (slot_width) { 1938 case 8: 1939 if (tx_mask || rx_mask) 1940 return -EINVAL; 1941 cl = RT5682S_I2S1_TX_CHL_8 | RT5682S_I2S1_RX_CHL_8; 1942 break; 1943 case 16: 1944 val = RT5682S_TDM_CL_16; 1945 cl = RT5682S_I2S1_TX_CHL_16 | RT5682S_I2S1_RX_CHL_16; 1946 break; 1947 case 20: 1948 val = RT5682S_TDM_CL_20; 1949 cl = RT5682S_I2S1_TX_CHL_20 | RT5682S_I2S1_RX_CHL_20; 1950 break; 1951 case 24: 1952 val = RT5682S_TDM_CL_24; 1953 cl = RT5682S_I2S1_TX_CHL_24 | RT5682S_I2S1_RX_CHL_24; 1954 break; 1955 case 32: 1956 val = RT5682S_TDM_CL_32; 1957 cl = RT5682S_I2S1_TX_CHL_32 | RT5682S_I2S1_RX_CHL_32; 1958 break; 1959 default: 1960 return -EINVAL; 1961 } 1962 1963 snd_soc_component_update_bits(component, RT5682S_TDM_TCON_CTRL_1, 1964 RT5682S_TDM_CL_MASK, val); 1965 snd_soc_component_update_bits(component, RT5682S_I2S1_SDP, 1966 RT5682S_I2S1_TX_CHL_MASK | RT5682S_I2S1_RX_CHL_MASK, cl); 1967 1968 return 0; 1969 } 1970 1971 static int rt5682s_hw_params(struct snd_pcm_substream *substream, 1972 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) 1973 { 1974 struct snd_soc_component *component = dai->component; 1975 struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component); 1976 unsigned int len_1 = 0, len_2 = 0; 1977 int frame_size; 1978 1979 rt5682s->lrck[dai->id] = params_rate(params); 1980 1981 frame_size = snd_soc_params_to_frame_size(params); 1982 if (frame_size < 0) { 1983 dev_err(component->dev, "Unsupported frame size: %d\n", frame_size); 1984 return -EINVAL; 1985 } 1986 1987 switch (params_width(params)) { 1988 case 16: 1989 break; 1990 case 20: 1991 len_1 |= RT5682S_I2S1_DL_20; 1992 len_2 |= RT5682S_I2S2_DL_20; 1993 break; 1994 case 24: 1995 len_1 |= RT5682S_I2S1_DL_24; 1996 len_2 |= RT5682S_I2S2_DL_24; 1997 break; 1998 case 32: 1999 len_1 |= RT5682S_I2S1_DL_32; 2000 len_2 |= RT5682S_I2S2_DL_24; 2001 break; 2002 case 8: 2003 len_1 |= RT5682S_I2S2_DL_8; 2004 len_2 |= RT5682S_I2S2_DL_8; 2005 break; 2006 default: 2007 return -EINVAL; 2008 } 2009 2010 switch (dai->id) { 2011 case RT5682S_AIF1: 2012 snd_soc_component_update_bits(component, RT5682S_I2S1_SDP, 2013 RT5682S_I2S1_DL_MASK, len_1); 2014 if (params_channels(params) == 1) /* mono mode */ 2015 snd_soc_component_update_bits(component, RT5682S_I2S1_SDP, 2016 RT5682S_I2S1_MONO_MASK, RT5682S_I2S1_MONO_EN); 2017 else 2018 snd_soc_component_update_bits(component, RT5682S_I2S1_SDP, 2019 RT5682S_I2S1_MONO_MASK, RT5682S_I2S1_MONO_DIS); 2020 break; 2021 case RT5682S_AIF2: 2022 snd_soc_component_update_bits(component, RT5682S_I2S2_SDP, 2023 RT5682S_I2S2_DL_MASK, len_2); 2024 if (params_channels(params) == 1) /* mono mode */ 2025 snd_soc_component_update_bits(component, RT5682S_I2S2_SDP, 2026 RT5682S_I2S2_MONO_MASK, RT5682S_I2S2_MONO_EN); 2027 else 2028 snd_soc_component_update_bits(component, RT5682S_I2S2_SDP, 2029 RT5682S_I2S2_MONO_MASK, RT5682S_I2S2_MONO_DIS); 2030 break; 2031 default: 2032 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id); 2033 return -EINVAL; 2034 } 2035 2036 return 0; 2037 } 2038 2039 static int rt5682s_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) 2040 { 2041 struct snd_soc_component *component = dai->component; 2042 struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component); 2043 unsigned int reg_val = 0, tdm_ctrl = 0; 2044 2045 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 2046 case SND_SOC_DAIFMT_CBM_CFM: 2047 rt5682s->master[dai->id] = 1; 2048 break; 2049 case SND_SOC_DAIFMT_CBS_CFS: 2050 rt5682s->master[dai->id] = 0; 2051 break; 2052 default: 2053 return -EINVAL; 2054 } 2055 2056 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 2057 case SND_SOC_DAIFMT_NB_NF: 2058 break; 2059 case SND_SOC_DAIFMT_IB_NF: 2060 reg_val |= RT5682S_I2S_BP_INV; 2061 tdm_ctrl |= RT5682S_TDM_S_BP_INV; 2062 break; 2063 case SND_SOC_DAIFMT_NB_IF: 2064 if (dai->id == RT5682S_AIF1) 2065 tdm_ctrl |= RT5682S_TDM_S_LP_INV | RT5682S_TDM_M_BP_INV; 2066 else 2067 return -EINVAL; 2068 break; 2069 case SND_SOC_DAIFMT_IB_IF: 2070 if (dai->id == RT5682S_AIF1) 2071 tdm_ctrl |= RT5682S_TDM_S_BP_INV | RT5682S_TDM_S_LP_INV | 2072 RT5682S_TDM_M_BP_INV | RT5682S_TDM_M_LP_INV; 2073 else 2074 return -EINVAL; 2075 break; 2076 default: 2077 return -EINVAL; 2078 } 2079 2080 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 2081 case SND_SOC_DAIFMT_I2S: 2082 break; 2083 case SND_SOC_DAIFMT_LEFT_J: 2084 reg_val |= RT5682S_I2S_DF_LEFT; 2085 tdm_ctrl |= RT5682S_TDM_DF_LEFT; 2086 break; 2087 case SND_SOC_DAIFMT_DSP_A: 2088 reg_val |= RT5682S_I2S_DF_PCM_A; 2089 tdm_ctrl |= RT5682S_TDM_DF_PCM_A; 2090 break; 2091 case SND_SOC_DAIFMT_DSP_B: 2092 reg_val |= RT5682S_I2S_DF_PCM_B; 2093 tdm_ctrl |= RT5682S_TDM_DF_PCM_B; 2094 break; 2095 default: 2096 return -EINVAL; 2097 } 2098 2099 switch (dai->id) { 2100 case RT5682S_AIF1: 2101 snd_soc_component_update_bits(component, RT5682S_I2S1_SDP, 2102 RT5682S_I2S_DF_MASK, reg_val); 2103 snd_soc_component_update_bits(component, RT5682S_TDM_TCON_CTRL_1, 2104 RT5682S_TDM_MS_MASK | RT5682S_TDM_S_BP_MASK | 2105 RT5682S_TDM_DF_MASK | RT5682S_TDM_M_BP_MASK | 2106 RT5682S_TDM_M_LP_MASK | RT5682S_TDM_S_LP_MASK, 2107 tdm_ctrl | rt5682s->master[dai->id]); 2108 break; 2109 case RT5682S_AIF2: 2110 if (rt5682s->master[dai->id] == 0) 2111 reg_val |= RT5682S_I2S2_MS_S; 2112 snd_soc_component_update_bits(component, RT5682S_I2S2_SDP, 2113 RT5682S_I2S2_MS_MASK | RT5682S_I2S_BP_MASK | 2114 RT5682S_I2S_DF_MASK, reg_val); 2115 break; 2116 default: 2117 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id); 2118 return -EINVAL; 2119 } 2120 return 0; 2121 } 2122 2123 static int rt5682s_set_component_sysclk(struct snd_soc_component *component, 2124 int clk_id, int source, unsigned int freq, int dir) 2125 { 2126 struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component); 2127 unsigned int src = 0; 2128 2129 if (freq == rt5682s->sysclk && clk_id == rt5682s->sysclk_src) 2130 return 0; 2131 2132 switch (clk_id) { 2133 case RT5682S_SCLK_S_MCLK: 2134 src = RT5682S_CLK_SRC_MCLK; 2135 break; 2136 case RT5682S_SCLK_S_PLL1: 2137 src = RT5682S_CLK_SRC_PLL1; 2138 break; 2139 case RT5682S_SCLK_S_PLL2: 2140 src = RT5682S_CLK_SRC_PLL2; 2141 break; 2142 case RT5682S_SCLK_S_RCCLK: 2143 src = RT5682S_CLK_SRC_RCCLK; 2144 break; 2145 default: 2146 dev_err(component->dev, "Invalid clock id (%d)\n", clk_id); 2147 return -EINVAL; 2148 } 2149 2150 snd_soc_component_update_bits(component, RT5682S_GLB_CLK, 2151 RT5682S_SCLK_SRC_MASK, src << RT5682S_SCLK_SRC_SFT); 2152 snd_soc_component_update_bits(component, RT5682S_ADDA_CLK_1, 2153 RT5682S_I2S_M_CLK_SRC_MASK, src << RT5682S_I2S_M_CLK_SRC_SFT); 2154 snd_soc_component_update_bits(component, RT5682S_I2S2_M_CLK_CTRL_1, 2155 RT5682S_I2S2_M_CLK_SRC_MASK, src << RT5682S_I2S2_M_CLK_SRC_SFT); 2156 2157 rt5682s->sysclk = freq; 2158 rt5682s->sysclk_src = clk_id; 2159 2160 dev_dbg(component->dev, "Sysclk is %dHz and clock id is %d\n", 2161 freq, clk_id); 2162 2163 return 0; 2164 } 2165 2166 static const struct pll_calc_map plla_table[] = { 2167 {2048000, 24576000, 0, 46, 2, true, false, false, false}, 2168 {256000, 24576000, 0, 382, 2, true, false, false, false}, 2169 {512000, 24576000, 0, 190, 2, true, false, false, false}, 2170 {4096000, 24576000, 0, 22, 2, true, false, false, false}, 2171 {1024000, 24576000, 0, 94, 2, true, false, false, false}, 2172 {11289600, 22579200, 1, 22, 2, false, false, false, false}, 2173 {1411200, 22579200, 0, 62, 2, true, false, false, false}, 2174 {2822400, 22579200, 0, 30, 2, true, false, false, false}, 2175 {12288000, 24576000, 1, 22, 2, false, false, false, false}, 2176 {1536000, 24576000, 0, 62, 2, true, false, false, false}, 2177 {3072000, 24576000, 0, 30, 2, true, false, false, false}, 2178 {24576000, 49152000, 4, 22, 0, false, false, false, false}, 2179 {3072000, 49152000, 0, 30, 0, true, false, false, false}, 2180 {6144000, 49152000, 0, 30, 0, false, false, false, false}, 2181 {49152000, 98304000, 10, 22, 0, false, true, false, false}, 2182 {6144000, 98304000, 0, 30, 0, false, true, false, false}, 2183 {12288000, 98304000, 1, 22, 0, false, true, false, false}, 2184 {48000000, 3840000, 10, 22, 23, false, false, false, false}, 2185 {24000000, 3840000, 4, 22, 23, false, false, false, false}, 2186 {19200000, 3840000, 3, 23, 23, false, false, false, false}, 2187 {38400000, 3840000, 8, 23, 23, false, false, false, false}, 2188 }; 2189 2190 static const struct pll_calc_map pllb_table[] = { 2191 {48000000, 24576000, 8, 6, 3, false, false, false, false}, 2192 {48000000, 22579200, 23, 12, 3, false, false, false, true}, 2193 {24000000, 24576000, 3, 6, 3, false, false, false, false}, 2194 {24000000, 22579200, 23, 26, 3, false, false, false, true}, 2195 {19200000, 24576000, 2, 6, 3, false, false, false, false}, 2196 {19200000, 22579200, 3, 5, 3, false, false, false, true}, 2197 {38400000, 24576000, 6, 6, 3, false, false, false, false}, 2198 {38400000, 22579200, 8, 5, 3, false, false, false, true}, 2199 {3840000, 49152000, 0, 6, 0, true, false, false, false}, 2200 }; 2201 2202 static int find_pll_inter_combination(unsigned int f_in, unsigned int f_out, 2203 struct pll_calc_map *a, struct pll_calc_map *b) 2204 { 2205 int i, j; 2206 2207 /* Look at PLLA table */ 2208 for (i = 0; i < ARRAY_SIZE(plla_table); i++) { 2209 if (plla_table[i].freq_in == f_in && plla_table[i].freq_out == f_out) { 2210 memcpy(a, plla_table + i, sizeof(*a)); 2211 return USE_PLLA; 2212 } 2213 } 2214 2215 /* Look at PLLB table */ 2216 for (i = 0; i < ARRAY_SIZE(pllb_table); i++) { 2217 if (pllb_table[i].freq_in == f_in && pllb_table[i].freq_out == f_out) { 2218 memcpy(b, pllb_table + i, sizeof(*b)); 2219 return USE_PLLB; 2220 } 2221 } 2222 2223 /* Find a combination of PLLA & PLLB */ 2224 for (i = ARRAY_SIZE(plla_table) - 1; i >= 0; i--) { 2225 if (plla_table[i].freq_in == f_in && plla_table[i].freq_out == 3840000) { 2226 for (j = ARRAY_SIZE(pllb_table) - 1; j >= 0; j--) { 2227 if (pllb_table[j].freq_in == 3840000 && 2228 pllb_table[j].freq_out == f_out) { 2229 memcpy(a, plla_table + i, sizeof(*a)); 2230 memcpy(b, pllb_table + j, sizeof(*b)); 2231 return USE_PLLAB; 2232 } 2233 } 2234 } 2235 } 2236 2237 return -EINVAL; 2238 } 2239 2240 static int rt5682s_set_component_pll(struct snd_soc_component *component, 2241 int pll_id, int source, unsigned int freq_in, 2242 unsigned int freq_out) 2243 { 2244 struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component); 2245 struct pll_calc_map a_map, b_map; 2246 2247 if (source == rt5682s->pll_src[pll_id] && freq_in == rt5682s->pll_in[pll_id] && 2248 freq_out == rt5682s->pll_out[pll_id]) 2249 return 0; 2250 2251 if (!freq_in || !freq_out) { 2252 dev_dbg(component->dev, "PLL disabled\n"); 2253 rt5682s->pll_in[pll_id] = 0; 2254 rt5682s->pll_out[pll_id] = 0; 2255 snd_soc_component_update_bits(component, RT5682S_GLB_CLK, 2256 RT5682S_SCLK_SRC_MASK, RT5682S_CLK_SRC_MCLK << RT5682S_SCLK_SRC_SFT); 2257 return 0; 2258 } 2259 2260 switch (source) { 2261 case RT5682S_PLL_S_MCLK: 2262 snd_soc_component_update_bits(component, RT5682S_GLB_CLK, 2263 RT5682S_PLL_SRC_MASK, RT5682S_PLL_SRC_MCLK); 2264 break; 2265 case RT5682S_PLL_S_BCLK1: 2266 snd_soc_component_update_bits(component, RT5682S_GLB_CLK, 2267 RT5682S_PLL_SRC_MASK, RT5682S_PLL_SRC_BCLK1); 2268 break; 2269 default: 2270 dev_err(component->dev, "Unknown PLL Source %d\n", source); 2271 return -EINVAL; 2272 } 2273 2274 rt5682s->pll_comb = find_pll_inter_combination(freq_in, freq_out, 2275 &a_map, &b_map); 2276 2277 if ((pll_id == RT5682S_PLL1 && rt5682s->pll_comb == USE_PLLA) || 2278 (pll_id == RT5682S_PLL2 && (rt5682s->pll_comb == USE_PLLB || 2279 rt5682s->pll_comb == USE_PLLAB))) { 2280 dev_dbg(component->dev, 2281 "Supported freq conversion for PLL%d:(%d->%d): %d\n", 2282 pll_id + 1, freq_in, freq_out, rt5682s->pll_comb); 2283 } else { 2284 dev_err(component->dev, 2285 "Unsupported freq conversion for PLL%d:(%d->%d): %d\n", 2286 pll_id + 1, freq_in, freq_out, rt5682s->pll_comb); 2287 return -EINVAL; 2288 } 2289 2290 if (rt5682s->pll_comb == USE_PLLA || rt5682s->pll_comb == USE_PLLAB) { 2291 dev_dbg(component->dev, 2292 "PLLA: fin=%d fout=%d m_bp=%d k_bp=%d m=%d n=%d k=%d\n", 2293 a_map.freq_in, a_map.freq_out, a_map.m_bp, a_map.k_bp, 2294 (a_map.m_bp ? 0 : a_map.m), a_map.n, (a_map.k_bp ? 0 : a_map.k)); 2295 snd_soc_component_update_bits(component, RT5682S_PLL_CTRL_1, 2296 RT5682S_PLLA_N_MASK, a_map.n); 2297 snd_soc_component_update_bits(component, RT5682S_PLL_CTRL_2, 2298 RT5682S_PLLA_M_MASK | RT5682S_PLLA_K_MASK, 2299 a_map.m << RT5682S_PLLA_M_SFT | a_map.k); 2300 snd_soc_component_update_bits(component, RT5682S_PLL_CTRL_6, 2301 RT5682S_PLLA_M_BP_MASK | RT5682S_PLLA_K_BP_MASK, 2302 a_map.m_bp << RT5682S_PLLA_M_BP_SFT | 2303 a_map.k_bp << RT5682S_PLLA_K_BP_SFT); 2304 } 2305 2306 if (rt5682s->pll_comb == USE_PLLB || rt5682s->pll_comb == USE_PLLAB) { 2307 dev_dbg(component->dev, 2308 "PLLB: fin=%d fout=%d m_bp=%d k_bp=%d m=%d n=%d k=%d byp_ps=%d sel_ps=%d\n", 2309 b_map.freq_in, b_map.freq_out, b_map.m_bp, b_map.k_bp, 2310 (b_map.m_bp ? 0 : b_map.m), b_map.n, (b_map.k_bp ? 0 : b_map.k), 2311 b_map.byp_ps, b_map.sel_ps); 2312 snd_soc_component_update_bits(component, RT5682S_PLL_CTRL_3, 2313 RT5682S_PLLB_N_MASK, b_map.n); 2314 snd_soc_component_update_bits(component, RT5682S_PLL_CTRL_4, 2315 RT5682S_PLLB_M_MASK | RT5682S_PLLB_K_MASK, 2316 b_map.m << RT5682S_PLLB_M_SFT | b_map.k); 2317 snd_soc_component_update_bits(component, RT5682S_PLL_CTRL_6, 2318 RT5682S_PLLB_SEL_PS_MASK | RT5682S_PLLB_BYP_PS_MASK | 2319 RT5682S_PLLB_M_BP_MASK | RT5682S_PLLB_K_BP_MASK, 2320 b_map.sel_ps << RT5682S_PLLB_SEL_PS_SFT | 2321 b_map.byp_ps << RT5682S_PLLB_BYP_PS_SFT | 2322 b_map.m_bp << RT5682S_PLLB_M_BP_SFT | 2323 b_map.k_bp << RT5682S_PLLB_K_BP_SFT); 2324 } 2325 2326 if (rt5682s->pll_comb == USE_PLLB) 2327 snd_soc_component_update_bits(component, RT5682S_PLL_CTRL_7, 2328 RT5682S_PLLB_SRC_MASK, RT5682S_PLLB_SRC_DFIN); 2329 2330 rt5682s->pll_in[pll_id] = freq_in; 2331 rt5682s->pll_out[pll_id] = freq_out; 2332 rt5682s->pll_src[pll_id] = source; 2333 2334 return 0; 2335 } 2336 2337 static int rt5682s_set_bclk1_ratio(struct snd_soc_dai *dai, 2338 unsigned int ratio) 2339 { 2340 struct snd_soc_component *component = dai->component; 2341 struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component); 2342 2343 rt5682s->bclk[dai->id] = ratio; 2344 2345 switch (ratio) { 2346 case 256: 2347 snd_soc_component_update_bits(component, RT5682S_TDM_TCON_CTRL_1, 2348 RT5682S_TDM_BCLK_MS1_MASK, RT5682S_TDM_BCLK_MS1_256); 2349 break; 2350 case 128: 2351 snd_soc_component_update_bits(component, RT5682S_TDM_TCON_CTRL_1, 2352 RT5682S_TDM_BCLK_MS1_MASK, RT5682S_TDM_BCLK_MS1_128); 2353 break; 2354 case 64: 2355 snd_soc_component_update_bits(component, RT5682S_TDM_TCON_CTRL_1, 2356 RT5682S_TDM_BCLK_MS1_MASK, RT5682S_TDM_BCLK_MS1_64); 2357 break; 2358 case 32: 2359 snd_soc_component_update_bits(component, RT5682S_TDM_TCON_CTRL_1, 2360 RT5682S_TDM_BCLK_MS1_MASK, RT5682S_TDM_BCLK_MS1_32); 2361 break; 2362 default: 2363 dev_err(dai->dev, "Invalid bclk1 ratio %d\n", ratio); 2364 return -EINVAL; 2365 } 2366 2367 return 0; 2368 } 2369 2370 static int rt5682s_set_bclk2_ratio(struct snd_soc_dai *dai, unsigned int ratio) 2371 { 2372 struct snd_soc_component *component = dai->component; 2373 struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component); 2374 2375 rt5682s->bclk[dai->id] = ratio; 2376 2377 switch (ratio) { 2378 case 64: 2379 snd_soc_component_update_bits(component, RT5682S_ADDA_CLK_2, 2380 RT5682S_I2S2_BCLK_MS2_MASK, RT5682S_I2S2_BCLK_MS2_64); 2381 break; 2382 case 32: 2383 snd_soc_component_update_bits(component, RT5682S_ADDA_CLK_2, 2384 RT5682S_I2S2_BCLK_MS2_MASK, RT5682S_I2S2_BCLK_MS2_32); 2385 break; 2386 default: 2387 dev_err(dai->dev, "Invalid bclk2 ratio %d\n", ratio); 2388 return -EINVAL; 2389 } 2390 2391 return 0; 2392 } 2393 2394 static int rt5682s_set_bias_level(struct snd_soc_component *component, 2395 enum snd_soc_bias_level level) 2396 { 2397 struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component); 2398 2399 switch (level) { 2400 case SND_SOC_BIAS_PREPARE: 2401 regmap_update_bits(rt5682s->regmap, RT5682S_PWR_DIG_1, 2402 RT5682S_PWR_LDO, RT5682S_PWR_LDO); 2403 break; 2404 case SND_SOC_BIAS_STANDBY: 2405 regmap_update_bits(rt5682s->regmap, RT5682S_PWR_DIG_1, 2406 RT5682S_DIG_GATE_CTRL, RT5682S_DIG_GATE_CTRL); 2407 break; 2408 case SND_SOC_BIAS_OFF: 2409 regmap_update_bits(rt5682s->regmap, RT5682S_PWR_DIG_1, 2410 RT5682S_DIG_GATE_CTRL | RT5682S_PWR_LDO, 0); 2411 break; 2412 case SND_SOC_BIAS_ON: 2413 break; 2414 } 2415 2416 return 0; 2417 } 2418 2419 #ifdef CONFIG_COMMON_CLK 2420 #define CLK_PLL2_FIN 48000000 2421 #define CLK_48 48000 2422 #define CLK_44 44100 2423 2424 static bool rt5682s_clk_check(struct rt5682s_priv *rt5682s) 2425 { 2426 if (!rt5682s->master[RT5682S_AIF1]) { 2427 dev_dbg(rt5682s->component->dev, "dai clk fmt not set correctly\n"); 2428 return false; 2429 } 2430 return true; 2431 } 2432 2433 static int rt5682s_wclk_prepare(struct clk_hw *hw) 2434 { 2435 struct rt5682s_priv *rt5682s = 2436 container_of(hw, struct rt5682s_priv, dai_clks_hw[RT5682S_DAI_WCLK_IDX]); 2437 struct snd_soc_component *component = rt5682s->component; 2438 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); 2439 2440 if (!rt5682s_clk_check(rt5682s)) 2441 return -EINVAL; 2442 2443 snd_soc_dapm_mutex_lock(dapm); 2444 2445 snd_soc_dapm_force_enable_pin_unlocked(dapm, "MICBIAS"); 2446 snd_soc_component_update_bits(component, RT5682S_PWR_ANLG_1, 2447 RT5682S_PWR_MB, RT5682S_PWR_MB); 2448 2449 snd_soc_dapm_force_enable_pin_unlocked(dapm, "Vref2"); 2450 snd_soc_component_update_bits(component, RT5682S_PWR_ANLG_1, 2451 RT5682S_PWR_VREF2 | RT5682S_PWR_FV2, RT5682S_PWR_VREF2); 2452 usleep_range(15000, 20000); 2453 snd_soc_component_update_bits(component, RT5682S_PWR_ANLG_1, 2454 RT5682S_PWR_FV2, RT5682S_PWR_FV2); 2455 2456 snd_soc_dapm_force_enable_pin_unlocked(dapm, "I2S1"); 2457 /* Only need to power PLLB due to the rate set restriction */ 2458 snd_soc_dapm_force_enable_pin_unlocked(dapm, "PLLB"); 2459 snd_soc_dapm_sync_unlocked(dapm); 2460 2461 snd_soc_dapm_mutex_unlock(dapm); 2462 2463 return 0; 2464 } 2465 2466 static void rt5682s_wclk_unprepare(struct clk_hw *hw) 2467 { 2468 struct rt5682s_priv *rt5682s = 2469 container_of(hw, struct rt5682s_priv, dai_clks_hw[RT5682S_DAI_WCLK_IDX]); 2470 struct snd_soc_component *component = rt5682s->component; 2471 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); 2472 2473 if (!rt5682s_clk_check(rt5682s)) 2474 return; 2475 2476 snd_soc_dapm_mutex_lock(dapm); 2477 2478 snd_soc_dapm_disable_pin_unlocked(dapm, "MICBIAS"); 2479 snd_soc_dapm_disable_pin_unlocked(dapm, "Vref2"); 2480 if (!rt5682s->jack_type) 2481 snd_soc_component_update_bits(component, RT5682S_PWR_ANLG_1, 2482 RT5682S_PWR_VREF2 | RT5682S_PWR_FV2 | RT5682S_PWR_MB, 0); 2483 2484 snd_soc_dapm_disable_pin_unlocked(dapm, "I2S1"); 2485 snd_soc_dapm_disable_pin_unlocked(dapm, "PLLB"); 2486 snd_soc_dapm_sync_unlocked(dapm); 2487 2488 snd_soc_dapm_mutex_unlock(dapm); 2489 } 2490 2491 static unsigned long rt5682s_wclk_recalc_rate(struct clk_hw *hw, 2492 unsigned long parent_rate) 2493 { 2494 struct rt5682s_priv *rt5682s = 2495 container_of(hw, struct rt5682s_priv, dai_clks_hw[RT5682S_DAI_WCLK_IDX]); 2496 struct snd_soc_component *component = rt5682s->component; 2497 const char * const clk_name = clk_hw_get_name(hw); 2498 2499 if (!rt5682s_clk_check(rt5682s)) 2500 return 0; 2501 /* 2502 * Only accept to set wclk rate to 44.1k or 48kHz. 2503 */ 2504 if (rt5682s->lrck[RT5682S_AIF1] != CLK_48 && 2505 rt5682s->lrck[RT5682S_AIF1] != CLK_44) { 2506 dev_warn(component->dev, "%s: clk %s only support %d or %d Hz output\n", 2507 __func__, clk_name, CLK_44, CLK_48); 2508 return 0; 2509 } 2510 2511 return rt5682s->lrck[RT5682S_AIF1]; 2512 } 2513 2514 static long rt5682s_wclk_round_rate(struct clk_hw *hw, unsigned long rate, 2515 unsigned long *parent_rate) 2516 { 2517 struct rt5682s_priv *rt5682s = 2518 container_of(hw, struct rt5682s_priv, dai_clks_hw[RT5682S_DAI_WCLK_IDX]); 2519 struct snd_soc_component *component = rt5682s->component; 2520 const char * const clk_name = clk_hw_get_name(hw); 2521 2522 if (!rt5682s_clk_check(rt5682s)) 2523 return -EINVAL; 2524 /* 2525 * Only accept to set wclk rate to 44.1k or 48kHz. 2526 * It will force to 48kHz if not both. 2527 */ 2528 if (rate != CLK_48 && rate != CLK_44) { 2529 dev_warn(component->dev, "%s: clk %s only support %d or %d Hz output\n", 2530 __func__, clk_name, CLK_44, CLK_48); 2531 rate = CLK_48; 2532 } 2533 2534 return rate; 2535 } 2536 2537 static int rt5682s_wclk_set_rate(struct clk_hw *hw, unsigned long rate, 2538 unsigned long parent_rate) 2539 { 2540 struct rt5682s_priv *rt5682s = 2541 container_of(hw, struct rt5682s_priv, dai_clks_hw[RT5682S_DAI_WCLK_IDX]); 2542 struct snd_soc_component *component = rt5682s->component; 2543 struct clk *parent_clk; 2544 const char * const clk_name = clk_hw_get_name(hw); 2545 unsigned int clk_pll2_fout; 2546 2547 if (!rt5682s_clk_check(rt5682s)) 2548 return -EINVAL; 2549 2550 /* 2551 * Whether the wclk's parent clk (mclk) exists or not, please ensure 2552 * it is fixed or set to 48MHz before setting wclk rate. It's a 2553 * temporary limitation. Only accept 48MHz clk as the clk provider. 2554 * 2555 * It will set the codec anyway by assuming mclk is 48MHz. 2556 */ 2557 parent_clk = clk_get_parent(hw->clk); 2558 if (!parent_clk) 2559 dev_warn(component->dev, 2560 "Parent mclk of wclk not acquired in driver. Please ensure mclk was provided as %d Hz.\n", 2561 CLK_PLL2_FIN); 2562 2563 if (parent_rate != CLK_PLL2_FIN) 2564 dev_warn(component->dev, "clk %s only support %d Hz input\n", 2565 clk_name, CLK_PLL2_FIN); 2566 2567 /* 2568 * To achieve the rate conversion from 48MHz to 44.1k or 48kHz, 2569 * PLL2 is needed. 2570 */ 2571 clk_pll2_fout = rate * 512; 2572 rt5682s_set_component_pll(component, RT5682S_PLL2, RT5682S_PLL_S_MCLK, 2573 CLK_PLL2_FIN, clk_pll2_fout); 2574 2575 rt5682s_set_component_sysclk(component, RT5682S_SCLK_S_PLL2, 0, 2576 clk_pll2_fout, SND_SOC_CLOCK_IN); 2577 2578 rt5682s->lrck[RT5682S_AIF1] = rate; 2579 2580 return 0; 2581 } 2582 2583 static unsigned long rt5682s_bclk_recalc_rate(struct clk_hw *hw, 2584 unsigned long parent_rate) 2585 { 2586 struct rt5682s_priv *rt5682s = 2587 container_of(hw, struct rt5682s_priv, dai_clks_hw[RT5682S_DAI_BCLK_IDX]); 2588 struct snd_soc_component *component = rt5682s->component; 2589 unsigned int bclks_per_wclk; 2590 2591 bclks_per_wclk = snd_soc_component_read(component, RT5682S_TDM_TCON_CTRL_1); 2592 2593 switch (bclks_per_wclk & RT5682S_TDM_BCLK_MS1_MASK) { 2594 case RT5682S_TDM_BCLK_MS1_256: 2595 return parent_rate * 256; 2596 case RT5682S_TDM_BCLK_MS1_128: 2597 return parent_rate * 128; 2598 case RT5682S_TDM_BCLK_MS1_64: 2599 return parent_rate * 64; 2600 case RT5682S_TDM_BCLK_MS1_32: 2601 return parent_rate * 32; 2602 default: 2603 return 0; 2604 } 2605 } 2606 2607 static unsigned long rt5682s_bclk_get_factor(unsigned long rate, 2608 unsigned long parent_rate) 2609 { 2610 unsigned long factor; 2611 2612 factor = rate / parent_rate; 2613 if (factor < 64) 2614 return 32; 2615 else if (factor < 128) 2616 return 64; 2617 else if (factor < 256) 2618 return 128; 2619 else 2620 return 256; 2621 } 2622 2623 static long rt5682s_bclk_round_rate(struct clk_hw *hw, unsigned long rate, 2624 unsigned long *parent_rate) 2625 { 2626 struct rt5682s_priv *rt5682s = 2627 container_of(hw, struct rt5682s_priv, dai_clks_hw[RT5682S_DAI_BCLK_IDX]); 2628 unsigned long factor; 2629 2630 if (!*parent_rate || !rt5682s_clk_check(rt5682s)) 2631 return -EINVAL; 2632 2633 /* 2634 * BCLK rates are set as a multiplier of WCLK in HW. 2635 * We don't allow changing the parent WCLK. We just do 2636 * some rounding down based on the parent WCLK rate 2637 * and find the appropriate multiplier of BCLK to 2638 * get the rounded down BCLK value. 2639 */ 2640 factor = rt5682s_bclk_get_factor(rate, *parent_rate); 2641 2642 return *parent_rate * factor; 2643 } 2644 2645 static int rt5682s_bclk_set_rate(struct clk_hw *hw, unsigned long rate, 2646 unsigned long parent_rate) 2647 { 2648 struct rt5682s_priv *rt5682s = 2649 container_of(hw, struct rt5682s_priv, dai_clks_hw[RT5682S_DAI_BCLK_IDX]); 2650 struct snd_soc_component *component = rt5682s->component; 2651 struct snd_soc_dai *dai; 2652 unsigned long factor; 2653 2654 if (!rt5682s_clk_check(rt5682s)) 2655 return -EINVAL; 2656 2657 factor = rt5682s_bclk_get_factor(rate, parent_rate); 2658 2659 for_each_component_dais(component, dai) 2660 if (dai->id == RT5682S_AIF1) 2661 break; 2662 if (!dai) { 2663 dev_err(component->dev, "dai %d not found in component\n", 2664 RT5682S_AIF1); 2665 return -ENODEV; 2666 } 2667 2668 return rt5682s_set_bclk1_ratio(dai, factor); 2669 } 2670 2671 static const struct clk_ops rt5682s_dai_clk_ops[RT5682S_DAI_NUM_CLKS] = { 2672 [RT5682S_DAI_WCLK_IDX] = { 2673 .prepare = rt5682s_wclk_prepare, 2674 .unprepare = rt5682s_wclk_unprepare, 2675 .recalc_rate = rt5682s_wclk_recalc_rate, 2676 .round_rate = rt5682s_wclk_round_rate, 2677 .set_rate = rt5682s_wclk_set_rate, 2678 }, 2679 [RT5682S_DAI_BCLK_IDX] = { 2680 .recalc_rate = rt5682s_bclk_recalc_rate, 2681 .round_rate = rt5682s_bclk_round_rate, 2682 .set_rate = rt5682s_bclk_set_rate, 2683 }, 2684 }; 2685 2686 static int rt5682s_register_dai_clks(struct snd_soc_component *component) 2687 { 2688 struct device *dev = component->dev; 2689 struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component); 2690 struct rt5682s_platform_data *pdata = &rt5682s->pdata; 2691 struct clk_hw *dai_clk_hw; 2692 int i, ret; 2693 2694 for (i = 0; i < RT5682S_DAI_NUM_CLKS; ++i) { 2695 struct clk_init_data init = { }; 2696 struct clk_parent_data parent_data; 2697 const struct clk_hw *parent; 2698 2699 dai_clk_hw = &rt5682s->dai_clks_hw[i]; 2700 2701 switch (i) { 2702 case RT5682S_DAI_WCLK_IDX: 2703 /* Make MCLK the parent of WCLK */ 2704 if (rt5682s->mclk) { 2705 parent_data = (struct clk_parent_data){ 2706 .fw_name = "mclk", 2707 }; 2708 init.parent_data = &parent_data; 2709 init.num_parents = 1; 2710 } 2711 break; 2712 case RT5682S_DAI_BCLK_IDX: 2713 /* Make WCLK the parent of BCLK */ 2714 parent = &rt5682s->dai_clks_hw[RT5682S_DAI_WCLK_IDX]; 2715 init.parent_hws = &parent; 2716 init.num_parents = 1; 2717 break; 2718 default: 2719 dev_err(dev, "Invalid clock index\n"); 2720 return -EINVAL; 2721 } 2722 2723 init.name = pdata->dai_clk_names[i]; 2724 init.ops = &rt5682s_dai_clk_ops[i]; 2725 init.flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_GATE; 2726 dai_clk_hw->init = &init; 2727 2728 ret = devm_clk_hw_register(dev, dai_clk_hw); 2729 if (ret) { 2730 dev_warn(dev, "Failed to register %s: %d\n", init.name, ret); 2731 return ret; 2732 } 2733 2734 if (dev->of_node) { 2735 devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, dai_clk_hw); 2736 } else { 2737 ret = devm_clk_hw_register_clkdev(dev, dai_clk_hw, 2738 init.name, dev_name(dev)); 2739 if (ret) 2740 return ret; 2741 } 2742 } 2743 2744 return 0; 2745 } 2746 2747 static int rt5682s_dai_probe_clks(struct snd_soc_component *component) 2748 { 2749 struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component); 2750 int ret; 2751 2752 /* Check if MCLK provided */ 2753 rt5682s->mclk = devm_clk_get(component->dev, "mclk"); 2754 if (IS_ERR(rt5682s->mclk)) { 2755 if (PTR_ERR(rt5682s->mclk) != -ENOENT) { 2756 ret = PTR_ERR(rt5682s->mclk); 2757 return ret; 2758 } 2759 rt5682s->mclk = NULL; 2760 } 2761 2762 /* Register CCF DAI clock control */ 2763 ret = rt5682s_register_dai_clks(component); 2764 if (ret) 2765 return ret; 2766 2767 /* Initial setup for CCF */ 2768 rt5682s->lrck[RT5682S_AIF1] = CLK_48; 2769 2770 return 0; 2771 } 2772 #else 2773 static inline int rt5682s_dai_probe_clks(struct snd_soc_component *component) 2774 { 2775 return 0; 2776 } 2777 #endif /* CONFIG_COMMON_CLK */ 2778 2779 static int rt5682s_probe(struct snd_soc_component *component) 2780 { 2781 struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component); 2782 struct snd_soc_dapm_context *dapm = &component->dapm; 2783 int ret; 2784 2785 rt5682s->component = component; 2786 2787 ret = rt5682s_dai_probe_clks(component); 2788 if (ret) 2789 return ret; 2790 2791 snd_soc_dapm_disable_pin(dapm, "MICBIAS"); 2792 snd_soc_dapm_disable_pin(dapm, "Vref2"); 2793 snd_soc_dapm_sync(dapm); 2794 return 0; 2795 } 2796 2797 static void rt5682s_remove(struct snd_soc_component *component) 2798 { 2799 struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component); 2800 2801 rt5682s_reset(rt5682s); 2802 } 2803 2804 #ifdef CONFIG_PM 2805 static int rt5682s_suspend(struct snd_soc_component *component) 2806 { 2807 struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component); 2808 2809 cancel_delayed_work_sync(&rt5682s->jack_detect_work); 2810 cancel_delayed_work_sync(&rt5682s->jd_check_work); 2811 2812 if (rt5682s->hs_jack && rt5682s->jack_type == SND_JACK_HEADSET) 2813 snd_soc_component_update_bits(component, RT5682S_4BTN_IL_CMD_2, 2814 RT5682S_4BTN_IL_MASK, RT5682S_4BTN_IL_DIS); 2815 2816 regcache_cache_only(rt5682s->regmap, true); 2817 regcache_mark_dirty(rt5682s->regmap); 2818 2819 return 0; 2820 } 2821 2822 static int rt5682s_resume(struct snd_soc_component *component) 2823 { 2824 struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component); 2825 2826 regcache_cache_only(rt5682s->regmap, false); 2827 regcache_sync(rt5682s->regmap); 2828 2829 if (rt5682s->hs_jack) { 2830 rt5682s->jack_type = 0; 2831 rt5682s_sar_power_mode(component, SAR_PWR_NORMAL, 0); 2832 mod_delayed_work(system_power_efficient_wq, 2833 &rt5682s->jack_detect_work, msecs_to_jiffies(0)); 2834 } 2835 2836 return 0; 2837 } 2838 #else 2839 #define rt5682s_suspend NULL 2840 #define rt5682s_resume NULL 2841 #endif 2842 2843 static const struct snd_soc_dai_ops rt5682s_aif1_dai_ops = { 2844 .hw_params = rt5682s_hw_params, 2845 .set_fmt = rt5682s_set_dai_fmt, 2846 .set_tdm_slot = rt5682s_set_tdm_slot, 2847 .set_bclk_ratio = rt5682s_set_bclk1_ratio, 2848 }; 2849 2850 static const struct snd_soc_dai_ops rt5682s_aif2_dai_ops = { 2851 .hw_params = rt5682s_hw_params, 2852 .set_fmt = rt5682s_set_dai_fmt, 2853 .set_bclk_ratio = rt5682s_set_bclk2_ratio, 2854 }; 2855 2856 static const struct snd_soc_component_driver rt5682s_soc_component_dev = { 2857 .probe = rt5682s_probe, 2858 .remove = rt5682s_remove, 2859 .suspend = rt5682s_suspend, 2860 .resume = rt5682s_resume, 2861 .set_bias_level = rt5682s_set_bias_level, 2862 .controls = rt5682s_snd_controls, 2863 .num_controls = ARRAY_SIZE(rt5682s_snd_controls), 2864 .dapm_widgets = rt5682s_dapm_widgets, 2865 .num_dapm_widgets = ARRAY_SIZE(rt5682s_dapm_widgets), 2866 .dapm_routes = rt5682s_dapm_routes, 2867 .num_dapm_routes = ARRAY_SIZE(rt5682s_dapm_routes), 2868 .set_sysclk = rt5682s_set_component_sysclk, 2869 .set_pll = rt5682s_set_component_pll, 2870 .set_jack = rt5682s_set_jack_detect, 2871 .use_pmdown_time = 1, 2872 .endianness = 1, 2873 .non_legacy_dai_naming = 1, 2874 }; 2875 2876 static int rt5682s_parse_dt(struct rt5682s_priv *rt5682s, struct device *dev) 2877 { 2878 device_property_read_u32(dev, "realtek,dmic1-data-pin", 2879 &rt5682s->pdata.dmic1_data_pin); 2880 device_property_read_u32(dev, "realtek,dmic1-clk-pin", 2881 &rt5682s->pdata.dmic1_clk_pin); 2882 device_property_read_u32(dev, "realtek,jd-src", 2883 &rt5682s->pdata.jd_src); 2884 device_property_read_u32(dev, "realtek,dmic-clk-rate-hz", 2885 &rt5682s->pdata.dmic_clk_rate); 2886 device_property_read_u32(dev, "realtek,dmic-delay-ms", 2887 &rt5682s->pdata.dmic_delay); 2888 2889 rt5682s->pdata.ldo1_en = of_get_named_gpio(dev->of_node, 2890 "realtek,ldo1-en-gpios", 0); 2891 2892 if (device_property_read_string_array(dev, "clock-output-names", 2893 rt5682s->pdata.dai_clk_names, 2894 RT5682S_DAI_NUM_CLKS) < 0) 2895 dev_warn(dev, "Using default DAI clk names: %s, %s\n", 2896 rt5682s->pdata.dai_clk_names[RT5682S_DAI_WCLK_IDX], 2897 rt5682s->pdata.dai_clk_names[RT5682S_DAI_BCLK_IDX]); 2898 2899 rt5682s->pdata.dmic_clk_driving_high = device_property_read_bool(dev, 2900 "realtek,dmic-clk-driving-high"); 2901 2902 return 0; 2903 } 2904 2905 static void rt5682s_calibrate(struct rt5682s_priv *rt5682s) 2906 { 2907 unsigned int count, value; 2908 2909 mutex_lock(&rt5682s->calibrate_mutex); 2910 2911 regmap_write(rt5682s->regmap, RT5682S_PWR_ANLG_1, 0xaa80); 2912 usleep_range(15000, 20000); 2913 regmap_write(rt5682s->regmap, RT5682S_PWR_ANLG_1, 0xfa80); 2914 regmap_write(rt5682s->regmap, RT5682S_PWR_DIG_1, 0x01c0); 2915 regmap_write(rt5682s->regmap, RT5682S_MICBIAS_2, 0x0380); 2916 regmap_write(rt5682s->regmap, RT5682S_GLB_CLK, 0x8000); 2917 regmap_write(rt5682s->regmap, RT5682S_ADDA_CLK_1, 0x1001); 2918 regmap_write(rt5682s->regmap, RT5682S_CHOP_DAC_2, 0x3030); 2919 regmap_write(rt5682s->regmap, RT5682S_CHOP_ADC, 0xb000); 2920 regmap_write(rt5682s->regmap, RT5682S_STO1_ADC_MIXER, 0x686c); 2921 regmap_write(rt5682s->regmap, RT5682S_CAL_REC, 0x5151); 2922 regmap_write(rt5682s->regmap, RT5682S_HP_CALIB_CTRL_2, 0x0321); 2923 regmap_write(rt5682s->regmap, RT5682S_HP_LOGIC_CTRL_2, 0x0004); 2924 regmap_write(rt5682s->regmap, RT5682S_HP_CALIB_CTRL_1, 0x7c00); 2925 regmap_write(rt5682s->regmap, RT5682S_HP_CALIB_CTRL_1, 0xfc00); 2926 2927 for (count = 0; count < 60; count++) { 2928 regmap_read(rt5682s->regmap, RT5682S_HP_CALIB_ST_1, &value); 2929 if (!(value & 0x8000)) 2930 break; 2931 2932 usleep_range(10000, 10005); 2933 } 2934 2935 if (count >= 60) 2936 dev_err(rt5682s->component->dev, "HP Calibration Failure\n"); 2937 2938 /* restore settings */ 2939 regmap_write(rt5682s->regmap, RT5682S_MICBIAS_2, 0x0180); 2940 regmap_write(rt5682s->regmap, RT5682S_CAL_REC, 0x5858); 2941 regmap_write(rt5682s->regmap, RT5682S_STO1_ADC_MIXER, 0xc0c4); 2942 regmap_write(rt5682s->regmap, RT5682S_HP_CALIB_CTRL_2, 0x0320); 2943 regmap_write(rt5682s->regmap, RT5682S_PWR_DIG_1, 0x00c0); 2944 regmap_write(rt5682s->regmap, RT5682S_PWR_ANLG_1, 0x0800); 2945 regmap_write(rt5682s->regmap, RT5682S_GLB_CLK, 0x0000); 2946 2947 mutex_unlock(&rt5682s->calibrate_mutex); 2948 } 2949 2950 static const struct regmap_config rt5682s_regmap = { 2951 .reg_bits = 16, 2952 .val_bits = 16, 2953 .max_register = RT5682S_MAX_REG, 2954 .volatile_reg = rt5682s_volatile_register, 2955 .readable_reg = rt5682s_readable_register, 2956 .cache_type = REGCACHE_RBTREE, 2957 .reg_defaults = rt5682s_reg, 2958 .num_reg_defaults = ARRAY_SIZE(rt5682s_reg), 2959 .use_single_read = true, 2960 .use_single_write = true, 2961 }; 2962 2963 static struct snd_soc_dai_driver rt5682s_dai[] = { 2964 { 2965 .name = "rt5682s-aif1", 2966 .id = RT5682S_AIF1, 2967 .playback = { 2968 .stream_name = "AIF1 Playback", 2969 .channels_min = 1, 2970 .channels_max = 2, 2971 .rates = RT5682S_STEREO_RATES, 2972 .formats = RT5682S_FORMATS, 2973 }, 2974 .capture = { 2975 .stream_name = "AIF1 Capture", 2976 .channels_min = 1, 2977 .channels_max = 2, 2978 .rates = RT5682S_STEREO_RATES, 2979 .formats = RT5682S_FORMATS, 2980 }, 2981 .ops = &rt5682s_aif1_dai_ops, 2982 }, 2983 { 2984 .name = "rt5682s-aif2", 2985 .id = RT5682S_AIF2, 2986 .capture = { 2987 .stream_name = "AIF2 Capture", 2988 .channels_min = 1, 2989 .channels_max = 2, 2990 .rates = RT5682S_STEREO_RATES, 2991 .formats = RT5682S_FORMATS, 2992 }, 2993 .ops = &rt5682s_aif2_dai_ops, 2994 }, 2995 }; 2996 2997 static void rt5682s_i2c_disable_regulators(void *data) 2998 { 2999 struct rt5682s_priv *rt5682s = data; 3000 3001 regulator_bulk_disable(ARRAY_SIZE(rt5682s->supplies), rt5682s->supplies); 3002 } 3003 3004 static int rt5682s_i2c_probe(struct i2c_client *i2c, 3005 const struct i2c_device_id *id) 3006 { 3007 struct rt5682s_platform_data *pdata = dev_get_platdata(&i2c->dev); 3008 struct rt5682s_priv *rt5682s; 3009 int i, ret; 3010 unsigned int val; 3011 3012 rt5682s = devm_kzalloc(&i2c->dev, sizeof(struct rt5682s_priv), GFP_KERNEL); 3013 if (!rt5682s) 3014 return -ENOMEM; 3015 3016 i2c_set_clientdata(i2c, rt5682s); 3017 3018 rt5682s->pdata = i2s_default_platform_data; 3019 3020 if (pdata) 3021 rt5682s->pdata = *pdata; 3022 else 3023 rt5682s_parse_dt(rt5682s, &i2c->dev); 3024 3025 rt5682s->regmap = devm_regmap_init_i2c(i2c, &rt5682s_regmap); 3026 if (IS_ERR(rt5682s->regmap)) { 3027 ret = PTR_ERR(rt5682s->regmap); 3028 dev_err(&i2c->dev, "Failed to allocate register map: %d\n", ret); 3029 return ret; 3030 } 3031 3032 for (i = 0; i < ARRAY_SIZE(rt5682s->supplies); i++) 3033 rt5682s->supplies[i].supply = rt5682s_supply_names[i]; 3034 3035 ret = devm_regulator_bulk_get(&i2c->dev, 3036 ARRAY_SIZE(rt5682s->supplies), rt5682s->supplies); 3037 if (ret) { 3038 dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret); 3039 return ret; 3040 } 3041 3042 ret = devm_add_action_or_reset(&i2c->dev, rt5682s_i2c_disable_regulators, rt5682s); 3043 if (ret) 3044 return ret; 3045 3046 ret = regulator_bulk_enable(ARRAY_SIZE(rt5682s->supplies), rt5682s->supplies); 3047 if (ret) { 3048 dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret); 3049 return ret; 3050 } 3051 3052 if (gpio_is_valid(rt5682s->pdata.ldo1_en)) { 3053 if (devm_gpio_request_one(&i2c->dev, rt5682s->pdata.ldo1_en, 3054 GPIOF_OUT_INIT_HIGH, "rt5682s")) 3055 dev_err(&i2c->dev, "Fail gpio_request gpio_ldo\n"); 3056 } 3057 3058 /* Sleep for 50 ms minimum */ 3059 usleep_range(50000, 55000); 3060 3061 regmap_read(rt5682s->regmap, RT5682S_DEVICE_ID, &val); 3062 if (val != DEVICE_ID) { 3063 dev_err(&i2c->dev, "Device with ID register %x is not rt5682s\n", val); 3064 return -ENODEV; 3065 } 3066 3067 rt5682s_reset(rt5682s); 3068 rt5682s_apply_patch_list(rt5682s, &i2c->dev); 3069 3070 regmap_update_bits(rt5682s->regmap, RT5682S_PWR_DIG_2, 3071 RT5682S_DLDO_I_LIMIT_MASK, RT5682S_DLDO_I_LIMIT_DIS); 3072 usleep_range(20000, 25000); 3073 3074 mutex_init(&rt5682s->calibrate_mutex); 3075 mutex_init(&rt5682s->sar_mutex); 3076 mutex_init(&rt5682s->jdet_mutex); 3077 rt5682s_calibrate(rt5682s); 3078 3079 regmap_update_bits(rt5682s->regmap, RT5682S_MICBIAS_2, 3080 RT5682S_PWR_CLK25M_MASK | RT5682S_PWR_CLK1M_MASK, 3081 RT5682S_PWR_CLK25M_PD | RT5682S_PWR_CLK1M_PU); 3082 regmap_update_bits(rt5682s->regmap, RT5682S_PWR_ANLG_1, 3083 RT5682S_PWR_BG, RT5682S_PWR_BG); 3084 regmap_update_bits(rt5682s->regmap, RT5682S_HP_LOGIC_CTRL_2, 3085 RT5682S_HP_SIG_SRC_MASK, RT5682S_HP_SIG_SRC_1BIT_CTL); 3086 regmap_update_bits(rt5682s->regmap, RT5682S_HP_CHARGE_PUMP_2, 3087 RT5682S_PM_HP_MASK, RT5682S_PM_HP_HV); 3088 regmap_update_bits(rt5682s->regmap, RT5682S_HP_AMP_DET_CTL_1, 3089 RT5682S_CP_SW_SIZE_MASK, RT5682S_CP_SW_SIZE_M); 3090 3091 /* DMIC data pin */ 3092 switch (rt5682s->pdata.dmic1_data_pin) { 3093 case RT5682S_DMIC1_DATA_NULL: 3094 break; 3095 case RT5682S_DMIC1_DATA_GPIO2: /* share with LRCK2 */ 3096 regmap_update_bits(rt5682s->regmap, RT5682S_DMIC_CTRL_1, 3097 RT5682S_DMIC_1_DP_MASK, RT5682S_DMIC_1_DP_GPIO2); 3098 regmap_update_bits(rt5682s->regmap, RT5682S_GPIO_CTRL_1, 3099 RT5682S_GP2_PIN_MASK, RT5682S_GP2_PIN_DMIC_SDA); 3100 break; 3101 case RT5682S_DMIC1_DATA_GPIO5: /* share with DACDAT1 */ 3102 regmap_update_bits(rt5682s->regmap, RT5682S_DMIC_CTRL_1, 3103 RT5682S_DMIC_1_DP_MASK, RT5682S_DMIC_1_DP_GPIO5); 3104 regmap_update_bits(rt5682s->regmap, RT5682S_GPIO_CTRL_1, 3105 RT5682S_GP5_PIN_MASK, RT5682S_GP5_PIN_DMIC_SDA); 3106 break; 3107 default: 3108 dev_warn(&i2c->dev, "invalid DMIC_DAT pin\n"); 3109 break; 3110 } 3111 3112 /* DMIC clk pin */ 3113 switch (rt5682s->pdata.dmic1_clk_pin) { 3114 case RT5682S_DMIC1_CLK_NULL: 3115 break; 3116 case RT5682S_DMIC1_CLK_GPIO1: /* share with IRQ */ 3117 regmap_update_bits(rt5682s->regmap, RT5682S_GPIO_CTRL_1, 3118 RT5682S_GP1_PIN_MASK, RT5682S_GP1_PIN_DMIC_CLK); 3119 break; 3120 case RT5682S_DMIC1_CLK_GPIO3: /* share with BCLK2 */ 3121 regmap_update_bits(rt5682s->regmap, RT5682S_GPIO_CTRL_1, 3122 RT5682S_GP3_PIN_MASK, RT5682S_GP3_PIN_DMIC_CLK); 3123 if (rt5682s->pdata.dmic_clk_driving_high) 3124 regmap_update_bits(rt5682s->regmap, RT5682S_PAD_DRIVING_CTRL, 3125 RT5682S_PAD_DRV_GP3_MASK, RT5682S_PAD_DRV_GP3_HIGH); 3126 break; 3127 default: 3128 dev_warn(&i2c->dev, "invalid DMIC_CLK pin\n"); 3129 break; 3130 } 3131 3132 INIT_DELAYED_WORK(&rt5682s->jack_detect_work, rt5682s_jack_detect_handler); 3133 INIT_DELAYED_WORK(&rt5682s->jd_check_work, rt5682s_jd_check_handler); 3134 3135 if (i2c->irq) { 3136 ret = devm_request_threaded_irq(&i2c->dev, i2c->irq, NULL, rt5682s_irq, 3137 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING | IRQF_ONESHOT, 3138 "rt5682s", rt5682s); 3139 if (ret) 3140 dev_err(&i2c->dev, "Failed to reguest IRQ: %d\n", ret); 3141 } 3142 3143 return devm_snd_soc_register_component(&i2c->dev, &rt5682s_soc_component_dev, 3144 rt5682s_dai, ARRAY_SIZE(rt5682s_dai)); 3145 } 3146 3147 static void rt5682s_i2c_shutdown(struct i2c_client *client) 3148 { 3149 struct rt5682s_priv *rt5682s = i2c_get_clientdata(client); 3150 3151 disable_irq(client->irq); 3152 cancel_delayed_work_sync(&rt5682s->jack_detect_work); 3153 cancel_delayed_work_sync(&rt5682s->jd_check_work); 3154 3155 rt5682s_reset(rt5682s); 3156 } 3157 3158 static int rt5682s_i2c_remove(struct i2c_client *client) 3159 { 3160 rt5682s_i2c_shutdown(client); 3161 3162 return 0; 3163 } 3164 3165 static const struct of_device_id rt5682s_of_match[] = { 3166 {.compatible = "realtek,rt5682s"}, 3167 {}, 3168 }; 3169 MODULE_DEVICE_TABLE(of, rt5682s_of_match); 3170 3171 static const struct acpi_device_id rt5682s_acpi_match[] = { 3172 {"RTL5682", 0,}, 3173 {}, 3174 }; 3175 MODULE_DEVICE_TABLE(acpi, rt5682s_acpi_match); 3176 3177 static const struct i2c_device_id rt5682s_i2c_id[] = { 3178 {"rt5682s", 0}, 3179 {} 3180 }; 3181 MODULE_DEVICE_TABLE(i2c, rt5682s_i2c_id); 3182 3183 static struct i2c_driver rt5682s_i2c_driver = { 3184 .driver = { 3185 .name = "rt5682s", 3186 .of_match_table = rt5682s_of_match, 3187 .acpi_match_table = rt5682s_acpi_match, 3188 .probe_type = PROBE_PREFER_ASYNCHRONOUS, 3189 }, 3190 .probe = rt5682s_i2c_probe, 3191 .remove = rt5682s_i2c_remove, 3192 .shutdown = rt5682s_i2c_shutdown, 3193 .id_table = rt5682s_i2c_id, 3194 }; 3195 module_i2c_driver(rt5682s_i2c_driver); 3196 3197 MODULE_DESCRIPTION("ASoC RT5682I-VS driver"); 3198 MODULE_AUTHOR("Derek Fang <derek.fang@realtek.com>"); 3199 MODULE_LICENSE("GPL v2"); 3200