1 // SPDX-License-Identifier: GPL-2.0-only 2 // 3 // rt5682s.c -- RT5682I-VS ALSA SoC audio component driver 4 // 5 // Copyright 2021 Realtek Semiconductor Corp. 6 // Author: Derek Fang <derek.fang@realtek.com> 7 // 8 9 #include <linux/module.h> 10 #include <linux/moduleparam.h> 11 #include <linux/init.h> 12 #include <linux/delay.h> 13 #include <linux/pm.h> 14 #include <linux/pm_runtime.h> 15 #include <linux/i2c.h> 16 #include <linux/platform_device.h> 17 #include <linux/spi/spi.h> 18 #include <linux/acpi.h> 19 #include <linux/gpio.h> 20 #include <linux/of_gpio.h> 21 #include <linux/mutex.h> 22 #include <sound/core.h> 23 #include <sound/pcm.h> 24 #include <sound/pcm_params.h> 25 #include <sound/jack.h> 26 #include <sound/soc.h> 27 #include <sound/soc-dapm.h> 28 #include <sound/initval.h> 29 #include <sound/tlv.h> 30 #include <sound/rt5682s.h> 31 32 #include "rt5682s.h" 33 34 #define DEVICE_ID 0x6749 35 36 static const struct rt5682s_platform_data i2s_default_platform_data = { 37 .dmic1_data_pin = RT5682S_DMIC1_DATA_GPIO2, 38 .dmic1_clk_pin = RT5682S_DMIC1_CLK_GPIO3, 39 .jd_src = RT5682S_JD1, 40 .dai_clk_names[RT5682S_DAI_WCLK_IDX] = "rt5682-dai-wclk", 41 .dai_clk_names[RT5682S_DAI_BCLK_IDX] = "rt5682-dai-bclk", 42 }; 43 44 static const char *rt5682s_supply_names[RT5682S_NUM_SUPPLIES] = { 45 "AVDD", 46 "MICVDD", 47 }; 48 49 static const struct reg_sequence patch_list[] = { 50 {RT5682S_I2C_CTRL, 0x0007}, 51 {RT5682S_DIG_IN_CTRL_1, 0x0000}, 52 {RT5682S_CHOP_DAC_2, 0x2020}, 53 {RT5682S_VREF_REC_OP_FB_CAP_CTRL_2, 0x0101}, 54 {RT5682S_VREF_REC_OP_FB_CAP_CTRL_1, 0x80c0}, 55 {RT5682S_HP_CALIB_CTRL_9, 0x0002}, 56 {RT5682S_DEPOP_1, 0x0000}, 57 {RT5682S_HP_CHARGE_PUMP_2, 0x3c15}, 58 {RT5682S_DAC1_DIG_VOL, 0xfefe}, 59 {RT5682S_SAR_IL_CMD_2, 0xac00}, 60 {RT5682S_SAR_IL_CMD_3, 0x024c}, 61 {RT5682S_CBJ_CTRL_6, 0x0804}, 62 }; 63 64 static void rt5682s_apply_patch_list(struct rt5682s_priv *rt5682s, 65 struct device *dev) 66 { 67 int ret; 68 69 ret = regmap_multi_reg_write(rt5682s->regmap, patch_list, ARRAY_SIZE(patch_list)); 70 if (ret) 71 dev_warn(dev, "Failed to apply regmap patch: %d\n", ret); 72 } 73 74 static const struct reg_default rt5682s_reg[] = { 75 {0x0002, 0x8080}, 76 {0x0003, 0x0001}, 77 {0x0005, 0x0000}, 78 {0x0006, 0x0000}, 79 {0x0008, 0x8007}, 80 {0x000b, 0x0000}, 81 {0x000f, 0x4000}, 82 {0x0010, 0x4040}, 83 {0x0011, 0x0000}, 84 {0x0012, 0x0000}, 85 {0x0013, 0x1200}, 86 {0x0014, 0x200a}, 87 {0x0015, 0x0404}, 88 {0x0016, 0x0404}, 89 {0x0017, 0x05a4}, 90 {0x0019, 0xffff}, 91 {0x001c, 0x2f2f}, 92 {0x001f, 0x0000}, 93 {0x0022, 0x5757}, 94 {0x0023, 0x0039}, 95 {0x0024, 0x000b}, 96 {0x0026, 0xc0c4}, 97 {0x0029, 0x8080}, 98 {0x002a, 0xa0a0}, 99 {0x002b, 0x0300}, 100 {0x0030, 0x0000}, 101 {0x003c, 0x08c0}, 102 {0x0044, 0x1818}, 103 {0x004b, 0x00c0}, 104 {0x004c, 0x0000}, 105 {0x004d, 0x0000}, 106 {0x0061, 0x00c0}, 107 {0x0062, 0x008a}, 108 {0x0063, 0x0800}, 109 {0x0064, 0x0000}, 110 {0x0065, 0x0000}, 111 {0x0066, 0x0030}, 112 {0x0067, 0x000c}, 113 {0x0068, 0x0000}, 114 {0x0069, 0x0000}, 115 {0x006a, 0x0000}, 116 {0x006b, 0x0000}, 117 {0x006c, 0x0000}, 118 {0x006d, 0x2200}, 119 {0x006e, 0x0810}, 120 {0x006f, 0xe4de}, 121 {0x0070, 0x3320}, 122 {0x0071, 0x0000}, 123 {0x0073, 0x0000}, 124 {0x0074, 0x0000}, 125 {0x0075, 0x0002}, 126 {0x0076, 0x0001}, 127 {0x0079, 0x0000}, 128 {0x007a, 0x0000}, 129 {0x007b, 0x0000}, 130 {0x007c, 0x0100}, 131 {0x007e, 0x0000}, 132 {0x007f, 0x0000}, 133 {0x0080, 0x0000}, 134 {0x0083, 0x0000}, 135 {0x0084, 0x0000}, 136 {0x0085, 0x0000}, 137 {0x0086, 0x0005}, 138 {0x0087, 0x0000}, 139 {0x0088, 0x0000}, 140 {0x008c, 0x0003}, 141 {0x008e, 0x0060}, 142 {0x008f, 0x4da1}, 143 {0x0091, 0x1c15}, 144 {0x0092, 0x0425}, 145 {0x0093, 0x0000}, 146 {0x0094, 0x0080}, 147 {0x0095, 0x008f}, 148 {0x0096, 0x0000}, 149 {0x0097, 0x0000}, 150 {0x0098, 0x0000}, 151 {0x0099, 0x0000}, 152 {0x009a, 0x0000}, 153 {0x009b, 0x0000}, 154 {0x009c, 0x0000}, 155 {0x009d, 0x0000}, 156 {0x009e, 0x0000}, 157 {0x009f, 0x0009}, 158 {0x00a0, 0x0000}, 159 {0x00a3, 0x0002}, 160 {0x00a4, 0x0001}, 161 {0x00b6, 0x0000}, 162 {0x00b7, 0x0000}, 163 {0x00b8, 0x0000}, 164 {0x00b9, 0x0002}, 165 {0x00be, 0x0000}, 166 {0x00c0, 0x0160}, 167 {0x00c1, 0x82a0}, 168 {0x00c2, 0x0000}, 169 {0x00d0, 0x0000}, 170 {0x00d2, 0x3300}, 171 {0x00d3, 0x2200}, 172 {0x00d4, 0x0000}, 173 {0x00d9, 0x0000}, 174 {0x00da, 0x0000}, 175 {0x00db, 0x0000}, 176 {0x00dc, 0x00c0}, 177 {0x00dd, 0x2220}, 178 {0x00de, 0x3131}, 179 {0x00df, 0x3131}, 180 {0x00e0, 0x3131}, 181 {0x00e2, 0x0000}, 182 {0x00e3, 0x4000}, 183 {0x00e4, 0x0aa0}, 184 {0x00e5, 0x3131}, 185 {0x00e6, 0x3131}, 186 {0x00e7, 0x3131}, 187 {0x00e8, 0x3131}, 188 {0x00ea, 0xb320}, 189 {0x00eb, 0x0000}, 190 {0x00f0, 0x0000}, 191 {0x00f6, 0x0000}, 192 {0x00fa, 0x0000}, 193 {0x00fb, 0x0000}, 194 {0x00fc, 0x0000}, 195 {0x00fd, 0x0000}, 196 {0x00fe, 0x10ec}, 197 {0x00ff, 0x6749}, 198 {0x0100, 0xa000}, 199 {0x010b, 0x0066}, 200 {0x010c, 0x6666}, 201 {0x010d, 0x2202}, 202 {0x010e, 0x6666}, 203 {0x010f, 0xa800}, 204 {0x0110, 0x0006}, 205 {0x0111, 0x0460}, 206 {0x0112, 0x2000}, 207 {0x0113, 0x0200}, 208 {0x0117, 0x8000}, 209 {0x0118, 0x0303}, 210 {0x0125, 0x0020}, 211 {0x0132, 0x5026}, 212 {0x0136, 0x8000}, 213 {0x0139, 0x0005}, 214 {0x013a, 0x3030}, 215 {0x013b, 0xa000}, 216 {0x013c, 0x4110}, 217 {0x013f, 0x0000}, 218 {0x0145, 0x0022}, 219 {0x0146, 0x0000}, 220 {0x0147, 0x0000}, 221 {0x0148, 0x0000}, 222 {0x0156, 0x0022}, 223 {0x0157, 0x0303}, 224 {0x0158, 0x2222}, 225 {0x0159, 0x0000}, 226 {0x0160, 0x4ec0}, 227 {0x0161, 0x0080}, 228 {0x0162, 0x0200}, 229 {0x0163, 0x0800}, 230 {0x0164, 0x0000}, 231 {0x0165, 0x0000}, 232 {0x0166, 0x0000}, 233 {0x0167, 0x000f}, 234 {0x0168, 0x000f}, 235 {0x0169, 0x0001}, 236 {0x0190, 0x4131}, 237 {0x0194, 0x0000}, 238 {0x0195, 0x0000}, 239 {0x0197, 0x0022}, 240 {0x0198, 0x0000}, 241 {0x0199, 0x0000}, 242 {0x01ac, 0x0000}, 243 {0x01ad, 0x0000}, 244 {0x01ae, 0x0000}, 245 {0x01af, 0x2000}, 246 {0x01b0, 0x0000}, 247 {0x01b1, 0x0000}, 248 {0x01b2, 0x0000}, 249 {0x01b3, 0x0017}, 250 {0x01b4, 0x004b}, 251 {0x01b5, 0x0000}, 252 {0x01b6, 0x03e8}, 253 {0x01b7, 0x0000}, 254 {0x01b8, 0x0000}, 255 {0x01b9, 0x0400}, 256 {0x01ba, 0xb5b6}, 257 {0x01bb, 0x9124}, 258 {0x01bc, 0x4924}, 259 {0x01bd, 0x0009}, 260 {0x01be, 0x0018}, 261 {0x01bf, 0x002a}, 262 {0x01c0, 0x004c}, 263 {0x01c1, 0x0097}, 264 {0x01c2, 0x01c3}, 265 {0x01c3, 0x03e9}, 266 {0x01c4, 0x1389}, 267 {0x01c5, 0xc351}, 268 {0x01c6, 0x02a0}, 269 {0x01c7, 0x0b0f}, 270 {0x01c8, 0x402f}, 271 {0x01c9, 0x0702}, 272 {0x01ca, 0x0000}, 273 {0x01cb, 0x0000}, 274 {0x01cc, 0x5757}, 275 {0x01cd, 0x5757}, 276 {0x01ce, 0x5757}, 277 {0x01cf, 0x5757}, 278 {0x01d0, 0x5757}, 279 {0x01d1, 0x5757}, 280 {0x01d2, 0x5757}, 281 {0x01d3, 0x5757}, 282 {0x01d4, 0x5757}, 283 {0x01d5, 0x5757}, 284 {0x01d6, 0x0000}, 285 {0x01d7, 0x0000}, 286 {0x01d8, 0x0162}, 287 {0x01d9, 0x0007}, 288 {0x01da, 0x0000}, 289 {0x01db, 0x0004}, 290 {0x01dc, 0x0000}, 291 {0x01de, 0x7c00}, 292 {0x01df, 0x0020}, 293 {0x01e0, 0x04c1}, 294 {0x01e1, 0x0000}, 295 {0x01e2, 0x0000}, 296 {0x01e3, 0x0000}, 297 {0x01e4, 0x0000}, 298 {0x01e5, 0x0000}, 299 {0x01e6, 0x0001}, 300 {0x01e7, 0x0000}, 301 {0x01e8, 0x0000}, 302 {0x01eb, 0x0000}, 303 {0x01ec, 0x0000}, 304 {0x01ed, 0x0000}, 305 {0x01ee, 0x0000}, 306 {0x01ef, 0x0000}, 307 {0x01f0, 0x0000}, 308 {0x01f1, 0x0000}, 309 {0x01f2, 0x0000}, 310 {0x01f3, 0x0000}, 311 {0x01f4, 0x0000}, 312 {0x0210, 0x6297}, 313 {0x0211, 0xa004}, 314 {0x0212, 0x0365}, 315 {0x0213, 0xf7ff}, 316 {0x0214, 0xf24c}, 317 {0x0215, 0x0102}, 318 {0x0216, 0x00a3}, 319 {0x0217, 0x0048}, 320 {0x0218, 0xa2c0}, 321 {0x0219, 0x0400}, 322 {0x021a, 0x00c8}, 323 {0x021b, 0x00c0}, 324 {0x021c, 0x0000}, 325 {0x021d, 0x024c}, 326 {0x02fa, 0x0000}, 327 {0x02fb, 0x0000}, 328 {0x02fc, 0x0000}, 329 {0x03fe, 0x0000}, 330 {0x03ff, 0x0000}, 331 {0x0500, 0x0000}, 332 {0x0600, 0x0000}, 333 {0x0610, 0x6666}, 334 {0x0611, 0xa9aa}, 335 {0x0620, 0x6666}, 336 {0x0621, 0xa9aa}, 337 {0x0630, 0x6666}, 338 {0x0631, 0xa9aa}, 339 {0x0640, 0x6666}, 340 {0x0641, 0xa9aa}, 341 {0x07fa, 0x0000}, 342 {0x08fa, 0x0000}, 343 {0x08fb, 0x0000}, 344 {0x0d00, 0x0000}, 345 {0x1100, 0x0000}, 346 {0x1101, 0x0000}, 347 {0x1102, 0x0000}, 348 {0x1103, 0x0000}, 349 {0x1104, 0x0000}, 350 {0x1105, 0x0000}, 351 {0x1106, 0x0000}, 352 {0x1107, 0x0000}, 353 {0x1108, 0x0000}, 354 {0x1109, 0x0000}, 355 {0x110a, 0x0000}, 356 {0x110b, 0x0000}, 357 {0x110c, 0x0000}, 358 {0x1111, 0x0000}, 359 {0x1112, 0x0000}, 360 {0x1113, 0x0000}, 361 {0x1114, 0x0000}, 362 {0x1115, 0x0000}, 363 {0x1116, 0x0000}, 364 {0x1117, 0x0000}, 365 {0x1118, 0x0000}, 366 {0x1119, 0x0000}, 367 {0x111a, 0x0000}, 368 {0x111b, 0x0000}, 369 {0x111c, 0x0000}, 370 {0x1401, 0x0404}, 371 {0x1402, 0x0007}, 372 {0x1403, 0x0365}, 373 {0x1404, 0x0210}, 374 {0x1405, 0x0365}, 375 {0x1406, 0x0210}, 376 {0x1407, 0x0000}, 377 {0x1408, 0x0000}, 378 {0x1409, 0x0000}, 379 {0x140a, 0x0000}, 380 {0x140b, 0x0000}, 381 {0x140c, 0x0000}, 382 {0x140d, 0x0000}, 383 {0x140e, 0x0000}, 384 {0x140f, 0x0000}, 385 {0x1410, 0x0000}, 386 {0x1411, 0x0000}, 387 {0x1801, 0x0004}, 388 {0x1802, 0x0000}, 389 {0x1803, 0x0000}, 390 {0x1804, 0x0000}, 391 {0x1805, 0x00ff}, 392 {0x2c00, 0x0000}, 393 {0x3400, 0x0200}, 394 {0x3404, 0x0000}, 395 {0x3405, 0x0000}, 396 {0x3406, 0x0000}, 397 {0x3407, 0x0000}, 398 {0x3408, 0x0000}, 399 {0x3409, 0x0000}, 400 {0x340a, 0x0000}, 401 {0x340b, 0x0000}, 402 {0x340c, 0x0000}, 403 {0x340d, 0x0000}, 404 {0x340e, 0x0000}, 405 {0x340f, 0x0000}, 406 {0x3410, 0x0000}, 407 {0x3411, 0x0000}, 408 {0x3412, 0x0000}, 409 {0x3413, 0x0000}, 410 {0x3414, 0x0000}, 411 {0x3415, 0x0000}, 412 {0x3424, 0x0000}, 413 {0x3425, 0x0000}, 414 {0x3426, 0x0000}, 415 {0x3427, 0x0000}, 416 {0x3428, 0x0000}, 417 {0x3429, 0x0000}, 418 {0x342a, 0x0000}, 419 {0x342b, 0x0000}, 420 {0x342c, 0x0000}, 421 {0x342d, 0x0000}, 422 {0x342e, 0x0000}, 423 {0x342f, 0x0000}, 424 {0x3430, 0x0000}, 425 {0x3431, 0x0000}, 426 {0x3432, 0x0000}, 427 {0x3433, 0x0000}, 428 {0x3434, 0x0000}, 429 {0x3435, 0x0000}, 430 {0x3440, 0x6319}, 431 {0x3441, 0x3771}, 432 {0x3500, 0x0002}, 433 {0x3501, 0x5728}, 434 {0x3b00, 0x3010}, 435 {0x3b01, 0x3300}, 436 {0x3b02, 0x2200}, 437 {0x3b03, 0x0100}, 438 }; 439 440 static bool rt5682s_volatile_register(struct device *dev, unsigned int reg) 441 { 442 switch (reg) { 443 case RT5682S_RESET: 444 case RT5682S_CBJ_CTRL_2: 445 case RT5682S_I2S1_F_DIV_CTRL_2: 446 case RT5682S_I2S2_F_DIV_CTRL_2: 447 case RT5682S_INT_ST_1: 448 case RT5682S_GPIO_ST: 449 case RT5682S_IL_CMD_1: 450 case RT5682S_4BTN_IL_CMD_1: 451 case RT5682S_AJD1_CTRL: 452 case RT5682S_VERSION_ID...RT5682S_DEVICE_ID: 453 case RT5682S_STO_NG2_CTRL_1: 454 case RT5682S_STO_NG2_CTRL_5...RT5682S_STO_NG2_CTRL_7: 455 case RT5682S_STO1_DAC_SIL_DET: 456 case RT5682S_HP_IMP_SENS_CTRL_1...RT5682S_HP_IMP_SENS_CTRL_4: 457 case RT5682S_HP_IMP_SENS_CTRL_13: 458 case RT5682S_HP_IMP_SENS_CTRL_14: 459 case RT5682S_HP_IMP_SENS_CTRL_43...RT5682S_HP_IMP_SENS_CTRL_46: 460 case RT5682S_HP_CALIB_CTRL_1: 461 case RT5682S_HP_CALIB_CTRL_10: 462 case RT5682S_HP_CALIB_ST_1...RT5682S_HP_CALIB_ST_11: 463 case RT5682S_SAR_IL_CMD_2...RT5682S_SAR_IL_CMD_5: 464 case RT5682S_SAR_IL_CMD_10: 465 case RT5682S_SAR_IL_CMD_11: 466 case RT5682S_VERSION_ID_HIDE: 467 case RT5682S_VERSION_ID_CUS: 468 case RT5682S_I2C_TRANS_CTRL: 469 case RT5682S_DMIC_FLOAT_DET: 470 case RT5682S_HA_CMP_OP_1: 471 case RT5682S_NEW_CBJ_DET_CTL_10...RT5682S_NEW_CBJ_DET_CTL_16: 472 case RT5682S_CLK_SW_TEST_1: 473 case RT5682S_CLK_SW_TEST_2: 474 case RT5682S_EFUSE_READ_1...RT5682S_EFUSE_READ_18: 475 case RT5682S_PILOT_DIG_CTL_1: 476 return true; 477 default: 478 return false; 479 } 480 } 481 482 static bool rt5682s_readable_register(struct device *dev, unsigned int reg) 483 { 484 switch (reg) { 485 case RT5682S_RESET: 486 case RT5682S_VERSION_ID: 487 case RT5682S_VENDOR_ID: 488 case RT5682S_DEVICE_ID: 489 case RT5682S_HP_CTRL_1: 490 case RT5682S_HP_CTRL_2: 491 case RT5682S_HPL_GAIN: 492 case RT5682S_HPR_GAIN: 493 case RT5682S_I2C_CTRL: 494 case RT5682S_CBJ_BST_CTRL: 495 case RT5682S_CBJ_DET_CTRL: 496 case RT5682S_CBJ_CTRL_1...RT5682S_CBJ_CTRL_8: 497 case RT5682S_DAC1_DIG_VOL: 498 case RT5682S_STO1_ADC_DIG_VOL: 499 case RT5682S_STO1_ADC_BOOST: 500 case RT5682S_HP_IMP_GAIN_1: 501 case RT5682S_HP_IMP_GAIN_2: 502 case RT5682S_SIDETONE_CTRL: 503 case RT5682S_STO1_ADC_MIXER: 504 case RT5682S_AD_DA_MIXER: 505 case RT5682S_STO1_DAC_MIXER: 506 case RT5682S_A_DAC1_MUX: 507 case RT5682S_DIG_INF2_DATA: 508 case RT5682S_REC_MIXER: 509 case RT5682S_CAL_REC: 510 case RT5682S_HP_ANA_OST_CTRL_1...RT5682S_HP_ANA_OST_CTRL_3: 511 case RT5682S_PWR_DIG_1...RT5682S_PWR_MIXER: 512 case RT5682S_MB_CTRL: 513 case RT5682S_CLK_GATE_TCON_1...RT5682S_CLK_GATE_TCON_3: 514 case RT5682S_CLK_DET...RT5682S_LPF_AD_DMIC: 515 case RT5682S_I2S1_SDP: 516 case RT5682S_I2S2_SDP: 517 case RT5682S_ADDA_CLK_1: 518 case RT5682S_ADDA_CLK_2: 519 case RT5682S_I2S1_F_DIV_CTRL_1: 520 case RT5682S_I2S1_F_DIV_CTRL_2: 521 case RT5682S_TDM_CTRL: 522 case RT5682S_TDM_ADDA_CTRL_1: 523 case RT5682S_TDM_ADDA_CTRL_2: 524 case RT5682S_DATA_SEL_CTRL_1: 525 case RT5682S_TDM_TCON_CTRL_1: 526 case RT5682S_TDM_TCON_CTRL_2: 527 case RT5682S_GLB_CLK: 528 case RT5682S_PLL_TRACK_1...RT5682S_PLL_TRACK_6: 529 case RT5682S_PLL_TRACK_11: 530 case RT5682S_DEPOP_1: 531 case RT5682S_HP_CHARGE_PUMP_1: 532 case RT5682S_HP_CHARGE_PUMP_2: 533 case RT5682S_HP_CHARGE_PUMP_3: 534 case RT5682S_MICBIAS_1...RT5682S_MICBIAS_3: 535 case RT5682S_PLL_TRACK_12...RT5682S_PLL_CTRL_7: 536 case RT5682S_RC_CLK_CTRL: 537 case RT5682S_I2S2_M_CLK_CTRL_1: 538 case RT5682S_I2S2_F_DIV_CTRL_1: 539 case RT5682S_I2S2_F_DIV_CTRL_2: 540 case RT5682S_IRQ_CTRL_1...RT5682S_IRQ_CTRL_4: 541 case RT5682S_INT_ST_1: 542 case RT5682S_GPIO_CTRL_1: 543 case RT5682S_GPIO_CTRL_2: 544 case RT5682S_GPIO_ST: 545 case RT5682S_HP_AMP_DET_CTRL_1: 546 case RT5682S_MID_HP_AMP_DET: 547 case RT5682S_LOW_HP_AMP_DET: 548 case RT5682S_DELAY_BUF_CTRL: 549 case RT5682S_SV_ZCD_1: 550 case RT5682S_SV_ZCD_2: 551 case RT5682S_IL_CMD_1...RT5682S_IL_CMD_6: 552 case RT5682S_4BTN_IL_CMD_1...RT5682S_4BTN_IL_CMD_7: 553 case RT5682S_ADC_STO1_HP_CTRL_1: 554 case RT5682S_ADC_STO1_HP_CTRL_2: 555 case RT5682S_AJD1_CTRL: 556 case RT5682S_JD_CTRL_1: 557 case RT5682S_DUMMY_1...RT5682S_DUMMY_3: 558 case RT5682S_DAC_ADC_DIG_VOL1: 559 case RT5682S_BIAS_CUR_CTRL_2...RT5682S_BIAS_CUR_CTRL_10: 560 case RT5682S_VREF_REC_OP_FB_CAP_CTRL_1: 561 case RT5682S_VREF_REC_OP_FB_CAP_CTRL_2: 562 case RT5682S_CHARGE_PUMP_1: 563 case RT5682S_DIG_IN_CTRL_1: 564 case RT5682S_PAD_DRIVING_CTRL: 565 case RT5682S_CHOP_DAC_1: 566 case RT5682S_CHOP_DAC_2: 567 case RT5682S_CHOP_ADC: 568 case RT5682S_CALIB_ADC_CTRL: 569 case RT5682S_VOL_TEST: 570 case RT5682S_SPKVDD_DET_ST: 571 case RT5682S_TEST_MODE_CTRL_1...RT5682S_TEST_MODE_CTRL_4: 572 case RT5682S_PLL_INTERNAL_1...RT5682S_PLL_INTERNAL_4: 573 case RT5682S_STO_NG2_CTRL_1...RT5682S_STO_NG2_CTRL_10: 574 case RT5682S_STO1_DAC_SIL_DET: 575 case RT5682S_SIL_PSV_CTRL1: 576 case RT5682S_SIL_PSV_CTRL2: 577 case RT5682S_SIL_PSV_CTRL3: 578 case RT5682S_SIL_PSV_CTRL4: 579 case RT5682S_SIL_PSV_CTRL5: 580 case RT5682S_HP_IMP_SENS_CTRL_1...RT5682S_HP_IMP_SENS_CTRL_46: 581 case RT5682S_HP_LOGIC_CTRL_1...RT5682S_HP_LOGIC_CTRL_3: 582 case RT5682S_HP_CALIB_CTRL_1...RT5682S_HP_CALIB_CTRL_11: 583 case RT5682S_HP_CALIB_ST_1...RT5682S_HP_CALIB_ST_11: 584 case RT5682S_SAR_IL_CMD_1...RT5682S_SAR_IL_CMD_14: 585 case RT5682S_DUMMY_4...RT5682S_DUMMY_6: 586 case RT5682S_VERSION_ID_HIDE: 587 case RT5682S_VERSION_ID_CUS: 588 case RT5682S_SCAN_CTL: 589 case RT5682S_HP_AMP_DET: 590 case RT5682S_BIAS_CUR_CTRL_11: 591 case RT5682S_BIAS_CUR_CTRL_12: 592 case RT5682S_BIAS_CUR_CTRL_13: 593 case RT5682S_BIAS_CUR_CTRL_14: 594 case RT5682S_BIAS_CUR_CTRL_15: 595 case RT5682S_BIAS_CUR_CTRL_16: 596 case RT5682S_BIAS_CUR_CTRL_17: 597 case RT5682S_BIAS_CUR_CTRL_18: 598 case RT5682S_I2C_TRANS_CTRL: 599 case RT5682S_DUMMY_7: 600 case RT5682S_DUMMY_8: 601 case RT5682S_DMIC_FLOAT_DET: 602 case RT5682S_HA_CMP_OP_1...RT5682S_HA_CMP_OP_13: 603 case RT5682S_HA_CMP_OP_14...RT5682S_HA_CMP_OP_25: 604 case RT5682S_NEW_CBJ_DET_CTL_1...RT5682S_NEW_CBJ_DET_CTL_16: 605 case RT5682S_DA_FILTER_1...RT5682S_DA_FILTER_5: 606 case RT5682S_CLK_SW_TEST_1: 607 case RT5682S_CLK_SW_TEST_2: 608 case RT5682S_CLK_SW_TEST_3...RT5682S_CLK_SW_TEST_14: 609 case RT5682S_EFUSE_MANU_WRITE_1...RT5682S_EFUSE_MANU_WRITE_6: 610 case RT5682S_EFUSE_READ_1...RT5682S_EFUSE_READ_18: 611 case RT5682S_EFUSE_TIMING_CTL_1: 612 case RT5682S_EFUSE_TIMING_CTL_2: 613 case RT5682S_PILOT_DIG_CTL_1: 614 case RT5682S_PILOT_DIG_CTL_2: 615 case RT5682S_HP_AMP_DET_CTL_1...RT5682S_HP_AMP_DET_CTL_4: 616 return true; 617 default: 618 return false; 619 } 620 } 621 622 static void rt5682s_reset(struct rt5682s_priv *rt5682s) 623 { 624 regmap_write(rt5682s->regmap, RT5682S_RESET, 0); 625 } 626 627 static int rt5682s_button_detect(struct snd_soc_component *component) 628 { 629 int btn_type, val; 630 631 val = snd_soc_component_read(component, RT5682S_4BTN_IL_CMD_1); 632 btn_type = val & 0xfff0; 633 snd_soc_component_write(component, RT5682S_4BTN_IL_CMD_1, val); 634 dev_dbg(component->dev, "%s btn_type=%x\n", __func__, btn_type); 635 snd_soc_component_update_bits(component, RT5682S_SAR_IL_CMD_2, 636 RT5682S_SAR_ADC_PSV_MASK, RT5682S_SAR_ADC_PSV_ENTRY); 637 638 return btn_type; 639 } 640 641 enum { 642 SAR_PWR_OFF, 643 SAR_PWR_NORMAL, 644 SAR_PWR_SAVING, 645 }; 646 647 static void rt5682s_sar_power_mode(struct snd_soc_component *component, 648 int mode, int jd_step) 649 { 650 struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component); 651 652 mutex_lock(&rt5682s->sar_mutex); 653 654 switch (mode) { 655 case SAR_PWR_SAVING: 656 snd_soc_component_update_bits(component, RT5682S_CBJ_CTRL_3, 657 RT5682S_CBJ_IN_BUF_MASK, RT5682S_CBJ_IN_BUF_DIS); 658 snd_soc_component_update_bits(component, RT5682S_CBJ_CTRL_1, 659 RT5682S_MB1_PATH_MASK | RT5682S_MB2_PATH_MASK, 660 RT5682S_CTRL_MB1_REG | RT5682S_CTRL_MB2_REG); 661 snd_soc_component_update_bits(component, RT5682S_SAR_IL_CMD_1, 662 RT5682S_SAR_BUTDET_MASK | RT5682S_SAR_BUTDET_POW_MASK | 663 RT5682S_SAR_SEL_MB1_2_CTL_MASK, RT5682S_SAR_BUTDET_DIS | 664 RT5682S_SAR_BUTDET_POW_SAV | RT5682S_SAR_SEL_MB1_2_MANU); 665 usleep_range(5000, 5500); 666 snd_soc_component_update_bits(component, RT5682S_SAR_IL_CMD_1, 667 RT5682S_SAR_BUTDET_MASK, RT5682S_SAR_BUTDET_EN); 668 usleep_range(5000, 5500); 669 snd_soc_component_update_bits(component, RT5682S_SAR_IL_CMD_2, 670 RT5682S_SAR_ADC_PSV_MASK, RT5682S_SAR_ADC_PSV_ENTRY); 671 break; 672 case SAR_PWR_NORMAL: 673 snd_soc_component_update_bits(component, RT5682S_CBJ_CTRL_3, 674 RT5682S_CBJ_IN_BUF_MASK, RT5682S_CBJ_IN_BUF_EN); 675 snd_soc_component_update_bits(component, RT5682S_CBJ_CTRL_1, 676 RT5682S_MB1_PATH_MASK | RT5682S_MB2_PATH_MASK, 677 RT5682S_CTRL_MB1_FSM | RT5682S_CTRL_MB2_FSM); 678 if (!jd_step) { 679 snd_soc_component_update_bits(component, RT5682S_SAR_IL_CMD_1, 680 RT5682S_SAR_SEL_MB1_2_CTL_MASK, RT5682S_SAR_SEL_MB1_2_AUTO); 681 usleep_range(5000, 5500); 682 snd_soc_component_update_bits(component, RT5682S_SAR_IL_CMD_1, 683 RT5682S_SAR_BUTDET_MASK | RT5682S_SAR_BUTDET_POW_MASK, 684 RT5682S_SAR_BUTDET_EN | RT5682S_SAR_BUTDET_POW_NORM); 685 } 686 break; 687 case SAR_PWR_OFF: 688 snd_soc_component_update_bits(component, RT5682S_SAR_IL_CMD_1, 689 RT5682S_SAR_BUTDET_MASK | RT5682S_SAR_BUTDET_POW_MASK | 690 RT5682S_SAR_SEL_MB1_2_CTL_MASK, RT5682S_SAR_BUTDET_DIS | 691 RT5682S_SAR_BUTDET_POW_SAV | RT5682S_SAR_SEL_MB1_2_MANU); 692 break; 693 default: 694 dev_err(component->dev, "Invalid SAR Power mode: %d\n", mode); 695 break; 696 } 697 698 mutex_unlock(&rt5682s->sar_mutex); 699 } 700 701 static void rt5682s_enable_push_button_irq(struct snd_soc_component *component) 702 { 703 snd_soc_component_update_bits(component, RT5682S_SAR_IL_CMD_13, 704 RT5682S_SAR_SOUR_MASK, RT5682S_SAR_SOUR_BTN); 705 snd_soc_component_write(component, RT5682S_IL_CMD_1, 0x0040); 706 snd_soc_component_update_bits(component, RT5682S_4BTN_IL_CMD_2, 707 RT5682S_4BTN_IL_MASK | RT5682S_4BTN_IL_RST_MASK, 708 RT5682S_4BTN_IL_EN | RT5682S_4BTN_IL_NOR); 709 snd_soc_component_update_bits(component, RT5682S_IRQ_CTRL_3, 710 RT5682S_IL_IRQ_MASK, RT5682S_IL_IRQ_EN); 711 } 712 713 static void rt5682s_disable_push_button_irq(struct snd_soc_component *component) 714 { 715 snd_soc_component_update_bits(component, RT5682S_IRQ_CTRL_3, 716 RT5682S_IL_IRQ_MASK, RT5682S_IL_IRQ_DIS); 717 snd_soc_component_update_bits(component, RT5682S_4BTN_IL_CMD_2, 718 RT5682S_4BTN_IL_MASK, RT5682S_4BTN_IL_DIS); 719 snd_soc_component_update_bits(component, RT5682S_SAR_IL_CMD_13, 720 RT5682S_SAR_SOUR_MASK, RT5682S_SAR_SOUR_TYPE); 721 } 722 723 /** 724 * rt5682s_headset_detect - Detect headset. 725 * @component: SoC audio component device. 726 * @jack_insert: Jack insert or not. 727 * 728 * Detect whether is headset or not when jack inserted. 729 * 730 * Returns detect status. 731 */ 732 static int rt5682s_headset_detect(struct snd_soc_component *component, int jack_insert) 733 { 734 unsigned int val, count; 735 int jack_type = 0; 736 737 if (jack_insert) { 738 rt5682s_disable_push_button_irq(component); 739 snd_soc_component_update_bits(component, RT5682S_PWR_ANLG_1, 740 RT5682S_PWR_VREF1 | RT5682S_PWR_VREF2 | RT5682S_PWR_MB, 741 RT5682S_PWR_VREF1 | RT5682S_PWR_VREF2 | RT5682S_PWR_MB); 742 snd_soc_component_update_bits(component, RT5682S_PWR_ANLG_1, 743 RT5682S_PWR_FV1 | RT5682S_PWR_FV2, 0); 744 usleep_range(15000, 20000); 745 snd_soc_component_update_bits(component, RT5682S_PWR_ANLG_1, 746 RT5682S_PWR_FV1 | RT5682S_PWR_FV2, 747 RT5682S_PWR_FV1 | RT5682S_PWR_FV2); 748 snd_soc_component_update_bits(component, RT5682S_PWR_ANLG_3, 749 RT5682S_PWR_CBJ, RT5682S_PWR_CBJ); 750 snd_soc_component_write(component, RT5682S_SAR_IL_CMD_3, 0x0365); 751 snd_soc_component_update_bits(component, RT5682S_HP_CHARGE_PUMP_2, 752 RT5682S_OSW_L_MASK | RT5682S_OSW_R_MASK, 753 RT5682S_OSW_L_DIS | RT5682S_OSW_R_DIS); 754 snd_soc_component_update_bits(component, RT5682S_SAR_IL_CMD_13, 755 RT5682S_SAR_SOUR_MASK, RT5682S_SAR_SOUR_TYPE); 756 rt5682s_sar_power_mode(component, SAR_PWR_NORMAL, 1); 757 snd_soc_component_update_bits(component, RT5682S_CBJ_CTRL_1, 758 RT5682S_TRIG_JD_MASK, RT5682S_TRIG_JD_LOW); 759 usleep_range(45000, 50000); 760 snd_soc_component_update_bits(component, RT5682S_CBJ_CTRL_1, 761 RT5682S_TRIG_JD_MASK, RT5682S_TRIG_JD_HIGH); 762 763 count = 0; 764 do { 765 usleep_range(10000, 15000); 766 val = snd_soc_component_read(component, RT5682S_CBJ_CTRL_2) 767 & RT5682S_JACK_TYPE_MASK; 768 count++; 769 } while (val == 0 && count < 50); 770 771 dev_dbg(component->dev, "%s, val=%d, count=%d\n", __func__, val, count); 772 773 switch (val) { 774 case 0x1: 775 case 0x2: 776 jack_type = SND_JACK_HEADSET; 777 snd_soc_component_write(component, RT5682S_SAR_IL_CMD_3, 0x024c); 778 snd_soc_component_update_bits(component, RT5682S_CBJ_CTRL_1, 779 RT5682S_FAST_OFF_MASK, RT5682S_FAST_OFF_EN); 780 snd_soc_component_update_bits(component, RT5682S_SAR_IL_CMD_1, 781 RT5682S_SAR_SEL_MB1_2_MASK, val << RT5682S_SAR_SEL_MB1_2_SFT); 782 if (!snd_soc_dapm_get_pin_status(&component->dapm, "SAR")) 783 rt5682s_sar_power_mode(component, SAR_PWR_SAVING, 1); 784 rt5682s_enable_push_button_irq(component); 785 break; 786 default: 787 jack_type = SND_JACK_HEADPHONE; 788 break; 789 } 790 snd_soc_component_update_bits(component, RT5682S_HP_CHARGE_PUMP_2, 791 RT5682S_OSW_L_MASK | RT5682S_OSW_R_MASK, 792 RT5682S_OSW_L_EN | RT5682S_OSW_R_EN); 793 usleep_range(35000, 40000); 794 } else { 795 rt5682s_sar_power_mode(component, SAR_PWR_OFF, 1); 796 rt5682s_disable_push_button_irq(component); 797 snd_soc_component_update_bits(component, RT5682S_CBJ_CTRL_1, 798 RT5682S_TRIG_JD_MASK, RT5682S_TRIG_JD_LOW); 799 800 if (!snd_soc_dapm_get_pin_status(&component->dapm, "MICBIAS")) 801 snd_soc_component_update_bits(component, 802 RT5682S_PWR_ANLG_1, RT5682S_PWR_MB, 0); 803 if (!snd_soc_dapm_get_pin_status(&component->dapm, "Vref2")) 804 snd_soc_component_update_bits(component, 805 RT5682S_PWR_ANLG_1, RT5682S_PWR_VREF2, 0); 806 807 snd_soc_component_update_bits(component, RT5682S_PWR_ANLG_3, 808 RT5682S_PWR_CBJ, 0); 809 snd_soc_component_update_bits(component, RT5682S_CBJ_CTRL_1, 810 RT5682S_FAST_OFF_MASK, RT5682S_FAST_OFF_DIS); 811 snd_soc_component_update_bits(component, RT5682S_CBJ_CTRL_3, 812 RT5682S_CBJ_IN_BUF_MASK, RT5682S_CBJ_IN_BUF_DIS); 813 jack_type = 0; 814 } 815 816 dev_dbg(component->dev, "jack_type = %d\n", jack_type); 817 818 return jack_type; 819 } 820 821 static void rt5682s_jack_detect_handler(struct work_struct *work) 822 { 823 struct rt5682s_priv *rt5682s = 824 container_of(work, struct rt5682s_priv, jack_detect_work.work); 825 int val, btn_type; 826 827 if (!rt5682s->component || !rt5682s->component->card || 828 !rt5682s->component->card->instantiated) { 829 /* card not yet ready, try later */ 830 mod_delayed_work(system_power_efficient_wq, 831 &rt5682s->jack_detect_work, msecs_to_jiffies(15)); 832 return; 833 } 834 835 mutex_lock(&rt5682s->jdet_mutex); 836 mutex_lock(&rt5682s->calibrate_mutex); 837 838 val = snd_soc_component_read(rt5682s->component, RT5682S_AJD1_CTRL) 839 & RT5682S_JDH_RS_MASK; 840 if (!val) { 841 /* jack in */ 842 if (rt5682s->jack_type == 0) { 843 /* jack was out, report jack type */ 844 rt5682s->jack_type = rt5682s_headset_detect(rt5682s->component, 1); 845 rt5682s->irq_work_delay_time = 0; 846 } else if ((rt5682s->jack_type & SND_JACK_HEADSET) == SND_JACK_HEADSET) { 847 /* jack is already in, report button event */ 848 rt5682s->jack_type = SND_JACK_HEADSET; 849 btn_type = rt5682s_button_detect(rt5682s->component); 850 /** 851 * rt5682s can report three kinds of button behavior, 852 * one click, double click and hold. However, 853 * currently we will report button pressed/released 854 * event. So all the three button behaviors are 855 * treated as button pressed. 856 */ 857 switch (btn_type) { 858 case 0x8000: 859 case 0x4000: 860 case 0x2000: 861 rt5682s->jack_type |= SND_JACK_BTN_0; 862 break; 863 case 0x1000: 864 case 0x0800: 865 case 0x0400: 866 rt5682s->jack_type |= SND_JACK_BTN_1; 867 break; 868 case 0x0200: 869 case 0x0100: 870 case 0x0080: 871 rt5682s->jack_type |= SND_JACK_BTN_2; 872 break; 873 case 0x0040: 874 case 0x0020: 875 case 0x0010: 876 rt5682s->jack_type |= SND_JACK_BTN_3; 877 break; 878 case 0x0000: /* unpressed */ 879 break; 880 default: 881 dev_err(rt5682s->component->dev, 882 "Unexpected button code 0x%04x\n", btn_type); 883 break; 884 } 885 } 886 } else { 887 /* jack out */ 888 rt5682s->jack_type = rt5682s_headset_detect(rt5682s->component, 0); 889 rt5682s->irq_work_delay_time = 50; 890 } 891 892 snd_soc_jack_report(rt5682s->hs_jack, rt5682s->jack_type, 893 SND_JACK_HEADSET | SND_JACK_BTN_0 | SND_JACK_BTN_1 | 894 SND_JACK_BTN_2 | SND_JACK_BTN_3); 895 896 if (rt5682s->jack_type & (SND_JACK_BTN_0 | SND_JACK_BTN_1 | 897 SND_JACK_BTN_2 | SND_JACK_BTN_3)) 898 schedule_delayed_work(&rt5682s->jd_check_work, 0); 899 else 900 cancel_delayed_work_sync(&rt5682s->jd_check_work); 901 902 mutex_unlock(&rt5682s->calibrate_mutex); 903 mutex_unlock(&rt5682s->jdet_mutex); 904 } 905 906 static void rt5682s_jd_check_handler(struct work_struct *work) 907 { 908 struct rt5682s_priv *rt5682s = 909 container_of(work, struct rt5682s_priv, jd_check_work.work); 910 911 if (snd_soc_component_read(rt5682s->component, RT5682S_AJD1_CTRL) 912 & RT5682S_JDH_RS_MASK) { 913 /* jack out */ 914 rt5682s->jack_type = rt5682s_headset_detect(rt5682s->component, 0); 915 916 snd_soc_jack_report(rt5682s->hs_jack, rt5682s->jack_type, 917 SND_JACK_HEADSET | SND_JACK_BTN_0 | SND_JACK_BTN_1 | 918 SND_JACK_BTN_2 | SND_JACK_BTN_3); 919 } else { 920 schedule_delayed_work(&rt5682s->jd_check_work, 500); 921 } 922 } 923 924 static irqreturn_t rt5682s_irq(int irq, void *data) 925 { 926 struct rt5682s_priv *rt5682s = data; 927 928 mod_delayed_work(system_power_efficient_wq, &rt5682s->jack_detect_work, 929 msecs_to_jiffies(rt5682s->irq_work_delay_time)); 930 931 return IRQ_HANDLED; 932 } 933 934 static int rt5682s_set_jack_detect(struct snd_soc_component *component, 935 struct snd_soc_jack *hs_jack, void *data) 936 { 937 struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component); 938 int btndet_delay = 16; 939 940 rt5682s->hs_jack = hs_jack; 941 942 if (!hs_jack) { 943 regmap_update_bits(rt5682s->regmap, RT5682S_IRQ_CTRL_2, 944 RT5682S_JD1_EN_MASK, RT5682S_JD1_DIS); 945 regmap_update_bits(rt5682s->regmap, RT5682S_RC_CLK_CTRL, 946 RT5682S_POW_JDH, 0); 947 cancel_delayed_work_sync(&rt5682s->jack_detect_work); 948 949 return 0; 950 } 951 952 switch (rt5682s->pdata.jd_src) { 953 case RT5682S_JD1: 954 regmap_update_bits(rt5682s->regmap, RT5682S_CBJ_CTRL_5, 955 RT5682S_JD_FAST_OFF_SRC_MASK, RT5682S_JD_FAST_OFF_SRC_JDH); 956 regmap_update_bits(rt5682s->regmap, RT5682S_CBJ_CTRL_2, 957 RT5682S_EXT_JD_SRC, RT5682S_EXT_JD_SRC_MANUAL); 958 regmap_update_bits(rt5682s->regmap, RT5682S_CBJ_CTRL_1, 959 RT5682S_EMB_JD_MASK | RT5682S_DET_TYPE | 960 RT5682S_POL_FAST_OFF_MASK | RT5682S_MIC_CAP_MASK, 961 RT5682S_EMB_JD_EN | RT5682S_DET_TYPE | 962 RT5682S_POL_FAST_OFF_HIGH | RT5682S_MIC_CAP_HS); 963 regmap_update_bits(rt5682s->regmap, RT5682S_SAR_IL_CMD_1, 964 RT5682S_SAR_POW_MASK, RT5682S_SAR_POW_EN); 965 regmap_update_bits(rt5682s->regmap, RT5682S_GPIO_CTRL_1, 966 RT5682S_GP1_PIN_MASK, RT5682S_GP1_PIN_IRQ); 967 regmap_update_bits(rt5682s->regmap, RT5682S_PWR_ANLG_3, 968 RT5682S_PWR_BGLDO, RT5682S_PWR_BGLDO); 969 regmap_update_bits(rt5682s->regmap, RT5682S_PWR_ANLG_2, 970 RT5682S_PWR_JD_MASK, RT5682S_PWR_JD_ENABLE); 971 regmap_update_bits(rt5682s->regmap, RT5682S_RC_CLK_CTRL, 972 RT5682S_POW_IRQ | RT5682S_POW_JDH, RT5682S_POW_IRQ | RT5682S_POW_JDH); 973 regmap_update_bits(rt5682s->regmap, RT5682S_IRQ_CTRL_2, 974 RT5682S_JD1_EN_MASK | RT5682S_JD1_POL_MASK, 975 RT5682S_JD1_EN | RT5682S_JD1_POL_NOR); 976 regmap_update_bits(rt5682s->regmap, RT5682S_4BTN_IL_CMD_4, 977 RT5682S_4BTN_IL_HOLD_WIN_MASK | RT5682S_4BTN_IL_CLICK_WIN_MASK, 978 (btndet_delay << RT5682S_4BTN_IL_HOLD_WIN_SFT | btndet_delay)); 979 regmap_update_bits(rt5682s->regmap, RT5682S_4BTN_IL_CMD_5, 980 RT5682S_4BTN_IL_HOLD_WIN_MASK | RT5682S_4BTN_IL_CLICK_WIN_MASK, 981 (btndet_delay << RT5682S_4BTN_IL_HOLD_WIN_SFT | btndet_delay)); 982 regmap_update_bits(rt5682s->regmap, RT5682S_4BTN_IL_CMD_6, 983 RT5682S_4BTN_IL_HOLD_WIN_MASK | RT5682S_4BTN_IL_CLICK_WIN_MASK, 984 (btndet_delay << RT5682S_4BTN_IL_HOLD_WIN_SFT | btndet_delay)); 985 regmap_update_bits(rt5682s->regmap, RT5682S_4BTN_IL_CMD_7, 986 RT5682S_4BTN_IL_HOLD_WIN_MASK | RT5682S_4BTN_IL_CLICK_WIN_MASK, 987 (btndet_delay << RT5682S_4BTN_IL_HOLD_WIN_SFT | btndet_delay)); 988 989 mod_delayed_work(system_power_efficient_wq, 990 &rt5682s->jack_detect_work, msecs_to_jiffies(250)); 991 break; 992 993 case RT5682S_JD_NULL: 994 regmap_update_bits(rt5682s->regmap, RT5682S_IRQ_CTRL_2, 995 RT5682S_JD1_EN_MASK, RT5682S_JD1_DIS); 996 regmap_update_bits(rt5682s->regmap, RT5682S_RC_CLK_CTRL, 997 RT5682S_POW_JDH, 0); 998 break; 999 1000 default: 1001 dev_warn(component->dev, "Wrong JD source\n"); 1002 break; 1003 } 1004 1005 return 0; 1006 } 1007 1008 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -9562, 75, 0); 1009 static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0); 1010 static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0); 1011 static const DECLARE_TLV_DB_SCALE(cbj_bst_tlv, -1200, 150, 0); 1012 1013 static const struct snd_kcontrol_new rt5682s_snd_controls[] = { 1014 /* DAC Digital Volume */ 1015 SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5682S_DAC1_DIG_VOL, 1016 RT5682S_L_VOL_SFT + 1, RT5682S_R_VOL_SFT + 1, 127, 0, dac_vol_tlv), 1017 1018 /* CBJ Boost Volume */ 1019 SOC_SINGLE_TLV("CBJ Boost Volume", RT5682S_REC_MIXER, 1020 RT5682S_BST_CBJ_SFT, 35, 0, cbj_bst_tlv), 1021 1022 /* ADC Digital Volume Control */ 1023 SOC_DOUBLE("STO1 ADC Capture Switch", RT5682S_STO1_ADC_DIG_VOL, 1024 RT5682S_L_MUTE_SFT, RT5682S_R_MUTE_SFT, 1, 1), 1025 SOC_DOUBLE_TLV("STO1 ADC Capture Volume", RT5682S_STO1_ADC_DIG_VOL, 1026 RT5682S_L_VOL_SFT + 1, RT5682S_R_VOL_SFT + 1, 63, 0, adc_vol_tlv), 1027 1028 /* ADC Boost Volume Control */ 1029 SOC_DOUBLE_TLV("STO1 ADC Boost Gain Volume", RT5682S_STO1_ADC_BOOST, 1030 RT5682S_STO1_ADC_L_BST_SFT, RT5682S_STO1_ADC_R_BST_SFT, 3, 0, adc_bst_tlv), 1031 }; 1032 1033 /** 1034 * rt5682s_sel_asrc_clk_src - select ASRC clock source for a set of filters 1035 * @component: SoC audio component device. 1036 * @filter_mask: mask of filters. 1037 * @clk_src: clock source 1038 * 1039 * The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5682S can 1040 * only support standard 32fs or 64fs i2s format, ASRC should be enabled to 1041 * support special i2s clock format such as Intel's 100fs(100 * sampling rate). 1042 * ASRC function will track i2s clock and generate a corresponding system clock 1043 * for codec. This function provides an API to select the clock source for a 1044 * set of filters specified by the mask. And the component driver will turn on 1045 * ASRC for these filters if ASRC is selected as their clock source. 1046 */ 1047 int rt5682s_sel_asrc_clk_src(struct snd_soc_component *component, 1048 unsigned int filter_mask, unsigned int clk_src) 1049 { 1050 switch (clk_src) { 1051 case RT5682S_CLK_SEL_SYS: 1052 case RT5682S_CLK_SEL_I2S1_ASRC: 1053 case RT5682S_CLK_SEL_I2S2_ASRC: 1054 break; 1055 1056 default: 1057 return -EINVAL; 1058 } 1059 1060 if (filter_mask & RT5682S_DA_STEREO1_FILTER) { 1061 snd_soc_component_update_bits(component, RT5682S_PLL_TRACK_2, 1062 RT5682S_FILTER_CLK_SEL_MASK, clk_src << RT5682S_FILTER_CLK_SEL_SFT); 1063 } 1064 1065 if (filter_mask & RT5682S_AD_STEREO1_FILTER) { 1066 snd_soc_component_update_bits(component, RT5682S_PLL_TRACK_3, 1067 RT5682S_FILTER_CLK_SEL_MASK, clk_src << RT5682S_FILTER_CLK_SEL_SFT); 1068 } 1069 1070 snd_soc_component_update_bits(component, RT5682S_PLL_TRACK_11, 1071 RT5682S_ASRCIN_AUTO_CLKOUT_MASK, RT5682S_ASRCIN_AUTO_CLKOUT_EN); 1072 1073 return 0; 1074 } 1075 EXPORT_SYMBOL_GPL(rt5682s_sel_asrc_clk_src); 1076 1077 static int rt5682s_div_sel(struct rt5682s_priv *rt5682s, 1078 int target, const int div[], int size) 1079 { 1080 int i; 1081 1082 if (rt5682s->sysclk < target) { 1083 dev_err(rt5682s->component->dev, 1084 "sysclk rate %d is too low\n", rt5682s->sysclk); 1085 return 0; 1086 } 1087 1088 for (i = 0; i < size - 1; i++) { 1089 dev_dbg(rt5682s->component->dev, "div[%d]=%d\n", i, div[i]); 1090 if (target * div[i] == rt5682s->sysclk) 1091 return i; 1092 if (target * div[i + 1] > rt5682s->sysclk) { 1093 dev_dbg(rt5682s->component->dev, 1094 "can't find div for sysclk %d\n", rt5682s->sysclk); 1095 return i; 1096 } 1097 } 1098 1099 if (target * div[i] < rt5682s->sysclk) 1100 dev_err(rt5682s->component->dev, 1101 "sysclk rate %d is too high\n", rt5682s->sysclk); 1102 1103 return size - 1; 1104 } 1105 1106 static int get_clk_info(int sclk, int rate) 1107 { 1108 int i; 1109 static const int pd[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32, 48}; 1110 1111 if (sclk <= 0 || rate <= 0) 1112 return -EINVAL; 1113 1114 rate = rate << 8; 1115 for (i = 0; i < ARRAY_SIZE(pd); i++) 1116 if (sclk == rate * pd[i]) 1117 return i; 1118 1119 return -EINVAL; 1120 } 1121 1122 /** 1123 * set_dmic_clk - Set parameter of dmic. 1124 * 1125 * @w: DAPM widget. 1126 * @kcontrol: The kcontrol of this widget. 1127 * @event: Event id. 1128 * 1129 * Choose dmic clock between 1MHz and 3MHz. 1130 * It is better for clock to approximate 3MHz. 1131 */ 1132 static int set_dmic_clk(struct snd_soc_dapm_widget *w, 1133 struct snd_kcontrol *kcontrol, int event) 1134 { 1135 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1136 struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component); 1137 int idx, dmic_clk_rate = 3072000; 1138 static const int div[] = {2, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, 128}; 1139 1140 if (rt5682s->pdata.dmic_clk_rate) 1141 dmic_clk_rate = rt5682s->pdata.dmic_clk_rate; 1142 1143 idx = rt5682s_div_sel(rt5682s, dmic_clk_rate, div, ARRAY_SIZE(div)); 1144 1145 snd_soc_component_update_bits(component, RT5682S_DMIC_CTRL_1, 1146 RT5682S_DMIC_CLK_MASK, idx << RT5682S_DMIC_CLK_SFT); 1147 1148 return 0; 1149 } 1150 1151 static int set_filter_clk(struct snd_soc_dapm_widget *w, 1152 struct snd_kcontrol *kcontrol, int event) 1153 { 1154 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1155 struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component); 1156 int ref, val, reg, idx; 1157 static const int div_f[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32, 48}; 1158 static const int div_o[] = {1, 2, 4, 6, 8, 12, 16, 24, 32, 48}; 1159 1160 val = snd_soc_component_read(component, RT5682S_GPIO_CTRL_1) 1161 & RT5682S_GP4_PIN_MASK; 1162 1163 if (w->shift == RT5682S_PWR_ADC_S1F_BIT && val == RT5682S_GP4_PIN_ADCDAT2) 1164 ref = 256 * rt5682s->lrck[RT5682S_AIF2]; 1165 else 1166 ref = 256 * rt5682s->lrck[RT5682S_AIF1]; 1167 1168 idx = rt5682s_div_sel(rt5682s, ref, div_f, ARRAY_SIZE(div_f)); 1169 1170 if (w->shift == RT5682S_PWR_ADC_S1F_BIT) 1171 reg = RT5682S_PLL_TRACK_3; 1172 else 1173 reg = RT5682S_PLL_TRACK_2; 1174 1175 snd_soc_component_update_bits(component, reg, 1176 RT5682S_FILTER_CLK_DIV_MASK, idx << RT5682S_FILTER_CLK_DIV_SFT); 1177 1178 /* select over sample rate */ 1179 for (idx = 0; idx < ARRAY_SIZE(div_o); idx++) { 1180 if (rt5682s->sysclk <= 12288000 * div_o[idx]) 1181 break; 1182 } 1183 1184 snd_soc_component_update_bits(component, RT5682S_ADDA_CLK_1, 1185 RT5682S_ADC_OSR_MASK | RT5682S_DAC_OSR_MASK, 1186 (idx << RT5682S_ADC_OSR_SFT) | (idx << RT5682S_DAC_OSR_SFT)); 1187 1188 return 0; 1189 } 1190 1191 static int set_dmic_power(struct snd_soc_dapm_widget *w, 1192 struct snd_kcontrol *kcontrol, int event) 1193 { 1194 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1195 struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component); 1196 unsigned int delay = 50, val; 1197 1198 if (rt5682s->pdata.dmic_delay) 1199 delay = rt5682s->pdata.dmic_delay; 1200 1201 switch (event) { 1202 case SND_SOC_DAPM_POST_PMU: 1203 val = (snd_soc_component_read(component, RT5682S_GLB_CLK) 1204 & RT5682S_SCLK_SRC_MASK) >> RT5682S_SCLK_SRC_SFT; 1205 if (val == RT5682S_CLK_SRC_PLL1 || val == RT5682S_CLK_SRC_PLL2) 1206 snd_soc_component_update_bits(component, RT5682S_PWR_ANLG_1, 1207 RT5682S_PWR_VREF2 | RT5682S_PWR_MB, 1208 RT5682S_PWR_VREF2 | RT5682S_PWR_MB); 1209 1210 /*Add delay to avoid pop noise*/ 1211 msleep(delay); 1212 break; 1213 1214 case SND_SOC_DAPM_POST_PMD: 1215 if (!rt5682s->jack_type) { 1216 if (!snd_soc_dapm_get_pin_status(w->dapm, "MICBIAS")) 1217 snd_soc_component_update_bits(component, 1218 RT5682S_PWR_ANLG_1, RT5682S_PWR_MB, 0); 1219 if (!snd_soc_dapm_get_pin_status(w->dapm, "Vref2")) 1220 snd_soc_component_update_bits(component, 1221 RT5682S_PWR_ANLG_1, RT5682S_PWR_VREF2, 0); 1222 } 1223 break; 1224 } 1225 1226 return 0; 1227 } 1228 1229 static int set_i2s_clk(struct snd_soc_dapm_widget *w, 1230 struct snd_kcontrol *kcontrol, int event) 1231 { 1232 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1233 struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component); 1234 int pre_div, id; 1235 unsigned int reg, mask, sft; 1236 1237 if (event != SND_SOC_DAPM_PRE_PMU) 1238 return 0; 1239 1240 if (w->shift == RT5682S_PWR_I2S2_BIT) { 1241 id = RT5682S_AIF2; 1242 reg = RT5682S_I2S2_M_CLK_CTRL_1; 1243 mask = RT5682S_I2S2_M_D_MASK; 1244 sft = RT5682S_I2S2_M_D_SFT; 1245 } else { 1246 id = RT5682S_AIF1; 1247 reg = RT5682S_ADDA_CLK_1; 1248 mask = RT5682S_I2S_M_D_MASK; 1249 sft = RT5682S_I2S_M_D_SFT; 1250 } 1251 1252 if (!rt5682s->master[id]) 1253 return 0; 1254 1255 pre_div = get_clk_info(rt5682s->sysclk, rt5682s->lrck[id]); 1256 if (pre_div < 0) { 1257 dev_err(component->dev, "get pre_div failed\n"); 1258 return -EINVAL; 1259 } 1260 1261 dev_dbg(component->dev, "lrck is %dHz and pre_div is %d for iis %d master\n", 1262 rt5682s->lrck[id], pre_div, id); 1263 snd_soc_component_update_bits(component, reg, mask, pre_div << sft); 1264 1265 return 0; 1266 } 1267 1268 static int is_sys_clk_from_plla(struct snd_soc_dapm_widget *w, 1269 struct snd_soc_dapm_widget *sink) 1270 { 1271 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1272 struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component); 1273 1274 if ((rt5682s->sysclk_src == RT5682S_CLK_SRC_PLL1) || 1275 (rt5682s->sysclk_src == RT5682S_CLK_SRC_PLL2 && rt5682s->pll_comb == USE_PLLAB)) 1276 return 1; 1277 1278 return 0; 1279 } 1280 1281 static int is_sys_clk_from_pllb(struct snd_soc_dapm_widget *w, 1282 struct snd_soc_dapm_widget *sink) 1283 { 1284 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1285 struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component); 1286 1287 if (rt5682s->sysclk_src == RT5682S_CLK_SRC_PLL2) 1288 return 1; 1289 1290 return 0; 1291 } 1292 1293 static int is_using_asrc(struct snd_soc_dapm_widget *w, 1294 struct snd_soc_dapm_widget *sink) 1295 { 1296 unsigned int reg, sft, val; 1297 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1298 1299 switch (w->shift) { 1300 case RT5682S_ADC_STO1_ASRC_SFT: 1301 reg = RT5682S_PLL_TRACK_3; 1302 sft = RT5682S_FILTER_CLK_SEL_SFT; 1303 break; 1304 case RT5682S_DAC_STO1_ASRC_SFT: 1305 reg = RT5682S_PLL_TRACK_2; 1306 sft = RT5682S_FILTER_CLK_SEL_SFT; 1307 break; 1308 default: 1309 return 0; 1310 } 1311 1312 val = (snd_soc_component_read(component, reg) >> sft) & 0xf; 1313 switch (val) { 1314 case RT5682S_CLK_SEL_I2S1_ASRC: 1315 case RT5682S_CLK_SEL_I2S2_ASRC: 1316 return 1; 1317 default: 1318 return 0; 1319 } 1320 } 1321 1322 static int rt5682s_hp_amp_event(struct snd_soc_dapm_widget *w, 1323 struct snd_kcontrol *kcontrol, int event) 1324 { 1325 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1326 struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component); 1327 1328 switch (event) { 1329 case SND_SOC_DAPM_POST_PMU: 1330 snd_soc_component_update_bits(component, RT5682S_DEPOP_1, 1331 RT5682S_OUT_HP_L_EN | RT5682S_OUT_HP_R_EN, 1332 RT5682S_OUT_HP_L_EN | RT5682S_OUT_HP_R_EN); 1333 usleep_range(15000, 20000); 1334 snd_soc_component_update_bits(component, RT5682S_DEPOP_1, 1335 RT5682S_LDO_PUMP_EN | RT5682S_PUMP_EN | 1336 RT5682S_CAPLESS_L_EN | RT5682S_CAPLESS_R_EN, 1337 RT5682S_LDO_PUMP_EN | RT5682S_PUMP_EN | 1338 RT5682S_CAPLESS_L_EN | RT5682S_CAPLESS_R_EN); 1339 snd_soc_component_write(component, RT5682S_BIAS_CUR_CTRL_11, 0x6666); 1340 snd_soc_component_write(component, RT5682S_BIAS_CUR_CTRL_12, 0xa82a); 1341 1342 mutex_lock(&rt5682s->jdet_mutex); 1343 1344 snd_soc_component_update_bits(component, RT5682S_HP_CTRL_2, 1345 RT5682S_HPO_L_PATH_MASK | RT5682S_HPO_R_PATH_MASK | 1346 RT5682S_HPO_SEL_IP_EN_SW, RT5682S_HPO_L_PATH_EN | 1347 RT5682S_HPO_R_PATH_EN | RT5682S_HPO_IP_EN_GATING); 1348 usleep_range(5000, 10000); 1349 snd_soc_component_update_bits(component, RT5682S_HP_AMP_DET_CTL_1, 1350 RT5682S_CP_SW_SIZE_MASK, RT5682S_CP_SW_SIZE_L | RT5682S_CP_SW_SIZE_S); 1351 1352 mutex_unlock(&rt5682s->jdet_mutex); 1353 break; 1354 1355 case SND_SOC_DAPM_POST_PMD: 1356 snd_soc_component_update_bits(component, RT5682S_HP_CTRL_2, 1357 RT5682S_HPO_L_PATH_MASK | RT5682S_HPO_R_PATH_MASK | 1358 RT5682S_HPO_SEL_IP_EN_SW, 0); 1359 snd_soc_component_update_bits(component, RT5682S_HP_AMP_DET_CTL_1, 1360 RT5682S_CP_SW_SIZE_MASK, RT5682S_CP_SW_SIZE_M); 1361 snd_soc_component_update_bits(component, RT5682S_DEPOP_1, 1362 RT5682S_LDO_PUMP_EN | RT5682S_PUMP_EN | 1363 RT5682S_CAPLESS_L_EN | RT5682S_CAPLESS_R_EN, 0); 1364 snd_soc_component_update_bits(component, RT5682S_DEPOP_1, 1365 RT5682S_OUT_HP_L_EN | RT5682S_OUT_HP_R_EN, 0); 1366 break; 1367 } 1368 1369 return 0; 1370 } 1371 1372 static int rt5682s_stereo1_adc_mixl_event(struct snd_soc_dapm_widget *w, 1373 struct snd_kcontrol *kcontrol, int event) 1374 { 1375 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1376 struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component); 1377 unsigned int delay = 0; 1378 1379 if (rt5682s->pdata.amic_delay) 1380 delay = rt5682s->pdata.amic_delay; 1381 1382 switch (event) { 1383 case SND_SOC_DAPM_POST_PMU: 1384 msleep(delay); 1385 snd_soc_component_update_bits(component, RT5682S_STO1_ADC_DIG_VOL, 1386 RT5682S_L_MUTE, 0); 1387 break; 1388 case SND_SOC_DAPM_PRE_PMD: 1389 snd_soc_component_update_bits(component, RT5682S_STO1_ADC_DIG_VOL, 1390 RT5682S_L_MUTE, RT5682S_L_MUTE); 1391 break; 1392 } 1393 1394 return 0; 1395 } 1396 1397 static int sar_power_event(struct snd_soc_dapm_widget *w, 1398 struct snd_kcontrol *kcontrol, int event) 1399 { 1400 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1401 struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component); 1402 1403 if ((rt5682s->jack_type & SND_JACK_HEADSET) != SND_JACK_HEADSET) 1404 return 0; 1405 1406 switch (event) { 1407 case SND_SOC_DAPM_PRE_PMU: 1408 rt5682s_sar_power_mode(component, SAR_PWR_NORMAL, 0); 1409 break; 1410 case SND_SOC_DAPM_POST_PMD: 1411 rt5682s_sar_power_mode(component, SAR_PWR_SAVING, 0); 1412 break; 1413 } 1414 1415 return 0; 1416 } 1417 1418 /* Interface data select */ 1419 static const char * const rt5682s_data_select[] = { 1420 "L/R", "R/L", "L/L", "R/R" 1421 }; 1422 1423 static SOC_ENUM_SINGLE_DECL(rt5682s_if2_adc_enum, RT5682S_DIG_INF2_DATA, 1424 RT5682S_IF2_ADC_SEL_SFT, rt5682s_data_select); 1425 1426 static SOC_ENUM_SINGLE_DECL(rt5682s_if1_01_adc_enum, RT5682S_TDM_ADDA_CTRL_1, 1427 RT5682S_IF1_ADC1_SEL_SFT, rt5682s_data_select); 1428 1429 static SOC_ENUM_SINGLE_DECL(rt5682s_if1_23_adc_enum, RT5682S_TDM_ADDA_CTRL_1, 1430 RT5682S_IF1_ADC2_SEL_SFT, rt5682s_data_select); 1431 1432 static SOC_ENUM_SINGLE_DECL(rt5682s_if1_45_adc_enum, RT5682S_TDM_ADDA_CTRL_1, 1433 RT5682S_IF1_ADC3_SEL_SFT, rt5682s_data_select); 1434 1435 static SOC_ENUM_SINGLE_DECL(rt5682s_if1_67_adc_enum, RT5682S_TDM_ADDA_CTRL_1, 1436 RT5682S_IF1_ADC4_SEL_SFT, rt5682s_data_select); 1437 1438 static const struct snd_kcontrol_new rt5682s_if2_adc_swap_mux = 1439 SOC_DAPM_ENUM("IF2 ADC Swap Mux", rt5682s_if2_adc_enum); 1440 1441 static const struct snd_kcontrol_new rt5682s_if1_01_adc_swap_mux = 1442 SOC_DAPM_ENUM("IF1 01 ADC Swap Mux", rt5682s_if1_01_adc_enum); 1443 1444 static const struct snd_kcontrol_new rt5682s_if1_23_adc_swap_mux = 1445 SOC_DAPM_ENUM("IF1 23 ADC Swap Mux", rt5682s_if1_23_adc_enum); 1446 1447 static const struct snd_kcontrol_new rt5682s_if1_45_adc_swap_mux = 1448 SOC_DAPM_ENUM("IF1 45 ADC Swap Mux", rt5682s_if1_45_adc_enum); 1449 1450 static const struct snd_kcontrol_new rt5682s_if1_67_adc_swap_mux = 1451 SOC_DAPM_ENUM("IF1 67 ADC Swap Mux", rt5682s_if1_67_adc_enum); 1452 1453 /* Digital Mixer */ 1454 static const struct snd_kcontrol_new rt5682s_sto1_adc_l_mix[] = { 1455 SOC_DAPM_SINGLE("ADC1 Switch", RT5682S_STO1_ADC_MIXER, 1456 RT5682S_M_STO1_ADC_L1_SFT, 1, 1), 1457 SOC_DAPM_SINGLE("ADC2 Switch", RT5682S_STO1_ADC_MIXER, 1458 RT5682S_M_STO1_ADC_L2_SFT, 1, 1), 1459 }; 1460 1461 static const struct snd_kcontrol_new rt5682s_sto1_adc_r_mix[] = { 1462 SOC_DAPM_SINGLE("ADC1 Switch", RT5682S_STO1_ADC_MIXER, 1463 RT5682S_M_STO1_ADC_R1_SFT, 1, 1), 1464 SOC_DAPM_SINGLE("ADC2 Switch", RT5682S_STO1_ADC_MIXER, 1465 RT5682S_M_STO1_ADC_R2_SFT, 1, 1), 1466 }; 1467 1468 static const struct snd_kcontrol_new rt5682s_dac_l_mix[] = { 1469 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5682S_AD_DA_MIXER, 1470 RT5682S_M_ADCMIX_L_SFT, 1, 1), 1471 SOC_DAPM_SINGLE("DAC1 Switch", RT5682S_AD_DA_MIXER, 1472 RT5682S_M_DAC1_L_SFT, 1, 1), 1473 }; 1474 1475 static const struct snd_kcontrol_new rt5682s_dac_r_mix[] = { 1476 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5682S_AD_DA_MIXER, 1477 RT5682S_M_ADCMIX_R_SFT, 1, 1), 1478 SOC_DAPM_SINGLE("DAC1 Switch", RT5682S_AD_DA_MIXER, 1479 RT5682S_M_DAC1_R_SFT, 1, 1), 1480 }; 1481 1482 static const struct snd_kcontrol_new rt5682s_sto1_dac_l_mix[] = { 1483 SOC_DAPM_SINGLE("DAC L1 Switch", RT5682S_STO1_DAC_MIXER, 1484 RT5682S_M_DAC_L1_STO_L_SFT, 1, 1), 1485 SOC_DAPM_SINGLE("DAC R1 Switch", RT5682S_STO1_DAC_MIXER, 1486 RT5682S_M_DAC_R1_STO_L_SFT, 1, 1), 1487 }; 1488 1489 static const struct snd_kcontrol_new rt5682s_sto1_dac_r_mix[] = { 1490 SOC_DAPM_SINGLE("DAC L1 Switch", RT5682S_STO1_DAC_MIXER, 1491 RT5682S_M_DAC_L1_STO_R_SFT, 1, 1), 1492 SOC_DAPM_SINGLE("DAC R1 Switch", RT5682S_STO1_DAC_MIXER, 1493 RT5682S_M_DAC_R1_STO_R_SFT, 1, 1), 1494 }; 1495 1496 /* Analog Input Mixer */ 1497 static const struct snd_kcontrol_new rt5682s_rec1_l_mix[] = { 1498 SOC_DAPM_SINGLE("CBJ Switch", RT5682S_REC_MIXER, 1499 RT5682S_M_CBJ_RM1_L_SFT, 1, 1), 1500 }; 1501 1502 static const struct snd_kcontrol_new rt5682s_rec1_r_mix[] = { 1503 SOC_DAPM_SINGLE("CBJ Switch", RT5682S_REC_MIXER, 1504 RT5682S_M_CBJ_RM1_R_SFT, 1, 1), 1505 }; 1506 1507 /* STO1 ADC1 Source */ 1508 /* MX-26 [13] [5] */ 1509 static const char * const rt5682s_sto1_adc1_src[] = { 1510 "DAC MIX", "ADC" 1511 }; 1512 1513 static SOC_ENUM_SINGLE_DECL(rt5682s_sto1_adc1l_enum, RT5682S_STO1_ADC_MIXER, 1514 RT5682S_STO1_ADC1L_SRC_SFT, rt5682s_sto1_adc1_src); 1515 1516 static const struct snd_kcontrol_new rt5682s_sto1_adc1l_mux = 1517 SOC_DAPM_ENUM("Stereo1 ADC1L Source", rt5682s_sto1_adc1l_enum); 1518 1519 static SOC_ENUM_SINGLE_DECL(rt5682s_sto1_adc1r_enum, RT5682S_STO1_ADC_MIXER, 1520 RT5682S_STO1_ADC1R_SRC_SFT, rt5682s_sto1_adc1_src); 1521 1522 static const struct snd_kcontrol_new rt5682s_sto1_adc1r_mux = 1523 SOC_DAPM_ENUM("Stereo1 ADC1L Source", rt5682s_sto1_adc1r_enum); 1524 1525 /* STO1 ADC Source */ 1526 /* MX-26 [11:10] [3:2] */ 1527 static const char * const rt5682s_sto1_adc_src[] = { 1528 "ADC1 L", "ADC1 R" 1529 }; 1530 1531 static SOC_ENUM_SINGLE_DECL(rt5682s_sto1_adcl_enum, RT5682S_STO1_ADC_MIXER, 1532 RT5682S_STO1_ADCL_SRC_SFT, rt5682s_sto1_adc_src); 1533 1534 static const struct snd_kcontrol_new rt5682s_sto1_adcl_mux = 1535 SOC_DAPM_ENUM("Stereo1 ADCL Source", rt5682s_sto1_adcl_enum); 1536 1537 static SOC_ENUM_SINGLE_DECL(rt5682s_sto1_adcr_enum, RT5682S_STO1_ADC_MIXER, 1538 RT5682S_STO1_ADCR_SRC_SFT, rt5682s_sto1_adc_src); 1539 1540 static const struct snd_kcontrol_new rt5682s_sto1_adcr_mux = 1541 SOC_DAPM_ENUM("Stereo1 ADCR Source", rt5682s_sto1_adcr_enum); 1542 1543 /* STO1 ADC2 Source */ 1544 /* MX-26 [12] [4] */ 1545 static const char * const rt5682s_sto1_adc2_src[] = { 1546 "DAC MIX", "DMIC" 1547 }; 1548 1549 static SOC_ENUM_SINGLE_DECL(rt5682s_sto1_adc2l_enum, RT5682S_STO1_ADC_MIXER, 1550 RT5682S_STO1_ADC2L_SRC_SFT, rt5682s_sto1_adc2_src); 1551 1552 static const struct snd_kcontrol_new rt5682s_sto1_adc2l_mux = 1553 SOC_DAPM_ENUM("Stereo1 ADC2L Source", rt5682s_sto1_adc2l_enum); 1554 1555 static SOC_ENUM_SINGLE_DECL(rt5682s_sto1_adc2r_enum, RT5682S_STO1_ADC_MIXER, 1556 RT5682S_STO1_ADC2R_SRC_SFT, rt5682s_sto1_adc2_src); 1557 1558 static const struct snd_kcontrol_new rt5682s_sto1_adc2r_mux = 1559 SOC_DAPM_ENUM("Stereo1 ADC2R Source", rt5682s_sto1_adc2r_enum); 1560 1561 /* MX-79 [6:4] I2S1 ADC data location */ 1562 static const unsigned int rt5682s_if1_adc_slot_values[] = { 1563 0, 2, 4, 6, 1564 }; 1565 1566 static const char * const rt5682s_if1_adc_slot_src[] = { 1567 "Slot 0", "Slot 2", "Slot 4", "Slot 6" 1568 }; 1569 1570 static SOC_VALUE_ENUM_SINGLE_DECL(rt5682s_if1_adc_slot_enum, 1571 RT5682S_TDM_CTRL, RT5682S_TDM_ADC_LCA_SFT, RT5682S_TDM_ADC_LCA_MASK, 1572 rt5682s_if1_adc_slot_src, rt5682s_if1_adc_slot_values); 1573 1574 static const struct snd_kcontrol_new rt5682s_if1_adc_slot_mux = 1575 SOC_DAPM_ENUM("IF1 ADC Slot location", rt5682s_if1_adc_slot_enum); 1576 1577 /* Analog DAC L1 Source, Analog DAC R1 Source*/ 1578 /* MX-2B [4], MX-2B [0]*/ 1579 static const char * const rt5682s_alg_dac1_src[] = { 1580 "Stereo1 DAC Mixer", "DAC1" 1581 }; 1582 1583 static SOC_ENUM_SINGLE_DECL(rt5682s_alg_dac_l1_enum, RT5682S_A_DAC1_MUX, 1584 RT5682S_A_DACL1_SFT, rt5682s_alg_dac1_src); 1585 1586 static const struct snd_kcontrol_new rt5682s_alg_dac_l1_mux = 1587 SOC_DAPM_ENUM("Analog DAC L1 Source", rt5682s_alg_dac_l1_enum); 1588 1589 static SOC_ENUM_SINGLE_DECL(rt5682s_alg_dac_r1_enum, RT5682S_A_DAC1_MUX, 1590 RT5682S_A_DACR1_SFT, rt5682s_alg_dac1_src); 1591 1592 static const struct snd_kcontrol_new rt5682s_alg_dac_r1_mux = 1593 SOC_DAPM_ENUM("Analog DAC R1 Source", rt5682s_alg_dac_r1_enum); 1594 1595 static const unsigned int rt5682s_adcdat_pin_values[] = { 1596 1, 3, 1597 }; 1598 1599 static const char * const rt5682s_adcdat_pin_select[] = { 1600 "ADCDAT1", "ADCDAT2", 1601 }; 1602 1603 static SOC_VALUE_ENUM_SINGLE_DECL(rt5682s_adcdat_pin_enum, 1604 RT5682S_GPIO_CTRL_1, RT5682S_GP4_PIN_SFT, RT5682S_GP4_PIN_MASK, 1605 rt5682s_adcdat_pin_select, rt5682s_adcdat_pin_values); 1606 1607 static const struct snd_kcontrol_new rt5682s_adcdat_pin_ctrl = 1608 SOC_DAPM_ENUM("ADCDAT", rt5682s_adcdat_pin_enum); 1609 1610 static const struct snd_soc_dapm_widget rt5682s_dapm_widgets[] = { 1611 SND_SOC_DAPM_SUPPLY("LDO MB1", RT5682S_PWR_ANLG_3, 1612 RT5682S_PWR_LDO_MB1_BIT, 0, NULL, 0), 1613 SND_SOC_DAPM_SUPPLY("LDO MB2", RT5682S_PWR_ANLG_3, 1614 RT5682S_PWR_LDO_MB2_BIT, 0, NULL, 0), 1615 SND_SOC_DAPM_SUPPLY("LDO", RT5682S_PWR_ANLG_3, 1616 RT5682S_PWR_LDO_BIT, 0, NULL, 0), 1617 SND_SOC_DAPM_SUPPLY("Vref2", SND_SOC_NOPM, 0, 0, NULL, 0), 1618 SND_SOC_DAPM_SUPPLY("MICBIAS", SND_SOC_NOPM, 0, 0, NULL, 0), 1619 1620 /* PLL Powers */ 1621 SND_SOC_DAPM_SUPPLY_S("PLLA_LDO", 0, RT5682S_PWR_ANLG_3, 1622 RT5682S_PWR_LDO_PLLA_BIT, 0, NULL, 0), 1623 SND_SOC_DAPM_SUPPLY_S("PLLB_LDO", 0, RT5682S_PWR_ANLG_3, 1624 RT5682S_PWR_LDO_PLLB_BIT, 0, NULL, 0), 1625 SND_SOC_DAPM_SUPPLY_S("PLLA_BIAS", 0, RT5682S_PWR_ANLG_3, 1626 RT5682S_PWR_BIAS_PLLA_BIT, 0, NULL, 0), 1627 SND_SOC_DAPM_SUPPLY_S("PLLB_BIAS", 0, RT5682S_PWR_ANLG_3, 1628 RT5682S_PWR_BIAS_PLLB_BIT, 0, NULL, 0), 1629 SND_SOC_DAPM_SUPPLY_S("PLLA", 0, RT5682S_PWR_ANLG_3, 1630 RT5682S_PWR_PLLA_BIT, 0, NULL, 0), 1631 SND_SOC_DAPM_SUPPLY_S("PLLB", 0, RT5682S_PWR_ANLG_3, 1632 RT5682S_PWR_PLLB_BIT, 0, set_filter_clk, SND_SOC_DAPM_PRE_PMU), 1633 SND_SOC_DAPM_SUPPLY_S("PLLA_RST", 1, RT5682S_PWR_ANLG_3, 1634 RT5682S_RSTB_PLLA_BIT, 0, NULL, 0), 1635 SND_SOC_DAPM_SUPPLY_S("PLLB_RST", 1, RT5682S_PWR_ANLG_3, 1636 RT5682S_RSTB_PLLB_BIT, 0, NULL, 0), 1637 1638 /* ASRC */ 1639 SND_SOC_DAPM_SUPPLY_S("DAC STO1 ASRC", 1, RT5682S_PLL_TRACK_1, 1640 RT5682S_DAC_STO1_ASRC_SFT, 0, NULL, 0), 1641 SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5682S_PLL_TRACK_1, 1642 RT5682S_ADC_STO1_ASRC_SFT, 0, NULL, 0), 1643 SND_SOC_DAPM_SUPPLY_S("AD ASRC", 1, RT5682S_PLL_TRACK_1, 1644 RT5682S_AD_ASRC_SFT, 0, NULL, 0), 1645 SND_SOC_DAPM_SUPPLY_S("DA ASRC", 1, RT5682S_PLL_TRACK_1, 1646 RT5682S_DA_ASRC_SFT, 0, NULL, 0), 1647 SND_SOC_DAPM_SUPPLY_S("DMIC ASRC", 1, RT5682S_PLL_TRACK_1, 1648 RT5682S_DMIC_ASRC_SFT, 0, NULL, 0), 1649 1650 /* Input Side */ 1651 SND_SOC_DAPM_SUPPLY("MICBIAS1", RT5682S_PWR_ANLG_2, 1652 RT5682S_PWR_MB1_BIT, 0, NULL, 0), 1653 SND_SOC_DAPM_SUPPLY("MICBIAS2", RT5682S_PWR_ANLG_2, 1654 RT5682S_PWR_MB2_BIT, 0, NULL, 0), 1655 1656 /* Input Lines */ 1657 SND_SOC_DAPM_INPUT("DMIC L1"), 1658 SND_SOC_DAPM_INPUT("DMIC R1"), 1659 1660 SND_SOC_DAPM_INPUT("IN1P"), 1661 1662 SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0, 1663 set_dmic_clk, SND_SOC_DAPM_PRE_PMU), 1664 SND_SOC_DAPM_SUPPLY("DMIC1 Power", RT5682S_DMIC_CTRL_1, RT5682S_DMIC_1_EN_SFT, 0, 1665 set_dmic_power, SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 1666 1667 /* Boost */ 1668 SND_SOC_DAPM_PGA("BST1 CBJ", SND_SOC_NOPM, 0, 0, NULL, 0), 1669 1670 /* REC Mixer */ 1671 SND_SOC_DAPM_MIXER("RECMIX1L", SND_SOC_NOPM, 0, 0, rt5682s_rec1_l_mix, 1672 ARRAY_SIZE(rt5682s_rec1_l_mix)), 1673 SND_SOC_DAPM_MIXER("RECMIX1R", SND_SOC_NOPM, 0, 0, rt5682s_rec1_r_mix, 1674 ARRAY_SIZE(rt5682s_rec1_r_mix)), 1675 SND_SOC_DAPM_SUPPLY("RECMIX1L Power", RT5682S_CAL_REC, 1676 RT5682S_PWR_RM1_L_BIT, 0, NULL, 0), 1677 SND_SOC_DAPM_SUPPLY("RECMIX1R Power", RT5682S_CAL_REC, 1678 RT5682S_PWR_RM1_R_BIT, 0, NULL, 0), 1679 1680 /* ADCs */ 1681 SND_SOC_DAPM_ADC("ADC1 L", NULL, SND_SOC_NOPM, 0, 0), 1682 SND_SOC_DAPM_ADC("ADC1 R", NULL, SND_SOC_NOPM, 0, 0), 1683 1684 SND_SOC_DAPM_SUPPLY("ADC1 L Power", RT5682S_PWR_DIG_1, 1685 RT5682S_PWR_ADC_L1_BIT, 0, NULL, 0), 1686 SND_SOC_DAPM_SUPPLY("ADC1 R Power", RT5682S_PWR_DIG_1, 1687 RT5682S_PWR_ADC_R1_BIT, 0, NULL, 0), 1688 SND_SOC_DAPM_SUPPLY("ADC1 clock", RT5682S_CHOP_ADC, 1689 RT5682S_CKGEN_ADC1_SFT, 0, NULL, 0), 1690 1691 /* ADC Mux */ 1692 SND_SOC_DAPM_MUX("Stereo1 ADC L1 Mux", SND_SOC_NOPM, 0, 0, 1693 &rt5682s_sto1_adc1l_mux), 1694 SND_SOC_DAPM_MUX("Stereo1 ADC R1 Mux", SND_SOC_NOPM, 0, 0, 1695 &rt5682s_sto1_adc1r_mux), 1696 SND_SOC_DAPM_MUX("Stereo1 ADC L2 Mux", SND_SOC_NOPM, 0, 0, 1697 &rt5682s_sto1_adc2l_mux), 1698 SND_SOC_DAPM_MUX("Stereo1 ADC R2 Mux", SND_SOC_NOPM, 0, 0, 1699 &rt5682s_sto1_adc2r_mux), 1700 SND_SOC_DAPM_MUX("Stereo1 ADC L Mux", SND_SOC_NOPM, 0, 0, 1701 &rt5682s_sto1_adcl_mux), 1702 SND_SOC_DAPM_MUX("Stereo1 ADC R Mux", SND_SOC_NOPM, 0, 0, 1703 &rt5682s_sto1_adcr_mux), 1704 SND_SOC_DAPM_MUX("IF1_ADC Mux", SND_SOC_NOPM, 0, 0, 1705 &rt5682s_if1_adc_slot_mux), 1706 1707 /* ADC Mixer */ 1708 SND_SOC_DAPM_SUPPLY("ADC Stereo1 Filter", RT5682S_PWR_DIG_2, 1709 RT5682S_PWR_ADC_S1F_BIT, 0, set_filter_clk, SND_SOC_DAPM_PRE_PMU), 1710 SND_SOC_DAPM_MIXER_E("Stereo1 ADC MIXL", SND_SOC_NOPM, 0, 0, 1711 rt5682s_sto1_adc_l_mix, ARRAY_SIZE(rt5682s_sto1_adc_l_mix), 1712 rt5682s_stereo1_adc_mixl_event, 1713 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU), 1714 SND_SOC_DAPM_MIXER("Stereo1 ADC MIXR", RT5682S_STO1_ADC_DIG_VOL, 1715 RT5682S_R_MUTE_SFT, 1, rt5682s_sto1_adc_r_mix, 1716 ARRAY_SIZE(rt5682s_sto1_adc_r_mix)), 1717 1718 /* ADC PGA */ 1719 SND_SOC_DAPM_PGA("Stereo1 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 1720 1721 /* Digital Interface */ 1722 SND_SOC_DAPM_SUPPLY("I2S1", RT5682S_PWR_DIG_1, RT5682S_PWR_I2S1_BIT, 1723 0, set_i2s_clk, SND_SOC_DAPM_PRE_PMU), 1724 SND_SOC_DAPM_SUPPLY("I2S2", RT5682S_PWR_DIG_1, RT5682S_PWR_I2S2_BIT, 1725 0, set_i2s_clk, SND_SOC_DAPM_PRE_PMU), 1726 SND_SOC_DAPM_PGA("IF1 DAC1 L", SND_SOC_NOPM, 0, 0, NULL, 0), 1727 SND_SOC_DAPM_PGA("IF1 DAC1 R", SND_SOC_NOPM, 0, 0, NULL, 0), 1728 1729 /* Digital Interface Select */ 1730 SND_SOC_DAPM_MUX("IF1 01 ADC Swap Mux", SND_SOC_NOPM, 0, 0, 1731 &rt5682s_if1_01_adc_swap_mux), 1732 SND_SOC_DAPM_MUX("IF1 23 ADC Swap Mux", SND_SOC_NOPM, 0, 0, 1733 &rt5682s_if1_23_adc_swap_mux), 1734 SND_SOC_DAPM_MUX("IF1 45 ADC Swap Mux", SND_SOC_NOPM, 0, 0, 1735 &rt5682s_if1_45_adc_swap_mux), 1736 SND_SOC_DAPM_MUX("IF1 67 ADC Swap Mux", SND_SOC_NOPM, 0, 0, 1737 &rt5682s_if1_67_adc_swap_mux), 1738 SND_SOC_DAPM_MUX("IF2 ADC Swap Mux", SND_SOC_NOPM, 0, 0, 1739 &rt5682s_if2_adc_swap_mux), 1740 1741 SND_SOC_DAPM_MUX("ADCDAT Mux", SND_SOC_NOPM, 0, 0, &rt5682s_adcdat_pin_ctrl), 1742 1743 /* Audio Interface */ 1744 SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, RT5682S_I2S1_SDP, 1745 RT5682S_SEL_ADCDAT_SFT, 1), 1746 SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, RT5682S_I2S2_SDP, 1747 RT5682S_I2S2_PIN_CFG_SFT, 1), 1748 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0), 1749 1750 /* Output Side */ 1751 /* DAC mixer before sound effect */ 1752 SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0, 1753 rt5682s_dac_l_mix, ARRAY_SIZE(rt5682s_dac_l_mix)), 1754 SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0, 1755 rt5682s_dac_r_mix, ARRAY_SIZE(rt5682s_dac_r_mix)), 1756 1757 /* DAC channel Mux */ 1758 SND_SOC_DAPM_MUX("DAC L1 Source", SND_SOC_NOPM, 0, 0, &rt5682s_alg_dac_l1_mux), 1759 SND_SOC_DAPM_MUX("DAC R1 Source", SND_SOC_NOPM, 0, 0, &rt5682s_alg_dac_r1_mux), 1760 1761 /* DAC Mixer */ 1762 SND_SOC_DAPM_SUPPLY("DAC Stereo1 Filter", RT5682S_PWR_DIG_2, 1763 RT5682S_PWR_DAC_S1F_BIT, 0, set_filter_clk, SND_SOC_DAPM_PRE_PMU), 1764 SND_SOC_DAPM_MIXER("Stereo1 DAC MIXL", SND_SOC_NOPM, 0, 0, 1765 rt5682s_sto1_dac_l_mix, ARRAY_SIZE(rt5682s_sto1_dac_l_mix)), 1766 SND_SOC_DAPM_MIXER("Stereo1 DAC MIXR", SND_SOC_NOPM, 0, 0, 1767 rt5682s_sto1_dac_r_mix, ARRAY_SIZE(rt5682s_sto1_dac_r_mix)), 1768 1769 /* DACs */ 1770 SND_SOC_DAPM_DAC("DAC L1", NULL, RT5682S_PWR_DIG_1, RT5682S_PWR_DAC_L1_BIT, 0), 1771 SND_SOC_DAPM_DAC("DAC R1", NULL, RT5682S_PWR_DIG_1, RT5682S_PWR_DAC_R1_BIT, 0), 1772 1773 /* HPO */ 1774 SND_SOC_DAPM_PGA_S("HP Amp", 1, SND_SOC_NOPM, 0, 0, rt5682s_hp_amp_event, 1775 SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_POST_PMU), 1776 1777 /* CLK DET */ 1778 SND_SOC_DAPM_SUPPLY("CLKDET SYS", RT5682S_CLK_DET, 1779 RT5682S_SYS_CLK_DET_SFT, 0, NULL, 0), 1780 SND_SOC_DAPM_SUPPLY("CLKDET PLL1", RT5682S_CLK_DET, 1781 RT5682S_PLL1_CLK_DET_SFT, 0, NULL, 0), 1782 SND_SOC_DAPM_SUPPLY("MCLK0 DET PWR", RT5682S_PWR_ANLG_2, 1783 RT5682S_PWR_MCLK0_WD_BIT, 0, NULL, 0), 1784 1785 /* SAR */ 1786 SND_SOC_DAPM_SUPPLY("SAR", SND_SOC_NOPM, 0, 0, sar_power_event, 1787 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 1788 1789 /* Output Lines */ 1790 SND_SOC_DAPM_OUTPUT("HPOL"), 1791 SND_SOC_DAPM_OUTPUT("HPOR"), 1792 }; 1793 1794 static const struct snd_soc_dapm_route rt5682s_dapm_routes[] = { 1795 /*PLL*/ 1796 {"ADC Stereo1 Filter", NULL, "PLLA", is_sys_clk_from_plla}, 1797 {"ADC Stereo1 Filter", NULL, "PLLB", is_sys_clk_from_pllb}, 1798 {"DAC Stereo1 Filter", NULL, "PLLA", is_sys_clk_from_plla}, 1799 {"DAC Stereo1 Filter", NULL, "PLLB", is_sys_clk_from_pllb}, 1800 {"PLLA", NULL, "PLLA_LDO"}, 1801 {"PLLA", NULL, "PLLA_BIAS"}, 1802 {"PLLA", NULL, "PLLA_RST"}, 1803 {"PLLB", NULL, "PLLB_LDO"}, 1804 {"PLLB", NULL, "PLLB_BIAS"}, 1805 {"PLLB", NULL, "PLLB_RST"}, 1806 1807 /*ASRC*/ 1808 {"ADC Stereo1 Filter", NULL, "ADC STO1 ASRC", is_using_asrc}, 1809 {"DAC Stereo1 Filter", NULL, "DAC STO1 ASRC", is_using_asrc}, 1810 {"ADC STO1 ASRC", NULL, "AD ASRC"}, 1811 {"ADC STO1 ASRC", NULL, "DA ASRC"}, 1812 {"DAC STO1 ASRC", NULL, "AD ASRC"}, 1813 {"DAC STO1 ASRC", NULL, "DA ASRC"}, 1814 1815 {"CLKDET SYS", NULL, "MCLK0 DET PWR"}, 1816 1817 {"BST1 CBJ", NULL, "IN1P"}, 1818 {"BST1 CBJ", NULL, "SAR"}, 1819 1820 {"RECMIX1L", "CBJ Switch", "BST1 CBJ"}, 1821 {"RECMIX1L", NULL, "RECMIX1L Power"}, 1822 {"RECMIX1R", "CBJ Switch", "BST1 CBJ"}, 1823 {"RECMIX1R", NULL, "RECMIX1R Power"}, 1824 1825 {"ADC1 L", NULL, "RECMIX1L"}, 1826 {"ADC1 L", NULL, "ADC1 L Power"}, 1827 {"ADC1 L", NULL, "ADC1 clock"}, 1828 {"ADC1 R", NULL, "RECMIX1R"}, 1829 {"ADC1 R", NULL, "ADC1 R Power"}, 1830 {"ADC1 R", NULL, "ADC1 clock"}, 1831 1832 {"DMIC L1", NULL, "DMIC CLK"}, 1833 {"DMIC L1", NULL, "DMIC1 Power"}, 1834 {"DMIC R1", NULL, "DMIC CLK"}, 1835 {"DMIC R1", NULL, "DMIC1 Power"}, 1836 {"DMIC CLK", NULL, "DMIC ASRC"}, 1837 1838 {"Stereo1 ADC L Mux", "ADC1 L", "ADC1 L"}, 1839 {"Stereo1 ADC L Mux", "ADC1 R", "ADC1 R"}, 1840 {"Stereo1 ADC R Mux", "ADC1 L", "ADC1 L"}, 1841 {"Stereo1 ADC R Mux", "ADC1 R", "ADC1 R"}, 1842 1843 {"Stereo1 ADC L1 Mux", "ADC", "Stereo1 ADC L Mux"}, 1844 {"Stereo1 ADC L1 Mux", "DAC MIX", "Stereo1 DAC MIXL"}, 1845 {"Stereo1 ADC L2 Mux", "DMIC", "DMIC L1"}, 1846 {"Stereo1 ADC L2 Mux", "DAC MIX", "Stereo1 DAC MIXL"}, 1847 1848 {"Stereo1 ADC R1 Mux", "ADC", "Stereo1 ADC R Mux"}, 1849 {"Stereo1 ADC R1 Mux", "DAC MIX", "Stereo1 DAC MIXR"}, 1850 {"Stereo1 ADC R2 Mux", "DMIC", "DMIC R1"}, 1851 {"Stereo1 ADC R2 Mux", "DAC MIX", "Stereo1 DAC MIXR"}, 1852 1853 {"Stereo1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC L1 Mux"}, 1854 {"Stereo1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC L2 Mux"}, 1855 {"Stereo1 ADC MIXL", NULL, "ADC Stereo1 Filter"}, 1856 1857 {"Stereo1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC R1 Mux"}, 1858 {"Stereo1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC R2 Mux"}, 1859 {"Stereo1 ADC MIXR", NULL, "ADC Stereo1 Filter"}, 1860 1861 {"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXL"}, 1862 {"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXR"}, 1863 1864 {"IF1 01 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"}, 1865 {"IF1 01 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"}, 1866 {"IF1 01 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"}, 1867 {"IF1 01 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"}, 1868 {"IF1 23 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"}, 1869 {"IF1 23 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"}, 1870 {"IF1 23 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"}, 1871 {"IF1 23 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"}, 1872 {"IF1 45 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"}, 1873 {"IF1 45 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"}, 1874 {"IF1 45 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"}, 1875 {"IF1 45 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"}, 1876 {"IF1 67 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"}, 1877 {"IF1 67 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"}, 1878 {"IF1 67 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"}, 1879 {"IF1 67 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"}, 1880 1881 {"IF1_ADC Mux", "Slot 0", "IF1 01 ADC Swap Mux"}, 1882 {"IF1_ADC Mux", "Slot 2", "IF1 23 ADC Swap Mux"}, 1883 {"IF1_ADC Mux", "Slot 4", "IF1 45 ADC Swap Mux"}, 1884 {"IF1_ADC Mux", "Slot 6", "IF1 67 ADC Swap Mux"}, 1885 {"ADCDAT Mux", "ADCDAT1", "IF1_ADC Mux"}, 1886 {"AIF1TX", NULL, "I2S1"}, 1887 {"AIF1TX", NULL, "ADCDAT Mux"}, 1888 {"IF2 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"}, 1889 {"IF2 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"}, 1890 {"IF2 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"}, 1891 {"IF2 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"}, 1892 {"ADCDAT Mux", "ADCDAT2", "IF2 ADC Swap Mux"}, 1893 {"AIF2TX", NULL, "ADCDAT Mux"}, 1894 1895 {"IF1 DAC1 L", NULL, "AIF1RX"}, 1896 {"IF1 DAC1 L", NULL, "I2S1"}, 1897 {"IF1 DAC1 L", NULL, "DAC Stereo1 Filter"}, 1898 {"IF1 DAC1 R", NULL, "AIF1RX"}, 1899 {"IF1 DAC1 R", NULL, "I2S1"}, 1900 {"IF1 DAC1 R", NULL, "DAC Stereo1 Filter"}, 1901 1902 {"DAC1 MIXL", "Stereo ADC Switch", "Stereo1 ADC MIXL"}, 1903 {"DAC1 MIXL", "DAC1 Switch", "IF1 DAC1 L"}, 1904 {"DAC1 MIXR", "Stereo ADC Switch", "Stereo1 ADC MIXR"}, 1905 {"DAC1 MIXR", "DAC1 Switch", "IF1 DAC1 R"}, 1906 1907 {"Stereo1 DAC MIXL", "DAC L1 Switch", "DAC1 MIXL"}, 1908 {"Stereo1 DAC MIXL", "DAC R1 Switch", "DAC1 MIXR"}, 1909 1910 {"Stereo1 DAC MIXR", "DAC R1 Switch", "DAC1 MIXR"}, 1911 {"Stereo1 DAC MIXR", "DAC L1 Switch", "DAC1 MIXL"}, 1912 1913 {"DAC L1 Source", "DAC1", "DAC1 MIXL"}, 1914 {"DAC L1 Source", "Stereo1 DAC Mixer", "Stereo1 DAC MIXL"}, 1915 {"DAC R1 Source", "DAC1", "DAC1 MIXR"}, 1916 {"DAC R1 Source", "Stereo1 DAC Mixer", "Stereo1 DAC MIXR"}, 1917 1918 {"DAC L1", NULL, "DAC L1 Source"}, 1919 {"DAC R1", NULL, "DAC R1 Source"}, 1920 1921 {"HP Amp", NULL, "DAC L1"}, 1922 {"HP Amp", NULL, "DAC R1"}, 1923 {"HP Amp", NULL, "CLKDET SYS"}, 1924 {"HP Amp", NULL, "SAR"}, 1925 1926 {"HPOL", NULL, "HP Amp"}, 1927 {"HPOR", NULL, "HP Amp"}, 1928 }; 1929 1930 static int rt5682s_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask, 1931 unsigned int rx_mask, int slots, int slot_width) 1932 { 1933 struct snd_soc_component *component = dai->component; 1934 unsigned int cl, val = 0; 1935 1936 if (tx_mask || rx_mask) 1937 snd_soc_component_update_bits(component, 1938 RT5682S_TDM_ADDA_CTRL_2, RT5682S_TDM_EN, RT5682S_TDM_EN); 1939 else 1940 snd_soc_component_update_bits(component, 1941 RT5682S_TDM_ADDA_CTRL_2, RT5682S_TDM_EN, 0); 1942 1943 switch (slots) { 1944 case 4: 1945 val |= RT5682S_TDM_TX_CH_4; 1946 val |= RT5682S_TDM_RX_CH_4; 1947 break; 1948 case 6: 1949 val |= RT5682S_TDM_TX_CH_6; 1950 val |= RT5682S_TDM_RX_CH_6; 1951 break; 1952 case 8: 1953 val |= RT5682S_TDM_TX_CH_8; 1954 val |= RT5682S_TDM_RX_CH_8; 1955 break; 1956 case 2: 1957 break; 1958 default: 1959 return -EINVAL; 1960 } 1961 1962 snd_soc_component_update_bits(component, RT5682S_TDM_CTRL, 1963 RT5682S_TDM_TX_CH_MASK | RT5682S_TDM_RX_CH_MASK, val); 1964 1965 switch (slot_width) { 1966 case 8: 1967 if (tx_mask || rx_mask) 1968 return -EINVAL; 1969 cl = RT5682S_I2S1_TX_CHL_8 | RT5682S_I2S1_RX_CHL_8; 1970 break; 1971 case 16: 1972 val = RT5682S_TDM_CL_16; 1973 cl = RT5682S_I2S1_TX_CHL_16 | RT5682S_I2S1_RX_CHL_16; 1974 break; 1975 case 20: 1976 val = RT5682S_TDM_CL_20; 1977 cl = RT5682S_I2S1_TX_CHL_20 | RT5682S_I2S1_RX_CHL_20; 1978 break; 1979 case 24: 1980 val = RT5682S_TDM_CL_24; 1981 cl = RT5682S_I2S1_TX_CHL_24 | RT5682S_I2S1_RX_CHL_24; 1982 break; 1983 case 32: 1984 val = RT5682S_TDM_CL_32; 1985 cl = RT5682S_I2S1_TX_CHL_32 | RT5682S_I2S1_RX_CHL_32; 1986 break; 1987 default: 1988 return -EINVAL; 1989 } 1990 1991 snd_soc_component_update_bits(component, RT5682S_TDM_TCON_CTRL_1, 1992 RT5682S_TDM_CL_MASK, val); 1993 snd_soc_component_update_bits(component, RT5682S_I2S1_SDP, 1994 RT5682S_I2S1_TX_CHL_MASK | RT5682S_I2S1_RX_CHL_MASK, cl); 1995 1996 return 0; 1997 } 1998 1999 static int rt5682s_hw_params(struct snd_pcm_substream *substream, 2000 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) 2001 { 2002 struct snd_soc_component *component = dai->component; 2003 struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component); 2004 unsigned int len_1 = 0, len_2 = 0; 2005 int frame_size; 2006 2007 rt5682s->lrck[dai->id] = params_rate(params); 2008 2009 frame_size = snd_soc_params_to_frame_size(params); 2010 if (frame_size < 0) { 2011 dev_err(component->dev, "Unsupported frame size: %d\n", frame_size); 2012 return -EINVAL; 2013 } 2014 2015 switch (params_width(params)) { 2016 case 16: 2017 break; 2018 case 20: 2019 len_1 |= RT5682S_I2S1_DL_20; 2020 len_2 |= RT5682S_I2S2_DL_20; 2021 break; 2022 case 24: 2023 len_1 |= RT5682S_I2S1_DL_24; 2024 len_2 |= RT5682S_I2S2_DL_24; 2025 break; 2026 case 32: 2027 len_1 |= RT5682S_I2S1_DL_32; 2028 len_2 |= RT5682S_I2S2_DL_24; 2029 break; 2030 case 8: 2031 len_1 |= RT5682S_I2S2_DL_8; 2032 len_2 |= RT5682S_I2S2_DL_8; 2033 break; 2034 default: 2035 return -EINVAL; 2036 } 2037 2038 switch (dai->id) { 2039 case RT5682S_AIF1: 2040 snd_soc_component_update_bits(component, RT5682S_I2S1_SDP, 2041 RT5682S_I2S1_DL_MASK, len_1); 2042 if (params_channels(params) == 1) /* mono mode */ 2043 snd_soc_component_update_bits(component, RT5682S_I2S1_SDP, 2044 RT5682S_I2S1_MONO_MASK, RT5682S_I2S1_MONO_EN); 2045 else 2046 snd_soc_component_update_bits(component, RT5682S_I2S1_SDP, 2047 RT5682S_I2S1_MONO_MASK, RT5682S_I2S1_MONO_DIS); 2048 break; 2049 case RT5682S_AIF2: 2050 snd_soc_component_update_bits(component, RT5682S_I2S2_SDP, 2051 RT5682S_I2S2_DL_MASK, len_2); 2052 if (params_channels(params) == 1) /* mono mode */ 2053 snd_soc_component_update_bits(component, RT5682S_I2S2_SDP, 2054 RT5682S_I2S2_MONO_MASK, RT5682S_I2S2_MONO_EN); 2055 else 2056 snd_soc_component_update_bits(component, RT5682S_I2S2_SDP, 2057 RT5682S_I2S2_MONO_MASK, RT5682S_I2S2_MONO_DIS); 2058 break; 2059 default: 2060 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id); 2061 return -EINVAL; 2062 } 2063 2064 return 0; 2065 } 2066 2067 static int rt5682s_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) 2068 { 2069 struct snd_soc_component *component = dai->component; 2070 struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component); 2071 unsigned int reg_val = 0, tdm_ctrl = 0; 2072 2073 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 2074 case SND_SOC_DAIFMT_CBM_CFM: 2075 rt5682s->master[dai->id] = 1; 2076 break; 2077 case SND_SOC_DAIFMT_CBS_CFS: 2078 rt5682s->master[dai->id] = 0; 2079 break; 2080 default: 2081 return -EINVAL; 2082 } 2083 2084 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 2085 case SND_SOC_DAIFMT_NB_NF: 2086 break; 2087 case SND_SOC_DAIFMT_IB_NF: 2088 reg_val |= RT5682S_I2S_BP_INV; 2089 tdm_ctrl |= RT5682S_TDM_S_BP_INV; 2090 break; 2091 case SND_SOC_DAIFMT_NB_IF: 2092 if (dai->id == RT5682S_AIF1) 2093 tdm_ctrl |= RT5682S_TDM_S_LP_INV | RT5682S_TDM_M_BP_INV; 2094 else 2095 return -EINVAL; 2096 break; 2097 case SND_SOC_DAIFMT_IB_IF: 2098 if (dai->id == RT5682S_AIF1) 2099 tdm_ctrl |= RT5682S_TDM_S_BP_INV | RT5682S_TDM_S_LP_INV | 2100 RT5682S_TDM_M_BP_INV | RT5682S_TDM_M_LP_INV; 2101 else 2102 return -EINVAL; 2103 break; 2104 default: 2105 return -EINVAL; 2106 } 2107 2108 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 2109 case SND_SOC_DAIFMT_I2S: 2110 break; 2111 case SND_SOC_DAIFMT_LEFT_J: 2112 reg_val |= RT5682S_I2S_DF_LEFT; 2113 tdm_ctrl |= RT5682S_TDM_DF_LEFT; 2114 break; 2115 case SND_SOC_DAIFMT_DSP_A: 2116 reg_val |= RT5682S_I2S_DF_PCM_A; 2117 tdm_ctrl |= RT5682S_TDM_DF_PCM_A; 2118 break; 2119 case SND_SOC_DAIFMT_DSP_B: 2120 reg_val |= RT5682S_I2S_DF_PCM_B; 2121 tdm_ctrl |= RT5682S_TDM_DF_PCM_B; 2122 break; 2123 default: 2124 return -EINVAL; 2125 } 2126 2127 switch (dai->id) { 2128 case RT5682S_AIF1: 2129 snd_soc_component_update_bits(component, RT5682S_I2S1_SDP, 2130 RT5682S_I2S_DF_MASK, reg_val); 2131 snd_soc_component_update_bits(component, RT5682S_TDM_TCON_CTRL_1, 2132 RT5682S_TDM_MS_MASK | RT5682S_TDM_S_BP_MASK | 2133 RT5682S_TDM_DF_MASK | RT5682S_TDM_M_BP_MASK | 2134 RT5682S_TDM_M_LP_MASK | RT5682S_TDM_S_LP_MASK, 2135 tdm_ctrl | rt5682s->master[dai->id]); 2136 break; 2137 case RT5682S_AIF2: 2138 if (rt5682s->master[dai->id] == 0) 2139 reg_val |= RT5682S_I2S2_MS_S; 2140 snd_soc_component_update_bits(component, RT5682S_I2S2_SDP, 2141 RT5682S_I2S2_MS_MASK | RT5682S_I2S_BP_MASK | 2142 RT5682S_I2S_DF_MASK, reg_val); 2143 break; 2144 default: 2145 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id); 2146 return -EINVAL; 2147 } 2148 return 0; 2149 } 2150 2151 static int rt5682s_set_component_sysclk(struct snd_soc_component *component, 2152 int clk_id, int source, unsigned int freq, int dir) 2153 { 2154 struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component); 2155 unsigned int src = 0; 2156 2157 if (freq == rt5682s->sysclk && clk_id == rt5682s->sysclk_src) 2158 return 0; 2159 2160 switch (clk_id) { 2161 case RT5682S_SCLK_S_MCLK: 2162 src = RT5682S_CLK_SRC_MCLK; 2163 break; 2164 case RT5682S_SCLK_S_PLL1: 2165 src = RT5682S_CLK_SRC_PLL1; 2166 break; 2167 case RT5682S_SCLK_S_PLL2: 2168 src = RT5682S_CLK_SRC_PLL2; 2169 break; 2170 case RT5682S_SCLK_S_RCCLK: 2171 src = RT5682S_CLK_SRC_RCCLK; 2172 break; 2173 default: 2174 dev_err(component->dev, "Invalid clock id (%d)\n", clk_id); 2175 return -EINVAL; 2176 } 2177 2178 snd_soc_component_update_bits(component, RT5682S_GLB_CLK, 2179 RT5682S_SCLK_SRC_MASK, src << RT5682S_SCLK_SRC_SFT); 2180 snd_soc_component_update_bits(component, RT5682S_ADDA_CLK_1, 2181 RT5682S_I2S_M_CLK_SRC_MASK, src << RT5682S_I2S_M_CLK_SRC_SFT); 2182 snd_soc_component_update_bits(component, RT5682S_I2S2_M_CLK_CTRL_1, 2183 RT5682S_I2S2_M_CLK_SRC_MASK, src << RT5682S_I2S2_M_CLK_SRC_SFT); 2184 2185 rt5682s->sysclk = freq; 2186 rt5682s->sysclk_src = clk_id; 2187 2188 dev_dbg(component->dev, "Sysclk is %dHz and clock id is %d\n", 2189 freq, clk_id); 2190 2191 return 0; 2192 } 2193 2194 static const struct pll_calc_map plla_table[] = { 2195 {2048000, 24576000, 0, 46, 2, true, false, false, false}, 2196 {256000, 24576000, 0, 382, 2, true, false, false, false}, 2197 {512000, 24576000, 0, 190, 2, true, false, false, false}, 2198 {4096000, 24576000, 0, 22, 2, true, false, false, false}, 2199 {1024000, 24576000, 0, 94, 2, true, false, false, false}, 2200 {11289600, 22579200, 1, 22, 2, false, false, false, false}, 2201 {1411200, 22579200, 0, 62, 2, true, false, false, false}, 2202 {2822400, 22579200, 0, 30, 2, true, false, false, false}, 2203 {12288000, 24576000, 1, 22, 2, false, false, false, false}, 2204 {1536000, 24576000, 0, 62, 2, true, false, false, false}, 2205 {3072000, 24576000, 0, 30, 2, true, false, false, false}, 2206 {24576000, 49152000, 4, 22, 0, false, false, false, false}, 2207 {3072000, 49152000, 0, 30, 0, true, false, false, false}, 2208 {6144000, 49152000, 0, 30, 0, false, false, false, false}, 2209 {49152000, 98304000, 10, 22, 0, false, true, false, false}, 2210 {6144000, 98304000, 0, 30, 0, false, true, false, false}, 2211 {12288000, 98304000, 1, 22, 0, false, true, false, false}, 2212 {48000000, 3840000, 10, 22, 23, false, false, false, false}, 2213 {24000000, 3840000, 4, 22, 23, false, false, false, false}, 2214 {19200000, 3840000, 3, 23, 23, false, false, false, false}, 2215 {38400000, 3840000, 8, 23, 23, false, false, false, false}, 2216 }; 2217 2218 static const struct pll_calc_map pllb_table[] = { 2219 {48000000, 24576000, 8, 6, 3, false, false, false, false}, 2220 {48000000, 22579200, 23, 12, 3, false, false, false, true}, 2221 {24000000, 24576000, 3, 6, 3, false, false, false, false}, 2222 {24000000, 22579200, 23, 26, 3, false, false, false, true}, 2223 {19200000, 24576000, 2, 6, 3, false, false, false, false}, 2224 {19200000, 22579200, 3, 5, 3, false, false, false, true}, 2225 {38400000, 24576000, 6, 6, 3, false, false, false, false}, 2226 {38400000, 22579200, 8, 5, 3, false, false, false, true}, 2227 {3840000, 49152000, 0, 6, 0, true, false, false, false}, 2228 }; 2229 2230 static int find_pll_inter_combination(unsigned int f_in, unsigned int f_out, 2231 struct pll_calc_map *a, struct pll_calc_map *b) 2232 { 2233 int i, j; 2234 2235 /* Look at PLLA table */ 2236 for (i = 0; i < ARRAY_SIZE(plla_table); i++) { 2237 if (plla_table[i].freq_in == f_in && plla_table[i].freq_out == f_out) { 2238 memcpy(a, plla_table + i, sizeof(*a)); 2239 return USE_PLLA; 2240 } 2241 } 2242 2243 /* Look at PLLB table */ 2244 for (i = 0; i < ARRAY_SIZE(pllb_table); i++) { 2245 if (pllb_table[i].freq_in == f_in && pllb_table[i].freq_out == f_out) { 2246 memcpy(b, pllb_table + i, sizeof(*b)); 2247 return USE_PLLB; 2248 } 2249 } 2250 2251 /* Find a combination of PLLA & PLLB */ 2252 for (i = ARRAY_SIZE(plla_table) - 1; i >= 0; i--) { 2253 if (plla_table[i].freq_in == f_in && plla_table[i].freq_out == 3840000) { 2254 for (j = ARRAY_SIZE(pllb_table) - 1; j >= 0; j--) { 2255 if (pllb_table[j].freq_in == 3840000 && 2256 pllb_table[j].freq_out == f_out) { 2257 memcpy(a, plla_table + i, sizeof(*a)); 2258 memcpy(b, pllb_table + j, sizeof(*b)); 2259 return USE_PLLAB; 2260 } 2261 } 2262 } 2263 } 2264 2265 return -EINVAL; 2266 } 2267 2268 static int rt5682s_set_component_pll(struct snd_soc_component *component, 2269 int pll_id, int source, unsigned int freq_in, 2270 unsigned int freq_out) 2271 { 2272 struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component); 2273 struct pll_calc_map a_map, b_map; 2274 2275 if (source == rt5682s->pll_src[pll_id] && freq_in == rt5682s->pll_in[pll_id] && 2276 freq_out == rt5682s->pll_out[pll_id]) 2277 return 0; 2278 2279 if (!freq_in || !freq_out) { 2280 dev_dbg(component->dev, "PLL disabled\n"); 2281 rt5682s->pll_in[pll_id] = 0; 2282 rt5682s->pll_out[pll_id] = 0; 2283 snd_soc_component_update_bits(component, RT5682S_GLB_CLK, 2284 RT5682S_SCLK_SRC_MASK, RT5682S_CLK_SRC_MCLK << RT5682S_SCLK_SRC_SFT); 2285 return 0; 2286 } 2287 2288 switch (source) { 2289 case RT5682S_PLL_S_MCLK: 2290 snd_soc_component_update_bits(component, RT5682S_GLB_CLK, 2291 RT5682S_PLL_SRC_MASK, RT5682S_PLL_SRC_MCLK); 2292 break; 2293 case RT5682S_PLL_S_BCLK1: 2294 snd_soc_component_update_bits(component, RT5682S_GLB_CLK, 2295 RT5682S_PLL_SRC_MASK, RT5682S_PLL_SRC_BCLK1); 2296 break; 2297 default: 2298 dev_err(component->dev, "Unknown PLL Source %d\n", source); 2299 return -EINVAL; 2300 } 2301 2302 rt5682s->pll_comb = find_pll_inter_combination(freq_in, freq_out, 2303 &a_map, &b_map); 2304 2305 if ((pll_id == RT5682S_PLL1 && rt5682s->pll_comb == USE_PLLA) || 2306 (pll_id == RT5682S_PLL2 && (rt5682s->pll_comb == USE_PLLB || 2307 rt5682s->pll_comb == USE_PLLAB))) { 2308 dev_dbg(component->dev, 2309 "Supported freq conversion for PLL%d:(%d->%d): %d\n", 2310 pll_id + 1, freq_in, freq_out, rt5682s->pll_comb); 2311 } else { 2312 dev_err(component->dev, 2313 "Unsupported freq conversion for PLL%d:(%d->%d): %d\n", 2314 pll_id + 1, freq_in, freq_out, rt5682s->pll_comb); 2315 return -EINVAL; 2316 } 2317 2318 if (rt5682s->pll_comb == USE_PLLA || rt5682s->pll_comb == USE_PLLAB) { 2319 dev_dbg(component->dev, 2320 "PLLA: fin=%d fout=%d m_bp=%d k_bp=%d m=%d n=%d k=%d\n", 2321 a_map.freq_in, a_map.freq_out, a_map.m_bp, a_map.k_bp, 2322 (a_map.m_bp ? 0 : a_map.m), a_map.n, (a_map.k_bp ? 0 : a_map.k)); 2323 snd_soc_component_update_bits(component, RT5682S_PLL_CTRL_1, 2324 RT5682S_PLLA_N_MASK, a_map.n); 2325 snd_soc_component_update_bits(component, RT5682S_PLL_CTRL_2, 2326 RT5682S_PLLA_M_MASK | RT5682S_PLLA_K_MASK, 2327 a_map.m << RT5682S_PLLA_M_SFT | a_map.k); 2328 snd_soc_component_update_bits(component, RT5682S_PLL_CTRL_6, 2329 RT5682S_PLLA_M_BP_MASK | RT5682S_PLLA_K_BP_MASK, 2330 a_map.m_bp << RT5682S_PLLA_M_BP_SFT | 2331 a_map.k_bp << RT5682S_PLLA_K_BP_SFT); 2332 } 2333 2334 if (rt5682s->pll_comb == USE_PLLB || rt5682s->pll_comb == USE_PLLAB) { 2335 dev_dbg(component->dev, 2336 "PLLB: fin=%d fout=%d m_bp=%d k_bp=%d m=%d n=%d k=%d byp_ps=%d sel_ps=%d\n", 2337 b_map.freq_in, b_map.freq_out, b_map.m_bp, b_map.k_bp, 2338 (b_map.m_bp ? 0 : b_map.m), b_map.n, (b_map.k_bp ? 0 : b_map.k), 2339 b_map.byp_ps, b_map.sel_ps); 2340 snd_soc_component_update_bits(component, RT5682S_PLL_CTRL_3, 2341 RT5682S_PLLB_N_MASK, b_map.n); 2342 snd_soc_component_update_bits(component, RT5682S_PLL_CTRL_4, 2343 RT5682S_PLLB_M_MASK | RT5682S_PLLB_K_MASK, 2344 b_map.m << RT5682S_PLLB_M_SFT | b_map.k); 2345 snd_soc_component_update_bits(component, RT5682S_PLL_CTRL_6, 2346 RT5682S_PLLB_SEL_PS_MASK | RT5682S_PLLB_BYP_PS_MASK | 2347 RT5682S_PLLB_M_BP_MASK | RT5682S_PLLB_K_BP_MASK, 2348 b_map.sel_ps << RT5682S_PLLB_SEL_PS_SFT | 2349 b_map.byp_ps << RT5682S_PLLB_BYP_PS_SFT | 2350 b_map.m_bp << RT5682S_PLLB_M_BP_SFT | 2351 b_map.k_bp << RT5682S_PLLB_K_BP_SFT); 2352 } 2353 2354 if (rt5682s->pll_comb == USE_PLLB) 2355 snd_soc_component_update_bits(component, RT5682S_PLL_CTRL_7, 2356 RT5682S_PLLB_SRC_MASK, RT5682S_PLLB_SRC_DFIN); 2357 2358 rt5682s->pll_in[pll_id] = freq_in; 2359 rt5682s->pll_out[pll_id] = freq_out; 2360 rt5682s->pll_src[pll_id] = source; 2361 2362 return 0; 2363 } 2364 2365 static int rt5682s_set_bclk1_ratio(struct snd_soc_dai *dai, 2366 unsigned int ratio) 2367 { 2368 struct snd_soc_component *component = dai->component; 2369 struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component); 2370 2371 rt5682s->bclk[dai->id] = ratio; 2372 2373 switch (ratio) { 2374 case 256: 2375 snd_soc_component_update_bits(component, RT5682S_TDM_TCON_CTRL_1, 2376 RT5682S_TDM_BCLK_MS1_MASK, RT5682S_TDM_BCLK_MS1_256); 2377 break; 2378 case 128: 2379 snd_soc_component_update_bits(component, RT5682S_TDM_TCON_CTRL_1, 2380 RT5682S_TDM_BCLK_MS1_MASK, RT5682S_TDM_BCLK_MS1_128); 2381 break; 2382 case 64: 2383 snd_soc_component_update_bits(component, RT5682S_TDM_TCON_CTRL_1, 2384 RT5682S_TDM_BCLK_MS1_MASK, RT5682S_TDM_BCLK_MS1_64); 2385 break; 2386 case 32: 2387 snd_soc_component_update_bits(component, RT5682S_TDM_TCON_CTRL_1, 2388 RT5682S_TDM_BCLK_MS1_MASK, RT5682S_TDM_BCLK_MS1_32); 2389 break; 2390 default: 2391 dev_err(dai->dev, "Invalid bclk1 ratio %d\n", ratio); 2392 return -EINVAL; 2393 } 2394 2395 return 0; 2396 } 2397 2398 static int rt5682s_set_bclk2_ratio(struct snd_soc_dai *dai, unsigned int ratio) 2399 { 2400 struct snd_soc_component *component = dai->component; 2401 struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component); 2402 2403 rt5682s->bclk[dai->id] = ratio; 2404 2405 switch (ratio) { 2406 case 64: 2407 snd_soc_component_update_bits(component, RT5682S_ADDA_CLK_2, 2408 RT5682S_I2S2_BCLK_MS2_MASK, RT5682S_I2S2_BCLK_MS2_64); 2409 break; 2410 case 32: 2411 snd_soc_component_update_bits(component, RT5682S_ADDA_CLK_2, 2412 RT5682S_I2S2_BCLK_MS2_MASK, RT5682S_I2S2_BCLK_MS2_32); 2413 break; 2414 default: 2415 dev_err(dai->dev, "Invalid bclk2 ratio %d\n", ratio); 2416 return -EINVAL; 2417 } 2418 2419 return 0; 2420 } 2421 2422 static int rt5682s_set_bias_level(struct snd_soc_component *component, 2423 enum snd_soc_bias_level level) 2424 { 2425 struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component); 2426 2427 switch (level) { 2428 case SND_SOC_BIAS_PREPARE: 2429 regmap_update_bits(rt5682s->regmap, RT5682S_PWR_DIG_1, 2430 RT5682S_PWR_LDO, RT5682S_PWR_LDO); 2431 break; 2432 case SND_SOC_BIAS_STANDBY: 2433 regmap_update_bits(rt5682s->regmap, RT5682S_PWR_DIG_1, 2434 RT5682S_DIG_GATE_CTRL, RT5682S_DIG_GATE_CTRL); 2435 break; 2436 case SND_SOC_BIAS_OFF: 2437 regmap_update_bits(rt5682s->regmap, RT5682S_PWR_DIG_1, 2438 RT5682S_DIG_GATE_CTRL | RT5682S_PWR_LDO, 0); 2439 break; 2440 case SND_SOC_BIAS_ON: 2441 break; 2442 } 2443 2444 return 0; 2445 } 2446 2447 #ifdef CONFIG_COMMON_CLK 2448 #define CLK_PLL2_FIN 48000000 2449 #define CLK_48 48000 2450 #define CLK_44 44100 2451 2452 static bool rt5682s_clk_check(struct rt5682s_priv *rt5682s) 2453 { 2454 if (!rt5682s->master[RT5682S_AIF1]) { 2455 dev_dbg(rt5682s->component->dev, "dai clk fmt not set correctly\n"); 2456 return false; 2457 } 2458 return true; 2459 } 2460 2461 static int rt5682s_wclk_prepare(struct clk_hw *hw) 2462 { 2463 struct rt5682s_priv *rt5682s = 2464 container_of(hw, struct rt5682s_priv, dai_clks_hw[RT5682S_DAI_WCLK_IDX]); 2465 struct snd_soc_component *component = rt5682s->component; 2466 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); 2467 2468 if (!rt5682s_clk_check(rt5682s)) 2469 return -EINVAL; 2470 2471 snd_soc_dapm_mutex_lock(dapm); 2472 2473 snd_soc_dapm_force_enable_pin_unlocked(dapm, "MICBIAS"); 2474 snd_soc_component_update_bits(component, RT5682S_PWR_ANLG_1, 2475 RT5682S_PWR_MB, RT5682S_PWR_MB); 2476 2477 snd_soc_dapm_force_enable_pin_unlocked(dapm, "Vref2"); 2478 snd_soc_component_update_bits(component, RT5682S_PWR_ANLG_1, 2479 RT5682S_PWR_VREF2 | RT5682S_PWR_FV2, RT5682S_PWR_VREF2); 2480 usleep_range(15000, 20000); 2481 snd_soc_component_update_bits(component, RT5682S_PWR_ANLG_1, 2482 RT5682S_PWR_FV2, RT5682S_PWR_FV2); 2483 2484 snd_soc_dapm_force_enable_pin_unlocked(dapm, "I2S1"); 2485 /* Only need to power PLLB due to the rate set restriction */ 2486 snd_soc_dapm_force_enable_pin_unlocked(dapm, "PLLB"); 2487 snd_soc_dapm_sync_unlocked(dapm); 2488 2489 snd_soc_dapm_mutex_unlock(dapm); 2490 2491 return 0; 2492 } 2493 2494 static void rt5682s_wclk_unprepare(struct clk_hw *hw) 2495 { 2496 struct rt5682s_priv *rt5682s = 2497 container_of(hw, struct rt5682s_priv, dai_clks_hw[RT5682S_DAI_WCLK_IDX]); 2498 struct snd_soc_component *component = rt5682s->component; 2499 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); 2500 2501 if (!rt5682s_clk_check(rt5682s)) 2502 return; 2503 2504 snd_soc_dapm_mutex_lock(dapm); 2505 2506 snd_soc_dapm_disable_pin_unlocked(dapm, "MICBIAS"); 2507 snd_soc_dapm_disable_pin_unlocked(dapm, "Vref2"); 2508 if (!rt5682s->jack_type) 2509 snd_soc_component_update_bits(component, RT5682S_PWR_ANLG_1, 2510 RT5682S_PWR_VREF2 | RT5682S_PWR_FV2 | RT5682S_PWR_MB, 0); 2511 2512 snd_soc_dapm_disable_pin_unlocked(dapm, "I2S1"); 2513 snd_soc_dapm_disable_pin_unlocked(dapm, "PLLB"); 2514 snd_soc_dapm_sync_unlocked(dapm); 2515 2516 snd_soc_dapm_mutex_unlock(dapm); 2517 } 2518 2519 static unsigned long rt5682s_wclk_recalc_rate(struct clk_hw *hw, 2520 unsigned long parent_rate) 2521 { 2522 struct rt5682s_priv *rt5682s = 2523 container_of(hw, struct rt5682s_priv, dai_clks_hw[RT5682S_DAI_WCLK_IDX]); 2524 struct snd_soc_component *component = rt5682s->component; 2525 const char * const clk_name = clk_hw_get_name(hw); 2526 2527 if (!rt5682s_clk_check(rt5682s)) 2528 return 0; 2529 /* 2530 * Only accept to set wclk rate to 44.1k or 48kHz. 2531 */ 2532 if (rt5682s->lrck[RT5682S_AIF1] != CLK_48 && 2533 rt5682s->lrck[RT5682S_AIF1] != CLK_44) { 2534 dev_warn(component->dev, "%s: clk %s only support %d or %d Hz output\n", 2535 __func__, clk_name, CLK_44, CLK_48); 2536 return 0; 2537 } 2538 2539 return rt5682s->lrck[RT5682S_AIF1]; 2540 } 2541 2542 static long rt5682s_wclk_round_rate(struct clk_hw *hw, unsigned long rate, 2543 unsigned long *parent_rate) 2544 { 2545 struct rt5682s_priv *rt5682s = 2546 container_of(hw, struct rt5682s_priv, dai_clks_hw[RT5682S_DAI_WCLK_IDX]); 2547 struct snd_soc_component *component = rt5682s->component; 2548 const char * const clk_name = clk_hw_get_name(hw); 2549 2550 if (!rt5682s_clk_check(rt5682s)) 2551 return -EINVAL; 2552 /* 2553 * Only accept to set wclk rate to 44.1k or 48kHz. 2554 * It will force to 48kHz if not both. 2555 */ 2556 if (rate != CLK_48 && rate != CLK_44) { 2557 dev_warn(component->dev, "%s: clk %s only support %d or %d Hz output\n", 2558 __func__, clk_name, CLK_44, CLK_48); 2559 rate = CLK_48; 2560 } 2561 2562 return rate; 2563 } 2564 2565 static int rt5682s_wclk_set_rate(struct clk_hw *hw, unsigned long rate, 2566 unsigned long parent_rate) 2567 { 2568 struct rt5682s_priv *rt5682s = 2569 container_of(hw, struct rt5682s_priv, dai_clks_hw[RT5682S_DAI_WCLK_IDX]); 2570 struct snd_soc_component *component = rt5682s->component; 2571 struct clk *parent_clk; 2572 const char * const clk_name = clk_hw_get_name(hw); 2573 unsigned int clk_pll2_fout; 2574 2575 if (!rt5682s_clk_check(rt5682s)) 2576 return -EINVAL; 2577 2578 /* 2579 * Whether the wclk's parent clk (mclk) exists or not, please ensure 2580 * it is fixed or set to 48MHz before setting wclk rate. It's a 2581 * temporary limitation. Only accept 48MHz clk as the clk provider. 2582 * 2583 * It will set the codec anyway by assuming mclk is 48MHz. 2584 */ 2585 parent_clk = clk_get_parent(hw->clk); 2586 if (!parent_clk) 2587 dev_warn(component->dev, 2588 "Parent mclk of wclk not acquired in driver. Please ensure mclk was provided as %d Hz.\n", 2589 CLK_PLL2_FIN); 2590 2591 if (parent_rate != CLK_PLL2_FIN) 2592 dev_warn(component->dev, "clk %s only support %d Hz input\n", 2593 clk_name, CLK_PLL2_FIN); 2594 2595 /* 2596 * To achieve the rate conversion from 48MHz to 44.1k or 48kHz, 2597 * PLL2 is needed. 2598 */ 2599 clk_pll2_fout = rate * 512; 2600 rt5682s_set_component_pll(component, RT5682S_PLL2, RT5682S_PLL_S_MCLK, 2601 CLK_PLL2_FIN, clk_pll2_fout); 2602 2603 rt5682s_set_component_sysclk(component, RT5682S_SCLK_S_PLL2, 0, 2604 clk_pll2_fout, SND_SOC_CLOCK_IN); 2605 2606 rt5682s->lrck[RT5682S_AIF1] = rate; 2607 2608 return 0; 2609 } 2610 2611 static unsigned long rt5682s_bclk_recalc_rate(struct clk_hw *hw, 2612 unsigned long parent_rate) 2613 { 2614 struct rt5682s_priv *rt5682s = 2615 container_of(hw, struct rt5682s_priv, dai_clks_hw[RT5682S_DAI_BCLK_IDX]); 2616 struct snd_soc_component *component = rt5682s->component; 2617 unsigned int bclks_per_wclk; 2618 2619 bclks_per_wclk = snd_soc_component_read(component, RT5682S_TDM_TCON_CTRL_1); 2620 2621 switch (bclks_per_wclk & RT5682S_TDM_BCLK_MS1_MASK) { 2622 case RT5682S_TDM_BCLK_MS1_256: 2623 return parent_rate * 256; 2624 case RT5682S_TDM_BCLK_MS1_128: 2625 return parent_rate * 128; 2626 case RT5682S_TDM_BCLK_MS1_64: 2627 return parent_rate * 64; 2628 case RT5682S_TDM_BCLK_MS1_32: 2629 return parent_rate * 32; 2630 default: 2631 return 0; 2632 } 2633 } 2634 2635 static unsigned long rt5682s_bclk_get_factor(unsigned long rate, 2636 unsigned long parent_rate) 2637 { 2638 unsigned long factor; 2639 2640 factor = rate / parent_rate; 2641 if (factor < 64) 2642 return 32; 2643 else if (factor < 128) 2644 return 64; 2645 else if (factor < 256) 2646 return 128; 2647 else 2648 return 256; 2649 } 2650 2651 static long rt5682s_bclk_round_rate(struct clk_hw *hw, unsigned long rate, 2652 unsigned long *parent_rate) 2653 { 2654 struct rt5682s_priv *rt5682s = 2655 container_of(hw, struct rt5682s_priv, dai_clks_hw[RT5682S_DAI_BCLK_IDX]); 2656 unsigned long factor; 2657 2658 if (!*parent_rate || !rt5682s_clk_check(rt5682s)) 2659 return -EINVAL; 2660 2661 /* 2662 * BCLK rates are set as a multiplier of WCLK in HW. 2663 * We don't allow changing the parent WCLK. We just do 2664 * some rounding down based on the parent WCLK rate 2665 * and find the appropriate multiplier of BCLK to 2666 * get the rounded down BCLK value. 2667 */ 2668 factor = rt5682s_bclk_get_factor(rate, *parent_rate); 2669 2670 return *parent_rate * factor; 2671 } 2672 2673 static int rt5682s_bclk_set_rate(struct clk_hw *hw, unsigned long rate, 2674 unsigned long parent_rate) 2675 { 2676 struct rt5682s_priv *rt5682s = 2677 container_of(hw, struct rt5682s_priv, dai_clks_hw[RT5682S_DAI_BCLK_IDX]); 2678 struct snd_soc_component *component = rt5682s->component; 2679 struct snd_soc_dai *dai; 2680 unsigned long factor; 2681 2682 if (!rt5682s_clk_check(rt5682s)) 2683 return -EINVAL; 2684 2685 factor = rt5682s_bclk_get_factor(rate, parent_rate); 2686 2687 for_each_component_dais(component, dai) 2688 if (dai->id == RT5682S_AIF1) 2689 break; 2690 if (!dai) { 2691 dev_err(component->dev, "dai %d not found in component\n", 2692 RT5682S_AIF1); 2693 return -ENODEV; 2694 } 2695 2696 return rt5682s_set_bclk1_ratio(dai, factor); 2697 } 2698 2699 static const struct clk_ops rt5682s_dai_clk_ops[RT5682S_DAI_NUM_CLKS] = { 2700 [RT5682S_DAI_WCLK_IDX] = { 2701 .prepare = rt5682s_wclk_prepare, 2702 .unprepare = rt5682s_wclk_unprepare, 2703 .recalc_rate = rt5682s_wclk_recalc_rate, 2704 .round_rate = rt5682s_wclk_round_rate, 2705 .set_rate = rt5682s_wclk_set_rate, 2706 }, 2707 [RT5682S_DAI_BCLK_IDX] = { 2708 .recalc_rate = rt5682s_bclk_recalc_rate, 2709 .round_rate = rt5682s_bclk_round_rate, 2710 .set_rate = rt5682s_bclk_set_rate, 2711 }, 2712 }; 2713 2714 static int rt5682s_register_dai_clks(struct snd_soc_component *component) 2715 { 2716 struct device *dev = component->dev; 2717 struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component); 2718 struct rt5682s_platform_data *pdata = &rt5682s->pdata; 2719 struct clk_hw *dai_clk_hw; 2720 int i, ret; 2721 2722 for (i = 0; i < RT5682S_DAI_NUM_CLKS; ++i) { 2723 struct clk_init_data init = { }; 2724 struct clk_parent_data parent_data; 2725 const struct clk_hw *parent; 2726 2727 dai_clk_hw = &rt5682s->dai_clks_hw[i]; 2728 2729 switch (i) { 2730 case RT5682S_DAI_WCLK_IDX: 2731 /* Make MCLK the parent of WCLK */ 2732 if (rt5682s->mclk) { 2733 parent_data = (struct clk_parent_data){ 2734 .fw_name = "mclk", 2735 }; 2736 init.parent_data = &parent_data; 2737 init.num_parents = 1; 2738 } 2739 break; 2740 case RT5682S_DAI_BCLK_IDX: 2741 /* Make WCLK the parent of BCLK */ 2742 parent = &rt5682s->dai_clks_hw[RT5682S_DAI_WCLK_IDX]; 2743 init.parent_hws = &parent; 2744 init.num_parents = 1; 2745 break; 2746 default: 2747 dev_err(dev, "Invalid clock index\n"); 2748 return -EINVAL; 2749 } 2750 2751 init.name = pdata->dai_clk_names[i]; 2752 init.ops = &rt5682s_dai_clk_ops[i]; 2753 init.flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_GATE; 2754 dai_clk_hw->init = &init; 2755 2756 ret = devm_clk_hw_register(dev, dai_clk_hw); 2757 if (ret) { 2758 dev_warn(dev, "Failed to register %s: %d\n", init.name, ret); 2759 return ret; 2760 } 2761 2762 if (dev->of_node) { 2763 devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, dai_clk_hw); 2764 } else { 2765 ret = devm_clk_hw_register_clkdev(dev, dai_clk_hw, 2766 init.name, dev_name(dev)); 2767 if (ret) 2768 return ret; 2769 } 2770 } 2771 2772 return 0; 2773 } 2774 2775 static int rt5682s_dai_probe_clks(struct snd_soc_component *component) 2776 { 2777 struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component); 2778 int ret; 2779 2780 /* Check if MCLK provided */ 2781 rt5682s->mclk = devm_clk_get(component->dev, "mclk"); 2782 if (IS_ERR(rt5682s->mclk)) { 2783 if (PTR_ERR(rt5682s->mclk) != -ENOENT) { 2784 ret = PTR_ERR(rt5682s->mclk); 2785 return ret; 2786 } 2787 rt5682s->mclk = NULL; 2788 } 2789 2790 /* Register CCF DAI clock control */ 2791 ret = rt5682s_register_dai_clks(component); 2792 if (ret) 2793 return ret; 2794 2795 /* Initial setup for CCF */ 2796 rt5682s->lrck[RT5682S_AIF1] = CLK_48; 2797 2798 return 0; 2799 } 2800 #else 2801 static inline int rt5682s_dai_probe_clks(struct snd_soc_component *component) 2802 { 2803 return 0; 2804 } 2805 #endif /* CONFIG_COMMON_CLK */ 2806 2807 static int rt5682s_probe(struct snd_soc_component *component) 2808 { 2809 struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component); 2810 struct snd_soc_dapm_context *dapm = &component->dapm; 2811 int ret; 2812 2813 rt5682s->component = component; 2814 2815 ret = rt5682s_dai_probe_clks(component); 2816 if (ret) 2817 return ret; 2818 2819 snd_soc_dapm_disable_pin(dapm, "MICBIAS"); 2820 snd_soc_dapm_disable_pin(dapm, "Vref2"); 2821 snd_soc_dapm_sync(dapm); 2822 return 0; 2823 } 2824 2825 static void rt5682s_remove(struct snd_soc_component *component) 2826 { 2827 struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component); 2828 2829 rt5682s_reset(rt5682s); 2830 } 2831 2832 #ifdef CONFIG_PM 2833 static int rt5682s_suspend(struct snd_soc_component *component) 2834 { 2835 struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component); 2836 2837 cancel_delayed_work_sync(&rt5682s->jack_detect_work); 2838 cancel_delayed_work_sync(&rt5682s->jd_check_work); 2839 2840 if (rt5682s->hs_jack && rt5682s->jack_type == SND_JACK_HEADSET) 2841 snd_soc_component_update_bits(component, RT5682S_4BTN_IL_CMD_2, 2842 RT5682S_4BTN_IL_MASK, RT5682S_4BTN_IL_DIS); 2843 2844 regcache_cache_only(rt5682s->regmap, true); 2845 regcache_mark_dirty(rt5682s->regmap); 2846 2847 return 0; 2848 } 2849 2850 static int rt5682s_resume(struct snd_soc_component *component) 2851 { 2852 struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component); 2853 2854 regcache_cache_only(rt5682s->regmap, false); 2855 regcache_sync(rt5682s->regmap); 2856 2857 if (rt5682s->hs_jack) { 2858 rt5682s->jack_type = 0; 2859 rt5682s_sar_power_mode(component, SAR_PWR_NORMAL, 0); 2860 mod_delayed_work(system_power_efficient_wq, 2861 &rt5682s->jack_detect_work, msecs_to_jiffies(0)); 2862 } 2863 2864 return 0; 2865 } 2866 #else 2867 #define rt5682s_suspend NULL 2868 #define rt5682s_resume NULL 2869 #endif 2870 2871 static const struct snd_soc_dai_ops rt5682s_aif1_dai_ops = { 2872 .hw_params = rt5682s_hw_params, 2873 .set_fmt = rt5682s_set_dai_fmt, 2874 .set_tdm_slot = rt5682s_set_tdm_slot, 2875 .set_bclk_ratio = rt5682s_set_bclk1_ratio, 2876 }; 2877 2878 static const struct snd_soc_dai_ops rt5682s_aif2_dai_ops = { 2879 .hw_params = rt5682s_hw_params, 2880 .set_fmt = rt5682s_set_dai_fmt, 2881 .set_bclk_ratio = rt5682s_set_bclk2_ratio, 2882 }; 2883 2884 static const struct snd_soc_component_driver rt5682s_soc_component_dev = { 2885 .probe = rt5682s_probe, 2886 .remove = rt5682s_remove, 2887 .suspend = rt5682s_suspend, 2888 .resume = rt5682s_resume, 2889 .set_bias_level = rt5682s_set_bias_level, 2890 .controls = rt5682s_snd_controls, 2891 .num_controls = ARRAY_SIZE(rt5682s_snd_controls), 2892 .dapm_widgets = rt5682s_dapm_widgets, 2893 .num_dapm_widgets = ARRAY_SIZE(rt5682s_dapm_widgets), 2894 .dapm_routes = rt5682s_dapm_routes, 2895 .num_dapm_routes = ARRAY_SIZE(rt5682s_dapm_routes), 2896 .set_sysclk = rt5682s_set_component_sysclk, 2897 .set_pll = rt5682s_set_component_pll, 2898 .set_jack = rt5682s_set_jack_detect, 2899 .use_pmdown_time = 1, 2900 .endianness = 1, 2901 .non_legacy_dai_naming = 1, 2902 }; 2903 2904 static int rt5682s_parse_dt(struct rt5682s_priv *rt5682s, struct device *dev) 2905 { 2906 device_property_read_u32(dev, "realtek,dmic1-data-pin", 2907 &rt5682s->pdata.dmic1_data_pin); 2908 device_property_read_u32(dev, "realtek,dmic1-clk-pin", 2909 &rt5682s->pdata.dmic1_clk_pin); 2910 device_property_read_u32(dev, "realtek,jd-src", 2911 &rt5682s->pdata.jd_src); 2912 device_property_read_u32(dev, "realtek,dmic-clk-rate-hz", 2913 &rt5682s->pdata.dmic_clk_rate); 2914 device_property_read_u32(dev, "realtek,dmic-delay-ms", 2915 &rt5682s->pdata.dmic_delay); 2916 device_property_read_u32(dev, "realtek,amic-delay-ms", 2917 &rt5682s->pdata.amic_delay); 2918 2919 rt5682s->pdata.ldo1_en = of_get_named_gpio(dev->of_node, 2920 "realtek,ldo1-en-gpios", 0); 2921 2922 if (device_property_read_string_array(dev, "clock-output-names", 2923 rt5682s->pdata.dai_clk_names, 2924 RT5682S_DAI_NUM_CLKS) < 0) 2925 dev_warn(dev, "Using default DAI clk names: %s, %s\n", 2926 rt5682s->pdata.dai_clk_names[RT5682S_DAI_WCLK_IDX], 2927 rt5682s->pdata.dai_clk_names[RT5682S_DAI_BCLK_IDX]); 2928 2929 rt5682s->pdata.dmic_clk_driving_high = device_property_read_bool(dev, 2930 "realtek,dmic-clk-driving-high"); 2931 2932 return 0; 2933 } 2934 2935 static void rt5682s_calibrate(struct rt5682s_priv *rt5682s) 2936 { 2937 unsigned int count, value; 2938 2939 mutex_lock(&rt5682s->calibrate_mutex); 2940 2941 regmap_write(rt5682s->regmap, RT5682S_PWR_ANLG_1, 0xaa80); 2942 usleep_range(15000, 20000); 2943 regmap_write(rt5682s->regmap, RT5682S_PWR_ANLG_1, 0xfa80); 2944 regmap_write(rt5682s->regmap, RT5682S_PWR_DIG_1, 0x01c0); 2945 regmap_write(rt5682s->regmap, RT5682S_MICBIAS_2, 0x0380); 2946 regmap_write(rt5682s->regmap, RT5682S_GLB_CLK, 0x8000); 2947 regmap_write(rt5682s->regmap, RT5682S_ADDA_CLK_1, 0x1001); 2948 regmap_write(rt5682s->regmap, RT5682S_CHOP_DAC_2, 0x3030); 2949 regmap_write(rt5682s->regmap, RT5682S_CHOP_ADC, 0xb000); 2950 regmap_write(rt5682s->regmap, RT5682S_STO1_ADC_MIXER, 0x686c); 2951 regmap_write(rt5682s->regmap, RT5682S_CAL_REC, 0x5151); 2952 regmap_write(rt5682s->regmap, RT5682S_HP_CALIB_CTRL_2, 0x0321); 2953 regmap_write(rt5682s->regmap, RT5682S_HP_LOGIC_CTRL_2, 0x0004); 2954 regmap_write(rt5682s->regmap, RT5682S_HP_CALIB_CTRL_1, 0x7c00); 2955 regmap_write(rt5682s->regmap, RT5682S_HP_CALIB_CTRL_1, 0xfc00); 2956 2957 for (count = 0; count < 60; count++) { 2958 regmap_read(rt5682s->regmap, RT5682S_HP_CALIB_ST_1, &value); 2959 if (!(value & 0x8000)) 2960 break; 2961 2962 usleep_range(10000, 10005); 2963 } 2964 2965 if (count >= 60) 2966 dev_err(rt5682s->component->dev, "HP Calibration Failure\n"); 2967 2968 /* restore settings */ 2969 regmap_write(rt5682s->regmap, RT5682S_MICBIAS_2, 0x0180); 2970 regmap_write(rt5682s->regmap, RT5682S_CAL_REC, 0x5858); 2971 regmap_write(rt5682s->regmap, RT5682S_STO1_ADC_MIXER, 0xc0c4); 2972 regmap_write(rt5682s->regmap, RT5682S_HP_CALIB_CTRL_2, 0x0320); 2973 regmap_write(rt5682s->regmap, RT5682S_PWR_DIG_1, 0x00c0); 2974 regmap_write(rt5682s->regmap, RT5682S_PWR_ANLG_1, 0x0800); 2975 regmap_write(rt5682s->regmap, RT5682S_GLB_CLK, 0x0000); 2976 2977 mutex_unlock(&rt5682s->calibrate_mutex); 2978 } 2979 2980 static const struct regmap_config rt5682s_regmap = { 2981 .reg_bits = 16, 2982 .val_bits = 16, 2983 .max_register = RT5682S_MAX_REG, 2984 .volatile_reg = rt5682s_volatile_register, 2985 .readable_reg = rt5682s_readable_register, 2986 .cache_type = REGCACHE_RBTREE, 2987 .reg_defaults = rt5682s_reg, 2988 .num_reg_defaults = ARRAY_SIZE(rt5682s_reg), 2989 .use_single_read = true, 2990 .use_single_write = true, 2991 }; 2992 2993 static struct snd_soc_dai_driver rt5682s_dai[] = { 2994 { 2995 .name = "rt5682s-aif1", 2996 .id = RT5682S_AIF1, 2997 .playback = { 2998 .stream_name = "AIF1 Playback", 2999 .channels_min = 1, 3000 .channels_max = 2, 3001 .rates = RT5682S_STEREO_RATES, 3002 .formats = RT5682S_FORMATS, 3003 }, 3004 .capture = { 3005 .stream_name = "AIF1 Capture", 3006 .channels_min = 1, 3007 .channels_max = 2, 3008 .rates = RT5682S_STEREO_RATES, 3009 .formats = RT5682S_FORMATS, 3010 }, 3011 .ops = &rt5682s_aif1_dai_ops, 3012 }, 3013 { 3014 .name = "rt5682s-aif2", 3015 .id = RT5682S_AIF2, 3016 .capture = { 3017 .stream_name = "AIF2 Capture", 3018 .channels_min = 1, 3019 .channels_max = 2, 3020 .rates = RT5682S_STEREO_RATES, 3021 .formats = RT5682S_FORMATS, 3022 }, 3023 .ops = &rt5682s_aif2_dai_ops, 3024 }, 3025 }; 3026 3027 static void rt5682s_i2c_disable_regulators(void *data) 3028 { 3029 struct rt5682s_priv *rt5682s = data; 3030 3031 regulator_bulk_disable(ARRAY_SIZE(rt5682s->supplies), rt5682s->supplies); 3032 } 3033 3034 static int rt5682s_i2c_probe(struct i2c_client *i2c, 3035 const struct i2c_device_id *id) 3036 { 3037 struct rt5682s_platform_data *pdata = dev_get_platdata(&i2c->dev); 3038 struct rt5682s_priv *rt5682s; 3039 int i, ret; 3040 unsigned int val; 3041 3042 rt5682s = devm_kzalloc(&i2c->dev, sizeof(struct rt5682s_priv), GFP_KERNEL); 3043 if (!rt5682s) 3044 return -ENOMEM; 3045 3046 i2c_set_clientdata(i2c, rt5682s); 3047 3048 rt5682s->pdata = i2s_default_platform_data; 3049 3050 if (pdata) 3051 rt5682s->pdata = *pdata; 3052 else 3053 rt5682s_parse_dt(rt5682s, &i2c->dev); 3054 3055 rt5682s->regmap = devm_regmap_init_i2c(i2c, &rt5682s_regmap); 3056 if (IS_ERR(rt5682s->regmap)) { 3057 ret = PTR_ERR(rt5682s->regmap); 3058 dev_err(&i2c->dev, "Failed to allocate register map: %d\n", ret); 3059 return ret; 3060 } 3061 3062 for (i = 0; i < ARRAY_SIZE(rt5682s->supplies); i++) 3063 rt5682s->supplies[i].supply = rt5682s_supply_names[i]; 3064 3065 ret = devm_regulator_bulk_get(&i2c->dev, 3066 ARRAY_SIZE(rt5682s->supplies), rt5682s->supplies); 3067 if (ret) { 3068 dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret); 3069 return ret; 3070 } 3071 3072 ret = devm_add_action_or_reset(&i2c->dev, rt5682s_i2c_disable_regulators, rt5682s); 3073 if (ret) 3074 return ret; 3075 3076 ret = regulator_bulk_enable(ARRAY_SIZE(rt5682s->supplies), rt5682s->supplies); 3077 if (ret) { 3078 dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret); 3079 return ret; 3080 } 3081 3082 if (gpio_is_valid(rt5682s->pdata.ldo1_en)) { 3083 if (devm_gpio_request_one(&i2c->dev, rt5682s->pdata.ldo1_en, 3084 GPIOF_OUT_INIT_HIGH, "rt5682s")) 3085 dev_err(&i2c->dev, "Fail gpio_request gpio_ldo\n"); 3086 } 3087 3088 /* Sleep for 50 ms minimum */ 3089 usleep_range(50000, 55000); 3090 3091 regmap_read(rt5682s->regmap, RT5682S_DEVICE_ID, &val); 3092 if (val != DEVICE_ID) { 3093 dev_err(&i2c->dev, "Device with ID register %x is not rt5682s\n", val); 3094 return -ENODEV; 3095 } 3096 3097 rt5682s_reset(rt5682s); 3098 rt5682s_apply_patch_list(rt5682s, &i2c->dev); 3099 3100 regmap_update_bits(rt5682s->regmap, RT5682S_PWR_DIG_2, 3101 RT5682S_DLDO_I_LIMIT_MASK, RT5682S_DLDO_I_LIMIT_DIS); 3102 usleep_range(20000, 25000); 3103 3104 mutex_init(&rt5682s->calibrate_mutex); 3105 mutex_init(&rt5682s->sar_mutex); 3106 mutex_init(&rt5682s->jdet_mutex); 3107 rt5682s_calibrate(rt5682s); 3108 3109 regmap_update_bits(rt5682s->regmap, RT5682S_MICBIAS_2, 3110 RT5682S_PWR_CLK25M_MASK | RT5682S_PWR_CLK1M_MASK, 3111 RT5682S_PWR_CLK25M_PD | RT5682S_PWR_CLK1M_PU); 3112 regmap_update_bits(rt5682s->regmap, RT5682S_PWR_ANLG_1, 3113 RT5682S_PWR_BG, RT5682S_PWR_BG); 3114 regmap_update_bits(rt5682s->regmap, RT5682S_HP_LOGIC_CTRL_2, 3115 RT5682S_HP_SIG_SRC_MASK, RT5682S_HP_SIG_SRC_1BIT_CTL); 3116 regmap_update_bits(rt5682s->regmap, RT5682S_HP_CHARGE_PUMP_2, 3117 RT5682S_PM_HP_MASK, RT5682S_PM_HP_HV); 3118 regmap_update_bits(rt5682s->regmap, RT5682S_HP_AMP_DET_CTL_1, 3119 RT5682S_CP_SW_SIZE_MASK, RT5682S_CP_SW_SIZE_M); 3120 3121 /* DMIC data pin */ 3122 switch (rt5682s->pdata.dmic1_data_pin) { 3123 case RT5682S_DMIC1_DATA_NULL: 3124 break; 3125 case RT5682S_DMIC1_DATA_GPIO2: /* share with LRCK2 */ 3126 regmap_update_bits(rt5682s->regmap, RT5682S_DMIC_CTRL_1, 3127 RT5682S_DMIC_1_DP_MASK, RT5682S_DMIC_1_DP_GPIO2); 3128 regmap_update_bits(rt5682s->regmap, RT5682S_GPIO_CTRL_1, 3129 RT5682S_GP2_PIN_MASK, RT5682S_GP2_PIN_DMIC_SDA); 3130 break; 3131 case RT5682S_DMIC1_DATA_GPIO5: /* share with DACDAT1 */ 3132 regmap_update_bits(rt5682s->regmap, RT5682S_DMIC_CTRL_1, 3133 RT5682S_DMIC_1_DP_MASK, RT5682S_DMIC_1_DP_GPIO5); 3134 regmap_update_bits(rt5682s->regmap, RT5682S_GPIO_CTRL_1, 3135 RT5682S_GP5_PIN_MASK, RT5682S_GP5_PIN_DMIC_SDA); 3136 break; 3137 default: 3138 dev_warn(&i2c->dev, "invalid DMIC_DAT pin\n"); 3139 break; 3140 } 3141 3142 /* DMIC clk pin */ 3143 switch (rt5682s->pdata.dmic1_clk_pin) { 3144 case RT5682S_DMIC1_CLK_NULL: 3145 break; 3146 case RT5682S_DMIC1_CLK_GPIO1: /* share with IRQ */ 3147 regmap_update_bits(rt5682s->regmap, RT5682S_GPIO_CTRL_1, 3148 RT5682S_GP1_PIN_MASK, RT5682S_GP1_PIN_DMIC_CLK); 3149 break; 3150 case RT5682S_DMIC1_CLK_GPIO3: /* share with BCLK2 */ 3151 regmap_update_bits(rt5682s->regmap, RT5682S_GPIO_CTRL_1, 3152 RT5682S_GP3_PIN_MASK, RT5682S_GP3_PIN_DMIC_CLK); 3153 if (rt5682s->pdata.dmic_clk_driving_high) 3154 regmap_update_bits(rt5682s->regmap, RT5682S_PAD_DRIVING_CTRL, 3155 RT5682S_PAD_DRV_GP3_MASK, RT5682S_PAD_DRV_GP3_HIGH); 3156 break; 3157 default: 3158 dev_warn(&i2c->dev, "invalid DMIC_CLK pin\n"); 3159 break; 3160 } 3161 3162 INIT_DELAYED_WORK(&rt5682s->jack_detect_work, rt5682s_jack_detect_handler); 3163 INIT_DELAYED_WORK(&rt5682s->jd_check_work, rt5682s_jd_check_handler); 3164 3165 if (i2c->irq) { 3166 ret = devm_request_threaded_irq(&i2c->dev, i2c->irq, NULL, rt5682s_irq, 3167 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING | IRQF_ONESHOT, 3168 "rt5682s", rt5682s); 3169 if (ret) 3170 dev_err(&i2c->dev, "Failed to reguest IRQ: %d\n", ret); 3171 } 3172 3173 return devm_snd_soc_register_component(&i2c->dev, &rt5682s_soc_component_dev, 3174 rt5682s_dai, ARRAY_SIZE(rt5682s_dai)); 3175 } 3176 3177 static void rt5682s_i2c_shutdown(struct i2c_client *client) 3178 { 3179 struct rt5682s_priv *rt5682s = i2c_get_clientdata(client); 3180 3181 disable_irq(client->irq); 3182 cancel_delayed_work_sync(&rt5682s->jack_detect_work); 3183 cancel_delayed_work_sync(&rt5682s->jd_check_work); 3184 3185 rt5682s_reset(rt5682s); 3186 } 3187 3188 static int rt5682s_i2c_remove(struct i2c_client *client) 3189 { 3190 rt5682s_i2c_shutdown(client); 3191 3192 return 0; 3193 } 3194 3195 static const struct of_device_id rt5682s_of_match[] = { 3196 {.compatible = "realtek,rt5682s"}, 3197 {}, 3198 }; 3199 MODULE_DEVICE_TABLE(of, rt5682s_of_match); 3200 3201 static const struct acpi_device_id rt5682s_acpi_match[] = { 3202 {"RTL5682", 0,}, 3203 {}, 3204 }; 3205 MODULE_DEVICE_TABLE(acpi, rt5682s_acpi_match); 3206 3207 static const struct i2c_device_id rt5682s_i2c_id[] = { 3208 {"rt5682s", 0}, 3209 {} 3210 }; 3211 MODULE_DEVICE_TABLE(i2c, rt5682s_i2c_id); 3212 3213 static struct i2c_driver rt5682s_i2c_driver = { 3214 .driver = { 3215 .name = "rt5682s", 3216 .of_match_table = rt5682s_of_match, 3217 .acpi_match_table = rt5682s_acpi_match, 3218 .probe_type = PROBE_PREFER_ASYNCHRONOUS, 3219 }, 3220 .probe = rt5682s_i2c_probe, 3221 .remove = rt5682s_i2c_remove, 3222 .shutdown = rt5682s_i2c_shutdown, 3223 .id_table = rt5682s_i2c_id, 3224 }; 3225 module_i2c_driver(rt5682s_i2c_driver); 3226 3227 MODULE_DESCRIPTION("ASoC RT5682I-VS driver"); 3228 MODULE_AUTHOR("Derek Fang <derek.fang@realtek.com>"); 3229 MODULE_LICENSE("GPL v2"); 3230