xref: /openbmc/linux/sound/soc/codecs/rt5682s.c (revision 06a95f71)
1 // SPDX-License-Identifier: GPL-2.0-only
2 //
3 // rt5682s.c  --  RT5682I-VS ALSA SoC audio component driver
4 //
5 // Copyright 2021 Realtek Semiconductor Corp.
6 // Author: Derek Fang <derek.fang@realtek.com>
7 //
8 
9 #include <linux/module.h>
10 #include <linux/moduleparam.h>
11 #include <linux/init.h>
12 #include <linux/delay.h>
13 #include <linux/pm.h>
14 #include <linux/i2c.h>
15 #include <linux/platform_device.h>
16 #include <linux/spi/spi.h>
17 #include <linux/acpi.h>
18 #include <linux/gpio/consumer.h>
19 #include <linux/mutex.h>
20 #include <sound/core.h>
21 #include <sound/pcm.h>
22 #include <sound/pcm_params.h>
23 #include <sound/jack.h>
24 #include <sound/soc.h>
25 #include <sound/soc-dapm.h>
26 #include <sound/initval.h>
27 #include <sound/tlv.h>
28 #include <sound/rt5682s.h>
29 
30 #include "rt5682s.h"
31 
32 #define DEVICE_ID 0x6749
33 
34 static const struct rt5682s_platform_data i2s_default_platform_data = {
35 	.dmic1_data_pin = RT5682S_DMIC1_DATA_GPIO2,
36 	.dmic1_clk_pin = RT5682S_DMIC1_CLK_GPIO3,
37 	.jd_src = RT5682S_JD1,
38 	.dai_clk_names[RT5682S_DAI_WCLK_IDX] = "rt5682-dai-wclk",
39 	.dai_clk_names[RT5682S_DAI_BCLK_IDX] = "rt5682-dai-bclk",
40 };
41 
42 static const char *rt5682s_supply_names[RT5682S_NUM_SUPPLIES] = {
43 	[RT5682S_SUPPLY_AVDD] = "AVDD",
44 	[RT5682S_SUPPLY_MICVDD] = "MICVDD",
45 	[RT5682S_SUPPLY_DBVDD] = "DBVDD",
46 	[RT5682S_SUPPLY_LDO1_IN] = "LDO1-IN",
47 };
48 
49 static const struct reg_sequence patch_list[] = {
50 	{RT5682S_I2C_CTRL,			0x0007},
51 	{RT5682S_DIG_IN_CTRL_1,			0x0000},
52 	{RT5682S_CHOP_DAC_2,			0x2020},
53 	{RT5682S_VREF_REC_OP_FB_CAP_CTRL_2,	0x0101},
54 	{RT5682S_VREF_REC_OP_FB_CAP_CTRL_1,	0x80c0},
55 	{RT5682S_HP_CALIB_CTRL_9,		0x0002},
56 	{RT5682S_DEPOP_1,			0x0000},
57 	{RT5682S_HP_CHARGE_PUMP_2,		0x3c15},
58 	{RT5682S_DAC1_DIG_VOL,			0xfefe},
59 	{RT5682S_SAR_IL_CMD_2,			0xac00},
60 	{RT5682S_SAR_IL_CMD_3,			0x024c},
61 	{RT5682S_CBJ_CTRL_6,			0x0804},
62 };
63 
rt5682s_apply_patch_list(struct rt5682s_priv * rt5682s,struct device * dev)64 static void rt5682s_apply_patch_list(struct rt5682s_priv *rt5682s,
65 		struct device *dev)
66 {
67 	int ret;
68 
69 	ret = regmap_multi_reg_write(rt5682s->regmap, patch_list, ARRAY_SIZE(patch_list));
70 	if (ret)
71 		dev_warn(dev, "Failed to apply regmap patch: %d\n", ret);
72 }
73 
74 static const struct reg_default rt5682s_reg[] = {
75 	{0x0002, 0x8080},
76 	{0x0003, 0x0001},
77 	{0x0005, 0x0000},
78 	{0x0006, 0x0000},
79 	{0x0008, 0x8007},
80 	{0x000b, 0x0000},
81 	{0x000f, 0x4000},
82 	{0x0010, 0x4040},
83 	{0x0011, 0x0000},
84 	{0x0012, 0x0000},
85 	{0x0013, 0x1200},
86 	{0x0014, 0x200a},
87 	{0x0015, 0x0404},
88 	{0x0016, 0x0404},
89 	{0x0017, 0x05a4},
90 	{0x0019, 0xffff},
91 	{0x001c, 0x2f2f},
92 	{0x001f, 0x0000},
93 	{0x0022, 0x5757},
94 	{0x0023, 0x0039},
95 	{0x0024, 0x000b},
96 	{0x0026, 0xc0c4},
97 	{0x0029, 0x8080},
98 	{0x002a, 0xa0a0},
99 	{0x002b, 0x0300},
100 	{0x0030, 0x0000},
101 	{0x003c, 0x08c0},
102 	{0x0044, 0x1818},
103 	{0x004b, 0x00c0},
104 	{0x004c, 0x0000},
105 	{0x004d, 0x0000},
106 	{0x0061, 0x00c0},
107 	{0x0062, 0x008a},
108 	{0x0063, 0x0800},
109 	{0x0064, 0x0000},
110 	{0x0065, 0x0000},
111 	{0x0066, 0x0030},
112 	{0x0067, 0x000c},
113 	{0x0068, 0x0000},
114 	{0x0069, 0x0000},
115 	{0x006a, 0x0000},
116 	{0x006b, 0x0000},
117 	{0x006c, 0x0000},
118 	{0x006d, 0x2200},
119 	{0x006e, 0x0810},
120 	{0x006f, 0xe4de},
121 	{0x0070, 0x3320},
122 	{0x0071, 0x0000},
123 	{0x0073, 0x0000},
124 	{0x0074, 0x0000},
125 	{0x0075, 0x0002},
126 	{0x0076, 0x0001},
127 	{0x0079, 0x0000},
128 	{0x007a, 0x0000},
129 	{0x007b, 0x0000},
130 	{0x007c, 0x0100},
131 	{0x007e, 0x0000},
132 	{0x007f, 0x0000},
133 	{0x0080, 0x0000},
134 	{0x0083, 0x0000},
135 	{0x0084, 0x0000},
136 	{0x0085, 0x0000},
137 	{0x0086, 0x0005},
138 	{0x0087, 0x0000},
139 	{0x0088, 0x0000},
140 	{0x008c, 0x0003},
141 	{0x008e, 0x0060},
142 	{0x008f, 0x4da1},
143 	{0x0091, 0x1c15},
144 	{0x0092, 0x0425},
145 	{0x0093, 0x0000},
146 	{0x0094, 0x0080},
147 	{0x0095, 0x008f},
148 	{0x0096, 0x0000},
149 	{0x0097, 0x0000},
150 	{0x0098, 0x0000},
151 	{0x0099, 0x0000},
152 	{0x009a, 0x0000},
153 	{0x009b, 0x0000},
154 	{0x009c, 0x0000},
155 	{0x009d, 0x0000},
156 	{0x009e, 0x0000},
157 	{0x009f, 0x0009},
158 	{0x00a0, 0x0000},
159 	{0x00a3, 0x0002},
160 	{0x00a4, 0x0001},
161 	{0x00b6, 0x0000},
162 	{0x00b7, 0x0000},
163 	{0x00b8, 0x0000},
164 	{0x00b9, 0x0002},
165 	{0x00be, 0x0000},
166 	{0x00c0, 0x0160},
167 	{0x00c1, 0x82a0},
168 	{0x00c2, 0x0000},
169 	{0x00d0, 0x0000},
170 	{0x00d2, 0x3300},
171 	{0x00d3, 0x2200},
172 	{0x00d4, 0x0000},
173 	{0x00d9, 0x0000},
174 	{0x00da, 0x0000},
175 	{0x00db, 0x0000},
176 	{0x00dc, 0x00c0},
177 	{0x00dd, 0x2220},
178 	{0x00de, 0x3131},
179 	{0x00df, 0x3131},
180 	{0x00e0, 0x3131},
181 	{0x00e2, 0x0000},
182 	{0x00e3, 0x4000},
183 	{0x00e4, 0x0aa0},
184 	{0x00e5, 0x3131},
185 	{0x00e6, 0x3131},
186 	{0x00e7, 0x3131},
187 	{0x00e8, 0x3131},
188 	{0x00ea, 0xb320},
189 	{0x00eb, 0x0000},
190 	{0x00f0, 0x0000},
191 	{0x00f6, 0x0000},
192 	{0x00fa, 0x0000},
193 	{0x00fb, 0x0000},
194 	{0x00fc, 0x0000},
195 	{0x00fd, 0x0000},
196 	{0x00fe, 0x10ec},
197 	{0x00ff, 0x6749},
198 	{0x0100, 0xa000},
199 	{0x010b, 0x0066},
200 	{0x010c, 0x6666},
201 	{0x010d, 0x2202},
202 	{0x010e, 0x6666},
203 	{0x010f, 0xa800},
204 	{0x0110, 0x0006},
205 	{0x0111, 0x0460},
206 	{0x0112, 0x2000},
207 	{0x0113, 0x0200},
208 	{0x0117, 0x8000},
209 	{0x0118, 0x0303},
210 	{0x0125, 0x0020},
211 	{0x0132, 0x5026},
212 	{0x0136, 0x8000},
213 	{0x0139, 0x0005},
214 	{0x013a, 0x3030},
215 	{0x013b, 0xa000},
216 	{0x013c, 0x4110},
217 	{0x013f, 0x0000},
218 	{0x0145, 0x0022},
219 	{0x0146, 0x0000},
220 	{0x0147, 0x0000},
221 	{0x0148, 0x0000},
222 	{0x0156, 0x0022},
223 	{0x0157, 0x0303},
224 	{0x0158, 0x2222},
225 	{0x0159, 0x0000},
226 	{0x0160, 0x4ec0},
227 	{0x0161, 0x0080},
228 	{0x0162, 0x0200},
229 	{0x0163, 0x0800},
230 	{0x0164, 0x0000},
231 	{0x0165, 0x0000},
232 	{0x0166, 0x0000},
233 	{0x0167, 0x000f},
234 	{0x0168, 0x000f},
235 	{0x0169, 0x0001},
236 	{0x0190, 0x4131},
237 	{0x0194, 0x0000},
238 	{0x0195, 0x0000},
239 	{0x0197, 0x0022},
240 	{0x0198, 0x0000},
241 	{0x0199, 0x0000},
242 	{0x01ac, 0x0000},
243 	{0x01ad, 0x0000},
244 	{0x01ae, 0x0000},
245 	{0x01af, 0x2000},
246 	{0x01b0, 0x0000},
247 	{0x01b1, 0x0000},
248 	{0x01b2, 0x0000},
249 	{0x01b3, 0x0017},
250 	{0x01b4, 0x004b},
251 	{0x01b5, 0x0000},
252 	{0x01b6, 0x03e8},
253 	{0x01b7, 0x0000},
254 	{0x01b8, 0x0000},
255 	{0x01b9, 0x0400},
256 	{0x01ba, 0xb5b6},
257 	{0x01bb, 0x9124},
258 	{0x01bc, 0x4924},
259 	{0x01bd, 0x0009},
260 	{0x01be, 0x0018},
261 	{0x01bf, 0x002a},
262 	{0x01c0, 0x004c},
263 	{0x01c1, 0x0097},
264 	{0x01c2, 0x01c3},
265 	{0x01c3, 0x03e9},
266 	{0x01c4, 0x1389},
267 	{0x01c5, 0xc351},
268 	{0x01c6, 0x02a0},
269 	{0x01c7, 0x0b0f},
270 	{0x01c8, 0x402f},
271 	{0x01c9, 0x0702},
272 	{0x01ca, 0x0000},
273 	{0x01cb, 0x0000},
274 	{0x01cc, 0x5757},
275 	{0x01cd, 0x5757},
276 	{0x01ce, 0x5757},
277 	{0x01cf, 0x5757},
278 	{0x01d0, 0x5757},
279 	{0x01d1, 0x5757},
280 	{0x01d2, 0x5757},
281 	{0x01d3, 0x5757},
282 	{0x01d4, 0x5757},
283 	{0x01d5, 0x5757},
284 	{0x01d6, 0x0000},
285 	{0x01d7, 0x0000},
286 	{0x01d8, 0x0162},
287 	{0x01d9, 0x0007},
288 	{0x01da, 0x0000},
289 	{0x01db, 0x0004},
290 	{0x01dc, 0x0000},
291 	{0x01de, 0x7c00},
292 	{0x01df, 0x0020},
293 	{0x01e0, 0x04c1},
294 	{0x01e1, 0x0000},
295 	{0x01e2, 0x0000},
296 	{0x01e3, 0x0000},
297 	{0x01e4, 0x0000},
298 	{0x01e5, 0x0000},
299 	{0x01e6, 0x0001},
300 	{0x01e7, 0x0000},
301 	{0x01e8, 0x0000},
302 	{0x01eb, 0x0000},
303 	{0x01ec, 0x0000},
304 	{0x01ed, 0x0000},
305 	{0x01ee, 0x0000},
306 	{0x01ef, 0x0000},
307 	{0x01f0, 0x0000},
308 	{0x01f1, 0x0000},
309 	{0x01f2, 0x0000},
310 	{0x01f3, 0x0000},
311 	{0x01f4, 0x0000},
312 	{0x0210, 0x6297},
313 	{0x0211, 0xa004},
314 	{0x0212, 0x0365},
315 	{0x0213, 0xf7ff},
316 	{0x0214, 0xf24c},
317 	{0x0215, 0x0102},
318 	{0x0216, 0x00a3},
319 	{0x0217, 0x0048},
320 	{0x0218, 0xa2c0},
321 	{0x0219, 0x0400},
322 	{0x021a, 0x00c8},
323 	{0x021b, 0x00c0},
324 	{0x021c, 0x0000},
325 	{0x021d, 0x024c},
326 	{0x02fa, 0x0000},
327 	{0x02fb, 0x0000},
328 	{0x02fc, 0x0000},
329 	{0x03fe, 0x0000},
330 	{0x03ff, 0x0000},
331 	{0x0500, 0x0000},
332 	{0x0600, 0x0000},
333 	{0x0610, 0x6666},
334 	{0x0611, 0xa9aa},
335 	{0x0620, 0x6666},
336 	{0x0621, 0xa9aa},
337 	{0x0630, 0x6666},
338 	{0x0631, 0xa9aa},
339 	{0x0640, 0x6666},
340 	{0x0641, 0xa9aa},
341 	{0x07fa, 0x0000},
342 	{0x08fa, 0x0000},
343 	{0x08fb, 0x0000},
344 	{0x0d00, 0x0000},
345 	{0x1100, 0x0000},
346 	{0x1101, 0x0000},
347 	{0x1102, 0x0000},
348 	{0x1103, 0x0000},
349 	{0x1104, 0x0000},
350 	{0x1105, 0x0000},
351 	{0x1106, 0x0000},
352 	{0x1107, 0x0000},
353 	{0x1108, 0x0000},
354 	{0x1109, 0x0000},
355 	{0x110a, 0x0000},
356 	{0x110b, 0x0000},
357 	{0x110c, 0x0000},
358 	{0x1111, 0x0000},
359 	{0x1112, 0x0000},
360 	{0x1113, 0x0000},
361 	{0x1114, 0x0000},
362 	{0x1115, 0x0000},
363 	{0x1116, 0x0000},
364 	{0x1117, 0x0000},
365 	{0x1118, 0x0000},
366 	{0x1119, 0x0000},
367 	{0x111a, 0x0000},
368 	{0x111b, 0x0000},
369 	{0x111c, 0x0000},
370 	{0x1401, 0x0404},
371 	{0x1402, 0x0007},
372 	{0x1403, 0x0365},
373 	{0x1404, 0x0210},
374 	{0x1405, 0x0365},
375 	{0x1406, 0x0210},
376 	{0x1407, 0x0000},
377 	{0x1408, 0x0000},
378 	{0x1409, 0x0000},
379 	{0x140a, 0x0000},
380 	{0x140b, 0x0000},
381 	{0x140c, 0x0000},
382 	{0x140d, 0x0000},
383 	{0x140e, 0x0000},
384 	{0x140f, 0x0000},
385 	{0x1410, 0x0000},
386 	{0x1411, 0x0000},
387 	{0x1801, 0x0004},
388 	{0x1802, 0x0000},
389 	{0x1803, 0x0000},
390 	{0x1804, 0x0000},
391 	{0x1805, 0x00ff},
392 	{0x2c00, 0x0000},
393 	{0x3400, 0x0200},
394 	{0x3404, 0x0000},
395 	{0x3405, 0x0000},
396 	{0x3406, 0x0000},
397 	{0x3407, 0x0000},
398 	{0x3408, 0x0000},
399 	{0x3409, 0x0000},
400 	{0x340a, 0x0000},
401 	{0x340b, 0x0000},
402 	{0x340c, 0x0000},
403 	{0x340d, 0x0000},
404 	{0x340e, 0x0000},
405 	{0x340f, 0x0000},
406 	{0x3410, 0x0000},
407 	{0x3411, 0x0000},
408 	{0x3412, 0x0000},
409 	{0x3413, 0x0000},
410 	{0x3414, 0x0000},
411 	{0x3415, 0x0000},
412 	{0x3424, 0x0000},
413 	{0x3425, 0x0000},
414 	{0x3426, 0x0000},
415 	{0x3427, 0x0000},
416 	{0x3428, 0x0000},
417 	{0x3429, 0x0000},
418 	{0x342a, 0x0000},
419 	{0x342b, 0x0000},
420 	{0x342c, 0x0000},
421 	{0x342d, 0x0000},
422 	{0x342e, 0x0000},
423 	{0x342f, 0x0000},
424 	{0x3430, 0x0000},
425 	{0x3431, 0x0000},
426 	{0x3432, 0x0000},
427 	{0x3433, 0x0000},
428 	{0x3434, 0x0000},
429 	{0x3435, 0x0000},
430 	{0x3440, 0x6319},
431 	{0x3441, 0x3771},
432 	{0x3500, 0x0002},
433 	{0x3501, 0x5728},
434 	{0x3b00, 0x3010},
435 	{0x3b01, 0x3300},
436 	{0x3b02, 0x2200},
437 	{0x3b03, 0x0100},
438 };
439 
rt5682s_volatile_register(struct device * dev,unsigned int reg)440 static bool rt5682s_volatile_register(struct device *dev, unsigned int reg)
441 {
442 	switch (reg) {
443 	case RT5682S_RESET:
444 	case RT5682S_CBJ_CTRL_2:
445 	case RT5682S_I2S1_F_DIV_CTRL_2:
446 	case RT5682S_I2S2_F_DIV_CTRL_2:
447 	case RT5682S_INT_ST_1:
448 	case RT5682S_GPIO_ST:
449 	case RT5682S_IL_CMD_1:
450 	case RT5682S_4BTN_IL_CMD_1:
451 	case RT5682S_AJD1_CTRL:
452 	case RT5682S_VERSION_ID...RT5682S_DEVICE_ID:
453 	case RT5682S_STO_NG2_CTRL_1:
454 	case RT5682S_STO_NG2_CTRL_5...RT5682S_STO_NG2_CTRL_7:
455 	case RT5682S_STO1_DAC_SIL_DET:
456 	case RT5682S_HP_IMP_SENS_CTRL_1...RT5682S_HP_IMP_SENS_CTRL_4:
457 	case RT5682S_HP_IMP_SENS_CTRL_13:
458 	case RT5682S_HP_IMP_SENS_CTRL_14:
459 	case RT5682S_HP_IMP_SENS_CTRL_43...RT5682S_HP_IMP_SENS_CTRL_46:
460 	case RT5682S_HP_CALIB_CTRL_1:
461 	case RT5682S_HP_CALIB_CTRL_10:
462 	case RT5682S_HP_CALIB_ST_1...RT5682S_HP_CALIB_ST_11:
463 	case RT5682S_SAR_IL_CMD_2...RT5682S_SAR_IL_CMD_5:
464 	case RT5682S_SAR_IL_CMD_10:
465 	case RT5682S_SAR_IL_CMD_11:
466 	case RT5682S_VERSION_ID_HIDE:
467 	case RT5682S_VERSION_ID_CUS:
468 	case RT5682S_I2C_TRANS_CTRL:
469 	case RT5682S_DMIC_FLOAT_DET:
470 	case RT5682S_HA_CMP_OP_1:
471 	case RT5682S_NEW_CBJ_DET_CTL_10...RT5682S_NEW_CBJ_DET_CTL_16:
472 	case RT5682S_CLK_SW_TEST_1:
473 	case RT5682S_CLK_SW_TEST_2:
474 	case RT5682S_EFUSE_READ_1...RT5682S_EFUSE_READ_18:
475 	case RT5682S_PILOT_DIG_CTL_1:
476 		return true;
477 	default:
478 		return false;
479 	}
480 }
481 
rt5682s_readable_register(struct device * dev,unsigned int reg)482 static bool rt5682s_readable_register(struct device *dev, unsigned int reg)
483 {
484 	switch (reg) {
485 	case RT5682S_RESET:
486 	case RT5682S_VERSION_ID:
487 	case RT5682S_VENDOR_ID:
488 	case RT5682S_DEVICE_ID:
489 	case RT5682S_HP_CTRL_1:
490 	case RT5682S_HP_CTRL_2:
491 	case RT5682S_HPL_GAIN:
492 	case RT5682S_HPR_GAIN:
493 	case RT5682S_I2C_CTRL:
494 	case RT5682S_CBJ_BST_CTRL:
495 	case RT5682S_CBJ_DET_CTRL:
496 	case RT5682S_CBJ_CTRL_1...RT5682S_CBJ_CTRL_8:
497 	case RT5682S_DAC1_DIG_VOL:
498 	case RT5682S_STO1_ADC_DIG_VOL:
499 	case RT5682S_STO1_ADC_BOOST:
500 	case RT5682S_HP_IMP_GAIN_1:
501 	case RT5682S_HP_IMP_GAIN_2:
502 	case RT5682S_SIDETONE_CTRL:
503 	case RT5682S_STO1_ADC_MIXER:
504 	case RT5682S_AD_DA_MIXER:
505 	case RT5682S_STO1_DAC_MIXER:
506 	case RT5682S_A_DAC1_MUX:
507 	case RT5682S_DIG_INF2_DATA:
508 	case RT5682S_REC_MIXER:
509 	case RT5682S_CAL_REC:
510 	case RT5682S_HP_ANA_OST_CTRL_1...RT5682S_HP_ANA_OST_CTRL_3:
511 	case RT5682S_PWR_DIG_1...RT5682S_PWR_MIXER:
512 	case RT5682S_MB_CTRL:
513 	case RT5682S_CLK_GATE_TCON_1...RT5682S_CLK_GATE_TCON_3:
514 	case RT5682S_CLK_DET...RT5682S_LPF_AD_DMIC:
515 	case RT5682S_I2S1_SDP:
516 	case RT5682S_I2S2_SDP:
517 	case RT5682S_ADDA_CLK_1:
518 	case RT5682S_ADDA_CLK_2:
519 	case RT5682S_I2S1_F_DIV_CTRL_1:
520 	case RT5682S_I2S1_F_DIV_CTRL_2:
521 	case RT5682S_TDM_CTRL:
522 	case RT5682S_TDM_ADDA_CTRL_1:
523 	case RT5682S_TDM_ADDA_CTRL_2:
524 	case RT5682S_DATA_SEL_CTRL_1:
525 	case RT5682S_TDM_TCON_CTRL_1:
526 	case RT5682S_TDM_TCON_CTRL_2:
527 	case RT5682S_GLB_CLK:
528 	case RT5682S_PLL_TRACK_1...RT5682S_PLL_TRACK_6:
529 	case RT5682S_PLL_TRACK_11:
530 	case RT5682S_DEPOP_1:
531 	case RT5682S_HP_CHARGE_PUMP_1:
532 	case RT5682S_HP_CHARGE_PUMP_2:
533 	case RT5682S_HP_CHARGE_PUMP_3:
534 	case RT5682S_MICBIAS_1...RT5682S_MICBIAS_3:
535 	case RT5682S_PLL_TRACK_12...RT5682S_PLL_CTRL_7:
536 	case RT5682S_RC_CLK_CTRL:
537 	case RT5682S_I2S2_M_CLK_CTRL_1:
538 	case RT5682S_I2S2_F_DIV_CTRL_1:
539 	case RT5682S_I2S2_F_DIV_CTRL_2:
540 	case RT5682S_IRQ_CTRL_1...RT5682S_IRQ_CTRL_4:
541 	case RT5682S_INT_ST_1:
542 	case RT5682S_GPIO_CTRL_1:
543 	case RT5682S_GPIO_CTRL_2:
544 	case RT5682S_GPIO_ST:
545 	case RT5682S_HP_AMP_DET_CTRL_1:
546 	case RT5682S_MID_HP_AMP_DET:
547 	case RT5682S_LOW_HP_AMP_DET:
548 	case RT5682S_DELAY_BUF_CTRL:
549 	case RT5682S_SV_ZCD_1:
550 	case RT5682S_SV_ZCD_2:
551 	case RT5682S_IL_CMD_1...RT5682S_IL_CMD_6:
552 	case RT5682S_4BTN_IL_CMD_1...RT5682S_4BTN_IL_CMD_7:
553 	case RT5682S_ADC_STO1_HP_CTRL_1:
554 	case RT5682S_ADC_STO1_HP_CTRL_2:
555 	case RT5682S_AJD1_CTRL:
556 	case RT5682S_JD_CTRL_1:
557 	case RT5682S_DUMMY_1...RT5682S_DUMMY_3:
558 	case RT5682S_DAC_ADC_DIG_VOL1:
559 	case RT5682S_BIAS_CUR_CTRL_2...RT5682S_BIAS_CUR_CTRL_10:
560 	case RT5682S_VREF_REC_OP_FB_CAP_CTRL_1:
561 	case RT5682S_VREF_REC_OP_FB_CAP_CTRL_2:
562 	case RT5682S_CHARGE_PUMP_1:
563 	case RT5682S_DIG_IN_CTRL_1:
564 	case RT5682S_PAD_DRIVING_CTRL:
565 	case RT5682S_CHOP_DAC_1:
566 	case RT5682S_CHOP_DAC_2:
567 	case RT5682S_CHOP_ADC:
568 	case RT5682S_CALIB_ADC_CTRL:
569 	case RT5682S_VOL_TEST:
570 	case RT5682S_SPKVDD_DET_ST:
571 	case RT5682S_TEST_MODE_CTRL_1...RT5682S_TEST_MODE_CTRL_4:
572 	case RT5682S_PLL_INTERNAL_1...RT5682S_PLL_INTERNAL_4:
573 	case RT5682S_STO_NG2_CTRL_1...RT5682S_STO_NG2_CTRL_10:
574 	case RT5682S_STO1_DAC_SIL_DET:
575 	case RT5682S_SIL_PSV_CTRL1:
576 	case RT5682S_SIL_PSV_CTRL2:
577 	case RT5682S_SIL_PSV_CTRL3:
578 	case RT5682S_SIL_PSV_CTRL4:
579 	case RT5682S_SIL_PSV_CTRL5:
580 	case RT5682S_HP_IMP_SENS_CTRL_1...RT5682S_HP_IMP_SENS_CTRL_46:
581 	case RT5682S_HP_LOGIC_CTRL_1...RT5682S_HP_LOGIC_CTRL_3:
582 	case RT5682S_HP_CALIB_CTRL_1...RT5682S_HP_CALIB_CTRL_11:
583 	case RT5682S_HP_CALIB_ST_1...RT5682S_HP_CALIB_ST_11:
584 	case RT5682S_SAR_IL_CMD_1...RT5682S_SAR_IL_CMD_14:
585 	case RT5682S_DUMMY_4...RT5682S_DUMMY_6:
586 	case RT5682S_VERSION_ID_HIDE:
587 	case RT5682S_VERSION_ID_CUS:
588 	case RT5682S_SCAN_CTL:
589 	case RT5682S_HP_AMP_DET:
590 	case RT5682S_BIAS_CUR_CTRL_11:
591 	case RT5682S_BIAS_CUR_CTRL_12:
592 	case RT5682S_BIAS_CUR_CTRL_13:
593 	case RT5682S_BIAS_CUR_CTRL_14:
594 	case RT5682S_BIAS_CUR_CTRL_15:
595 	case RT5682S_BIAS_CUR_CTRL_16:
596 	case RT5682S_BIAS_CUR_CTRL_17:
597 	case RT5682S_BIAS_CUR_CTRL_18:
598 	case RT5682S_I2C_TRANS_CTRL:
599 	case RT5682S_DUMMY_7:
600 	case RT5682S_DUMMY_8:
601 	case RT5682S_DMIC_FLOAT_DET:
602 	case RT5682S_HA_CMP_OP_1...RT5682S_HA_CMP_OP_13:
603 	case RT5682S_HA_CMP_OP_14...RT5682S_HA_CMP_OP_25:
604 	case RT5682S_NEW_CBJ_DET_CTL_1...RT5682S_NEW_CBJ_DET_CTL_16:
605 	case RT5682S_DA_FILTER_1...RT5682S_DA_FILTER_5:
606 	case RT5682S_CLK_SW_TEST_1:
607 	case RT5682S_CLK_SW_TEST_2:
608 	case RT5682S_CLK_SW_TEST_3...RT5682S_CLK_SW_TEST_14:
609 	case RT5682S_EFUSE_MANU_WRITE_1...RT5682S_EFUSE_MANU_WRITE_6:
610 	case RT5682S_EFUSE_READ_1...RT5682S_EFUSE_READ_18:
611 	case RT5682S_EFUSE_TIMING_CTL_1:
612 	case RT5682S_EFUSE_TIMING_CTL_2:
613 	case RT5682S_PILOT_DIG_CTL_1:
614 	case RT5682S_PILOT_DIG_CTL_2:
615 	case RT5682S_HP_AMP_DET_CTL_1...RT5682S_HP_AMP_DET_CTL_4:
616 		return true;
617 	default:
618 		return false;
619 	}
620 }
621 
rt5682s_reset(struct rt5682s_priv * rt5682s)622 static void rt5682s_reset(struct rt5682s_priv *rt5682s)
623 {
624 	regmap_write(rt5682s->regmap, RT5682S_RESET, 0);
625 }
626 
rt5682s_button_detect(struct snd_soc_component * component)627 static int rt5682s_button_detect(struct snd_soc_component *component)
628 {
629 	int btn_type, val;
630 
631 	val = snd_soc_component_read(component, RT5682S_4BTN_IL_CMD_1);
632 	btn_type = val & 0xfff0;
633 	snd_soc_component_write(component, RT5682S_4BTN_IL_CMD_1, val);
634 	dev_dbg(component->dev, "%s btn_type=%x\n", __func__, btn_type);
635 	snd_soc_component_update_bits(component, RT5682S_SAR_IL_CMD_2,
636 		RT5682S_SAR_ADC_PSV_MASK, RT5682S_SAR_ADC_PSV_ENTRY);
637 
638 	return btn_type;
639 }
640 
641 enum {
642 	SAR_PWR_OFF,
643 	SAR_PWR_NORMAL,
644 	SAR_PWR_SAVING,
645 };
646 
rt5682s_sar_power_mode(struct snd_soc_component * component,int mode)647 static void rt5682s_sar_power_mode(struct snd_soc_component *component, int mode)
648 {
649 	struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component);
650 
651 	mutex_lock(&rt5682s->sar_mutex);
652 
653 	switch (mode) {
654 	case SAR_PWR_SAVING:
655 		snd_soc_component_update_bits(component, RT5682S_CBJ_CTRL_3,
656 			RT5682S_CBJ_IN_BUF_MASK, RT5682S_CBJ_IN_BUF_DIS);
657 		snd_soc_component_update_bits(component, RT5682S_CBJ_CTRL_1,
658 			RT5682S_MB1_PATH_MASK | RT5682S_MB2_PATH_MASK,
659 			RT5682S_CTRL_MB1_REG | RT5682S_CTRL_MB2_REG);
660 		snd_soc_component_update_bits(component, RT5682S_SAR_IL_CMD_1,
661 			RT5682S_SAR_BUTDET_MASK | RT5682S_SAR_BUTDET_POW_MASK |
662 			RT5682S_SAR_SEL_MB1_2_CTL_MASK, RT5682S_SAR_BUTDET_DIS |
663 			RT5682S_SAR_BUTDET_POW_SAV | RT5682S_SAR_SEL_MB1_2_MANU);
664 		usleep_range(5000, 5500);
665 		snd_soc_component_update_bits(component, RT5682S_SAR_IL_CMD_1,
666 			RT5682S_SAR_BUTDET_MASK, RT5682S_SAR_BUTDET_EN);
667 		usleep_range(5000, 5500);
668 		snd_soc_component_update_bits(component, RT5682S_SAR_IL_CMD_2,
669 			RT5682S_SAR_ADC_PSV_MASK, RT5682S_SAR_ADC_PSV_ENTRY);
670 		break;
671 	case SAR_PWR_NORMAL:
672 		snd_soc_component_update_bits(component, RT5682S_CBJ_CTRL_3,
673 			RT5682S_CBJ_IN_BUF_MASK, RT5682S_CBJ_IN_BUF_EN);
674 		snd_soc_component_update_bits(component, RT5682S_CBJ_CTRL_1,
675 			RT5682S_MB1_PATH_MASK | RT5682S_MB2_PATH_MASK,
676 			RT5682S_CTRL_MB1_FSM | RT5682S_CTRL_MB2_FSM);
677 		snd_soc_component_update_bits(component, RT5682S_SAR_IL_CMD_1,
678 			RT5682S_SAR_SEL_MB1_2_CTL_MASK, RT5682S_SAR_SEL_MB1_2_AUTO);
679 		usleep_range(5000, 5500);
680 		snd_soc_component_update_bits(component, RT5682S_SAR_IL_CMD_1,
681 			RT5682S_SAR_BUTDET_MASK | RT5682S_SAR_BUTDET_POW_MASK,
682 			RT5682S_SAR_BUTDET_EN | RT5682S_SAR_BUTDET_POW_NORM);
683 		break;
684 	case SAR_PWR_OFF:
685 		snd_soc_component_update_bits(component, RT5682S_CBJ_CTRL_1,
686 			RT5682S_MB1_PATH_MASK | RT5682S_MB2_PATH_MASK,
687 			RT5682S_CTRL_MB1_FSM | RT5682S_CTRL_MB2_FSM);
688 		snd_soc_component_update_bits(component, RT5682S_SAR_IL_CMD_1,
689 			RT5682S_SAR_BUTDET_MASK | RT5682S_SAR_BUTDET_POW_MASK |
690 			RT5682S_SAR_SEL_MB1_2_CTL_MASK, RT5682S_SAR_BUTDET_DIS |
691 			RT5682S_SAR_BUTDET_POW_SAV | RT5682S_SAR_SEL_MB1_2_MANU);
692 		break;
693 	default:
694 		dev_err(component->dev, "Invalid SAR Power mode: %d\n", mode);
695 		break;
696 	}
697 
698 	mutex_unlock(&rt5682s->sar_mutex);
699 }
700 
rt5682s_enable_push_button_irq(struct snd_soc_component * component)701 static void rt5682s_enable_push_button_irq(struct snd_soc_component *component)
702 {
703 	snd_soc_component_update_bits(component, RT5682S_SAR_IL_CMD_13,
704 		RT5682S_SAR_SOUR_MASK, RT5682S_SAR_SOUR_BTN);
705 	snd_soc_component_update_bits(component, RT5682S_SAR_IL_CMD_1,
706 		RT5682S_SAR_BUTDET_MASK | RT5682S_SAR_BUTDET_POW_MASK |
707 		RT5682S_SAR_SEL_MB1_2_CTL_MASK, RT5682S_SAR_BUTDET_EN |
708 		RT5682S_SAR_BUTDET_POW_NORM | RT5682S_SAR_SEL_MB1_2_AUTO);
709 	snd_soc_component_write(component, RT5682S_IL_CMD_1, 0x0040);
710 	snd_soc_component_update_bits(component, RT5682S_4BTN_IL_CMD_2,
711 		RT5682S_4BTN_IL_MASK | RT5682S_4BTN_IL_RST_MASK,
712 		RT5682S_4BTN_IL_EN | RT5682S_4BTN_IL_NOR);
713 	snd_soc_component_update_bits(component, RT5682S_IRQ_CTRL_3,
714 		RT5682S_IL_IRQ_MASK, RT5682S_IL_IRQ_EN);
715 }
716 
rt5682s_disable_push_button_irq(struct snd_soc_component * component)717 static void rt5682s_disable_push_button_irq(struct snd_soc_component *component)
718 {
719 	snd_soc_component_update_bits(component, RT5682S_IRQ_CTRL_3,
720 		RT5682S_IL_IRQ_MASK, RT5682S_IL_IRQ_DIS);
721 	snd_soc_component_update_bits(component, RT5682S_4BTN_IL_CMD_2,
722 		RT5682S_4BTN_IL_MASK, RT5682S_4BTN_IL_DIS);
723 	snd_soc_component_update_bits(component, RT5682S_SAR_IL_CMD_13,
724 		RT5682S_SAR_SOUR_MASK, RT5682S_SAR_SOUR_TYPE);
725 	snd_soc_component_update_bits(component, RT5682S_SAR_IL_CMD_1,
726 		RT5682S_SAR_BUTDET_MASK | RT5682S_SAR_BUTDET_POW_MASK |
727 		RT5682S_SAR_SEL_MB1_2_CTL_MASK, RT5682S_SAR_BUTDET_DIS |
728 		RT5682S_SAR_BUTDET_POW_SAV | RT5682S_SAR_SEL_MB1_2_MANU);
729 }
730 
731 /**
732  * rt5682s_headset_detect - Detect headset.
733  * @component: SoC audio component device.
734  * @jack_insert: Jack insert or not.
735  *
736  * Detect whether is headset or not when jack inserted.
737  *
738  * Returns detect status.
739  */
rt5682s_headset_detect(struct snd_soc_component * component,int jack_insert)740 static int rt5682s_headset_detect(struct snd_soc_component *component, int jack_insert)
741 {
742 	struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component);
743 	unsigned int val, count;
744 	int jack_type = 0;
745 
746 	if (jack_insert) {
747 		rt5682s_disable_push_button_irq(component);
748 		snd_soc_component_update_bits(component, RT5682S_PWR_ANLG_1,
749 			RT5682S_PWR_VREF1 | RT5682S_PWR_VREF2 | RT5682S_PWR_MB,
750 			RT5682S_PWR_VREF1 | RT5682S_PWR_VREF2 | RT5682S_PWR_MB);
751 		snd_soc_component_update_bits(component, RT5682S_PWR_ANLG_1,
752 			RT5682S_PWR_FV1 | RT5682S_PWR_FV2, 0);
753 		usleep_range(15000, 20000);
754 		snd_soc_component_update_bits(component, RT5682S_PWR_ANLG_1,
755 			RT5682S_PWR_FV1 | RT5682S_PWR_FV2,
756 			RT5682S_PWR_FV1 | RT5682S_PWR_FV2);
757 		snd_soc_component_update_bits(component, RT5682S_PWR_ANLG_3,
758 			RT5682S_PWR_CBJ, RT5682S_PWR_CBJ);
759 		snd_soc_component_write(component, RT5682S_SAR_IL_CMD_3, 0x0365);
760 		snd_soc_component_update_bits(component, RT5682S_HP_CHARGE_PUMP_2,
761 			RT5682S_OSW_L_MASK | RT5682S_OSW_R_MASK,
762 			RT5682S_OSW_L_DIS | RT5682S_OSW_R_DIS);
763 		snd_soc_component_update_bits(component, RT5682S_SAR_IL_CMD_13,
764 			RT5682S_SAR_SOUR_MASK, RT5682S_SAR_SOUR_TYPE);
765 		snd_soc_component_update_bits(component, RT5682S_CBJ_CTRL_3,
766 			RT5682S_CBJ_IN_BUF_MASK, RT5682S_CBJ_IN_BUF_EN);
767 		snd_soc_component_update_bits(component, RT5682S_CBJ_CTRL_1,
768 			RT5682S_TRIG_JD_MASK, RT5682S_TRIG_JD_LOW);
769 		usleep_range(45000, 50000);
770 		snd_soc_component_update_bits(component, RT5682S_CBJ_CTRL_1,
771 			RT5682S_TRIG_JD_MASK, RT5682S_TRIG_JD_HIGH);
772 
773 		count = 0;
774 		do {
775 			usleep_range(10000, 15000);
776 			val = snd_soc_component_read(component, RT5682S_CBJ_CTRL_2)
777 				& RT5682S_JACK_TYPE_MASK;
778 			count++;
779 		} while (val == 0 && count < 50);
780 
781 		dev_dbg(component->dev, "%s, val=%d, count=%d\n", __func__, val, count);
782 
783 		switch (val) {
784 		case 0x1:
785 		case 0x2:
786 			jack_type = SND_JACK_HEADSET;
787 			snd_soc_component_write(component, RT5682S_SAR_IL_CMD_3, 0x024c);
788 			snd_soc_component_update_bits(component, RT5682S_CBJ_CTRL_1,
789 				RT5682S_FAST_OFF_MASK, RT5682S_FAST_OFF_EN);
790 			snd_soc_component_update_bits(component, RT5682S_SAR_IL_CMD_1,
791 				RT5682S_SAR_SEL_MB1_2_MASK, val << RT5682S_SAR_SEL_MB1_2_SFT);
792 			rt5682s_enable_push_button_irq(component);
793 			rt5682s_sar_power_mode(component, SAR_PWR_SAVING);
794 			break;
795 		default:
796 			jack_type = SND_JACK_HEADPHONE;
797 			break;
798 		}
799 		snd_soc_component_update_bits(component, RT5682S_HP_CHARGE_PUMP_2,
800 			RT5682S_OSW_L_MASK | RT5682S_OSW_R_MASK,
801 			RT5682S_OSW_L_EN | RT5682S_OSW_R_EN);
802 		usleep_range(35000, 40000);
803 	} else {
804 		rt5682s_sar_power_mode(component, SAR_PWR_OFF);
805 		rt5682s_disable_push_button_irq(component);
806 		snd_soc_component_update_bits(component, RT5682S_CBJ_CTRL_1,
807 			RT5682S_TRIG_JD_MASK, RT5682S_TRIG_JD_LOW);
808 
809 		if (!rt5682s->wclk_enabled) {
810 			snd_soc_component_update_bits(component,
811 				RT5682S_PWR_ANLG_1, RT5682S_PWR_VREF2 | RT5682S_PWR_MB, 0);
812 		}
813 
814 		snd_soc_component_update_bits(component, RT5682S_PWR_ANLG_3,
815 			RT5682S_PWR_CBJ, 0);
816 		snd_soc_component_update_bits(component, RT5682S_CBJ_CTRL_1,
817 			RT5682S_FAST_OFF_MASK, RT5682S_FAST_OFF_DIS);
818 		snd_soc_component_update_bits(component, RT5682S_CBJ_CTRL_3,
819 			RT5682S_CBJ_IN_BUF_MASK, RT5682S_CBJ_IN_BUF_DIS);
820 		jack_type = 0;
821 	}
822 
823 	dev_dbg(component->dev, "jack_type = %d\n", jack_type);
824 
825 	return jack_type;
826 }
827 
rt5682s_jack_detect_handler(struct work_struct * work)828 static void rt5682s_jack_detect_handler(struct work_struct *work)
829 {
830 	struct rt5682s_priv *rt5682s =
831 		container_of(work, struct rt5682s_priv, jack_detect_work.work);
832 	struct snd_soc_dapm_context *dapm;
833 	int val, btn_type;
834 
835 	if (!rt5682s->component ||
836 	    !snd_soc_card_is_instantiated(rt5682s->component->card)) {
837 		/* card not yet ready, try later */
838 		mod_delayed_work(system_power_efficient_wq,
839 				 &rt5682s->jack_detect_work, msecs_to_jiffies(15));
840 		return;
841 	}
842 
843 	dapm = snd_soc_component_get_dapm(rt5682s->component);
844 
845 	snd_soc_dapm_mutex_lock(dapm);
846 	mutex_lock(&rt5682s->calibrate_mutex);
847 	mutex_lock(&rt5682s->wclk_mutex);
848 
849 	val = snd_soc_component_read(rt5682s->component, RT5682S_AJD1_CTRL)
850 		& RT5682S_JDH_RS_MASK;
851 	if (!val) {
852 		/* jack in */
853 		if (rt5682s->jack_type == 0) {
854 			/* jack was out, report jack type */
855 			rt5682s->jack_type = rt5682s_headset_detect(rt5682s->component, 1);
856 			rt5682s->irq_work_delay_time = 0;
857 		} else if ((rt5682s->jack_type & SND_JACK_HEADSET) == SND_JACK_HEADSET) {
858 			/* jack is already in, report button event */
859 			rt5682s->jack_type = SND_JACK_HEADSET;
860 			btn_type = rt5682s_button_detect(rt5682s->component);
861 			/**
862 			 * rt5682s can report three kinds of button behavior,
863 			 * one click, double click and hold. However,
864 			 * currently we will report button pressed/released
865 			 * event. So all the three button behaviors are
866 			 * treated as button pressed.
867 			 */
868 			switch (btn_type) {
869 			case 0x8000:
870 			case 0x4000:
871 			case 0x2000:
872 				rt5682s->jack_type |= SND_JACK_BTN_0;
873 				break;
874 			case 0x1000:
875 			case 0x0800:
876 			case 0x0400:
877 				rt5682s->jack_type |= SND_JACK_BTN_1;
878 				break;
879 			case 0x0200:
880 			case 0x0100:
881 			case 0x0080:
882 				rt5682s->jack_type |= SND_JACK_BTN_2;
883 				break;
884 			case 0x0040:
885 			case 0x0020:
886 			case 0x0010:
887 				rt5682s->jack_type |= SND_JACK_BTN_3;
888 				break;
889 			case 0x0000: /* unpressed */
890 				break;
891 			default:
892 				dev_err(rt5682s->component->dev,
893 					"Unexpected button code 0x%04x\n", btn_type);
894 				break;
895 			}
896 		}
897 	} else {
898 		/* jack out */
899 		rt5682s->jack_type = rt5682s_headset_detect(rt5682s->component, 0);
900 		rt5682s->irq_work_delay_time = 50;
901 	}
902 
903 	mutex_unlock(&rt5682s->wclk_mutex);
904 	mutex_unlock(&rt5682s->calibrate_mutex);
905 	snd_soc_dapm_mutex_unlock(dapm);
906 
907 	snd_soc_jack_report(rt5682s->hs_jack, rt5682s->jack_type,
908 		SND_JACK_HEADSET | SND_JACK_BTN_0 | SND_JACK_BTN_1 |
909 		SND_JACK_BTN_2 | SND_JACK_BTN_3);
910 
911 	if (rt5682s->jack_type & (SND_JACK_BTN_0 | SND_JACK_BTN_1 |
912 		SND_JACK_BTN_2 | SND_JACK_BTN_3))
913 		schedule_delayed_work(&rt5682s->jd_check_work, 0);
914 	else
915 		cancel_delayed_work_sync(&rt5682s->jd_check_work);
916 }
917 
rt5682s_jd_check_handler(struct work_struct * work)918 static void rt5682s_jd_check_handler(struct work_struct *work)
919 {
920 	struct rt5682s_priv *rt5682s =
921 		container_of(work, struct rt5682s_priv, jd_check_work.work);
922 
923 	if (snd_soc_component_read(rt5682s->component, RT5682S_AJD1_CTRL) & RT5682S_JDH_RS_MASK) {
924 		/* jack out */
925 		schedule_delayed_work(&rt5682s->jack_detect_work, 0);
926 	} else {
927 		schedule_delayed_work(&rt5682s->jd_check_work, 500);
928 	}
929 }
930 
rt5682s_irq(int irq,void * data)931 static irqreturn_t rt5682s_irq(int irq, void *data)
932 {
933 	struct rt5682s_priv *rt5682s = data;
934 
935 	mod_delayed_work(system_power_efficient_wq, &rt5682s->jack_detect_work,
936 		msecs_to_jiffies(rt5682s->irq_work_delay_time));
937 
938 	return IRQ_HANDLED;
939 }
940 
rt5682s_set_jack_detect(struct snd_soc_component * component,struct snd_soc_jack * hs_jack,void * data)941 static int rt5682s_set_jack_detect(struct snd_soc_component *component,
942 		struct snd_soc_jack *hs_jack, void *data)
943 {
944 	struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component);
945 	int btndet_delay = 16;
946 
947 	rt5682s->hs_jack = hs_jack;
948 
949 	if (!hs_jack) {
950 		regmap_update_bits(rt5682s->regmap, RT5682S_IRQ_CTRL_2,
951 			RT5682S_JD1_EN_MASK, RT5682S_JD1_DIS);
952 		regmap_update_bits(rt5682s->regmap, RT5682S_RC_CLK_CTRL,
953 			RT5682S_POW_JDH, 0);
954 		cancel_delayed_work_sync(&rt5682s->jack_detect_work);
955 
956 		return 0;
957 	}
958 
959 	switch (rt5682s->pdata.jd_src) {
960 	case RT5682S_JD1:
961 		regmap_update_bits(rt5682s->regmap, RT5682S_CBJ_CTRL_5,
962 			RT5682S_JD_FAST_OFF_SRC_MASK, RT5682S_JD_FAST_OFF_SRC_JDH);
963 		regmap_update_bits(rt5682s->regmap, RT5682S_CBJ_CTRL_2,
964 			RT5682S_EXT_JD_SRC, RT5682S_EXT_JD_SRC_MANUAL);
965 		regmap_update_bits(rt5682s->regmap, RT5682S_CBJ_CTRL_1,
966 			RT5682S_EMB_JD_MASK | RT5682S_DET_TYPE |
967 			RT5682S_POL_FAST_OFF_MASK | RT5682S_MIC_CAP_MASK,
968 			RT5682S_EMB_JD_EN | RT5682S_DET_TYPE |
969 			RT5682S_POL_FAST_OFF_HIGH | RT5682S_MIC_CAP_HS);
970 		regmap_update_bits(rt5682s->regmap, RT5682S_SAR_IL_CMD_1,
971 			RT5682S_SAR_POW_MASK, RT5682S_SAR_POW_EN);
972 		regmap_update_bits(rt5682s->regmap, RT5682S_GPIO_CTRL_1,
973 			RT5682S_GP1_PIN_MASK, RT5682S_GP1_PIN_IRQ);
974 		regmap_update_bits(rt5682s->regmap, RT5682S_PWR_ANLG_3,
975 			RT5682S_PWR_BGLDO, RT5682S_PWR_BGLDO);
976 		regmap_update_bits(rt5682s->regmap, RT5682S_PWR_ANLG_2,
977 			RT5682S_PWR_JD_MASK, RT5682S_PWR_JD_ENABLE);
978 		regmap_update_bits(rt5682s->regmap, RT5682S_RC_CLK_CTRL,
979 			RT5682S_POW_IRQ | RT5682S_POW_JDH, RT5682S_POW_IRQ | RT5682S_POW_JDH);
980 		regmap_update_bits(rt5682s->regmap, RT5682S_IRQ_CTRL_2,
981 			RT5682S_JD1_EN_MASK | RT5682S_JD1_POL_MASK,
982 			RT5682S_JD1_EN | RT5682S_JD1_POL_NOR);
983 		regmap_update_bits(rt5682s->regmap, RT5682S_4BTN_IL_CMD_4,
984 			RT5682S_4BTN_IL_HOLD_WIN_MASK | RT5682S_4BTN_IL_CLICK_WIN_MASK,
985 			(btndet_delay << RT5682S_4BTN_IL_HOLD_WIN_SFT | btndet_delay));
986 		regmap_update_bits(rt5682s->regmap, RT5682S_4BTN_IL_CMD_5,
987 			RT5682S_4BTN_IL_HOLD_WIN_MASK | RT5682S_4BTN_IL_CLICK_WIN_MASK,
988 			(btndet_delay << RT5682S_4BTN_IL_HOLD_WIN_SFT | btndet_delay));
989 		regmap_update_bits(rt5682s->regmap, RT5682S_4BTN_IL_CMD_6,
990 			RT5682S_4BTN_IL_HOLD_WIN_MASK | RT5682S_4BTN_IL_CLICK_WIN_MASK,
991 			(btndet_delay << RT5682S_4BTN_IL_HOLD_WIN_SFT | btndet_delay));
992 		regmap_update_bits(rt5682s->regmap, RT5682S_4BTN_IL_CMD_7,
993 			RT5682S_4BTN_IL_HOLD_WIN_MASK | RT5682S_4BTN_IL_CLICK_WIN_MASK,
994 			(btndet_delay << RT5682S_4BTN_IL_HOLD_WIN_SFT | btndet_delay));
995 
996 		mod_delayed_work(system_power_efficient_wq,
997 			&rt5682s->jack_detect_work, msecs_to_jiffies(250));
998 		break;
999 
1000 	case RT5682S_JD_NULL:
1001 		regmap_update_bits(rt5682s->regmap, RT5682S_IRQ_CTRL_2,
1002 			RT5682S_JD1_EN_MASK, RT5682S_JD1_DIS);
1003 		regmap_update_bits(rt5682s->regmap, RT5682S_RC_CLK_CTRL,
1004 			RT5682S_POW_JDH, 0);
1005 		break;
1006 
1007 	default:
1008 		dev_warn(component->dev, "Wrong JD source\n");
1009 		break;
1010 	}
1011 
1012 	return 0;
1013 }
1014 
1015 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -9562, 75, 0);
1016 static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0);
1017 static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
1018 static const DECLARE_TLV_DB_SCALE(cbj_bst_tlv, -1200, 150, 0);
1019 
1020 static const struct snd_kcontrol_new rt5682s_snd_controls[] = {
1021 	/* DAC Digital Volume */
1022 	SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5682S_DAC1_DIG_VOL,
1023 		RT5682S_L_VOL_SFT + 1, RT5682S_R_VOL_SFT + 1, 127, 0, dac_vol_tlv),
1024 
1025 	/* CBJ Boost Volume */
1026 	SOC_SINGLE_TLV("CBJ Boost Volume", RT5682S_REC_MIXER,
1027 		RT5682S_BST_CBJ_SFT, 35, 0,  cbj_bst_tlv),
1028 
1029 	/* ADC Digital Volume Control */
1030 	SOC_DOUBLE("STO1 ADC Capture Switch", RT5682S_STO1_ADC_DIG_VOL,
1031 		RT5682S_L_MUTE_SFT, RT5682S_R_MUTE_SFT, 1, 1),
1032 	SOC_DOUBLE_TLV("STO1 ADC Capture Volume", RT5682S_STO1_ADC_DIG_VOL,
1033 		RT5682S_L_VOL_SFT + 1, RT5682S_R_VOL_SFT + 1, 63, 0, adc_vol_tlv),
1034 
1035 	/* ADC Boost Volume Control */
1036 	SOC_DOUBLE_TLV("STO1 ADC Boost Gain Volume", RT5682S_STO1_ADC_BOOST,
1037 		RT5682S_STO1_ADC_L_BST_SFT, RT5682S_STO1_ADC_R_BST_SFT, 3, 0, adc_bst_tlv),
1038 };
1039 
1040 /**
1041  * rt5682s_sel_asrc_clk_src - select ASRC clock source for a set of filters
1042  * @component: SoC audio component device.
1043  * @filter_mask: mask of filters.
1044  * @clk_src: clock source
1045  *
1046  * The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5682S can
1047  * only support standard 32fs or 64fs i2s format, ASRC should be enabled to
1048  * support special i2s clock format such as Intel's 100fs(100 * sampling rate).
1049  * ASRC function will track i2s clock and generate a corresponding system clock
1050  * for codec. This function provides an API to select the clock source for a
1051  * set of filters specified by the mask. And the component driver will turn on
1052  * ASRC for these filters if ASRC is selected as their clock source.
1053  */
rt5682s_sel_asrc_clk_src(struct snd_soc_component * component,unsigned int filter_mask,unsigned int clk_src)1054 int rt5682s_sel_asrc_clk_src(struct snd_soc_component *component,
1055 		unsigned int filter_mask, unsigned int clk_src)
1056 {
1057 	switch (clk_src) {
1058 	case RT5682S_CLK_SEL_SYS:
1059 	case RT5682S_CLK_SEL_I2S1_ASRC:
1060 	case RT5682S_CLK_SEL_I2S2_ASRC:
1061 		break;
1062 
1063 	default:
1064 		return -EINVAL;
1065 	}
1066 
1067 	if (filter_mask & RT5682S_DA_STEREO1_FILTER) {
1068 		snd_soc_component_update_bits(component, RT5682S_PLL_TRACK_2,
1069 			RT5682S_FILTER_CLK_SEL_MASK, clk_src << RT5682S_FILTER_CLK_SEL_SFT);
1070 	}
1071 
1072 	if (filter_mask & RT5682S_AD_STEREO1_FILTER) {
1073 		snd_soc_component_update_bits(component, RT5682S_PLL_TRACK_3,
1074 			RT5682S_FILTER_CLK_SEL_MASK, clk_src << RT5682S_FILTER_CLK_SEL_SFT);
1075 	}
1076 
1077 	snd_soc_component_update_bits(component, RT5682S_PLL_TRACK_11,
1078 		RT5682S_ASRCIN_AUTO_CLKOUT_MASK, RT5682S_ASRCIN_AUTO_CLKOUT_EN);
1079 
1080 	return 0;
1081 }
1082 EXPORT_SYMBOL_GPL(rt5682s_sel_asrc_clk_src);
1083 
rt5682s_div_sel(struct rt5682s_priv * rt5682s,int target,const int div[],int size)1084 static int rt5682s_div_sel(struct rt5682s_priv *rt5682s,
1085 		int target, const int div[], int size)
1086 {
1087 	int i;
1088 
1089 	if (rt5682s->sysclk < target) {
1090 		dev_err(rt5682s->component->dev,
1091 			"sysclk rate %d is too low\n", rt5682s->sysclk);
1092 		return 0;
1093 	}
1094 
1095 	for (i = 0; i < size - 1; i++) {
1096 		dev_dbg(rt5682s->component->dev, "div[%d]=%d\n", i, div[i]);
1097 		if (target * div[i] == rt5682s->sysclk)
1098 			return i;
1099 		if (target * div[i + 1] > rt5682s->sysclk) {
1100 			dev_dbg(rt5682s->component->dev,
1101 				"can't find div for sysclk %d\n", rt5682s->sysclk);
1102 			return i;
1103 		}
1104 	}
1105 
1106 	if (target * div[i] < rt5682s->sysclk)
1107 		dev_err(rt5682s->component->dev,
1108 			"sysclk rate %d is too high\n", rt5682s->sysclk);
1109 
1110 	return size - 1;
1111 }
1112 
get_clk_info(int sclk,int rate)1113 static int get_clk_info(int sclk, int rate)
1114 {
1115 	int i;
1116 	static const int pd[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32, 48};
1117 
1118 	if (sclk <= 0 || rate <= 0)
1119 		return -EINVAL;
1120 
1121 	rate = rate << 8;
1122 	for (i = 0; i < ARRAY_SIZE(pd); i++)
1123 		if (sclk == rate * pd[i])
1124 			return i;
1125 
1126 	return -EINVAL;
1127 }
1128 
1129 /**
1130  * set_dmic_clk - Set parameter of dmic.
1131  *
1132  * @w: DAPM widget.
1133  * @kcontrol: The kcontrol of this widget.
1134  * @event: Event id.
1135  *
1136  * Choose dmic clock between 1MHz and 3MHz.
1137  * It is better for clock to approximate 3MHz.
1138  */
set_dmic_clk(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)1139 static int set_dmic_clk(struct snd_soc_dapm_widget *w,
1140 		struct snd_kcontrol *kcontrol, int event)
1141 {
1142 	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1143 	struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component);
1144 	int idx, dmic_clk_rate = 3072000;
1145 	static const int div[] = {2, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, 128};
1146 
1147 	if (rt5682s->pdata.dmic_clk_rate)
1148 		dmic_clk_rate = rt5682s->pdata.dmic_clk_rate;
1149 
1150 	idx = rt5682s_div_sel(rt5682s, dmic_clk_rate, div, ARRAY_SIZE(div));
1151 
1152 	snd_soc_component_update_bits(component, RT5682S_DMIC_CTRL_1,
1153 		RT5682S_DMIC_CLK_MASK, idx << RT5682S_DMIC_CLK_SFT);
1154 
1155 	return 0;
1156 }
1157 
1158 
rt5682s_set_pllb_power(struct rt5682s_priv * rt5682s,int on)1159 static int rt5682s_set_pllb_power(struct rt5682s_priv *rt5682s, int on)
1160 {
1161 	struct snd_soc_component *component = rt5682s->component;
1162 
1163 	if (on) {
1164 		snd_soc_component_update_bits(component, RT5682S_PWR_ANLG_3,
1165 			RT5682S_PWR_LDO_PLLB | RT5682S_PWR_BIAS_PLLB | RT5682S_PWR_PLLB,
1166 			RT5682S_PWR_LDO_PLLB | RT5682S_PWR_BIAS_PLLB | RT5682S_PWR_PLLB);
1167 		snd_soc_component_update_bits(component, RT5682S_PWR_ANLG_3,
1168 			RT5682S_RSTB_PLLB, RT5682S_RSTB_PLLB);
1169 	} else {
1170 		snd_soc_component_update_bits(component, RT5682S_PWR_ANLG_3,
1171 			RT5682S_PWR_LDO_PLLB | RT5682S_PWR_BIAS_PLLB |
1172 			RT5682S_RSTB_PLLB | RT5682S_PWR_PLLB, 0);
1173 	}
1174 
1175 	return 0;
1176 }
1177 
set_pllb_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)1178 static int set_pllb_event(struct snd_soc_dapm_widget *w,
1179 		struct snd_kcontrol *kcontrol, int event)
1180 {
1181 	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1182 	struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component);
1183 	int on = 0;
1184 
1185 	if (rt5682s->wclk_enabled)
1186 		return 0;
1187 
1188 	if (SND_SOC_DAPM_EVENT_ON(event))
1189 		on = 1;
1190 
1191 	rt5682s_set_pllb_power(rt5682s, on);
1192 
1193 	return 0;
1194 }
1195 
rt5682s_set_filter_clk(struct rt5682s_priv * rt5682s,int reg,int ref)1196 static void rt5682s_set_filter_clk(struct rt5682s_priv *rt5682s, int reg, int ref)
1197 {
1198 	struct snd_soc_component *component = rt5682s->component;
1199 	int idx;
1200 	static const int div_f[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32, 48};
1201 	static const int div_o[] = {1, 2, 4, 6, 8, 12, 16, 24, 32, 48};
1202 
1203 	idx = rt5682s_div_sel(rt5682s, ref, div_f, ARRAY_SIZE(div_f));
1204 
1205 	snd_soc_component_update_bits(component, reg,
1206 		RT5682S_FILTER_CLK_DIV_MASK, idx << RT5682S_FILTER_CLK_DIV_SFT);
1207 
1208 	/* select over sample rate */
1209 	for (idx = 0; idx < ARRAY_SIZE(div_o); idx++) {
1210 		if (rt5682s->sysclk <= 12288000 * div_o[idx])
1211 			break;
1212 	}
1213 
1214 	snd_soc_component_update_bits(component, RT5682S_ADDA_CLK_1,
1215 		RT5682S_ADC_OSR_MASK | RT5682S_DAC_OSR_MASK,
1216 		(idx << RT5682S_ADC_OSR_SFT) | (idx << RT5682S_DAC_OSR_SFT));
1217 }
1218 
set_filter_clk(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)1219 static int set_filter_clk(struct snd_soc_dapm_widget *w,
1220 		struct snd_kcontrol *kcontrol, int event)
1221 {
1222 	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1223 	struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component);
1224 	int ref, reg, val;
1225 
1226 	val = snd_soc_component_read(component, RT5682S_GPIO_CTRL_1)
1227 			& RT5682S_GP4_PIN_MASK;
1228 
1229 	if (w->shift == RT5682S_PWR_ADC_S1F_BIT && val == RT5682S_GP4_PIN_ADCDAT2)
1230 		ref = 256 * rt5682s->lrck[RT5682S_AIF2];
1231 	else
1232 		ref = 256 * rt5682s->lrck[RT5682S_AIF1];
1233 
1234 	if (w->shift == RT5682S_PWR_ADC_S1F_BIT)
1235 		reg = RT5682S_PLL_TRACK_3;
1236 	else
1237 		reg = RT5682S_PLL_TRACK_2;
1238 
1239 	rt5682s_set_filter_clk(rt5682s, reg, ref);
1240 
1241 	return 0;
1242 }
1243 
set_dmic_power(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)1244 static int set_dmic_power(struct snd_soc_dapm_widget *w,
1245 		struct snd_kcontrol *kcontrol, int event)
1246 {
1247 	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1248 	struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component);
1249 	unsigned int delay = 50, val;
1250 
1251 	if (rt5682s->pdata.dmic_delay)
1252 		delay = rt5682s->pdata.dmic_delay;
1253 
1254 	switch (event) {
1255 	case SND_SOC_DAPM_POST_PMU:
1256 		val = (snd_soc_component_read(component, RT5682S_GLB_CLK)
1257 			& RT5682S_SCLK_SRC_MASK) >> RT5682S_SCLK_SRC_SFT;
1258 		if (val == RT5682S_CLK_SRC_PLL1 || val == RT5682S_CLK_SRC_PLL2)
1259 			snd_soc_component_update_bits(component, RT5682S_PWR_ANLG_1,
1260 				RT5682S_PWR_VREF2 | RT5682S_PWR_MB,
1261 				RT5682S_PWR_VREF2 | RT5682S_PWR_MB);
1262 
1263 		/*Add delay to avoid pop noise*/
1264 		msleep(delay);
1265 		break;
1266 
1267 	case SND_SOC_DAPM_POST_PMD:
1268 		if (!rt5682s->jack_type && !rt5682s->wclk_enabled) {
1269 			snd_soc_component_update_bits(component, RT5682S_PWR_ANLG_1,
1270 				RT5682S_PWR_VREF2 | RT5682S_PWR_MB, 0);
1271 		}
1272 		break;
1273 	}
1274 
1275 	return 0;
1276 }
1277 
rt5682s_set_i2s(struct rt5682s_priv * rt5682s,int id,int on)1278 static void rt5682s_set_i2s(struct rt5682s_priv *rt5682s, int id, int on)
1279 {
1280 	struct snd_soc_component *component = rt5682s->component;
1281 	int pre_div;
1282 	unsigned int p_reg, p_mask, p_sft;
1283 	unsigned int c_reg, c_mask, c_sft;
1284 
1285 	if (id == RT5682S_AIF1) {
1286 		c_reg = RT5682S_ADDA_CLK_1;
1287 		c_mask = RT5682S_I2S_M_D_MASK;
1288 		c_sft = RT5682S_I2S_M_D_SFT;
1289 		p_reg = RT5682S_PWR_DIG_1;
1290 		p_mask = RT5682S_PWR_I2S1;
1291 		p_sft = RT5682S_PWR_I2S1_BIT;
1292 	} else {
1293 		c_reg = RT5682S_I2S2_M_CLK_CTRL_1;
1294 		c_mask = RT5682S_I2S2_M_D_MASK;
1295 		c_sft = RT5682S_I2S2_M_D_SFT;
1296 		p_reg = RT5682S_PWR_DIG_1;
1297 		p_mask = RT5682S_PWR_I2S2;
1298 		p_sft = RT5682S_PWR_I2S2_BIT;
1299 	}
1300 
1301 	if (on && rt5682s->master[id]) {
1302 		pre_div = get_clk_info(rt5682s->sysclk, rt5682s->lrck[id]);
1303 		if (pre_div < 0) {
1304 			dev_err(component->dev, "get pre_div failed\n");
1305 			return;
1306 		}
1307 
1308 		dev_dbg(component->dev, "lrck is %dHz and pre_div is %d for iis %d master\n",
1309 			rt5682s->lrck[id], pre_div, id);
1310 		snd_soc_component_update_bits(component, c_reg, c_mask, pre_div << c_sft);
1311 	}
1312 
1313 	snd_soc_component_update_bits(component, p_reg, p_mask, on << p_sft);
1314 }
1315 
set_i2s_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)1316 static int set_i2s_event(struct snd_soc_dapm_widget *w,
1317 		struct snd_kcontrol *kcontrol, int event)
1318 {
1319 	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1320 	struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component);
1321 	int on = 0;
1322 
1323 	if (SND_SOC_DAPM_EVENT_ON(event))
1324 		on = 1;
1325 
1326 	if (!strcmp(w->name, "I2S1") && !rt5682s->wclk_enabled)
1327 		rt5682s_set_i2s(rt5682s, RT5682S_AIF1, on);
1328 	else if (!strcmp(w->name, "I2S2"))
1329 		rt5682s_set_i2s(rt5682s, RT5682S_AIF2, on);
1330 
1331 	return 0;
1332 }
1333 
is_sys_clk_from_plla(struct snd_soc_dapm_widget * w,struct snd_soc_dapm_widget * sink)1334 static int is_sys_clk_from_plla(struct snd_soc_dapm_widget *w,
1335 		struct snd_soc_dapm_widget *sink)
1336 {
1337 	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1338 	struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component);
1339 
1340 	if ((rt5682s->sysclk_src == RT5682S_CLK_SRC_PLL1) ||
1341 	    (rt5682s->sysclk_src == RT5682S_CLK_SRC_PLL2 && rt5682s->pll_comb == USE_PLLAB))
1342 		return 1;
1343 
1344 	return 0;
1345 }
1346 
is_sys_clk_from_pllb(struct snd_soc_dapm_widget * w,struct snd_soc_dapm_widget * sink)1347 static int is_sys_clk_from_pllb(struct snd_soc_dapm_widget *w,
1348 		struct snd_soc_dapm_widget *sink)
1349 {
1350 	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1351 	struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component);
1352 
1353 	if (rt5682s->sysclk_src == RT5682S_CLK_SRC_PLL2)
1354 		return 1;
1355 
1356 	return 0;
1357 }
1358 
is_using_asrc(struct snd_soc_dapm_widget * w,struct snd_soc_dapm_widget * sink)1359 static int is_using_asrc(struct snd_soc_dapm_widget *w,
1360 		struct snd_soc_dapm_widget *sink)
1361 {
1362 	unsigned int reg, sft, val;
1363 	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1364 
1365 	switch (w->shift) {
1366 	case RT5682S_ADC_STO1_ASRC_SFT:
1367 		reg = RT5682S_PLL_TRACK_3;
1368 		sft = RT5682S_FILTER_CLK_SEL_SFT;
1369 		break;
1370 	case RT5682S_DAC_STO1_ASRC_SFT:
1371 		reg = RT5682S_PLL_TRACK_2;
1372 		sft = RT5682S_FILTER_CLK_SEL_SFT;
1373 		break;
1374 	default:
1375 		return 0;
1376 	}
1377 
1378 	val = (snd_soc_component_read(component, reg) >> sft) & 0xf;
1379 	switch (val) {
1380 	case RT5682S_CLK_SEL_I2S1_ASRC:
1381 	case RT5682S_CLK_SEL_I2S2_ASRC:
1382 		return 1;
1383 	default:
1384 		return 0;
1385 	}
1386 }
1387 
rt5682s_hp_amp_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)1388 static int rt5682s_hp_amp_event(struct snd_soc_dapm_widget *w,
1389 		struct snd_kcontrol *kcontrol, int event)
1390 {
1391 	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1392 
1393 	switch (event) {
1394 	case SND_SOC_DAPM_POST_PMU:
1395 		snd_soc_component_update_bits(component, RT5682S_DEPOP_1,
1396 			RT5682S_OUT_HP_L_EN | RT5682S_OUT_HP_R_EN,
1397 			RT5682S_OUT_HP_L_EN | RT5682S_OUT_HP_R_EN);
1398 		usleep_range(15000, 20000);
1399 		snd_soc_component_update_bits(component, RT5682S_DEPOP_1,
1400 			RT5682S_LDO_PUMP_EN | RT5682S_PUMP_EN |
1401 			RT5682S_CAPLESS_L_EN | RT5682S_CAPLESS_R_EN,
1402 			RT5682S_LDO_PUMP_EN | RT5682S_PUMP_EN |
1403 			RT5682S_CAPLESS_L_EN | RT5682S_CAPLESS_R_EN);
1404 		snd_soc_component_write(component, RT5682S_BIAS_CUR_CTRL_11, 0x6666);
1405 		snd_soc_component_write(component, RT5682S_BIAS_CUR_CTRL_12, 0xa82a);
1406 
1407 		snd_soc_component_update_bits(component, RT5682S_HP_CTRL_2,
1408 			RT5682S_HPO_L_PATH_MASK | RT5682S_HPO_R_PATH_MASK |
1409 			RT5682S_HPO_SEL_IP_EN_SW, RT5682S_HPO_L_PATH_EN |
1410 			RT5682S_HPO_R_PATH_EN | RT5682S_HPO_IP_EN_GATING);
1411 		usleep_range(5000, 10000);
1412 		snd_soc_component_update_bits(component, RT5682S_HP_AMP_DET_CTL_1,
1413 			RT5682S_CP_SW_SIZE_MASK, RT5682S_CP_SW_SIZE_L | RT5682S_CP_SW_SIZE_S);
1414 		break;
1415 
1416 	case SND_SOC_DAPM_POST_PMD:
1417 		snd_soc_component_update_bits(component, RT5682S_HP_CTRL_2,
1418 			RT5682S_HPO_L_PATH_MASK | RT5682S_HPO_R_PATH_MASK |
1419 			RT5682S_HPO_SEL_IP_EN_SW, 0);
1420 		snd_soc_component_update_bits(component, RT5682S_HP_AMP_DET_CTL_1,
1421 			RT5682S_CP_SW_SIZE_MASK, RT5682S_CP_SW_SIZE_M);
1422 		snd_soc_component_update_bits(component, RT5682S_DEPOP_1,
1423 			RT5682S_LDO_PUMP_EN | RT5682S_PUMP_EN |
1424 			RT5682S_CAPLESS_L_EN | RT5682S_CAPLESS_R_EN, 0);
1425 		snd_soc_component_update_bits(component, RT5682S_DEPOP_1,
1426 			RT5682S_OUT_HP_L_EN | RT5682S_OUT_HP_R_EN, 0);
1427 		break;
1428 	}
1429 
1430 	return 0;
1431 }
1432 
rt5682s_stereo1_adc_mixl_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)1433 static int rt5682s_stereo1_adc_mixl_event(struct snd_soc_dapm_widget *w,
1434 		struct snd_kcontrol *kcontrol, int event)
1435 {
1436 	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1437 	struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component);
1438 	unsigned int delay = 0;
1439 
1440 	if (rt5682s->pdata.amic_delay)
1441 		delay = rt5682s->pdata.amic_delay;
1442 
1443 	switch (event) {
1444 	case SND_SOC_DAPM_POST_PMU:
1445 		msleep(delay);
1446 		snd_soc_component_update_bits(component, RT5682S_STO1_ADC_DIG_VOL,
1447 			RT5682S_L_MUTE, 0);
1448 		break;
1449 	case SND_SOC_DAPM_PRE_PMD:
1450 		snd_soc_component_update_bits(component, RT5682S_STO1_ADC_DIG_VOL,
1451 			RT5682S_L_MUTE, RT5682S_L_MUTE);
1452 		break;
1453 	}
1454 
1455 	return 0;
1456 }
1457 
sar_power_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)1458 static int sar_power_event(struct snd_soc_dapm_widget *w,
1459 		struct snd_kcontrol *kcontrol, int event)
1460 {
1461 	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1462 	struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component);
1463 
1464 	if ((rt5682s->jack_type & SND_JACK_HEADSET) != SND_JACK_HEADSET)
1465 		return 0;
1466 
1467 	switch (event) {
1468 	case SND_SOC_DAPM_PRE_PMU:
1469 		rt5682s_sar_power_mode(component, SAR_PWR_NORMAL);
1470 		break;
1471 	case SND_SOC_DAPM_POST_PMD:
1472 		rt5682s_sar_power_mode(component, SAR_PWR_SAVING);
1473 		break;
1474 	}
1475 
1476 	return 0;
1477 }
1478 
1479 /* Interface data select */
1480 static const char * const rt5682s_data_select[] = {
1481 	"L/R", "R/L", "L/L", "R/R"
1482 };
1483 
1484 static SOC_ENUM_SINGLE_DECL(rt5682s_if2_adc_enum, RT5682S_DIG_INF2_DATA,
1485 	RT5682S_IF2_ADC_SEL_SFT, rt5682s_data_select);
1486 
1487 static SOC_ENUM_SINGLE_DECL(rt5682s_if1_01_adc_enum, RT5682S_TDM_ADDA_CTRL_1,
1488 	RT5682S_IF1_ADC1_SEL_SFT, rt5682s_data_select);
1489 
1490 static SOC_ENUM_SINGLE_DECL(rt5682s_if1_23_adc_enum, RT5682S_TDM_ADDA_CTRL_1,
1491 	RT5682S_IF1_ADC2_SEL_SFT, rt5682s_data_select);
1492 
1493 static SOC_ENUM_SINGLE_DECL(rt5682s_if1_45_adc_enum, RT5682S_TDM_ADDA_CTRL_1,
1494 	RT5682S_IF1_ADC3_SEL_SFT, rt5682s_data_select);
1495 
1496 static SOC_ENUM_SINGLE_DECL(rt5682s_if1_67_adc_enum, RT5682S_TDM_ADDA_CTRL_1,
1497 	RT5682S_IF1_ADC4_SEL_SFT, rt5682s_data_select);
1498 
1499 static const struct snd_kcontrol_new rt5682s_if2_adc_swap_mux =
1500 	SOC_DAPM_ENUM("IF2 ADC Swap Mux", rt5682s_if2_adc_enum);
1501 
1502 static const struct snd_kcontrol_new rt5682s_if1_01_adc_swap_mux =
1503 	SOC_DAPM_ENUM("IF1 01 ADC Swap Mux", rt5682s_if1_01_adc_enum);
1504 
1505 static const struct snd_kcontrol_new rt5682s_if1_23_adc_swap_mux =
1506 	SOC_DAPM_ENUM("IF1 23 ADC Swap Mux", rt5682s_if1_23_adc_enum);
1507 
1508 static const struct snd_kcontrol_new rt5682s_if1_45_adc_swap_mux =
1509 	SOC_DAPM_ENUM("IF1 45 ADC Swap Mux", rt5682s_if1_45_adc_enum);
1510 
1511 static const struct snd_kcontrol_new rt5682s_if1_67_adc_swap_mux =
1512 	SOC_DAPM_ENUM("IF1 67 ADC Swap Mux", rt5682s_if1_67_adc_enum);
1513 
1514 /* Digital Mixer */
1515 static const struct snd_kcontrol_new rt5682s_sto1_adc_l_mix[] = {
1516 	SOC_DAPM_SINGLE("ADC1 Switch", RT5682S_STO1_ADC_MIXER,
1517 			RT5682S_M_STO1_ADC_L1_SFT, 1, 1),
1518 	SOC_DAPM_SINGLE("ADC2 Switch", RT5682S_STO1_ADC_MIXER,
1519 			RT5682S_M_STO1_ADC_L2_SFT, 1, 1),
1520 };
1521 
1522 static const struct snd_kcontrol_new rt5682s_sto1_adc_r_mix[] = {
1523 	SOC_DAPM_SINGLE("ADC1 Switch", RT5682S_STO1_ADC_MIXER,
1524 			RT5682S_M_STO1_ADC_R1_SFT, 1, 1),
1525 	SOC_DAPM_SINGLE("ADC2 Switch", RT5682S_STO1_ADC_MIXER,
1526 			RT5682S_M_STO1_ADC_R2_SFT, 1, 1),
1527 };
1528 
1529 static const struct snd_kcontrol_new rt5682s_dac_l_mix[] = {
1530 	SOC_DAPM_SINGLE("Stereo ADC Switch", RT5682S_AD_DA_MIXER,
1531 			RT5682S_M_ADCMIX_L_SFT, 1, 1),
1532 	SOC_DAPM_SINGLE("DAC1 Switch", RT5682S_AD_DA_MIXER,
1533 			RT5682S_M_DAC1_L_SFT, 1, 1),
1534 };
1535 
1536 static const struct snd_kcontrol_new rt5682s_dac_r_mix[] = {
1537 	SOC_DAPM_SINGLE("Stereo ADC Switch", RT5682S_AD_DA_MIXER,
1538 			RT5682S_M_ADCMIX_R_SFT, 1, 1),
1539 	SOC_DAPM_SINGLE("DAC1 Switch", RT5682S_AD_DA_MIXER,
1540 			RT5682S_M_DAC1_R_SFT, 1, 1),
1541 };
1542 
1543 static const struct snd_kcontrol_new rt5682s_sto1_dac_l_mix[] = {
1544 	SOC_DAPM_SINGLE("DAC L1 Switch", RT5682S_STO1_DAC_MIXER,
1545 			RT5682S_M_DAC_L1_STO_L_SFT, 1, 1),
1546 	SOC_DAPM_SINGLE("DAC R1 Switch", RT5682S_STO1_DAC_MIXER,
1547 			RT5682S_M_DAC_R1_STO_L_SFT, 1, 1),
1548 };
1549 
1550 static const struct snd_kcontrol_new rt5682s_sto1_dac_r_mix[] = {
1551 	SOC_DAPM_SINGLE("DAC L1 Switch", RT5682S_STO1_DAC_MIXER,
1552 			RT5682S_M_DAC_L1_STO_R_SFT, 1, 1),
1553 	SOC_DAPM_SINGLE("DAC R1 Switch", RT5682S_STO1_DAC_MIXER,
1554 			RT5682S_M_DAC_R1_STO_R_SFT, 1, 1),
1555 };
1556 
1557 /* Analog Input Mixer */
1558 static const struct snd_kcontrol_new rt5682s_rec1_l_mix[] = {
1559 	SOC_DAPM_SINGLE("CBJ Switch", RT5682S_REC_MIXER,
1560 			RT5682S_M_CBJ_RM1_L_SFT, 1, 1),
1561 };
1562 
1563 static const struct snd_kcontrol_new rt5682s_rec1_r_mix[] = {
1564 	SOC_DAPM_SINGLE("CBJ Switch", RT5682S_REC_MIXER,
1565 			RT5682S_M_CBJ_RM1_R_SFT, 1, 1),
1566 };
1567 
1568 /* STO1 ADC1 Source */
1569 /* MX-26 [13] [5] */
1570 static const char * const rt5682s_sto1_adc1_src[] = {
1571 	"DAC MIX", "ADC"
1572 };
1573 
1574 static SOC_ENUM_SINGLE_DECL(rt5682s_sto1_adc1l_enum, RT5682S_STO1_ADC_MIXER,
1575 	RT5682S_STO1_ADC1L_SRC_SFT, rt5682s_sto1_adc1_src);
1576 
1577 static const struct snd_kcontrol_new rt5682s_sto1_adc1l_mux =
1578 	SOC_DAPM_ENUM("Stereo1 ADC1L Source", rt5682s_sto1_adc1l_enum);
1579 
1580 static SOC_ENUM_SINGLE_DECL(rt5682s_sto1_adc1r_enum, RT5682S_STO1_ADC_MIXER,
1581 	RT5682S_STO1_ADC1R_SRC_SFT, rt5682s_sto1_adc1_src);
1582 
1583 static const struct snd_kcontrol_new rt5682s_sto1_adc1r_mux =
1584 	SOC_DAPM_ENUM("Stereo1 ADC1L Source", rt5682s_sto1_adc1r_enum);
1585 
1586 /* STO1 ADC Source */
1587 /* MX-26 [11:10] [3:2] */
1588 static const char * const rt5682s_sto1_adc_src[] = {
1589 	"ADC1 L", "ADC1 R"
1590 };
1591 
1592 static SOC_ENUM_SINGLE_DECL(rt5682s_sto1_adcl_enum, RT5682S_STO1_ADC_MIXER,
1593 	RT5682S_STO1_ADCL_SRC_SFT, rt5682s_sto1_adc_src);
1594 
1595 static const struct snd_kcontrol_new rt5682s_sto1_adcl_mux =
1596 	SOC_DAPM_ENUM("Stereo1 ADCL Source", rt5682s_sto1_adcl_enum);
1597 
1598 static SOC_ENUM_SINGLE_DECL(rt5682s_sto1_adcr_enum, RT5682S_STO1_ADC_MIXER,
1599 	RT5682S_STO1_ADCR_SRC_SFT, rt5682s_sto1_adc_src);
1600 
1601 static const struct snd_kcontrol_new rt5682s_sto1_adcr_mux =
1602 	SOC_DAPM_ENUM("Stereo1 ADCR Source", rt5682s_sto1_adcr_enum);
1603 
1604 /* STO1 ADC2 Source */
1605 /* MX-26 [12] [4] */
1606 static const char * const rt5682s_sto1_adc2_src[] = {
1607 	"DAC MIX", "DMIC"
1608 };
1609 
1610 static SOC_ENUM_SINGLE_DECL(rt5682s_sto1_adc2l_enum, RT5682S_STO1_ADC_MIXER,
1611 	RT5682S_STO1_ADC2L_SRC_SFT, rt5682s_sto1_adc2_src);
1612 
1613 static const struct snd_kcontrol_new rt5682s_sto1_adc2l_mux =
1614 	SOC_DAPM_ENUM("Stereo1 ADC2L Source", rt5682s_sto1_adc2l_enum);
1615 
1616 static SOC_ENUM_SINGLE_DECL(rt5682s_sto1_adc2r_enum, RT5682S_STO1_ADC_MIXER,
1617 	RT5682S_STO1_ADC2R_SRC_SFT, rt5682s_sto1_adc2_src);
1618 
1619 static const struct snd_kcontrol_new rt5682s_sto1_adc2r_mux =
1620 	SOC_DAPM_ENUM("Stereo1 ADC2R Source", rt5682s_sto1_adc2r_enum);
1621 
1622 /* MX-79 [6:4] I2S1 ADC data location */
1623 static const unsigned int rt5682s_if1_adc_slot_values[] = {
1624 	0, 2, 4, 6,
1625 };
1626 
1627 static const char * const rt5682s_if1_adc_slot_src[] = {
1628 	"Slot 0", "Slot 2", "Slot 4", "Slot 6"
1629 };
1630 
1631 static SOC_VALUE_ENUM_SINGLE_DECL(rt5682s_if1_adc_slot_enum,
1632 	RT5682S_TDM_CTRL, RT5682S_TDM_ADC_LCA_SFT, RT5682S_TDM_ADC_LCA_MASK,
1633 	rt5682s_if1_adc_slot_src, rt5682s_if1_adc_slot_values);
1634 
1635 static const struct snd_kcontrol_new rt5682s_if1_adc_slot_mux =
1636 	SOC_DAPM_ENUM("IF1 ADC Slot location", rt5682s_if1_adc_slot_enum);
1637 
1638 /* Analog DAC L1 Source, Analog DAC R1 Source*/
1639 /* MX-2B [4], MX-2B [0]*/
1640 static const char * const rt5682s_alg_dac1_src[] = {
1641 	"Stereo1 DAC Mixer", "DAC1"
1642 };
1643 
1644 static SOC_ENUM_SINGLE_DECL(rt5682s_alg_dac_l1_enum, RT5682S_A_DAC1_MUX,
1645 	RT5682S_A_DACL1_SFT, rt5682s_alg_dac1_src);
1646 
1647 static const struct snd_kcontrol_new rt5682s_alg_dac_l1_mux =
1648 	SOC_DAPM_ENUM("Analog DAC L1 Source", rt5682s_alg_dac_l1_enum);
1649 
1650 static SOC_ENUM_SINGLE_DECL(rt5682s_alg_dac_r1_enum, RT5682S_A_DAC1_MUX,
1651 	RT5682S_A_DACR1_SFT, rt5682s_alg_dac1_src);
1652 
1653 static const struct snd_kcontrol_new rt5682s_alg_dac_r1_mux =
1654 	SOC_DAPM_ENUM("Analog DAC R1 Source", rt5682s_alg_dac_r1_enum);
1655 
1656 static const unsigned int rt5682s_adcdat_pin_values[] = {
1657 	1, 3,
1658 };
1659 
1660 static const char * const rt5682s_adcdat_pin_select[] = {
1661 	"ADCDAT1", "ADCDAT2",
1662 };
1663 
1664 static SOC_VALUE_ENUM_SINGLE_DECL(rt5682s_adcdat_pin_enum,
1665 	RT5682S_GPIO_CTRL_1, RT5682S_GP4_PIN_SFT, RT5682S_GP4_PIN_MASK,
1666 	rt5682s_adcdat_pin_select, rt5682s_adcdat_pin_values);
1667 
1668 static const struct snd_kcontrol_new rt5682s_adcdat_pin_ctrl =
1669 	SOC_DAPM_ENUM("ADCDAT", rt5682s_adcdat_pin_enum);
1670 
1671 static const struct snd_soc_dapm_widget rt5682s_dapm_widgets[] = {
1672 	SND_SOC_DAPM_SUPPLY("LDO MB1", RT5682S_PWR_ANLG_3,
1673 		RT5682S_PWR_LDO_MB1_BIT, 0, NULL, 0),
1674 	SND_SOC_DAPM_SUPPLY("LDO MB2", RT5682S_PWR_ANLG_3,
1675 		RT5682S_PWR_LDO_MB2_BIT, 0, NULL, 0),
1676 	SND_SOC_DAPM_SUPPLY("LDO", RT5682S_PWR_ANLG_3,
1677 		RT5682S_PWR_LDO_BIT, 0, NULL, 0),
1678 
1679 	/* PLL Powers */
1680 	SND_SOC_DAPM_SUPPLY_S("PLLA_LDO", 0, RT5682S_PWR_ANLG_3,
1681 		RT5682S_PWR_LDO_PLLA_BIT, 0, NULL, 0),
1682 	SND_SOC_DAPM_SUPPLY_S("PLLA_BIAS", 0, RT5682S_PWR_ANLG_3,
1683 		RT5682S_PWR_BIAS_PLLA_BIT, 0, NULL, 0),
1684 	SND_SOC_DAPM_SUPPLY_S("PLLA", 0, RT5682S_PWR_ANLG_3,
1685 		RT5682S_PWR_PLLA_BIT, 0, NULL, 0),
1686 	SND_SOC_DAPM_SUPPLY_S("PLLA_RST", 1, RT5682S_PWR_ANLG_3,
1687 		RT5682S_RSTB_PLLA_BIT, 0, NULL, 0),
1688 	SND_SOC_DAPM_SUPPLY("PLLB", SND_SOC_NOPM, 0, 0,
1689 		set_pllb_event, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1690 
1691 	/* ASRC */
1692 	SND_SOC_DAPM_SUPPLY_S("DAC STO1 ASRC", 1, RT5682S_PLL_TRACK_1,
1693 		RT5682S_DAC_STO1_ASRC_SFT, 0, NULL, 0),
1694 	SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5682S_PLL_TRACK_1,
1695 		RT5682S_ADC_STO1_ASRC_SFT, 0, NULL, 0),
1696 	SND_SOC_DAPM_SUPPLY_S("AD ASRC", 1, RT5682S_PLL_TRACK_1,
1697 		RT5682S_AD_ASRC_SFT, 0, NULL, 0),
1698 	SND_SOC_DAPM_SUPPLY_S("DA ASRC", 1, RT5682S_PLL_TRACK_1,
1699 		RT5682S_DA_ASRC_SFT, 0, NULL, 0),
1700 	SND_SOC_DAPM_SUPPLY_S("DMIC ASRC", 1, RT5682S_PLL_TRACK_1,
1701 		RT5682S_DMIC_ASRC_SFT, 0, NULL, 0),
1702 
1703 	/* Input Side */
1704 	SND_SOC_DAPM_SUPPLY("MICBIAS1", RT5682S_PWR_ANLG_2,
1705 		RT5682S_PWR_MB1_BIT, 0, NULL, 0),
1706 	SND_SOC_DAPM_SUPPLY("MICBIAS2", RT5682S_PWR_ANLG_2,
1707 		RT5682S_PWR_MB2_BIT, 0, NULL, 0),
1708 
1709 	/* Input Lines */
1710 	SND_SOC_DAPM_INPUT("DMIC L1"),
1711 	SND_SOC_DAPM_INPUT("DMIC R1"),
1712 
1713 	SND_SOC_DAPM_INPUT("IN1P"),
1714 
1715 	SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
1716 		set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
1717 	SND_SOC_DAPM_SUPPLY("DMIC1 Power", RT5682S_DMIC_CTRL_1, RT5682S_DMIC_1_EN_SFT, 0,
1718 		set_dmic_power, SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1719 
1720 	/* Boost */
1721 	SND_SOC_DAPM_PGA("BST1 CBJ", SND_SOC_NOPM, 0, 0, NULL, 0),
1722 
1723 	/* REC Mixer */
1724 	SND_SOC_DAPM_MIXER("RECMIX1L", SND_SOC_NOPM, 0, 0, rt5682s_rec1_l_mix,
1725 		ARRAY_SIZE(rt5682s_rec1_l_mix)),
1726 	SND_SOC_DAPM_MIXER("RECMIX1R", SND_SOC_NOPM, 0, 0, rt5682s_rec1_r_mix,
1727 		ARRAY_SIZE(rt5682s_rec1_r_mix)),
1728 	SND_SOC_DAPM_SUPPLY("RECMIX1L Power", RT5682S_CAL_REC,
1729 		RT5682S_PWR_RM1_L_BIT, 0, NULL, 0),
1730 	SND_SOC_DAPM_SUPPLY("RECMIX1R Power", RT5682S_CAL_REC,
1731 		RT5682S_PWR_RM1_R_BIT, 0, NULL, 0),
1732 
1733 	/* ADCs */
1734 	SND_SOC_DAPM_ADC("ADC1 L", NULL, SND_SOC_NOPM, 0, 0),
1735 	SND_SOC_DAPM_ADC("ADC1 R", NULL, SND_SOC_NOPM, 0, 0),
1736 
1737 	SND_SOC_DAPM_SUPPLY("ADC1 L Power", RT5682S_PWR_DIG_1,
1738 		RT5682S_PWR_ADC_L1_BIT, 0, NULL, 0),
1739 	SND_SOC_DAPM_SUPPLY("ADC1 R Power", RT5682S_PWR_DIG_1,
1740 		RT5682S_PWR_ADC_R1_BIT, 0, NULL, 0),
1741 	SND_SOC_DAPM_SUPPLY("ADC1 clock", RT5682S_CHOP_ADC,
1742 		RT5682S_CKGEN_ADC1_SFT, 0, NULL, 0),
1743 
1744 	/* ADC Mux */
1745 	SND_SOC_DAPM_MUX("Stereo1 ADC L1 Mux", SND_SOC_NOPM, 0, 0,
1746 		&rt5682s_sto1_adc1l_mux),
1747 	SND_SOC_DAPM_MUX("Stereo1 ADC R1 Mux", SND_SOC_NOPM, 0, 0,
1748 		&rt5682s_sto1_adc1r_mux),
1749 	SND_SOC_DAPM_MUX("Stereo1 ADC L2 Mux", SND_SOC_NOPM, 0, 0,
1750 		&rt5682s_sto1_adc2l_mux),
1751 	SND_SOC_DAPM_MUX("Stereo1 ADC R2 Mux", SND_SOC_NOPM, 0, 0,
1752 		&rt5682s_sto1_adc2r_mux),
1753 	SND_SOC_DAPM_MUX("Stereo1 ADC L Mux", SND_SOC_NOPM, 0, 0,
1754 		&rt5682s_sto1_adcl_mux),
1755 	SND_SOC_DAPM_MUX("Stereo1 ADC R Mux", SND_SOC_NOPM, 0, 0,
1756 		&rt5682s_sto1_adcr_mux),
1757 	SND_SOC_DAPM_MUX("IF1_ADC Mux", SND_SOC_NOPM, 0, 0,
1758 		&rt5682s_if1_adc_slot_mux),
1759 
1760 	/* ADC Mixer */
1761 	SND_SOC_DAPM_SUPPLY("ADC Stereo1 Filter", RT5682S_PWR_DIG_2,
1762 		RT5682S_PWR_ADC_S1F_BIT, 0, set_filter_clk, SND_SOC_DAPM_PRE_PMU),
1763 	SND_SOC_DAPM_MIXER_E("Stereo1 ADC MIXL", SND_SOC_NOPM, 0, 0,
1764 		rt5682s_sto1_adc_l_mix, ARRAY_SIZE(rt5682s_sto1_adc_l_mix),
1765 		rt5682s_stereo1_adc_mixl_event,
1766 		SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
1767 	SND_SOC_DAPM_MIXER("Stereo1 ADC MIXR", RT5682S_STO1_ADC_DIG_VOL,
1768 		RT5682S_R_MUTE_SFT, 1, rt5682s_sto1_adc_r_mix,
1769 		ARRAY_SIZE(rt5682s_sto1_adc_r_mix)),
1770 
1771 	/* ADC PGA */
1772 	SND_SOC_DAPM_PGA("Stereo1 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
1773 
1774 	/* Digital Interface */
1775 	SND_SOC_DAPM_SUPPLY("I2S1", SND_SOC_NOPM, 0, 0,
1776 		set_i2s_event, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1777 	SND_SOC_DAPM_SUPPLY("I2S2", SND_SOC_NOPM, 0, 0,
1778 		set_i2s_event, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1779 	SND_SOC_DAPM_PGA("IF1 DAC1 L", SND_SOC_NOPM, 0, 0, NULL, 0),
1780 	SND_SOC_DAPM_PGA("IF1 DAC1 R", SND_SOC_NOPM, 0, 0, NULL, 0),
1781 
1782 	/* Digital Interface Select */
1783 	SND_SOC_DAPM_MUX("IF1 01 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1784 		&rt5682s_if1_01_adc_swap_mux),
1785 	SND_SOC_DAPM_MUX("IF1 23 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1786 		&rt5682s_if1_23_adc_swap_mux),
1787 	SND_SOC_DAPM_MUX("IF1 45 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1788 		&rt5682s_if1_45_adc_swap_mux),
1789 	SND_SOC_DAPM_MUX("IF1 67 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1790 		&rt5682s_if1_67_adc_swap_mux),
1791 	SND_SOC_DAPM_MUX("IF2 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1792 		&rt5682s_if2_adc_swap_mux),
1793 
1794 	SND_SOC_DAPM_MUX("ADCDAT Mux", SND_SOC_NOPM, 0, 0, &rt5682s_adcdat_pin_ctrl),
1795 
1796 	/* Audio Interface */
1797 	SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, RT5682S_I2S1_SDP,
1798 		RT5682S_SEL_ADCDAT_SFT, 1),
1799 	SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, RT5682S_I2S2_SDP,
1800 		RT5682S_I2S2_PIN_CFG_SFT, 1),
1801 	SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
1802 
1803 	/* Output Side */
1804 	/* DAC mixer before sound effect  */
1805 	SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0,
1806 		rt5682s_dac_l_mix, ARRAY_SIZE(rt5682s_dac_l_mix)),
1807 	SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0,
1808 		rt5682s_dac_r_mix, ARRAY_SIZE(rt5682s_dac_r_mix)),
1809 
1810 	/* DAC channel Mux */
1811 	SND_SOC_DAPM_MUX("DAC L1 Source", SND_SOC_NOPM, 0, 0, &rt5682s_alg_dac_l1_mux),
1812 	SND_SOC_DAPM_MUX("DAC R1 Source", SND_SOC_NOPM, 0, 0, &rt5682s_alg_dac_r1_mux),
1813 
1814 	/* DAC Mixer */
1815 	SND_SOC_DAPM_SUPPLY("DAC Stereo1 Filter", RT5682S_PWR_DIG_2,
1816 		RT5682S_PWR_DAC_S1F_BIT, 0, set_filter_clk, SND_SOC_DAPM_PRE_PMU),
1817 	SND_SOC_DAPM_MIXER("Stereo1 DAC MIXL", SND_SOC_NOPM, 0, 0,
1818 		rt5682s_sto1_dac_l_mix, ARRAY_SIZE(rt5682s_sto1_dac_l_mix)),
1819 	SND_SOC_DAPM_MIXER("Stereo1 DAC MIXR", SND_SOC_NOPM, 0, 0,
1820 		rt5682s_sto1_dac_r_mix, ARRAY_SIZE(rt5682s_sto1_dac_r_mix)),
1821 
1822 	/* DACs */
1823 	SND_SOC_DAPM_DAC("DAC L1", NULL, RT5682S_PWR_DIG_1, RT5682S_PWR_DAC_L1_BIT, 0),
1824 	SND_SOC_DAPM_DAC("DAC R1", NULL, RT5682S_PWR_DIG_1, RT5682S_PWR_DAC_R1_BIT, 0),
1825 
1826 	/* HPO */
1827 	SND_SOC_DAPM_PGA_S("HP Amp", 1, SND_SOC_NOPM, 0, 0, rt5682s_hp_amp_event,
1828 		SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_POST_PMU),
1829 
1830 	/* CLK DET */
1831 	SND_SOC_DAPM_SUPPLY("CLKDET SYS", RT5682S_CLK_DET,
1832 		RT5682S_SYS_CLK_DET_SFT, 0, NULL, 0),
1833 	SND_SOC_DAPM_SUPPLY("CLKDET PLL1", RT5682S_CLK_DET,
1834 		RT5682S_PLL1_CLK_DET_SFT, 0, NULL, 0),
1835 	SND_SOC_DAPM_SUPPLY("MCLK0 DET PWR", RT5682S_PWR_ANLG_2,
1836 		RT5682S_PWR_MCLK0_WD_BIT, 0, NULL, 0),
1837 
1838 	/* SAR */
1839 	SND_SOC_DAPM_SUPPLY("SAR", SND_SOC_NOPM, 0, 0, sar_power_event,
1840 		SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1841 
1842 	/* Output Lines */
1843 	SND_SOC_DAPM_OUTPUT("HPOL"),
1844 	SND_SOC_DAPM_OUTPUT("HPOR"),
1845 };
1846 
1847 static const struct snd_soc_dapm_route rt5682s_dapm_routes[] = {
1848 	/*PLL*/
1849 	{"ADC Stereo1 Filter", NULL, "PLLA", is_sys_clk_from_plla},
1850 	{"ADC Stereo1 Filter", NULL, "PLLB", is_sys_clk_from_pllb},
1851 	{"DAC Stereo1 Filter", NULL, "PLLA", is_sys_clk_from_plla},
1852 	{"DAC Stereo1 Filter", NULL, "PLLB", is_sys_clk_from_pllb},
1853 	{"PLLA", NULL, "PLLA_LDO"},
1854 	{"PLLA", NULL, "PLLA_BIAS"},
1855 	{"PLLA", NULL, "PLLA_RST"},
1856 
1857 	/*ASRC*/
1858 	{"ADC Stereo1 Filter", NULL, "ADC STO1 ASRC", is_using_asrc},
1859 	{"DAC Stereo1 Filter", NULL, "DAC STO1 ASRC", is_using_asrc},
1860 	{"ADC STO1 ASRC", NULL, "AD ASRC"},
1861 	{"ADC STO1 ASRC", NULL, "DA ASRC"},
1862 	{"DAC STO1 ASRC", NULL, "AD ASRC"},
1863 	{"DAC STO1 ASRC", NULL, "DA ASRC"},
1864 
1865 	{"CLKDET SYS", NULL, "MCLK0 DET PWR"},
1866 
1867 	{"BST1 CBJ", NULL, "IN1P"},
1868 	{"BST1 CBJ", NULL, "SAR"},
1869 
1870 	{"RECMIX1L", "CBJ Switch", "BST1 CBJ"},
1871 	{"RECMIX1L", NULL, "RECMIX1L Power"},
1872 	{"RECMIX1R", "CBJ Switch", "BST1 CBJ"},
1873 	{"RECMIX1R", NULL, "RECMIX1R Power"},
1874 
1875 	{"ADC1 L", NULL, "RECMIX1L"},
1876 	{"ADC1 L", NULL, "ADC1 L Power"},
1877 	{"ADC1 L", NULL, "ADC1 clock"},
1878 	{"ADC1 R", NULL, "RECMIX1R"},
1879 	{"ADC1 R", NULL, "ADC1 R Power"},
1880 	{"ADC1 R", NULL, "ADC1 clock"},
1881 
1882 	{"DMIC L1", NULL, "DMIC CLK"},
1883 	{"DMIC L1", NULL, "DMIC1 Power"},
1884 	{"DMIC R1", NULL, "DMIC CLK"},
1885 	{"DMIC R1", NULL, "DMIC1 Power"},
1886 	{"DMIC CLK", NULL, "DMIC ASRC"},
1887 
1888 	{"Stereo1 ADC L Mux", "ADC1 L", "ADC1 L"},
1889 	{"Stereo1 ADC L Mux", "ADC1 R", "ADC1 R"},
1890 	{"Stereo1 ADC R Mux", "ADC1 L", "ADC1 L"},
1891 	{"Stereo1 ADC R Mux", "ADC1 R", "ADC1 R"},
1892 
1893 	{"Stereo1 ADC L1 Mux", "ADC", "Stereo1 ADC L Mux"},
1894 	{"Stereo1 ADC L1 Mux", "DAC MIX", "Stereo1 DAC MIXL"},
1895 	{"Stereo1 ADC L2 Mux", "DMIC", "DMIC L1"},
1896 	{"Stereo1 ADC L2 Mux", "DAC MIX", "Stereo1 DAC MIXL"},
1897 
1898 	{"Stereo1 ADC R1 Mux", "ADC", "Stereo1 ADC R Mux"},
1899 	{"Stereo1 ADC R1 Mux", "DAC MIX", "Stereo1 DAC MIXR"},
1900 	{"Stereo1 ADC R2 Mux", "DMIC", "DMIC R1"},
1901 	{"Stereo1 ADC R2 Mux", "DAC MIX", "Stereo1 DAC MIXR"},
1902 
1903 	{"Stereo1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC L1 Mux"},
1904 	{"Stereo1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC L2 Mux"},
1905 	{"Stereo1 ADC MIXL", NULL, "ADC Stereo1 Filter"},
1906 
1907 	{"Stereo1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC R1 Mux"},
1908 	{"Stereo1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC R2 Mux"},
1909 	{"Stereo1 ADC MIXR", NULL, "ADC Stereo1 Filter"},
1910 
1911 	{"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXL"},
1912 	{"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXR"},
1913 
1914 	{"IF1 01 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1915 	{"IF1 01 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1916 	{"IF1 01 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1917 	{"IF1 01 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1918 	{"IF1 23 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1919 	{"IF1 23 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1920 	{"IF1 23 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1921 	{"IF1 23 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1922 	{"IF1 45 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1923 	{"IF1 45 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1924 	{"IF1 45 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1925 	{"IF1 45 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1926 	{"IF1 67 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1927 	{"IF1 67 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1928 	{"IF1 67 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1929 	{"IF1 67 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1930 
1931 	{"IF1_ADC Mux", "Slot 0", "IF1 01 ADC Swap Mux"},
1932 	{"IF1_ADC Mux", "Slot 2", "IF1 23 ADC Swap Mux"},
1933 	{"IF1_ADC Mux", "Slot 4", "IF1 45 ADC Swap Mux"},
1934 	{"IF1_ADC Mux", "Slot 6", "IF1 67 ADC Swap Mux"},
1935 	{"ADCDAT Mux", "ADCDAT1", "IF1_ADC Mux"},
1936 	{"AIF1TX", NULL, "I2S1"},
1937 	{"AIF1TX", NULL, "ADCDAT Mux"},
1938 	{"IF2 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1939 	{"IF2 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1940 	{"IF2 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1941 	{"IF2 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1942 	{"ADCDAT Mux", "ADCDAT2", "IF2 ADC Swap Mux"},
1943 	{"AIF2TX", NULL, "ADCDAT Mux"},
1944 
1945 	{"IF1 DAC1 L", NULL, "AIF1RX"},
1946 	{"IF1 DAC1 L", NULL, "I2S1"},
1947 	{"IF1 DAC1 L", NULL, "DAC Stereo1 Filter"},
1948 	{"IF1 DAC1 R", NULL, "AIF1RX"},
1949 	{"IF1 DAC1 R", NULL, "I2S1"},
1950 	{"IF1 DAC1 R", NULL, "DAC Stereo1 Filter"},
1951 
1952 	{"DAC1 MIXL", "Stereo ADC Switch", "Stereo1 ADC MIXL"},
1953 	{"DAC1 MIXL", "DAC1 Switch", "IF1 DAC1 L"},
1954 	{"DAC1 MIXR", "Stereo ADC Switch", "Stereo1 ADC MIXR"},
1955 	{"DAC1 MIXR", "DAC1 Switch", "IF1 DAC1 R"},
1956 
1957 	{"Stereo1 DAC MIXL", "DAC L1 Switch", "DAC1 MIXL"},
1958 	{"Stereo1 DAC MIXL", "DAC R1 Switch", "DAC1 MIXR"},
1959 
1960 	{"Stereo1 DAC MIXR", "DAC R1 Switch", "DAC1 MIXR"},
1961 	{"Stereo1 DAC MIXR", "DAC L1 Switch", "DAC1 MIXL"},
1962 
1963 	{"DAC L1 Source", "DAC1", "DAC1 MIXL"},
1964 	{"DAC L1 Source", "Stereo1 DAC Mixer", "Stereo1 DAC MIXL"},
1965 	{"DAC R1 Source", "DAC1", "DAC1 MIXR"},
1966 	{"DAC R1 Source", "Stereo1 DAC Mixer", "Stereo1 DAC MIXR"},
1967 
1968 	{"DAC L1", NULL, "DAC L1 Source"},
1969 	{"DAC R1", NULL, "DAC R1 Source"},
1970 
1971 	{"HP Amp", NULL, "DAC L1"},
1972 	{"HP Amp", NULL, "DAC R1"},
1973 	{"HP Amp", NULL, "CLKDET SYS"},
1974 	{"HP Amp", NULL, "SAR"},
1975 
1976 	{"HPOL", NULL, "HP Amp"},
1977 	{"HPOR", NULL, "HP Amp"},
1978 };
1979 
rt5682s_set_tdm_slot(struct snd_soc_dai * dai,unsigned int tx_mask,unsigned int rx_mask,int slots,int slot_width)1980 static int rt5682s_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
1981 		unsigned int rx_mask, int slots, int slot_width)
1982 {
1983 	struct snd_soc_component *component = dai->component;
1984 	unsigned int cl, val = 0, tx_slotnum;
1985 
1986 	if (tx_mask || rx_mask)
1987 		snd_soc_component_update_bits(component,
1988 			RT5682S_TDM_ADDA_CTRL_2, RT5682S_TDM_EN, RT5682S_TDM_EN);
1989 	else
1990 		snd_soc_component_update_bits(component,
1991 			RT5682S_TDM_ADDA_CTRL_2, RT5682S_TDM_EN, 0);
1992 
1993 	/* Tx slot configuration */
1994 	tx_slotnum = hweight_long(tx_mask);
1995 	if (tx_slotnum) {
1996 		if (tx_slotnum > slots) {
1997 			dev_err(component->dev, "Invalid or oversized Tx slots.\n");
1998 			return -EINVAL;
1999 		}
2000 		val |= (tx_slotnum - 1) << RT5682S_TDM_ADC_DL_SFT;
2001 	}
2002 
2003 	switch (slots) {
2004 	case 4:
2005 		val |= RT5682S_TDM_TX_CH_4;
2006 		val |= RT5682S_TDM_RX_CH_4;
2007 		break;
2008 	case 6:
2009 		val |= RT5682S_TDM_TX_CH_6;
2010 		val |= RT5682S_TDM_RX_CH_6;
2011 		break;
2012 	case 8:
2013 		val |= RT5682S_TDM_TX_CH_8;
2014 		val |= RT5682S_TDM_RX_CH_8;
2015 		break;
2016 	case 2:
2017 		break;
2018 	default:
2019 		return -EINVAL;
2020 	}
2021 
2022 	snd_soc_component_update_bits(component, RT5682S_TDM_CTRL,
2023 		RT5682S_TDM_TX_CH_MASK | RT5682S_TDM_RX_CH_MASK |
2024 		RT5682S_TDM_ADC_DL_MASK, val);
2025 
2026 	switch (slot_width) {
2027 	case 8:
2028 		if (tx_mask || rx_mask)
2029 			return -EINVAL;
2030 		cl = RT5682S_I2S1_TX_CHL_8 | RT5682S_I2S1_RX_CHL_8;
2031 		break;
2032 	case 16:
2033 		val = RT5682S_TDM_CL_16;
2034 		cl = RT5682S_I2S1_TX_CHL_16 | RT5682S_I2S1_RX_CHL_16;
2035 		break;
2036 	case 20:
2037 		val = RT5682S_TDM_CL_20;
2038 		cl = RT5682S_I2S1_TX_CHL_20 | RT5682S_I2S1_RX_CHL_20;
2039 		break;
2040 	case 24:
2041 		val = RT5682S_TDM_CL_24;
2042 		cl = RT5682S_I2S1_TX_CHL_24 | RT5682S_I2S1_RX_CHL_24;
2043 		break;
2044 	case 32:
2045 		val = RT5682S_TDM_CL_32;
2046 		cl = RT5682S_I2S1_TX_CHL_32 | RT5682S_I2S1_RX_CHL_32;
2047 		break;
2048 	default:
2049 		return -EINVAL;
2050 	}
2051 
2052 	snd_soc_component_update_bits(component, RT5682S_TDM_TCON_CTRL_1,
2053 		RT5682S_TDM_CL_MASK, val);
2054 	snd_soc_component_update_bits(component, RT5682S_I2S1_SDP,
2055 		RT5682S_I2S1_TX_CHL_MASK | RT5682S_I2S1_RX_CHL_MASK, cl);
2056 
2057 	return 0;
2058 }
2059 
rt5682s_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)2060 static int rt5682s_hw_params(struct snd_pcm_substream *substream,
2061 		struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
2062 {
2063 	struct snd_soc_component *component = dai->component;
2064 	struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component);
2065 	unsigned int len_1 = 0, len_2 = 0;
2066 	int frame_size;
2067 
2068 	rt5682s->lrck[dai->id] = params_rate(params);
2069 
2070 	frame_size = snd_soc_params_to_frame_size(params);
2071 	if (frame_size < 0) {
2072 		dev_err(component->dev, "Unsupported frame size: %d\n", frame_size);
2073 		return -EINVAL;
2074 	}
2075 
2076 	switch (params_width(params)) {
2077 	case 16:
2078 		break;
2079 	case 20:
2080 		len_1 |= RT5682S_I2S1_DL_20;
2081 		len_2 |= RT5682S_I2S2_DL_20;
2082 		break;
2083 	case 24:
2084 		len_1 |= RT5682S_I2S1_DL_24;
2085 		len_2 |= RT5682S_I2S2_DL_24;
2086 		break;
2087 	case 32:
2088 		len_1 |= RT5682S_I2S1_DL_32;
2089 		len_2 |= RT5682S_I2S2_DL_24;
2090 		break;
2091 	case 8:
2092 		len_1 |= RT5682S_I2S2_DL_8;
2093 		len_2 |= RT5682S_I2S2_DL_8;
2094 		break;
2095 	default:
2096 		return -EINVAL;
2097 	}
2098 
2099 	switch (dai->id) {
2100 	case RT5682S_AIF1:
2101 		snd_soc_component_update_bits(component, RT5682S_I2S1_SDP,
2102 			RT5682S_I2S1_DL_MASK, len_1);
2103 		if (params_channels(params) == 1) /* mono mode */
2104 			snd_soc_component_update_bits(component, RT5682S_I2S1_SDP,
2105 				RT5682S_I2S1_MONO_MASK, RT5682S_I2S1_MONO_EN);
2106 		else
2107 			snd_soc_component_update_bits(component, RT5682S_I2S1_SDP,
2108 				RT5682S_I2S1_MONO_MASK, RT5682S_I2S1_MONO_DIS);
2109 		break;
2110 	case RT5682S_AIF2:
2111 		snd_soc_component_update_bits(component, RT5682S_I2S2_SDP,
2112 			RT5682S_I2S2_DL_MASK, len_2);
2113 		if (params_channels(params) == 1) /* mono mode */
2114 			snd_soc_component_update_bits(component, RT5682S_I2S2_SDP,
2115 				RT5682S_I2S2_MONO_MASK, RT5682S_I2S2_MONO_EN);
2116 		else
2117 			snd_soc_component_update_bits(component, RT5682S_I2S2_SDP,
2118 				RT5682S_I2S2_MONO_MASK, RT5682S_I2S2_MONO_DIS);
2119 		break;
2120 	default:
2121 		dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
2122 		return -EINVAL;
2123 	}
2124 
2125 	return 0;
2126 }
2127 
rt5682s_set_dai_fmt(struct snd_soc_dai * dai,unsigned int fmt)2128 static int rt5682s_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2129 {
2130 	struct snd_soc_component *component = dai->component;
2131 	struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component);
2132 	unsigned int reg_val = 0, tdm_ctrl = 0;
2133 
2134 	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2135 	case SND_SOC_DAIFMT_CBM_CFM:
2136 		rt5682s->master[dai->id] = 1;
2137 		break;
2138 	case SND_SOC_DAIFMT_CBS_CFS:
2139 		rt5682s->master[dai->id] = 0;
2140 		break;
2141 	default:
2142 		return -EINVAL;
2143 	}
2144 
2145 	switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2146 	case SND_SOC_DAIFMT_NB_NF:
2147 		break;
2148 	case SND_SOC_DAIFMT_IB_NF:
2149 		reg_val |= RT5682S_I2S_BP_INV;
2150 		tdm_ctrl |= RT5682S_TDM_S_BP_INV;
2151 		break;
2152 	case SND_SOC_DAIFMT_NB_IF:
2153 		if (dai->id == RT5682S_AIF1)
2154 			tdm_ctrl |= RT5682S_TDM_S_LP_INV | RT5682S_TDM_M_BP_INV;
2155 		else
2156 			return -EINVAL;
2157 		break;
2158 	case SND_SOC_DAIFMT_IB_IF:
2159 		if (dai->id == RT5682S_AIF1)
2160 			tdm_ctrl |= RT5682S_TDM_S_BP_INV | RT5682S_TDM_S_LP_INV |
2161 				RT5682S_TDM_M_BP_INV | RT5682S_TDM_M_LP_INV;
2162 		else
2163 			return -EINVAL;
2164 		break;
2165 	default:
2166 		return -EINVAL;
2167 	}
2168 
2169 	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2170 	case SND_SOC_DAIFMT_I2S:
2171 		break;
2172 	case SND_SOC_DAIFMT_LEFT_J:
2173 		reg_val |= RT5682S_I2S_DF_LEFT;
2174 		tdm_ctrl |= RT5682S_TDM_DF_LEFT;
2175 		break;
2176 	case SND_SOC_DAIFMT_DSP_A:
2177 		reg_val |= RT5682S_I2S_DF_PCM_A;
2178 		tdm_ctrl |= RT5682S_TDM_DF_PCM_A;
2179 		break;
2180 	case SND_SOC_DAIFMT_DSP_B:
2181 		reg_val |= RT5682S_I2S_DF_PCM_B;
2182 		tdm_ctrl |= RT5682S_TDM_DF_PCM_B;
2183 		break;
2184 	default:
2185 		return -EINVAL;
2186 	}
2187 
2188 	switch (dai->id) {
2189 	case RT5682S_AIF1:
2190 		snd_soc_component_update_bits(component, RT5682S_I2S1_SDP,
2191 			RT5682S_I2S_DF_MASK, reg_val);
2192 		snd_soc_component_update_bits(component, RT5682S_TDM_TCON_CTRL_1,
2193 			RT5682S_TDM_MS_MASK | RT5682S_TDM_S_BP_MASK |
2194 			RT5682S_TDM_DF_MASK | RT5682S_TDM_M_BP_MASK |
2195 			RT5682S_TDM_M_LP_MASK | RT5682S_TDM_S_LP_MASK,
2196 			tdm_ctrl | rt5682s->master[dai->id]);
2197 		break;
2198 	case RT5682S_AIF2:
2199 		if (rt5682s->master[dai->id] == 0)
2200 			reg_val |= RT5682S_I2S2_MS_S;
2201 		snd_soc_component_update_bits(component, RT5682S_I2S2_SDP,
2202 			RT5682S_I2S2_MS_MASK | RT5682S_I2S_BP_MASK |
2203 			RT5682S_I2S_DF_MASK, reg_val);
2204 		break;
2205 	default:
2206 		dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
2207 		return -EINVAL;
2208 	}
2209 	return 0;
2210 }
2211 
rt5682s_set_component_sysclk(struct snd_soc_component * component,int clk_id,int source,unsigned int freq,int dir)2212 static int rt5682s_set_component_sysclk(struct snd_soc_component *component,
2213 		int clk_id, int source, unsigned int freq, int dir)
2214 {
2215 	struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component);
2216 	unsigned int src = 0;
2217 
2218 	if (freq == rt5682s->sysclk && clk_id == rt5682s->sysclk_src)
2219 		return 0;
2220 
2221 	switch (clk_id) {
2222 	case RT5682S_SCLK_S_MCLK:
2223 		src = RT5682S_CLK_SRC_MCLK;
2224 		break;
2225 	case RT5682S_SCLK_S_PLL1:
2226 		src = RT5682S_CLK_SRC_PLL1;
2227 		break;
2228 	case RT5682S_SCLK_S_PLL2:
2229 		src = RT5682S_CLK_SRC_PLL2;
2230 		break;
2231 	case RT5682S_SCLK_S_RCCLK:
2232 		src = RT5682S_CLK_SRC_RCCLK;
2233 		break;
2234 	default:
2235 		dev_err(component->dev, "Invalid clock id (%d)\n", clk_id);
2236 		return -EINVAL;
2237 	}
2238 
2239 	snd_soc_component_update_bits(component, RT5682S_GLB_CLK,
2240 		RT5682S_SCLK_SRC_MASK, src << RT5682S_SCLK_SRC_SFT);
2241 	snd_soc_component_update_bits(component, RT5682S_ADDA_CLK_1,
2242 		RT5682S_I2S_M_CLK_SRC_MASK, src << RT5682S_I2S_M_CLK_SRC_SFT);
2243 	snd_soc_component_update_bits(component, RT5682S_I2S2_M_CLK_CTRL_1,
2244 		RT5682S_I2S2_M_CLK_SRC_MASK, src << RT5682S_I2S2_M_CLK_SRC_SFT);
2245 
2246 	rt5682s->sysclk = freq;
2247 	rt5682s->sysclk_src = clk_id;
2248 
2249 	dev_dbg(component->dev, "Sysclk is %dHz and clock id is %d\n",
2250 		freq, clk_id);
2251 
2252 	return 0;
2253 }
2254 
2255 static const struct pll_calc_map plla_table[] = {
2256 	{2048000, 24576000, 0, 46, 2, true, false, false, false},
2257 	{256000, 24576000, 0, 382, 2, true, false, false, false},
2258 	{512000, 24576000, 0, 190, 2, true, false, false, false},
2259 	{4096000, 24576000, 0, 22, 2, true, false, false, false},
2260 	{1024000, 24576000, 0, 94, 2, true, false, false, false},
2261 	{11289600, 22579200, 1, 22, 2, false, false, false, false},
2262 	{1411200, 22579200, 0, 62, 2, true, false, false, false},
2263 	{2822400, 22579200, 0, 30, 2, true, false, false, false},
2264 	{12288000, 24576000, 1, 22, 2, false, false, false, false},
2265 	{1536000, 24576000, 0, 62, 2, true, false, false, false},
2266 	{3072000, 24576000, 0, 30, 2, true, false, false, false},
2267 	{24576000, 49152000, 4, 22, 0, false, false, false, false},
2268 	{3072000, 49152000, 0, 30, 0, true, false, false, false},
2269 	{6144000, 49152000, 0, 30, 0, false, false, false, false},
2270 	{49152000, 98304000, 10, 22, 0, false, true, false, false},
2271 	{6144000, 98304000, 0, 30, 0, false, true, false, false},
2272 	{12288000, 98304000, 1, 22, 0, false, true, false, false},
2273 	{48000000, 3840000, 10, 22, 23, false, false, false, false},
2274 	{24000000, 3840000, 4, 22, 23, false, false, false, false},
2275 	{19200000, 3840000, 3, 23, 23, false, false, false, false},
2276 	{38400000, 3840000, 8, 23, 23, false, false, false, false},
2277 };
2278 
2279 static const struct pll_calc_map pllb_table[] = {
2280 	{48000000, 24576000, 8, 6, 3, false, false, false, false},
2281 	{48000000, 22579200, 23, 12, 3, false, false, false, true},
2282 	{24000000, 24576000, 3, 6, 3, false, false, false, false},
2283 	{24000000, 22579200, 23, 26, 3, false, false, false, true},
2284 	{19200000, 24576000, 2, 6, 3, false, false, false, false},
2285 	{19200000, 22579200, 3, 5, 3, false, false, false, true},
2286 	{38400000, 24576000, 6, 6, 3, false, false, false, false},
2287 	{38400000, 22579200, 8, 5, 3, false, false, false, true},
2288 	{3840000, 49152000, 0, 6, 0, true, false, false, false},
2289 };
2290 
find_pll_inter_combination(unsigned int f_in,unsigned int f_out,struct pll_calc_map * a,struct pll_calc_map * b)2291 static int find_pll_inter_combination(unsigned int f_in, unsigned int f_out,
2292 		struct pll_calc_map *a, struct pll_calc_map *b)
2293 {
2294 	int i, j;
2295 
2296 	/* Look at PLLA table */
2297 	for (i = 0; i < ARRAY_SIZE(plla_table); i++) {
2298 		if (plla_table[i].freq_in == f_in && plla_table[i].freq_out == f_out) {
2299 			memcpy(a, plla_table + i, sizeof(*a));
2300 			return USE_PLLA;
2301 		}
2302 	}
2303 
2304 	/* Look at PLLB table */
2305 	for (i = 0; i < ARRAY_SIZE(pllb_table); i++) {
2306 		if (pllb_table[i].freq_in == f_in && pllb_table[i].freq_out == f_out) {
2307 			memcpy(b, pllb_table + i, sizeof(*b));
2308 			return USE_PLLB;
2309 		}
2310 	}
2311 
2312 	/* Find a combination of PLLA & PLLB */
2313 	for (i = ARRAY_SIZE(plla_table) - 1; i >= 0; i--) {
2314 		if (plla_table[i].freq_in == f_in && plla_table[i].freq_out == 3840000) {
2315 			for (j = ARRAY_SIZE(pllb_table) - 1; j >= 0; j--) {
2316 				if (pllb_table[j].freq_in == 3840000 &&
2317 					pllb_table[j].freq_out == f_out) {
2318 					memcpy(a, plla_table + i, sizeof(*a));
2319 					memcpy(b, pllb_table + j, sizeof(*b));
2320 					return USE_PLLAB;
2321 				}
2322 			}
2323 		}
2324 	}
2325 
2326 	return -EINVAL;
2327 }
2328 
rt5682s_set_component_pll(struct snd_soc_component * component,int pll_id,int source,unsigned int freq_in,unsigned int freq_out)2329 static int rt5682s_set_component_pll(struct snd_soc_component *component,
2330 		int pll_id, int source, unsigned int freq_in,
2331 		unsigned int freq_out)
2332 {
2333 	struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component);
2334 	struct pll_calc_map a_map, b_map;
2335 
2336 	if (source == rt5682s->pll_src[pll_id] && freq_in == rt5682s->pll_in[pll_id] &&
2337 	    freq_out == rt5682s->pll_out[pll_id])
2338 		return 0;
2339 
2340 	if (!freq_in || !freq_out) {
2341 		dev_dbg(component->dev, "PLL disabled\n");
2342 		rt5682s->pll_in[pll_id] = 0;
2343 		rt5682s->pll_out[pll_id] = 0;
2344 		snd_soc_component_update_bits(component, RT5682S_GLB_CLK,
2345 			RT5682S_SCLK_SRC_MASK, RT5682S_CLK_SRC_MCLK << RT5682S_SCLK_SRC_SFT);
2346 		return 0;
2347 	}
2348 
2349 	switch (source) {
2350 	case RT5682S_PLL_S_MCLK:
2351 		snd_soc_component_update_bits(component, RT5682S_GLB_CLK,
2352 			RT5682S_PLL_SRC_MASK, RT5682S_PLL_SRC_MCLK);
2353 		break;
2354 	case RT5682S_PLL_S_BCLK1:
2355 		snd_soc_component_update_bits(component, RT5682S_GLB_CLK,
2356 			RT5682S_PLL_SRC_MASK, RT5682S_PLL_SRC_BCLK1);
2357 		break;
2358 	default:
2359 		dev_err(component->dev, "Unknown PLL Source %d\n", source);
2360 		return -EINVAL;
2361 	}
2362 
2363 	rt5682s->pll_comb = find_pll_inter_combination(freq_in, freq_out,
2364 							&a_map, &b_map);
2365 
2366 	if ((pll_id == RT5682S_PLL1 && rt5682s->pll_comb == USE_PLLA) ||
2367 	    (pll_id == RT5682S_PLL2 && (rt5682s->pll_comb == USE_PLLB ||
2368 					rt5682s->pll_comb == USE_PLLAB))) {
2369 		dev_dbg(component->dev,
2370 			"Supported freq conversion for PLL%d:(%d->%d): %d\n",
2371 			pll_id + 1, freq_in, freq_out, rt5682s->pll_comb);
2372 	} else {
2373 		dev_err(component->dev,
2374 			"Unsupported freq conversion for PLL%d:(%d->%d): %d\n",
2375 			pll_id + 1, freq_in, freq_out, rt5682s->pll_comb);
2376 		return -EINVAL;
2377 	}
2378 
2379 	if (rt5682s->pll_comb == USE_PLLA || rt5682s->pll_comb == USE_PLLAB) {
2380 		dev_dbg(component->dev,
2381 			"PLLA: fin=%d fout=%d m_bp=%d k_bp=%d m=%d n=%d k=%d\n",
2382 			a_map.freq_in, a_map.freq_out, a_map.m_bp, a_map.k_bp,
2383 			(a_map.m_bp ? 0 : a_map.m), a_map.n, (a_map.k_bp ? 0 : a_map.k));
2384 		snd_soc_component_update_bits(component, RT5682S_PLL_CTRL_1,
2385 			RT5682S_PLLA_N_MASK, a_map.n);
2386 		snd_soc_component_update_bits(component, RT5682S_PLL_CTRL_2,
2387 			RT5682S_PLLA_M_MASK | RT5682S_PLLA_K_MASK,
2388 			a_map.m << RT5682S_PLLA_M_SFT | a_map.k);
2389 		snd_soc_component_update_bits(component, RT5682S_PLL_CTRL_6,
2390 			RT5682S_PLLA_M_BP_MASK | RT5682S_PLLA_K_BP_MASK,
2391 			a_map.m_bp << RT5682S_PLLA_M_BP_SFT |
2392 			a_map.k_bp << RT5682S_PLLA_K_BP_SFT);
2393 	}
2394 
2395 	if (rt5682s->pll_comb == USE_PLLB || rt5682s->pll_comb == USE_PLLAB) {
2396 		dev_dbg(component->dev,
2397 			"PLLB: fin=%d fout=%d m_bp=%d k_bp=%d m=%d n=%d k=%d byp_ps=%d sel_ps=%d\n",
2398 			b_map.freq_in, b_map.freq_out, b_map.m_bp, b_map.k_bp,
2399 			(b_map.m_bp ? 0 : b_map.m), b_map.n, (b_map.k_bp ? 0 : b_map.k),
2400 			b_map.byp_ps, b_map.sel_ps);
2401 		snd_soc_component_update_bits(component, RT5682S_PLL_CTRL_3,
2402 			RT5682S_PLLB_N_MASK, b_map.n);
2403 		snd_soc_component_update_bits(component, RT5682S_PLL_CTRL_4,
2404 			RT5682S_PLLB_M_MASK | RT5682S_PLLB_K_MASK,
2405 			b_map.m << RT5682S_PLLB_M_SFT | b_map.k);
2406 		snd_soc_component_update_bits(component, RT5682S_PLL_CTRL_6,
2407 			RT5682S_PLLB_SEL_PS_MASK | RT5682S_PLLB_BYP_PS_MASK |
2408 			RT5682S_PLLB_M_BP_MASK | RT5682S_PLLB_K_BP_MASK,
2409 			b_map.sel_ps << RT5682S_PLLB_SEL_PS_SFT |
2410 			b_map.byp_ps << RT5682S_PLLB_BYP_PS_SFT |
2411 			b_map.m_bp << RT5682S_PLLB_M_BP_SFT |
2412 			b_map.k_bp << RT5682S_PLLB_K_BP_SFT);
2413 	}
2414 
2415 	if (rt5682s->pll_comb == USE_PLLB)
2416 		snd_soc_component_update_bits(component, RT5682S_PLL_CTRL_7,
2417 			RT5682S_PLLB_SRC_MASK, RT5682S_PLLB_SRC_DFIN);
2418 
2419 	rt5682s->pll_in[pll_id] = freq_in;
2420 	rt5682s->pll_out[pll_id] = freq_out;
2421 	rt5682s->pll_src[pll_id] = source;
2422 
2423 	return 0;
2424 }
2425 
rt5682s_set_bclk1_ratio(struct snd_soc_dai * dai,unsigned int ratio)2426 static int rt5682s_set_bclk1_ratio(struct snd_soc_dai *dai,
2427 		unsigned int ratio)
2428 {
2429 	struct snd_soc_component *component = dai->component;
2430 	struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component);
2431 
2432 	rt5682s->bclk[dai->id] = ratio;
2433 
2434 	switch (ratio) {
2435 	case 256:
2436 		snd_soc_component_update_bits(component, RT5682S_TDM_TCON_CTRL_1,
2437 			RT5682S_TDM_BCLK_MS1_MASK, RT5682S_TDM_BCLK_MS1_256);
2438 		break;
2439 	case 128:
2440 		snd_soc_component_update_bits(component, RT5682S_TDM_TCON_CTRL_1,
2441 			RT5682S_TDM_BCLK_MS1_MASK, RT5682S_TDM_BCLK_MS1_128);
2442 		break;
2443 	case 64:
2444 		snd_soc_component_update_bits(component, RT5682S_TDM_TCON_CTRL_1,
2445 			RT5682S_TDM_BCLK_MS1_MASK, RT5682S_TDM_BCLK_MS1_64);
2446 		break;
2447 	case 32:
2448 		snd_soc_component_update_bits(component, RT5682S_TDM_TCON_CTRL_1,
2449 			RT5682S_TDM_BCLK_MS1_MASK, RT5682S_TDM_BCLK_MS1_32);
2450 		break;
2451 	default:
2452 		dev_err(dai->dev, "Invalid bclk1 ratio %d\n", ratio);
2453 		return -EINVAL;
2454 	}
2455 
2456 	return 0;
2457 }
2458 
rt5682s_set_bclk2_ratio(struct snd_soc_dai * dai,unsigned int ratio)2459 static int rt5682s_set_bclk2_ratio(struct snd_soc_dai *dai, unsigned int ratio)
2460 {
2461 	struct snd_soc_component *component = dai->component;
2462 	struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component);
2463 
2464 	rt5682s->bclk[dai->id] = ratio;
2465 
2466 	switch (ratio) {
2467 	case 64:
2468 		snd_soc_component_update_bits(component, RT5682S_ADDA_CLK_2,
2469 			RT5682S_I2S2_BCLK_MS2_MASK, RT5682S_I2S2_BCLK_MS2_64);
2470 		break;
2471 	case 32:
2472 		snd_soc_component_update_bits(component, RT5682S_ADDA_CLK_2,
2473 			RT5682S_I2S2_BCLK_MS2_MASK, RT5682S_I2S2_BCLK_MS2_32);
2474 		break;
2475 	default:
2476 		dev_err(dai->dev, "Invalid bclk2 ratio %d\n", ratio);
2477 		return -EINVAL;
2478 	}
2479 
2480 	return 0;
2481 }
2482 
rt5682s_set_bias_level(struct snd_soc_component * component,enum snd_soc_bias_level level)2483 static int rt5682s_set_bias_level(struct snd_soc_component *component,
2484 		enum snd_soc_bias_level level)
2485 {
2486 	struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component);
2487 
2488 	switch (level) {
2489 	case SND_SOC_BIAS_PREPARE:
2490 		regmap_update_bits(rt5682s->regmap, RT5682S_PWR_DIG_1,
2491 			RT5682S_PWR_LDO, RT5682S_PWR_LDO);
2492 		break;
2493 	case SND_SOC_BIAS_STANDBY:
2494 		if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF)
2495 			regmap_update_bits(rt5682s->regmap, RT5682S_PWR_DIG_1,
2496 				RT5682S_DIG_GATE_CTRL, RT5682S_DIG_GATE_CTRL);
2497 		break;
2498 	case SND_SOC_BIAS_OFF:
2499 		regmap_update_bits(rt5682s->regmap, RT5682S_PWR_DIG_1, RT5682S_PWR_LDO, 0);
2500 		if (!rt5682s->wclk_enabled)
2501 			regmap_update_bits(rt5682s->regmap, RT5682S_PWR_DIG_1,
2502 				RT5682S_DIG_GATE_CTRL, 0);
2503 		break;
2504 	case SND_SOC_BIAS_ON:
2505 		break;
2506 	}
2507 
2508 	return 0;
2509 }
2510 
2511 #ifdef CONFIG_COMMON_CLK
2512 #define CLK_PLL2_FIN 48000000
2513 #define CLK_48 48000
2514 #define CLK_44 44100
2515 
rt5682s_clk_check(struct rt5682s_priv * rt5682s)2516 static bool rt5682s_clk_check(struct rt5682s_priv *rt5682s)
2517 {
2518 	if (!rt5682s->master[RT5682S_AIF1]) {
2519 		dev_dbg(rt5682s->component->dev, "dai clk fmt not set correctly\n");
2520 		return false;
2521 	}
2522 	return true;
2523 }
2524 
rt5682s_wclk_prepare(struct clk_hw * hw)2525 static int rt5682s_wclk_prepare(struct clk_hw *hw)
2526 {
2527 	struct rt5682s_priv *rt5682s =
2528 		container_of(hw, struct rt5682s_priv, dai_clks_hw[RT5682S_DAI_WCLK_IDX]);
2529 	struct snd_soc_component *component = rt5682s->component;
2530 	int ref, reg;
2531 
2532 	if (!rt5682s_clk_check(rt5682s))
2533 		return -EINVAL;
2534 
2535 	mutex_lock(&rt5682s->wclk_mutex);
2536 
2537 	snd_soc_component_update_bits(component, RT5682S_PWR_ANLG_1,
2538 		RT5682S_PWR_VREF2 | RT5682S_PWR_FV2 | RT5682S_PWR_MB,
2539 		RT5682S_PWR_VREF2 | RT5682S_PWR_MB);
2540 	usleep_range(15000, 20000);
2541 	snd_soc_component_update_bits(component, RT5682S_PWR_ANLG_1,
2542 		RT5682S_PWR_FV2, RT5682S_PWR_FV2);
2543 
2544 	/* Set and power on I2S1 */
2545 	snd_soc_component_update_bits(component, RT5682S_PWR_DIG_1,
2546 		RT5682S_DIG_GATE_CTRL, RT5682S_DIG_GATE_CTRL);
2547 	rt5682s_set_i2s(rt5682s, RT5682S_AIF1, 1);
2548 
2549 	/* Only need to power on PLLB due to the rate set restriction */
2550 	reg = RT5682S_PLL_TRACK_2;
2551 	ref = 256 * rt5682s->lrck[RT5682S_AIF1];
2552 	rt5682s_set_filter_clk(rt5682s, reg, ref);
2553 	rt5682s_set_pllb_power(rt5682s, 1);
2554 
2555 	rt5682s->wclk_enabled = 1;
2556 
2557 	mutex_unlock(&rt5682s->wclk_mutex);
2558 
2559 	return 0;
2560 }
2561 
rt5682s_wclk_unprepare(struct clk_hw * hw)2562 static void rt5682s_wclk_unprepare(struct clk_hw *hw)
2563 {
2564 	struct rt5682s_priv *rt5682s =
2565 		container_of(hw, struct rt5682s_priv, dai_clks_hw[RT5682S_DAI_WCLK_IDX]);
2566 	struct snd_soc_component *component = rt5682s->component;
2567 
2568 	if (!rt5682s_clk_check(rt5682s))
2569 		return;
2570 
2571 	mutex_lock(&rt5682s->wclk_mutex);
2572 
2573 	if (!rt5682s->jack_type)
2574 		snd_soc_component_update_bits(component, RT5682S_PWR_ANLG_1,
2575 			RT5682S_PWR_VREF2 | RT5682S_PWR_FV2 | RT5682S_PWR_MB, 0);
2576 
2577 	/* Power down I2S1 */
2578 	rt5682s_set_i2s(rt5682s, RT5682S_AIF1, 0);
2579 	snd_soc_component_update_bits(component, RT5682S_PWR_DIG_1,
2580 		RT5682S_DIG_GATE_CTRL, 0);
2581 
2582 	/* Power down PLLB */
2583 	rt5682s_set_pllb_power(rt5682s, 0);
2584 
2585 	rt5682s->wclk_enabled = 0;
2586 
2587 	mutex_unlock(&rt5682s->wclk_mutex);
2588 }
2589 
rt5682s_wclk_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)2590 static unsigned long rt5682s_wclk_recalc_rate(struct clk_hw *hw,
2591 					     unsigned long parent_rate)
2592 {
2593 	struct rt5682s_priv *rt5682s =
2594 		container_of(hw, struct rt5682s_priv, dai_clks_hw[RT5682S_DAI_WCLK_IDX]);
2595 	struct snd_soc_component *component = rt5682s->component;
2596 	const char * const clk_name = clk_hw_get_name(hw);
2597 
2598 	if (!rt5682s_clk_check(rt5682s))
2599 		return 0;
2600 	/*
2601 	 * Only accept to set wclk rate to 44.1k or 48kHz.
2602 	 */
2603 	if (rt5682s->lrck[RT5682S_AIF1] != CLK_48 &&
2604 	    rt5682s->lrck[RT5682S_AIF1] != CLK_44) {
2605 		dev_warn(component->dev, "%s: clk %s only support %d or %d Hz output\n",
2606 			__func__, clk_name, CLK_44, CLK_48);
2607 		return 0;
2608 	}
2609 
2610 	return rt5682s->lrck[RT5682S_AIF1];
2611 }
2612 
rt5682s_wclk_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * parent_rate)2613 static long rt5682s_wclk_round_rate(struct clk_hw *hw, unsigned long rate,
2614 				   unsigned long *parent_rate)
2615 {
2616 	struct rt5682s_priv *rt5682s =
2617 		container_of(hw, struct rt5682s_priv, dai_clks_hw[RT5682S_DAI_WCLK_IDX]);
2618 	struct snd_soc_component *component = rt5682s->component;
2619 	const char * const clk_name = clk_hw_get_name(hw);
2620 
2621 	if (!rt5682s_clk_check(rt5682s))
2622 		return -EINVAL;
2623 	/*
2624 	 * Only accept to set wclk rate to 44.1k or 48kHz.
2625 	 * It will force to 48kHz if not both.
2626 	 */
2627 	if (rate != CLK_48 && rate != CLK_44) {
2628 		dev_warn(component->dev, "%s: clk %s only support %d or %d Hz output\n",
2629 			__func__, clk_name, CLK_44, CLK_48);
2630 		rate = CLK_48;
2631 	}
2632 
2633 	return rate;
2634 }
2635 
rt5682s_wclk_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)2636 static int rt5682s_wclk_set_rate(struct clk_hw *hw, unsigned long rate,
2637 				unsigned long parent_rate)
2638 {
2639 	struct rt5682s_priv *rt5682s =
2640 		container_of(hw, struct rt5682s_priv, dai_clks_hw[RT5682S_DAI_WCLK_IDX]);
2641 	struct snd_soc_component *component = rt5682s->component;
2642 	struct clk *parent_clk;
2643 	const char * const clk_name = clk_hw_get_name(hw);
2644 	unsigned int clk_pll2_fout;
2645 
2646 	if (!rt5682s_clk_check(rt5682s))
2647 		return -EINVAL;
2648 
2649 	/*
2650 	 * Whether the wclk's parent clk (mclk) exists or not, please ensure
2651 	 * it is fixed or set to 48MHz before setting wclk rate. It's a
2652 	 * temporary limitation. Only accept 48MHz clk as the clk provider.
2653 	 *
2654 	 * It will set the codec anyway by assuming mclk is 48MHz.
2655 	 */
2656 	parent_clk = clk_get_parent(hw->clk);
2657 	if (!parent_clk)
2658 		dev_warn(component->dev,
2659 			"Parent mclk of wclk not acquired in driver. Please ensure mclk was provided as %d Hz.\n",
2660 			CLK_PLL2_FIN);
2661 
2662 	if (parent_rate != CLK_PLL2_FIN)
2663 		dev_warn(component->dev, "clk %s only support %d Hz input\n",
2664 			clk_name, CLK_PLL2_FIN);
2665 
2666 	/*
2667 	 * To achieve the rate conversion from 48MHz to 44.1k or 48kHz,
2668 	 * PLL2 is needed.
2669 	 */
2670 	clk_pll2_fout = rate * 512;
2671 	rt5682s_set_component_pll(component, RT5682S_PLL2, RT5682S_PLL_S_MCLK,
2672 		CLK_PLL2_FIN, clk_pll2_fout);
2673 
2674 	rt5682s_set_component_sysclk(component, RT5682S_SCLK_S_PLL2, 0,
2675 		clk_pll2_fout, SND_SOC_CLOCK_IN);
2676 
2677 	rt5682s->lrck[RT5682S_AIF1] = rate;
2678 
2679 	return 0;
2680 }
2681 
rt5682s_bclk_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)2682 static unsigned long rt5682s_bclk_recalc_rate(struct clk_hw *hw,
2683 					     unsigned long parent_rate)
2684 {
2685 	struct rt5682s_priv *rt5682s =
2686 		container_of(hw, struct rt5682s_priv, dai_clks_hw[RT5682S_DAI_BCLK_IDX]);
2687 	struct snd_soc_component *component = rt5682s->component;
2688 	unsigned int bclks_per_wclk;
2689 
2690 	bclks_per_wclk = snd_soc_component_read(component, RT5682S_TDM_TCON_CTRL_1);
2691 
2692 	switch (bclks_per_wclk & RT5682S_TDM_BCLK_MS1_MASK) {
2693 	case RT5682S_TDM_BCLK_MS1_256:
2694 		return parent_rate * 256;
2695 	case RT5682S_TDM_BCLK_MS1_128:
2696 		return parent_rate * 128;
2697 	case RT5682S_TDM_BCLK_MS1_64:
2698 		return parent_rate * 64;
2699 	case RT5682S_TDM_BCLK_MS1_32:
2700 		return parent_rate * 32;
2701 	default:
2702 		return 0;
2703 	}
2704 }
2705 
rt5682s_bclk_get_factor(unsigned long rate,unsigned long parent_rate)2706 static unsigned long rt5682s_bclk_get_factor(unsigned long rate,
2707 					    unsigned long parent_rate)
2708 {
2709 	unsigned long factor;
2710 
2711 	factor = rate / parent_rate;
2712 	if (factor < 64)
2713 		return 32;
2714 	else if (factor < 128)
2715 		return 64;
2716 	else if (factor < 256)
2717 		return 128;
2718 	else
2719 		return 256;
2720 }
2721 
rt5682s_bclk_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * parent_rate)2722 static long rt5682s_bclk_round_rate(struct clk_hw *hw, unsigned long rate,
2723 				   unsigned long *parent_rate)
2724 {
2725 	struct rt5682s_priv *rt5682s =
2726 		container_of(hw, struct rt5682s_priv, dai_clks_hw[RT5682S_DAI_BCLK_IDX]);
2727 	unsigned long factor;
2728 
2729 	if (!*parent_rate || !rt5682s_clk_check(rt5682s))
2730 		return -EINVAL;
2731 
2732 	/*
2733 	 * BCLK rates are set as a multiplier of WCLK in HW.
2734 	 * We don't allow changing the parent WCLK. We just do
2735 	 * some rounding down based on the parent WCLK rate
2736 	 * and find the appropriate multiplier of BCLK to
2737 	 * get the rounded down BCLK value.
2738 	 */
2739 	factor = rt5682s_bclk_get_factor(rate, *parent_rate);
2740 
2741 	return *parent_rate * factor;
2742 }
2743 
rt5682s_bclk_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)2744 static int rt5682s_bclk_set_rate(struct clk_hw *hw, unsigned long rate,
2745 				unsigned long parent_rate)
2746 {
2747 	struct rt5682s_priv *rt5682s =
2748 		container_of(hw, struct rt5682s_priv, dai_clks_hw[RT5682S_DAI_BCLK_IDX]);
2749 	struct snd_soc_component *component = rt5682s->component;
2750 	struct snd_soc_dai *dai;
2751 	unsigned long factor;
2752 
2753 	if (!rt5682s_clk_check(rt5682s))
2754 		return -EINVAL;
2755 
2756 	factor = rt5682s_bclk_get_factor(rate, parent_rate);
2757 
2758 	for_each_component_dais(component, dai)
2759 		if (dai->id == RT5682S_AIF1)
2760 			return rt5682s_set_bclk1_ratio(dai, factor);
2761 
2762 	dev_err(component->dev, "dai %d not found in component\n",
2763 		RT5682S_AIF1);
2764 	return -ENODEV;
2765 }
2766 
2767 static const struct clk_ops rt5682s_dai_clk_ops[RT5682S_DAI_NUM_CLKS] = {
2768 	[RT5682S_DAI_WCLK_IDX] = {
2769 		.prepare = rt5682s_wclk_prepare,
2770 		.unprepare = rt5682s_wclk_unprepare,
2771 		.recalc_rate = rt5682s_wclk_recalc_rate,
2772 		.round_rate = rt5682s_wclk_round_rate,
2773 		.set_rate = rt5682s_wclk_set_rate,
2774 	},
2775 	[RT5682S_DAI_BCLK_IDX] = {
2776 		.recalc_rate = rt5682s_bclk_recalc_rate,
2777 		.round_rate = rt5682s_bclk_round_rate,
2778 		.set_rate = rt5682s_bclk_set_rate,
2779 	},
2780 };
2781 
rt5682s_register_dai_clks(struct snd_soc_component * component)2782 static int rt5682s_register_dai_clks(struct snd_soc_component *component)
2783 {
2784 	struct device *dev = component->dev;
2785 	struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component);
2786 	struct rt5682s_platform_data *pdata = &rt5682s->pdata;
2787 	struct clk_hw *dai_clk_hw;
2788 	int i, ret;
2789 
2790 	for (i = 0; i < RT5682S_DAI_NUM_CLKS; ++i) {
2791 		struct clk_init_data init = { };
2792 		struct clk_parent_data parent_data;
2793 		const struct clk_hw *parent;
2794 
2795 		dai_clk_hw = &rt5682s->dai_clks_hw[i];
2796 
2797 		switch (i) {
2798 		case RT5682S_DAI_WCLK_IDX:
2799 			/* Make MCLK the parent of WCLK */
2800 			if (rt5682s->mclk) {
2801 				parent_data = (struct clk_parent_data){
2802 					.fw_name = "mclk",
2803 				};
2804 				init.parent_data = &parent_data;
2805 				init.num_parents = 1;
2806 			}
2807 			break;
2808 		case RT5682S_DAI_BCLK_IDX:
2809 			/* Make WCLK the parent of BCLK */
2810 			parent = &rt5682s->dai_clks_hw[RT5682S_DAI_WCLK_IDX];
2811 			init.parent_hws = &parent;
2812 			init.num_parents = 1;
2813 			break;
2814 		default:
2815 			dev_err(dev, "Invalid clock index\n");
2816 			return -EINVAL;
2817 		}
2818 
2819 		init.name = pdata->dai_clk_names[i];
2820 		init.ops = &rt5682s_dai_clk_ops[i];
2821 		init.flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_GATE;
2822 		dai_clk_hw->init = &init;
2823 
2824 		ret = devm_clk_hw_register(dev, dai_clk_hw);
2825 		if (ret) {
2826 			dev_warn(dev, "Failed to register %s: %d\n", init.name, ret);
2827 			return ret;
2828 		}
2829 
2830 		if (dev->of_node) {
2831 			ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, dai_clk_hw);
2832 			if (ret)
2833 				return ret;
2834 		} else {
2835 			ret = devm_clk_hw_register_clkdev(dev, dai_clk_hw,
2836 							  init.name, dev_name(dev));
2837 			if (ret)
2838 				return ret;
2839 		}
2840 	}
2841 
2842 	return 0;
2843 }
2844 
rt5682s_dai_probe_clks(struct snd_soc_component * component)2845 static int rt5682s_dai_probe_clks(struct snd_soc_component *component)
2846 {
2847 	struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component);
2848 	int ret;
2849 
2850 	/* Check if MCLK provided */
2851 	rt5682s->mclk = devm_clk_get_optional(component->dev, "mclk");
2852 	if (IS_ERR(rt5682s->mclk))
2853 		return PTR_ERR(rt5682s->mclk);
2854 
2855 	/* Register CCF DAI clock control */
2856 	ret = rt5682s_register_dai_clks(component);
2857 	if (ret)
2858 		return ret;
2859 
2860 	/* Initial setup for CCF */
2861 	rt5682s->lrck[RT5682S_AIF1] = CLK_48;
2862 
2863 	return 0;
2864 }
2865 #else
rt5682s_dai_probe_clks(struct snd_soc_component * component)2866 static inline int rt5682s_dai_probe_clks(struct snd_soc_component *component)
2867 {
2868 	return 0;
2869 }
2870 #endif /* CONFIG_COMMON_CLK */
2871 
rt5682s_probe(struct snd_soc_component * component)2872 static int rt5682s_probe(struct snd_soc_component *component)
2873 {
2874 	struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component);
2875 
2876 	rt5682s->component = component;
2877 
2878 	return rt5682s_dai_probe_clks(component);
2879 }
2880 
rt5682s_remove(struct snd_soc_component * component)2881 static void rt5682s_remove(struct snd_soc_component *component)
2882 {
2883 	struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component);
2884 
2885 	rt5682s_reset(rt5682s);
2886 }
2887 
2888 #ifdef CONFIG_PM
rt5682s_suspend(struct snd_soc_component * component)2889 static int rt5682s_suspend(struct snd_soc_component *component)
2890 {
2891 	struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component);
2892 
2893 	if (rt5682s->irq)
2894 		disable_irq(rt5682s->irq);
2895 
2896 	cancel_delayed_work_sync(&rt5682s->jack_detect_work);
2897 	cancel_delayed_work_sync(&rt5682s->jd_check_work);
2898 
2899 	if (rt5682s->hs_jack)
2900 		rt5682s->jack_type = rt5682s_headset_detect(component, 0);
2901 
2902 	regcache_cache_only(rt5682s->regmap, true);
2903 	regcache_mark_dirty(rt5682s->regmap);
2904 
2905 	return 0;
2906 }
2907 
rt5682s_resume(struct snd_soc_component * component)2908 static int rt5682s_resume(struct snd_soc_component *component)
2909 {
2910 	struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component);
2911 
2912 	regcache_cache_only(rt5682s->regmap, false);
2913 	regcache_sync(rt5682s->regmap);
2914 
2915 	if (rt5682s->hs_jack) {
2916 		mod_delayed_work(system_power_efficient_wq,
2917 			&rt5682s->jack_detect_work, msecs_to_jiffies(0));
2918 	}
2919 
2920 	if (rt5682s->irq)
2921 		enable_irq(rt5682s->irq);
2922 
2923 	return 0;
2924 }
2925 #else
2926 #define rt5682s_suspend NULL
2927 #define rt5682s_resume NULL
2928 #endif
2929 
2930 static const struct snd_soc_dai_ops rt5682s_aif1_dai_ops = {
2931 	.hw_params = rt5682s_hw_params,
2932 	.set_fmt = rt5682s_set_dai_fmt,
2933 	.set_tdm_slot = rt5682s_set_tdm_slot,
2934 	.set_bclk_ratio = rt5682s_set_bclk1_ratio,
2935 };
2936 
2937 static const struct snd_soc_dai_ops rt5682s_aif2_dai_ops = {
2938 	.hw_params = rt5682s_hw_params,
2939 	.set_fmt = rt5682s_set_dai_fmt,
2940 	.set_bclk_ratio = rt5682s_set_bclk2_ratio,
2941 };
2942 
2943 static const struct snd_soc_component_driver rt5682s_soc_component_dev = {
2944 	.probe = rt5682s_probe,
2945 	.remove = rt5682s_remove,
2946 	.suspend = rt5682s_suspend,
2947 	.resume = rt5682s_resume,
2948 	.set_bias_level = rt5682s_set_bias_level,
2949 	.controls = rt5682s_snd_controls,
2950 	.num_controls = ARRAY_SIZE(rt5682s_snd_controls),
2951 	.dapm_widgets = rt5682s_dapm_widgets,
2952 	.num_dapm_widgets = ARRAY_SIZE(rt5682s_dapm_widgets),
2953 	.dapm_routes = rt5682s_dapm_routes,
2954 	.num_dapm_routes = ARRAY_SIZE(rt5682s_dapm_routes),
2955 	.set_sysclk = rt5682s_set_component_sysclk,
2956 	.set_pll = rt5682s_set_component_pll,
2957 	.set_jack = rt5682s_set_jack_detect,
2958 	.use_pmdown_time	= 1,
2959 	.endianness		= 1,
2960 };
2961 
rt5682s_parse_dt(struct rt5682s_priv * rt5682s,struct device * dev)2962 static int rt5682s_parse_dt(struct rt5682s_priv *rt5682s, struct device *dev)
2963 {
2964 	device_property_read_u32(dev, "realtek,dmic1-data-pin",
2965 		&rt5682s->pdata.dmic1_data_pin);
2966 	device_property_read_u32(dev, "realtek,dmic1-clk-pin",
2967 		&rt5682s->pdata.dmic1_clk_pin);
2968 	device_property_read_u32(dev, "realtek,jd-src",
2969 		&rt5682s->pdata.jd_src);
2970 	device_property_read_u32(dev, "realtek,dmic-clk-rate-hz",
2971 		&rt5682s->pdata.dmic_clk_rate);
2972 	device_property_read_u32(dev, "realtek,dmic-delay-ms",
2973 		&rt5682s->pdata.dmic_delay);
2974 	device_property_read_u32(dev, "realtek,amic-delay-ms",
2975 		&rt5682s->pdata.amic_delay);
2976 
2977 	if (device_property_read_string_array(dev, "clock-output-names",
2978 					      rt5682s->pdata.dai_clk_names,
2979 					      RT5682S_DAI_NUM_CLKS) < 0)
2980 		dev_warn(dev, "Using default DAI clk names: %s, %s\n",
2981 			 rt5682s->pdata.dai_clk_names[RT5682S_DAI_WCLK_IDX],
2982 			 rt5682s->pdata.dai_clk_names[RT5682S_DAI_BCLK_IDX]);
2983 
2984 	rt5682s->pdata.dmic_clk_driving_high = device_property_read_bool(dev,
2985 		"realtek,dmic-clk-driving-high");
2986 
2987 	return 0;
2988 }
2989 
rt5682s_calibrate(struct rt5682s_priv * rt5682s)2990 static void rt5682s_calibrate(struct rt5682s_priv *rt5682s)
2991 {
2992 	unsigned int count, value;
2993 
2994 	mutex_lock(&rt5682s->calibrate_mutex);
2995 
2996 	regmap_write(rt5682s->regmap, RT5682S_PWR_ANLG_1, 0xaa80);
2997 	usleep_range(15000, 20000);
2998 	regmap_write(rt5682s->regmap, RT5682S_PWR_ANLG_1, 0xfa80);
2999 	regmap_write(rt5682s->regmap, RT5682S_PWR_DIG_1, 0x01c0);
3000 	regmap_write(rt5682s->regmap, RT5682S_MICBIAS_2, 0x0380);
3001 	regmap_write(rt5682s->regmap, RT5682S_GLB_CLK, 0x8000);
3002 	regmap_write(rt5682s->regmap, RT5682S_ADDA_CLK_1, 0x1001);
3003 	regmap_write(rt5682s->regmap, RT5682S_CHOP_DAC_2, 0x3030);
3004 	regmap_write(rt5682s->regmap, RT5682S_CHOP_ADC, 0xb000);
3005 	regmap_write(rt5682s->regmap, RT5682S_STO1_ADC_MIXER, 0x686c);
3006 	regmap_write(rt5682s->regmap, RT5682S_CAL_REC, 0x5151);
3007 	regmap_write(rt5682s->regmap, RT5682S_HP_CALIB_CTRL_2, 0x0321);
3008 	regmap_write(rt5682s->regmap, RT5682S_HP_LOGIC_CTRL_2, 0x0004);
3009 	regmap_write(rt5682s->regmap, RT5682S_HP_CALIB_CTRL_1, 0x7c00);
3010 	regmap_write(rt5682s->regmap, RT5682S_HP_CALIB_CTRL_1, 0xfc00);
3011 
3012 	for (count = 0; count < 60; count++) {
3013 		regmap_read(rt5682s->regmap, RT5682S_HP_CALIB_ST_1, &value);
3014 		if (!(value & 0x8000))
3015 			break;
3016 
3017 		usleep_range(10000, 10005);
3018 	}
3019 
3020 	if (count >= 60)
3021 		dev_err(rt5682s->component->dev, "HP Calibration Failure\n");
3022 
3023 	/* restore settings */
3024 	regmap_write(rt5682s->regmap, RT5682S_MICBIAS_2, 0x0180);
3025 	regmap_write(rt5682s->regmap, RT5682S_CAL_REC, 0x5858);
3026 	regmap_write(rt5682s->regmap, RT5682S_STO1_ADC_MIXER, 0xc0c4);
3027 	regmap_write(rt5682s->regmap, RT5682S_HP_CALIB_CTRL_2, 0x0320);
3028 	regmap_write(rt5682s->regmap, RT5682S_PWR_DIG_1, 0x00c0);
3029 	regmap_write(rt5682s->regmap, RT5682S_PWR_ANLG_1, 0x0800);
3030 	regmap_write(rt5682s->regmap, RT5682S_GLB_CLK, 0x0000);
3031 
3032 	mutex_unlock(&rt5682s->calibrate_mutex);
3033 }
3034 
3035 static const struct regmap_config rt5682s_regmap = {
3036 	.reg_bits = 16,
3037 	.val_bits = 16,
3038 	.max_register = RT5682S_MAX_REG,
3039 	.volatile_reg = rt5682s_volatile_register,
3040 	.readable_reg = rt5682s_readable_register,
3041 	.cache_type = REGCACHE_MAPLE,
3042 	.reg_defaults = rt5682s_reg,
3043 	.num_reg_defaults = ARRAY_SIZE(rt5682s_reg),
3044 	.use_single_read = true,
3045 	.use_single_write = true,
3046 };
3047 
3048 static struct snd_soc_dai_driver rt5682s_dai[] = {
3049 	{
3050 		.name = "rt5682s-aif1",
3051 		.id = RT5682S_AIF1,
3052 		.playback = {
3053 			.stream_name = "AIF1 Playback",
3054 			.channels_min = 1,
3055 			.channels_max = 2,
3056 			.rates = RT5682S_STEREO_RATES,
3057 			.formats = RT5682S_FORMATS,
3058 		},
3059 		.capture = {
3060 			.stream_name = "AIF1 Capture",
3061 			.channels_min = 1,
3062 			.channels_max = 2,
3063 			.rates = RT5682S_STEREO_RATES,
3064 			.formats = RT5682S_FORMATS,
3065 		},
3066 		.ops = &rt5682s_aif1_dai_ops,
3067 	},
3068 	{
3069 		.name = "rt5682s-aif2",
3070 		.id = RT5682S_AIF2,
3071 		.capture = {
3072 			.stream_name = "AIF2 Capture",
3073 			.channels_min = 1,
3074 			.channels_max = 2,
3075 			.rates = RT5682S_STEREO_RATES,
3076 			.formats = RT5682S_FORMATS,
3077 		},
3078 		.ops = &rt5682s_aif2_dai_ops,
3079 	},
3080 };
3081 
rt5682s_i2c_disable_regulators(void * data)3082 static void rt5682s_i2c_disable_regulators(void *data)
3083 {
3084 	struct rt5682s_priv *rt5682s = data;
3085 	struct device *dev = regmap_get_device(rt5682s->regmap);
3086 	int ret;
3087 
3088 	ret = regulator_disable(rt5682s->supplies[RT5682S_SUPPLY_AVDD].consumer);
3089 	if (ret)
3090 		dev_err(dev, "Failed to disable supply AVDD: %d\n", ret);
3091 
3092 	ret = regulator_disable(rt5682s->supplies[RT5682S_SUPPLY_DBVDD].consumer);
3093 	if (ret)
3094 		dev_err(dev, "Failed to disable supply DBVDD: %d\n", ret);
3095 
3096 	ret = regulator_disable(rt5682s->supplies[RT5682S_SUPPLY_LDO1_IN].consumer);
3097 	if (ret)
3098 		dev_err(dev, "Failed to disable supply LDO1-IN: %d\n", ret);
3099 
3100 	usleep_range(1000, 1500);
3101 
3102 	ret = regulator_disable(rt5682s->supplies[RT5682S_SUPPLY_MICVDD].consumer);
3103 	if (ret)
3104 		dev_err(dev, "Failed to disable supply MICVDD: %d\n", ret);
3105 }
3106 
rt5682s_i2c_probe(struct i2c_client * i2c)3107 static int rt5682s_i2c_probe(struct i2c_client *i2c)
3108 {
3109 	struct rt5682s_platform_data *pdata = dev_get_platdata(&i2c->dev);
3110 	struct rt5682s_priv *rt5682s;
3111 	int i, ret;
3112 	unsigned int val;
3113 
3114 	rt5682s = devm_kzalloc(&i2c->dev, sizeof(struct rt5682s_priv), GFP_KERNEL);
3115 	if (!rt5682s)
3116 		return -ENOMEM;
3117 
3118 	i2c_set_clientdata(i2c, rt5682s);
3119 
3120 	rt5682s->pdata = i2s_default_platform_data;
3121 
3122 	if (pdata)
3123 		rt5682s->pdata = *pdata;
3124 	else
3125 		rt5682s_parse_dt(rt5682s, &i2c->dev);
3126 
3127 	rt5682s->regmap = devm_regmap_init_i2c(i2c, &rt5682s_regmap);
3128 	if (IS_ERR(rt5682s->regmap)) {
3129 		ret = PTR_ERR(rt5682s->regmap);
3130 		dev_err(&i2c->dev, "Failed to allocate register map: %d\n", ret);
3131 		return ret;
3132 	}
3133 
3134 	for (i = 0; i < ARRAY_SIZE(rt5682s->supplies); i++)
3135 		rt5682s->supplies[i].supply = rt5682s_supply_names[i];
3136 
3137 	ret = devm_regulator_bulk_get(&i2c->dev,
3138 			ARRAY_SIZE(rt5682s->supplies), rt5682s->supplies);
3139 	if (ret) {
3140 		dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
3141 		return ret;
3142 	}
3143 
3144 	ret = devm_add_action_or_reset(&i2c->dev, rt5682s_i2c_disable_regulators, rt5682s);
3145 	if (ret)
3146 		return ret;
3147 
3148 	ret = regulator_enable(rt5682s->supplies[RT5682S_SUPPLY_MICVDD].consumer);
3149 	if (ret) {
3150 		dev_err(&i2c->dev, "Failed to enable supply MICVDD: %d\n", ret);
3151 		return ret;
3152 	}
3153 	usleep_range(1000, 1500);
3154 
3155 	ret = regulator_enable(rt5682s->supplies[RT5682S_SUPPLY_AVDD].consumer);
3156 	if (ret) {
3157 		dev_err(&i2c->dev, "Failed to enable supply AVDD: %d\n", ret);
3158 		return ret;
3159 	}
3160 
3161 	ret = regulator_enable(rt5682s->supplies[RT5682S_SUPPLY_DBVDD].consumer);
3162 	if (ret) {
3163 		dev_err(&i2c->dev, "Failed to enable supply DBVDD: %d\n", ret);
3164 		return ret;
3165 	}
3166 
3167 	ret = regulator_enable(rt5682s->supplies[RT5682S_SUPPLY_LDO1_IN].consumer);
3168 	if (ret) {
3169 		dev_err(&i2c->dev, "Failed to enable supply LDO1-IN: %d\n", ret);
3170 		return ret;
3171 	}
3172 
3173 	rt5682s->ldo1_en = devm_gpiod_get_optional(&i2c->dev,
3174 						   "realtek,ldo1-en",
3175 						   GPIOD_OUT_HIGH);
3176 	if (IS_ERR(rt5682s->ldo1_en)) {
3177 		dev_err(&i2c->dev, "Fail gpio request ldo1_en\n");
3178 		return PTR_ERR(rt5682s->ldo1_en);
3179 	}
3180 
3181 	/* Sleep for 50 ms minimum */
3182 	usleep_range(50000, 55000);
3183 
3184 	regmap_read(rt5682s->regmap, RT5682S_DEVICE_ID, &val);
3185 	if (val != DEVICE_ID) {
3186 		dev_err(&i2c->dev, "Device with ID register %x is not rt5682s\n", val);
3187 		return -ENODEV;
3188 	}
3189 
3190 	rt5682s_reset(rt5682s);
3191 	rt5682s_apply_patch_list(rt5682s, &i2c->dev);
3192 
3193 	regmap_update_bits(rt5682s->regmap, RT5682S_PWR_DIG_2,
3194 		RT5682S_DLDO_I_LIMIT_MASK, RT5682S_DLDO_I_LIMIT_DIS);
3195 	usleep_range(20000, 25000);
3196 
3197 	mutex_init(&rt5682s->calibrate_mutex);
3198 	mutex_init(&rt5682s->sar_mutex);
3199 	mutex_init(&rt5682s->wclk_mutex);
3200 	rt5682s_calibrate(rt5682s);
3201 
3202 	regmap_update_bits(rt5682s->regmap, RT5682S_MICBIAS_2,
3203 		RT5682S_PWR_CLK25M_MASK | RT5682S_PWR_CLK1M_MASK,
3204 		RT5682S_PWR_CLK25M_PD | RT5682S_PWR_CLK1M_PU);
3205 	regmap_update_bits(rt5682s->regmap, RT5682S_PWR_ANLG_1,
3206 		RT5682S_PWR_BG, RT5682S_PWR_BG);
3207 	regmap_update_bits(rt5682s->regmap, RT5682S_HP_LOGIC_CTRL_2,
3208 		RT5682S_HP_SIG_SRC_MASK, RT5682S_HP_SIG_SRC_1BIT_CTL);
3209 	regmap_update_bits(rt5682s->regmap, RT5682S_HP_CHARGE_PUMP_2,
3210 		RT5682S_PM_HP_MASK, RT5682S_PM_HP_HV);
3211 	regmap_update_bits(rt5682s->regmap, RT5682S_HP_AMP_DET_CTL_1,
3212 		RT5682S_CP_SW_SIZE_MASK, RT5682S_CP_SW_SIZE_M);
3213 
3214 	/* DMIC data pin */
3215 	switch (rt5682s->pdata.dmic1_data_pin) {
3216 	case RT5682S_DMIC1_DATA_NULL:
3217 		break;
3218 	case RT5682S_DMIC1_DATA_GPIO2: /* share with LRCK2 */
3219 		regmap_update_bits(rt5682s->regmap, RT5682S_DMIC_CTRL_1,
3220 			RT5682S_DMIC_1_DP_MASK, RT5682S_DMIC_1_DP_GPIO2);
3221 		regmap_update_bits(rt5682s->regmap, RT5682S_GPIO_CTRL_1,
3222 			RT5682S_GP2_PIN_MASK, RT5682S_GP2_PIN_DMIC_SDA);
3223 		break;
3224 	case RT5682S_DMIC1_DATA_GPIO5: /* share with DACDAT1 */
3225 		regmap_update_bits(rt5682s->regmap, RT5682S_DMIC_CTRL_1,
3226 			RT5682S_DMIC_1_DP_MASK, RT5682S_DMIC_1_DP_GPIO5);
3227 		regmap_update_bits(rt5682s->regmap, RT5682S_GPIO_CTRL_1,
3228 			RT5682S_GP5_PIN_MASK, RT5682S_GP5_PIN_DMIC_SDA);
3229 		break;
3230 	default:
3231 		dev_warn(&i2c->dev, "invalid DMIC_DAT pin\n");
3232 		break;
3233 	}
3234 
3235 	/* DMIC clk pin */
3236 	switch (rt5682s->pdata.dmic1_clk_pin) {
3237 	case RT5682S_DMIC1_CLK_NULL:
3238 		break;
3239 	case RT5682S_DMIC1_CLK_GPIO1: /* share with IRQ */
3240 		regmap_update_bits(rt5682s->regmap, RT5682S_GPIO_CTRL_1,
3241 			RT5682S_GP1_PIN_MASK, RT5682S_GP1_PIN_DMIC_CLK);
3242 		break;
3243 	case RT5682S_DMIC1_CLK_GPIO3: /* share with BCLK2 */
3244 		regmap_update_bits(rt5682s->regmap, RT5682S_GPIO_CTRL_1,
3245 			RT5682S_GP3_PIN_MASK, RT5682S_GP3_PIN_DMIC_CLK);
3246 		if (rt5682s->pdata.dmic_clk_driving_high)
3247 			regmap_update_bits(rt5682s->regmap, RT5682S_PAD_DRIVING_CTRL,
3248 				RT5682S_PAD_DRV_GP3_MASK, RT5682S_PAD_DRV_GP3_HIGH);
3249 		break;
3250 	default:
3251 		dev_warn(&i2c->dev, "invalid DMIC_CLK pin\n");
3252 		break;
3253 	}
3254 
3255 	INIT_DELAYED_WORK(&rt5682s->jack_detect_work, rt5682s_jack_detect_handler);
3256 	INIT_DELAYED_WORK(&rt5682s->jd_check_work, rt5682s_jd_check_handler);
3257 
3258 	if (i2c->irq) {
3259 		ret = devm_request_threaded_irq(&i2c->dev, i2c->irq, NULL, rt5682s_irq,
3260 			IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
3261 			"rt5682s", rt5682s);
3262 		if (!ret)
3263 			rt5682s->irq = i2c->irq;
3264 		else
3265 			dev_err(&i2c->dev, "Failed to reguest IRQ: %d\n", ret);
3266 	}
3267 
3268 	return devm_snd_soc_register_component(&i2c->dev, &rt5682s_soc_component_dev,
3269 			rt5682s_dai, ARRAY_SIZE(rt5682s_dai));
3270 }
3271 
rt5682s_i2c_shutdown(struct i2c_client * client)3272 static void rt5682s_i2c_shutdown(struct i2c_client *client)
3273 {
3274 	struct rt5682s_priv *rt5682s = i2c_get_clientdata(client);
3275 
3276 	disable_irq(client->irq);
3277 	cancel_delayed_work_sync(&rt5682s->jack_detect_work);
3278 	cancel_delayed_work_sync(&rt5682s->jd_check_work);
3279 
3280 	rt5682s_reset(rt5682s);
3281 }
3282 
rt5682s_i2c_remove(struct i2c_client * client)3283 static void rt5682s_i2c_remove(struct i2c_client *client)
3284 {
3285 	rt5682s_i2c_shutdown(client);
3286 }
3287 
3288 static const struct of_device_id rt5682s_of_match[] = {
3289 	{.compatible = "realtek,rt5682s"},
3290 	{},
3291 };
3292 MODULE_DEVICE_TABLE(of, rt5682s_of_match);
3293 
3294 static const struct acpi_device_id rt5682s_acpi_match[] = {
3295 	{"RTL5682", 0,},
3296 	{},
3297 };
3298 MODULE_DEVICE_TABLE(acpi, rt5682s_acpi_match);
3299 
3300 static const struct i2c_device_id rt5682s_i2c_id[] = {
3301 	{"rt5682s", 0},
3302 	{}
3303 };
3304 MODULE_DEVICE_TABLE(i2c, rt5682s_i2c_id);
3305 
3306 static struct i2c_driver rt5682s_i2c_driver = {
3307 	.driver = {
3308 		.name = "rt5682s",
3309 		.of_match_table = rt5682s_of_match,
3310 		.acpi_match_table = rt5682s_acpi_match,
3311 		.probe_type = PROBE_PREFER_ASYNCHRONOUS,
3312 	},
3313 	.probe = rt5682s_i2c_probe,
3314 	.remove = rt5682s_i2c_remove,
3315 	.shutdown = rt5682s_i2c_shutdown,
3316 	.id_table = rt5682s_i2c_id,
3317 };
3318 module_i2c_driver(rt5682s_i2c_driver);
3319 
3320 MODULE_DESCRIPTION("ASoC RT5682I-VS driver");
3321 MODULE_AUTHOR("Derek Fang <derek.fang@realtek.com>");
3322 MODULE_LICENSE("GPL v2");
3323