1 /* 2 * rt5682.c -- RT5682 ALSA SoC audio component driver 3 * 4 * Copyright 2018 Realtek Semiconductor Corp. 5 * Author: Bard Liao <bardliao@realtek.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11 12 #include <linux/module.h> 13 #include <linux/moduleparam.h> 14 #include <linux/init.h> 15 #include <linux/delay.h> 16 #include <linux/pm.h> 17 #include <linux/i2c.h> 18 #include <linux/platform_device.h> 19 #include <linux/spi/spi.h> 20 #include <linux/acpi.h> 21 #include <linux/gpio.h> 22 #include <linux/of_gpio.h> 23 #include <linux/regulator/consumer.h> 24 #include <linux/mutex.h> 25 #include <sound/core.h> 26 #include <sound/pcm.h> 27 #include <sound/pcm_params.h> 28 #include <sound/jack.h> 29 #include <sound/soc.h> 30 #include <sound/soc-dapm.h> 31 #include <sound/initval.h> 32 #include <sound/tlv.h> 33 #include <sound/rt5682.h> 34 35 #include "rl6231.h" 36 #include "rt5682.h" 37 38 #define RT5682_NUM_SUPPLIES 3 39 40 static const char *rt5682_supply_names[RT5682_NUM_SUPPLIES] = { 41 "AVDD", 42 "MICVDD", 43 "VBAT", 44 }; 45 46 struct rt5682_priv { 47 struct snd_soc_component *component; 48 struct rt5682_platform_data pdata; 49 struct regmap *regmap; 50 struct snd_soc_jack *hs_jack; 51 struct regulator_bulk_data supplies[RT5682_NUM_SUPPLIES]; 52 struct delayed_work jack_detect_work; 53 struct delayed_work jd_check_work; 54 struct mutex calibrate_mutex; 55 56 int sysclk; 57 int sysclk_src; 58 int lrck[RT5682_AIFS]; 59 int bclk[RT5682_AIFS]; 60 int master[RT5682_AIFS]; 61 62 int pll_src; 63 int pll_in; 64 int pll_out; 65 66 int jack_type; 67 }; 68 69 static const struct reg_sequence patch_list[] = { 70 {0x01c1, 0x1000}, 71 }; 72 73 static const struct reg_default rt5682_reg[] = { 74 {0x0002, 0x8080}, 75 {0x0003, 0x8000}, 76 {0x0005, 0x0000}, 77 {0x0006, 0x0000}, 78 {0x0008, 0x800f}, 79 {0x000b, 0x0000}, 80 {0x0010, 0x4040}, 81 {0x0011, 0x0000}, 82 {0x0012, 0x1404}, 83 {0x0013, 0x1000}, 84 {0x0014, 0xa00a}, 85 {0x0015, 0x0404}, 86 {0x0016, 0x0404}, 87 {0x0019, 0xafaf}, 88 {0x001c, 0x2f2f}, 89 {0x001f, 0x0000}, 90 {0x0022, 0x5757}, 91 {0x0023, 0x0039}, 92 {0x0024, 0x000b}, 93 {0x0026, 0xc0c4}, 94 {0x0029, 0x8080}, 95 {0x002a, 0xa0a0}, 96 {0x002b, 0x0300}, 97 {0x0030, 0x0000}, 98 {0x003c, 0x0080}, 99 {0x0044, 0x0c0c}, 100 {0x0049, 0x0000}, 101 {0x0061, 0x0000}, 102 {0x0062, 0x0000}, 103 {0x0063, 0x003f}, 104 {0x0064, 0x0000}, 105 {0x0065, 0x0000}, 106 {0x0066, 0x0030}, 107 {0x0067, 0x0000}, 108 {0x006b, 0x0000}, 109 {0x006c, 0x0000}, 110 {0x006d, 0x2200}, 111 {0x006e, 0x0a10}, 112 {0x0070, 0x8000}, 113 {0x0071, 0x8000}, 114 {0x0073, 0x0000}, 115 {0x0074, 0x0000}, 116 {0x0075, 0x0002}, 117 {0x0076, 0x0001}, 118 {0x0079, 0x0000}, 119 {0x007a, 0x0000}, 120 {0x007b, 0x0000}, 121 {0x007c, 0x0100}, 122 {0x007e, 0x0000}, 123 {0x0080, 0x0000}, 124 {0x0081, 0x0000}, 125 {0x0082, 0x0000}, 126 {0x0083, 0x0000}, 127 {0x0084, 0x0000}, 128 {0x0085, 0x0000}, 129 {0x0086, 0x0005}, 130 {0x0087, 0x0000}, 131 {0x0088, 0x0000}, 132 {0x008c, 0x0003}, 133 {0x008d, 0x0000}, 134 {0x008e, 0x0060}, 135 {0x008f, 0x1000}, 136 {0x0091, 0x0c26}, 137 {0x0092, 0x0073}, 138 {0x0093, 0x0000}, 139 {0x0094, 0x0080}, 140 {0x0098, 0x0000}, 141 {0x009a, 0x0000}, 142 {0x009b, 0x0000}, 143 {0x009c, 0x0000}, 144 {0x009d, 0x0000}, 145 {0x009e, 0x100c}, 146 {0x009f, 0x0000}, 147 {0x00a0, 0x0000}, 148 {0x00a3, 0x0002}, 149 {0x00a4, 0x0001}, 150 {0x00ae, 0x2040}, 151 {0x00af, 0x0000}, 152 {0x00b6, 0x0000}, 153 {0x00b7, 0x0000}, 154 {0x00b8, 0x0000}, 155 {0x00b9, 0x0002}, 156 {0x00be, 0x0000}, 157 {0x00c0, 0x0160}, 158 {0x00c1, 0x82a0}, 159 {0x00c2, 0x0000}, 160 {0x00d0, 0x0000}, 161 {0x00d1, 0x2244}, 162 {0x00d2, 0x3300}, 163 {0x00d3, 0x2200}, 164 {0x00d4, 0x0000}, 165 {0x00d9, 0x0009}, 166 {0x00da, 0x0000}, 167 {0x00db, 0x0000}, 168 {0x00dc, 0x00c0}, 169 {0x00dd, 0x2220}, 170 {0x00de, 0x3131}, 171 {0x00df, 0x3131}, 172 {0x00e0, 0x3131}, 173 {0x00e2, 0x0000}, 174 {0x00e3, 0x4000}, 175 {0x00e4, 0x0aa0}, 176 {0x00e5, 0x3131}, 177 {0x00e6, 0x3131}, 178 {0x00e7, 0x3131}, 179 {0x00e8, 0x3131}, 180 {0x00ea, 0xb320}, 181 {0x00eb, 0x0000}, 182 {0x00f0, 0x0000}, 183 {0x00f1, 0x00d0}, 184 {0x00f2, 0x00d0}, 185 {0x00f6, 0x0000}, 186 {0x00fa, 0x0000}, 187 {0x00fb, 0x0000}, 188 {0x00fc, 0x0000}, 189 {0x00fd, 0x0000}, 190 {0x00fe, 0x10ec}, 191 {0x00ff, 0x6530}, 192 {0x0100, 0xa0a0}, 193 {0x010b, 0x0000}, 194 {0x010c, 0xae00}, 195 {0x010d, 0xaaa0}, 196 {0x010e, 0x8aa2}, 197 {0x010f, 0x02a2}, 198 {0x0110, 0xc000}, 199 {0x0111, 0x04a2}, 200 {0x0112, 0x2800}, 201 {0x0113, 0x0000}, 202 {0x0117, 0x0100}, 203 {0x0125, 0x0410}, 204 {0x0132, 0x6026}, 205 {0x0136, 0x5555}, 206 {0x0138, 0x3700}, 207 {0x013a, 0x2000}, 208 {0x013b, 0x2000}, 209 {0x013c, 0x2005}, 210 {0x013f, 0x0000}, 211 {0x0142, 0x0000}, 212 {0x0145, 0x0002}, 213 {0x0146, 0x0000}, 214 {0x0147, 0x0000}, 215 {0x0148, 0x0000}, 216 {0x0149, 0x0000}, 217 {0x0150, 0x79a1}, 218 {0x0151, 0x0000}, 219 {0x0160, 0x4ec0}, 220 {0x0161, 0x0080}, 221 {0x0162, 0x0200}, 222 {0x0163, 0x0800}, 223 {0x0164, 0x0000}, 224 {0x0165, 0x0000}, 225 {0x0166, 0x0000}, 226 {0x0167, 0x000f}, 227 {0x0168, 0x000f}, 228 {0x0169, 0x0021}, 229 {0x0190, 0x413d}, 230 {0x0194, 0x0000}, 231 {0x0195, 0x0000}, 232 {0x0197, 0x0022}, 233 {0x0198, 0x0000}, 234 {0x0199, 0x0000}, 235 {0x01af, 0x0000}, 236 {0x01b0, 0x0400}, 237 {0x01b1, 0x0000}, 238 {0x01b2, 0x0000}, 239 {0x01b3, 0x0000}, 240 {0x01b4, 0x0000}, 241 {0x01b5, 0x0000}, 242 {0x01b6, 0x01c3}, 243 {0x01b7, 0x02a0}, 244 {0x01b8, 0x03e9}, 245 {0x01b9, 0x1389}, 246 {0x01ba, 0xc351}, 247 {0x01bb, 0x0009}, 248 {0x01bc, 0x0018}, 249 {0x01bd, 0x002a}, 250 {0x01be, 0x004c}, 251 {0x01bf, 0x0097}, 252 {0x01c0, 0x433d}, 253 {0x01c2, 0x0000}, 254 {0x01c3, 0x0000}, 255 {0x01c4, 0x0000}, 256 {0x01c5, 0x0000}, 257 {0x01c6, 0x0000}, 258 {0x01c7, 0x0000}, 259 {0x01c8, 0x40af}, 260 {0x01c9, 0x0702}, 261 {0x01ca, 0x0000}, 262 {0x01cb, 0x0000}, 263 {0x01cc, 0x5757}, 264 {0x01cd, 0x5757}, 265 {0x01ce, 0x5757}, 266 {0x01cf, 0x5757}, 267 {0x01d0, 0x5757}, 268 {0x01d1, 0x5757}, 269 {0x01d2, 0x5757}, 270 {0x01d3, 0x5757}, 271 {0x01d4, 0x5757}, 272 {0x01d5, 0x5757}, 273 {0x01d6, 0x0000}, 274 {0x01d7, 0x0008}, 275 {0x01d8, 0x0029}, 276 {0x01d9, 0x3333}, 277 {0x01da, 0x0000}, 278 {0x01db, 0x0004}, 279 {0x01dc, 0x0000}, 280 {0x01de, 0x7c00}, 281 {0x01df, 0x0320}, 282 {0x01e0, 0x06a1}, 283 {0x01e1, 0x0000}, 284 {0x01e2, 0x0000}, 285 {0x01e3, 0x0000}, 286 {0x01e4, 0x0000}, 287 {0x01e6, 0x0001}, 288 {0x01e7, 0x0000}, 289 {0x01e8, 0x0000}, 290 {0x01ea, 0x0000}, 291 {0x01eb, 0x0000}, 292 {0x01ec, 0x0000}, 293 {0x01ed, 0x0000}, 294 {0x01ee, 0x0000}, 295 {0x01ef, 0x0000}, 296 {0x01f0, 0x0000}, 297 {0x01f1, 0x0000}, 298 {0x01f2, 0x0000}, 299 {0x01f3, 0x0000}, 300 {0x01f4, 0x0000}, 301 {0x0210, 0x6297}, 302 {0x0211, 0xa005}, 303 {0x0212, 0x824c}, 304 {0x0213, 0xf7ff}, 305 {0x0214, 0xf24c}, 306 {0x0215, 0x0102}, 307 {0x0216, 0x00a3}, 308 {0x0217, 0x0048}, 309 {0x0218, 0xa2c0}, 310 {0x0219, 0x0400}, 311 {0x021a, 0x00c8}, 312 {0x021b, 0x00c0}, 313 {0x021c, 0x0000}, 314 {0x0250, 0x4500}, 315 {0x0251, 0x40b3}, 316 {0x0252, 0x0000}, 317 {0x0253, 0x0000}, 318 {0x0254, 0x0000}, 319 {0x0255, 0x0000}, 320 {0x0256, 0x0000}, 321 {0x0257, 0x0000}, 322 {0x0258, 0x0000}, 323 {0x0259, 0x0000}, 324 {0x025a, 0x0005}, 325 {0x0270, 0x0000}, 326 {0x02ff, 0x0110}, 327 {0x0300, 0x001f}, 328 {0x0301, 0x032c}, 329 {0x0302, 0x5f21}, 330 {0x0303, 0x4000}, 331 {0x0304, 0x4000}, 332 {0x0305, 0x06d5}, 333 {0x0306, 0x8000}, 334 {0x0307, 0x0700}, 335 {0x0310, 0x4560}, 336 {0x0311, 0xa4a8}, 337 {0x0312, 0x7418}, 338 {0x0313, 0x0000}, 339 {0x0314, 0x0006}, 340 {0x0315, 0xffff}, 341 {0x0316, 0xc400}, 342 {0x0317, 0x0000}, 343 {0x03c0, 0x7e00}, 344 {0x03c1, 0x8000}, 345 {0x03c2, 0x8000}, 346 {0x03c3, 0x8000}, 347 {0x03c4, 0x8000}, 348 {0x03c5, 0x8000}, 349 {0x03c6, 0x8000}, 350 {0x03c7, 0x8000}, 351 {0x03c8, 0x8000}, 352 {0x03c9, 0x8000}, 353 {0x03ca, 0x8000}, 354 {0x03cb, 0x8000}, 355 {0x03cc, 0x8000}, 356 {0x03d0, 0x0000}, 357 {0x03d1, 0x0000}, 358 {0x03d2, 0x0000}, 359 {0x03d3, 0x0000}, 360 {0x03d4, 0x2000}, 361 {0x03d5, 0x2000}, 362 {0x03d6, 0x0000}, 363 {0x03d7, 0x0000}, 364 {0x03d8, 0x2000}, 365 {0x03d9, 0x2000}, 366 {0x03da, 0x2000}, 367 {0x03db, 0x2000}, 368 {0x03dc, 0x0000}, 369 {0x03dd, 0x0000}, 370 {0x03de, 0x0000}, 371 {0x03df, 0x2000}, 372 {0x03e0, 0x0000}, 373 {0x03e1, 0x0000}, 374 {0x03e2, 0x0000}, 375 {0x03e3, 0x0000}, 376 {0x03e4, 0x0000}, 377 {0x03e5, 0x0000}, 378 {0x03e6, 0x0000}, 379 {0x03e7, 0x0000}, 380 {0x03e8, 0x0000}, 381 {0x03e9, 0x0000}, 382 {0x03ea, 0x0000}, 383 {0x03eb, 0x0000}, 384 {0x03ec, 0x0000}, 385 {0x03ed, 0x0000}, 386 {0x03ee, 0x0000}, 387 {0x03ef, 0x0000}, 388 {0x03f0, 0x0800}, 389 {0x03f1, 0x0800}, 390 {0x03f2, 0x0800}, 391 {0x03f3, 0x0800}, 392 }; 393 394 static bool rt5682_volatile_register(struct device *dev, unsigned int reg) 395 { 396 switch (reg) { 397 case RT5682_RESET: 398 case RT5682_CBJ_CTRL_2: 399 case RT5682_INT_ST_1: 400 case RT5682_4BTN_IL_CMD_1: 401 case RT5682_AJD1_CTRL: 402 case RT5682_HP_CALIB_CTRL_1: 403 case RT5682_DEVICE_ID: 404 case RT5682_I2C_MODE: 405 case RT5682_HP_CALIB_CTRL_10: 406 case RT5682_EFUSE_CTRL_2: 407 case RT5682_JD_TOP_VC_VTRL: 408 case RT5682_HP_IMP_SENS_CTRL_19: 409 case RT5682_IL_CMD_1: 410 case RT5682_SAR_IL_CMD_2: 411 case RT5682_SAR_IL_CMD_4: 412 case RT5682_SAR_IL_CMD_10: 413 case RT5682_SAR_IL_CMD_11: 414 case RT5682_EFUSE_CTRL_6...RT5682_EFUSE_CTRL_11: 415 case RT5682_HP_CALIB_STA_1...RT5682_HP_CALIB_STA_11: 416 return true; 417 default: 418 return false; 419 } 420 } 421 422 static bool rt5682_readable_register(struct device *dev, unsigned int reg) 423 { 424 switch (reg) { 425 case RT5682_RESET: 426 case RT5682_VERSION_ID: 427 case RT5682_VENDOR_ID: 428 case RT5682_DEVICE_ID: 429 case RT5682_HP_CTRL_1: 430 case RT5682_HP_CTRL_2: 431 case RT5682_HPL_GAIN: 432 case RT5682_HPR_GAIN: 433 case RT5682_I2C_CTRL: 434 case RT5682_CBJ_BST_CTRL: 435 case RT5682_CBJ_CTRL_1: 436 case RT5682_CBJ_CTRL_2: 437 case RT5682_CBJ_CTRL_3: 438 case RT5682_CBJ_CTRL_4: 439 case RT5682_CBJ_CTRL_5: 440 case RT5682_CBJ_CTRL_6: 441 case RT5682_CBJ_CTRL_7: 442 case RT5682_DAC1_DIG_VOL: 443 case RT5682_STO1_ADC_DIG_VOL: 444 case RT5682_STO1_ADC_BOOST: 445 case RT5682_HP_IMP_GAIN_1: 446 case RT5682_HP_IMP_GAIN_2: 447 case RT5682_SIDETONE_CTRL: 448 case RT5682_STO1_ADC_MIXER: 449 case RT5682_AD_DA_MIXER: 450 case RT5682_STO1_DAC_MIXER: 451 case RT5682_A_DAC1_MUX: 452 case RT5682_DIG_INF2_DATA: 453 case RT5682_REC_MIXER: 454 case RT5682_CAL_REC: 455 case RT5682_ALC_BACK_GAIN: 456 case RT5682_PWR_DIG_1: 457 case RT5682_PWR_DIG_2: 458 case RT5682_PWR_ANLG_1: 459 case RT5682_PWR_ANLG_2: 460 case RT5682_PWR_ANLG_3: 461 case RT5682_PWR_MIXER: 462 case RT5682_PWR_VOL: 463 case RT5682_CLK_DET: 464 case RT5682_RESET_LPF_CTRL: 465 case RT5682_RESET_HPF_CTRL: 466 case RT5682_DMIC_CTRL_1: 467 case RT5682_I2S1_SDP: 468 case RT5682_I2S2_SDP: 469 case RT5682_ADDA_CLK_1: 470 case RT5682_ADDA_CLK_2: 471 case RT5682_I2S1_F_DIV_CTRL_1: 472 case RT5682_I2S1_F_DIV_CTRL_2: 473 case RT5682_TDM_CTRL: 474 case RT5682_TDM_ADDA_CTRL_1: 475 case RT5682_TDM_ADDA_CTRL_2: 476 case RT5682_DATA_SEL_CTRL_1: 477 case RT5682_TDM_TCON_CTRL: 478 case RT5682_GLB_CLK: 479 case RT5682_PLL_CTRL_1: 480 case RT5682_PLL_CTRL_2: 481 case RT5682_PLL_TRACK_1: 482 case RT5682_PLL_TRACK_2: 483 case RT5682_PLL_TRACK_3: 484 case RT5682_PLL_TRACK_4: 485 case RT5682_PLL_TRACK_5: 486 case RT5682_PLL_TRACK_6: 487 case RT5682_PLL_TRACK_11: 488 case RT5682_SDW_REF_CLK: 489 case RT5682_DEPOP_1: 490 case RT5682_DEPOP_2: 491 case RT5682_HP_CHARGE_PUMP_1: 492 case RT5682_HP_CHARGE_PUMP_2: 493 case RT5682_MICBIAS_1: 494 case RT5682_MICBIAS_2: 495 case RT5682_PLL_TRACK_12: 496 case RT5682_PLL_TRACK_14: 497 case RT5682_PLL2_CTRL_1: 498 case RT5682_PLL2_CTRL_2: 499 case RT5682_PLL2_CTRL_3: 500 case RT5682_PLL2_CTRL_4: 501 case RT5682_RC_CLK_CTRL: 502 case RT5682_I2S_M_CLK_CTRL_1: 503 case RT5682_I2S2_F_DIV_CTRL_1: 504 case RT5682_I2S2_F_DIV_CTRL_2: 505 case RT5682_EQ_CTRL_1: 506 case RT5682_EQ_CTRL_2: 507 case RT5682_IRQ_CTRL_1: 508 case RT5682_IRQ_CTRL_2: 509 case RT5682_IRQ_CTRL_3: 510 case RT5682_IRQ_CTRL_4: 511 case RT5682_INT_ST_1: 512 case RT5682_GPIO_CTRL_1: 513 case RT5682_GPIO_CTRL_2: 514 case RT5682_GPIO_CTRL_3: 515 case RT5682_HP_AMP_DET_CTRL_1: 516 case RT5682_HP_AMP_DET_CTRL_2: 517 case RT5682_MID_HP_AMP_DET: 518 case RT5682_LOW_HP_AMP_DET: 519 case RT5682_DELAY_BUF_CTRL: 520 case RT5682_SV_ZCD_1: 521 case RT5682_SV_ZCD_2: 522 case RT5682_IL_CMD_1: 523 case RT5682_IL_CMD_2: 524 case RT5682_IL_CMD_3: 525 case RT5682_IL_CMD_4: 526 case RT5682_IL_CMD_5: 527 case RT5682_IL_CMD_6: 528 case RT5682_4BTN_IL_CMD_1: 529 case RT5682_4BTN_IL_CMD_2: 530 case RT5682_4BTN_IL_CMD_3: 531 case RT5682_4BTN_IL_CMD_4: 532 case RT5682_4BTN_IL_CMD_5: 533 case RT5682_4BTN_IL_CMD_6: 534 case RT5682_4BTN_IL_CMD_7: 535 case RT5682_ADC_STO1_HP_CTRL_1: 536 case RT5682_ADC_STO1_HP_CTRL_2: 537 case RT5682_AJD1_CTRL: 538 case RT5682_JD1_THD: 539 case RT5682_JD2_THD: 540 case RT5682_JD_CTRL_1: 541 case RT5682_DUMMY_1: 542 case RT5682_DUMMY_2: 543 case RT5682_DUMMY_3: 544 case RT5682_DAC_ADC_DIG_VOL1: 545 case RT5682_BIAS_CUR_CTRL_2: 546 case RT5682_BIAS_CUR_CTRL_3: 547 case RT5682_BIAS_CUR_CTRL_4: 548 case RT5682_BIAS_CUR_CTRL_5: 549 case RT5682_BIAS_CUR_CTRL_6: 550 case RT5682_BIAS_CUR_CTRL_7: 551 case RT5682_BIAS_CUR_CTRL_8: 552 case RT5682_BIAS_CUR_CTRL_9: 553 case RT5682_BIAS_CUR_CTRL_10: 554 case RT5682_VREF_REC_OP_FB_CAP_CTRL: 555 case RT5682_CHARGE_PUMP_1: 556 case RT5682_DIG_IN_CTRL_1: 557 case RT5682_PAD_DRIVING_CTRL: 558 case RT5682_SOFT_RAMP_DEPOP: 559 case RT5682_CHOP_DAC: 560 case RT5682_CHOP_ADC: 561 case RT5682_CALIB_ADC_CTRL: 562 case RT5682_VOL_TEST: 563 case RT5682_SPKVDD_DET_STA: 564 case RT5682_TEST_MODE_CTRL_1: 565 case RT5682_TEST_MODE_CTRL_2: 566 case RT5682_TEST_MODE_CTRL_3: 567 case RT5682_TEST_MODE_CTRL_4: 568 case RT5682_TEST_MODE_CTRL_5: 569 case RT5682_PLL1_INTERNAL: 570 case RT5682_PLL2_INTERNAL: 571 case RT5682_STO_NG2_CTRL_1: 572 case RT5682_STO_NG2_CTRL_2: 573 case RT5682_STO_NG2_CTRL_3: 574 case RT5682_STO_NG2_CTRL_4: 575 case RT5682_STO_NG2_CTRL_5: 576 case RT5682_STO_NG2_CTRL_6: 577 case RT5682_STO_NG2_CTRL_7: 578 case RT5682_STO_NG2_CTRL_8: 579 case RT5682_STO_NG2_CTRL_9: 580 case RT5682_STO_NG2_CTRL_10: 581 case RT5682_STO1_DAC_SIL_DET: 582 case RT5682_SIL_PSV_CTRL1: 583 case RT5682_SIL_PSV_CTRL2: 584 case RT5682_SIL_PSV_CTRL3: 585 case RT5682_SIL_PSV_CTRL4: 586 case RT5682_SIL_PSV_CTRL5: 587 case RT5682_HP_IMP_SENS_CTRL_01: 588 case RT5682_HP_IMP_SENS_CTRL_02: 589 case RT5682_HP_IMP_SENS_CTRL_03: 590 case RT5682_HP_IMP_SENS_CTRL_04: 591 case RT5682_HP_IMP_SENS_CTRL_05: 592 case RT5682_HP_IMP_SENS_CTRL_06: 593 case RT5682_HP_IMP_SENS_CTRL_07: 594 case RT5682_HP_IMP_SENS_CTRL_08: 595 case RT5682_HP_IMP_SENS_CTRL_09: 596 case RT5682_HP_IMP_SENS_CTRL_10: 597 case RT5682_HP_IMP_SENS_CTRL_11: 598 case RT5682_HP_IMP_SENS_CTRL_12: 599 case RT5682_HP_IMP_SENS_CTRL_13: 600 case RT5682_HP_IMP_SENS_CTRL_14: 601 case RT5682_HP_IMP_SENS_CTRL_15: 602 case RT5682_HP_IMP_SENS_CTRL_16: 603 case RT5682_HP_IMP_SENS_CTRL_17: 604 case RT5682_HP_IMP_SENS_CTRL_18: 605 case RT5682_HP_IMP_SENS_CTRL_19: 606 case RT5682_HP_IMP_SENS_CTRL_20: 607 case RT5682_HP_IMP_SENS_CTRL_21: 608 case RT5682_HP_IMP_SENS_CTRL_22: 609 case RT5682_HP_IMP_SENS_CTRL_23: 610 case RT5682_HP_IMP_SENS_CTRL_24: 611 case RT5682_HP_IMP_SENS_CTRL_25: 612 case RT5682_HP_IMP_SENS_CTRL_26: 613 case RT5682_HP_IMP_SENS_CTRL_27: 614 case RT5682_HP_IMP_SENS_CTRL_28: 615 case RT5682_HP_IMP_SENS_CTRL_29: 616 case RT5682_HP_IMP_SENS_CTRL_30: 617 case RT5682_HP_IMP_SENS_CTRL_31: 618 case RT5682_HP_IMP_SENS_CTRL_32: 619 case RT5682_HP_IMP_SENS_CTRL_33: 620 case RT5682_HP_IMP_SENS_CTRL_34: 621 case RT5682_HP_IMP_SENS_CTRL_35: 622 case RT5682_HP_IMP_SENS_CTRL_36: 623 case RT5682_HP_IMP_SENS_CTRL_37: 624 case RT5682_HP_IMP_SENS_CTRL_38: 625 case RT5682_HP_IMP_SENS_CTRL_39: 626 case RT5682_HP_IMP_SENS_CTRL_40: 627 case RT5682_HP_IMP_SENS_CTRL_41: 628 case RT5682_HP_IMP_SENS_CTRL_42: 629 case RT5682_HP_IMP_SENS_CTRL_43: 630 case RT5682_HP_LOGIC_CTRL_1: 631 case RT5682_HP_LOGIC_CTRL_2: 632 case RT5682_HP_LOGIC_CTRL_3: 633 case RT5682_HP_CALIB_CTRL_1: 634 case RT5682_HP_CALIB_CTRL_2: 635 case RT5682_HP_CALIB_CTRL_3: 636 case RT5682_HP_CALIB_CTRL_4: 637 case RT5682_HP_CALIB_CTRL_5: 638 case RT5682_HP_CALIB_CTRL_6: 639 case RT5682_HP_CALIB_CTRL_7: 640 case RT5682_HP_CALIB_CTRL_9: 641 case RT5682_HP_CALIB_CTRL_10: 642 case RT5682_HP_CALIB_CTRL_11: 643 case RT5682_HP_CALIB_STA_1: 644 case RT5682_HP_CALIB_STA_2: 645 case RT5682_HP_CALIB_STA_3: 646 case RT5682_HP_CALIB_STA_4: 647 case RT5682_HP_CALIB_STA_5: 648 case RT5682_HP_CALIB_STA_6: 649 case RT5682_HP_CALIB_STA_7: 650 case RT5682_HP_CALIB_STA_8: 651 case RT5682_HP_CALIB_STA_9: 652 case RT5682_HP_CALIB_STA_10: 653 case RT5682_HP_CALIB_STA_11: 654 case RT5682_SAR_IL_CMD_1: 655 case RT5682_SAR_IL_CMD_2: 656 case RT5682_SAR_IL_CMD_3: 657 case RT5682_SAR_IL_CMD_4: 658 case RT5682_SAR_IL_CMD_5: 659 case RT5682_SAR_IL_CMD_6: 660 case RT5682_SAR_IL_CMD_7: 661 case RT5682_SAR_IL_CMD_8: 662 case RT5682_SAR_IL_CMD_9: 663 case RT5682_SAR_IL_CMD_10: 664 case RT5682_SAR_IL_CMD_11: 665 case RT5682_SAR_IL_CMD_12: 666 case RT5682_SAR_IL_CMD_13: 667 case RT5682_EFUSE_CTRL_1: 668 case RT5682_EFUSE_CTRL_2: 669 case RT5682_EFUSE_CTRL_3: 670 case RT5682_EFUSE_CTRL_4: 671 case RT5682_EFUSE_CTRL_5: 672 case RT5682_EFUSE_CTRL_6: 673 case RT5682_EFUSE_CTRL_7: 674 case RT5682_EFUSE_CTRL_8: 675 case RT5682_EFUSE_CTRL_9: 676 case RT5682_EFUSE_CTRL_10: 677 case RT5682_EFUSE_CTRL_11: 678 case RT5682_JD_TOP_VC_VTRL: 679 case RT5682_DRC1_CTRL_0: 680 case RT5682_DRC1_CTRL_1: 681 case RT5682_DRC1_CTRL_2: 682 case RT5682_DRC1_CTRL_3: 683 case RT5682_DRC1_CTRL_4: 684 case RT5682_DRC1_CTRL_5: 685 case RT5682_DRC1_CTRL_6: 686 case RT5682_DRC1_HARD_LMT_CTRL_1: 687 case RT5682_DRC1_HARD_LMT_CTRL_2: 688 case RT5682_DRC1_PRIV_1: 689 case RT5682_DRC1_PRIV_2: 690 case RT5682_DRC1_PRIV_3: 691 case RT5682_DRC1_PRIV_4: 692 case RT5682_DRC1_PRIV_5: 693 case RT5682_DRC1_PRIV_6: 694 case RT5682_DRC1_PRIV_7: 695 case RT5682_DRC1_PRIV_8: 696 case RT5682_EQ_AUTO_RCV_CTRL1: 697 case RT5682_EQ_AUTO_RCV_CTRL2: 698 case RT5682_EQ_AUTO_RCV_CTRL3: 699 case RT5682_EQ_AUTO_RCV_CTRL4: 700 case RT5682_EQ_AUTO_RCV_CTRL5: 701 case RT5682_EQ_AUTO_RCV_CTRL6: 702 case RT5682_EQ_AUTO_RCV_CTRL7: 703 case RT5682_EQ_AUTO_RCV_CTRL8: 704 case RT5682_EQ_AUTO_RCV_CTRL9: 705 case RT5682_EQ_AUTO_RCV_CTRL10: 706 case RT5682_EQ_AUTO_RCV_CTRL11: 707 case RT5682_EQ_AUTO_RCV_CTRL12: 708 case RT5682_EQ_AUTO_RCV_CTRL13: 709 case RT5682_ADC_L_EQ_LPF1_A1: 710 case RT5682_R_EQ_LPF1_A1: 711 case RT5682_L_EQ_LPF1_H0: 712 case RT5682_R_EQ_LPF1_H0: 713 case RT5682_L_EQ_BPF1_A1: 714 case RT5682_R_EQ_BPF1_A1: 715 case RT5682_L_EQ_BPF1_A2: 716 case RT5682_R_EQ_BPF1_A2: 717 case RT5682_L_EQ_BPF1_H0: 718 case RT5682_R_EQ_BPF1_H0: 719 case RT5682_L_EQ_BPF2_A1: 720 case RT5682_R_EQ_BPF2_A1: 721 case RT5682_L_EQ_BPF2_A2: 722 case RT5682_R_EQ_BPF2_A2: 723 case RT5682_L_EQ_BPF2_H0: 724 case RT5682_R_EQ_BPF2_H0: 725 case RT5682_L_EQ_BPF3_A1: 726 case RT5682_R_EQ_BPF3_A1: 727 case RT5682_L_EQ_BPF3_A2: 728 case RT5682_R_EQ_BPF3_A2: 729 case RT5682_L_EQ_BPF3_H0: 730 case RT5682_R_EQ_BPF3_H0: 731 case RT5682_L_EQ_BPF4_A1: 732 case RT5682_R_EQ_BPF4_A1: 733 case RT5682_L_EQ_BPF4_A2: 734 case RT5682_R_EQ_BPF4_A2: 735 case RT5682_L_EQ_BPF4_H0: 736 case RT5682_R_EQ_BPF4_H0: 737 case RT5682_L_EQ_HPF1_A1: 738 case RT5682_R_EQ_HPF1_A1: 739 case RT5682_L_EQ_HPF1_H0: 740 case RT5682_R_EQ_HPF1_H0: 741 case RT5682_L_EQ_PRE_VOL: 742 case RT5682_R_EQ_PRE_VOL: 743 case RT5682_L_EQ_POST_VOL: 744 case RT5682_R_EQ_POST_VOL: 745 case RT5682_I2C_MODE: 746 return true; 747 default: 748 return false; 749 } 750 } 751 752 static const DECLARE_TLV_DB_SCALE(hp_vol_tlv, -2250, 150, 0); 753 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -65625, 375, 0); 754 static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -17625, 375, 0); 755 static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0); 756 757 /* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */ 758 static const DECLARE_TLV_DB_RANGE(bst_tlv, 759 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0), 760 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0), 761 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0), 762 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0), 763 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0), 764 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0), 765 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0) 766 ); 767 768 /* Interface data select */ 769 static const char * const rt5682_data_select[] = { 770 "L/R", "R/L", "L/L", "R/R" 771 }; 772 773 static SOC_ENUM_SINGLE_DECL(rt5682_if2_adc_enum, 774 RT5682_DIG_INF2_DATA, RT5682_IF2_ADC_SEL_SFT, rt5682_data_select); 775 776 static SOC_ENUM_SINGLE_DECL(rt5682_if1_01_adc_enum, 777 RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC1_SEL_SFT, rt5682_data_select); 778 779 static SOC_ENUM_SINGLE_DECL(rt5682_if1_23_adc_enum, 780 RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC2_SEL_SFT, rt5682_data_select); 781 782 static SOC_ENUM_SINGLE_DECL(rt5682_if1_45_adc_enum, 783 RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC3_SEL_SFT, rt5682_data_select); 784 785 static SOC_ENUM_SINGLE_DECL(rt5682_if1_67_adc_enum, 786 RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC4_SEL_SFT, rt5682_data_select); 787 788 static const struct snd_kcontrol_new rt5682_if2_adc_swap_mux = 789 SOC_DAPM_ENUM("IF2 ADC Swap Mux", rt5682_if2_adc_enum); 790 791 static const struct snd_kcontrol_new rt5682_if1_01_adc_swap_mux = 792 SOC_DAPM_ENUM("IF1 01 ADC Swap Mux", rt5682_if1_01_adc_enum); 793 794 static const struct snd_kcontrol_new rt5682_if1_23_adc_swap_mux = 795 SOC_DAPM_ENUM("IF1 23 ADC Swap Mux", rt5682_if1_23_adc_enum); 796 797 static const struct snd_kcontrol_new rt5682_if1_45_adc_swap_mux = 798 SOC_DAPM_ENUM("IF1 45 ADC Swap Mux", rt5682_if1_45_adc_enum); 799 800 static const struct snd_kcontrol_new rt5682_if1_67_adc_swap_mux = 801 SOC_DAPM_ENUM("IF1 67 ADC Swap Mux", rt5682_if1_67_adc_enum); 802 803 static void rt5682_reset(struct regmap *regmap) 804 { 805 regmap_write(regmap, RT5682_RESET, 0); 806 regmap_write(regmap, RT5682_I2C_MODE, 1); 807 } 808 /** 809 * rt5682_sel_asrc_clk_src - select ASRC clock source for a set of filters 810 * @component: SoC audio component device. 811 * @filter_mask: mask of filters. 812 * @clk_src: clock source 813 * 814 * The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5682 can 815 * only support standard 32fs or 64fs i2s format, ASRC should be enabled to 816 * support special i2s clock format such as Intel's 100fs(100 * sampling rate). 817 * ASRC function will track i2s clock and generate a corresponding system clock 818 * for codec. This function provides an API to select the clock source for a 819 * set of filters specified by the mask. And the component driver will turn on 820 * ASRC for these filters if ASRC is selected as their clock source. 821 */ 822 int rt5682_sel_asrc_clk_src(struct snd_soc_component *component, 823 unsigned int filter_mask, unsigned int clk_src) 824 { 825 826 switch (clk_src) { 827 case RT5682_CLK_SEL_SYS: 828 case RT5682_CLK_SEL_I2S1_ASRC: 829 case RT5682_CLK_SEL_I2S2_ASRC: 830 break; 831 832 default: 833 return -EINVAL; 834 } 835 836 if (filter_mask & RT5682_DA_STEREO1_FILTER) { 837 snd_soc_component_update_bits(component, RT5682_PLL_TRACK_2, 838 RT5682_FILTER_CLK_SEL_MASK, 839 clk_src << RT5682_FILTER_CLK_SEL_SFT); 840 } 841 842 if (filter_mask & RT5682_AD_STEREO1_FILTER) { 843 snd_soc_component_update_bits(component, RT5682_PLL_TRACK_3, 844 RT5682_FILTER_CLK_SEL_MASK, 845 clk_src << RT5682_FILTER_CLK_SEL_SFT); 846 } 847 848 return 0; 849 } 850 EXPORT_SYMBOL_GPL(rt5682_sel_asrc_clk_src); 851 852 static int rt5682_button_detect(struct snd_soc_component *component) 853 { 854 int btn_type, val; 855 856 val = snd_soc_component_read32(component, RT5682_4BTN_IL_CMD_1); 857 btn_type = val & 0xfff0; 858 snd_soc_component_write(component, RT5682_4BTN_IL_CMD_1, val); 859 pr_debug("%s btn_type=%x\n", __func__, btn_type); 860 snd_soc_component_update_bits(component, 861 RT5682_SAR_IL_CMD_2, 0x10, 0x10); 862 863 return btn_type; 864 } 865 866 static void rt5682_enable_push_button_irq(struct snd_soc_component *component, 867 bool enable) 868 { 869 if (enable) { 870 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1, 871 RT5682_SAR_BUTT_DET_MASK, RT5682_SAR_BUTT_DET_EN); 872 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_13, 873 RT5682_SAR_SOUR_MASK, RT5682_SAR_SOUR_BTN); 874 snd_soc_component_write(component, RT5682_IL_CMD_1, 0x0040); 875 snd_soc_component_update_bits(component, RT5682_4BTN_IL_CMD_2, 876 RT5682_4BTN_IL_MASK | RT5682_4BTN_IL_RST_MASK, 877 RT5682_4BTN_IL_EN | RT5682_4BTN_IL_NOR); 878 snd_soc_component_update_bits(component, RT5682_IRQ_CTRL_3, 879 RT5682_IL_IRQ_MASK, RT5682_IL_IRQ_EN); 880 } else { 881 snd_soc_component_update_bits(component, RT5682_IRQ_CTRL_3, 882 RT5682_IL_IRQ_MASK, RT5682_IL_IRQ_DIS); 883 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1, 884 RT5682_SAR_BUTT_DET_MASK, RT5682_SAR_BUTT_DET_DIS); 885 snd_soc_component_update_bits(component, RT5682_4BTN_IL_CMD_2, 886 RT5682_4BTN_IL_MASK, RT5682_4BTN_IL_DIS); 887 snd_soc_component_update_bits(component, RT5682_4BTN_IL_CMD_2, 888 RT5682_4BTN_IL_RST_MASK, RT5682_4BTN_IL_RST); 889 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_13, 890 RT5682_SAR_SOUR_MASK, RT5682_SAR_SOUR_TYPE); 891 } 892 } 893 894 /** 895 * rt5682_headset_detect - Detect headset. 896 * @component: SoC audio component device. 897 * @jack_insert: Jack insert or not. 898 * 899 * Detect whether is headset or not when jack inserted. 900 * 901 * Returns detect status. 902 */ 903 static int rt5682_headset_detect(struct snd_soc_component *component, 904 int jack_insert) 905 { 906 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 907 struct snd_soc_dapm_context *dapm = 908 snd_soc_component_get_dapm(component); 909 unsigned int val, count; 910 911 if (jack_insert) { 912 snd_soc_dapm_force_enable_pin(dapm, "CBJ Power"); 913 snd_soc_dapm_sync(dapm); 914 snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1, 915 RT5682_TRIG_JD_MASK, RT5682_TRIG_JD_HIGH); 916 917 count = 0; 918 val = snd_soc_component_read32(component, RT5682_CBJ_CTRL_2) 919 & RT5682_JACK_TYPE_MASK; 920 while (val == 0 && count < 50) { 921 usleep_range(10000, 15000); 922 val = snd_soc_component_read32(component, 923 RT5682_CBJ_CTRL_2) & RT5682_JACK_TYPE_MASK; 924 count++; 925 } 926 927 switch (val) { 928 case 0x1: 929 case 0x2: 930 rt5682->jack_type = SND_JACK_HEADSET; 931 rt5682_enable_push_button_irq(component, true); 932 break; 933 default: 934 rt5682->jack_type = SND_JACK_HEADPHONE; 935 } 936 937 } else { 938 rt5682_enable_push_button_irq(component, false); 939 snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1, 940 RT5682_TRIG_JD_MASK, RT5682_TRIG_JD_LOW); 941 snd_soc_dapm_disable_pin(dapm, "CBJ Power"); 942 snd_soc_dapm_sync(dapm); 943 944 rt5682->jack_type = 0; 945 } 946 947 dev_dbg(component->dev, "jack_type = %d\n", rt5682->jack_type); 948 return rt5682->jack_type; 949 } 950 951 static irqreturn_t rt5682_irq(int irq, void *data) 952 { 953 struct rt5682_priv *rt5682 = data; 954 955 mod_delayed_work(system_power_efficient_wq, 956 &rt5682->jack_detect_work, msecs_to_jiffies(250)); 957 958 return IRQ_HANDLED; 959 } 960 961 static void rt5682_jd_check_handler(struct work_struct *work) 962 { 963 struct rt5682_priv *rt5682 = container_of(work, struct rt5682_priv, 964 jd_check_work.work); 965 966 if (snd_soc_component_read32(rt5682->component, RT5682_AJD1_CTRL) 967 & RT5682_JDH_RS_MASK) { 968 /* jack out */ 969 rt5682->jack_type = rt5682_headset_detect(rt5682->component, 0); 970 971 snd_soc_jack_report(rt5682->hs_jack, rt5682->jack_type, 972 SND_JACK_HEADSET | 973 SND_JACK_BTN_0 | SND_JACK_BTN_1 | 974 SND_JACK_BTN_2 | SND_JACK_BTN_3); 975 } else { 976 schedule_delayed_work(&rt5682->jd_check_work, 500); 977 } 978 } 979 980 static int rt5682_set_jack_detect(struct snd_soc_component *component, 981 struct snd_soc_jack *hs_jack, void *data) 982 { 983 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 984 985 switch (rt5682->pdata.jd_src) { 986 case RT5682_JD1: 987 snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_2, 988 RT5682_EXT_JD_SRC, RT5682_EXT_JD_SRC_MANUAL); 989 snd_soc_component_write(component, RT5682_CBJ_CTRL_1, 0xd042); 990 snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_3, 991 RT5682_CBJ_IN_BUF_EN, RT5682_CBJ_IN_BUF_EN); 992 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1, 993 RT5682_SAR_POW_MASK, RT5682_SAR_POW_EN); 994 regmap_update_bits(rt5682->regmap, RT5682_GPIO_CTRL_1, 995 RT5682_GP1_PIN_MASK, RT5682_GP1_PIN_IRQ); 996 regmap_update_bits(rt5682->regmap, RT5682_RC_CLK_CTRL, 997 RT5682_POW_IRQ | RT5682_POW_JDH | 998 RT5682_POW_ANA, RT5682_POW_IRQ | 999 RT5682_POW_JDH | RT5682_POW_ANA); 1000 regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_2, 1001 RT5682_PWR_JDH | RT5682_PWR_JDL, 1002 RT5682_PWR_JDH | RT5682_PWR_JDL); 1003 regmap_update_bits(rt5682->regmap, RT5682_IRQ_CTRL_2, 1004 RT5682_JD1_EN_MASK | RT5682_JD1_POL_MASK, 1005 RT5682_JD1_EN | RT5682_JD1_POL_NOR); 1006 mod_delayed_work(system_power_efficient_wq, 1007 &rt5682->jack_detect_work, msecs_to_jiffies(250)); 1008 break; 1009 1010 case RT5682_JD_NULL: 1011 regmap_update_bits(rt5682->regmap, RT5682_IRQ_CTRL_2, 1012 RT5682_JD1_EN_MASK, RT5682_JD1_DIS); 1013 regmap_update_bits(rt5682->regmap, RT5682_RC_CLK_CTRL, 1014 RT5682_POW_JDH | RT5682_POW_JDL, 0); 1015 break; 1016 1017 default: 1018 dev_warn(component->dev, "Wrong JD source\n"); 1019 break; 1020 } 1021 1022 rt5682->hs_jack = hs_jack; 1023 1024 return 0; 1025 } 1026 1027 static void rt5682_jack_detect_handler(struct work_struct *work) 1028 { 1029 struct rt5682_priv *rt5682 = 1030 container_of(work, struct rt5682_priv, jack_detect_work.work); 1031 int val, btn_type; 1032 1033 while (!rt5682->component) 1034 usleep_range(10000, 15000); 1035 1036 while (!rt5682->component->card->instantiated) 1037 usleep_range(10000, 15000); 1038 1039 mutex_lock(&rt5682->calibrate_mutex); 1040 1041 val = snd_soc_component_read32(rt5682->component, RT5682_AJD1_CTRL) 1042 & RT5682_JDH_RS_MASK; 1043 if (!val) { 1044 /* jack in */ 1045 if (rt5682->jack_type == 0) { 1046 /* jack was out, report jack type */ 1047 rt5682->jack_type = 1048 rt5682_headset_detect(rt5682->component, 1); 1049 } else { 1050 /* jack is already in, report button event */ 1051 rt5682->jack_type = SND_JACK_HEADSET; 1052 btn_type = rt5682_button_detect(rt5682->component); 1053 /** 1054 * rt5682 can report three kinds of button behavior, 1055 * one click, double click and hold. However, 1056 * currently we will report button pressed/released 1057 * event. So all the three button behaviors are 1058 * treated as button pressed. 1059 */ 1060 switch (btn_type) { 1061 case 0x8000: 1062 case 0x4000: 1063 case 0x2000: 1064 rt5682->jack_type |= SND_JACK_BTN_0; 1065 break; 1066 case 0x1000: 1067 case 0x0800: 1068 case 0x0400: 1069 rt5682->jack_type |= SND_JACK_BTN_1; 1070 break; 1071 case 0x0200: 1072 case 0x0100: 1073 case 0x0080: 1074 rt5682->jack_type |= SND_JACK_BTN_2; 1075 break; 1076 case 0x0040: 1077 case 0x0020: 1078 case 0x0010: 1079 rt5682->jack_type |= SND_JACK_BTN_3; 1080 break; 1081 case 0x0000: /* unpressed */ 1082 break; 1083 default: 1084 btn_type = 0; 1085 dev_err(rt5682->component->dev, 1086 "Unexpected button code 0x%04x\n", 1087 btn_type); 1088 break; 1089 } 1090 } 1091 } else { 1092 /* jack out */ 1093 rt5682->jack_type = rt5682_headset_detect(rt5682->component, 0); 1094 } 1095 1096 snd_soc_jack_report(rt5682->hs_jack, rt5682->jack_type, 1097 SND_JACK_HEADSET | 1098 SND_JACK_BTN_0 | SND_JACK_BTN_1 | 1099 SND_JACK_BTN_2 | SND_JACK_BTN_3); 1100 1101 if (rt5682->jack_type & (SND_JACK_BTN_0 | SND_JACK_BTN_1 | 1102 SND_JACK_BTN_2 | SND_JACK_BTN_3)) 1103 schedule_delayed_work(&rt5682->jd_check_work, 0); 1104 else 1105 cancel_delayed_work_sync(&rt5682->jd_check_work); 1106 1107 mutex_unlock(&rt5682->calibrate_mutex); 1108 } 1109 1110 static const struct snd_kcontrol_new rt5682_snd_controls[] = { 1111 /* Headphone Output Volume */ 1112 SOC_DOUBLE_R_TLV("Headphone Playback Volume", RT5682_HPL_GAIN, 1113 RT5682_HPR_GAIN, RT5682_G_HP_SFT, 15, 1, hp_vol_tlv), 1114 1115 /* DAC Digital Volume */ 1116 SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5682_DAC1_DIG_VOL, 1117 RT5682_L_VOL_SFT, RT5682_R_VOL_SFT, 175, 0, dac_vol_tlv), 1118 1119 /* IN Boost Volume */ 1120 SOC_SINGLE_TLV("CBJ Boost Volume", RT5682_CBJ_BST_CTRL, 1121 RT5682_BST_CBJ_SFT, 8, 0, bst_tlv), 1122 1123 /* ADC Digital Volume Control */ 1124 SOC_DOUBLE("STO1 ADC Capture Switch", RT5682_STO1_ADC_DIG_VOL, 1125 RT5682_L_MUTE_SFT, RT5682_R_MUTE_SFT, 1, 1), 1126 SOC_DOUBLE_TLV("STO1 ADC Capture Volume", RT5682_STO1_ADC_DIG_VOL, 1127 RT5682_L_VOL_SFT, RT5682_R_VOL_SFT, 127, 0, adc_vol_tlv), 1128 1129 /* ADC Boost Volume Control */ 1130 SOC_DOUBLE_TLV("STO1 ADC Boost Gain Volume", RT5682_STO1_ADC_BOOST, 1131 RT5682_STO1_ADC_L_BST_SFT, RT5682_STO1_ADC_R_BST_SFT, 1132 3, 0, adc_bst_tlv), 1133 }; 1134 1135 1136 static int rt5682_div_sel(struct rt5682_priv *rt5682, 1137 int target, const int div[], int size) 1138 { 1139 int i; 1140 1141 if (rt5682->sysclk < target) { 1142 pr_err("sysclk rate %d is too low\n", 1143 rt5682->sysclk); 1144 return 0; 1145 } 1146 1147 for (i = 0; i < size - 1; i++) { 1148 pr_info("div[%d]=%d\n", i, div[i]); 1149 if (target * div[i] == rt5682->sysclk) 1150 return i; 1151 if (target * div[i + 1] > rt5682->sysclk) { 1152 pr_err("can't find div for sysclk %d\n", 1153 rt5682->sysclk); 1154 return i; 1155 } 1156 } 1157 1158 if (target * div[i] < rt5682->sysclk) 1159 pr_err("sysclk rate %d is too high\n", 1160 rt5682->sysclk); 1161 1162 return size - 1; 1163 1164 } 1165 1166 /** 1167 * set_dmic_clk - Set parameter of dmic. 1168 * 1169 * @w: DAPM widget. 1170 * @kcontrol: The kcontrol of this widget. 1171 * @event: Event id. 1172 * 1173 * Choose dmic clock between 1MHz and 3MHz. 1174 * It is better for clock to approximate 3MHz. 1175 */ 1176 static int set_dmic_clk(struct snd_soc_dapm_widget *w, 1177 struct snd_kcontrol *kcontrol, int event) 1178 { 1179 struct snd_soc_component *component = 1180 snd_soc_dapm_to_component(w->dapm); 1181 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 1182 int idx = -EINVAL; 1183 static const int div[] = {2, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, 128}; 1184 1185 idx = rt5682_div_sel(rt5682, 1500000, div, ARRAY_SIZE(div)); 1186 1187 snd_soc_component_update_bits(component, RT5682_DMIC_CTRL_1, 1188 RT5682_DMIC_CLK_MASK, idx << RT5682_DMIC_CLK_SFT); 1189 1190 return 0; 1191 } 1192 1193 static int set_filter_clk(struct snd_soc_dapm_widget *w, 1194 struct snd_kcontrol *kcontrol, int event) 1195 { 1196 struct snd_soc_component *component = 1197 snd_soc_dapm_to_component(w->dapm); 1198 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 1199 int ref, val, reg, sft, mask, idx = -EINVAL; 1200 static const int div_f[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32, 48}; 1201 static const int div_o[] = {1, 2, 4, 6, 8, 12, 16, 24, 32, 48}; 1202 1203 val = snd_soc_component_read32(component, RT5682_GPIO_CTRL_1) & 1204 RT5682_GP4_PIN_MASK; 1205 if (w->shift == RT5682_PWR_ADC_S1F_BIT && 1206 val == RT5682_GP4_PIN_ADCDAT2) 1207 ref = 256 * rt5682->lrck[RT5682_AIF2]; 1208 else 1209 ref = 256 * rt5682->lrck[RT5682_AIF1]; 1210 1211 idx = rt5682_div_sel(rt5682, ref, div_f, ARRAY_SIZE(div_f)); 1212 1213 if (w->shift == RT5682_PWR_ADC_S1F_BIT) { 1214 reg = RT5682_PLL_TRACK_3; 1215 sft = RT5682_ADC_OSR_SFT; 1216 mask = RT5682_ADC_OSR_MASK; 1217 } else { 1218 reg = RT5682_PLL_TRACK_2; 1219 sft = RT5682_DAC_OSR_SFT; 1220 mask = RT5682_DAC_OSR_MASK; 1221 } 1222 1223 snd_soc_component_update_bits(component, reg, 1224 RT5682_FILTER_CLK_DIV_MASK, idx << RT5682_FILTER_CLK_DIV_SFT); 1225 1226 /* select over sample rate */ 1227 for (idx = 0; idx < ARRAY_SIZE(div_o); idx++) { 1228 if (rt5682->sysclk <= 12288000 * div_o[idx]) 1229 break; 1230 } 1231 1232 snd_soc_component_update_bits(component, RT5682_ADDA_CLK_1, 1233 mask, idx << sft); 1234 1235 return 0; 1236 } 1237 1238 static int is_sys_clk_from_pll1(struct snd_soc_dapm_widget *w, 1239 struct snd_soc_dapm_widget *sink) 1240 { 1241 unsigned int val; 1242 struct snd_soc_component *component = 1243 snd_soc_dapm_to_component(w->dapm); 1244 1245 val = snd_soc_component_read32(component, RT5682_GLB_CLK); 1246 val &= RT5682_SCLK_SRC_MASK; 1247 if (val == RT5682_SCLK_SRC_PLL1) 1248 return 1; 1249 else 1250 return 0; 1251 } 1252 1253 static int is_using_asrc(struct snd_soc_dapm_widget *w, 1254 struct snd_soc_dapm_widget *sink) 1255 { 1256 unsigned int reg, shift, val; 1257 struct snd_soc_component *component = 1258 snd_soc_dapm_to_component(w->dapm); 1259 1260 switch (w->shift) { 1261 case RT5682_ADC_STO1_ASRC_SFT: 1262 reg = RT5682_PLL_TRACK_3; 1263 shift = RT5682_FILTER_CLK_SEL_SFT; 1264 break; 1265 case RT5682_DAC_STO1_ASRC_SFT: 1266 reg = RT5682_PLL_TRACK_2; 1267 shift = RT5682_FILTER_CLK_SEL_SFT; 1268 break; 1269 default: 1270 return 0; 1271 } 1272 1273 val = (snd_soc_component_read32(component, reg) >> shift) & 0xf; 1274 switch (val) { 1275 case RT5682_CLK_SEL_I2S1_ASRC: 1276 case RT5682_CLK_SEL_I2S2_ASRC: 1277 return 1; 1278 default: 1279 return 0; 1280 } 1281 1282 } 1283 1284 /* Digital Mixer */ 1285 static const struct snd_kcontrol_new rt5682_sto1_adc_l_mix[] = { 1286 SOC_DAPM_SINGLE("ADC1 Switch", RT5682_STO1_ADC_MIXER, 1287 RT5682_M_STO1_ADC_L1_SFT, 1, 1), 1288 SOC_DAPM_SINGLE("ADC2 Switch", RT5682_STO1_ADC_MIXER, 1289 RT5682_M_STO1_ADC_L2_SFT, 1, 1), 1290 }; 1291 1292 static const struct snd_kcontrol_new rt5682_sto1_adc_r_mix[] = { 1293 SOC_DAPM_SINGLE("ADC1 Switch", RT5682_STO1_ADC_MIXER, 1294 RT5682_M_STO1_ADC_R1_SFT, 1, 1), 1295 SOC_DAPM_SINGLE("ADC2 Switch", RT5682_STO1_ADC_MIXER, 1296 RT5682_M_STO1_ADC_R2_SFT, 1, 1), 1297 }; 1298 1299 static const struct snd_kcontrol_new rt5682_dac_l_mix[] = { 1300 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5682_AD_DA_MIXER, 1301 RT5682_M_ADCMIX_L_SFT, 1, 1), 1302 SOC_DAPM_SINGLE("DAC1 Switch", RT5682_AD_DA_MIXER, 1303 RT5682_M_DAC1_L_SFT, 1, 1), 1304 }; 1305 1306 static const struct snd_kcontrol_new rt5682_dac_r_mix[] = { 1307 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5682_AD_DA_MIXER, 1308 RT5682_M_ADCMIX_R_SFT, 1, 1), 1309 SOC_DAPM_SINGLE("DAC1 Switch", RT5682_AD_DA_MIXER, 1310 RT5682_M_DAC1_R_SFT, 1, 1), 1311 }; 1312 1313 static const struct snd_kcontrol_new rt5682_sto1_dac_l_mix[] = { 1314 SOC_DAPM_SINGLE("DAC L1 Switch", RT5682_STO1_DAC_MIXER, 1315 RT5682_M_DAC_L1_STO_L_SFT, 1, 1), 1316 SOC_DAPM_SINGLE("DAC R1 Switch", RT5682_STO1_DAC_MIXER, 1317 RT5682_M_DAC_R1_STO_L_SFT, 1, 1), 1318 }; 1319 1320 static const struct snd_kcontrol_new rt5682_sto1_dac_r_mix[] = { 1321 SOC_DAPM_SINGLE("DAC L1 Switch", RT5682_STO1_DAC_MIXER, 1322 RT5682_M_DAC_L1_STO_R_SFT, 1, 1), 1323 SOC_DAPM_SINGLE("DAC R1 Switch", RT5682_STO1_DAC_MIXER, 1324 RT5682_M_DAC_R1_STO_R_SFT, 1, 1), 1325 }; 1326 1327 /* Analog Input Mixer */ 1328 static const struct snd_kcontrol_new rt5682_rec1_l_mix[] = { 1329 SOC_DAPM_SINGLE("CBJ Switch", RT5682_REC_MIXER, 1330 RT5682_M_CBJ_RM1_L_SFT, 1, 1), 1331 }; 1332 1333 /* STO1 ADC1 Source */ 1334 /* MX-26 [13] [5] */ 1335 static const char * const rt5682_sto1_adc1_src[] = { 1336 "DAC MIX", "ADC" 1337 }; 1338 1339 static SOC_ENUM_SINGLE_DECL( 1340 rt5682_sto1_adc1l_enum, RT5682_STO1_ADC_MIXER, 1341 RT5682_STO1_ADC1L_SRC_SFT, rt5682_sto1_adc1_src); 1342 1343 static const struct snd_kcontrol_new rt5682_sto1_adc1l_mux = 1344 SOC_DAPM_ENUM("Stereo1 ADC1L Source", rt5682_sto1_adc1l_enum); 1345 1346 static SOC_ENUM_SINGLE_DECL( 1347 rt5682_sto1_adc1r_enum, RT5682_STO1_ADC_MIXER, 1348 RT5682_STO1_ADC1R_SRC_SFT, rt5682_sto1_adc1_src); 1349 1350 static const struct snd_kcontrol_new rt5682_sto1_adc1r_mux = 1351 SOC_DAPM_ENUM("Stereo1 ADC1L Source", rt5682_sto1_adc1r_enum); 1352 1353 /* STO1 ADC Source */ 1354 /* MX-26 [11:10] [3:2] */ 1355 static const char * const rt5682_sto1_adc_src[] = { 1356 "ADC1 L", "ADC1 R" 1357 }; 1358 1359 static SOC_ENUM_SINGLE_DECL( 1360 rt5682_sto1_adcl_enum, RT5682_STO1_ADC_MIXER, 1361 RT5682_STO1_ADCL_SRC_SFT, rt5682_sto1_adc_src); 1362 1363 static const struct snd_kcontrol_new rt5682_sto1_adcl_mux = 1364 SOC_DAPM_ENUM("Stereo1 ADCL Source", rt5682_sto1_adcl_enum); 1365 1366 static SOC_ENUM_SINGLE_DECL( 1367 rt5682_sto1_adcr_enum, RT5682_STO1_ADC_MIXER, 1368 RT5682_STO1_ADCR_SRC_SFT, rt5682_sto1_adc_src); 1369 1370 static const struct snd_kcontrol_new rt5682_sto1_adcr_mux = 1371 SOC_DAPM_ENUM("Stereo1 ADCR Source", rt5682_sto1_adcr_enum); 1372 1373 /* STO1 ADC2 Source */ 1374 /* MX-26 [12] [4] */ 1375 static const char * const rt5682_sto1_adc2_src[] = { 1376 "DAC MIX", "DMIC" 1377 }; 1378 1379 static SOC_ENUM_SINGLE_DECL( 1380 rt5682_sto1_adc2l_enum, RT5682_STO1_ADC_MIXER, 1381 RT5682_STO1_ADC2L_SRC_SFT, rt5682_sto1_adc2_src); 1382 1383 static const struct snd_kcontrol_new rt5682_sto1_adc2l_mux = 1384 SOC_DAPM_ENUM("Stereo1 ADC2L Source", rt5682_sto1_adc2l_enum); 1385 1386 static SOC_ENUM_SINGLE_DECL( 1387 rt5682_sto1_adc2r_enum, RT5682_STO1_ADC_MIXER, 1388 RT5682_STO1_ADC2R_SRC_SFT, rt5682_sto1_adc2_src); 1389 1390 static const struct snd_kcontrol_new rt5682_sto1_adc2r_mux = 1391 SOC_DAPM_ENUM("Stereo1 ADC2R Source", rt5682_sto1_adc2r_enum); 1392 1393 /* MX-79 [6:4] I2S1 ADC data location */ 1394 static const unsigned int rt5682_if1_adc_slot_values[] = { 1395 0, 1396 2, 1397 4, 1398 6, 1399 }; 1400 1401 static const char * const rt5682_if1_adc_slot_src[] = { 1402 "Slot 0", "Slot 2", "Slot 4", "Slot 6" 1403 }; 1404 1405 static SOC_VALUE_ENUM_SINGLE_DECL(rt5682_if1_adc_slot_enum, 1406 RT5682_TDM_CTRL, RT5682_TDM_ADC_LCA_SFT, RT5682_TDM_ADC_LCA_MASK, 1407 rt5682_if1_adc_slot_src, rt5682_if1_adc_slot_values); 1408 1409 static const struct snd_kcontrol_new rt5682_if1_adc_slot_mux = 1410 SOC_DAPM_ENUM("IF1 ADC Slot location", rt5682_if1_adc_slot_enum); 1411 1412 /* Analog DAC L1 Source, Analog DAC R1 Source*/ 1413 /* MX-2B [4], MX-2B [0]*/ 1414 static const char * const rt5682_alg_dac1_src[] = { 1415 "Stereo1 DAC Mixer", "DAC1" 1416 }; 1417 1418 static SOC_ENUM_SINGLE_DECL( 1419 rt5682_alg_dac_l1_enum, RT5682_A_DAC1_MUX, 1420 RT5682_A_DACL1_SFT, rt5682_alg_dac1_src); 1421 1422 static const struct snd_kcontrol_new rt5682_alg_dac_l1_mux = 1423 SOC_DAPM_ENUM("Analog DAC L1 Source", rt5682_alg_dac_l1_enum); 1424 1425 static SOC_ENUM_SINGLE_DECL( 1426 rt5682_alg_dac_r1_enum, RT5682_A_DAC1_MUX, 1427 RT5682_A_DACR1_SFT, rt5682_alg_dac1_src); 1428 1429 static const struct snd_kcontrol_new rt5682_alg_dac_r1_mux = 1430 SOC_DAPM_ENUM("Analog DAC R1 Source", rt5682_alg_dac_r1_enum); 1431 1432 /* Out Switch */ 1433 static const struct snd_kcontrol_new hpol_switch = 1434 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5682_HP_CTRL_1, 1435 RT5682_L_MUTE_SFT, 1, 1); 1436 static const struct snd_kcontrol_new hpor_switch = 1437 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5682_HP_CTRL_1, 1438 RT5682_R_MUTE_SFT, 1, 1); 1439 1440 static int rt5682_hp_event(struct snd_soc_dapm_widget *w, 1441 struct snd_kcontrol *kcontrol, int event) 1442 { 1443 struct snd_soc_component *component = 1444 snd_soc_dapm_to_component(w->dapm); 1445 1446 switch (event) { 1447 case SND_SOC_DAPM_PRE_PMU: 1448 snd_soc_component_write(component, 1449 RT5682_HP_LOGIC_CTRL_2, 0x0012); 1450 snd_soc_component_write(component, 1451 RT5682_HP_CTRL_2, 0x6000); 1452 snd_soc_component_update_bits(component, RT5682_STO_NG2_CTRL_1, 1453 RT5682_NG2_EN_MASK, RT5682_NG2_EN); 1454 snd_soc_component_update_bits(component, 1455 RT5682_DEPOP_1, 0x60, 0x60); 1456 break; 1457 1458 case SND_SOC_DAPM_POST_PMD: 1459 snd_soc_component_update_bits(component, 1460 RT5682_DEPOP_1, 0x60, 0x0); 1461 snd_soc_component_write(component, 1462 RT5682_HP_CTRL_2, 0x0000); 1463 break; 1464 1465 default: 1466 return 0; 1467 } 1468 1469 return 0; 1470 1471 } 1472 1473 static int set_dmic_power(struct snd_soc_dapm_widget *w, 1474 struct snd_kcontrol *kcontrol, int event) 1475 { 1476 switch (event) { 1477 case SND_SOC_DAPM_POST_PMU: 1478 /*Add delay to avoid pop noise*/ 1479 msleep(150); 1480 break; 1481 1482 default: 1483 return 0; 1484 } 1485 1486 return 0; 1487 } 1488 1489 static int rt5655_set_verf(struct snd_soc_dapm_widget *w, 1490 struct snd_kcontrol *kcontrol, int event) 1491 { 1492 struct snd_soc_component *component = 1493 snd_soc_dapm_to_component(w->dapm); 1494 1495 switch (event) { 1496 case SND_SOC_DAPM_PRE_PMU: 1497 switch (w->shift) { 1498 case RT5682_PWR_VREF1_BIT: 1499 snd_soc_component_update_bits(component, 1500 RT5682_PWR_ANLG_1, RT5682_PWR_FV1, 0); 1501 break; 1502 1503 case RT5682_PWR_VREF2_BIT: 1504 snd_soc_component_update_bits(component, 1505 RT5682_PWR_ANLG_1, RT5682_PWR_FV2, 0); 1506 break; 1507 1508 default: 1509 break; 1510 } 1511 break; 1512 1513 case SND_SOC_DAPM_POST_PMU: 1514 usleep_range(15000, 20000); 1515 switch (w->shift) { 1516 case RT5682_PWR_VREF1_BIT: 1517 snd_soc_component_update_bits(component, 1518 RT5682_PWR_ANLG_1, RT5682_PWR_FV1, 1519 RT5682_PWR_FV1); 1520 break; 1521 1522 case RT5682_PWR_VREF2_BIT: 1523 snd_soc_component_update_bits(component, 1524 RT5682_PWR_ANLG_1, RT5682_PWR_FV2, 1525 RT5682_PWR_FV2); 1526 break; 1527 1528 default: 1529 break; 1530 } 1531 break; 1532 1533 default: 1534 return 0; 1535 } 1536 1537 return 0; 1538 } 1539 1540 static const unsigned int rt5682_adcdat_pin_values[] = { 1541 1, 1542 3, 1543 }; 1544 1545 static const char * const rt5682_adcdat_pin_select[] = { 1546 "ADCDAT1", 1547 "ADCDAT2", 1548 }; 1549 1550 static SOC_VALUE_ENUM_SINGLE_DECL(rt5682_adcdat_pin_enum, 1551 RT5682_GPIO_CTRL_1, RT5682_GP4_PIN_SFT, RT5682_GP4_PIN_MASK, 1552 rt5682_adcdat_pin_select, rt5682_adcdat_pin_values); 1553 1554 static const struct snd_kcontrol_new rt5682_adcdat_pin_ctrl = 1555 SOC_DAPM_ENUM("ADCDAT", rt5682_adcdat_pin_enum); 1556 1557 static const struct snd_soc_dapm_widget rt5682_dapm_widgets[] = { 1558 SND_SOC_DAPM_SUPPLY("LDO2", RT5682_PWR_ANLG_3, RT5682_PWR_LDO2_BIT, 1559 0, NULL, 0), 1560 SND_SOC_DAPM_SUPPLY("PLL1", RT5682_PWR_ANLG_3, RT5682_PWR_PLL_BIT, 1561 0, NULL, 0), 1562 SND_SOC_DAPM_SUPPLY("PLL2B", RT5682_PWR_ANLG_3, RT5682_PWR_PLL2B_BIT, 1563 0, NULL, 0), 1564 SND_SOC_DAPM_SUPPLY("PLL2F", RT5682_PWR_ANLG_3, RT5682_PWR_PLL2F_BIT, 1565 0, NULL, 0), 1566 SND_SOC_DAPM_SUPPLY("Vref1", RT5682_PWR_ANLG_1, RT5682_PWR_VREF1_BIT, 0, 1567 rt5655_set_verf, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), 1568 SND_SOC_DAPM_SUPPLY("Vref2", RT5682_PWR_ANLG_1, RT5682_PWR_VREF2_BIT, 0, 1569 rt5655_set_verf, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), 1570 1571 /* ASRC */ 1572 SND_SOC_DAPM_SUPPLY_S("DAC STO1 ASRC", 1, RT5682_PLL_TRACK_1, 1573 RT5682_DAC_STO1_ASRC_SFT, 0, NULL, 0), 1574 SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5682_PLL_TRACK_1, 1575 RT5682_ADC_STO1_ASRC_SFT, 0, NULL, 0), 1576 SND_SOC_DAPM_SUPPLY_S("AD ASRC", 1, RT5682_PLL_TRACK_1, 1577 RT5682_AD_ASRC_SFT, 0, NULL, 0), 1578 SND_SOC_DAPM_SUPPLY_S("DA ASRC", 1, RT5682_PLL_TRACK_1, 1579 RT5682_DA_ASRC_SFT, 0, NULL, 0), 1580 SND_SOC_DAPM_SUPPLY_S("DMIC ASRC", 1, RT5682_PLL_TRACK_1, 1581 RT5682_DMIC_ASRC_SFT, 0, NULL, 0), 1582 1583 /* Input Side */ 1584 SND_SOC_DAPM_SUPPLY("MICBIAS1", RT5682_PWR_ANLG_2, RT5682_PWR_MB1_BIT, 1585 0, NULL, 0), 1586 SND_SOC_DAPM_SUPPLY("MICBIAS2", RT5682_PWR_ANLG_2, RT5682_PWR_MB2_BIT, 1587 0, NULL, 0), 1588 1589 /* Input Lines */ 1590 SND_SOC_DAPM_INPUT("DMIC L1"), 1591 SND_SOC_DAPM_INPUT("DMIC R1"), 1592 1593 SND_SOC_DAPM_INPUT("IN1P"), 1594 1595 SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0, 1596 set_dmic_clk, SND_SOC_DAPM_PRE_PMU), 1597 SND_SOC_DAPM_SUPPLY("DMIC1 Power", RT5682_DMIC_CTRL_1, 1598 RT5682_DMIC_1_EN_SFT, 0, set_dmic_power, SND_SOC_DAPM_POST_PMU), 1599 1600 /* Boost */ 1601 SND_SOC_DAPM_PGA("BST1 CBJ", SND_SOC_NOPM, 1602 0, 0, NULL, 0), 1603 1604 SND_SOC_DAPM_SUPPLY("CBJ Power", RT5682_PWR_ANLG_3, 1605 RT5682_PWR_CBJ_BIT, 0, NULL, 0), 1606 1607 /* REC Mixer */ 1608 SND_SOC_DAPM_MIXER("RECMIX1L", SND_SOC_NOPM, 0, 0, rt5682_rec1_l_mix, 1609 ARRAY_SIZE(rt5682_rec1_l_mix)), 1610 SND_SOC_DAPM_SUPPLY("RECMIX1L Power", RT5682_PWR_ANLG_2, 1611 RT5682_PWR_RM1_L_BIT, 0, NULL, 0), 1612 1613 /* ADCs */ 1614 SND_SOC_DAPM_ADC("ADC1 L", NULL, SND_SOC_NOPM, 0, 0), 1615 SND_SOC_DAPM_ADC("ADC1 R", NULL, SND_SOC_NOPM, 0, 0), 1616 1617 SND_SOC_DAPM_SUPPLY("ADC1 L Power", RT5682_PWR_DIG_1, 1618 RT5682_PWR_ADC_L1_BIT, 0, NULL, 0), 1619 SND_SOC_DAPM_SUPPLY("ADC1 R Power", RT5682_PWR_DIG_1, 1620 RT5682_PWR_ADC_R1_BIT, 0, NULL, 0), 1621 SND_SOC_DAPM_SUPPLY("ADC1 clock", RT5682_CHOP_ADC, 1622 RT5682_CKGEN_ADC1_SFT, 0, NULL, 0), 1623 1624 /* ADC Mux */ 1625 SND_SOC_DAPM_MUX("Stereo1 ADC L1 Mux", SND_SOC_NOPM, 0, 0, 1626 &rt5682_sto1_adc1l_mux), 1627 SND_SOC_DAPM_MUX("Stereo1 ADC R1 Mux", SND_SOC_NOPM, 0, 0, 1628 &rt5682_sto1_adc1r_mux), 1629 SND_SOC_DAPM_MUX("Stereo1 ADC L2 Mux", SND_SOC_NOPM, 0, 0, 1630 &rt5682_sto1_adc2l_mux), 1631 SND_SOC_DAPM_MUX("Stereo1 ADC R2 Mux", SND_SOC_NOPM, 0, 0, 1632 &rt5682_sto1_adc2r_mux), 1633 SND_SOC_DAPM_MUX("Stereo1 ADC L Mux", SND_SOC_NOPM, 0, 0, 1634 &rt5682_sto1_adcl_mux), 1635 SND_SOC_DAPM_MUX("Stereo1 ADC R Mux", SND_SOC_NOPM, 0, 0, 1636 &rt5682_sto1_adcr_mux), 1637 SND_SOC_DAPM_MUX("IF1_ADC Mux", SND_SOC_NOPM, 0, 0, 1638 &rt5682_if1_adc_slot_mux), 1639 1640 /* ADC Mixer */ 1641 SND_SOC_DAPM_SUPPLY("ADC Stereo1 Filter", RT5682_PWR_DIG_2, 1642 RT5682_PWR_ADC_S1F_BIT, 0, set_filter_clk, 1643 SND_SOC_DAPM_PRE_PMU), 1644 SND_SOC_DAPM_MIXER("Stereo1 ADC MIXL", RT5682_STO1_ADC_DIG_VOL, 1645 RT5682_L_MUTE_SFT, 1, rt5682_sto1_adc_l_mix, 1646 ARRAY_SIZE(rt5682_sto1_adc_l_mix)), 1647 SND_SOC_DAPM_MIXER("Stereo1 ADC MIXR", RT5682_STO1_ADC_DIG_VOL, 1648 RT5682_R_MUTE_SFT, 1, rt5682_sto1_adc_r_mix, 1649 ARRAY_SIZE(rt5682_sto1_adc_r_mix)), 1650 SND_SOC_DAPM_SUPPLY("BTN Detection Mode", RT5682_SAR_IL_CMD_1, 1651 14, 1, NULL, 0), 1652 1653 /* ADC PGA */ 1654 SND_SOC_DAPM_PGA("Stereo1 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 1655 1656 /* Digital Interface */ 1657 SND_SOC_DAPM_SUPPLY("I2S1", RT5682_PWR_DIG_1, RT5682_PWR_I2S1_BIT, 1658 0, NULL, 0), 1659 SND_SOC_DAPM_SUPPLY("I2S2", RT5682_PWR_DIG_1, RT5682_PWR_I2S2_BIT, 1660 0, NULL, 0), 1661 SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0), 1662 SND_SOC_DAPM_PGA("IF1 DAC1 L", SND_SOC_NOPM, 0, 0, NULL, 0), 1663 SND_SOC_DAPM_PGA("IF1 DAC1 R", SND_SOC_NOPM, 0, 0, NULL, 0), 1664 1665 /* Digital Interface Select */ 1666 SND_SOC_DAPM_MUX("IF1 01 ADC Swap Mux", SND_SOC_NOPM, 0, 0, 1667 &rt5682_if1_01_adc_swap_mux), 1668 SND_SOC_DAPM_MUX("IF1 23 ADC Swap Mux", SND_SOC_NOPM, 0, 0, 1669 &rt5682_if1_23_adc_swap_mux), 1670 SND_SOC_DAPM_MUX("IF1 45 ADC Swap Mux", SND_SOC_NOPM, 0, 0, 1671 &rt5682_if1_45_adc_swap_mux), 1672 SND_SOC_DAPM_MUX("IF1 67 ADC Swap Mux", SND_SOC_NOPM, 0, 0, 1673 &rt5682_if1_67_adc_swap_mux), 1674 SND_SOC_DAPM_MUX("IF2 ADC Swap Mux", SND_SOC_NOPM, 0, 0, 1675 &rt5682_if2_adc_swap_mux), 1676 1677 SND_SOC_DAPM_MUX("ADCDAT Mux", SND_SOC_NOPM, 0, 0, 1678 &rt5682_adcdat_pin_ctrl), 1679 1680 /* Audio Interface */ 1681 SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, 1682 RT5682_I2S1_SDP, RT5682_SEL_ADCDAT_SFT, 1), 1683 SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, 1684 RT5682_I2S2_SDP, RT5682_I2S2_PIN_CFG_SFT, 1), 1685 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0), 1686 1687 /* Output Side */ 1688 /* DAC mixer before sound effect */ 1689 SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0, 1690 rt5682_dac_l_mix, ARRAY_SIZE(rt5682_dac_l_mix)), 1691 SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0, 1692 rt5682_dac_r_mix, ARRAY_SIZE(rt5682_dac_r_mix)), 1693 1694 /* DAC channel Mux */ 1695 SND_SOC_DAPM_MUX("DAC L1 Source", SND_SOC_NOPM, 0, 0, 1696 &rt5682_alg_dac_l1_mux), 1697 SND_SOC_DAPM_MUX("DAC R1 Source", SND_SOC_NOPM, 0, 0, 1698 &rt5682_alg_dac_r1_mux), 1699 1700 /* DAC Mixer */ 1701 SND_SOC_DAPM_SUPPLY("DAC Stereo1 Filter", RT5682_PWR_DIG_2, 1702 RT5682_PWR_DAC_S1F_BIT, 0, set_filter_clk, 1703 SND_SOC_DAPM_PRE_PMU), 1704 SND_SOC_DAPM_MIXER("Stereo1 DAC MIXL", SND_SOC_NOPM, 0, 0, 1705 rt5682_sto1_dac_l_mix, ARRAY_SIZE(rt5682_sto1_dac_l_mix)), 1706 SND_SOC_DAPM_MIXER("Stereo1 DAC MIXR", SND_SOC_NOPM, 0, 0, 1707 rt5682_sto1_dac_r_mix, ARRAY_SIZE(rt5682_sto1_dac_r_mix)), 1708 1709 /* DACs */ 1710 SND_SOC_DAPM_DAC("DAC L1", NULL, RT5682_PWR_DIG_1, 1711 RT5682_PWR_DAC_L1_BIT, 0), 1712 SND_SOC_DAPM_DAC("DAC R1", NULL, RT5682_PWR_DIG_1, 1713 RT5682_PWR_DAC_R1_BIT, 0), 1714 SND_SOC_DAPM_SUPPLY_S("DAC 1 Clock", 3, RT5682_CHOP_DAC, 1715 RT5682_CKGEN_DAC1_SFT, 0, NULL, 0), 1716 1717 /* HPO */ 1718 SND_SOC_DAPM_PGA_S("HP Amp", 1, SND_SOC_NOPM, 0, 0, rt5682_hp_event, 1719 SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_PRE_PMU), 1720 1721 SND_SOC_DAPM_SUPPLY("HP Amp L", RT5682_PWR_ANLG_1, 1722 RT5682_PWR_HA_L_BIT, 0, NULL, 0), 1723 SND_SOC_DAPM_SUPPLY("HP Amp R", RT5682_PWR_ANLG_1, 1724 RT5682_PWR_HA_R_BIT, 0, NULL, 0), 1725 SND_SOC_DAPM_SUPPLY_S("Charge Pump", 1, RT5682_DEPOP_1, 1726 RT5682_PUMP_EN_SFT, 0, NULL, 0), 1727 SND_SOC_DAPM_SUPPLY_S("Capless", 2, RT5682_DEPOP_1, 1728 RT5682_CAPLESS_EN_SFT, 0, NULL, 0), 1729 1730 SND_SOC_DAPM_SWITCH("HPOL Playback", SND_SOC_NOPM, 0, 0, 1731 &hpol_switch), 1732 SND_SOC_DAPM_SWITCH("HPOR Playback", SND_SOC_NOPM, 0, 0, 1733 &hpor_switch), 1734 1735 /* CLK DET */ 1736 SND_SOC_DAPM_SUPPLY("CLKDET SYS", RT5682_CLK_DET, 1737 RT5682_SYS_CLK_DET_SFT, 0, NULL, 0), 1738 SND_SOC_DAPM_SUPPLY("CLKDET PLL1", RT5682_CLK_DET, 1739 RT5682_PLL1_CLK_DET_SFT, 0, NULL, 0), 1740 SND_SOC_DAPM_SUPPLY("CLKDET PLL2", RT5682_CLK_DET, 1741 RT5682_PLL2_CLK_DET_SFT, 0, NULL, 0), 1742 SND_SOC_DAPM_SUPPLY("CLKDET", RT5682_CLK_DET, 1743 RT5682_POW_CLK_DET_SFT, 0, NULL, 0), 1744 1745 /* Output Lines */ 1746 SND_SOC_DAPM_OUTPUT("HPOL"), 1747 SND_SOC_DAPM_OUTPUT("HPOR"), 1748 1749 }; 1750 1751 static const struct snd_soc_dapm_route rt5682_dapm_routes[] = { 1752 /*PLL*/ 1753 {"ADC Stereo1 Filter", NULL, "PLL1", is_sys_clk_from_pll1}, 1754 {"DAC Stereo1 Filter", NULL, "PLL1", is_sys_clk_from_pll1}, 1755 1756 /*ASRC*/ 1757 {"ADC Stereo1 Filter", NULL, "ADC STO1 ASRC", is_using_asrc}, 1758 {"DAC Stereo1 Filter", NULL, "DAC STO1 ASRC", is_using_asrc}, 1759 {"ADC STO1 ASRC", NULL, "AD ASRC"}, 1760 {"ADC STO1 ASRC", NULL, "CLKDET"}, 1761 {"DAC STO1 ASRC", NULL, "DA ASRC"}, 1762 {"DAC STO1 ASRC", NULL, "CLKDET"}, 1763 1764 /*Vref*/ 1765 {"MICBIAS1", NULL, "Vref1"}, 1766 {"MICBIAS1", NULL, "Vref2"}, 1767 {"MICBIAS2", NULL, "Vref1"}, 1768 {"MICBIAS2", NULL, "Vref2"}, 1769 1770 {"CLKDET SYS", NULL, "CLKDET"}, 1771 1772 {"IN1P", NULL, "LDO2"}, 1773 1774 {"BST1 CBJ", NULL, "IN1P"}, 1775 {"BST1 CBJ", NULL, "CBJ Power"}, 1776 {"CBJ Power", NULL, "Vref2"}, 1777 1778 {"RECMIX1L", "CBJ Switch", "BST1 CBJ"}, 1779 {"RECMIX1L", NULL, "RECMIX1L Power"}, 1780 1781 {"ADC1 L", NULL, "RECMIX1L"}, 1782 {"ADC1 L", NULL, "ADC1 L Power"}, 1783 {"ADC1 L", NULL, "ADC1 clock"}, 1784 1785 {"DMIC L1", NULL, "DMIC CLK"}, 1786 {"DMIC L1", NULL, "DMIC1 Power"}, 1787 {"DMIC R1", NULL, "DMIC CLK"}, 1788 {"DMIC R1", NULL, "DMIC1 Power"}, 1789 {"DMIC CLK", NULL, "DMIC ASRC"}, 1790 1791 {"Stereo1 ADC L Mux", "ADC1 L", "ADC1 L"}, 1792 {"Stereo1 ADC L Mux", "ADC1 R", "ADC1 R"}, 1793 {"Stereo1 ADC R Mux", "ADC1 L", "ADC1 L"}, 1794 {"Stereo1 ADC R Mux", "ADC1 R", "ADC1 R"}, 1795 1796 {"Stereo1 ADC L1 Mux", "ADC", "Stereo1 ADC L Mux"}, 1797 {"Stereo1 ADC L1 Mux", "DAC MIX", "Stereo1 DAC MIXL"}, 1798 {"Stereo1 ADC L2 Mux", "DMIC", "DMIC L1"}, 1799 {"Stereo1 ADC L2 Mux", "DAC MIX", "Stereo1 DAC MIXL"}, 1800 1801 {"Stereo1 ADC R1 Mux", "ADC", "Stereo1 ADC R Mux"}, 1802 {"Stereo1 ADC R1 Mux", "DAC MIX", "Stereo1 DAC MIXR"}, 1803 {"Stereo1 ADC R2 Mux", "DMIC", "DMIC R1"}, 1804 {"Stereo1 ADC R2 Mux", "DAC MIX", "Stereo1 DAC MIXR"}, 1805 1806 {"Stereo1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC L1 Mux"}, 1807 {"Stereo1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC L2 Mux"}, 1808 {"Stereo1 ADC MIXL", NULL, "ADC Stereo1 Filter"}, 1809 1810 {"Stereo1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC R1 Mux"}, 1811 {"Stereo1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC R2 Mux"}, 1812 {"Stereo1 ADC MIXR", NULL, "ADC Stereo1 Filter"}, 1813 1814 {"ADC Stereo1 Filter", NULL, "BTN Detection Mode"}, 1815 1816 {"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXL"}, 1817 {"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXR"}, 1818 1819 {"IF1 01 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"}, 1820 {"IF1 01 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"}, 1821 {"IF1 01 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"}, 1822 {"IF1 01 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"}, 1823 {"IF1 23 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"}, 1824 {"IF1 23 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"}, 1825 {"IF1 23 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"}, 1826 {"IF1 23 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"}, 1827 {"IF1 45 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"}, 1828 {"IF1 45 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"}, 1829 {"IF1 45 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"}, 1830 {"IF1 45 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"}, 1831 {"IF1 67 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"}, 1832 {"IF1 67 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"}, 1833 {"IF1 67 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"}, 1834 {"IF1 67 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"}, 1835 1836 {"IF1_ADC Mux", "Slot 0", "IF1 01 ADC Swap Mux"}, 1837 {"IF1_ADC Mux", "Slot 2", "IF1 23 ADC Swap Mux"}, 1838 {"IF1_ADC Mux", "Slot 4", "IF1 45 ADC Swap Mux"}, 1839 {"IF1_ADC Mux", "Slot 6", "IF1 67 ADC Swap Mux"}, 1840 {"IF1_ADC Mux", NULL, "I2S1"}, 1841 {"ADCDAT Mux", "ADCDAT1", "IF1_ADC Mux"}, 1842 {"AIF1TX", NULL, "ADCDAT Mux"}, 1843 {"IF2 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"}, 1844 {"IF2 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"}, 1845 {"IF2 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"}, 1846 {"IF2 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"}, 1847 {"ADCDAT Mux", "ADCDAT2", "IF2 ADC Swap Mux"}, 1848 {"AIF2TX", NULL, "ADCDAT Mux"}, 1849 1850 {"IF1 DAC1 L", NULL, "AIF1RX"}, 1851 {"IF1 DAC1 L", NULL, "I2S1"}, 1852 {"IF1 DAC1 L", NULL, "DAC Stereo1 Filter"}, 1853 {"IF1 DAC1 R", NULL, "AIF1RX"}, 1854 {"IF1 DAC1 R", NULL, "I2S1"}, 1855 {"IF1 DAC1 R", NULL, "DAC Stereo1 Filter"}, 1856 1857 {"DAC1 MIXL", "Stereo ADC Switch", "Stereo1 ADC MIXL"}, 1858 {"DAC1 MIXL", "DAC1 Switch", "IF1 DAC1 L"}, 1859 {"DAC1 MIXR", "Stereo ADC Switch", "Stereo1 ADC MIXR"}, 1860 {"DAC1 MIXR", "DAC1 Switch", "IF1 DAC1 R"}, 1861 1862 {"Stereo1 DAC MIXL", "DAC L1 Switch", "DAC1 MIXL"}, 1863 {"Stereo1 DAC MIXL", "DAC R1 Switch", "DAC1 MIXR"}, 1864 1865 {"Stereo1 DAC MIXR", "DAC R1 Switch", "DAC1 MIXR"}, 1866 {"Stereo1 DAC MIXR", "DAC L1 Switch", "DAC1 MIXL"}, 1867 1868 {"DAC L1 Source", "DAC1", "DAC1 MIXL"}, 1869 {"DAC L1 Source", "Stereo1 DAC Mixer", "Stereo1 DAC MIXL"}, 1870 {"DAC R1 Source", "DAC1", "DAC1 MIXR"}, 1871 {"DAC R1 Source", "Stereo1 DAC Mixer", "Stereo1 DAC MIXR"}, 1872 1873 {"DAC L1", NULL, "DAC L1 Source"}, 1874 {"DAC R1", NULL, "DAC R1 Source"}, 1875 1876 {"DAC L1", NULL, "DAC 1 Clock"}, 1877 {"DAC R1", NULL, "DAC 1 Clock"}, 1878 1879 {"HP Amp", NULL, "DAC L1"}, 1880 {"HP Amp", NULL, "DAC R1"}, 1881 {"HP Amp", NULL, "HP Amp L"}, 1882 {"HP Amp", NULL, "HP Amp R"}, 1883 {"HP Amp", NULL, "Capless"}, 1884 {"HP Amp", NULL, "Charge Pump"}, 1885 {"HP Amp", NULL, "CLKDET SYS"}, 1886 {"HP Amp", NULL, "CBJ Power"}, 1887 {"HP Amp", NULL, "Vref2"}, 1888 {"HPOL Playback", "Switch", "HP Amp"}, 1889 {"HPOR Playback", "Switch", "HP Amp"}, 1890 {"HPOL", NULL, "HPOL Playback"}, 1891 {"HPOR", NULL, "HPOR Playback"}, 1892 }; 1893 1894 static int rt5682_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask, 1895 unsigned int rx_mask, int slots, int slot_width) 1896 { 1897 struct snd_soc_component *component = dai->component; 1898 unsigned int cl, val = 0; 1899 1900 if (tx_mask || rx_mask) 1901 snd_soc_component_update_bits(component, RT5682_TDM_ADDA_CTRL_2, 1902 RT5682_TDM_EN, RT5682_TDM_EN); 1903 else 1904 snd_soc_component_update_bits(component, RT5682_TDM_ADDA_CTRL_2, 1905 RT5682_TDM_EN, 0); 1906 1907 switch (slots) { 1908 case 4: 1909 val |= RT5682_TDM_TX_CH_4; 1910 val |= RT5682_TDM_RX_CH_4; 1911 break; 1912 case 6: 1913 val |= RT5682_TDM_TX_CH_6; 1914 val |= RT5682_TDM_RX_CH_6; 1915 break; 1916 case 8: 1917 val |= RT5682_TDM_TX_CH_8; 1918 val |= RT5682_TDM_RX_CH_8; 1919 break; 1920 case 2: 1921 break; 1922 default: 1923 return -EINVAL; 1924 } 1925 1926 snd_soc_component_update_bits(component, RT5682_TDM_CTRL, 1927 RT5682_TDM_TX_CH_MASK | RT5682_TDM_RX_CH_MASK, val); 1928 1929 switch (slot_width) { 1930 case 8: 1931 if (tx_mask || rx_mask) 1932 return -EINVAL; 1933 cl = RT5682_I2S1_TX_CHL_8 | RT5682_I2S1_RX_CHL_8; 1934 break; 1935 case 16: 1936 val = RT5682_TDM_CL_16; 1937 cl = RT5682_I2S1_TX_CHL_16 | RT5682_I2S1_RX_CHL_16; 1938 break; 1939 case 20: 1940 val = RT5682_TDM_CL_20; 1941 cl = RT5682_I2S1_TX_CHL_20 | RT5682_I2S1_RX_CHL_20; 1942 break; 1943 case 24: 1944 val = RT5682_TDM_CL_24; 1945 cl = RT5682_I2S1_TX_CHL_24 | RT5682_I2S1_RX_CHL_24; 1946 break; 1947 case 32: 1948 val = RT5682_TDM_CL_32; 1949 cl = RT5682_I2S1_TX_CHL_32 | RT5682_I2S1_RX_CHL_32; 1950 break; 1951 default: 1952 return -EINVAL; 1953 } 1954 1955 snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL, 1956 RT5682_TDM_CL_MASK, val); 1957 snd_soc_component_update_bits(component, RT5682_I2S1_SDP, 1958 RT5682_I2S1_TX_CHL_MASK | RT5682_I2S1_RX_CHL_MASK, cl); 1959 1960 return 0; 1961 } 1962 1963 1964 static int rt5682_hw_params(struct snd_pcm_substream *substream, 1965 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) 1966 { 1967 struct snd_soc_component *component = dai->component; 1968 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 1969 unsigned int len_1 = 0, len_2 = 0; 1970 int pre_div, frame_size; 1971 1972 rt5682->lrck[dai->id] = params_rate(params); 1973 pre_div = rl6231_get_clk_info(rt5682->sysclk, rt5682->lrck[dai->id]); 1974 1975 frame_size = snd_soc_params_to_frame_size(params); 1976 if (frame_size < 0) { 1977 dev_err(component->dev, "Unsupported frame size: %d\n", 1978 frame_size); 1979 return -EINVAL; 1980 } 1981 1982 dev_dbg(dai->dev, "lrck is %dHz and pre_div is %d for iis %d\n", 1983 rt5682->lrck[dai->id], pre_div, dai->id); 1984 1985 switch (params_width(params)) { 1986 case 16: 1987 break; 1988 case 20: 1989 len_1 |= RT5682_I2S1_DL_20; 1990 len_2 |= RT5682_I2S2_DL_20; 1991 break; 1992 case 24: 1993 len_1 |= RT5682_I2S1_DL_24; 1994 len_2 |= RT5682_I2S2_DL_24; 1995 break; 1996 case 32: 1997 len_1 |= RT5682_I2S1_DL_32; 1998 len_2 |= RT5682_I2S2_DL_24; 1999 break; 2000 case 8: 2001 len_1 |= RT5682_I2S2_DL_8; 2002 len_2 |= RT5682_I2S2_DL_8; 2003 break; 2004 default: 2005 return -EINVAL; 2006 } 2007 2008 switch (dai->id) { 2009 case RT5682_AIF1: 2010 snd_soc_component_update_bits(component, RT5682_I2S1_SDP, 2011 RT5682_I2S1_DL_MASK, len_1); 2012 if (rt5682->master[RT5682_AIF1]) { 2013 snd_soc_component_update_bits(component, 2014 RT5682_ADDA_CLK_1, RT5682_I2S_M_DIV_MASK, 2015 pre_div << RT5682_I2S_M_DIV_SFT); 2016 } 2017 if (params_channels(params) == 1) /* mono mode */ 2018 snd_soc_component_update_bits(component, 2019 RT5682_I2S1_SDP, RT5682_I2S1_MONO_MASK, 2020 RT5682_I2S1_MONO_EN); 2021 else 2022 snd_soc_component_update_bits(component, 2023 RT5682_I2S1_SDP, RT5682_I2S1_MONO_MASK, 2024 RT5682_I2S1_MONO_DIS); 2025 break; 2026 case RT5682_AIF2: 2027 snd_soc_component_update_bits(component, RT5682_I2S2_SDP, 2028 RT5682_I2S2_DL_MASK, len_2); 2029 if (rt5682->master[RT5682_AIF2]) { 2030 snd_soc_component_update_bits(component, 2031 RT5682_I2S_M_CLK_CTRL_1, RT5682_I2S2_M_PD_MASK, 2032 pre_div << RT5682_I2S2_M_PD_SFT); 2033 } 2034 if (params_channels(params) == 1) /* mono mode */ 2035 snd_soc_component_update_bits(component, 2036 RT5682_I2S2_SDP, RT5682_I2S2_MONO_MASK, 2037 RT5682_I2S2_MONO_EN); 2038 else 2039 snd_soc_component_update_bits(component, 2040 RT5682_I2S2_SDP, RT5682_I2S2_MONO_MASK, 2041 RT5682_I2S2_MONO_DIS); 2042 break; 2043 default: 2044 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id); 2045 return -EINVAL; 2046 } 2047 2048 return 0; 2049 } 2050 2051 static int rt5682_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) 2052 { 2053 struct snd_soc_component *component = dai->component; 2054 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 2055 unsigned int reg_val = 0, tdm_ctrl = 0; 2056 2057 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 2058 case SND_SOC_DAIFMT_CBM_CFM: 2059 rt5682->master[dai->id] = 1; 2060 break; 2061 case SND_SOC_DAIFMT_CBS_CFS: 2062 rt5682->master[dai->id] = 0; 2063 break; 2064 default: 2065 return -EINVAL; 2066 } 2067 2068 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 2069 case SND_SOC_DAIFMT_NB_NF: 2070 break; 2071 case SND_SOC_DAIFMT_IB_NF: 2072 reg_val |= RT5682_I2S_BP_INV; 2073 tdm_ctrl |= RT5682_TDM_S_BP_INV; 2074 break; 2075 case SND_SOC_DAIFMT_NB_IF: 2076 if (dai->id == RT5682_AIF1) 2077 tdm_ctrl |= RT5682_TDM_S_LP_INV | RT5682_TDM_M_BP_INV; 2078 else 2079 return -EINVAL; 2080 break; 2081 case SND_SOC_DAIFMT_IB_IF: 2082 if (dai->id == RT5682_AIF1) 2083 tdm_ctrl |= RT5682_TDM_S_BP_INV | RT5682_TDM_S_LP_INV | 2084 RT5682_TDM_M_BP_INV | RT5682_TDM_M_LP_INV; 2085 else 2086 return -EINVAL; 2087 break; 2088 default: 2089 return -EINVAL; 2090 } 2091 2092 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 2093 case SND_SOC_DAIFMT_I2S: 2094 break; 2095 case SND_SOC_DAIFMT_LEFT_J: 2096 reg_val |= RT5682_I2S_DF_LEFT; 2097 tdm_ctrl |= RT5682_TDM_DF_LEFT; 2098 break; 2099 case SND_SOC_DAIFMT_DSP_A: 2100 reg_val |= RT5682_I2S_DF_PCM_A; 2101 tdm_ctrl |= RT5682_TDM_DF_PCM_A; 2102 break; 2103 case SND_SOC_DAIFMT_DSP_B: 2104 reg_val |= RT5682_I2S_DF_PCM_B; 2105 tdm_ctrl |= RT5682_TDM_DF_PCM_B; 2106 break; 2107 default: 2108 return -EINVAL; 2109 } 2110 2111 switch (dai->id) { 2112 case RT5682_AIF1: 2113 snd_soc_component_update_bits(component, RT5682_I2S1_SDP, 2114 RT5682_I2S_DF_MASK, reg_val); 2115 snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL, 2116 RT5682_TDM_MS_MASK | RT5682_TDM_S_BP_MASK | 2117 RT5682_TDM_DF_MASK | RT5682_TDM_M_BP_MASK | 2118 RT5682_TDM_M_LP_MASK | RT5682_TDM_S_LP_MASK, 2119 tdm_ctrl | rt5682->master[dai->id]); 2120 break; 2121 case RT5682_AIF2: 2122 if (rt5682->master[dai->id] == 0) 2123 reg_val |= RT5682_I2S2_MS_S; 2124 snd_soc_component_update_bits(component, RT5682_I2S2_SDP, 2125 RT5682_I2S2_MS_MASK | RT5682_I2S_BP_MASK | 2126 RT5682_I2S_DF_MASK, reg_val); 2127 break; 2128 default: 2129 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id); 2130 return -EINVAL; 2131 } 2132 return 0; 2133 } 2134 2135 static int rt5682_set_component_sysclk(struct snd_soc_component *component, 2136 int clk_id, int source, unsigned int freq, int dir) 2137 { 2138 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 2139 unsigned int reg_val = 0, src = 0; 2140 2141 if (freq == rt5682->sysclk && clk_id == rt5682->sysclk_src) 2142 return 0; 2143 2144 switch (clk_id) { 2145 case RT5682_SCLK_S_MCLK: 2146 reg_val |= RT5682_SCLK_SRC_MCLK; 2147 src = RT5682_CLK_SRC_MCLK; 2148 break; 2149 case RT5682_SCLK_S_PLL1: 2150 reg_val |= RT5682_SCLK_SRC_PLL1; 2151 src = RT5682_CLK_SRC_PLL1; 2152 break; 2153 case RT5682_SCLK_S_PLL2: 2154 reg_val |= RT5682_SCLK_SRC_PLL2; 2155 src = RT5682_CLK_SRC_PLL2; 2156 break; 2157 case RT5682_SCLK_S_RCCLK: 2158 reg_val |= RT5682_SCLK_SRC_RCCLK; 2159 src = RT5682_CLK_SRC_RCCLK; 2160 break; 2161 default: 2162 dev_err(component->dev, "Invalid clock id (%d)\n", clk_id); 2163 return -EINVAL; 2164 } 2165 snd_soc_component_update_bits(component, RT5682_GLB_CLK, 2166 RT5682_SCLK_SRC_MASK, reg_val); 2167 2168 if (rt5682->master[RT5682_AIF2]) { 2169 snd_soc_component_update_bits(component, 2170 RT5682_I2S_M_CLK_CTRL_1, RT5682_I2S2_SRC_MASK, 2171 src << RT5682_I2S2_SRC_SFT); 2172 } 2173 2174 rt5682->sysclk = freq; 2175 rt5682->sysclk_src = clk_id; 2176 2177 dev_dbg(component->dev, "Sysclk is %dHz and clock id is %d\n", 2178 freq, clk_id); 2179 2180 return 0; 2181 } 2182 2183 static int rt5682_set_component_pll(struct snd_soc_component *component, 2184 int pll_id, int source, unsigned int freq_in, 2185 unsigned int freq_out) 2186 { 2187 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 2188 struct rl6231_pll_code pll_code; 2189 int ret; 2190 2191 if (source == rt5682->pll_src && freq_in == rt5682->pll_in && 2192 freq_out == rt5682->pll_out) 2193 return 0; 2194 2195 if (!freq_in || !freq_out) { 2196 dev_dbg(component->dev, "PLL disabled\n"); 2197 2198 rt5682->pll_in = 0; 2199 rt5682->pll_out = 0; 2200 snd_soc_component_update_bits(component, RT5682_GLB_CLK, 2201 RT5682_SCLK_SRC_MASK, RT5682_SCLK_SRC_MCLK); 2202 return 0; 2203 } 2204 2205 switch (source) { 2206 case RT5682_PLL1_S_MCLK: 2207 snd_soc_component_update_bits(component, RT5682_GLB_CLK, 2208 RT5682_PLL1_SRC_MASK, RT5682_PLL1_SRC_MCLK); 2209 break; 2210 case RT5682_PLL1_S_BCLK1: 2211 snd_soc_component_update_bits(component, RT5682_GLB_CLK, 2212 RT5682_PLL1_SRC_MASK, RT5682_PLL1_SRC_BCLK1); 2213 break; 2214 default: 2215 dev_err(component->dev, "Unknown PLL Source %d\n", source); 2216 return -EINVAL; 2217 } 2218 2219 ret = rl6231_pll_calc(freq_in, freq_out, &pll_code); 2220 if (ret < 0) { 2221 dev_err(component->dev, "Unsupport input clock %d\n", freq_in); 2222 return ret; 2223 } 2224 2225 dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n", 2226 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code), 2227 pll_code.n_code, pll_code.k_code); 2228 2229 snd_soc_component_write(component, RT5682_PLL_CTRL_1, 2230 pll_code.n_code << RT5682_PLL_N_SFT | pll_code.k_code); 2231 snd_soc_component_write(component, RT5682_PLL_CTRL_2, 2232 (pll_code.m_bp ? 0 : pll_code.m_code) << RT5682_PLL_M_SFT | 2233 pll_code.m_bp << RT5682_PLL_M_BP_SFT | RT5682_PLL_RST); 2234 2235 rt5682->pll_in = freq_in; 2236 rt5682->pll_out = freq_out; 2237 rt5682->pll_src = source; 2238 2239 return 0; 2240 } 2241 2242 static int rt5682_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio) 2243 { 2244 struct snd_soc_component *component = dai->component; 2245 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 2246 2247 rt5682->bclk[dai->id] = ratio; 2248 2249 switch (ratio) { 2250 case 64: 2251 snd_soc_component_update_bits(component, RT5682_ADDA_CLK_2, 2252 RT5682_I2S2_BCLK_MS2_MASK, 2253 RT5682_I2S2_BCLK_MS2_64); 2254 break; 2255 case 32: 2256 snd_soc_component_update_bits(component, RT5682_ADDA_CLK_2, 2257 RT5682_I2S2_BCLK_MS2_MASK, 2258 RT5682_I2S2_BCLK_MS2_32); 2259 break; 2260 default: 2261 dev_err(dai->dev, "Invalid bclk ratio %d\n", ratio); 2262 return -EINVAL; 2263 } 2264 2265 return 0; 2266 } 2267 2268 static int rt5682_set_bias_level(struct snd_soc_component *component, 2269 enum snd_soc_bias_level level) 2270 { 2271 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 2272 2273 switch (level) { 2274 case SND_SOC_BIAS_PREPARE: 2275 regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_1, 2276 RT5682_PWR_MB | RT5682_PWR_BG, 2277 RT5682_PWR_MB | RT5682_PWR_BG); 2278 regmap_update_bits(rt5682->regmap, RT5682_PWR_DIG_1, 2279 RT5682_DIG_GATE_CTRL | RT5682_PWR_LDO, 2280 RT5682_DIG_GATE_CTRL | RT5682_PWR_LDO); 2281 break; 2282 2283 case SND_SOC_BIAS_STANDBY: 2284 regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_1, 2285 RT5682_PWR_MB, RT5682_PWR_MB); 2286 regmap_update_bits(rt5682->regmap, RT5682_PWR_DIG_1, 2287 RT5682_DIG_GATE_CTRL, RT5682_DIG_GATE_CTRL); 2288 break; 2289 case SND_SOC_BIAS_OFF: 2290 regmap_update_bits(rt5682->regmap, RT5682_PWR_DIG_1, 2291 RT5682_DIG_GATE_CTRL | RT5682_PWR_LDO, 0); 2292 regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_1, 2293 RT5682_PWR_MB | RT5682_PWR_BG, 0); 2294 break; 2295 2296 default: 2297 break; 2298 } 2299 2300 return 0; 2301 } 2302 2303 static int rt5682_probe(struct snd_soc_component *component) 2304 { 2305 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 2306 2307 rt5682->component = component; 2308 2309 return 0; 2310 } 2311 2312 static void rt5682_remove(struct snd_soc_component *component) 2313 { 2314 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 2315 2316 rt5682_reset(rt5682->regmap); 2317 } 2318 2319 #ifdef CONFIG_PM 2320 static int rt5682_suspend(struct snd_soc_component *component) 2321 { 2322 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 2323 2324 regcache_cache_only(rt5682->regmap, true); 2325 regcache_mark_dirty(rt5682->regmap); 2326 return 0; 2327 } 2328 2329 static int rt5682_resume(struct snd_soc_component *component) 2330 { 2331 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 2332 2333 regcache_cache_only(rt5682->regmap, false); 2334 regcache_sync(rt5682->regmap); 2335 2336 return 0; 2337 } 2338 #else 2339 #define rt5682_suspend NULL 2340 #define rt5682_resume NULL 2341 #endif 2342 2343 #define RT5682_STEREO_RATES SNDRV_PCM_RATE_8000_192000 2344 #define RT5682_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ 2345 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8) 2346 2347 static const struct snd_soc_dai_ops rt5682_aif1_dai_ops = { 2348 .hw_params = rt5682_hw_params, 2349 .set_fmt = rt5682_set_dai_fmt, 2350 .set_tdm_slot = rt5682_set_tdm_slot, 2351 }; 2352 2353 static const struct snd_soc_dai_ops rt5682_aif2_dai_ops = { 2354 .hw_params = rt5682_hw_params, 2355 .set_fmt = rt5682_set_dai_fmt, 2356 .set_bclk_ratio = rt5682_set_bclk_ratio, 2357 }; 2358 2359 static struct snd_soc_dai_driver rt5682_dai[] = { 2360 { 2361 .name = "rt5682-aif1", 2362 .id = RT5682_AIF1, 2363 .playback = { 2364 .stream_name = "AIF1 Playback", 2365 .channels_min = 1, 2366 .channels_max = 2, 2367 .rates = RT5682_STEREO_RATES, 2368 .formats = RT5682_FORMATS, 2369 }, 2370 .capture = { 2371 .stream_name = "AIF1 Capture", 2372 .channels_min = 1, 2373 .channels_max = 2, 2374 .rates = RT5682_STEREO_RATES, 2375 .formats = RT5682_FORMATS, 2376 }, 2377 .ops = &rt5682_aif1_dai_ops, 2378 }, 2379 { 2380 .name = "rt5682-aif2", 2381 .id = RT5682_AIF2, 2382 .capture = { 2383 .stream_name = "AIF2 Capture", 2384 .channels_min = 1, 2385 .channels_max = 2, 2386 .rates = RT5682_STEREO_RATES, 2387 .formats = RT5682_FORMATS, 2388 }, 2389 .ops = &rt5682_aif2_dai_ops, 2390 }, 2391 }; 2392 2393 static const struct snd_soc_component_driver soc_component_dev_rt5682 = { 2394 .probe = rt5682_probe, 2395 .remove = rt5682_remove, 2396 .suspend = rt5682_suspend, 2397 .resume = rt5682_resume, 2398 .set_bias_level = rt5682_set_bias_level, 2399 .controls = rt5682_snd_controls, 2400 .num_controls = ARRAY_SIZE(rt5682_snd_controls), 2401 .dapm_widgets = rt5682_dapm_widgets, 2402 .num_dapm_widgets = ARRAY_SIZE(rt5682_dapm_widgets), 2403 .dapm_routes = rt5682_dapm_routes, 2404 .num_dapm_routes = ARRAY_SIZE(rt5682_dapm_routes), 2405 .set_sysclk = rt5682_set_component_sysclk, 2406 .set_pll = rt5682_set_component_pll, 2407 .set_jack = rt5682_set_jack_detect, 2408 .use_pmdown_time = 1, 2409 .endianness = 1, 2410 .non_legacy_dai_naming = 1, 2411 }; 2412 2413 static const struct regmap_config rt5682_regmap = { 2414 .reg_bits = 16, 2415 .val_bits = 16, 2416 .max_register = RT5682_I2C_MODE, 2417 .volatile_reg = rt5682_volatile_register, 2418 .readable_reg = rt5682_readable_register, 2419 .cache_type = REGCACHE_RBTREE, 2420 .reg_defaults = rt5682_reg, 2421 .num_reg_defaults = ARRAY_SIZE(rt5682_reg), 2422 .use_single_rw = true, 2423 }; 2424 2425 static const struct i2c_device_id rt5682_i2c_id[] = { 2426 {"rt5682", 0}, 2427 {} 2428 }; 2429 MODULE_DEVICE_TABLE(i2c, rt5682_i2c_id); 2430 2431 static int rt5682_parse_dt(struct rt5682_priv *rt5682, struct device *dev) 2432 { 2433 2434 device_property_read_u32(dev, "realtek,dmic1-data-pin", 2435 &rt5682->pdata.dmic1_data_pin); 2436 device_property_read_u32(dev, "realtek,dmic1-clk-pin", 2437 &rt5682->pdata.dmic1_clk_pin); 2438 device_property_read_u32(dev, "realtek,jd-src", 2439 &rt5682->pdata.jd_src); 2440 2441 rt5682->pdata.ldo1_en = of_get_named_gpio(dev->of_node, 2442 "realtek,ldo1-en-gpios", 0); 2443 2444 return 0; 2445 } 2446 2447 static void rt5682_calibrate(struct rt5682_priv *rt5682) 2448 { 2449 int value, count; 2450 2451 mutex_lock(&rt5682->calibrate_mutex); 2452 2453 rt5682_reset(rt5682->regmap); 2454 regmap_write(rt5682->regmap, RT5682_PWR_ANLG_1, 0xa2bf); 2455 usleep_range(15000, 20000); 2456 regmap_write(rt5682->regmap, RT5682_PWR_ANLG_1, 0xf2bf); 2457 regmap_write(rt5682->regmap, RT5682_MICBIAS_2, 0x0380); 2458 regmap_write(rt5682->regmap, RT5682_PWR_DIG_1, 0x8001); 2459 regmap_write(rt5682->regmap, RT5682_TEST_MODE_CTRL_1, 0x0000); 2460 regmap_write(rt5682->regmap, RT5682_STO1_DAC_MIXER, 0x2080); 2461 regmap_write(rt5682->regmap, RT5682_STO1_ADC_MIXER, 0x4040); 2462 regmap_write(rt5682->regmap, RT5682_DEPOP_1, 0x0069); 2463 regmap_write(rt5682->regmap, RT5682_CHOP_DAC, 0x3000); 2464 regmap_write(rt5682->regmap, RT5682_HP_CTRL_2, 0x6000); 2465 regmap_write(rt5682->regmap, RT5682_HP_CHARGE_PUMP_1, 0x0f26); 2466 regmap_write(rt5682->regmap, RT5682_CALIB_ADC_CTRL, 0x7f05); 2467 regmap_write(rt5682->regmap, RT5682_STO1_ADC_MIXER, 0x686c); 2468 regmap_write(rt5682->regmap, RT5682_CAL_REC, 0x0d0d); 2469 regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_9, 0x000f); 2470 regmap_write(rt5682->regmap, RT5682_PWR_DIG_1, 0x8d01); 2471 regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_2, 0x0321); 2472 regmap_write(rt5682->regmap, RT5682_HP_LOGIC_CTRL_2, 0x0004); 2473 regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_1, 0x7c00); 2474 regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_3, 0x06a1); 2475 regmap_write(rt5682->regmap, RT5682_A_DAC1_MUX, 0x0311); 2476 regmap_write(rt5682->regmap, RT5682_RESET_HPF_CTRL, 0x0000); 2477 regmap_write(rt5682->regmap, RT5682_ADC_STO1_HP_CTRL_1, 0x3320); 2478 2479 regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_1, 0xfc00); 2480 2481 for (count = 0; count < 60; count++) { 2482 regmap_read(rt5682->regmap, RT5682_HP_CALIB_STA_1, &value); 2483 if (!(value & 0x8000)) 2484 break; 2485 2486 usleep_range(10000, 10005); 2487 } 2488 2489 if (count >= 60) 2490 pr_err("HP Calibration Failure\n"); 2491 2492 /* restore settings */ 2493 regmap_write(rt5682->regmap, RT5682_STO1_ADC_MIXER, 0xc0c4); 2494 regmap_write(rt5682->regmap, RT5682_PWR_DIG_1, 0x0000); 2495 2496 mutex_unlock(&rt5682->calibrate_mutex); 2497 2498 } 2499 2500 static int rt5682_i2c_probe(struct i2c_client *i2c, 2501 const struct i2c_device_id *id) 2502 { 2503 struct rt5682_platform_data *pdata = dev_get_platdata(&i2c->dev); 2504 struct rt5682_priv *rt5682; 2505 int i, ret; 2506 unsigned int val; 2507 2508 rt5682 = devm_kzalloc(&i2c->dev, sizeof(struct rt5682_priv), 2509 GFP_KERNEL); 2510 2511 if (rt5682 == NULL) 2512 return -ENOMEM; 2513 2514 i2c_set_clientdata(i2c, rt5682); 2515 2516 if (pdata) 2517 rt5682->pdata = *pdata; 2518 else 2519 rt5682_parse_dt(rt5682, &i2c->dev); 2520 2521 rt5682->regmap = devm_regmap_init_i2c(i2c, &rt5682_regmap); 2522 if (IS_ERR(rt5682->regmap)) { 2523 ret = PTR_ERR(rt5682->regmap); 2524 dev_err(&i2c->dev, "Failed to allocate register map: %d\n", 2525 ret); 2526 return ret; 2527 } 2528 2529 for (i = 0; i < ARRAY_SIZE(rt5682->supplies); i++) 2530 rt5682->supplies[i].supply = rt5682_supply_names[i]; 2531 2532 ret = devm_regulator_bulk_get(&i2c->dev, ARRAY_SIZE(rt5682->supplies), 2533 rt5682->supplies); 2534 if (ret != 0) { 2535 dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret); 2536 return ret; 2537 } 2538 2539 ret = regulator_bulk_enable(ARRAY_SIZE(rt5682->supplies), 2540 rt5682->supplies); 2541 if (ret != 0) { 2542 dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret); 2543 return ret; 2544 } 2545 2546 if (gpio_is_valid(rt5682->pdata.ldo1_en)) { 2547 if (devm_gpio_request_one(&i2c->dev, rt5682->pdata.ldo1_en, 2548 GPIOF_OUT_INIT_HIGH, "rt5682")) 2549 dev_err(&i2c->dev, "Fail gpio_request gpio_ldo\n"); 2550 } 2551 2552 /* Sleep for 300 ms miniumum */ 2553 usleep_range(300000, 350000); 2554 2555 regmap_write(rt5682->regmap, RT5682_I2C_MODE, 0x1); 2556 usleep_range(10000, 15000); 2557 2558 regmap_read(rt5682->regmap, RT5682_DEVICE_ID, &val); 2559 if (val != DEVICE_ID) { 2560 pr_err("Device with ID register %x is not rt5682\n", val); 2561 return -ENODEV; 2562 } 2563 2564 rt5682_reset(rt5682->regmap); 2565 2566 rt5682_calibrate(rt5682); 2567 2568 ret = regmap_register_patch(rt5682->regmap, patch_list, 2569 ARRAY_SIZE(patch_list)); 2570 if (ret != 0) 2571 dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret); 2572 2573 regmap_write(rt5682->regmap, RT5682_DEPOP_1, 0x0000); 2574 2575 /* DMIC pin*/ 2576 if (rt5682->pdata.dmic1_data_pin != RT5682_DMIC1_NULL) { 2577 switch (rt5682->pdata.dmic1_data_pin) { 2578 case RT5682_DMIC1_DATA_GPIO2: /* share with LRCK2 */ 2579 regmap_update_bits(rt5682->regmap, RT5682_DMIC_CTRL_1, 2580 RT5682_DMIC_1_DP_MASK, RT5682_DMIC_1_DP_GPIO2); 2581 regmap_update_bits(rt5682->regmap, RT5682_GPIO_CTRL_1, 2582 RT5682_GP2_PIN_MASK, RT5682_GP2_PIN_DMIC_SDA); 2583 break; 2584 2585 case RT5682_DMIC1_DATA_GPIO5: /* share with DACDAT1 */ 2586 regmap_update_bits(rt5682->regmap, RT5682_DMIC_CTRL_1, 2587 RT5682_DMIC_1_DP_MASK, RT5682_DMIC_1_DP_GPIO5); 2588 regmap_update_bits(rt5682->regmap, RT5682_GPIO_CTRL_1, 2589 RT5682_GP5_PIN_MASK, RT5682_GP5_PIN_DMIC_SDA); 2590 break; 2591 2592 default: 2593 dev_warn(&i2c->dev, "invalid DMIC_DAT pin\n"); 2594 break; 2595 } 2596 2597 switch (rt5682->pdata.dmic1_clk_pin) { 2598 case RT5682_DMIC1_CLK_GPIO1: /* share with IRQ */ 2599 regmap_update_bits(rt5682->regmap, RT5682_GPIO_CTRL_1, 2600 RT5682_GP1_PIN_MASK, RT5682_GP1_PIN_DMIC_CLK); 2601 break; 2602 2603 case RT5682_DMIC1_CLK_GPIO3: /* share with BCLK2 */ 2604 regmap_update_bits(rt5682->regmap, RT5682_GPIO_CTRL_1, 2605 RT5682_GP3_PIN_MASK, RT5682_GP3_PIN_DMIC_CLK); 2606 break; 2607 2608 default: 2609 dev_warn(&i2c->dev, "invalid DMIC_CLK pin\n"); 2610 break; 2611 } 2612 } 2613 2614 regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_1, 2615 RT5682_LDO1_DVO_MASK | RT5682_HP_DRIVER_MASK, 2616 RT5682_LDO1_DVO_12 | RT5682_HP_DRIVER_5X); 2617 regmap_write(rt5682->regmap, RT5682_MICBIAS_2, 0x0380); 2618 regmap_update_bits(rt5682->regmap, RT5682_GPIO_CTRL_1, 2619 RT5682_GP4_PIN_MASK | RT5682_GP5_PIN_MASK, 2620 RT5682_GP4_PIN_ADCDAT1 | RT5682_GP5_PIN_DACDAT1); 2621 regmap_write(rt5682->regmap, RT5682_TEST_MODE_CTRL_1, 0x0000); 2622 2623 INIT_DELAYED_WORK(&rt5682->jack_detect_work, 2624 rt5682_jack_detect_handler); 2625 INIT_DELAYED_WORK(&rt5682->jd_check_work, 2626 rt5682_jd_check_handler); 2627 2628 mutex_init(&rt5682->calibrate_mutex); 2629 2630 if (i2c->irq) { 2631 ret = devm_request_threaded_irq(&i2c->dev, i2c->irq, NULL, 2632 rt5682_irq, IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING 2633 | IRQF_ONESHOT, "rt5682", rt5682); 2634 if (ret) 2635 dev_err(&i2c->dev, "Failed to reguest IRQ: %d\n", ret); 2636 2637 } 2638 2639 return devm_snd_soc_register_component(&i2c->dev, 2640 &soc_component_dev_rt5682, 2641 rt5682_dai, ARRAY_SIZE(rt5682_dai)); 2642 } 2643 2644 static void rt5682_i2c_shutdown(struct i2c_client *client) 2645 { 2646 struct rt5682_priv *rt5682 = i2c_get_clientdata(client); 2647 2648 rt5682_reset(rt5682->regmap); 2649 } 2650 2651 #ifdef CONFIG_OF 2652 static const struct of_device_id rt5682_of_match[] = { 2653 {.compatible = "realtek,rt5682i"}, 2654 {}, 2655 }; 2656 MODULE_DEVICE_TABLE(of, rt5682_of_match); 2657 #endif 2658 2659 #ifdef CONFIG_ACPI 2660 static const struct acpi_device_id rt5682_acpi_match[] = { 2661 {"10EC5682", 0,}, 2662 {}, 2663 }; 2664 MODULE_DEVICE_TABLE(acpi, rt5682_acpi_match); 2665 #endif 2666 2667 static struct i2c_driver rt5682_i2c_driver = { 2668 .driver = { 2669 .name = "rt5682", 2670 .of_match_table = of_match_ptr(rt5682_of_match), 2671 .acpi_match_table = ACPI_PTR(rt5682_acpi_match), 2672 }, 2673 .probe = rt5682_i2c_probe, 2674 .shutdown = rt5682_i2c_shutdown, 2675 .id_table = rt5682_i2c_id, 2676 }; 2677 module_i2c_driver(rt5682_i2c_driver); 2678 2679 MODULE_DESCRIPTION("ASoC RT5682 driver"); 2680 MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>"); 2681 MODULE_LICENSE("GPL v2"); 2682