1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * rt5682.c -- RT5682 ALSA SoC audio component driver 4 * 5 * Copyright 2018 Realtek Semiconductor Corp. 6 * Author: Bard Liao <bardliao@realtek.com> 7 */ 8 9 #include <linux/module.h> 10 #include <linux/moduleparam.h> 11 #include <linux/init.h> 12 #include <linux/delay.h> 13 #include <linux/pm.h> 14 #include <linux/pm_runtime.h> 15 #include <linux/i2c.h> 16 #include <linux/platform_device.h> 17 #include <linux/spi/spi.h> 18 #include <linux/acpi.h> 19 #include <linux/gpio.h> 20 #include <linux/of_gpio.h> 21 #include <linux/mutex.h> 22 #include <sound/core.h> 23 #include <sound/pcm.h> 24 #include <sound/pcm_params.h> 25 #include <sound/jack.h> 26 #include <sound/soc.h> 27 #include <sound/soc-dapm.h> 28 #include <sound/initval.h> 29 #include <sound/tlv.h> 30 #include <sound/rt5682.h> 31 32 #include "rl6231.h" 33 #include "rt5682.h" 34 #include "rt5682-sdw.h" 35 36 static const char *rt5682_supply_names[RT5682_NUM_SUPPLIES] = { 37 "AVDD", 38 "MICVDD", 39 "VBAT", 40 }; 41 42 static const struct rt5682_platform_data i2s_default_platform_data = { 43 .dmic1_data_pin = RT5682_DMIC1_DATA_GPIO2, 44 .dmic1_clk_pin = RT5682_DMIC1_CLK_GPIO3, 45 .jd_src = RT5682_JD1, 46 .btndet_delay = 16, 47 .dai_clk_names[RT5682_DAI_WCLK_IDX] = "rt5682-dai-wclk", 48 .dai_clk_names[RT5682_DAI_BCLK_IDX] = "rt5682-dai-bclk", 49 }; 50 51 static const struct reg_sequence patch_list[] = { 52 {RT5682_HP_IMP_SENS_CTRL_19, 0x1000}, 53 {RT5682_DAC_ADC_DIG_VOL1, 0xa020}, 54 {RT5682_I2C_CTRL, 0x000f}, 55 {RT5682_PLL2_INTERNAL, 0x8266}, 56 }; 57 58 static const struct reg_default rt5682_reg[] = { 59 {0x0002, 0x8080}, 60 {0x0003, 0x8000}, 61 {0x0005, 0x0000}, 62 {0x0006, 0x0000}, 63 {0x0008, 0x800f}, 64 {0x000b, 0x0000}, 65 {0x0010, 0x4040}, 66 {0x0011, 0x0000}, 67 {0x0012, 0x1404}, 68 {0x0013, 0x1000}, 69 {0x0014, 0xa00a}, 70 {0x0015, 0x0404}, 71 {0x0016, 0x0404}, 72 {0x0019, 0xafaf}, 73 {0x001c, 0x2f2f}, 74 {0x001f, 0x0000}, 75 {0x0022, 0x5757}, 76 {0x0023, 0x0039}, 77 {0x0024, 0x000b}, 78 {0x0026, 0xc0c4}, 79 {0x0029, 0x8080}, 80 {0x002a, 0xa0a0}, 81 {0x002b, 0x0300}, 82 {0x0030, 0x0000}, 83 {0x003c, 0x0080}, 84 {0x0044, 0x0c0c}, 85 {0x0049, 0x0000}, 86 {0x0061, 0x0000}, 87 {0x0062, 0x0000}, 88 {0x0063, 0x003f}, 89 {0x0064, 0x0000}, 90 {0x0065, 0x0000}, 91 {0x0066, 0x0030}, 92 {0x0067, 0x0000}, 93 {0x006b, 0x0000}, 94 {0x006c, 0x0000}, 95 {0x006d, 0x2200}, 96 {0x006e, 0x0a10}, 97 {0x0070, 0x8000}, 98 {0x0071, 0x8000}, 99 {0x0073, 0x0000}, 100 {0x0074, 0x0000}, 101 {0x0075, 0x0002}, 102 {0x0076, 0x0001}, 103 {0x0079, 0x0000}, 104 {0x007a, 0x0000}, 105 {0x007b, 0x0000}, 106 {0x007c, 0x0100}, 107 {0x007e, 0x0000}, 108 {0x0080, 0x0000}, 109 {0x0081, 0x0000}, 110 {0x0082, 0x0000}, 111 {0x0083, 0x0000}, 112 {0x0084, 0x0000}, 113 {0x0085, 0x0000}, 114 {0x0086, 0x0005}, 115 {0x0087, 0x0000}, 116 {0x0088, 0x0000}, 117 {0x008c, 0x0003}, 118 {0x008d, 0x0000}, 119 {0x008e, 0x0060}, 120 {0x008f, 0x1000}, 121 {0x0091, 0x0c26}, 122 {0x0092, 0x0073}, 123 {0x0093, 0x0000}, 124 {0x0094, 0x0080}, 125 {0x0098, 0x0000}, 126 {0x009a, 0x0000}, 127 {0x009b, 0x0000}, 128 {0x009c, 0x0000}, 129 {0x009d, 0x0000}, 130 {0x009e, 0x100c}, 131 {0x009f, 0x0000}, 132 {0x00a0, 0x0000}, 133 {0x00a3, 0x0002}, 134 {0x00a4, 0x0001}, 135 {0x00ae, 0x2040}, 136 {0x00af, 0x0000}, 137 {0x00b6, 0x0000}, 138 {0x00b7, 0x0000}, 139 {0x00b8, 0x0000}, 140 {0x00b9, 0x0002}, 141 {0x00be, 0x0000}, 142 {0x00c0, 0x0160}, 143 {0x00c1, 0x82a0}, 144 {0x00c2, 0x0000}, 145 {0x00d0, 0x0000}, 146 {0x00d1, 0x2244}, 147 {0x00d2, 0x3300}, 148 {0x00d3, 0x2200}, 149 {0x00d4, 0x0000}, 150 {0x00d9, 0x0009}, 151 {0x00da, 0x0000}, 152 {0x00db, 0x0000}, 153 {0x00dc, 0x00c0}, 154 {0x00dd, 0x2220}, 155 {0x00de, 0x3131}, 156 {0x00df, 0x3131}, 157 {0x00e0, 0x3131}, 158 {0x00e2, 0x0000}, 159 {0x00e3, 0x4000}, 160 {0x00e4, 0x0aa0}, 161 {0x00e5, 0x3131}, 162 {0x00e6, 0x3131}, 163 {0x00e7, 0x3131}, 164 {0x00e8, 0x3131}, 165 {0x00ea, 0xb320}, 166 {0x00eb, 0x0000}, 167 {0x00f0, 0x0000}, 168 {0x00f1, 0x00d0}, 169 {0x00f2, 0x00d0}, 170 {0x00f6, 0x0000}, 171 {0x00fa, 0x0000}, 172 {0x00fb, 0x0000}, 173 {0x00fc, 0x0000}, 174 {0x00fd, 0x0000}, 175 {0x00fe, 0x10ec}, 176 {0x00ff, 0x6530}, 177 {0x0100, 0xa0a0}, 178 {0x010b, 0x0000}, 179 {0x010c, 0xae00}, 180 {0x010d, 0xaaa0}, 181 {0x010e, 0x8aa2}, 182 {0x010f, 0x02a2}, 183 {0x0110, 0xc000}, 184 {0x0111, 0x04a2}, 185 {0x0112, 0x2800}, 186 {0x0113, 0x0000}, 187 {0x0117, 0x0100}, 188 {0x0125, 0x0410}, 189 {0x0132, 0x6026}, 190 {0x0136, 0x5555}, 191 {0x0138, 0x3700}, 192 {0x013a, 0x2000}, 193 {0x013b, 0x2000}, 194 {0x013c, 0x2005}, 195 {0x013f, 0x0000}, 196 {0x0142, 0x0000}, 197 {0x0145, 0x0002}, 198 {0x0146, 0x0000}, 199 {0x0147, 0x0000}, 200 {0x0148, 0x0000}, 201 {0x0149, 0x0000}, 202 {0x0150, 0x79a1}, 203 {0x0156, 0xaaaa}, 204 {0x0160, 0x4ec0}, 205 {0x0161, 0x0080}, 206 {0x0162, 0x0200}, 207 {0x0163, 0x0800}, 208 {0x0164, 0x0000}, 209 {0x0165, 0x0000}, 210 {0x0166, 0x0000}, 211 {0x0167, 0x000f}, 212 {0x0168, 0x000f}, 213 {0x0169, 0x0021}, 214 {0x0190, 0x413d}, 215 {0x0194, 0x0000}, 216 {0x0195, 0x0000}, 217 {0x0197, 0x0022}, 218 {0x0198, 0x0000}, 219 {0x0199, 0x0000}, 220 {0x01af, 0x0000}, 221 {0x01b0, 0x0400}, 222 {0x01b1, 0x0000}, 223 {0x01b2, 0x0000}, 224 {0x01b3, 0x0000}, 225 {0x01b4, 0x0000}, 226 {0x01b5, 0x0000}, 227 {0x01b6, 0x01c3}, 228 {0x01b7, 0x02a0}, 229 {0x01b8, 0x03e9}, 230 {0x01b9, 0x1389}, 231 {0x01ba, 0xc351}, 232 {0x01bb, 0x0009}, 233 {0x01bc, 0x0018}, 234 {0x01bd, 0x002a}, 235 {0x01be, 0x004c}, 236 {0x01bf, 0x0097}, 237 {0x01c0, 0x433d}, 238 {0x01c2, 0x0000}, 239 {0x01c3, 0x0000}, 240 {0x01c4, 0x0000}, 241 {0x01c5, 0x0000}, 242 {0x01c6, 0x0000}, 243 {0x01c7, 0x0000}, 244 {0x01c8, 0x40af}, 245 {0x01c9, 0x0702}, 246 {0x01ca, 0x0000}, 247 {0x01cb, 0x0000}, 248 {0x01cc, 0x5757}, 249 {0x01cd, 0x5757}, 250 {0x01ce, 0x5757}, 251 {0x01cf, 0x5757}, 252 {0x01d0, 0x5757}, 253 {0x01d1, 0x5757}, 254 {0x01d2, 0x5757}, 255 {0x01d3, 0x5757}, 256 {0x01d4, 0x5757}, 257 {0x01d5, 0x5757}, 258 {0x01d6, 0x0000}, 259 {0x01d7, 0x0008}, 260 {0x01d8, 0x0029}, 261 {0x01d9, 0x3333}, 262 {0x01da, 0x0000}, 263 {0x01db, 0x0004}, 264 {0x01dc, 0x0000}, 265 {0x01de, 0x7c00}, 266 {0x01df, 0x0320}, 267 {0x01e0, 0x06a1}, 268 {0x01e1, 0x0000}, 269 {0x01e2, 0x0000}, 270 {0x01e3, 0x0000}, 271 {0x01e4, 0x0000}, 272 {0x01e6, 0x0001}, 273 {0x01e7, 0x0000}, 274 {0x01e8, 0x0000}, 275 {0x01ea, 0x0000}, 276 {0x01eb, 0x0000}, 277 {0x01ec, 0x0000}, 278 {0x01ed, 0x0000}, 279 {0x01ee, 0x0000}, 280 {0x01ef, 0x0000}, 281 {0x01f0, 0x0000}, 282 {0x01f1, 0x0000}, 283 {0x01f2, 0x0000}, 284 {0x01f3, 0x0000}, 285 {0x01f4, 0x0000}, 286 {0x0210, 0x6297}, 287 {0x0211, 0xa005}, 288 {0x0212, 0x824c}, 289 {0x0213, 0xf7ff}, 290 {0x0214, 0xf24c}, 291 {0x0215, 0x0102}, 292 {0x0216, 0x00a3}, 293 {0x0217, 0x0048}, 294 {0x0218, 0xa2c0}, 295 {0x0219, 0x0400}, 296 {0x021a, 0x00c8}, 297 {0x021b, 0x00c0}, 298 {0x021c, 0x0000}, 299 {0x0250, 0x4500}, 300 {0x0251, 0x40b3}, 301 {0x0252, 0x0000}, 302 {0x0253, 0x0000}, 303 {0x0254, 0x0000}, 304 {0x0255, 0x0000}, 305 {0x0256, 0x0000}, 306 {0x0257, 0x0000}, 307 {0x0258, 0x0000}, 308 {0x0259, 0x0000}, 309 {0x025a, 0x0005}, 310 {0x0270, 0x0000}, 311 {0x02ff, 0x0110}, 312 {0x0300, 0x001f}, 313 {0x0301, 0x032c}, 314 {0x0302, 0x5f21}, 315 {0x0303, 0x4000}, 316 {0x0304, 0x4000}, 317 {0x0305, 0x06d5}, 318 {0x0306, 0x8000}, 319 {0x0307, 0x0700}, 320 {0x0310, 0x4560}, 321 {0x0311, 0xa4a8}, 322 {0x0312, 0x7418}, 323 {0x0313, 0x0000}, 324 {0x0314, 0x0006}, 325 {0x0315, 0xffff}, 326 {0x0316, 0xc400}, 327 {0x0317, 0x0000}, 328 {0x03c0, 0x7e00}, 329 {0x03c1, 0x8000}, 330 {0x03c2, 0x8000}, 331 {0x03c3, 0x8000}, 332 {0x03c4, 0x8000}, 333 {0x03c5, 0x8000}, 334 {0x03c6, 0x8000}, 335 {0x03c7, 0x8000}, 336 {0x03c8, 0x8000}, 337 {0x03c9, 0x8000}, 338 {0x03ca, 0x8000}, 339 {0x03cb, 0x8000}, 340 {0x03cc, 0x8000}, 341 {0x03d0, 0x0000}, 342 {0x03d1, 0x0000}, 343 {0x03d2, 0x0000}, 344 {0x03d3, 0x0000}, 345 {0x03d4, 0x2000}, 346 {0x03d5, 0x2000}, 347 {0x03d6, 0x0000}, 348 {0x03d7, 0x0000}, 349 {0x03d8, 0x2000}, 350 {0x03d9, 0x2000}, 351 {0x03da, 0x2000}, 352 {0x03db, 0x2000}, 353 {0x03dc, 0x0000}, 354 {0x03dd, 0x0000}, 355 {0x03de, 0x0000}, 356 {0x03df, 0x2000}, 357 {0x03e0, 0x0000}, 358 {0x03e1, 0x0000}, 359 {0x03e2, 0x0000}, 360 {0x03e3, 0x0000}, 361 {0x03e4, 0x0000}, 362 {0x03e5, 0x0000}, 363 {0x03e6, 0x0000}, 364 {0x03e7, 0x0000}, 365 {0x03e8, 0x0000}, 366 {0x03e9, 0x0000}, 367 {0x03ea, 0x0000}, 368 {0x03eb, 0x0000}, 369 {0x03ec, 0x0000}, 370 {0x03ed, 0x0000}, 371 {0x03ee, 0x0000}, 372 {0x03ef, 0x0000}, 373 {0x03f0, 0x0800}, 374 {0x03f1, 0x0800}, 375 {0x03f2, 0x0800}, 376 {0x03f3, 0x0800}, 377 }; 378 379 static bool rt5682_volatile_register(struct device *dev, unsigned int reg) 380 { 381 switch (reg) { 382 case RT5682_RESET: 383 case RT5682_CBJ_CTRL_2: 384 case RT5682_INT_ST_1: 385 case RT5682_4BTN_IL_CMD_1: 386 case RT5682_AJD1_CTRL: 387 case RT5682_HP_CALIB_CTRL_1: 388 case RT5682_DEVICE_ID: 389 case RT5682_I2C_MODE: 390 case RT5682_HP_CALIB_CTRL_10: 391 case RT5682_EFUSE_CTRL_2: 392 case RT5682_JD_TOP_VC_VTRL: 393 case RT5682_HP_IMP_SENS_CTRL_19: 394 case RT5682_IL_CMD_1: 395 case RT5682_SAR_IL_CMD_2: 396 case RT5682_SAR_IL_CMD_4: 397 case RT5682_SAR_IL_CMD_10: 398 case RT5682_SAR_IL_CMD_11: 399 case RT5682_EFUSE_CTRL_6...RT5682_EFUSE_CTRL_11: 400 case RT5682_HP_CALIB_STA_1...RT5682_HP_CALIB_STA_11: 401 return true; 402 default: 403 return false; 404 } 405 } 406 407 static bool rt5682_readable_register(struct device *dev, unsigned int reg) 408 { 409 switch (reg) { 410 case RT5682_RESET: 411 case RT5682_VERSION_ID: 412 case RT5682_VENDOR_ID: 413 case RT5682_DEVICE_ID: 414 case RT5682_HP_CTRL_1: 415 case RT5682_HP_CTRL_2: 416 case RT5682_HPL_GAIN: 417 case RT5682_HPR_GAIN: 418 case RT5682_I2C_CTRL: 419 case RT5682_CBJ_BST_CTRL: 420 case RT5682_CBJ_CTRL_1: 421 case RT5682_CBJ_CTRL_2: 422 case RT5682_CBJ_CTRL_3: 423 case RT5682_CBJ_CTRL_4: 424 case RT5682_CBJ_CTRL_5: 425 case RT5682_CBJ_CTRL_6: 426 case RT5682_CBJ_CTRL_7: 427 case RT5682_DAC1_DIG_VOL: 428 case RT5682_STO1_ADC_DIG_VOL: 429 case RT5682_STO1_ADC_BOOST: 430 case RT5682_HP_IMP_GAIN_1: 431 case RT5682_HP_IMP_GAIN_2: 432 case RT5682_SIDETONE_CTRL: 433 case RT5682_STO1_ADC_MIXER: 434 case RT5682_AD_DA_MIXER: 435 case RT5682_STO1_DAC_MIXER: 436 case RT5682_A_DAC1_MUX: 437 case RT5682_DIG_INF2_DATA: 438 case RT5682_REC_MIXER: 439 case RT5682_CAL_REC: 440 case RT5682_ALC_BACK_GAIN: 441 case RT5682_PWR_DIG_1: 442 case RT5682_PWR_DIG_2: 443 case RT5682_PWR_ANLG_1: 444 case RT5682_PWR_ANLG_2: 445 case RT5682_PWR_ANLG_3: 446 case RT5682_PWR_MIXER: 447 case RT5682_PWR_VOL: 448 case RT5682_CLK_DET: 449 case RT5682_RESET_LPF_CTRL: 450 case RT5682_RESET_HPF_CTRL: 451 case RT5682_DMIC_CTRL_1: 452 case RT5682_I2S1_SDP: 453 case RT5682_I2S2_SDP: 454 case RT5682_ADDA_CLK_1: 455 case RT5682_ADDA_CLK_2: 456 case RT5682_I2S1_F_DIV_CTRL_1: 457 case RT5682_I2S1_F_DIV_CTRL_2: 458 case RT5682_TDM_CTRL: 459 case RT5682_TDM_ADDA_CTRL_1: 460 case RT5682_TDM_ADDA_CTRL_2: 461 case RT5682_DATA_SEL_CTRL_1: 462 case RT5682_TDM_TCON_CTRL: 463 case RT5682_GLB_CLK: 464 case RT5682_PLL_CTRL_1: 465 case RT5682_PLL_CTRL_2: 466 case RT5682_PLL_TRACK_1: 467 case RT5682_PLL_TRACK_2: 468 case RT5682_PLL_TRACK_3: 469 case RT5682_PLL_TRACK_4: 470 case RT5682_PLL_TRACK_5: 471 case RT5682_PLL_TRACK_6: 472 case RT5682_PLL_TRACK_11: 473 case RT5682_SDW_REF_CLK: 474 case RT5682_DEPOP_1: 475 case RT5682_DEPOP_2: 476 case RT5682_HP_CHARGE_PUMP_1: 477 case RT5682_HP_CHARGE_PUMP_2: 478 case RT5682_MICBIAS_1: 479 case RT5682_MICBIAS_2: 480 case RT5682_PLL_TRACK_12: 481 case RT5682_PLL_TRACK_14: 482 case RT5682_PLL2_CTRL_1: 483 case RT5682_PLL2_CTRL_2: 484 case RT5682_PLL2_CTRL_3: 485 case RT5682_PLL2_CTRL_4: 486 case RT5682_RC_CLK_CTRL: 487 case RT5682_I2S_M_CLK_CTRL_1: 488 case RT5682_I2S2_F_DIV_CTRL_1: 489 case RT5682_I2S2_F_DIV_CTRL_2: 490 case RT5682_EQ_CTRL_1: 491 case RT5682_EQ_CTRL_2: 492 case RT5682_IRQ_CTRL_1: 493 case RT5682_IRQ_CTRL_2: 494 case RT5682_IRQ_CTRL_3: 495 case RT5682_IRQ_CTRL_4: 496 case RT5682_INT_ST_1: 497 case RT5682_GPIO_CTRL_1: 498 case RT5682_GPIO_CTRL_2: 499 case RT5682_GPIO_CTRL_3: 500 case RT5682_HP_AMP_DET_CTRL_1: 501 case RT5682_HP_AMP_DET_CTRL_2: 502 case RT5682_MID_HP_AMP_DET: 503 case RT5682_LOW_HP_AMP_DET: 504 case RT5682_DELAY_BUF_CTRL: 505 case RT5682_SV_ZCD_1: 506 case RT5682_SV_ZCD_2: 507 case RT5682_IL_CMD_1: 508 case RT5682_IL_CMD_2: 509 case RT5682_IL_CMD_3: 510 case RT5682_IL_CMD_4: 511 case RT5682_IL_CMD_5: 512 case RT5682_IL_CMD_6: 513 case RT5682_4BTN_IL_CMD_1: 514 case RT5682_4BTN_IL_CMD_2: 515 case RT5682_4BTN_IL_CMD_3: 516 case RT5682_4BTN_IL_CMD_4: 517 case RT5682_4BTN_IL_CMD_5: 518 case RT5682_4BTN_IL_CMD_6: 519 case RT5682_4BTN_IL_CMD_7: 520 case RT5682_ADC_STO1_HP_CTRL_1: 521 case RT5682_ADC_STO1_HP_CTRL_2: 522 case RT5682_AJD1_CTRL: 523 case RT5682_JD1_THD: 524 case RT5682_JD2_THD: 525 case RT5682_JD_CTRL_1: 526 case RT5682_DUMMY_1: 527 case RT5682_DUMMY_2: 528 case RT5682_DUMMY_3: 529 case RT5682_DAC_ADC_DIG_VOL1: 530 case RT5682_BIAS_CUR_CTRL_2: 531 case RT5682_BIAS_CUR_CTRL_3: 532 case RT5682_BIAS_CUR_CTRL_4: 533 case RT5682_BIAS_CUR_CTRL_5: 534 case RT5682_BIAS_CUR_CTRL_6: 535 case RT5682_BIAS_CUR_CTRL_7: 536 case RT5682_BIAS_CUR_CTRL_8: 537 case RT5682_BIAS_CUR_CTRL_9: 538 case RT5682_BIAS_CUR_CTRL_10: 539 case RT5682_VREF_REC_OP_FB_CAP_CTRL: 540 case RT5682_CHARGE_PUMP_1: 541 case RT5682_DIG_IN_CTRL_1: 542 case RT5682_PAD_DRIVING_CTRL: 543 case RT5682_SOFT_RAMP_DEPOP: 544 case RT5682_CHOP_DAC: 545 case RT5682_CHOP_ADC: 546 case RT5682_CALIB_ADC_CTRL: 547 case RT5682_VOL_TEST: 548 case RT5682_SPKVDD_DET_STA: 549 case RT5682_TEST_MODE_CTRL_1: 550 case RT5682_TEST_MODE_CTRL_2: 551 case RT5682_TEST_MODE_CTRL_3: 552 case RT5682_TEST_MODE_CTRL_4: 553 case RT5682_TEST_MODE_CTRL_5: 554 case RT5682_PLL1_INTERNAL: 555 case RT5682_PLL2_INTERNAL: 556 case RT5682_STO_NG2_CTRL_1: 557 case RT5682_STO_NG2_CTRL_2: 558 case RT5682_STO_NG2_CTRL_3: 559 case RT5682_STO_NG2_CTRL_4: 560 case RT5682_STO_NG2_CTRL_5: 561 case RT5682_STO_NG2_CTRL_6: 562 case RT5682_STO_NG2_CTRL_7: 563 case RT5682_STO_NG2_CTRL_8: 564 case RT5682_STO_NG2_CTRL_9: 565 case RT5682_STO_NG2_CTRL_10: 566 case RT5682_STO1_DAC_SIL_DET: 567 case RT5682_SIL_PSV_CTRL1: 568 case RT5682_SIL_PSV_CTRL2: 569 case RT5682_SIL_PSV_CTRL3: 570 case RT5682_SIL_PSV_CTRL4: 571 case RT5682_SIL_PSV_CTRL5: 572 case RT5682_HP_IMP_SENS_CTRL_01: 573 case RT5682_HP_IMP_SENS_CTRL_02: 574 case RT5682_HP_IMP_SENS_CTRL_03: 575 case RT5682_HP_IMP_SENS_CTRL_04: 576 case RT5682_HP_IMP_SENS_CTRL_05: 577 case RT5682_HP_IMP_SENS_CTRL_06: 578 case RT5682_HP_IMP_SENS_CTRL_07: 579 case RT5682_HP_IMP_SENS_CTRL_08: 580 case RT5682_HP_IMP_SENS_CTRL_09: 581 case RT5682_HP_IMP_SENS_CTRL_10: 582 case RT5682_HP_IMP_SENS_CTRL_11: 583 case RT5682_HP_IMP_SENS_CTRL_12: 584 case RT5682_HP_IMP_SENS_CTRL_13: 585 case RT5682_HP_IMP_SENS_CTRL_14: 586 case RT5682_HP_IMP_SENS_CTRL_15: 587 case RT5682_HP_IMP_SENS_CTRL_16: 588 case RT5682_HP_IMP_SENS_CTRL_17: 589 case RT5682_HP_IMP_SENS_CTRL_18: 590 case RT5682_HP_IMP_SENS_CTRL_19: 591 case RT5682_HP_IMP_SENS_CTRL_20: 592 case RT5682_HP_IMP_SENS_CTRL_21: 593 case RT5682_HP_IMP_SENS_CTRL_22: 594 case RT5682_HP_IMP_SENS_CTRL_23: 595 case RT5682_HP_IMP_SENS_CTRL_24: 596 case RT5682_HP_IMP_SENS_CTRL_25: 597 case RT5682_HP_IMP_SENS_CTRL_26: 598 case RT5682_HP_IMP_SENS_CTRL_27: 599 case RT5682_HP_IMP_SENS_CTRL_28: 600 case RT5682_HP_IMP_SENS_CTRL_29: 601 case RT5682_HP_IMP_SENS_CTRL_30: 602 case RT5682_HP_IMP_SENS_CTRL_31: 603 case RT5682_HP_IMP_SENS_CTRL_32: 604 case RT5682_HP_IMP_SENS_CTRL_33: 605 case RT5682_HP_IMP_SENS_CTRL_34: 606 case RT5682_HP_IMP_SENS_CTRL_35: 607 case RT5682_HP_IMP_SENS_CTRL_36: 608 case RT5682_HP_IMP_SENS_CTRL_37: 609 case RT5682_HP_IMP_SENS_CTRL_38: 610 case RT5682_HP_IMP_SENS_CTRL_39: 611 case RT5682_HP_IMP_SENS_CTRL_40: 612 case RT5682_HP_IMP_SENS_CTRL_41: 613 case RT5682_HP_IMP_SENS_CTRL_42: 614 case RT5682_HP_IMP_SENS_CTRL_43: 615 case RT5682_HP_LOGIC_CTRL_1: 616 case RT5682_HP_LOGIC_CTRL_2: 617 case RT5682_HP_LOGIC_CTRL_3: 618 case RT5682_HP_CALIB_CTRL_1: 619 case RT5682_HP_CALIB_CTRL_2: 620 case RT5682_HP_CALIB_CTRL_3: 621 case RT5682_HP_CALIB_CTRL_4: 622 case RT5682_HP_CALIB_CTRL_5: 623 case RT5682_HP_CALIB_CTRL_6: 624 case RT5682_HP_CALIB_CTRL_7: 625 case RT5682_HP_CALIB_CTRL_9: 626 case RT5682_HP_CALIB_CTRL_10: 627 case RT5682_HP_CALIB_CTRL_11: 628 case RT5682_HP_CALIB_STA_1: 629 case RT5682_HP_CALIB_STA_2: 630 case RT5682_HP_CALIB_STA_3: 631 case RT5682_HP_CALIB_STA_4: 632 case RT5682_HP_CALIB_STA_5: 633 case RT5682_HP_CALIB_STA_6: 634 case RT5682_HP_CALIB_STA_7: 635 case RT5682_HP_CALIB_STA_8: 636 case RT5682_HP_CALIB_STA_9: 637 case RT5682_HP_CALIB_STA_10: 638 case RT5682_HP_CALIB_STA_11: 639 case RT5682_SAR_IL_CMD_1: 640 case RT5682_SAR_IL_CMD_2: 641 case RT5682_SAR_IL_CMD_3: 642 case RT5682_SAR_IL_CMD_4: 643 case RT5682_SAR_IL_CMD_5: 644 case RT5682_SAR_IL_CMD_6: 645 case RT5682_SAR_IL_CMD_7: 646 case RT5682_SAR_IL_CMD_8: 647 case RT5682_SAR_IL_CMD_9: 648 case RT5682_SAR_IL_CMD_10: 649 case RT5682_SAR_IL_CMD_11: 650 case RT5682_SAR_IL_CMD_12: 651 case RT5682_SAR_IL_CMD_13: 652 case RT5682_EFUSE_CTRL_1: 653 case RT5682_EFUSE_CTRL_2: 654 case RT5682_EFUSE_CTRL_3: 655 case RT5682_EFUSE_CTRL_4: 656 case RT5682_EFUSE_CTRL_5: 657 case RT5682_EFUSE_CTRL_6: 658 case RT5682_EFUSE_CTRL_7: 659 case RT5682_EFUSE_CTRL_8: 660 case RT5682_EFUSE_CTRL_9: 661 case RT5682_EFUSE_CTRL_10: 662 case RT5682_EFUSE_CTRL_11: 663 case RT5682_JD_TOP_VC_VTRL: 664 case RT5682_DRC1_CTRL_0: 665 case RT5682_DRC1_CTRL_1: 666 case RT5682_DRC1_CTRL_2: 667 case RT5682_DRC1_CTRL_3: 668 case RT5682_DRC1_CTRL_4: 669 case RT5682_DRC1_CTRL_5: 670 case RT5682_DRC1_CTRL_6: 671 case RT5682_DRC1_HARD_LMT_CTRL_1: 672 case RT5682_DRC1_HARD_LMT_CTRL_2: 673 case RT5682_DRC1_PRIV_1: 674 case RT5682_DRC1_PRIV_2: 675 case RT5682_DRC1_PRIV_3: 676 case RT5682_DRC1_PRIV_4: 677 case RT5682_DRC1_PRIV_5: 678 case RT5682_DRC1_PRIV_6: 679 case RT5682_DRC1_PRIV_7: 680 case RT5682_DRC1_PRIV_8: 681 case RT5682_EQ_AUTO_RCV_CTRL1: 682 case RT5682_EQ_AUTO_RCV_CTRL2: 683 case RT5682_EQ_AUTO_RCV_CTRL3: 684 case RT5682_EQ_AUTO_RCV_CTRL4: 685 case RT5682_EQ_AUTO_RCV_CTRL5: 686 case RT5682_EQ_AUTO_RCV_CTRL6: 687 case RT5682_EQ_AUTO_RCV_CTRL7: 688 case RT5682_EQ_AUTO_RCV_CTRL8: 689 case RT5682_EQ_AUTO_RCV_CTRL9: 690 case RT5682_EQ_AUTO_RCV_CTRL10: 691 case RT5682_EQ_AUTO_RCV_CTRL11: 692 case RT5682_EQ_AUTO_RCV_CTRL12: 693 case RT5682_EQ_AUTO_RCV_CTRL13: 694 case RT5682_ADC_L_EQ_LPF1_A1: 695 case RT5682_R_EQ_LPF1_A1: 696 case RT5682_L_EQ_LPF1_H0: 697 case RT5682_R_EQ_LPF1_H0: 698 case RT5682_L_EQ_BPF1_A1: 699 case RT5682_R_EQ_BPF1_A1: 700 case RT5682_L_EQ_BPF1_A2: 701 case RT5682_R_EQ_BPF1_A2: 702 case RT5682_L_EQ_BPF1_H0: 703 case RT5682_R_EQ_BPF1_H0: 704 case RT5682_L_EQ_BPF2_A1: 705 case RT5682_R_EQ_BPF2_A1: 706 case RT5682_L_EQ_BPF2_A2: 707 case RT5682_R_EQ_BPF2_A2: 708 case RT5682_L_EQ_BPF2_H0: 709 case RT5682_R_EQ_BPF2_H0: 710 case RT5682_L_EQ_BPF3_A1: 711 case RT5682_R_EQ_BPF3_A1: 712 case RT5682_L_EQ_BPF3_A2: 713 case RT5682_R_EQ_BPF3_A2: 714 case RT5682_L_EQ_BPF3_H0: 715 case RT5682_R_EQ_BPF3_H0: 716 case RT5682_L_EQ_BPF4_A1: 717 case RT5682_R_EQ_BPF4_A1: 718 case RT5682_L_EQ_BPF4_A2: 719 case RT5682_R_EQ_BPF4_A2: 720 case RT5682_L_EQ_BPF4_H0: 721 case RT5682_R_EQ_BPF4_H0: 722 case RT5682_L_EQ_HPF1_A1: 723 case RT5682_R_EQ_HPF1_A1: 724 case RT5682_L_EQ_HPF1_H0: 725 case RT5682_R_EQ_HPF1_H0: 726 case RT5682_L_EQ_PRE_VOL: 727 case RT5682_R_EQ_PRE_VOL: 728 case RT5682_L_EQ_POST_VOL: 729 case RT5682_R_EQ_POST_VOL: 730 case RT5682_I2C_MODE: 731 return true; 732 default: 733 return false; 734 } 735 } 736 737 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6525, 75, 0); 738 static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0); 739 static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0); 740 741 /* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */ 742 static const DECLARE_TLV_DB_RANGE(bst_tlv, 743 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0), 744 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0), 745 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0), 746 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0), 747 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0), 748 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0), 749 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0) 750 ); 751 752 /* Interface data select */ 753 static const char * const rt5682_data_select[] = { 754 "L/R", "R/L", "L/L", "R/R" 755 }; 756 757 static SOC_ENUM_SINGLE_DECL(rt5682_if2_adc_enum, 758 RT5682_DIG_INF2_DATA, RT5682_IF2_ADC_SEL_SFT, rt5682_data_select); 759 760 static SOC_ENUM_SINGLE_DECL(rt5682_if1_01_adc_enum, 761 RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC1_SEL_SFT, rt5682_data_select); 762 763 static SOC_ENUM_SINGLE_DECL(rt5682_if1_23_adc_enum, 764 RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC2_SEL_SFT, rt5682_data_select); 765 766 static SOC_ENUM_SINGLE_DECL(rt5682_if1_45_adc_enum, 767 RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC3_SEL_SFT, rt5682_data_select); 768 769 static SOC_ENUM_SINGLE_DECL(rt5682_if1_67_adc_enum, 770 RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC4_SEL_SFT, rt5682_data_select); 771 772 static const struct snd_kcontrol_new rt5682_if2_adc_swap_mux = 773 SOC_DAPM_ENUM("IF2 ADC Swap Mux", rt5682_if2_adc_enum); 774 775 static const struct snd_kcontrol_new rt5682_if1_01_adc_swap_mux = 776 SOC_DAPM_ENUM("IF1 01 ADC Swap Mux", rt5682_if1_01_adc_enum); 777 778 static const struct snd_kcontrol_new rt5682_if1_23_adc_swap_mux = 779 SOC_DAPM_ENUM("IF1 23 ADC Swap Mux", rt5682_if1_23_adc_enum); 780 781 static const struct snd_kcontrol_new rt5682_if1_45_adc_swap_mux = 782 SOC_DAPM_ENUM("IF1 45 ADC Swap Mux", rt5682_if1_45_adc_enum); 783 784 static const struct snd_kcontrol_new rt5682_if1_67_adc_swap_mux = 785 SOC_DAPM_ENUM("IF1 67 ADC Swap Mux", rt5682_if1_67_adc_enum); 786 787 static const char * const rt5682_dac_select[] = { 788 "IF1", "SOUND" 789 }; 790 791 static SOC_ENUM_SINGLE_DECL(rt5682_dacl_enum, 792 RT5682_AD_DA_MIXER, RT5682_DAC1_L_SEL_SFT, rt5682_dac_select); 793 794 static const struct snd_kcontrol_new rt5682_dac_l_mux = 795 SOC_DAPM_ENUM("DAC L Mux", rt5682_dacl_enum); 796 797 static SOC_ENUM_SINGLE_DECL(rt5682_dacr_enum, 798 RT5682_AD_DA_MIXER, RT5682_DAC1_R_SEL_SFT, rt5682_dac_select); 799 800 static const struct snd_kcontrol_new rt5682_dac_r_mux = 801 SOC_DAPM_ENUM("DAC R Mux", rt5682_dacr_enum); 802 803 static void rt5682_reset(struct rt5682_priv *rt5682) 804 { 805 regmap_write(rt5682->regmap, RT5682_RESET, 0); 806 if (!rt5682->is_sdw) 807 regmap_write(rt5682->regmap, RT5682_I2C_MODE, 1); 808 } 809 /** 810 * rt5682_sel_asrc_clk_src - select ASRC clock source for a set of filters 811 * @component: SoC audio component device. 812 * @filter_mask: mask of filters. 813 * @clk_src: clock source 814 * 815 * The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5682 can 816 * only support standard 32fs or 64fs i2s format, ASRC should be enabled to 817 * support special i2s clock format such as Intel's 100fs(100 * sampling rate). 818 * ASRC function will track i2s clock and generate a corresponding system clock 819 * for codec. This function provides an API to select the clock source for a 820 * set of filters specified by the mask. And the component driver will turn on 821 * ASRC for these filters if ASRC is selected as their clock source. 822 */ 823 int rt5682_sel_asrc_clk_src(struct snd_soc_component *component, 824 unsigned int filter_mask, unsigned int clk_src) 825 { 826 827 switch (clk_src) { 828 case RT5682_CLK_SEL_SYS: 829 case RT5682_CLK_SEL_I2S1_ASRC: 830 case RT5682_CLK_SEL_I2S2_ASRC: 831 break; 832 833 default: 834 return -EINVAL; 835 } 836 837 if (filter_mask & RT5682_DA_STEREO1_FILTER) { 838 snd_soc_component_update_bits(component, RT5682_PLL_TRACK_2, 839 RT5682_FILTER_CLK_SEL_MASK, 840 clk_src << RT5682_FILTER_CLK_SEL_SFT); 841 } 842 843 if (filter_mask & RT5682_AD_STEREO1_FILTER) { 844 snd_soc_component_update_bits(component, RT5682_PLL_TRACK_3, 845 RT5682_FILTER_CLK_SEL_MASK, 846 clk_src << RT5682_FILTER_CLK_SEL_SFT); 847 } 848 849 return 0; 850 } 851 EXPORT_SYMBOL_GPL(rt5682_sel_asrc_clk_src); 852 853 static int rt5682_button_detect(struct snd_soc_component *component) 854 { 855 int btn_type, val; 856 857 val = snd_soc_component_read32(component, RT5682_4BTN_IL_CMD_1); 858 btn_type = val & 0xfff0; 859 snd_soc_component_write(component, RT5682_4BTN_IL_CMD_1, val); 860 pr_debug("%s btn_type=%x\n", __func__, btn_type); 861 snd_soc_component_update_bits(component, 862 RT5682_SAR_IL_CMD_2, 0x10, 0x10); 863 864 return btn_type; 865 } 866 867 static void rt5682_enable_push_button_irq(struct snd_soc_component *component, 868 bool enable) 869 { 870 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 871 872 if (enable) { 873 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1, 874 RT5682_SAR_BUTT_DET_MASK, RT5682_SAR_BUTT_DET_EN); 875 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_13, 876 RT5682_SAR_SOUR_MASK, RT5682_SAR_SOUR_BTN); 877 snd_soc_component_write(component, RT5682_IL_CMD_1, 0x0040); 878 snd_soc_component_update_bits(component, RT5682_4BTN_IL_CMD_2, 879 RT5682_4BTN_IL_MASK | RT5682_4BTN_IL_RST_MASK, 880 RT5682_4BTN_IL_EN | RT5682_4BTN_IL_NOR); 881 if (rt5682->is_sdw) 882 snd_soc_component_update_bits(component, 883 RT5682_IRQ_CTRL_3, 884 RT5682_IL_IRQ_MASK | RT5682_IL_IRQ_TYPE_MASK, 885 RT5682_IL_IRQ_EN | RT5682_IL_IRQ_PUL); 886 else 887 snd_soc_component_update_bits(component, 888 RT5682_IRQ_CTRL_3, RT5682_IL_IRQ_MASK, 889 RT5682_IL_IRQ_EN); 890 } else { 891 snd_soc_component_update_bits(component, RT5682_IRQ_CTRL_3, 892 RT5682_IL_IRQ_MASK, RT5682_IL_IRQ_DIS); 893 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1, 894 RT5682_SAR_BUTT_DET_MASK, RT5682_SAR_BUTT_DET_DIS); 895 snd_soc_component_update_bits(component, RT5682_4BTN_IL_CMD_2, 896 RT5682_4BTN_IL_MASK, RT5682_4BTN_IL_DIS); 897 snd_soc_component_update_bits(component, RT5682_4BTN_IL_CMD_2, 898 RT5682_4BTN_IL_RST_MASK, RT5682_4BTN_IL_RST); 899 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_13, 900 RT5682_SAR_SOUR_MASK, RT5682_SAR_SOUR_TYPE); 901 } 902 } 903 904 /** 905 * rt5682_headset_detect - Detect headset. 906 * @component: SoC audio component device. 907 * @jack_insert: Jack insert or not. 908 * 909 * Detect whether is headset or not when jack inserted. 910 * 911 * Returns detect status. 912 */ 913 static int rt5682_headset_detect(struct snd_soc_component *component, 914 int jack_insert) 915 { 916 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 917 struct snd_soc_dapm_context *dapm = &component->dapm; 918 unsigned int val, count; 919 920 if (jack_insert) { 921 922 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_1, 923 RT5682_PWR_VREF2 | RT5682_PWR_MB, 924 RT5682_PWR_VREF2 | RT5682_PWR_MB); 925 snd_soc_component_update_bits(component, 926 RT5682_PWR_ANLG_1, RT5682_PWR_FV2, 0); 927 usleep_range(15000, 20000); 928 snd_soc_component_update_bits(component, 929 RT5682_PWR_ANLG_1, RT5682_PWR_FV2, RT5682_PWR_FV2); 930 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_3, 931 RT5682_PWR_CBJ, RT5682_PWR_CBJ); 932 933 snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1, 934 RT5682_TRIG_JD_MASK, RT5682_TRIG_JD_HIGH); 935 936 count = 0; 937 val = snd_soc_component_read32(component, RT5682_CBJ_CTRL_2) 938 & RT5682_JACK_TYPE_MASK; 939 while (val == 0 && count < 50) { 940 usleep_range(10000, 15000); 941 val = snd_soc_component_read32(component, 942 RT5682_CBJ_CTRL_2) & RT5682_JACK_TYPE_MASK; 943 count++; 944 } 945 946 switch (val) { 947 case 0x1: 948 case 0x2: 949 rt5682->jack_type = SND_JACK_HEADSET; 950 rt5682_enable_push_button_irq(component, true); 951 break; 952 default: 953 rt5682->jack_type = SND_JACK_HEADPHONE; 954 } 955 956 } else { 957 rt5682_enable_push_button_irq(component, false); 958 snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1, 959 RT5682_TRIG_JD_MASK, RT5682_TRIG_JD_LOW); 960 if (snd_soc_dapm_get_pin_status(dapm, "MICBIAS")) 961 snd_soc_component_update_bits(component, 962 RT5682_PWR_ANLG_1, RT5682_PWR_VREF2, 0); 963 else 964 snd_soc_component_update_bits(component, 965 RT5682_PWR_ANLG_1, 966 RT5682_PWR_VREF2 | RT5682_PWR_MB, 0); 967 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_3, 968 RT5682_PWR_CBJ, 0); 969 970 rt5682->jack_type = 0; 971 } 972 973 dev_dbg(component->dev, "jack_type = %d\n", rt5682->jack_type); 974 return rt5682->jack_type; 975 } 976 977 static irqreturn_t rt5682_irq(int irq, void *data) 978 { 979 struct rt5682_priv *rt5682 = data; 980 981 mod_delayed_work(system_power_efficient_wq, 982 &rt5682->jack_detect_work, msecs_to_jiffies(250)); 983 984 return IRQ_HANDLED; 985 } 986 987 static void rt5682_jd_check_handler(struct work_struct *work) 988 { 989 struct rt5682_priv *rt5682 = container_of(work, struct rt5682_priv, 990 jd_check_work.work); 991 992 if (snd_soc_component_read32(rt5682->component, RT5682_AJD1_CTRL) 993 & RT5682_JDH_RS_MASK) { 994 /* jack out */ 995 rt5682->jack_type = rt5682_headset_detect(rt5682->component, 0); 996 997 snd_soc_jack_report(rt5682->hs_jack, rt5682->jack_type, 998 SND_JACK_HEADSET | 999 SND_JACK_BTN_0 | SND_JACK_BTN_1 | 1000 SND_JACK_BTN_2 | SND_JACK_BTN_3); 1001 } else { 1002 schedule_delayed_work(&rt5682->jd_check_work, 500); 1003 } 1004 } 1005 1006 static int rt5682_set_jack_detect(struct snd_soc_component *component, 1007 struct snd_soc_jack *hs_jack, void *data) 1008 { 1009 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 1010 1011 rt5682->hs_jack = hs_jack; 1012 1013 if (!rt5682->is_sdw) { 1014 if (!hs_jack) { 1015 regmap_update_bits(rt5682->regmap, RT5682_IRQ_CTRL_2, 1016 RT5682_JD1_EN_MASK, RT5682_JD1_DIS); 1017 regmap_update_bits(rt5682->regmap, RT5682_RC_CLK_CTRL, 1018 RT5682_POW_JDH | RT5682_POW_JDL, 0); 1019 cancel_delayed_work_sync(&rt5682->jack_detect_work); 1020 return 0; 1021 } 1022 1023 switch (rt5682->pdata.jd_src) { 1024 case RT5682_JD1: 1025 snd_soc_component_update_bits(component, 1026 RT5682_CBJ_CTRL_2, RT5682_EXT_JD_SRC, 1027 RT5682_EXT_JD_SRC_MANUAL); 1028 snd_soc_component_write(component, RT5682_CBJ_CTRL_1, 1029 0xd042); 1030 snd_soc_component_update_bits(component, 1031 RT5682_CBJ_CTRL_3, RT5682_CBJ_IN_BUF_EN, 1032 RT5682_CBJ_IN_BUF_EN); 1033 snd_soc_component_update_bits(component, 1034 RT5682_SAR_IL_CMD_1, RT5682_SAR_POW_MASK, 1035 RT5682_SAR_POW_EN); 1036 regmap_update_bits(rt5682->regmap, RT5682_GPIO_CTRL_1, 1037 RT5682_GP1_PIN_MASK, RT5682_GP1_PIN_IRQ); 1038 regmap_update_bits(rt5682->regmap, RT5682_RC_CLK_CTRL, 1039 RT5682_POW_IRQ | RT5682_POW_JDH | 1040 RT5682_POW_ANA, RT5682_POW_IRQ | 1041 RT5682_POW_JDH | RT5682_POW_ANA); 1042 regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_2, 1043 RT5682_PWR_JDH | RT5682_PWR_JDL, 1044 RT5682_PWR_JDH | RT5682_PWR_JDL); 1045 regmap_update_bits(rt5682->regmap, RT5682_IRQ_CTRL_2, 1046 RT5682_JD1_EN_MASK | RT5682_JD1_POL_MASK, 1047 RT5682_JD1_EN | RT5682_JD1_POL_NOR); 1048 regmap_update_bits(rt5682->regmap, RT5682_4BTN_IL_CMD_4, 1049 0x7f7f, (rt5682->pdata.btndet_delay << 8 | 1050 rt5682->pdata.btndet_delay)); 1051 regmap_update_bits(rt5682->regmap, RT5682_4BTN_IL_CMD_5, 1052 0x7f7f, (rt5682->pdata.btndet_delay << 8 | 1053 rt5682->pdata.btndet_delay)); 1054 regmap_update_bits(rt5682->regmap, RT5682_4BTN_IL_CMD_6, 1055 0x7f7f, (rt5682->pdata.btndet_delay << 8 | 1056 rt5682->pdata.btndet_delay)); 1057 regmap_update_bits(rt5682->regmap, RT5682_4BTN_IL_CMD_7, 1058 0x7f7f, (rt5682->pdata.btndet_delay << 8 | 1059 rt5682->pdata.btndet_delay)); 1060 mod_delayed_work(system_power_efficient_wq, 1061 &rt5682->jack_detect_work, 1062 msecs_to_jiffies(250)); 1063 break; 1064 1065 case RT5682_JD_NULL: 1066 regmap_update_bits(rt5682->regmap, RT5682_IRQ_CTRL_2, 1067 RT5682_JD1_EN_MASK, RT5682_JD1_DIS); 1068 regmap_update_bits(rt5682->regmap, RT5682_RC_CLK_CTRL, 1069 RT5682_POW_JDH | RT5682_POW_JDL, 0); 1070 break; 1071 1072 default: 1073 dev_warn(component->dev, "Wrong JD source\n"); 1074 break; 1075 } 1076 } 1077 1078 return 0; 1079 } 1080 1081 static void rt5682_jack_detect_handler(struct work_struct *work) 1082 { 1083 struct rt5682_priv *rt5682 = 1084 container_of(work, struct rt5682_priv, jack_detect_work.work); 1085 int val, btn_type; 1086 1087 while (!rt5682->component) 1088 usleep_range(10000, 15000); 1089 1090 while (!rt5682->component->card->instantiated) 1091 usleep_range(10000, 15000); 1092 1093 mutex_lock(&rt5682->calibrate_mutex); 1094 1095 val = snd_soc_component_read32(rt5682->component, RT5682_AJD1_CTRL) 1096 & RT5682_JDH_RS_MASK; 1097 if (!val) { 1098 /* jack in */ 1099 if (rt5682->jack_type == 0) { 1100 /* jack was out, report jack type */ 1101 rt5682->jack_type = 1102 rt5682_headset_detect(rt5682->component, 1); 1103 } else { 1104 /* jack is already in, report button event */ 1105 rt5682->jack_type = SND_JACK_HEADSET; 1106 btn_type = rt5682_button_detect(rt5682->component); 1107 /** 1108 * rt5682 can report three kinds of button behavior, 1109 * one click, double click and hold. However, 1110 * currently we will report button pressed/released 1111 * event. So all the three button behaviors are 1112 * treated as button pressed. 1113 */ 1114 switch (btn_type) { 1115 case 0x8000: 1116 case 0x4000: 1117 case 0x2000: 1118 rt5682->jack_type |= SND_JACK_BTN_0; 1119 break; 1120 case 0x1000: 1121 case 0x0800: 1122 case 0x0400: 1123 rt5682->jack_type |= SND_JACK_BTN_1; 1124 break; 1125 case 0x0200: 1126 case 0x0100: 1127 case 0x0080: 1128 rt5682->jack_type |= SND_JACK_BTN_2; 1129 break; 1130 case 0x0040: 1131 case 0x0020: 1132 case 0x0010: 1133 rt5682->jack_type |= SND_JACK_BTN_3; 1134 break; 1135 case 0x0000: /* unpressed */ 1136 break; 1137 default: 1138 btn_type = 0; 1139 dev_err(rt5682->component->dev, 1140 "Unexpected button code 0x%04x\n", 1141 btn_type); 1142 break; 1143 } 1144 } 1145 } else { 1146 /* jack out */ 1147 rt5682->jack_type = rt5682_headset_detect(rt5682->component, 0); 1148 } 1149 1150 snd_soc_jack_report(rt5682->hs_jack, rt5682->jack_type, 1151 SND_JACK_HEADSET | 1152 SND_JACK_BTN_0 | SND_JACK_BTN_1 | 1153 SND_JACK_BTN_2 | SND_JACK_BTN_3); 1154 1155 if (!rt5682->is_sdw) { 1156 if (rt5682->jack_type & (SND_JACK_BTN_0 | SND_JACK_BTN_1 | 1157 SND_JACK_BTN_2 | SND_JACK_BTN_3)) 1158 schedule_delayed_work(&rt5682->jd_check_work, 0); 1159 else 1160 cancel_delayed_work_sync(&rt5682->jd_check_work); 1161 } 1162 1163 mutex_unlock(&rt5682->calibrate_mutex); 1164 } 1165 1166 static const struct snd_kcontrol_new rt5682_snd_controls[] = { 1167 /* DAC Digital Volume */ 1168 SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5682_DAC1_DIG_VOL, 1169 RT5682_L_VOL_SFT + 1, RT5682_R_VOL_SFT + 1, 87, 0, dac_vol_tlv), 1170 1171 /* IN Boost Volume */ 1172 SOC_SINGLE_TLV("CBJ Boost Volume", RT5682_CBJ_BST_CTRL, 1173 RT5682_BST_CBJ_SFT, 8, 0, bst_tlv), 1174 1175 /* ADC Digital Volume Control */ 1176 SOC_DOUBLE("STO1 ADC Capture Switch", RT5682_STO1_ADC_DIG_VOL, 1177 RT5682_L_MUTE_SFT, RT5682_R_MUTE_SFT, 1, 1), 1178 SOC_DOUBLE_TLV("STO1 ADC Capture Volume", RT5682_STO1_ADC_DIG_VOL, 1179 RT5682_L_VOL_SFT + 1, RT5682_R_VOL_SFT + 1, 63, 0, adc_vol_tlv), 1180 1181 /* ADC Boost Volume Control */ 1182 SOC_DOUBLE_TLV("STO1 ADC Boost Gain Volume", RT5682_STO1_ADC_BOOST, 1183 RT5682_STO1_ADC_L_BST_SFT, RT5682_STO1_ADC_R_BST_SFT, 1184 3, 0, adc_bst_tlv), 1185 }; 1186 1187 1188 static int rt5682_div_sel(struct rt5682_priv *rt5682, 1189 int target, const int div[], int size) 1190 { 1191 int i; 1192 1193 if (rt5682->sysclk < target) { 1194 pr_err("sysclk rate %d is too low\n", 1195 rt5682->sysclk); 1196 return 0; 1197 } 1198 1199 for (i = 0; i < size - 1; i++) { 1200 dev_dbg(rt5682->component->dev, "div[%d]=%d\n", i, div[i]); 1201 if (target * div[i] == rt5682->sysclk) 1202 return i; 1203 if (target * div[i + 1] > rt5682->sysclk) { 1204 dev_dbg(rt5682->component->dev, "can't find div for sysclk %d\n", 1205 rt5682->sysclk); 1206 return i; 1207 } 1208 } 1209 1210 if (target * div[i] < rt5682->sysclk) 1211 pr_err("sysclk rate %d is too high\n", 1212 rt5682->sysclk); 1213 1214 return size - 1; 1215 1216 } 1217 1218 /** 1219 * set_dmic_clk - Set parameter of dmic. 1220 * 1221 * @w: DAPM widget. 1222 * @kcontrol: The kcontrol of this widget. 1223 * @event: Event id. 1224 * 1225 * Choose dmic clock between 1MHz and 3MHz. 1226 * It is better for clock to approximate 3MHz. 1227 */ 1228 static int set_dmic_clk(struct snd_soc_dapm_widget *w, 1229 struct snd_kcontrol *kcontrol, int event) 1230 { 1231 struct snd_soc_component *component = 1232 snd_soc_dapm_to_component(w->dapm); 1233 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 1234 int idx = -EINVAL, dmic_clk_rate = 3072000; 1235 static const int div[] = {2, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, 128}; 1236 1237 if (rt5682->pdata.dmic_clk_rate) 1238 dmic_clk_rate = rt5682->pdata.dmic_clk_rate; 1239 1240 idx = rt5682_div_sel(rt5682, dmic_clk_rate, div, ARRAY_SIZE(div)); 1241 1242 snd_soc_component_update_bits(component, RT5682_DMIC_CTRL_1, 1243 RT5682_DMIC_CLK_MASK, idx << RT5682_DMIC_CLK_SFT); 1244 1245 return 0; 1246 } 1247 1248 static int set_filter_clk(struct snd_soc_dapm_widget *w, 1249 struct snd_kcontrol *kcontrol, int event) 1250 { 1251 struct snd_soc_component *component = 1252 snd_soc_dapm_to_component(w->dapm); 1253 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 1254 int ref, val, reg, idx = -EINVAL; 1255 static const int div_f[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32, 48}; 1256 static const int div_o[] = {1, 2, 4, 6, 8, 12, 16, 24, 32, 48}; 1257 1258 if (rt5682->is_sdw) 1259 return 0; 1260 1261 val = snd_soc_component_read32(component, RT5682_GPIO_CTRL_1) & 1262 RT5682_GP4_PIN_MASK; 1263 if (w->shift == RT5682_PWR_ADC_S1F_BIT && 1264 val == RT5682_GP4_PIN_ADCDAT2) 1265 ref = 256 * rt5682->lrck[RT5682_AIF2]; 1266 else 1267 ref = 256 * rt5682->lrck[RT5682_AIF1]; 1268 1269 idx = rt5682_div_sel(rt5682, ref, div_f, ARRAY_SIZE(div_f)); 1270 1271 if (w->shift == RT5682_PWR_ADC_S1F_BIT) 1272 reg = RT5682_PLL_TRACK_3; 1273 else 1274 reg = RT5682_PLL_TRACK_2; 1275 1276 snd_soc_component_update_bits(component, reg, 1277 RT5682_FILTER_CLK_DIV_MASK, idx << RT5682_FILTER_CLK_DIV_SFT); 1278 1279 /* select over sample rate */ 1280 for (idx = 0; idx < ARRAY_SIZE(div_o); idx++) { 1281 if (rt5682->sysclk <= 12288000 * div_o[idx]) 1282 break; 1283 } 1284 1285 snd_soc_component_update_bits(component, RT5682_ADDA_CLK_1, 1286 RT5682_ADC_OSR_MASK | RT5682_DAC_OSR_MASK, 1287 (idx << RT5682_ADC_OSR_SFT) | (idx << RT5682_DAC_OSR_SFT)); 1288 1289 return 0; 1290 } 1291 1292 static int is_sys_clk_from_pll1(struct snd_soc_dapm_widget *w, 1293 struct snd_soc_dapm_widget *sink) 1294 { 1295 unsigned int val; 1296 struct snd_soc_component *component = 1297 snd_soc_dapm_to_component(w->dapm); 1298 1299 val = snd_soc_component_read32(component, RT5682_GLB_CLK); 1300 val &= RT5682_SCLK_SRC_MASK; 1301 if (val == RT5682_SCLK_SRC_PLL1) 1302 return 1; 1303 else 1304 return 0; 1305 } 1306 1307 static int is_sys_clk_from_pll2(struct snd_soc_dapm_widget *w, 1308 struct snd_soc_dapm_widget *sink) 1309 { 1310 unsigned int val; 1311 struct snd_soc_component *component = 1312 snd_soc_dapm_to_component(w->dapm); 1313 1314 val = snd_soc_component_read32(component, RT5682_GLB_CLK); 1315 val &= RT5682_SCLK_SRC_MASK; 1316 if (val == RT5682_SCLK_SRC_PLL2) 1317 return 1; 1318 else 1319 return 0; 1320 } 1321 1322 static int is_using_asrc(struct snd_soc_dapm_widget *w, 1323 struct snd_soc_dapm_widget *sink) 1324 { 1325 unsigned int reg, shift, val; 1326 struct snd_soc_component *component = 1327 snd_soc_dapm_to_component(w->dapm); 1328 1329 switch (w->shift) { 1330 case RT5682_ADC_STO1_ASRC_SFT: 1331 reg = RT5682_PLL_TRACK_3; 1332 shift = RT5682_FILTER_CLK_SEL_SFT; 1333 break; 1334 case RT5682_DAC_STO1_ASRC_SFT: 1335 reg = RT5682_PLL_TRACK_2; 1336 shift = RT5682_FILTER_CLK_SEL_SFT; 1337 break; 1338 default: 1339 return 0; 1340 } 1341 1342 val = (snd_soc_component_read32(component, reg) >> shift) & 0xf; 1343 switch (val) { 1344 case RT5682_CLK_SEL_I2S1_ASRC: 1345 case RT5682_CLK_SEL_I2S2_ASRC: 1346 return 1; 1347 default: 1348 return 0; 1349 } 1350 1351 } 1352 1353 /* Digital Mixer */ 1354 static const struct snd_kcontrol_new rt5682_sto1_adc_l_mix[] = { 1355 SOC_DAPM_SINGLE("ADC1 Switch", RT5682_STO1_ADC_MIXER, 1356 RT5682_M_STO1_ADC_L1_SFT, 1, 1), 1357 SOC_DAPM_SINGLE("ADC2 Switch", RT5682_STO1_ADC_MIXER, 1358 RT5682_M_STO1_ADC_L2_SFT, 1, 1), 1359 }; 1360 1361 static const struct snd_kcontrol_new rt5682_sto1_adc_r_mix[] = { 1362 SOC_DAPM_SINGLE("ADC1 Switch", RT5682_STO1_ADC_MIXER, 1363 RT5682_M_STO1_ADC_R1_SFT, 1, 1), 1364 SOC_DAPM_SINGLE("ADC2 Switch", RT5682_STO1_ADC_MIXER, 1365 RT5682_M_STO1_ADC_R2_SFT, 1, 1), 1366 }; 1367 1368 static const struct snd_kcontrol_new rt5682_dac_l_mix[] = { 1369 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5682_AD_DA_MIXER, 1370 RT5682_M_ADCMIX_L_SFT, 1, 1), 1371 SOC_DAPM_SINGLE("DAC1 Switch", RT5682_AD_DA_MIXER, 1372 RT5682_M_DAC1_L_SFT, 1, 1), 1373 }; 1374 1375 static const struct snd_kcontrol_new rt5682_dac_r_mix[] = { 1376 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5682_AD_DA_MIXER, 1377 RT5682_M_ADCMIX_R_SFT, 1, 1), 1378 SOC_DAPM_SINGLE("DAC1 Switch", RT5682_AD_DA_MIXER, 1379 RT5682_M_DAC1_R_SFT, 1, 1), 1380 }; 1381 1382 static const struct snd_kcontrol_new rt5682_sto1_dac_l_mix[] = { 1383 SOC_DAPM_SINGLE("DAC L1 Switch", RT5682_STO1_DAC_MIXER, 1384 RT5682_M_DAC_L1_STO_L_SFT, 1, 1), 1385 SOC_DAPM_SINGLE("DAC R1 Switch", RT5682_STO1_DAC_MIXER, 1386 RT5682_M_DAC_R1_STO_L_SFT, 1, 1), 1387 }; 1388 1389 static const struct snd_kcontrol_new rt5682_sto1_dac_r_mix[] = { 1390 SOC_DAPM_SINGLE("DAC L1 Switch", RT5682_STO1_DAC_MIXER, 1391 RT5682_M_DAC_L1_STO_R_SFT, 1, 1), 1392 SOC_DAPM_SINGLE("DAC R1 Switch", RT5682_STO1_DAC_MIXER, 1393 RT5682_M_DAC_R1_STO_R_SFT, 1, 1), 1394 }; 1395 1396 /* Analog Input Mixer */ 1397 static const struct snd_kcontrol_new rt5682_rec1_l_mix[] = { 1398 SOC_DAPM_SINGLE("CBJ Switch", RT5682_REC_MIXER, 1399 RT5682_M_CBJ_RM1_L_SFT, 1, 1), 1400 }; 1401 1402 /* STO1 ADC1 Source */ 1403 /* MX-26 [13] [5] */ 1404 static const char * const rt5682_sto1_adc1_src[] = { 1405 "DAC MIX", "ADC" 1406 }; 1407 1408 static SOC_ENUM_SINGLE_DECL( 1409 rt5682_sto1_adc1l_enum, RT5682_STO1_ADC_MIXER, 1410 RT5682_STO1_ADC1L_SRC_SFT, rt5682_sto1_adc1_src); 1411 1412 static const struct snd_kcontrol_new rt5682_sto1_adc1l_mux = 1413 SOC_DAPM_ENUM("Stereo1 ADC1L Source", rt5682_sto1_adc1l_enum); 1414 1415 static SOC_ENUM_SINGLE_DECL( 1416 rt5682_sto1_adc1r_enum, RT5682_STO1_ADC_MIXER, 1417 RT5682_STO1_ADC1R_SRC_SFT, rt5682_sto1_adc1_src); 1418 1419 static const struct snd_kcontrol_new rt5682_sto1_adc1r_mux = 1420 SOC_DAPM_ENUM("Stereo1 ADC1L Source", rt5682_sto1_adc1r_enum); 1421 1422 /* STO1 ADC Source */ 1423 /* MX-26 [11:10] [3:2] */ 1424 static const char * const rt5682_sto1_adc_src[] = { 1425 "ADC1 L", "ADC1 R" 1426 }; 1427 1428 static SOC_ENUM_SINGLE_DECL( 1429 rt5682_sto1_adcl_enum, RT5682_STO1_ADC_MIXER, 1430 RT5682_STO1_ADCL_SRC_SFT, rt5682_sto1_adc_src); 1431 1432 static const struct snd_kcontrol_new rt5682_sto1_adcl_mux = 1433 SOC_DAPM_ENUM("Stereo1 ADCL Source", rt5682_sto1_adcl_enum); 1434 1435 static SOC_ENUM_SINGLE_DECL( 1436 rt5682_sto1_adcr_enum, RT5682_STO1_ADC_MIXER, 1437 RT5682_STO1_ADCR_SRC_SFT, rt5682_sto1_adc_src); 1438 1439 static const struct snd_kcontrol_new rt5682_sto1_adcr_mux = 1440 SOC_DAPM_ENUM("Stereo1 ADCR Source", rt5682_sto1_adcr_enum); 1441 1442 /* STO1 ADC2 Source */ 1443 /* MX-26 [12] [4] */ 1444 static const char * const rt5682_sto1_adc2_src[] = { 1445 "DAC MIX", "DMIC" 1446 }; 1447 1448 static SOC_ENUM_SINGLE_DECL( 1449 rt5682_sto1_adc2l_enum, RT5682_STO1_ADC_MIXER, 1450 RT5682_STO1_ADC2L_SRC_SFT, rt5682_sto1_adc2_src); 1451 1452 static const struct snd_kcontrol_new rt5682_sto1_adc2l_mux = 1453 SOC_DAPM_ENUM("Stereo1 ADC2L Source", rt5682_sto1_adc2l_enum); 1454 1455 static SOC_ENUM_SINGLE_DECL( 1456 rt5682_sto1_adc2r_enum, RT5682_STO1_ADC_MIXER, 1457 RT5682_STO1_ADC2R_SRC_SFT, rt5682_sto1_adc2_src); 1458 1459 static const struct snd_kcontrol_new rt5682_sto1_adc2r_mux = 1460 SOC_DAPM_ENUM("Stereo1 ADC2R Source", rt5682_sto1_adc2r_enum); 1461 1462 /* MX-79 [6:4] I2S1 ADC data location */ 1463 static const unsigned int rt5682_if1_adc_slot_values[] = { 1464 0, 1465 2, 1466 4, 1467 6, 1468 }; 1469 1470 static const char * const rt5682_if1_adc_slot_src[] = { 1471 "Slot 0", "Slot 2", "Slot 4", "Slot 6" 1472 }; 1473 1474 static SOC_VALUE_ENUM_SINGLE_DECL(rt5682_if1_adc_slot_enum, 1475 RT5682_TDM_CTRL, RT5682_TDM_ADC_LCA_SFT, RT5682_TDM_ADC_LCA_MASK, 1476 rt5682_if1_adc_slot_src, rt5682_if1_adc_slot_values); 1477 1478 static const struct snd_kcontrol_new rt5682_if1_adc_slot_mux = 1479 SOC_DAPM_ENUM("IF1 ADC Slot location", rt5682_if1_adc_slot_enum); 1480 1481 /* Analog DAC L1 Source, Analog DAC R1 Source*/ 1482 /* MX-2B [4], MX-2B [0]*/ 1483 static const char * const rt5682_alg_dac1_src[] = { 1484 "Stereo1 DAC Mixer", "DAC1" 1485 }; 1486 1487 static SOC_ENUM_SINGLE_DECL( 1488 rt5682_alg_dac_l1_enum, RT5682_A_DAC1_MUX, 1489 RT5682_A_DACL1_SFT, rt5682_alg_dac1_src); 1490 1491 static const struct snd_kcontrol_new rt5682_alg_dac_l1_mux = 1492 SOC_DAPM_ENUM("Analog DAC L1 Source", rt5682_alg_dac_l1_enum); 1493 1494 static SOC_ENUM_SINGLE_DECL( 1495 rt5682_alg_dac_r1_enum, RT5682_A_DAC1_MUX, 1496 RT5682_A_DACR1_SFT, rt5682_alg_dac1_src); 1497 1498 static const struct snd_kcontrol_new rt5682_alg_dac_r1_mux = 1499 SOC_DAPM_ENUM("Analog DAC R1 Source", rt5682_alg_dac_r1_enum); 1500 1501 /* Out Switch */ 1502 static const struct snd_kcontrol_new hpol_switch = 1503 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5682_HP_CTRL_1, 1504 RT5682_L_MUTE_SFT, 1, 1); 1505 static const struct snd_kcontrol_new hpor_switch = 1506 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5682_HP_CTRL_1, 1507 RT5682_R_MUTE_SFT, 1, 1); 1508 1509 static int rt5682_hp_event(struct snd_soc_dapm_widget *w, 1510 struct snd_kcontrol *kcontrol, int event) 1511 { 1512 struct snd_soc_component *component = 1513 snd_soc_dapm_to_component(w->dapm); 1514 1515 switch (event) { 1516 case SND_SOC_DAPM_PRE_PMU: 1517 snd_soc_component_write(component, 1518 RT5682_HP_LOGIC_CTRL_2, 0x0012); 1519 snd_soc_component_write(component, 1520 RT5682_HP_CTRL_2, 0x6000); 1521 snd_soc_component_update_bits(component, 1522 RT5682_DEPOP_1, 0x60, 0x60); 1523 snd_soc_component_update_bits(component, 1524 RT5682_DAC_ADC_DIG_VOL1, 0x00c0, 0x0080); 1525 break; 1526 1527 case SND_SOC_DAPM_POST_PMD: 1528 snd_soc_component_update_bits(component, 1529 RT5682_DEPOP_1, 0x60, 0x0); 1530 snd_soc_component_write(component, 1531 RT5682_HP_CTRL_2, 0x0000); 1532 snd_soc_component_update_bits(component, 1533 RT5682_DAC_ADC_DIG_VOL1, 0x00c0, 0x0000); 1534 break; 1535 1536 default: 1537 return 0; 1538 } 1539 1540 return 0; 1541 1542 } 1543 1544 static int set_dmic_power(struct snd_soc_dapm_widget *w, 1545 struct snd_kcontrol *kcontrol, int event) 1546 { 1547 struct snd_soc_component *component = 1548 snd_soc_dapm_to_component(w->dapm); 1549 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 1550 unsigned int delay = 50; 1551 1552 if (rt5682->pdata.dmic_delay) 1553 delay = rt5682->pdata.dmic_delay; 1554 1555 switch (event) { 1556 case SND_SOC_DAPM_POST_PMU: 1557 /*Add delay to avoid pop noise*/ 1558 msleep(delay); 1559 break; 1560 1561 default: 1562 return 0; 1563 } 1564 1565 return 0; 1566 } 1567 1568 static int rt5682_set_verf(struct snd_soc_dapm_widget *w, 1569 struct snd_kcontrol *kcontrol, int event) 1570 { 1571 struct snd_soc_component *component = 1572 snd_soc_dapm_to_component(w->dapm); 1573 1574 switch (event) { 1575 case SND_SOC_DAPM_PRE_PMU: 1576 switch (w->shift) { 1577 case RT5682_PWR_VREF1_BIT: 1578 snd_soc_component_update_bits(component, 1579 RT5682_PWR_ANLG_1, RT5682_PWR_FV1, 0); 1580 break; 1581 1582 case RT5682_PWR_VREF2_BIT: 1583 snd_soc_component_update_bits(component, 1584 RT5682_PWR_ANLG_1, RT5682_PWR_FV2, 0); 1585 break; 1586 1587 default: 1588 break; 1589 } 1590 break; 1591 1592 case SND_SOC_DAPM_POST_PMU: 1593 usleep_range(15000, 20000); 1594 switch (w->shift) { 1595 case RT5682_PWR_VREF1_BIT: 1596 snd_soc_component_update_bits(component, 1597 RT5682_PWR_ANLG_1, RT5682_PWR_FV1, 1598 RT5682_PWR_FV1); 1599 break; 1600 1601 case RT5682_PWR_VREF2_BIT: 1602 snd_soc_component_update_bits(component, 1603 RT5682_PWR_ANLG_1, RT5682_PWR_FV2, 1604 RT5682_PWR_FV2); 1605 break; 1606 1607 default: 1608 break; 1609 } 1610 break; 1611 1612 default: 1613 return 0; 1614 } 1615 1616 return 0; 1617 } 1618 1619 static const unsigned int rt5682_adcdat_pin_values[] = { 1620 1, 1621 3, 1622 }; 1623 1624 static const char * const rt5682_adcdat_pin_select[] = { 1625 "ADCDAT1", 1626 "ADCDAT2", 1627 }; 1628 1629 static SOC_VALUE_ENUM_SINGLE_DECL(rt5682_adcdat_pin_enum, 1630 RT5682_GPIO_CTRL_1, RT5682_GP4_PIN_SFT, RT5682_GP4_PIN_MASK, 1631 rt5682_adcdat_pin_select, rt5682_adcdat_pin_values); 1632 1633 static const struct snd_kcontrol_new rt5682_adcdat_pin_ctrl = 1634 SOC_DAPM_ENUM("ADCDAT", rt5682_adcdat_pin_enum); 1635 1636 static const struct snd_soc_dapm_widget rt5682_dapm_widgets[] = { 1637 SND_SOC_DAPM_SUPPLY("LDO2", RT5682_PWR_ANLG_3, RT5682_PWR_LDO2_BIT, 1638 0, NULL, 0), 1639 SND_SOC_DAPM_SUPPLY("PLL1", RT5682_PWR_ANLG_3, RT5682_PWR_PLL_BIT, 1640 0, NULL, 0), 1641 SND_SOC_DAPM_SUPPLY("PLL2B", RT5682_PWR_ANLG_3, RT5682_PWR_PLL2B_BIT, 1642 0, NULL, 0), 1643 SND_SOC_DAPM_SUPPLY("PLL2F", RT5682_PWR_ANLG_3, RT5682_PWR_PLL2F_BIT, 1644 0, set_filter_clk, SND_SOC_DAPM_PRE_PMU), 1645 SND_SOC_DAPM_SUPPLY("Vref1", RT5682_PWR_ANLG_1, RT5682_PWR_VREF1_BIT, 0, 1646 rt5682_set_verf, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), 1647 SND_SOC_DAPM_SUPPLY("Vref2", RT5682_PWR_ANLG_1, RT5682_PWR_VREF2_BIT, 0, 1648 NULL, 0), 1649 SND_SOC_DAPM_SUPPLY("MICBIAS", SND_SOC_NOPM, 0, 0, NULL, 0), 1650 1651 /* ASRC */ 1652 SND_SOC_DAPM_SUPPLY_S("DAC STO1 ASRC", 1, RT5682_PLL_TRACK_1, 1653 RT5682_DAC_STO1_ASRC_SFT, 0, NULL, 0), 1654 SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5682_PLL_TRACK_1, 1655 RT5682_ADC_STO1_ASRC_SFT, 0, NULL, 0), 1656 SND_SOC_DAPM_SUPPLY_S("AD ASRC", 1, RT5682_PLL_TRACK_1, 1657 RT5682_AD_ASRC_SFT, 0, NULL, 0), 1658 SND_SOC_DAPM_SUPPLY_S("DA ASRC", 1, RT5682_PLL_TRACK_1, 1659 RT5682_DA_ASRC_SFT, 0, NULL, 0), 1660 SND_SOC_DAPM_SUPPLY_S("DMIC ASRC", 1, RT5682_PLL_TRACK_1, 1661 RT5682_DMIC_ASRC_SFT, 0, NULL, 0), 1662 1663 /* Input Side */ 1664 SND_SOC_DAPM_SUPPLY("MICBIAS1", RT5682_PWR_ANLG_2, RT5682_PWR_MB1_BIT, 1665 0, NULL, 0), 1666 SND_SOC_DAPM_SUPPLY("MICBIAS2", RT5682_PWR_ANLG_2, RT5682_PWR_MB2_BIT, 1667 0, NULL, 0), 1668 1669 /* Input Lines */ 1670 SND_SOC_DAPM_INPUT("DMIC L1"), 1671 SND_SOC_DAPM_INPUT("DMIC R1"), 1672 1673 SND_SOC_DAPM_INPUT("IN1P"), 1674 1675 SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0, 1676 set_dmic_clk, SND_SOC_DAPM_PRE_PMU), 1677 SND_SOC_DAPM_SUPPLY("DMIC1 Power", RT5682_DMIC_CTRL_1, 1678 RT5682_DMIC_1_EN_SFT, 0, set_dmic_power, SND_SOC_DAPM_POST_PMU), 1679 1680 /* Boost */ 1681 SND_SOC_DAPM_PGA("BST1 CBJ", SND_SOC_NOPM, 1682 0, 0, NULL, 0), 1683 1684 /* REC Mixer */ 1685 SND_SOC_DAPM_MIXER("RECMIX1L", SND_SOC_NOPM, 0, 0, rt5682_rec1_l_mix, 1686 ARRAY_SIZE(rt5682_rec1_l_mix)), 1687 SND_SOC_DAPM_SUPPLY("RECMIX1L Power", RT5682_PWR_ANLG_2, 1688 RT5682_PWR_RM1_L_BIT, 0, NULL, 0), 1689 1690 /* ADCs */ 1691 SND_SOC_DAPM_ADC("ADC1 L", NULL, SND_SOC_NOPM, 0, 0), 1692 SND_SOC_DAPM_ADC("ADC1 R", NULL, SND_SOC_NOPM, 0, 0), 1693 1694 SND_SOC_DAPM_SUPPLY("ADC1 L Power", RT5682_PWR_DIG_1, 1695 RT5682_PWR_ADC_L1_BIT, 0, NULL, 0), 1696 SND_SOC_DAPM_SUPPLY("ADC1 R Power", RT5682_PWR_DIG_1, 1697 RT5682_PWR_ADC_R1_BIT, 0, NULL, 0), 1698 SND_SOC_DAPM_SUPPLY("ADC1 clock", RT5682_CHOP_ADC, 1699 RT5682_CKGEN_ADC1_SFT, 0, NULL, 0), 1700 1701 /* ADC Mux */ 1702 SND_SOC_DAPM_MUX("Stereo1 ADC L1 Mux", SND_SOC_NOPM, 0, 0, 1703 &rt5682_sto1_adc1l_mux), 1704 SND_SOC_DAPM_MUX("Stereo1 ADC R1 Mux", SND_SOC_NOPM, 0, 0, 1705 &rt5682_sto1_adc1r_mux), 1706 SND_SOC_DAPM_MUX("Stereo1 ADC L2 Mux", SND_SOC_NOPM, 0, 0, 1707 &rt5682_sto1_adc2l_mux), 1708 SND_SOC_DAPM_MUX("Stereo1 ADC R2 Mux", SND_SOC_NOPM, 0, 0, 1709 &rt5682_sto1_adc2r_mux), 1710 SND_SOC_DAPM_MUX("Stereo1 ADC L Mux", SND_SOC_NOPM, 0, 0, 1711 &rt5682_sto1_adcl_mux), 1712 SND_SOC_DAPM_MUX("Stereo1 ADC R Mux", SND_SOC_NOPM, 0, 0, 1713 &rt5682_sto1_adcr_mux), 1714 SND_SOC_DAPM_MUX("IF1_ADC Mux", SND_SOC_NOPM, 0, 0, 1715 &rt5682_if1_adc_slot_mux), 1716 1717 /* ADC Mixer */ 1718 SND_SOC_DAPM_SUPPLY("ADC Stereo1 Filter", RT5682_PWR_DIG_2, 1719 RT5682_PWR_ADC_S1F_BIT, 0, set_filter_clk, 1720 SND_SOC_DAPM_PRE_PMU), 1721 SND_SOC_DAPM_MIXER("Stereo1 ADC MIXL", RT5682_STO1_ADC_DIG_VOL, 1722 RT5682_L_MUTE_SFT, 1, rt5682_sto1_adc_l_mix, 1723 ARRAY_SIZE(rt5682_sto1_adc_l_mix)), 1724 SND_SOC_DAPM_MIXER("Stereo1 ADC MIXR", RT5682_STO1_ADC_DIG_VOL, 1725 RT5682_R_MUTE_SFT, 1, rt5682_sto1_adc_r_mix, 1726 ARRAY_SIZE(rt5682_sto1_adc_r_mix)), 1727 SND_SOC_DAPM_SUPPLY("BTN Detection Mode", RT5682_SAR_IL_CMD_1, 1728 14, 1, NULL, 0), 1729 1730 /* ADC PGA */ 1731 SND_SOC_DAPM_PGA("Stereo1 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 1732 1733 /* Digital Interface */ 1734 SND_SOC_DAPM_SUPPLY("I2S1", RT5682_PWR_DIG_1, RT5682_PWR_I2S1_BIT, 1735 0, NULL, 0), 1736 SND_SOC_DAPM_SUPPLY("I2S2", RT5682_PWR_DIG_1, RT5682_PWR_I2S2_BIT, 1737 0, NULL, 0), 1738 SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0), 1739 SND_SOC_DAPM_PGA("IF1 DAC1 L", SND_SOC_NOPM, 0, 0, NULL, 0), 1740 SND_SOC_DAPM_PGA("IF1 DAC1 R", SND_SOC_NOPM, 0, 0, NULL, 0), 1741 SND_SOC_DAPM_PGA("SOUND DAC L", SND_SOC_NOPM, 0, 0, NULL, 0), 1742 SND_SOC_DAPM_PGA("SOUND DAC R", SND_SOC_NOPM, 0, 0, NULL, 0), 1743 1744 /* Digital Interface Select */ 1745 SND_SOC_DAPM_MUX("IF1 01 ADC Swap Mux", SND_SOC_NOPM, 0, 0, 1746 &rt5682_if1_01_adc_swap_mux), 1747 SND_SOC_DAPM_MUX("IF1 23 ADC Swap Mux", SND_SOC_NOPM, 0, 0, 1748 &rt5682_if1_23_adc_swap_mux), 1749 SND_SOC_DAPM_MUX("IF1 45 ADC Swap Mux", SND_SOC_NOPM, 0, 0, 1750 &rt5682_if1_45_adc_swap_mux), 1751 SND_SOC_DAPM_MUX("IF1 67 ADC Swap Mux", SND_SOC_NOPM, 0, 0, 1752 &rt5682_if1_67_adc_swap_mux), 1753 SND_SOC_DAPM_MUX("IF2 ADC Swap Mux", SND_SOC_NOPM, 0, 0, 1754 &rt5682_if2_adc_swap_mux), 1755 1756 SND_SOC_DAPM_MUX("ADCDAT Mux", SND_SOC_NOPM, 0, 0, 1757 &rt5682_adcdat_pin_ctrl), 1758 1759 SND_SOC_DAPM_MUX("DAC L Mux", SND_SOC_NOPM, 0, 0, 1760 &rt5682_dac_l_mux), 1761 SND_SOC_DAPM_MUX("DAC R Mux", SND_SOC_NOPM, 0, 0, 1762 &rt5682_dac_r_mux), 1763 1764 /* Audio Interface */ 1765 SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, 1766 RT5682_I2S1_SDP, RT5682_SEL_ADCDAT_SFT, 1), 1767 SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, 1768 RT5682_I2S2_SDP, RT5682_I2S2_PIN_CFG_SFT, 1), 1769 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0), 1770 SND_SOC_DAPM_AIF_IN("SDWRX", "SDW Playback", 0, SND_SOC_NOPM, 0, 0), 1771 SND_SOC_DAPM_AIF_OUT("SDWTX", "SDW Capture", 0, SND_SOC_NOPM, 0, 0), 1772 1773 /* Output Side */ 1774 /* DAC mixer before sound effect */ 1775 SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0, 1776 rt5682_dac_l_mix, ARRAY_SIZE(rt5682_dac_l_mix)), 1777 SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0, 1778 rt5682_dac_r_mix, ARRAY_SIZE(rt5682_dac_r_mix)), 1779 1780 /* DAC channel Mux */ 1781 SND_SOC_DAPM_MUX("DAC L1 Source", SND_SOC_NOPM, 0, 0, 1782 &rt5682_alg_dac_l1_mux), 1783 SND_SOC_DAPM_MUX("DAC R1 Source", SND_SOC_NOPM, 0, 0, 1784 &rt5682_alg_dac_r1_mux), 1785 1786 /* DAC Mixer */ 1787 SND_SOC_DAPM_SUPPLY("DAC Stereo1 Filter", RT5682_PWR_DIG_2, 1788 RT5682_PWR_DAC_S1F_BIT, 0, set_filter_clk, 1789 SND_SOC_DAPM_PRE_PMU), 1790 SND_SOC_DAPM_MIXER("Stereo1 DAC MIXL", SND_SOC_NOPM, 0, 0, 1791 rt5682_sto1_dac_l_mix, ARRAY_SIZE(rt5682_sto1_dac_l_mix)), 1792 SND_SOC_DAPM_MIXER("Stereo1 DAC MIXR", SND_SOC_NOPM, 0, 0, 1793 rt5682_sto1_dac_r_mix, ARRAY_SIZE(rt5682_sto1_dac_r_mix)), 1794 1795 /* DACs */ 1796 SND_SOC_DAPM_DAC("DAC L1", NULL, RT5682_PWR_DIG_1, 1797 RT5682_PWR_DAC_L1_BIT, 0), 1798 SND_SOC_DAPM_DAC("DAC R1", NULL, RT5682_PWR_DIG_1, 1799 RT5682_PWR_DAC_R1_BIT, 0), 1800 SND_SOC_DAPM_SUPPLY_S("DAC 1 Clock", 3, RT5682_CHOP_DAC, 1801 RT5682_CKGEN_DAC1_SFT, 0, NULL, 0), 1802 1803 /* HPO */ 1804 SND_SOC_DAPM_PGA_S("HP Amp", 1, SND_SOC_NOPM, 0, 0, rt5682_hp_event, 1805 SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_PRE_PMU), 1806 1807 SND_SOC_DAPM_SUPPLY("HP Amp L", RT5682_PWR_ANLG_1, 1808 RT5682_PWR_HA_L_BIT, 0, NULL, 0), 1809 SND_SOC_DAPM_SUPPLY("HP Amp R", RT5682_PWR_ANLG_1, 1810 RT5682_PWR_HA_R_BIT, 0, NULL, 0), 1811 SND_SOC_DAPM_SUPPLY_S("Charge Pump", 1, RT5682_DEPOP_1, 1812 RT5682_PUMP_EN_SFT, 0, NULL, 0), 1813 SND_SOC_DAPM_SUPPLY_S("Capless", 2, RT5682_DEPOP_1, 1814 RT5682_CAPLESS_EN_SFT, 0, NULL, 0), 1815 1816 SND_SOC_DAPM_SWITCH("HPOL Playback", SND_SOC_NOPM, 0, 0, 1817 &hpol_switch), 1818 SND_SOC_DAPM_SWITCH("HPOR Playback", SND_SOC_NOPM, 0, 0, 1819 &hpor_switch), 1820 1821 /* CLK DET */ 1822 SND_SOC_DAPM_SUPPLY("CLKDET SYS", RT5682_CLK_DET, 1823 RT5682_SYS_CLK_DET_SFT, 0, NULL, 0), 1824 SND_SOC_DAPM_SUPPLY("CLKDET PLL1", RT5682_CLK_DET, 1825 RT5682_PLL1_CLK_DET_SFT, 0, NULL, 0), 1826 SND_SOC_DAPM_SUPPLY("CLKDET PLL2", RT5682_CLK_DET, 1827 RT5682_PLL2_CLK_DET_SFT, 0, NULL, 0), 1828 SND_SOC_DAPM_SUPPLY("CLKDET", RT5682_CLK_DET, 1829 RT5682_POW_CLK_DET_SFT, 0, NULL, 0), 1830 1831 /* Output Lines */ 1832 SND_SOC_DAPM_OUTPUT("HPOL"), 1833 SND_SOC_DAPM_OUTPUT("HPOR"), 1834 1835 }; 1836 1837 static const struct snd_soc_dapm_route rt5682_dapm_routes[] = { 1838 /*PLL*/ 1839 {"ADC Stereo1 Filter", NULL, "PLL1", is_sys_clk_from_pll1}, 1840 {"ADC Stereo1 Filter", NULL, "PLL2B", is_sys_clk_from_pll2}, 1841 {"ADC Stereo1 Filter", NULL, "PLL2F", is_sys_clk_from_pll2}, 1842 {"DAC Stereo1 Filter", NULL, "PLL1", is_sys_clk_from_pll1}, 1843 {"DAC Stereo1 Filter", NULL, "PLL2B", is_sys_clk_from_pll2}, 1844 {"DAC Stereo1 Filter", NULL, "PLL2F", is_sys_clk_from_pll2}, 1845 1846 /*ASRC*/ 1847 {"ADC Stereo1 Filter", NULL, "ADC STO1 ASRC", is_using_asrc}, 1848 {"DAC Stereo1 Filter", NULL, "DAC STO1 ASRC", is_using_asrc}, 1849 {"ADC STO1 ASRC", NULL, "AD ASRC"}, 1850 {"ADC STO1 ASRC", NULL, "DA ASRC"}, 1851 {"ADC STO1 ASRC", NULL, "CLKDET"}, 1852 {"DAC STO1 ASRC", NULL, "AD ASRC"}, 1853 {"DAC STO1 ASRC", NULL, "DA ASRC"}, 1854 {"DAC STO1 ASRC", NULL, "CLKDET"}, 1855 1856 /*Vref*/ 1857 {"MICBIAS1", NULL, "Vref1"}, 1858 {"MICBIAS2", NULL, "Vref1"}, 1859 1860 {"CLKDET SYS", NULL, "CLKDET"}, 1861 1862 {"IN1P", NULL, "LDO2"}, 1863 1864 {"BST1 CBJ", NULL, "IN1P"}, 1865 1866 {"RECMIX1L", "CBJ Switch", "BST1 CBJ"}, 1867 {"RECMIX1L", NULL, "RECMIX1L Power"}, 1868 1869 {"ADC1 L", NULL, "RECMIX1L"}, 1870 {"ADC1 L", NULL, "ADC1 L Power"}, 1871 {"ADC1 L", NULL, "ADC1 clock"}, 1872 1873 {"DMIC L1", NULL, "DMIC CLK"}, 1874 {"DMIC L1", NULL, "DMIC1 Power"}, 1875 {"DMIC R1", NULL, "DMIC CLK"}, 1876 {"DMIC R1", NULL, "DMIC1 Power"}, 1877 {"DMIC CLK", NULL, "DMIC ASRC"}, 1878 1879 {"Stereo1 ADC L Mux", "ADC1 L", "ADC1 L"}, 1880 {"Stereo1 ADC L Mux", "ADC1 R", "ADC1 R"}, 1881 {"Stereo1 ADC R Mux", "ADC1 L", "ADC1 L"}, 1882 {"Stereo1 ADC R Mux", "ADC1 R", "ADC1 R"}, 1883 1884 {"Stereo1 ADC L1 Mux", "ADC", "Stereo1 ADC L Mux"}, 1885 {"Stereo1 ADC L1 Mux", "DAC MIX", "Stereo1 DAC MIXL"}, 1886 {"Stereo1 ADC L2 Mux", "DMIC", "DMIC L1"}, 1887 {"Stereo1 ADC L2 Mux", "DAC MIX", "Stereo1 DAC MIXL"}, 1888 1889 {"Stereo1 ADC R1 Mux", "ADC", "Stereo1 ADC R Mux"}, 1890 {"Stereo1 ADC R1 Mux", "DAC MIX", "Stereo1 DAC MIXR"}, 1891 {"Stereo1 ADC R2 Mux", "DMIC", "DMIC R1"}, 1892 {"Stereo1 ADC R2 Mux", "DAC MIX", "Stereo1 DAC MIXR"}, 1893 1894 {"Stereo1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC L1 Mux"}, 1895 {"Stereo1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC L2 Mux"}, 1896 {"Stereo1 ADC MIXL", NULL, "ADC Stereo1 Filter"}, 1897 1898 {"Stereo1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC R1 Mux"}, 1899 {"Stereo1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC R2 Mux"}, 1900 {"Stereo1 ADC MIXR", NULL, "ADC Stereo1 Filter"}, 1901 1902 {"ADC Stereo1 Filter", NULL, "BTN Detection Mode"}, 1903 1904 {"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXL"}, 1905 {"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXR"}, 1906 1907 {"IF1 01 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"}, 1908 {"IF1 01 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"}, 1909 {"IF1 01 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"}, 1910 {"IF1 01 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"}, 1911 {"IF1 23 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"}, 1912 {"IF1 23 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"}, 1913 {"IF1 23 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"}, 1914 {"IF1 23 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"}, 1915 {"IF1 45 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"}, 1916 {"IF1 45 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"}, 1917 {"IF1 45 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"}, 1918 {"IF1 45 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"}, 1919 {"IF1 67 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"}, 1920 {"IF1 67 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"}, 1921 {"IF1 67 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"}, 1922 {"IF1 67 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"}, 1923 1924 {"IF1_ADC Mux", "Slot 0", "IF1 01 ADC Swap Mux"}, 1925 {"IF1_ADC Mux", "Slot 2", "IF1 23 ADC Swap Mux"}, 1926 {"IF1_ADC Mux", "Slot 4", "IF1 45 ADC Swap Mux"}, 1927 {"IF1_ADC Mux", "Slot 6", "IF1 67 ADC Swap Mux"}, 1928 {"ADCDAT Mux", "ADCDAT1", "IF1_ADC Mux"}, 1929 {"AIF1TX", NULL, "I2S1"}, 1930 {"AIF1TX", NULL, "ADCDAT Mux"}, 1931 {"IF2 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"}, 1932 {"IF2 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"}, 1933 {"IF2 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"}, 1934 {"IF2 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"}, 1935 {"ADCDAT Mux", "ADCDAT2", "IF2 ADC Swap Mux"}, 1936 {"AIF2TX", NULL, "ADCDAT Mux"}, 1937 1938 {"SDWTX", NULL, "PLL2B"}, 1939 {"SDWTX", NULL, "PLL2F"}, 1940 {"SDWTX", NULL, "ADCDAT Mux"}, 1941 1942 {"IF1 DAC1 L", NULL, "AIF1RX"}, 1943 {"IF1 DAC1 L", NULL, "I2S1"}, 1944 {"IF1 DAC1 L", NULL, "DAC Stereo1 Filter"}, 1945 {"IF1 DAC1 R", NULL, "AIF1RX"}, 1946 {"IF1 DAC1 R", NULL, "I2S1"}, 1947 {"IF1 DAC1 R", NULL, "DAC Stereo1 Filter"}, 1948 1949 {"SOUND DAC L", NULL, "SDWRX"}, 1950 {"SOUND DAC L", NULL, "DAC Stereo1 Filter"}, 1951 {"SOUND DAC L", NULL, "PLL2B"}, 1952 {"SOUND DAC L", NULL, "PLL2F"}, 1953 {"SOUND DAC R", NULL, "SDWRX"}, 1954 {"SOUND DAC R", NULL, "DAC Stereo1 Filter"}, 1955 {"SOUND DAC R", NULL, "PLL2B"}, 1956 {"SOUND DAC R", NULL, "PLL2F"}, 1957 1958 {"DAC L Mux", "IF1", "IF1 DAC1 L"}, 1959 {"DAC L Mux", "SOUND", "SOUND DAC L"}, 1960 {"DAC R Mux", "IF1", "IF1 DAC1 R"}, 1961 {"DAC R Mux", "SOUND", "SOUND DAC R"}, 1962 1963 {"DAC1 MIXL", "Stereo ADC Switch", "Stereo1 ADC MIXL"}, 1964 {"DAC1 MIXL", "DAC1 Switch", "DAC L Mux"}, 1965 {"DAC1 MIXR", "Stereo ADC Switch", "Stereo1 ADC MIXR"}, 1966 {"DAC1 MIXR", "DAC1 Switch", "DAC R Mux"}, 1967 1968 {"Stereo1 DAC MIXL", "DAC L1 Switch", "DAC1 MIXL"}, 1969 {"Stereo1 DAC MIXL", "DAC R1 Switch", "DAC1 MIXR"}, 1970 1971 {"Stereo1 DAC MIXR", "DAC R1 Switch", "DAC1 MIXR"}, 1972 {"Stereo1 DAC MIXR", "DAC L1 Switch", "DAC1 MIXL"}, 1973 1974 {"DAC L1 Source", "DAC1", "DAC1 MIXL"}, 1975 {"DAC L1 Source", "Stereo1 DAC Mixer", "Stereo1 DAC MIXL"}, 1976 {"DAC R1 Source", "DAC1", "DAC1 MIXR"}, 1977 {"DAC R1 Source", "Stereo1 DAC Mixer", "Stereo1 DAC MIXR"}, 1978 1979 {"DAC L1", NULL, "DAC L1 Source"}, 1980 {"DAC R1", NULL, "DAC R1 Source"}, 1981 1982 {"DAC L1", NULL, "DAC 1 Clock"}, 1983 {"DAC R1", NULL, "DAC 1 Clock"}, 1984 1985 {"HP Amp", NULL, "DAC L1"}, 1986 {"HP Amp", NULL, "DAC R1"}, 1987 {"HP Amp", NULL, "HP Amp L"}, 1988 {"HP Amp", NULL, "HP Amp R"}, 1989 {"HP Amp", NULL, "Capless"}, 1990 {"HP Amp", NULL, "Charge Pump"}, 1991 {"HP Amp", NULL, "CLKDET SYS"}, 1992 {"HP Amp", NULL, "Vref1"}, 1993 {"HPOL Playback", "Switch", "HP Amp"}, 1994 {"HPOR Playback", "Switch", "HP Amp"}, 1995 {"HPOL", NULL, "HPOL Playback"}, 1996 {"HPOR", NULL, "HPOR Playback"}, 1997 }; 1998 1999 static int rt5682_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask, 2000 unsigned int rx_mask, int slots, int slot_width) 2001 { 2002 struct snd_soc_component *component = dai->component; 2003 unsigned int cl, val = 0; 2004 2005 if (tx_mask || rx_mask) 2006 snd_soc_component_update_bits(component, RT5682_TDM_ADDA_CTRL_2, 2007 RT5682_TDM_EN, RT5682_TDM_EN); 2008 else 2009 snd_soc_component_update_bits(component, RT5682_TDM_ADDA_CTRL_2, 2010 RT5682_TDM_EN, 0); 2011 2012 switch (slots) { 2013 case 4: 2014 val |= RT5682_TDM_TX_CH_4; 2015 val |= RT5682_TDM_RX_CH_4; 2016 break; 2017 case 6: 2018 val |= RT5682_TDM_TX_CH_6; 2019 val |= RT5682_TDM_RX_CH_6; 2020 break; 2021 case 8: 2022 val |= RT5682_TDM_TX_CH_8; 2023 val |= RT5682_TDM_RX_CH_8; 2024 break; 2025 case 2: 2026 break; 2027 default: 2028 return -EINVAL; 2029 } 2030 2031 snd_soc_component_update_bits(component, RT5682_TDM_CTRL, 2032 RT5682_TDM_TX_CH_MASK | RT5682_TDM_RX_CH_MASK, val); 2033 2034 switch (slot_width) { 2035 case 8: 2036 if (tx_mask || rx_mask) 2037 return -EINVAL; 2038 cl = RT5682_I2S1_TX_CHL_8 | RT5682_I2S1_RX_CHL_8; 2039 break; 2040 case 16: 2041 val = RT5682_TDM_CL_16; 2042 cl = RT5682_I2S1_TX_CHL_16 | RT5682_I2S1_RX_CHL_16; 2043 break; 2044 case 20: 2045 val = RT5682_TDM_CL_20; 2046 cl = RT5682_I2S1_TX_CHL_20 | RT5682_I2S1_RX_CHL_20; 2047 break; 2048 case 24: 2049 val = RT5682_TDM_CL_24; 2050 cl = RT5682_I2S1_TX_CHL_24 | RT5682_I2S1_RX_CHL_24; 2051 break; 2052 case 32: 2053 val = RT5682_TDM_CL_32; 2054 cl = RT5682_I2S1_TX_CHL_32 | RT5682_I2S1_RX_CHL_32; 2055 break; 2056 default: 2057 return -EINVAL; 2058 } 2059 2060 snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL, 2061 RT5682_TDM_CL_MASK, val); 2062 snd_soc_component_update_bits(component, RT5682_I2S1_SDP, 2063 RT5682_I2S1_TX_CHL_MASK | RT5682_I2S1_RX_CHL_MASK, cl); 2064 2065 return 0; 2066 } 2067 2068 2069 static int rt5682_hw_params(struct snd_pcm_substream *substream, 2070 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) 2071 { 2072 struct snd_soc_component *component = dai->component; 2073 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 2074 unsigned int len_1 = 0, len_2 = 0; 2075 int pre_div, frame_size; 2076 2077 rt5682->lrck[dai->id] = params_rate(params); 2078 pre_div = rl6231_get_clk_info(rt5682->sysclk, rt5682->lrck[dai->id]); 2079 2080 frame_size = snd_soc_params_to_frame_size(params); 2081 if (frame_size < 0) { 2082 dev_err(component->dev, "Unsupported frame size: %d\n", 2083 frame_size); 2084 return -EINVAL; 2085 } 2086 2087 dev_dbg(dai->dev, "lrck is %dHz and pre_div is %d for iis %d\n", 2088 rt5682->lrck[dai->id], pre_div, dai->id); 2089 2090 switch (params_width(params)) { 2091 case 16: 2092 break; 2093 case 20: 2094 len_1 |= RT5682_I2S1_DL_20; 2095 len_2 |= RT5682_I2S2_DL_20; 2096 break; 2097 case 24: 2098 len_1 |= RT5682_I2S1_DL_24; 2099 len_2 |= RT5682_I2S2_DL_24; 2100 break; 2101 case 32: 2102 len_1 |= RT5682_I2S1_DL_32; 2103 len_2 |= RT5682_I2S2_DL_24; 2104 break; 2105 case 8: 2106 len_1 |= RT5682_I2S2_DL_8; 2107 len_2 |= RT5682_I2S2_DL_8; 2108 break; 2109 default: 2110 return -EINVAL; 2111 } 2112 2113 switch (dai->id) { 2114 case RT5682_AIF1: 2115 snd_soc_component_update_bits(component, RT5682_I2S1_SDP, 2116 RT5682_I2S1_DL_MASK, len_1); 2117 if (rt5682->master[RT5682_AIF1]) { 2118 snd_soc_component_update_bits(component, 2119 RT5682_ADDA_CLK_1, RT5682_I2S_M_DIV_MASK | 2120 RT5682_I2S_CLK_SRC_MASK, 2121 pre_div << RT5682_I2S_M_DIV_SFT | 2122 (rt5682->sysclk_src) << RT5682_I2S_CLK_SRC_SFT); 2123 } 2124 if (params_channels(params) == 1) /* mono mode */ 2125 snd_soc_component_update_bits(component, 2126 RT5682_I2S1_SDP, RT5682_I2S1_MONO_MASK, 2127 RT5682_I2S1_MONO_EN); 2128 else 2129 snd_soc_component_update_bits(component, 2130 RT5682_I2S1_SDP, RT5682_I2S1_MONO_MASK, 2131 RT5682_I2S1_MONO_DIS); 2132 break; 2133 case RT5682_AIF2: 2134 snd_soc_component_update_bits(component, RT5682_I2S2_SDP, 2135 RT5682_I2S2_DL_MASK, len_2); 2136 if (rt5682->master[RT5682_AIF2]) { 2137 snd_soc_component_update_bits(component, 2138 RT5682_I2S_M_CLK_CTRL_1, RT5682_I2S2_M_PD_MASK, 2139 pre_div << RT5682_I2S2_M_PD_SFT); 2140 } 2141 if (params_channels(params) == 1) /* mono mode */ 2142 snd_soc_component_update_bits(component, 2143 RT5682_I2S2_SDP, RT5682_I2S2_MONO_MASK, 2144 RT5682_I2S2_MONO_EN); 2145 else 2146 snd_soc_component_update_bits(component, 2147 RT5682_I2S2_SDP, RT5682_I2S2_MONO_MASK, 2148 RT5682_I2S2_MONO_DIS); 2149 break; 2150 default: 2151 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id); 2152 return -EINVAL; 2153 } 2154 2155 return 0; 2156 } 2157 2158 static int rt5682_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) 2159 { 2160 struct snd_soc_component *component = dai->component; 2161 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 2162 unsigned int reg_val = 0, tdm_ctrl = 0; 2163 2164 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 2165 case SND_SOC_DAIFMT_CBM_CFM: 2166 rt5682->master[dai->id] = 1; 2167 break; 2168 case SND_SOC_DAIFMT_CBS_CFS: 2169 rt5682->master[dai->id] = 0; 2170 break; 2171 default: 2172 return -EINVAL; 2173 } 2174 2175 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 2176 case SND_SOC_DAIFMT_NB_NF: 2177 break; 2178 case SND_SOC_DAIFMT_IB_NF: 2179 reg_val |= RT5682_I2S_BP_INV; 2180 tdm_ctrl |= RT5682_TDM_S_BP_INV; 2181 break; 2182 case SND_SOC_DAIFMT_NB_IF: 2183 if (dai->id == RT5682_AIF1) 2184 tdm_ctrl |= RT5682_TDM_S_LP_INV | RT5682_TDM_M_BP_INV; 2185 else 2186 return -EINVAL; 2187 break; 2188 case SND_SOC_DAIFMT_IB_IF: 2189 if (dai->id == RT5682_AIF1) 2190 tdm_ctrl |= RT5682_TDM_S_BP_INV | RT5682_TDM_S_LP_INV | 2191 RT5682_TDM_M_BP_INV | RT5682_TDM_M_LP_INV; 2192 else 2193 return -EINVAL; 2194 break; 2195 default: 2196 return -EINVAL; 2197 } 2198 2199 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 2200 case SND_SOC_DAIFMT_I2S: 2201 break; 2202 case SND_SOC_DAIFMT_LEFT_J: 2203 reg_val |= RT5682_I2S_DF_LEFT; 2204 tdm_ctrl |= RT5682_TDM_DF_LEFT; 2205 break; 2206 case SND_SOC_DAIFMT_DSP_A: 2207 reg_val |= RT5682_I2S_DF_PCM_A; 2208 tdm_ctrl |= RT5682_TDM_DF_PCM_A; 2209 break; 2210 case SND_SOC_DAIFMT_DSP_B: 2211 reg_val |= RT5682_I2S_DF_PCM_B; 2212 tdm_ctrl |= RT5682_TDM_DF_PCM_B; 2213 break; 2214 default: 2215 return -EINVAL; 2216 } 2217 2218 switch (dai->id) { 2219 case RT5682_AIF1: 2220 snd_soc_component_update_bits(component, RT5682_I2S1_SDP, 2221 RT5682_I2S_DF_MASK, reg_val); 2222 snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL, 2223 RT5682_TDM_MS_MASK | RT5682_TDM_S_BP_MASK | 2224 RT5682_TDM_DF_MASK | RT5682_TDM_M_BP_MASK | 2225 RT5682_TDM_M_LP_MASK | RT5682_TDM_S_LP_MASK, 2226 tdm_ctrl | rt5682->master[dai->id]); 2227 break; 2228 case RT5682_AIF2: 2229 if (rt5682->master[dai->id] == 0) 2230 reg_val |= RT5682_I2S2_MS_S; 2231 snd_soc_component_update_bits(component, RT5682_I2S2_SDP, 2232 RT5682_I2S2_MS_MASK | RT5682_I2S_BP_MASK | 2233 RT5682_I2S_DF_MASK, reg_val); 2234 break; 2235 default: 2236 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id); 2237 return -EINVAL; 2238 } 2239 return 0; 2240 } 2241 2242 static int rt5682_set_component_sysclk(struct snd_soc_component *component, 2243 int clk_id, int source, unsigned int freq, int dir) 2244 { 2245 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 2246 unsigned int reg_val = 0, src = 0; 2247 2248 if (freq == rt5682->sysclk && clk_id == rt5682->sysclk_src) 2249 return 0; 2250 2251 switch (clk_id) { 2252 case RT5682_SCLK_S_MCLK: 2253 reg_val |= RT5682_SCLK_SRC_MCLK; 2254 src = RT5682_CLK_SRC_MCLK; 2255 break; 2256 case RT5682_SCLK_S_PLL1: 2257 reg_val |= RT5682_SCLK_SRC_PLL1; 2258 src = RT5682_CLK_SRC_PLL1; 2259 break; 2260 case RT5682_SCLK_S_PLL2: 2261 reg_val |= RT5682_SCLK_SRC_PLL2; 2262 src = RT5682_CLK_SRC_PLL2; 2263 break; 2264 case RT5682_SCLK_S_RCCLK: 2265 reg_val |= RT5682_SCLK_SRC_RCCLK; 2266 src = RT5682_CLK_SRC_RCCLK; 2267 break; 2268 default: 2269 dev_err(component->dev, "Invalid clock id (%d)\n", clk_id); 2270 return -EINVAL; 2271 } 2272 snd_soc_component_update_bits(component, RT5682_GLB_CLK, 2273 RT5682_SCLK_SRC_MASK, reg_val); 2274 2275 if (rt5682->master[RT5682_AIF2]) { 2276 snd_soc_component_update_bits(component, 2277 RT5682_I2S_M_CLK_CTRL_1, RT5682_I2S2_SRC_MASK, 2278 src << RT5682_I2S2_SRC_SFT); 2279 } 2280 2281 rt5682->sysclk = freq; 2282 rt5682->sysclk_src = clk_id; 2283 2284 dev_dbg(component->dev, "Sysclk is %dHz and clock id is %d\n", 2285 freq, clk_id); 2286 2287 return 0; 2288 } 2289 2290 static int rt5682_set_component_pll(struct snd_soc_component *component, 2291 int pll_id, int source, unsigned int freq_in, 2292 unsigned int freq_out) 2293 { 2294 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 2295 struct rl6231_pll_code pll_code, pll2f_code, pll2b_code; 2296 unsigned int pll2_fout1; 2297 int ret; 2298 2299 if (source == rt5682->pll_src[pll_id] && 2300 freq_in == rt5682->pll_in[pll_id] && 2301 freq_out == rt5682->pll_out[pll_id]) 2302 return 0; 2303 2304 if (!freq_in || !freq_out) { 2305 dev_dbg(component->dev, "PLL disabled\n"); 2306 2307 rt5682->pll_in[pll_id] = 0; 2308 rt5682->pll_out[pll_id] = 0; 2309 snd_soc_component_update_bits(component, RT5682_GLB_CLK, 2310 RT5682_SCLK_SRC_MASK, RT5682_SCLK_SRC_MCLK); 2311 return 0; 2312 } 2313 2314 if (pll_id == RT5682_PLL2) { 2315 switch (source) { 2316 case RT5682_PLL2_S_MCLK: 2317 snd_soc_component_update_bits(component, 2318 RT5682_GLB_CLK, RT5682_PLL2_SRC_MASK, 2319 RT5682_PLL2_SRC_MCLK); 2320 break; 2321 default: 2322 dev_err(component->dev, "Unknown PLL2 Source %d\n", 2323 source); 2324 return -EINVAL; 2325 } 2326 2327 /** 2328 * PLL2 concatenates 2 PLL units. 2329 * We suggest the Fout of the front PLL is 3.84MHz. 2330 */ 2331 pll2_fout1 = 3840000; 2332 ret = rl6231_pll_calc(freq_in, pll2_fout1, &pll2f_code); 2333 if (ret < 0) { 2334 dev_err(component->dev, "Unsupport input clock %d\n", 2335 freq_in); 2336 return ret; 2337 } 2338 dev_dbg(component->dev, "PLL2F: fin=%d fout=%d bypass=%d m=%d n=%d k=%d\n", 2339 freq_in, pll2_fout1, 2340 pll2f_code.m_bp, 2341 (pll2f_code.m_bp ? 0 : pll2f_code.m_code), 2342 pll2f_code.n_code, pll2f_code.k_code); 2343 2344 ret = rl6231_pll_calc(pll2_fout1, freq_out, &pll2b_code); 2345 if (ret < 0) { 2346 dev_err(component->dev, "Unsupport input clock %d\n", 2347 pll2_fout1); 2348 return ret; 2349 } 2350 dev_dbg(component->dev, "PLL2B: fin=%d fout=%d bypass=%d m=%d n=%d k=%d\n", 2351 pll2_fout1, freq_out, 2352 pll2b_code.m_bp, 2353 (pll2b_code.m_bp ? 0 : pll2b_code.m_code), 2354 pll2b_code.n_code, pll2b_code.k_code); 2355 2356 snd_soc_component_write(component, RT5682_PLL2_CTRL_1, 2357 pll2f_code.k_code << RT5682_PLL2F_K_SFT | 2358 pll2b_code.k_code << RT5682_PLL2B_K_SFT | 2359 pll2b_code.m_code); 2360 snd_soc_component_write(component, RT5682_PLL2_CTRL_2, 2361 pll2f_code.m_code << RT5682_PLL2F_M_SFT | 2362 pll2b_code.n_code); 2363 snd_soc_component_write(component, RT5682_PLL2_CTRL_3, 2364 pll2f_code.n_code << RT5682_PLL2F_N_SFT); 2365 snd_soc_component_update_bits(component, RT5682_PLL2_CTRL_4, 2366 RT5682_PLL2B_M_BP_MASK | RT5682_PLL2F_M_BP_MASK | 0xf, 2367 (pll2b_code.m_bp ? 1 : 0) << RT5682_PLL2B_M_BP_SFT | 2368 (pll2f_code.m_bp ? 1 : 0) << RT5682_PLL2F_M_BP_SFT | 2369 0xf); 2370 } else { 2371 switch (source) { 2372 case RT5682_PLL1_S_MCLK: 2373 snd_soc_component_update_bits(component, 2374 RT5682_GLB_CLK, RT5682_PLL1_SRC_MASK, 2375 RT5682_PLL1_SRC_MCLK); 2376 break; 2377 case RT5682_PLL1_S_BCLK1: 2378 snd_soc_component_update_bits(component, 2379 RT5682_GLB_CLK, RT5682_PLL1_SRC_MASK, 2380 RT5682_PLL1_SRC_BCLK1); 2381 break; 2382 default: 2383 dev_err(component->dev, "Unknown PLL1 Source %d\n", 2384 source); 2385 return -EINVAL; 2386 } 2387 2388 ret = rl6231_pll_calc(freq_in, freq_out, &pll_code); 2389 if (ret < 0) { 2390 dev_err(component->dev, "Unsupport input clock %d\n", 2391 freq_in); 2392 return ret; 2393 } 2394 2395 dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n", 2396 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code), 2397 pll_code.n_code, pll_code.k_code); 2398 2399 snd_soc_component_write(component, RT5682_PLL_CTRL_1, 2400 pll_code.n_code << RT5682_PLL_N_SFT | pll_code.k_code); 2401 snd_soc_component_write(component, RT5682_PLL_CTRL_2, 2402 (pll_code.m_bp ? 0 : pll_code.m_code) << RT5682_PLL_M_SFT | 2403 pll_code.m_bp << RT5682_PLL_M_BP_SFT | RT5682_PLL_RST); 2404 } 2405 2406 rt5682->pll_in[pll_id] = freq_in; 2407 rt5682->pll_out[pll_id] = freq_out; 2408 rt5682->pll_src[pll_id] = source; 2409 2410 return 0; 2411 } 2412 2413 static int rt5682_set_bclk1_ratio(struct snd_soc_dai *dai, unsigned int ratio) 2414 { 2415 struct snd_soc_component *component = dai->component; 2416 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 2417 2418 rt5682->bclk[dai->id] = ratio; 2419 2420 switch (ratio) { 2421 case 256: 2422 snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL, 2423 RT5682_TDM_BCLK_MS1_MASK, RT5682_TDM_BCLK_MS1_256); 2424 break; 2425 case 128: 2426 snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL, 2427 RT5682_TDM_BCLK_MS1_MASK, RT5682_TDM_BCLK_MS1_128); 2428 break; 2429 case 64: 2430 snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL, 2431 RT5682_TDM_BCLK_MS1_MASK, RT5682_TDM_BCLK_MS1_64); 2432 break; 2433 case 32: 2434 snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL, 2435 RT5682_TDM_BCLK_MS1_MASK, RT5682_TDM_BCLK_MS1_32); 2436 break; 2437 default: 2438 dev_err(dai->dev, "Invalid bclk1 ratio %d\n", ratio); 2439 return -EINVAL; 2440 } 2441 2442 return 0; 2443 } 2444 2445 static int rt5682_set_bclk2_ratio(struct snd_soc_dai *dai, unsigned int ratio) 2446 { 2447 struct snd_soc_component *component = dai->component; 2448 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 2449 2450 rt5682->bclk[dai->id] = ratio; 2451 2452 switch (ratio) { 2453 case 64: 2454 snd_soc_component_update_bits(component, RT5682_ADDA_CLK_2, 2455 RT5682_I2S2_BCLK_MS2_MASK, 2456 RT5682_I2S2_BCLK_MS2_64); 2457 break; 2458 case 32: 2459 snd_soc_component_update_bits(component, RT5682_ADDA_CLK_2, 2460 RT5682_I2S2_BCLK_MS2_MASK, 2461 RT5682_I2S2_BCLK_MS2_32); 2462 break; 2463 default: 2464 dev_err(dai->dev, "Invalid bclk2 ratio %d\n", ratio); 2465 return -EINVAL; 2466 } 2467 2468 return 0; 2469 } 2470 2471 static int rt5682_set_bias_level(struct snd_soc_component *component, 2472 enum snd_soc_bias_level level) 2473 { 2474 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 2475 2476 switch (level) { 2477 case SND_SOC_BIAS_PREPARE: 2478 regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_1, 2479 RT5682_PWR_BG, RT5682_PWR_BG); 2480 regmap_update_bits(rt5682->regmap, RT5682_PWR_DIG_1, 2481 RT5682_DIG_GATE_CTRL | RT5682_PWR_LDO, 2482 RT5682_DIG_GATE_CTRL | RT5682_PWR_LDO); 2483 break; 2484 2485 case SND_SOC_BIAS_STANDBY: 2486 regmap_update_bits(rt5682->regmap, RT5682_PWR_DIG_1, 2487 RT5682_DIG_GATE_CTRL, RT5682_DIG_GATE_CTRL); 2488 break; 2489 case SND_SOC_BIAS_OFF: 2490 regmap_update_bits(rt5682->regmap, RT5682_PWR_DIG_1, 2491 RT5682_DIG_GATE_CTRL | RT5682_PWR_LDO, 0); 2492 regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_1, 2493 RT5682_PWR_BG, 0); 2494 break; 2495 2496 default: 2497 break; 2498 } 2499 2500 return 0; 2501 } 2502 2503 #ifdef CONFIG_COMMON_CLK 2504 #define CLK_PLL2_FIN 48000000 2505 #define CLK_PLL2_FOUT 24576000 2506 #define CLK_48 48000 2507 2508 static bool rt5682_clk_check(struct rt5682_priv *rt5682) 2509 { 2510 if (!rt5682->master[RT5682_AIF1]) { 2511 dev_err(rt5682->component->dev, "sysclk/dai not set correctly\n"); 2512 return false; 2513 } 2514 return true; 2515 } 2516 2517 static int rt5682_wclk_prepare(struct clk_hw *hw) 2518 { 2519 struct rt5682_priv *rt5682 = 2520 container_of(hw, struct rt5682_priv, 2521 dai_clks_hw[RT5682_DAI_WCLK_IDX]); 2522 struct snd_soc_component *component = rt5682->component; 2523 struct snd_soc_dapm_context *dapm = 2524 snd_soc_component_get_dapm(component); 2525 2526 if (!rt5682_clk_check(rt5682)) 2527 return -EINVAL; 2528 2529 snd_soc_dapm_mutex_lock(dapm); 2530 2531 snd_soc_dapm_force_enable_pin_unlocked(dapm, "MICBIAS"); 2532 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_1, 2533 RT5682_PWR_MB, RT5682_PWR_MB); 2534 snd_soc_dapm_force_enable_pin_unlocked(dapm, "I2S1"); 2535 snd_soc_dapm_force_enable_pin_unlocked(dapm, "PLL2F"); 2536 snd_soc_dapm_force_enable_pin_unlocked(dapm, "PLL2B"); 2537 snd_soc_dapm_sync_unlocked(dapm); 2538 2539 snd_soc_dapm_mutex_unlock(dapm); 2540 2541 return 0; 2542 } 2543 2544 static void rt5682_wclk_unprepare(struct clk_hw *hw) 2545 { 2546 struct rt5682_priv *rt5682 = 2547 container_of(hw, struct rt5682_priv, 2548 dai_clks_hw[RT5682_DAI_WCLK_IDX]); 2549 struct snd_soc_component *component = rt5682->component; 2550 struct snd_soc_dapm_context *dapm = 2551 snd_soc_component_get_dapm(component); 2552 2553 if (!rt5682_clk_check(rt5682)) 2554 return; 2555 2556 snd_soc_dapm_mutex_lock(dapm); 2557 2558 snd_soc_dapm_disable_pin_unlocked(dapm, "MICBIAS"); 2559 if (!rt5682->jack_type) 2560 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_1, 2561 RT5682_PWR_MB, 0); 2562 snd_soc_dapm_disable_pin_unlocked(dapm, "I2S1"); 2563 snd_soc_dapm_disable_pin_unlocked(dapm, "PLL2F"); 2564 snd_soc_dapm_disable_pin_unlocked(dapm, "PLL2B"); 2565 snd_soc_dapm_sync_unlocked(dapm); 2566 2567 snd_soc_dapm_mutex_unlock(dapm); 2568 } 2569 2570 static unsigned long rt5682_wclk_recalc_rate(struct clk_hw *hw, 2571 unsigned long parent_rate) 2572 { 2573 struct rt5682_priv *rt5682 = 2574 container_of(hw, struct rt5682_priv, 2575 dai_clks_hw[RT5682_DAI_WCLK_IDX]); 2576 2577 if (!rt5682_clk_check(rt5682)) 2578 return 0; 2579 /* 2580 * Only accept to set wclk rate to 48kHz temporarily. 2581 */ 2582 return CLK_48; 2583 } 2584 2585 static long rt5682_wclk_round_rate(struct clk_hw *hw, unsigned long rate, 2586 unsigned long *parent_rate) 2587 { 2588 struct rt5682_priv *rt5682 = 2589 container_of(hw, struct rt5682_priv, 2590 dai_clks_hw[RT5682_DAI_WCLK_IDX]); 2591 2592 if (!rt5682_clk_check(rt5682)) 2593 return -EINVAL; 2594 /* 2595 * Only accept to set wclk rate to 48kHz temporarily. 2596 */ 2597 return CLK_48; 2598 } 2599 2600 static int rt5682_wclk_set_rate(struct clk_hw *hw, unsigned long rate, 2601 unsigned long parent_rate) 2602 { 2603 struct rt5682_priv *rt5682 = 2604 container_of(hw, struct rt5682_priv, 2605 dai_clks_hw[RT5682_DAI_WCLK_IDX]); 2606 struct snd_soc_component *component = rt5682->component; 2607 struct clk *parent_clk; 2608 const char * const clk_name = __clk_get_name(hw->clk); 2609 int pre_div; 2610 2611 if (!rt5682_clk_check(rt5682)) 2612 return -EINVAL; 2613 2614 /* 2615 * Whether the wclk's parent clk (mclk) exists or not, please ensure 2616 * it is fixed or set to 48MHz before setting wclk rate. It's a 2617 * temporary limitation. Only accept 48MHz clk as the clk provider. 2618 * 2619 * It will set the codec anyway by assuming mclk is 48MHz. 2620 */ 2621 parent_clk = clk_get_parent(hw->clk); 2622 if (!parent_clk) 2623 dev_warn(component->dev, 2624 "Parent mclk of wclk not acquired in driver. Please ensure mclk was provided as %d Hz.\n", 2625 CLK_PLL2_FIN); 2626 2627 if (parent_rate != CLK_PLL2_FIN) 2628 dev_warn(component->dev, "clk %s only support %d Hz input\n", 2629 clk_name, CLK_PLL2_FIN); 2630 2631 /* 2632 * It's a temporary limitation. Only accept to set wclk rate to 48kHz. 2633 * It will force wclk to 48kHz even it's not. 2634 */ 2635 if (rate != CLK_48) { 2636 dev_warn(component->dev, "clk %s only support %d Hz output\n", 2637 clk_name, CLK_48); 2638 rate = CLK_48; 2639 } 2640 2641 /* 2642 * To achieve the rate conversion from 48MHz to 48kHz, PLL2 is needed. 2643 */ 2644 rt5682_set_component_pll(component, RT5682_PLL2, RT5682_PLL2_S_MCLK, 2645 CLK_PLL2_FIN, CLK_PLL2_FOUT); 2646 2647 rt5682_set_component_sysclk(component, RT5682_SCLK_S_PLL2, 0, 2648 CLK_PLL2_FOUT, SND_SOC_CLOCK_IN); 2649 2650 pre_div = rl6231_get_clk_info(rt5682->sysclk, rate); 2651 2652 snd_soc_component_update_bits(component, RT5682_ADDA_CLK_1, 2653 RT5682_I2S_M_DIV_MASK | RT5682_I2S_CLK_SRC_MASK, 2654 pre_div << RT5682_I2S_M_DIV_SFT | 2655 (rt5682->sysclk_src) << RT5682_I2S_CLK_SRC_SFT); 2656 2657 return 0; 2658 } 2659 2660 static unsigned long rt5682_bclk_recalc_rate(struct clk_hw *hw, 2661 unsigned long parent_rate) 2662 { 2663 struct rt5682_priv *rt5682 = 2664 container_of(hw, struct rt5682_priv, 2665 dai_clks_hw[RT5682_DAI_BCLK_IDX]); 2666 struct snd_soc_component *component = rt5682->component; 2667 unsigned int bclks_per_wclk; 2668 2669 snd_soc_component_read(component, RT5682_TDM_TCON_CTRL, 2670 &bclks_per_wclk); 2671 2672 switch (bclks_per_wclk & RT5682_TDM_BCLK_MS1_MASK) { 2673 case RT5682_TDM_BCLK_MS1_256: 2674 return parent_rate * 256; 2675 case RT5682_TDM_BCLK_MS1_128: 2676 return parent_rate * 128; 2677 case RT5682_TDM_BCLK_MS1_64: 2678 return parent_rate * 64; 2679 case RT5682_TDM_BCLK_MS1_32: 2680 return parent_rate * 32; 2681 default: 2682 return 0; 2683 } 2684 } 2685 2686 static unsigned long rt5682_bclk_get_factor(unsigned long rate, 2687 unsigned long parent_rate) 2688 { 2689 unsigned long factor; 2690 2691 factor = rate / parent_rate; 2692 if (factor < 64) 2693 return 32; 2694 else if (factor < 128) 2695 return 64; 2696 else if (factor < 256) 2697 return 128; 2698 else 2699 return 256; 2700 } 2701 2702 static long rt5682_bclk_round_rate(struct clk_hw *hw, unsigned long rate, 2703 unsigned long *parent_rate) 2704 { 2705 struct rt5682_priv *rt5682 = 2706 container_of(hw, struct rt5682_priv, 2707 dai_clks_hw[RT5682_DAI_BCLK_IDX]); 2708 unsigned long factor; 2709 2710 if (!*parent_rate || !rt5682_clk_check(rt5682)) 2711 return -EINVAL; 2712 2713 /* 2714 * BCLK rates are set as a multiplier of WCLK in HW. 2715 * We don't allow changing the parent WCLK. We just do 2716 * some rounding down based on the parent WCLK rate 2717 * and find the appropriate multiplier of BCLK to 2718 * get the rounded down BCLK value. 2719 */ 2720 factor = rt5682_bclk_get_factor(rate, *parent_rate); 2721 2722 return *parent_rate * factor; 2723 } 2724 2725 static int rt5682_bclk_set_rate(struct clk_hw *hw, unsigned long rate, 2726 unsigned long parent_rate) 2727 { 2728 struct rt5682_priv *rt5682 = 2729 container_of(hw, struct rt5682_priv, 2730 dai_clks_hw[RT5682_DAI_BCLK_IDX]); 2731 struct snd_soc_component *component = rt5682->component; 2732 struct snd_soc_dai *dai = NULL; 2733 unsigned long factor; 2734 2735 if (!rt5682_clk_check(rt5682)) 2736 return -EINVAL; 2737 2738 factor = rt5682_bclk_get_factor(rate, parent_rate); 2739 2740 for_each_component_dais(component, dai) 2741 if (dai->id == RT5682_AIF1) 2742 break; 2743 if (!dai) { 2744 dev_err(component->dev, "dai %d not found in component\n", 2745 RT5682_AIF1); 2746 return -ENODEV; 2747 } 2748 2749 return rt5682_set_bclk1_ratio(dai, factor); 2750 } 2751 2752 static const struct clk_ops rt5682_dai_clk_ops[RT5682_DAI_NUM_CLKS] = { 2753 [RT5682_DAI_WCLK_IDX] = { 2754 .prepare = rt5682_wclk_prepare, 2755 .unprepare = rt5682_wclk_unprepare, 2756 .recalc_rate = rt5682_wclk_recalc_rate, 2757 .round_rate = rt5682_wclk_round_rate, 2758 .set_rate = rt5682_wclk_set_rate, 2759 }, 2760 [RT5682_DAI_BCLK_IDX] = { 2761 .recalc_rate = rt5682_bclk_recalc_rate, 2762 .round_rate = rt5682_bclk_round_rate, 2763 .set_rate = rt5682_bclk_set_rate, 2764 }, 2765 }; 2766 2767 static int rt5682_register_dai_clks(struct snd_soc_component *component) 2768 { 2769 struct device *dev = component->dev; 2770 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 2771 struct rt5682_platform_data *pdata = &rt5682->pdata; 2772 struct clk_init_data init; 2773 struct clk *dai_clk; 2774 struct clk_lookup *dai_clk_lookup; 2775 struct clk_hw *dai_clk_hw; 2776 const char *parent_name; 2777 int i, ret; 2778 2779 for (i = 0; i < RT5682_DAI_NUM_CLKS; ++i) { 2780 dai_clk_hw = &rt5682->dai_clks_hw[i]; 2781 2782 switch (i) { 2783 case RT5682_DAI_WCLK_IDX: 2784 /* Make MCLK the parent of WCLK */ 2785 if (rt5682->mclk) { 2786 parent_name = __clk_get_name(rt5682->mclk); 2787 init.parent_names = &parent_name; 2788 init.num_parents = 1; 2789 } else { 2790 init.parent_names = NULL; 2791 init.num_parents = 0; 2792 } 2793 break; 2794 case RT5682_DAI_BCLK_IDX: 2795 /* Make WCLK the parent of BCLK */ 2796 parent_name = __clk_get_name( 2797 rt5682->dai_clks[RT5682_DAI_WCLK_IDX]); 2798 init.parent_names = &parent_name; 2799 init.num_parents = 1; 2800 break; 2801 default: 2802 dev_err(dev, "Invalid clock index\n"); 2803 ret = -EINVAL; 2804 goto err; 2805 } 2806 2807 init.name = pdata->dai_clk_names[i]; 2808 init.ops = &rt5682_dai_clk_ops[i]; 2809 init.flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_GATE; 2810 dai_clk_hw->init = &init; 2811 2812 dai_clk = devm_clk_register(dev, dai_clk_hw); 2813 if (IS_ERR(dai_clk)) { 2814 dev_warn(dev, "Failed to register %s: %ld\n", 2815 init.name, PTR_ERR(dai_clk)); 2816 ret = PTR_ERR(dai_clk); 2817 goto err; 2818 } 2819 rt5682->dai_clks[i] = dai_clk; 2820 2821 if (dev->of_node) { 2822 devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, 2823 dai_clk_hw); 2824 } else { 2825 dai_clk_lookup = clkdev_create(dai_clk, init.name, 2826 "%s", dev_name(dev)); 2827 if (!dai_clk_lookup) { 2828 ret = -ENOMEM; 2829 goto err; 2830 } else { 2831 rt5682->dai_clks_lookup[i] = dai_clk_lookup; 2832 } 2833 } 2834 } 2835 2836 return 0; 2837 2838 err: 2839 do { 2840 if (rt5682->dai_clks_lookup[i]) 2841 clkdev_drop(rt5682->dai_clks_lookup[i]); 2842 } while (i-- > 0); 2843 2844 return ret; 2845 } 2846 #endif /* CONFIG_COMMON_CLK */ 2847 2848 static int rt5682_probe(struct snd_soc_component *component) 2849 { 2850 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 2851 struct sdw_slave *slave; 2852 unsigned long time; 2853 2854 #ifdef CONFIG_COMMON_CLK 2855 int ret; 2856 #endif 2857 rt5682->component = component; 2858 2859 if (rt5682->is_sdw) { 2860 slave = rt5682->slave; 2861 time = wait_for_completion_timeout( 2862 &slave->initialization_complete, 2863 msecs_to_jiffies(RT5682_PROBE_TIMEOUT)); 2864 if (!time) { 2865 dev_err(&slave->dev, "Initialization not complete, timed out\n"); 2866 return -ETIMEDOUT; 2867 } 2868 } else { 2869 #ifdef CONFIG_COMMON_CLK 2870 /* Check if MCLK provided */ 2871 rt5682->mclk = devm_clk_get(component->dev, "mclk"); 2872 if (IS_ERR(rt5682->mclk)) { 2873 if (PTR_ERR(rt5682->mclk) != -ENOENT) { 2874 ret = PTR_ERR(rt5682->mclk); 2875 return ret; 2876 } 2877 rt5682->mclk = NULL; 2878 } else { 2879 /* Register CCF DAI clock control */ 2880 ret = rt5682_register_dai_clks(component); 2881 if (ret) 2882 return ret; 2883 } 2884 /* Initial setup for CCF */ 2885 rt5682->lrck[RT5682_AIF1] = CLK_48; 2886 #endif 2887 } 2888 2889 return 0; 2890 } 2891 2892 static void rt5682_remove(struct snd_soc_component *component) 2893 { 2894 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 2895 2896 #ifdef CONFIG_COMMON_CLK 2897 int i; 2898 2899 for (i = RT5682_DAI_NUM_CLKS - 1; i >= 0; --i) { 2900 if (rt5682->dai_clks_lookup[i]) 2901 clkdev_drop(rt5682->dai_clks_lookup[i]); 2902 } 2903 #endif 2904 2905 rt5682_reset(rt5682); 2906 } 2907 2908 #ifdef CONFIG_PM 2909 static int rt5682_suspend(struct snd_soc_component *component) 2910 { 2911 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 2912 2913 regcache_cache_only(rt5682->regmap, true); 2914 regcache_mark_dirty(rt5682->regmap); 2915 return 0; 2916 } 2917 2918 static int rt5682_resume(struct snd_soc_component *component) 2919 { 2920 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 2921 2922 regcache_cache_only(rt5682->regmap, false); 2923 regcache_sync(rt5682->regmap); 2924 2925 rt5682_irq(0, rt5682); 2926 2927 return 0; 2928 } 2929 #else 2930 #define rt5682_suspend NULL 2931 #define rt5682_resume NULL 2932 #endif 2933 2934 #define RT5682_STEREO_RATES SNDRV_PCM_RATE_8000_192000 2935 #define RT5682_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ 2936 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8) 2937 2938 static const struct snd_soc_dai_ops rt5682_aif1_dai_ops = { 2939 .hw_params = rt5682_hw_params, 2940 .set_fmt = rt5682_set_dai_fmt, 2941 .set_tdm_slot = rt5682_set_tdm_slot, 2942 .set_bclk_ratio = rt5682_set_bclk1_ratio, 2943 }; 2944 2945 static const struct snd_soc_dai_ops rt5682_aif2_dai_ops = { 2946 .hw_params = rt5682_hw_params, 2947 .set_fmt = rt5682_set_dai_fmt, 2948 .set_bclk_ratio = rt5682_set_bclk2_ratio, 2949 }; 2950 2951 #if IS_ENABLED(CONFIG_SND_SOC_RT5682_SDW) 2952 struct sdw_stream_data { 2953 struct sdw_stream_runtime *sdw_stream; 2954 }; 2955 2956 static int rt5682_set_sdw_stream(struct snd_soc_dai *dai, void *sdw_stream, 2957 int direction) 2958 { 2959 struct sdw_stream_data *stream; 2960 2961 stream = kzalloc(sizeof(*stream), GFP_KERNEL); 2962 if (!stream) 2963 return -ENOMEM; 2964 2965 stream->sdw_stream = (struct sdw_stream_runtime *)sdw_stream; 2966 2967 /* Use tx_mask or rx_mask to configure stream tag and set dma_data */ 2968 if (direction == SNDRV_PCM_STREAM_PLAYBACK) 2969 dai->playback_dma_data = stream; 2970 else 2971 dai->capture_dma_data = stream; 2972 2973 return 0; 2974 } 2975 2976 static void rt5682_sdw_shutdown(struct snd_pcm_substream *substream, 2977 struct snd_soc_dai *dai) 2978 { 2979 struct sdw_stream_data *stream; 2980 2981 stream = snd_soc_dai_get_dma_data(dai, substream); 2982 snd_soc_dai_set_dma_data(dai, substream, NULL); 2983 kfree(stream); 2984 } 2985 2986 static int rt5682_sdw_hw_params(struct snd_pcm_substream *substream, 2987 struct snd_pcm_hw_params *params, 2988 struct snd_soc_dai *dai) 2989 { 2990 struct snd_soc_component *component = dai->component; 2991 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 2992 struct sdw_stream_config stream_config; 2993 struct sdw_port_config port_config; 2994 enum sdw_data_direction direction; 2995 struct sdw_stream_data *stream; 2996 int retval, port, num_channels; 2997 unsigned int val_p = 0, val_c = 0, osr_p = 0, osr_c = 0; 2998 2999 dev_dbg(dai->dev, "%s %s", __func__, dai->name); 3000 stream = snd_soc_dai_get_dma_data(dai, substream); 3001 3002 if (!stream) 3003 return -ENOMEM; 3004 3005 if (!rt5682->slave) 3006 return -EINVAL; 3007 3008 /* SoundWire specific configuration */ 3009 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 3010 direction = SDW_DATA_DIR_RX; 3011 port = 1; 3012 } else { 3013 direction = SDW_DATA_DIR_TX; 3014 port = 2; 3015 } 3016 3017 stream_config.frame_rate = params_rate(params); 3018 stream_config.ch_count = params_channels(params); 3019 stream_config.bps = snd_pcm_format_width(params_format(params)); 3020 stream_config.direction = direction; 3021 3022 num_channels = params_channels(params); 3023 port_config.ch_mask = (1 << (num_channels)) - 1; 3024 port_config.num = port; 3025 3026 retval = sdw_stream_add_slave(rt5682->slave, &stream_config, 3027 &port_config, 1, stream->sdw_stream); 3028 if (retval) { 3029 dev_err(dai->dev, "Unable to configure port\n"); 3030 return retval; 3031 } 3032 3033 switch (params_rate(params)) { 3034 case 48000: 3035 val_p = RT5682_SDW_REF_1_48K; 3036 val_c = RT5682_SDW_REF_2_48K; 3037 break; 3038 case 96000: 3039 val_p = RT5682_SDW_REF_1_96K; 3040 val_c = RT5682_SDW_REF_2_96K; 3041 break; 3042 case 192000: 3043 val_p = RT5682_SDW_REF_1_192K; 3044 val_c = RT5682_SDW_REF_2_192K; 3045 break; 3046 case 32000: 3047 val_p = RT5682_SDW_REF_1_32K; 3048 val_c = RT5682_SDW_REF_2_32K; 3049 break; 3050 case 24000: 3051 val_p = RT5682_SDW_REF_1_24K; 3052 val_c = RT5682_SDW_REF_2_24K; 3053 break; 3054 case 16000: 3055 val_p = RT5682_SDW_REF_1_16K; 3056 val_c = RT5682_SDW_REF_2_16K; 3057 break; 3058 case 12000: 3059 val_p = RT5682_SDW_REF_1_12K; 3060 val_c = RT5682_SDW_REF_2_12K; 3061 break; 3062 case 8000: 3063 val_p = RT5682_SDW_REF_1_8K; 3064 val_c = RT5682_SDW_REF_2_8K; 3065 break; 3066 case 44100: 3067 val_p = RT5682_SDW_REF_1_44K; 3068 val_c = RT5682_SDW_REF_2_44K; 3069 break; 3070 case 88200: 3071 val_p = RT5682_SDW_REF_1_88K; 3072 val_c = RT5682_SDW_REF_2_88K; 3073 break; 3074 case 176400: 3075 val_p = RT5682_SDW_REF_1_176K; 3076 val_c = RT5682_SDW_REF_2_176K; 3077 break; 3078 case 22050: 3079 val_p = RT5682_SDW_REF_1_22K; 3080 val_c = RT5682_SDW_REF_2_22K; 3081 break; 3082 case 11025: 3083 val_p = RT5682_SDW_REF_1_11K; 3084 val_c = RT5682_SDW_REF_2_11K; 3085 break; 3086 default: 3087 return -EINVAL; 3088 } 3089 3090 if (params_rate(params) <= 48000) { 3091 osr_p = RT5682_DAC_OSR_D_8; 3092 osr_c = RT5682_ADC_OSR_D_8; 3093 } else if (params_rate(params) <= 96000) { 3094 osr_p = RT5682_DAC_OSR_D_4; 3095 osr_c = RT5682_ADC_OSR_D_4; 3096 } else { 3097 osr_p = RT5682_DAC_OSR_D_2; 3098 osr_c = RT5682_ADC_OSR_D_2; 3099 } 3100 3101 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 3102 regmap_update_bits(rt5682->regmap, RT5682_SDW_REF_CLK, 3103 RT5682_SDW_REF_1_MASK, val_p); 3104 regmap_update_bits(rt5682->regmap, RT5682_ADDA_CLK_1, 3105 RT5682_DAC_OSR_MASK, osr_p); 3106 } else { 3107 regmap_update_bits(rt5682->regmap, RT5682_SDW_REF_CLK, 3108 RT5682_SDW_REF_2_MASK, val_c); 3109 regmap_update_bits(rt5682->regmap, RT5682_ADDA_CLK_1, 3110 RT5682_ADC_OSR_MASK, osr_c); 3111 } 3112 3113 return retval; 3114 } 3115 3116 static int rt5682_sdw_hw_free(struct snd_pcm_substream *substream, 3117 struct snd_soc_dai *dai) 3118 { 3119 struct snd_soc_component *component = dai->component; 3120 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 3121 struct sdw_stream_data *stream = 3122 snd_soc_dai_get_dma_data(dai, substream); 3123 3124 if (!rt5682->slave) 3125 return -EINVAL; 3126 3127 sdw_stream_remove_slave(rt5682->slave, stream->sdw_stream); 3128 return 0; 3129 } 3130 3131 static struct snd_soc_dai_ops rt5682_sdw_ops = { 3132 .hw_params = rt5682_sdw_hw_params, 3133 .hw_free = rt5682_sdw_hw_free, 3134 .set_sdw_stream = rt5682_set_sdw_stream, 3135 .shutdown = rt5682_sdw_shutdown, 3136 }; 3137 #endif 3138 3139 static struct snd_soc_dai_driver rt5682_dai[] = { 3140 { 3141 .name = "rt5682-aif1", 3142 .id = RT5682_AIF1, 3143 .playback = { 3144 .stream_name = "AIF1 Playback", 3145 .channels_min = 1, 3146 .channels_max = 2, 3147 .rates = RT5682_STEREO_RATES, 3148 .formats = RT5682_FORMATS, 3149 }, 3150 .capture = { 3151 .stream_name = "AIF1 Capture", 3152 .channels_min = 1, 3153 .channels_max = 2, 3154 .rates = RT5682_STEREO_RATES, 3155 .formats = RT5682_FORMATS, 3156 }, 3157 .ops = &rt5682_aif1_dai_ops, 3158 }, 3159 { 3160 .name = "rt5682-aif2", 3161 .id = RT5682_AIF2, 3162 .capture = { 3163 .stream_name = "AIF2 Capture", 3164 .channels_min = 1, 3165 .channels_max = 2, 3166 .rates = RT5682_STEREO_RATES, 3167 .formats = RT5682_FORMATS, 3168 }, 3169 .ops = &rt5682_aif2_dai_ops, 3170 }, 3171 #if IS_ENABLED(CONFIG_SND_SOC_RT5682_SDW) 3172 { 3173 .name = "rt5682-sdw", 3174 .id = RT5682_SDW, 3175 .playback = { 3176 .stream_name = "SDW Playback", 3177 .channels_min = 1, 3178 .channels_max = 2, 3179 .rates = RT5682_STEREO_RATES, 3180 .formats = RT5682_FORMATS, 3181 }, 3182 .capture = { 3183 .stream_name = "SDW Capture", 3184 .channels_min = 1, 3185 .channels_max = 2, 3186 .rates = RT5682_STEREO_RATES, 3187 .formats = RT5682_FORMATS, 3188 }, 3189 .ops = &rt5682_sdw_ops, 3190 }, 3191 #endif 3192 }; 3193 3194 static const struct snd_soc_component_driver soc_component_dev_rt5682 = { 3195 .probe = rt5682_probe, 3196 .remove = rt5682_remove, 3197 .suspend = rt5682_suspend, 3198 .resume = rt5682_resume, 3199 .set_bias_level = rt5682_set_bias_level, 3200 .controls = rt5682_snd_controls, 3201 .num_controls = ARRAY_SIZE(rt5682_snd_controls), 3202 .dapm_widgets = rt5682_dapm_widgets, 3203 .num_dapm_widgets = ARRAY_SIZE(rt5682_dapm_widgets), 3204 .dapm_routes = rt5682_dapm_routes, 3205 .num_dapm_routes = ARRAY_SIZE(rt5682_dapm_routes), 3206 .set_sysclk = rt5682_set_component_sysclk, 3207 .set_pll = rt5682_set_component_pll, 3208 .set_jack = rt5682_set_jack_detect, 3209 .use_pmdown_time = 1, 3210 .endianness = 1, 3211 .non_legacy_dai_naming = 1, 3212 }; 3213 3214 static const struct regmap_config rt5682_regmap = { 3215 .reg_bits = 16, 3216 .val_bits = 16, 3217 .max_register = RT5682_I2C_MODE, 3218 .volatile_reg = rt5682_volatile_register, 3219 .readable_reg = rt5682_readable_register, 3220 .cache_type = REGCACHE_RBTREE, 3221 .reg_defaults = rt5682_reg, 3222 .num_reg_defaults = ARRAY_SIZE(rt5682_reg), 3223 .use_single_read = true, 3224 .use_single_write = true, 3225 }; 3226 3227 static const struct i2c_device_id rt5682_i2c_id[] = { 3228 {"rt5682", 0}, 3229 {} 3230 }; 3231 MODULE_DEVICE_TABLE(i2c, rt5682_i2c_id); 3232 3233 static int rt5682_parse_dt(struct rt5682_priv *rt5682, struct device *dev) 3234 { 3235 3236 device_property_read_u32(dev, "realtek,dmic1-data-pin", 3237 &rt5682->pdata.dmic1_data_pin); 3238 device_property_read_u32(dev, "realtek,dmic1-clk-pin", 3239 &rt5682->pdata.dmic1_clk_pin); 3240 device_property_read_u32(dev, "realtek,jd-src", 3241 &rt5682->pdata.jd_src); 3242 device_property_read_u32(dev, "realtek,btndet-delay", 3243 &rt5682->pdata.btndet_delay); 3244 device_property_read_u32(dev, "realtek,dmic-clk-rate-hz", 3245 &rt5682->pdata.dmic_clk_rate); 3246 device_property_read_u32(dev, "realtek,dmic-delay-ms", 3247 &rt5682->pdata.dmic_delay); 3248 3249 rt5682->pdata.ldo1_en = of_get_named_gpio(dev->of_node, 3250 "realtek,ldo1-en-gpios", 0); 3251 3252 if (device_property_read_string_array(dev, "clock-output-names", 3253 rt5682->pdata.dai_clk_names, 3254 RT5682_DAI_NUM_CLKS) < 0) 3255 dev_warn(dev, "Using default DAI clk names: %s, %s\n", 3256 rt5682->pdata.dai_clk_names[RT5682_DAI_WCLK_IDX], 3257 rt5682->pdata.dai_clk_names[RT5682_DAI_BCLK_IDX]); 3258 3259 return 0; 3260 } 3261 3262 static void rt5682_calibrate(struct rt5682_priv *rt5682) 3263 { 3264 int value, count; 3265 3266 mutex_lock(&rt5682->calibrate_mutex); 3267 3268 rt5682_reset(rt5682); 3269 regmap_write(rt5682->regmap, RT5682_I2C_CTRL, 0x000f); 3270 regmap_write(rt5682->regmap, RT5682_PWR_ANLG_1, 0xa2af); 3271 usleep_range(15000, 20000); 3272 regmap_write(rt5682->regmap, RT5682_PWR_ANLG_1, 0xf2af); 3273 regmap_write(rt5682->regmap, RT5682_MICBIAS_2, 0x0300); 3274 regmap_write(rt5682->regmap, RT5682_GLB_CLK, 0x8000); 3275 regmap_write(rt5682->regmap, RT5682_PWR_DIG_1, 0x0100); 3276 regmap_write(rt5682->regmap, RT5682_HP_IMP_SENS_CTRL_19, 0x3800); 3277 regmap_write(rt5682->regmap, RT5682_CHOP_DAC, 0x3000); 3278 regmap_write(rt5682->regmap, RT5682_CALIB_ADC_CTRL, 0x7005); 3279 regmap_write(rt5682->regmap, RT5682_STO1_ADC_MIXER, 0x686c); 3280 regmap_write(rt5682->regmap, RT5682_CAL_REC, 0x0d0d); 3281 regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_2, 0x0321); 3282 regmap_write(rt5682->regmap, RT5682_HP_LOGIC_CTRL_2, 0x0004); 3283 regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_1, 0x7c00); 3284 regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_3, 0x06a1); 3285 regmap_write(rt5682->regmap, RT5682_A_DAC1_MUX, 0x0311); 3286 regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_1, 0x7c00); 3287 3288 regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_1, 0xfc00); 3289 3290 for (count = 0; count < 60; count++) { 3291 regmap_read(rt5682->regmap, RT5682_HP_CALIB_STA_1, &value); 3292 if (!(value & 0x8000)) 3293 break; 3294 3295 usleep_range(10000, 10005); 3296 } 3297 3298 if (count >= 60) 3299 pr_err("HP Calibration Failure\n"); 3300 3301 /* restore settings */ 3302 regmap_write(rt5682->regmap, RT5682_PWR_ANLG_1, 0x02af); 3303 regmap_write(rt5682->regmap, RT5682_MICBIAS_2, 0x0080); 3304 regmap_write(rt5682->regmap, RT5682_GLB_CLK, 0x0000); 3305 regmap_write(rt5682->regmap, RT5682_PWR_DIG_1, 0x0000); 3306 regmap_write(rt5682->regmap, RT5682_CHOP_DAC, 0x2000); 3307 regmap_write(rt5682->regmap, RT5682_CALIB_ADC_CTRL, 0x2005); 3308 regmap_write(rt5682->regmap, RT5682_STO1_ADC_MIXER, 0xc0c4); 3309 3310 mutex_unlock(&rt5682->calibrate_mutex); 3311 3312 } 3313 3314 #if IS_ENABLED(CONFIG_SND_SOC_RT5682_SDW) 3315 static int rt5682_sdw_read(void *context, unsigned int reg, unsigned int *val) 3316 { 3317 struct device *dev = context; 3318 struct rt5682_priv *rt5682 = dev_get_drvdata(dev); 3319 unsigned int data_l, data_h; 3320 3321 regmap_write(rt5682->sdw_regmap, RT5682_SDW_CMD, 0); 3322 regmap_write(rt5682->sdw_regmap, RT5682_SDW_ADDR_H, (reg >> 8) & 0xff); 3323 regmap_write(rt5682->sdw_regmap, RT5682_SDW_ADDR_L, (reg & 0xff)); 3324 regmap_read(rt5682->sdw_regmap, RT5682_SDW_DATA_H, &data_h); 3325 regmap_read(rt5682->sdw_regmap, RT5682_SDW_DATA_L, &data_l); 3326 3327 *val = (data_h << 8) | data_l; 3328 3329 dev_vdbg(dev, "[%s] %04x => %04x\n", __func__, reg, *val); 3330 3331 return 0; 3332 } 3333 3334 static int rt5682_sdw_write(void *context, unsigned int reg, unsigned int val) 3335 { 3336 struct device *dev = context; 3337 struct rt5682_priv *rt5682 = dev_get_drvdata(dev); 3338 3339 regmap_write(rt5682->sdw_regmap, RT5682_SDW_CMD, 1); 3340 regmap_write(rt5682->sdw_regmap, RT5682_SDW_ADDR_H, (reg >> 8) & 0xff); 3341 regmap_write(rt5682->sdw_regmap, RT5682_SDW_ADDR_L, (reg & 0xff)); 3342 regmap_write(rt5682->sdw_regmap, RT5682_SDW_DATA_H, (val >> 8) & 0xff); 3343 regmap_write(rt5682->sdw_regmap, RT5682_SDW_DATA_L, (val & 0xff)); 3344 3345 dev_vdbg(dev, "[%s] %04x <= %04x\n", __func__, reg, val); 3346 3347 return 0; 3348 } 3349 3350 static const struct regmap_config rt5682_sdw_regmap = { 3351 .reg_bits = 16, 3352 .val_bits = 16, 3353 .max_register = RT5682_I2C_MODE, 3354 .volatile_reg = rt5682_volatile_register, 3355 .readable_reg = rt5682_readable_register, 3356 .cache_type = REGCACHE_RBTREE, 3357 .reg_defaults = rt5682_reg, 3358 .num_reg_defaults = ARRAY_SIZE(rt5682_reg), 3359 .use_single_read = true, 3360 .use_single_write = true, 3361 .reg_read = rt5682_sdw_read, 3362 .reg_write = rt5682_sdw_write, 3363 }; 3364 3365 int rt5682_sdw_init(struct device *dev, struct regmap *regmap, 3366 struct sdw_slave *slave) 3367 { 3368 struct rt5682_priv *rt5682; 3369 int ret; 3370 3371 rt5682 = devm_kzalloc(dev, sizeof(*rt5682), GFP_KERNEL); 3372 if (!rt5682) 3373 return -ENOMEM; 3374 3375 dev_set_drvdata(dev, rt5682); 3376 rt5682->slave = slave; 3377 rt5682->sdw_regmap = regmap; 3378 rt5682->is_sdw = true; 3379 3380 rt5682->regmap = devm_regmap_init(dev, NULL, dev, &rt5682_sdw_regmap); 3381 if (IS_ERR(rt5682->regmap)) { 3382 ret = PTR_ERR(rt5682->regmap); 3383 dev_err(dev, "Failed to allocate register map: %d\n", 3384 ret); 3385 return ret; 3386 } 3387 3388 /* 3389 * Mark hw_init to false 3390 * HW init will be performed when device reports present 3391 */ 3392 rt5682->hw_init = false; 3393 rt5682->first_hw_init = false; 3394 3395 mutex_init(&rt5682->calibrate_mutex); 3396 INIT_DELAYED_WORK(&rt5682->jack_detect_work, 3397 rt5682_jack_detect_handler); 3398 3399 ret = devm_snd_soc_register_component(dev, &soc_component_dev_rt5682, 3400 rt5682_dai, ARRAY_SIZE(rt5682_dai)); 3401 3402 dev_dbg(&slave->dev, "%s\n", __func__); 3403 3404 return ret; 3405 } 3406 EXPORT_SYMBOL_GPL(rt5682_sdw_init); 3407 3408 int rt5682_io_init(struct device *dev, struct sdw_slave *slave) 3409 { 3410 struct rt5682_priv *rt5682 = dev_get_drvdata(dev); 3411 int ret = 0; 3412 unsigned int val; 3413 3414 if (rt5682->hw_init) 3415 return 0; 3416 3417 regmap_read(rt5682->regmap, RT5682_DEVICE_ID, &val); 3418 if (val != DEVICE_ID) { 3419 pr_err("Device with ID register %x is not rt5682\n", val); 3420 return -ENODEV; 3421 } 3422 3423 /* 3424 * PM runtime is only enabled when a Slave reports as Attached 3425 */ 3426 if (!rt5682->first_hw_init) { 3427 /* set autosuspend parameters */ 3428 pm_runtime_set_autosuspend_delay(&slave->dev, 3000); 3429 pm_runtime_use_autosuspend(&slave->dev); 3430 3431 /* update count of parent 'active' children */ 3432 pm_runtime_set_active(&slave->dev); 3433 3434 /* make sure the device does not suspend immediately */ 3435 pm_runtime_mark_last_busy(&slave->dev); 3436 3437 pm_runtime_enable(&slave->dev); 3438 } 3439 3440 pm_runtime_get_noresume(&slave->dev); 3441 3442 rt5682_reset(rt5682); 3443 3444 if (rt5682->first_hw_init) { 3445 regcache_cache_only(rt5682->regmap, false); 3446 regcache_cache_bypass(rt5682->regmap, true); 3447 } 3448 3449 rt5682_calibrate(rt5682); 3450 3451 if (rt5682->first_hw_init) { 3452 regcache_cache_bypass(rt5682->regmap, false); 3453 regcache_mark_dirty(rt5682->regmap); 3454 regcache_sync(rt5682->regmap); 3455 3456 /* volatile registers */ 3457 regmap_update_bits(rt5682->regmap, RT5682_CBJ_CTRL_2, 3458 RT5682_EXT_JD_SRC, RT5682_EXT_JD_SRC_MANUAL); 3459 3460 goto reinit; 3461 } 3462 3463 ret = regmap_multi_reg_write(rt5682->regmap, patch_list, 3464 ARRAY_SIZE(patch_list)); 3465 if (ret != 0) 3466 dev_warn(dev, "Failed to apply regmap patch: %d\n", ret); 3467 3468 regmap_write(rt5682->regmap, RT5682_DEPOP_1, 0x0000); 3469 3470 regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_1, 3471 RT5682_LDO1_DVO_MASK | RT5682_HP_DRIVER_MASK, 3472 RT5682_LDO1_DVO_12 | RT5682_HP_DRIVER_5X); 3473 regmap_write(rt5682->regmap, RT5682_MICBIAS_2, 0x0380); 3474 regmap_write(rt5682->regmap, RT5682_TEST_MODE_CTRL_1, 0x0000); 3475 regmap_update_bits(rt5682->regmap, RT5682_BIAS_CUR_CTRL_8, 3476 RT5682_HPA_CP_BIAS_CTRL_MASK, RT5682_HPA_CP_BIAS_3UA); 3477 regmap_update_bits(rt5682->regmap, RT5682_CHARGE_PUMP_1, 3478 RT5682_CP_CLK_HP_MASK, RT5682_CP_CLK_HP_300KHZ); 3479 regmap_update_bits(rt5682->regmap, RT5682_HP_CHARGE_PUMP_1, 3480 RT5682_PM_HP_MASK, RT5682_PM_HP_HV); 3481 3482 /* Soundwire */ 3483 regmap_write(rt5682->regmap, RT5682_PLL2_INTERNAL, 0xa266); 3484 regmap_write(rt5682->regmap, RT5682_PLL2_CTRL_1, 0x1700); 3485 regmap_write(rt5682->regmap, RT5682_PLL2_CTRL_2, 0x0006); 3486 regmap_write(rt5682->regmap, RT5682_PLL2_CTRL_3, 0x2600); 3487 regmap_write(rt5682->regmap, RT5682_PLL2_CTRL_4, 0x0c8f); 3488 regmap_write(rt5682->regmap, RT5682_PLL_TRACK_2, 0x3000); 3489 regmap_write(rt5682->regmap, RT5682_PLL_TRACK_3, 0x4000); 3490 regmap_update_bits(rt5682->regmap, RT5682_GLB_CLK, 3491 RT5682_SCLK_SRC_MASK | RT5682_PLL2_SRC_MASK, 3492 RT5682_SCLK_SRC_PLL2 | RT5682_PLL2_SRC_SDW); 3493 3494 regmap_update_bits(rt5682->regmap, RT5682_CBJ_CTRL_2, 3495 RT5682_EXT_JD_SRC, RT5682_EXT_JD_SRC_MANUAL); 3496 regmap_write(rt5682->regmap, RT5682_CBJ_CTRL_1, 0xd042); 3497 regmap_update_bits(rt5682->regmap, RT5682_CBJ_CTRL_3, 3498 RT5682_CBJ_IN_BUF_EN, RT5682_CBJ_IN_BUF_EN); 3499 regmap_update_bits(rt5682->regmap, RT5682_SAR_IL_CMD_1, 3500 RT5682_SAR_POW_MASK, RT5682_SAR_POW_EN); 3501 regmap_update_bits(rt5682->regmap, RT5682_RC_CLK_CTRL, 3502 RT5682_POW_IRQ | RT5682_POW_JDH | 3503 RT5682_POW_ANA, RT5682_POW_IRQ | 3504 RT5682_POW_JDH | RT5682_POW_ANA); 3505 regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_2, 3506 RT5682_PWR_JDH, RT5682_PWR_JDH); 3507 regmap_update_bits(rt5682->regmap, RT5682_IRQ_CTRL_2, 3508 RT5682_JD1_EN_MASK | RT5682_JD1_IRQ_MASK, 3509 RT5682_JD1_EN | RT5682_JD1_IRQ_PUL); 3510 3511 reinit: 3512 mod_delayed_work(system_power_efficient_wq, 3513 &rt5682->jack_detect_work, msecs_to_jiffies(250)); 3514 3515 /* Mark Slave initialization complete */ 3516 rt5682->hw_init = true; 3517 rt5682->first_hw_init = true; 3518 3519 pm_runtime_mark_last_busy(&slave->dev); 3520 pm_runtime_put_autosuspend(&slave->dev); 3521 3522 dev_dbg(&slave->dev, "%s hw_init complete\n", __func__); 3523 3524 return ret; 3525 } 3526 EXPORT_SYMBOL_GPL(rt5682_io_init); 3527 #endif 3528 3529 static int rt5682_i2c_probe(struct i2c_client *i2c, 3530 const struct i2c_device_id *id) 3531 { 3532 struct rt5682_platform_data *pdata = dev_get_platdata(&i2c->dev); 3533 struct rt5682_priv *rt5682; 3534 int i, ret; 3535 unsigned int val; 3536 3537 rt5682 = devm_kzalloc(&i2c->dev, sizeof(struct rt5682_priv), 3538 GFP_KERNEL); 3539 3540 if (rt5682 == NULL) 3541 return -ENOMEM; 3542 3543 i2c_set_clientdata(i2c, rt5682); 3544 3545 rt5682->pdata = i2s_default_platform_data; 3546 3547 if (pdata) 3548 rt5682->pdata = *pdata; 3549 else 3550 rt5682_parse_dt(rt5682, &i2c->dev); 3551 3552 rt5682->regmap = devm_regmap_init_i2c(i2c, &rt5682_regmap); 3553 if (IS_ERR(rt5682->regmap)) { 3554 ret = PTR_ERR(rt5682->regmap); 3555 dev_err(&i2c->dev, "Failed to allocate register map: %d\n", 3556 ret); 3557 return ret; 3558 } 3559 3560 for (i = 0; i < ARRAY_SIZE(rt5682->supplies); i++) 3561 rt5682->supplies[i].supply = rt5682_supply_names[i]; 3562 3563 ret = devm_regulator_bulk_get(&i2c->dev, ARRAY_SIZE(rt5682->supplies), 3564 rt5682->supplies); 3565 if (ret != 0) { 3566 dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret); 3567 return ret; 3568 } 3569 3570 ret = regulator_bulk_enable(ARRAY_SIZE(rt5682->supplies), 3571 rt5682->supplies); 3572 if (ret != 0) { 3573 dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret); 3574 return ret; 3575 } 3576 3577 if (gpio_is_valid(rt5682->pdata.ldo1_en)) { 3578 if (devm_gpio_request_one(&i2c->dev, rt5682->pdata.ldo1_en, 3579 GPIOF_OUT_INIT_HIGH, "rt5682")) 3580 dev_err(&i2c->dev, "Fail gpio_request gpio_ldo\n"); 3581 } 3582 3583 /* Sleep for 300 ms miniumum */ 3584 usleep_range(300000, 350000); 3585 3586 regmap_write(rt5682->regmap, RT5682_I2C_MODE, 0x1); 3587 usleep_range(10000, 15000); 3588 3589 regmap_read(rt5682->regmap, RT5682_DEVICE_ID, &val); 3590 if (val != DEVICE_ID) { 3591 pr_err("Device with ID register %x is not rt5682\n", val); 3592 return -ENODEV; 3593 } 3594 3595 rt5682_reset(rt5682); 3596 3597 mutex_init(&rt5682->calibrate_mutex); 3598 rt5682_calibrate(rt5682); 3599 3600 ret = regmap_multi_reg_write(rt5682->regmap, patch_list, 3601 ARRAY_SIZE(patch_list)); 3602 if (ret != 0) 3603 dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret); 3604 3605 regmap_write(rt5682->regmap, RT5682_DEPOP_1, 0x0000); 3606 3607 /* DMIC pin*/ 3608 if (rt5682->pdata.dmic1_data_pin != RT5682_DMIC1_NULL) { 3609 switch (rt5682->pdata.dmic1_data_pin) { 3610 case RT5682_DMIC1_DATA_GPIO2: /* share with LRCK2 */ 3611 regmap_update_bits(rt5682->regmap, RT5682_DMIC_CTRL_1, 3612 RT5682_DMIC_1_DP_MASK, RT5682_DMIC_1_DP_GPIO2); 3613 regmap_update_bits(rt5682->regmap, RT5682_GPIO_CTRL_1, 3614 RT5682_GP2_PIN_MASK, RT5682_GP2_PIN_DMIC_SDA); 3615 break; 3616 3617 case RT5682_DMIC1_DATA_GPIO5: /* share with DACDAT1 */ 3618 regmap_update_bits(rt5682->regmap, RT5682_DMIC_CTRL_1, 3619 RT5682_DMIC_1_DP_MASK, RT5682_DMIC_1_DP_GPIO5); 3620 regmap_update_bits(rt5682->regmap, RT5682_GPIO_CTRL_1, 3621 RT5682_GP5_PIN_MASK, RT5682_GP5_PIN_DMIC_SDA); 3622 break; 3623 3624 default: 3625 dev_warn(&i2c->dev, "invalid DMIC_DAT pin\n"); 3626 break; 3627 } 3628 3629 switch (rt5682->pdata.dmic1_clk_pin) { 3630 case RT5682_DMIC1_CLK_GPIO1: /* share with IRQ */ 3631 regmap_update_bits(rt5682->regmap, RT5682_GPIO_CTRL_1, 3632 RT5682_GP1_PIN_MASK, RT5682_GP1_PIN_DMIC_CLK); 3633 break; 3634 3635 case RT5682_DMIC1_CLK_GPIO3: /* share with BCLK2 */ 3636 regmap_update_bits(rt5682->regmap, RT5682_GPIO_CTRL_1, 3637 RT5682_GP3_PIN_MASK, RT5682_GP3_PIN_DMIC_CLK); 3638 break; 3639 3640 default: 3641 dev_warn(&i2c->dev, "invalid DMIC_CLK pin\n"); 3642 break; 3643 } 3644 } 3645 3646 regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_1, 3647 RT5682_LDO1_DVO_MASK | RT5682_HP_DRIVER_MASK, 3648 RT5682_LDO1_DVO_12 | RT5682_HP_DRIVER_5X); 3649 regmap_write(rt5682->regmap, RT5682_MICBIAS_2, 0x0380); 3650 regmap_update_bits(rt5682->regmap, RT5682_GPIO_CTRL_1, 3651 RT5682_GP4_PIN_MASK | RT5682_GP5_PIN_MASK, 3652 RT5682_GP4_PIN_ADCDAT1 | RT5682_GP5_PIN_DACDAT1); 3653 regmap_write(rt5682->regmap, RT5682_TEST_MODE_CTRL_1, 0x0000); 3654 regmap_update_bits(rt5682->regmap, RT5682_BIAS_CUR_CTRL_8, 3655 RT5682_HPA_CP_BIAS_CTRL_MASK, RT5682_HPA_CP_BIAS_3UA); 3656 regmap_update_bits(rt5682->regmap, RT5682_CHARGE_PUMP_1, 3657 RT5682_CP_CLK_HP_MASK, RT5682_CP_CLK_HP_300KHZ); 3658 regmap_update_bits(rt5682->regmap, RT5682_HP_CHARGE_PUMP_1, 3659 RT5682_PM_HP_MASK, RT5682_PM_HP_HV); 3660 regmap_update_bits(rt5682->regmap, RT5682_DMIC_CTRL_1, 3661 RT5682_FIFO_CLK_DIV_MASK, RT5682_FIFO_CLK_DIV_2); 3662 3663 INIT_DELAYED_WORK(&rt5682->jack_detect_work, 3664 rt5682_jack_detect_handler); 3665 INIT_DELAYED_WORK(&rt5682->jd_check_work, 3666 rt5682_jd_check_handler); 3667 3668 3669 if (i2c->irq) { 3670 ret = devm_request_threaded_irq(&i2c->dev, i2c->irq, NULL, 3671 rt5682_irq, IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING 3672 | IRQF_ONESHOT, "rt5682", rt5682); 3673 if (ret) 3674 dev_err(&i2c->dev, "Failed to reguest IRQ: %d\n", ret); 3675 3676 } 3677 3678 return devm_snd_soc_register_component(&i2c->dev, 3679 &soc_component_dev_rt5682, 3680 rt5682_dai, ARRAY_SIZE(rt5682_dai)); 3681 } 3682 3683 static void rt5682_i2c_shutdown(struct i2c_client *client) 3684 { 3685 struct rt5682_priv *rt5682 = i2c_get_clientdata(client); 3686 3687 rt5682_reset(rt5682); 3688 } 3689 3690 #ifdef CONFIG_OF 3691 static const struct of_device_id rt5682_of_match[] = { 3692 {.compatible = "realtek,rt5682i"}, 3693 {}, 3694 }; 3695 MODULE_DEVICE_TABLE(of, rt5682_of_match); 3696 #endif 3697 3698 #ifdef CONFIG_ACPI 3699 static const struct acpi_device_id rt5682_acpi_match[] = { 3700 {"10EC5682", 0,}, 3701 {}, 3702 }; 3703 MODULE_DEVICE_TABLE(acpi, rt5682_acpi_match); 3704 #endif 3705 3706 static struct i2c_driver __maybe_unused rt5682_i2c_driver = { 3707 .driver = { 3708 .name = "rt5682", 3709 .of_match_table = of_match_ptr(rt5682_of_match), 3710 .acpi_match_table = ACPI_PTR(rt5682_acpi_match), 3711 }, 3712 .probe = rt5682_i2c_probe, 3713 .shutdown = rt5682_i2c_shutdown, 3714 .id_table = rt5682_i2c_id, 3715 }; 3716 3717 #ifdef CONFIG_I2C 3718 module_i2c_driver(rt5682_i2c_driver); 3719 #endif 3720 3721 MODULE_DESCRIPTION("ASoC RT5682 driver"); 3722 MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>"); 3723 MODULE_LICENSE("GPL v2"); 3724