1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * rt5682.c -- RT5682 ALSA SoC audio component driver 4 * 5 * Copyright 2018 Realtek Semiconductor Corp. 6 * Author: Bard Liao <bardliao@realtek.com> 7 */ 8 9 #include <linux/module.h> 10 #include <linux/moduleparam.h> 11 #include <linux/init.h> 12 #include <linux/delay.h> 13 #include <linux/pm.h> 14 #include <linux/i2c.h> 15 #include <linux/platform_device.h> 16 #include <linux/spi/spi.h> 17 #include <linux/acpi.h> 18 #include <linux/gpio.h> 19 #include <linux/of_gpio.h> 20 #include <linux/regulator/consumer.h> 21 #include <linux/mutex.h> 22 #include <sound/core.h> 23 #include <sound/pcm.h> 24 #include <sound/pcm_params.h> 25 #include <sound/jack.h> 26 #include <sound/soc.h> 27 #include <sound/soc-dapm.h> 28 #include <sound/initval.h> 29 #include <sound/tlv.h> 30 #include <sound/rt5682.h> 31 32 #include "rl6231.h" 33 #include "rt5682.h" 34 35 #define RT5682_NUM_SUPPLIES 3 36 37 static const char *rt5682_supply_names[RT5682_NUM_SUPPLIES] = { 38 "AVDD", 39 "MICVDD", 40 "VBAT", 41 }; 42 43 static const struct rt5682_platform_data i2s_default_platform_data = { 44 .dmic1_data_pin = RT5682_DMIC1_DATA_GPIO2, 45 .dmic1_clk_pin = RT5682_DMIC1_CLK_GPIO3, 46 .jd_src = RT5682_JD1, 47 }; 48 49 struct rt5682_priv { 50 struct snd_soc_component *component; 51 struct rt5682_platform_data pdata; 52 struct regmap *regmap; 53 struct snd_soc_jack *hs_jack; 54 struct regulator_bulk_data supplies[RT5682_NUM_SUPPLIES]; 55 struct delayed_work jack_detect_work; 56 struct delayed_work jd_check_work; 57 struct mutex calibrate_mutex; 58 59 int sysclk; 60 int sysclk_src; 61 int lrck[RT5682_AIFS]; 62 int bclk[RT5682_AIFS]; 63 int master[RT5682_AIFS]; 64 65 int pll_src; 66 int pll_in; 67 int pll_out; 68 69 int jack_type; 70 }; 71 72 static const struct reg_sequence patch_list[] = { 73 {RT5682_HP_IMP_SENS_CTRL_19, 0x1000}, 74 {RT5682_DAC_ADC_DIG_VOL1, 0xa020}, 75 }; 76 77 static const struct reg_default rt5682_reg[] = { 78 {0x0002, 0x8080}, 79 {0x0003, 0x8000}, 80 {0x0005, 0x0000}, 81 {0x0006, 0x0000}, 82 {0x0008, 0x800f}, 83 {0x000b, 0x0000}, 84 {0x0010, 0x4040}, 85 {0x0011, 0x0000}, 86 {0x0012, 0x1404}, 87 {0x0013, 0x1000}, 88 {0x0014, 0xa00a}, 89 {0x0015, 0x0404}, 90 {0x0016, 0x0404}, 91 {0x0019, 0xafaf}, 92 {0x001c, 0x2f2f}, 93 {0x001f, 0x0000}, 94 {0x0022, 0x5757}, 95 {0x0023, 0x0039}, 96 {0x0024, 0x000b}, 97 {0x0026, 0xc0c4}, 98 {0x0029, 0x8080}, 99 {0x002a, 0xa0a0}, 100 {0x002b, 0x0300}, 101 {0x0030, 0x0000}, 102 {0x003c, 0x0080}, 103 {0x0044, 0x0c0c}, 104 {0x0049, 0x0000}, 105 {0x0061, 0x0000}, 106 {0x0062, 0x0000}, 107 {0x0063, 0x003f}, 108 {0x0064, 0x0000}, 109 {0x0065, 0x0000}, 110 {0x0066, 0x0030}, 111 {0x0067, 0x0000}, 112 {0x006b, 0x0000}, 113 {0x006c, 0x0000}, 114 {0x006d, 0x2200}, 115 {0x006e, 0x0a10}, 116 {0x0070, 0x8000}, 117 {0x0071, 0x8000}, 118 {0x0073, 0x0000}, 119 {0x0074, 0x0000}, 120 {0x0075, 0x0002}, 121 {0x0076, 0x0001}, 122 {0x0079, 0x0000}, 123 {0x007a, 0x0000}, 124 {0x007b, 0x0000}, 125 {0x007c, 0x0100}, 126 {0x007e, 0x0000}, 127 {0x0080, 0x0000}, 128 {0x0081, 0x0000}, 129 {0x0082, 0x0000}, 130 {0x0083, 0x0000}, 131 {0x0084, 0x0000}, 132 {0x0085, 0x0000}, 133 {0x0086, 0x0005}, 134 {0x0087, 0x0000}, 135 {0x0088, 0x0000}, 136 {0x008c, 0x0003}, 137 {0x008d, 0x0000}, 138 {0x008e, 0x0060}, 139 {0x008f, 0x1000}, 140 {0x0091, 0x0c26}, 141 {0x0092, 0x0073}, 142 {0x0093, 0x0000}, 143 {0x0094, 0x0080}, 144 {0x0098, 0x0000}, 145 {0x009a, 0x0000}, 146 {0x009b, 0x0000}, 147 {0x009c, 0x0000}, 148 {0x009d, 0x0000}, 149 {0x009e, 0x100c}, 150 {0x009f, 0x0000}, 151 {0x00a0, 0x0000}, 152 {0x00a3, 0x0002}, 153 {0x00a4, 0x0001}, 154 {0x00ae, 0x2040}, 155 {0x00af, 0x0000}, 156 {0x00b6, 0x0000}, 157 {0x00b7, 0x0000}, 158 {0x00b8, 0x0000}, 159 {0x00b9, 0x0002}, 160 {0x00be, 0x0000}, 161 {0x00c0, 0x0160}, 162 {0x00c1, 0x82a0}, 163 {0x00c2, 0x0000}, 164 {0x00d0, 0x0000}, 165 {0x00d1, 0x2244}, 166 {0x00d2, 0x3300}, 167 {0x00d3, 0x2200}, 168 {0x00d4, 0x0000}, 169 {0x00d9, 0x0009}, 170 {0x00da, 0x0000}, 171 {0x00db, 0x0000}, 172 {0x00dc, 0x00c0}, 173 {0x00dd, 0x2220}, 174 {0x00de, 0x3131}, 175 {0x00df, 0x3131}, 176 {0x00e0, 0x3131}, 177 {0x00e2, 0x0000}, 178 {0x00e3, 0x4000}, 179 {0x00e4, 0x0aa0}, 180 {0x00e5, 0x3131}, 181 {0x00e6, 0x3131}, 182 {0x00e7, 0x3131}, 183 {0x00e8, 0x3131}, 184 {0x00ea, 0xb320}, 185 {0x00eb, 0x0000}, 186 {0x00f0, 0x0000}, 187 {0x00f1, 0x00d0}, 188 {0x00f2, 0x00d0}, 189 {0x00f6, 0x0000}, 190 {0x00fa, 0x0000}, 191 {0x00fb, 0x0000}, 192 {0x00fc, 0x0000}, 193 {0x00fd, 0x0000}, 194 {0x00fe, 0x10ec}, 195 {0x00ff, 0x6530}, 196 {0x0100, 0xa0a0}, 197 {0x010b, 0x0000}, 198 {0x010c, 0xae00}, 199 {0x010d, 0xaaa0}, 200 {0x010e, 0x8aa2}, 201 {0x010f, 0x02a2}, 202 {0x0110, 0xc000}, 203 {0x0111, 0x04a2}, 204 {0x0112, 0x2800}, 205 {0x0113, 0x0000}, 206 {0x0117, 0x0100}, 207 {0x0125, 0x0410}, 208 {0x0132, 0x6026}, 209 {0x0136, 0x5555}, 210 {0x0138, 0x3700}, 211 {0x013a, 0x2000}, 212 {0x013b, 0x2000}, 213 {0x013c, 0x2005}, 214 {0x013f, 0x0000}, 215 {0x0142, 0x0000}, 216 {0x0145, 0x0002}, 217 {0x0146, 0x0000}, 218 {0x0147, 0x0000}, 219 {0x0148, 0x0000}, 220 {0x0149, 0x0000}, 221 {0x0150, 0x79a1}, 222 {0x0151, 0x0000}, 223 {0x0160, 0x4ec0}, 224 {0x0161, 0x0080}, 225 {0x0162, 0x0200}, 226 {0x0163, 0x0800}, 227 {0x0164, 0x0000}, 228 {0x0165, 0x0000}, 229 {0x0166, 0x0000}, 230 {0x0167, 0x000f}, 231 {0x0168, 0x000f}, 232 {0x0169, 0x0021}, 233 {0x0190, 0x413d}, 234 {0x0194, 0x0000}, 235 {0x0195, 0x0000}, 236 {0x0197, 0x0022}, 237 {0x0198, 0x0000}, 238 {0x0199, 0x0000}, 239 {0x01af, 0x0000}, 240 {0x01b0, 0x0400}, 241 {0x01b1, 0x0000}, 242 {0x01b2, 0x0000}, 243 {0x01b3, 0x0000}, 244 {0x01b4, 0x0000}, 245 {0x01b5, 0x0000}, 246 {0x01b6, 0x01c3}, 247 {0x01b7, 0x02a0}, 248 {0x01b8, 0x03e9}, 249 {0x01b9, 0x1389}, 250 {0x01ba, 0xc351}, 251 {0x01bb, 0x0009}, 252 {0x01bc, 0x0018}, 253 {0x01bd, 0x002a}, 254 {0x01be, 0x004c}, 255 {0x01bf, 0x0097}, 256 {0x01c0, 0x433d}, 257 {0x01c2, 0x0000}, 258 {0x01c3, 0x0000}, 259 {0x01c4, 0x0000}, 260 {0x01c5, 0x0000}, 261 {0x01c6, 0x0000}, 262 {0x01c7, 0x0000}, 263 {0x01c8, 0x40af}, 264 {0x01c9, 0x0702}, 265 {0x01ca, 0x0000}, 266 {0x01cb, 0x0000}, 267 {0x01cc, 0x5757}, 268 {0x01cd, 0x5757}, 269 {0x01ce, 0x5757}, 270 {0x01cf, 0x5757}, 271 {0x01d0, 0x5757}, 272 {0x01d1, 0x5757}, 273 {0x01d2, 0x5757}, 274 {0x01d3, 0x5757}, 275 {0x01d4, 0x5757}, 276 {0x01d5, 0x5757}, 277 {0x01d6, 0x0000}, 278 {0x01d7, 0x0008}, 279 {0x01d8, 0x0029}, 280 {0x01d9, 0x3333}, 281 {0x01da, 0x0000}, 282 {0x01db, 0x0004}, 283 {0x01dc, 0x0000}, 284 {0x01de, 0x7c00}, 285 {0x01df, 0x0320}, 286 {0x01e0, 0x06a1}, 287 {0x01e1, 0x0000}, 288 {0x01e2, 0x0000}, 289 {0x01e3, 0x0000}, 290 {0x01e4, 0x0000}, 291 {0x01e6, 0x0001}, 292 {0x01e7, 0x0000}, 293 {0x01e8, 0x0000}, 294 {0x01ea, 0x0000}, 295 {0x01eb, 0x0000}, 296 {0x01ec, 0x0000}, 297 {0x01ed, 0x0000}, 298 {0x01ee, 0x0000}, 299 {0x01ef, 0x0000}, 300 {0x01f0, 0x0000}, 301 {0x01f1, 0x0000}, 302 {0x01f2, 0x0000}, 303 {0x01f3, 0x0000}, 304 {0x01f4, 0x0000}, 305 {0x0210, 0x6297}, 306 {0x0211, 0xa005}, 307 {0x0212, 0x824c}, 308 {0x0213, 0xf7ff}, 309 {0x0214, 0xf24c}, 310 {0x0215, 0x0102}, 311 {0x0216, 0x00a3}, 312 {0x0217, 0x0048}, 313 {0x0218, 0xa2c0}, 314 {0x0219, 0x0400}, 315 {0x021a, 0x00c8}, 316 {0x021b, 0x00c0}, 317 {0x021c, 0x0000}, 318 {0x0250, 0x4500}, 319 {0x0251, 0x40b3}, 320 {0x0252, 0x0000}, 321 {0x0253, 0x0000}, 322 {0x0254, 0x0000}, 323 {0x0255, 0x0000}, 324 {0x0256, 0x0000}, 325 {0x0257, 0x0000}, 326 {0x0258, 0x0000}, 327 {0x0259, 0x0000}, 328 {0x025a, 0x0005}, 329 {0x0270, 0x0000}, 330 {0x02ff, 0x0110}, 331 {0x0300, 0x001f}, 332 {0x0301, 0x032c}, 333 {0x0302, 0x5f21}, 334 {0x0303, 0x4000}, 335 {0x0304, 0x4000}, 336 {0x0305, 0x06d5}, 337 {0x0306, 0x8000}, 338 {0x0307, 0x0700}, 339 {0x0310, 0x4560}, 340 {0x0311, 0xa4a8}, 341 {0x0312, 0x7418}, 342 {0x0313, 0x0000}, 343 {0x0314, 0x0006}, 344 {0x0315, 0xffff}, 345 {0x0316, 0xc400}, 346 {0x0317, 0x0000}, 347 {0x03c0, 0x7e00}, 348 {0x03c1, 0x8000}, 349 {0x03c2, 0x8000}, 350 {0x03c3, 0x8000}, 351 {0x03c4, 0x8000}, 352 {0x03c5, 0x8000}, 353 {0x03c6, 0x8000}, 354 {0x03c7, 0x8000}, 355 {0x03c8, 0x8000}, 356 {0x03c9, 0x8000}, 357 {0x03ca, 0x8000}, 358 {0x03cb, 0x8000}, 359 {0x03cc, 0x8000}, 360 {0x03d0, 0x0000}, 361 {0x03d1, 0x0000}, 362 {0x03d2, 0x0000}, 363 {0x03d3, 0x0000}, 364 {0x03d4, 0x2000}, 365 {0x03d5, 0x2000}, 366 {0x03d6, 0x0000}, 367 {0x03d7, 0x0000}, 368 {0x03d8, 0x2000}, 369 {0x03d9, 0x2000}, 370 {0x03da, 0x2000}, 371 {0x03db, 0x2000}, 372 {0x03dc, 0x0000}, 373 {0x03dd, 0x0000}, 374 {0x03de, 0x0000}, 375 {0x03df, 0x2000}, 376 {0x03e0, 0x0000}, 377 {0x03e1, 0x0000}, 378 {0x03e2, 0x0000}, 379 {0x03e3, 0x0000}, 380 {0x03e4, 0x0000}, 381 {0x03e5, 0x0000}, 382 {0x03e6, 0x0000}, 383 {0x03e7, 0x0000}, 384 {0x03e8, 0x0000}, 385 {0x03e9, 0x0000}, 386 {0x03ea, 0x0000}, 387 {0x03eb, 0x0000}, 388 {0x03ec, 0x0000}, 389 {0x03ed, 0x0000}, 390 {0x03ee, 0x0000}, 391 {0x03ef, 0x0000}, 392 {0x03f0, 0x0800}, 393 {0x03f1, 0x0800}, 394 {0x03f2, 0x0800}, 395 {0x03f3, 0x0800}, 396 }; 397 398 static bool rt5682_volatile_register(struct device *dev, unsigned int reg) 399 { 400 switch (reg) { 401 case RT5682_RESET: 402 case RT5682_CBJ_CTRL_2: 403 case RT5682_INT_ST_1: 404 case RT5682_4BTN_IL_CMD_1: 405 case RT5682_AJD1_CTRL: 406 case RT5682_HP_CALIB_CTRL_1: 407 case RT5682_DEVICE_ID: 408 case RT5682_I2C_MODE: 409 case RT5682_HP_CALIB_CTRL_10: 410 case RT5682_EFUSE_CTRL_2: 411 case RT5682_JD_TOP_VC_VTRL: 412 case RT5682_HP_IMP_SENS_CTRL_19: 413 case RT5682_IL_CMD_1: 414 case RT5682_SAR_IL_CMD_2: 415 case RT5682_SAR_IL_CMD_4: 416 case RT5682_SAR_IL_CMD_10: 417 case RT5682_SAR_IL_CMD_11: 418 case RT5682_EFUSE_CTRL_6...RT5682_EFUSE_CTRL_11: 419 case RT5682_HP_CALIB_STA_1...RT5682_HP_CALIB_STA_11: 420 return true; 421 default: 422 return false; 423 } 424 } 425 426 static bool rt5682_readable_register(struct device *dev, unsigned int reg) 427 { 428 switch (reg) { 429 case RT5682_RESET: 430 case RT5682_VERSION_ID: 431 case RT5682_VENDOR_ID: 432 case RT5682_DEVICE_ID: 433 case RT5682_HP_CTRL_1: 434 case RT5682_HP_CTRL_2: 435 case RT5682_HPL_GAIN: 436 case RT5682_HPR_GAIN: 437 case RT5682_I2C_CTRL: 438 case RT5682_CBJ_BST_CTRL: 439 case RT5682_CBJ_CTRL_1: 440 case RT5682_CBJ_CTRL_2: 441 case RT5682_CBJ_CTRL_3: 442 case RT5682_CBJ_CTRL_4: 443 case RT5682_CBJ_CTRL_5: 444 case RT5682_CBJ_CTRL_6: 445 case RT5682_CBJ_CTRL_7: 446 case RT5682_DAC1_DIG_VOL: 447 case RT5682_STO1_ADC_DIG_VOL: 448 case RT5682_STO1_ADC_BOOST: 449 case RT5682_HP_IMP_GAIN_1: 450 case RT5682_HP_IMP_GAIN_2: 451 case RT5682_SIDETONE_CTRL: 452 case RT5682_STO1_ADC_MIXER: 453 case RT5682_AD_DA_MIXER: 454 case RT5682_STO1_DAC_MIXER: 455 case RT5682_A_DAC1_MUX: 456 case RT5682_DIG_INF2_DATA: 457 case RT5682_REC_MIXER: 458 case RT5682_CAL_REC: 459 case RT5682_ALC_BACK_GAIN: 460 case RT5682_PWR_DIG_1: 461 case RT5682_PWR_DIG_2: 462 case RT5682_PWR_ANLG_1: 463 case RT5682_PWR_ANLG_2: 464 case RT5682_PWR_ANLG_3: 465 case RT5682_PWR_MIXER: 466 case RT5682_PWR_VOL: 467 case RT5682_CLK_DET: 468 case RT5682_RESET_LPF_CTRL: 469 case RT5682_RESET_HPF_CTRL: 470 case RT5682_DMIC_CTRL_1: 471 case RT5682_I2S1_SDP: 472 case RT5682_I2S2_SDP: 473 case RT5682_ADDA_CLK_1: 474 case RT5682_ADDA_CLK_2: 475 case RT5682_I2S1_F_DIV_CTRL_1: 476 case RT5682_I2S1_F_DIV_CTRL_2: 477 case RT5682_TDM_CTRL: 478 case RT5682_TDM_ADDA_CTRL_1: 479 case RT5682_TDM_ADDA_CTRL_2: 480 case RT5682_DATA_SEL_CTRL_1: 481 case RT5682_TDM_TCON_CTRL: 482 case RT5682_GLB_CLK: 483 case RT5682_PLL_CTRL_1: 484 case RT5682_PLL_CTRL_2: 485 case RT5682_PLL_TRACK_1: 486 case RT5682_PLL_TRACK_2: 487 case RT5682_PLL_TRACK_3: 488 case RT5682_PLL_TRACK_4: 489 case RT5682_PLL_TRACK_5: 490 case RT5682_PLL_TRACK_6: 491 case RT5682_PLL_TRACK_11: 492 case RT5682_SDW_REF_CLK: 493 case RT5682_DEPOP_1: 494 case RT5682_DEPOP_2: 495 case RT5682_HP_CHARGE_PUMP_1: 496 case RT5682_HP_CHARGE_PUMP_2: 497 case RT5682_MICBIAS_1: 498 case RT5682_MICBIAS_2: 499 case RT5682_PLL_TRACK_12: 500 case RT5682_PLL_TRACK_14: 501 case RT5682_PLL2_CTRL_1: 502 case RT5682_PLL2_CTRL_2: 503 case RT5682_PLL2_CTRL_3: 504 case RT5682_PLL2_CTRL_4: 505 case RT5682_RC_CLK_CTRL: 506 case RT5682_I2S_M_CLK_CTRL_1: 507 case RT5682_I2S2_F_DIV_CTRL_1: 508 case RT5682_I2S2_F_DIV_CTRL_2: 509 case RT5682_EQ_CTRL_1: 510 case RT5682_EQ_CTRL_2: 511 case RT5682_IRQ_CTRL_1: 512 case RT5682_IRQ_CTRL_2: 513 case RT5682_IRQ_CTRL_3: 514 case RT5682_IRQ_CTRL_4: 515 case RT5682_INT_ST_1: 516 case RT5682_GPIO_CTRL_1: 517 case RT5682_GPIO_CTRL_2: 518 case RT5682_GPIO_CTRL_3: 519 case RT5682_HP_AMP_DET_CTRL_1: 520 case RT5682_HP_AMP_DET_CTRL_2: 521 case RT5682_MID_HP_AMP_DET: 522 case RT5682_LOW_HP_AMP_DET: 523 case RT5682_DELAY_BUF_CTRL: 524 case RT5682_SV_ZCD_1: 525 case RT5682_SV_ZCD_2: 526 case RT5682_IL_CMD_1: 527 case RT5682_IL_CMD_2: 528 case RT5682_IL_CMD_3: 529 case RT5682_IL_CMD_4: 530 case RT5682_IL_CMD_5: 531 case RT5682_IL_CMD_6: 532 case RT5682_4BTN_IL_CMD_1: 533 case RT5682_4BTN_IL_CMD_2: 534 case RT5682_4BTN_IL_CMD_3: 535 case RT5682_4BTN_IL_CMD_4: 536 case RT5682_4BTN_IL_CMD_5: 537 case RT5682_4BTN_IL_CMD_6: 538 case RT5682_4BTN_IL_CMD_7: 539 case RT5682_ADC_STO1_HP_CTRL_1: 540 case RT5682_ADC_STO1_HP_CTRL_2: 541 case RT5682_AJD1_CTRL: 542 case RT5682_JD1_THD: 543 case RT5682_JD2_THD: 544 case RT5682_JD_CTRL_1: 545 case RT5682_DUMMY_1: 546 case RT5682_DUMMY_2: 547 case RT5682_DUMMY_3: 548 case RT5682_DAC_ADC_DIG_VOL1: 549 case RT5682_BIAS_CUR_CTRL_2: 550 case RT5682_BIAS_CUR_CTRL_3: 551 case RT5682_BIAS_CUR_CTRL_4: 552 case RT5682_BIAS_CUR_CTRL_5: 553 case RT5682_BIAS_CUR_CTRL_6: 554 case RT5682_BIAS_CUR_CTRL_7: 555 case RT5682_BIAS_CUR_CTRL_8: 556 case RT5682_BIAS_CUR_CTRL_9: 557 case RT5682_BIAS_CUR_CTRL_10: 558 case RT5682_VREF_REC_OP_FB_CAP_CTRL: 559 case RT5682_CHARGE_PUMP_1: 560 case RT5682_DIG_IN_CTRL_1: 561 case RT5682_PAD_DRIVING_CTRL: 562 case RT5682_SOFT_RAMP_DEPOP: 563 case RT5682_CHOP_DAC: 564 case RT5682_CHOP_ADC: 565 case RT5682_CALIB_ADC_CTRL: 566 case RT5682_VOL_TEST: 567 case RT5682_SPKVDD_DET_STA: 568 case RT5682_TEST_MODE_CTRL_1: 569 case RT5682_TEST_MODE_CTRL_2: 570 case RT5682_TEST_MODE_CTRL_3: 571 case RT5682_TEST_MODE_CTRL_4: 572 case RT5682_TEST_MODE_CTRL_5: 573 case RT5682_PLL1_INTERNAL: 574 case RT5682_PLL2_INTERNAL: 575 case RT5682_STO_NG2_CTRL_1: 576 case RT5682_STO_NG2_CTRL_2: 577 case RT5682_STO_NG2_CTRL_3: 578 case RT5682_STO_NG2_CTRL_4: 579 case RT5682_STO_NG2_CTRL_5: 580 case RT5682_STO_NG2_CTRL_6: 581 case RT5682_STO_NG2_CTRL_7: 582 case RT5682_STO_NG2_CTRL_8: 583 case RT5682_STO_NG2_CTRL_9: 584 case RT5682_STO_NG2_CTRL_10: 585 case RT5682_STO1_DAC_SIL_DET: 586 case RT5682_SIL_PSV_CTRL1: 587 case RT5682_SIL_PSV_CTRL2: 588 case RT5682_SIL_PSV_CTRL3: 589 case RT5682_SIL_PSV_CTRL4: 590 case RT5682_SIL_PSV_CTRL5: 591 case RT5682_HP_IMP_SENS_CTRL_01: 592 case RT5682_HP_IMP_SENS_CTRL_02: 593 case RT5682_HP_IMP_SENS_CTRL_03: 594 case RT5682_HP_IMP_SENS_CTRL_04: 595 case RT5682_HP_IMP_SENS_CTRL_05: 596 case RT5682_HP_IMP_SENS_CTRL_06: 597 case RT5682_HP_IMP_SENS_CTRL_07: 598 case RT5682_HP_IMP_SENS_CTRL_08: 599 case RT5682_HP_IMP_SENS_CTRL_09: 600 case RT5682_HP_IMP_SENS_CTRL_10: 601 case RT5682_HP_IMP_SENS_CTRL_11: 602 case RT5682_HP_IMP_SENS_CTRL_12: 603 case RT5682_HP_IMP_SENS_CTRL_13: 604 case RT5682_HP_IMP_SENS_CTRL_14: 605 case RT5682_HP_IMP_SENS_CTRL_15: 606 case RT5682_HP_IMP_SENS_CTRL_16: 607 case RT5682_HP_IMP_SENS_CTRL_17: 608 case RT5682_HP_IMP_SENS_CTRL_18: 609 case RT5682_HP_IMP_SENS_CTRL_19: 610 case RT5682_HP_IMP_SENS_CTRL_20: 611 case RT5682_HP_IMP_SENS_CTRL_21: 612 case RT5682_HP_IMP_SENS_CTRL_22: 613 case RT5682_HP_IMP_SENS_CTRL_23: 614 case RT5682_HP_IMP_SENS_CTRL_24: 615 case RT5682_HP_IMP_SENS_CTRL_25: 616 case RT5682_HP_IMP_SENS_CTRL_26: 617 case RT5682_HP_IMP_SENS_CTRL_27: 618 case RT5682_HP_IMP_SENS_CTRL_28: 619 case RT5682_HP_IMP_SENS_CTRL_29: 620 case RT5682_HP_IMP_SENS_CTRL_30: 621 case RT5682_HP_IMP_SENS_CTRL_31: 622 case RT5682_HP_IMP_SENS_CTRL_32: 623 case RT5682_HP_IMP_SENS_CTRL_33: 624 case RT5682_HP_IMP_SENS_CTRL_34: 625 case RT5682_HP_IMP_SENS_CTRL_35: 626 case RT5682_HP_IMP_SENS_CTRL_36: 627 case RT5682_HP_IMP_SENS_CTRL_37: 628 case RT5682_HP_IMP_SENS_CTRL_38: 629 case RT5682_HP_IMP_SENS_CTRL_39: 630 case RT5682_HP_IMP_SENS_CTRL_40: 631 case RT5682_HP_IMP_SENS_CTRL_41: 632 case RT5682_HP_IMP_SENS_CTRL_42: 633 case RT5682_HP_IMP_SENS_CTRL_43: 634 case RT5682_HP_LOGIC_CTRL_1: 635 case RT5682_HP_LOGIC_CTRL_2: 636 case RT5682_HP_LOGIC_CTRL_3: 637 case RT5682_HP_CALIB_CTRL_1: 638 case RT5682_HP_CALIB_CTRL_2: 639 case RT5682_HP_CALIB_CTRL_3: 640 case RT5682_HP_CALIB_CTRL_4: 641 case RT5682_HP_CALIB_CTRL_5: 642 case RT5682_HP_CALIB_CTRL_6: 643 case RT5682_HP_CALIB_CTRL_7: 644 case RT5682_HP_CALIB_CTRL_9: 645 case RT5682_HP_CALIB_CTRL_10: 646 case RT5682_HP_CALIB_CTRL_11: 647 case RT5682_HP_CALIB_STA_1: 648 case RT5682_HP_CALIB_STA_2: 649 case RT5682_HP_CALIB_STA_3: 650 case RT5682_HP_CALIB_STA_4: 651 case RT5682_HP_CALIB_STA_5: 652 case RT5682_HP_CALIB_STA_6: 653 case RT5682_HP_CALIB_STA_7: 654 case RT5682_HP_CALIB_STA_8: 655 case RT5682_HP_CALIB_STA_9: 656 case RT5682_HP_CALIB_STA_10: 657 case RT5682_HP_CALIB_STA_11: 658 case RT5682_SAR_IL_CMD_1: 659 case RT5682_SAR_IL_CMD_2: 660 case RT5682_SAR_IL_CMD_3: 661 case RT5682_SAR_IL_CMD_4: 662 case RT5682_SAR_IL_CMD_5: 663 case RT5682_SAR_IL_CMD_6: 664 case RT5682_SAR_IL_CMD_7: 665 case RT5682_SAR_IL_CMD_8: 666 case RT5682_SAR_IL_CMD_9: 667 case RT5682_SAR_IL_CMD_10: 668 case RT5682_SAR_IL_CMD_11: 669 case RT5682_SAR_IL_CMD_12: 670 case RT5682_SAR_IL_CMD_13: 671 case RT5682_EFUSE_CTRL_1: 672 case RT5682_EFUSE_CTRL_2: 673 case RT5682_EFUSE_CTRL_3: 674 case RT5682_EFUSE_CTRL_4: 675 case RT5682_EFUSE_CTRL_5: 676 case RT5682_EFUSE_CTRL_6: 677 case RT5682_EFUSE_CTRL_7: 678 case RT5682_EFUSE_CTRL_8: 679 case RT5682_EFUSE_CTRL_9: 680 case RT5682_EFUSE_CTRL_10: 681 case RT5682_EFUSE_CTRL_11: 682 case RT5682_JD_TOP_VC_VTRL: 683 case RT5682_DRC1_CTRL_0: 684 case RT5682_DRC1_CTRL_1: 685 case RT5682_DRC1_CTRL_2: 686 case RT5682_DRC1_CTRL_3: 687 case RT5682_DRC1_CTRL_4: 688 case RT5682_DRC1_CTRL_5: 689 case RT5682_DRC1_CTRL_6: 690 case RT5682_DRC1_HARD_LMT_CTRL_1: 691 case RT5682_DRC1_HARD_LMT_CTRL_2: 692 case RT5682_DRC1_PRIV_1: 693 case RT5682_DRC1_PRIV_2: 694 case RT5682_DRC1_PRIV_3: 695 case RT5682_DRC1_PRIV_4: 696 case RT5682_DRC1_PRIV_5: 697 case RT5682_DRC1_PRIV_6: 698 case RT5682_DRC1_PRIV_7: 699 case RT5682_DRC1_PRIV_8: 700 case RT5682_EQ_AUTO_RCV_CTRL1: 701 case RT5682_EQ_AUTO_RCV_CTRL2: 702 case RT5682_EQ_AUTO_RCV_CTRL3: 703 case RT5682_EQ_AUTO_RCV_CTRL4: 704 case RT5682_EQ_AUTO_RCV_CTRL5: 705 case RT5682_EQ_AUTO_RCV_CTRL6: 706 case RT5682_EQ_AUTO_RCV_CTRL7: 707 case RT5682_EQ_AUTO_RCV_CTRL8: 708 case RT5682_EQ_AUTO_RCV_CTRL9: 709 case RT5682_EQ_AUTO_RCV_CTRL10: 710 case RT5682_EQ_AUTO_RCV_CTRL11: 711 case RT5682_EQ_AUTO_RCV_CTRL12: 712 case RT5682_EQ_AUTO_RCV_CTRL13: 713 case RT5682_ADC_L_EQ_LPF1_A1: 714 case RT5682_R_EQ_LPF1_A1: 715 case RT5682_L_EQ_LPF1_H0: 716 case RT5682_R_EQ_LPF1_H0: 717 case RT5682_L_EQ_BPF1_A1: 718 case RT5682_R_EQ_BPF1_A1: 719 case RT5682_L_EQ_BPF1_A2: 720 case RT5682_R_EQ_BPF1_A2: 721 case RT5682_L_EQ_BPF1_H0: 722 case RT5682_R_EQ_BPF1_H0: 723 case RT5682_L_EQ_BPF2_A1: 724 case RT5682_R_EQ_BPF2_A1: 725 case RT5682_L_EQ_BPF2_A2: 726 case RT5682_R_EQ_BPF2_A2: 727 case RT5682_L_EQ_BPF2_H0: 728 case RT5682_R_EQ_BPF2_H0: 729 case RT5682_L_EQ_BPF3_A1: 730 case RT5682_R_EQ_BPF3_A1: 731 case RT5682_L_EQ_BPF3_A2: 732 case RT5682_R_EQ_BPF3_A2: 733 case RT5682_L_EQ_BPF3_H0: 734 case RT5682_R_EQ_BPF3_H0: 735 case RT5682_L_EQ_BPF4_A1: 736 case RT5682_R_EQ_BPF4_A1: 737 case RT5682_L_EQ_BPF4_A2: 738 case RT5682_R_EQ_BPF4_A2: 739 case RT5682_L_EQ_BPF4_H0: 740 case RT5682_R_EQ_BPF4_H0: 741 case RT5682_L_EQ_HPF1_A1: 742 case RT5682_R_EQ_HPF1_A1: 743 case RT5682_L_EQ_HPF1_H0: 744 case RT5682_R_EQ_HPF1_H0: 745 case RT5682_L_EQ_PRE_VOL: 746 case RT5682_R_EQ_PRE_VOL: 747 case RT5682_L_EQ_POST_VOL: 748 case RT5682_R_EQ_POST_VOL: 749 case RT5682_I2C_MODE: 750 return true; 751 default: 752 return false; 753 } 754 } 755 756 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6525, 75, 0); 757 static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0); 758 static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0); 759 760 /* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */ 761 static const DECLARE_TLV_DB_RANGE(bst_tlv, 762 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0), 763 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0), 764 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0), 765 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0), 766 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0), 767 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0), 768 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0) 769 ); 770 771 /* Interface data select */ 772 static const char * const rt5682_data_select[] = { 773 "L/R", "R/L", "L/L", "R/R" 774 }; 775 776 static SOC_ENUM_SINGLE_DECL(rt5682_if2_adc_enum, 777 RT5682_DIG_INF2_DATA, RT5682_IF2_ADC_SEL_SFT, rt5682_data_select); 778 779 static SOC_ENUM_SINGLE_DECL(rt5682_if1_01_adc_enum, 780 RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC1_SEL_SFT, rt5682_data_select); 781 782 static SOC_ENUM_SINGLE_DECL(rt5682_if1_23_adc_enum, 783 RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC2_SEL_SFT, rt5682_data_select); 784 785 static SOC_ENUM_SINGLE_DECL(rt5682_if1_45_adc_enum, 786 RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC3_SEL_SFT, rt5682_data_select); 787 788 static SOC_ENUM_SINGLE_DECL(rt5682_if1_67_adc_enum, 789 RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC4_SEL_SFT, rt5682_data_select); 790 791 static const struct snd_kcontrol_new rt5682_if2_adc_swap_mux = 792 SOC_DAPM_ENUM("IF2 ADC Swap Mux", rt5682_if2_adc_enum); 793 794 static const struct snd_kcontrol_new rt5682_if1_01_adc_swap_mux = 795 SOC_DAPM_ENUM("IF1 01 ADC Swap Mux", rt5682_if1_01_adc_enum); 796 797 static const struct snd_kcontrol_new rt5682_if1_23_adc_swap_mux = 798 SOC_DAPM_ENUM("IF1 23 ADC Swap Mux", rt5682_if1_23_adc_enum); 799 800 static const struct snd_kcontrol_new rt5682_if1_45_adc_swap_mux = 801 SOC_DAPM_ENUM("IF1 45 ADC Swap Mux", rt5682_if1_45_adc_enum); 802 803 static const struct snd_kcontrol_new rt5682_if1_67_adc_swap_mux = 804 SOC_DAPM_ENUM("IF1 67 ADC Swap Mux", rt5682_if1_67_adc_enum); 805 806 static void rt5682_reset(struct regmap *regmap) 807 { 808 regmap_write(regmap, RT5682_RESET, 0); 809 regmap_write(regmap, RT5682_I2C_MODE, 1); 810 } 811 /** 812 * rt5682_sel_asrc_clk_src - select ASRC clock source for a set of filters 813 * @component: SoC audio component device. 814 * @filter_mask: mask of filters. 815 * @clk_src: clock source 816 * 817 * The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5682 can 818 * only support standard 32fs or 64fs i2s format, ASRC should be enabled to 819 * support special i2s clock format such as Intel's 100fs(100 * sampling rate). 820 * ASRC function will track i2s clock and generate a corresponding system clock 821 * for codec. This function provides an API to select the clock source for a 822 * set of filters specified by the mask. And the component driver will turn on 823 * ASRC for these filters if ASRC is selected as their clock source. 824 */ 825 int rt5682_sel_asrc_clk_src(struct snd_soc_component *component, 826 unsigned int filter_mask, unsigned int clk_src) 827 { 828 829 switch (clk_src) { 830 case RT5682_CLK_SEL_SYS: 831 case RT5682_CLK_SEL_I2S1_ASRC: 832 case RT5682_CLK_SEL_I2S2_ASRC: 833 break; 834 835 default: 836 return -EINVAL; 837 } 838 839 if (filter_mask & RT5682_DA_STEREO1_FILTER) { 840 snd_soc_component_update_bits(component, RT5682_PLL_TRACK_2, 841 RT5682_FILTER_CLK_SEL_MASK, 842 clk_src << RT5682_FILTER_CLK_SEL_SFT); 843 } 844 845 if (filter_mask & RT5682_AD_STEREO1_FILTER) { 846 snd_soc_component_update_bits(component, RT5682_PLL_TRACK_3, 847 RT5682_FILTER_CLK_SEL_MASK, 848 clk_src << RT5682_FILTER_CLK_SEL_SFT); 849 } 850 851 return 0; 852 } 853 EXPORT_SYMBOL_GPL(rt5682_sel_asrc_clk_src); 854 855 static int rt5682_button_detect(struct snd_soc_component *component) 856 { 857 int btn_type, val; 858 859 val = snd_soc_component_read32(component, RT5682_4BTN_IL_CMD_1); 860 btn_type = val & 0xfff0; 861 snd_soc_component_write(component, RT5682_4BTN_IL_CMD_1, val); 862 pr_debug("%s btn_type=%x\n", __func__, btn_type); 863 snd_soc_component_update_bits(component, 864 RT5682_SAR_IL_CMD_2, 0x10, 0x10); 865 866 return btn_type; 867 } 868 869 static void rt5682_enable_push_button_irq(struct snd_soc_component *component, 870 bool enable) 871 { 872 if (enable) { 873 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1, 874 RT5682_SAR_BUTT_DET_MASK, RT5682_SAR_BUTT_DET_EN); 875 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_13, 876 RT5682_SAR_SOUR_MASK, RT5682_SAR_SOUR_BTN); 877 snd_soc_component_write(component, RT5682_IL_CMD_1, 0x0040); 878 snd_soc_component_update_bits(component, RT5682_4BTN_IL_CMD_2, 879 RT5682_4BTN_IL_MASK | RT5682_4BTN_IL_RST_MASK, 880 RT5682_4BTN_IL_EN | RT5682_4BTN_IL_NOR); 881 snd_soc_component_update_bits(component, RT5682_IRQ_CTRL_3, 882 RT5682_IL_IRQ_MASK, RT5682_IL_IRQ_EN); 883 } else { 884 snd_soc_component_update_bits(component, RT5682_IRQ_CTRL_3, 885 RT5682_IL_IRQ_MASK, RT5682_IL_IRQ_DIS); 886 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1, 887 RT5682_SAR_BUTT_DET_MASK, RT5682_SAR_BUTT_DET_DIS); 888 snd_soc_component_update_bits(component, RT5682_4BTN_IL_CMD_2, 889 RT5682_4BTN_IL_MASK, RT5682_4BTN_IL_DIS); 890 snd_soc_component_update_bits(component, RT5682_4BTN_IL_CMD_2, 891 RT5682_4BTN_IL_RST_MASK, RT5682_4BTN_IL_RST); 892 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_13, 893 RT5682_SAR_SOUR_MASK, RT5682_SAR_SOUR_TYPE); 894 } 895 } 896 897 /** 898 * rt5682_headset_detect - Detect headset. 899 * @component: SoC audio component device. 900 * @jack_insert: Jack insert or not. 901 * 902 * Detect whether is headset or not when jack inserted. 903 * 904 * Returns detect status. 905 */ 906 static int rt5682_headset_detect(struct snd_soc_component *component, 907 int jack_insert) 908 { 909 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 910 unsigned int val, count; 911 912 if (jack_insert) { 913 914 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_1, 915 RT5682_PWR_VREF2 | RT5682_PWR_MB, 916 RT5682_PWR_VREF2 | RT5682_PWR_MB); 917 snd_soc_component_update_bits(component, 918 RT5682_PWR_ANLG_1, RT5682_PWR_FV2, 0); 919 usleep_range(15000, 20000); 920 snd_soc_component_update_bits(component, 921 RT5682_PWR_ANLG_1, RT5682_PWR_FV2, RT5682_PWR_FV2); 922 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_3, 923 RT5682_PWR_CBJ, RT5682_PWR_CBJ); 924 925 snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1, 926 RT5682_TRIG_JD_MASK, RT5682_TRIG_JD_HIGH); 927 928 count = 0; 929 val = snd_soc_component_read32(component, RT5682_CBJ_CTRL_2) 930 & RT5682_JACK_TYPE_MASK; 931 while (val == 0 && count < 50) { 932 usleep_range(10000, 15000); 933 val = snd_soc_component_read32(component, 934 RT5682_CBJ_CTRL_2) & RT5682_JACK_TYPE_MASK; 935 count++; 936 } 937 938 switch (val) { 939 case 0x1: 940 case 0x2: 941 rt5682->jack_type = SND_JACK_HEADSET; 942 rt5682_enable_push_button_irq(component, true); 943 break; 944 default: 945 rt5682->jack_type = SND_JACK_HEADPHONE; 946 } 947 948 } else { 949 rt5682_enable_push_button_irq(component, false); 950 snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1, 951 RT5682_TRIG_JD_MASK, RT5682_TRIG_JD_LOW); 952 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_1, 953 RT5682_PWR_VREF2 | RT5682_PWR_MB, 0); 954 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_3, 955 RT5682_PWR_CBJ, 0); 956 957 rt5682->jack_type = 0; 958 } 959 960 dev_dbg(component->dev, "jack_type = %d\n", rt5682->jack_type); 961 return rt5682->jack_type; 962 } 963 964 static irqreturn_t rt5682_irq(int irq, void *data) 965 { 966 struct rt5682_priv *rt5682 = data; 967 968 mod_delayed_work(system_power_efficient_wq, 969 &rt5682->jack_detect_work, msecs_to_jiffies(250)); 970 971 return IRQ_HANDLED; 972 } 973 974 static void rt5682_jd_check_handler(struct work_struct *work) 975 { 976 struct rt5682_priv *rt5682 = container_of(work, struct rt5682_priv, 977 jd_check_work.work); 978 979 if (snd_soc_component_read32(rt5682->component, RT5682_AJD1_CTRL) 980 & RT5682_JDH_RS_MASK) { 981 /* jack out */ 982 rt5682->jack_type = rt5682_headset_detect(rt5682->component, 0); 983 984 snd_soc_jack_report(rt5682->hs_jack, rt5682->jack_type, 985 SND_JACK_HEADSET | 986 SND_JACK_BTN_0 | SND_JACK_BTN_1 | 987 SND_JACK_BTN_2 | SND_JACK_BTN_3); 988 } else { 989 schedule_delayed_work(&rt5682->jd_check_work, 500); 990 } 991 } 992 993 static int rt5682_set_jack_detect(struct snd_soc_component *component, 994 struct snd_soc_jack *hs_jack, void *data) 995 { 996 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 997 998 rt5682->hs_jack = hs_jack; 999 1000 if (!hs_jack) { 1001 regmap_update_bits(rt5682->regmap, RT5682_IRQ_CTRL_2, 1002 RT5682_JD1_EN_MASK, RT5682_JD1_DIS); 1003 regmap_update_bits(rt5682->regmap, RT5682_RC_CLK_CTRL, 1004 RT5682_POW_JDH | RT5682_POW_JDL, 0); 1005 return 0; 1006 } 1007 1008 switch (rt5682->pdata.jd_src) { 1009 case RT5682_JD1: 1010 snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_2, 1011 RT5682_EXT_JD_SRC, RT5682_EXT_JD_SRC_MANUAL); 1012 snd_soc_component_write(component, RT5682_CBJ_CTRL_1, 0xd042); 1013 snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_3, 1014 RT5682_CBJ_IN_BUF_EN, RT5682_CBJ_IN_BUF_EN); 1015 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1, 1016 RT5682_SAR_POW_MASK, RT5682_SAR_POW_EN); 1017 regmap_update_bits(rt5682->regmap, RT5682_GPIO_CTRL_1, 1018 RT5682_GP1_PIN_MASK, RT5682_GP1_PIN_IRQ); 1019 regmap_update_bits(rt5682->regmap, RT5682_RC_CLK_CTRL, 1020 RT5682_POW_IRQ | RT5682_POW_JDH | 1021 RT5682_POW_ANA, RT5682_POW_IRQ | 1022 RT5682_POW_JDH | RT5682_POW_ANA); 1023 regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_2, 1024 RT5682_PWR_JDH | RT5682_PWR_JDL, 1025 RT5682_PWR_JDH | RT5682_PWR_JDL); 1026 regmap_update_bits(rt5682->regmap, RT5682_IRQ_CTRL_2, 1027 RT5682_JD1_EN_MASK | RT5682_JD1_POL_MASK, 1028 RT5682_JD1_EN | RT5682_JD1_POL_NOR); 1029 mod_delayed_work(system_power_efficient_wq, 1030 &rt5682->jack_detect_work, msecs_to_jiffies(250)); 1031 break; 1032 1033 case RT5682_JD_NULL: 1034 regmap_update_bits(rt5682->regmap, RT5682_IRQ_CTRL_2, 1035 RT5682_JD1_EN_MASK, RT5682_JD1_DIS); 1036 regmap_update_bits(rt5682->regmap, RT5682_RC_CLK_CTRL, 1037 RT5682_POW_JDH | RT5682_POW_JDL, 0); 1038 break; 1039 1040 default: 1041 dev_warn(component->dev, "Wrong JD source\n"); 1042 break; 1043 } 1044 1045 return 0; 1046 } 1047 1048 static void rt5682_jack_detect_handler(struct work_struct *work) 1049 { 1050 struct rt5682_priv *rt5682 = 1051 container_of(work, struct rt5682_priv, jack_detect_work.work); 1052 int val, btn_type; 1053 1054 while (!rt5682->component) 1055 usleep_range(10000, 15000); 1056 1057 while (!rt5682->component->card->instantiated) 1058 usleep_range(10000, 15000); 1059 1060 mutex_lock(&rt5682->calibrate_mutex); 1061 1062 val = snd_soc_component_read32(rt5682->component, RT5682_AJD1_CTRL) 1063 & RT5682_JDH_RS_MASK; 1064 if (!val) { 1065 /* jack in */ 1066 if (rt5682->jack_type == 0) { 1067 /* jack was out, report jack type */ 1068 rt5682->jack_type = 1069 rt5682_headset_detect(rt5682->component, 1); 1070 } else { 1071 /* jack is already in, report button event */ 1072 rt5682->jack_type = SND_JACK_HEADSET; 1073 btn_type = rt5682_button_detect(rt5682->component); 1074 /** 1075 * rt5682 can report three kinds of button behavior, 1076 * one click, double click and hold. However, 1077 * currently we will report button pressed/released 1078 * event. So all the three button behaviors are 1079 * treated as button pressed. 1080 */ 1081 switch (btn_type) { 1082 case 0x8000: 1083 case 0x4000: 1084 case 0x2000: 1085 rt5682->jack_type |= SND_JACK_BTN_0; 1086 break; 1087 case 0x1000: 1088 case 0x0800: 1089 case 0x0400: 1090 rt5682->jack_type |= SND_JACK_BTN_1; 1091 break; 1092 case 0x0200: 1093 case 0x0100: 1094 case 0x0080: 1095 rt5682->jack_type |= SND_JACK_BTN_2; 1096 break; 1097 case 0x0040: 1098 case 0x0020: 1099 case 0x0010: 1100 rt5682->jack_type |= SND_JACK_BTN_3; 1101 break; 1102 case 0x0000: /* unpressed */ 1103 break; 1104 default: 1105 btn_type = 0; 1106 dev_err(rt5682->component->dev, 1107 "Unexpected button code 0x%04x\n", 1108 btn_type); 1109 break; 1110 } 1111 } 1112 } else { 1113 /* jack out */ 1114 rt5682->jack_type = rt5682_headset_detect(rt5682->component, 0); 1115 } 1116 1117 snd_soc_jack_report(rt5682->hs_jack, rt5682->jack_type, 1118 SND_JACK_HEADSET | 1119 SND_JACK_BTN_0 | SND_JACK_BTN_1 | 1120 SND_JACK_BTN_2 | SND_JACK_BTN_3); 1121 1122 if (rt5682->jack_type & (SND_JACK_BTN_0 | SND_JACK_BTN_1 | 1123 SND_JACK_BTN_2 | SND_JACK_BTN_3)) 1124 schedule_delayed_work(&rt5682->jd_check_work, 0); 1125 else 1126 cancel_delayed_work_sync(&rt5682->jd_check_work); 1127 1128 mutex_unlock(&rt5682->calibrate_mutex); 1129 } 1130 1131 static const struct snd_kcontrol_new rt5682_snd_controls[] = { 1132 /* DAC Digital Volume */ 1133 SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5682_DAC1_DIG_VOL, 1134 RT5682_L_VOL_SFT + 1, RT5682_R_VOL_SFT + 1, 86, 0, dac_vol_tlv), 1135 1136 /* IN Boost Volume */ 1137 SOC_SINGLE_TLV("CBJ Boost Volume", RT5682_CBJ_BST_CTRL, 1138 RT5682_BST_CBJ_SFT, 8, 0, bst_tlv), 1139 1140 /* ADC Digital Volume Control */ 1141 SOC_DOUBLE("STO1 ADC Capture Switch", RT5682_STO1_ADC_DIG_VOL, 1142 RT5682_L_MUTE_SFT, RT5682_R_MUTE_SFT, 1, 1), 1143 SOC_DOUBLE_TLV("STO1 ADC Capture Volume", RT5682_STO1_ADC_DIG_VOL, 1144 RT5682_L_VOL_SFT + 1, RT5682_R_VOL_SFT + 1, 63, 0, adc_vol_tlv), 1145 1146 /* ADC Boost Volume Control */ 1147 SOC_DOUBLE_TLV("STO1 ADC Boost Gain Volume", RT5682_STO1_ADC_BOOST, 1148 RT5682_STO1_ADC_L_BST_SFT, RT5682_STO1_ADC_R_BST_SFT, 1149 3, 0, adc_bst_tlv), 1150 }; 1151 1152 1153 static int rt5682_div_sel(struct rt5682_priv *rt5682, 1154 int target, const int div[], int size) 1155 { 1156 int i; 1157 1158 if (rt5682->sysclk < target) { 1159 pr_err("sysclk rate %d is too low\n", 1160 rt5682->sysclk); 1161 return 0; 1162 } 1163 1164 for (i = 0; i < size - 1; i++) { 1165 pr_info("div[%d]=%d\n", i, div[i]); 1166 if (target * div[i] == rt5682->sysclk) 1167 return i; 1168 if (target * div[i + 1] > rt5682->sysclk) { 1169 pr_err("can't find div for sysclk %d\n", 1170 rt5682->sysclk); 1171 return i; 1172 } 1173 } 1174 1175 if (target * div[i] < rt5682->sysclk) 1176 pr_err("sysclk rate %d is too high\n", 1177 rt5682->sysclk); 1178 1179 return size - 1; 1180 1181 } 1182 1183 /** 1184 * set_dmic_clk - Set parameter of dmic. 1185 * 1186 * @w: DAPM widget. 1187 * @kcontrol: The kcontrol of this widget. 1188 * @event: Event id. 1189 * 1190 * Choose dmic clock between 1MHz and 3MHz. 1191 * It is better for clock to approximate 3MHz. 1192 */ 1193 static int set_dmic_clk(struct snd_soc_dapm_widget *w, 1194 struct snd_kcontrol *kcontrol, int event) 1195 { 1196 struct snd_soc_component *component = 1197 snd_soc_dapm_to_component(w->dapm); 1198 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 1199 int idx = -EINVAL; 1200 static const int div[] = {2, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, 128}; 1201 1202 idx = rt5682_div_sel(rt5682, 1500000, div, ARRAY_SIZE(div)); 1203 1204 snd_soc_component_update_bits(component, RT5682_DMIC_CTRL_1, 1205 RT5682_DMIC_CLK_MASK, idx << RT5682_DMIC_CLK_SFT); 1206 1207 return 0; 1208 } 1209 1210 static int set_filter_clk(struct snd_soc_dapm_widget *w, 1211 struct snd_kcontrol *kcontrol, int event) 1212 { 1213 struct snd_soc_component *component = 1214 snd_soc_dapm_to_component(w->dapm); 1215 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 1216 int ref, val, reg, idx = -EINVAL; 1217 static const int div_f[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32, 48}; 1218 static const int div_o[] = {1, 2, 4, 6, 8, 12, 16, 24, 32, 48}; 1219 1220 val = snd_soc_component_read32(component, RT5682_GPIO_CTRL_1) & 1221 RT5682_GP4_PIN_MASK; 1222 if (w->shift == RT5682_PWR_ADC_S1F_BIT && 1223 val == RT5682_GP4_PIN_ADCDAT2) 1224 ref = 256 * rt5682->lrck[RT5682_AIF2]; 1225 else 1226 ref = 256 * rt5682->lrck[RT5682_AIF1]; 1227 1228 idx = rt5682_div_sel(rt5682, ref, div_f, ARRAY_SIZE(div_f)); 1229 1230 if (w->shift == RT5682_PWR_ADC_S1F_BIT) 1231 reg = RT5682_PLL_TRACK_3; 1232 else 1233 reg = RT5682_PLL_TRACK_2; 1234 1235 snd_soc_component_update_bits(component, reg, 1236 RT5682_FILTER_CLK_DIV_MASK, idx << RT5682_FILTER_CLK_DIV_SFT); 1237 1238 /* select over sample rate */ 1239 for (idx = 0; idx < ARRAY_SIZE(div_o); idx++) { 1240 if (rt5682->sysclk <= 12288000 * div_o[idx]) 1241 break; 1242 } 1243 1244 snd_soc_component_update_bits(component, RT5682_ADDA_CLK_1, 1245 RT5682_ADC_OSR_MASK | RT5682_DAC_OSR_MASK, 1246 (idx << RT5682_ADC_OSR_SFT) | (idx << RT5682_DAC_OSR_SFT)); 1247 1248 return 0; 1249 } 1250 1251 static int is_sys_clk_from_pll1(struct snd_soc_dapm_widget *w, 1252 struct snd_soc_dapm_widget *sink) 1253 { 1254 unsigned int val; 1255 struct snd_soc_component *component = 1256 snd_soc_dapm_to_component(w->dapm); 1257 1258 val = snd_soc_component_read32(component, RT5682_GLB_CLK); 1259 val &= RT5682_SCLK_SRC_MASK; 1260 if (val == RT5682_SCLK_SRC_PLL1) 1261 return 1; 1262 else 1263 return 0; 1264 } 1265 1266 static int is_using_asrc(struct snd_soc_dapm_widget *w, 1267 struct snd_soc_dapm_widget *sink) 1268 { 1269 unsigned int reg, shift, val; 1270 struct snd_soc_component *component = 1271 snd_soc_dapm_to_component(w->dapm); 1272 1273 switch (w->shift) { 1274 case RT5682_ADC_STO1_ASRC_SFT: 1275 reg = RT5682_PLL_TRACK_3; 1276 shift = RT5682_FILTER_CLK_SEL_SFT; 1277 break; 1278 case RT5682_DAC_STO1_ASRC_SFT: 1279 reg = RT5682_PLL_TRACK_2; 1280 shift = RT5682_FILTER_CLK_SEL_SFT; 1281 break; 1282 default: 1283 return 0; 1284 } 1285 1286 val = (snd_soc_component_read32(component, reg) >> shift) & 0xf; 1287 switch (val) { 1288 case RT5682_CLK_SEL_I2S1_ASRC: 1289 case RT5682_CLK_SEL_I2S2_ASRC: 1290 return 1; 1291 default: 1292 return 0; 1293 } 1294 1295 } 1296 1297 /* Digital Mixer */ 1298 static const struct snd_kcontrol_new rt5682_sto1_adc_l_mix[] = { 1299 SOC_DAPM_SINGLE("ADC1 Switch", RT5682_STO1_ADC_MIXER, 1300 RT5682_M_STO1_ADC_L1_SFT, 1, 1), 1301 SOC_DAPM_SINGLE("ADC2 Switch", RT5682_STO1_ADC_MIXER, 1302 RT5682_M_STO1_ADC_L2_SFT, 1, 1), 1303 }; 1304 1305 static const struct snd_kcontrol_new rt5682_sto1_adc_r_mix[] = { 1306 SOC_DAPM_SINGLE("ADC1 Switch", RT5682_STO1_ADC_MIXER, 1307 RT5682_M_STO1_ADC_R1_SFT, 1, 1), 1308 SOC_DAPM_SINGLE("ADC2 Switch", RT5682_STO1_ADC_MIXER, 1309 RT5682_M_STO1_ADC_R2_SFT, 1, 1), 1310 }; 1311 1312 static const struct snd_kcontrol_new rt5682_dac_l_mix[] = { 1313 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5682_AD_DA_MIXER, 1314 RT5682_M_ADCMIX_L_SFT, 1, 1), 1315 SOC_DAPM_SINGLE("DAC1 Switch", RT5682_AD_DA_MIXER, 1316 RT5682_M_DAC1_L_SFT, 1, 1), 1317 }; 1318 1319 static const struct snd_kcontrol_new rt5682_dac_r_mix[] = { 1320 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5682_AD_DA_MIXER, 1321 RT5682_M_ADCMIX_R_SFT, 1, 1), 1322 SOC_DAPM_SINGLE("DAC1 Switch", RT5682_AD_DA_MIXER, 1323 RT5682_M_DAC1_R_SFT, 1, 1), 1324 }; 1325 1326 static const struct snd_kcontrol_new rt5682_sto1_dac_l_mix[] = { 1327 SOC_DAPM_SINGLE("DAC L1 Switch", RT5682_STO1_DAC_MIXER, 1328 RT5682_M_DAC_L1_STO_L_SFT, 1, 1), 1329 SOC_DAPM_SINGLE("DAC R1 Switch", RT5682_STO1_DAC_MIXER, 1330 RT5682_M_DAC_R1_STO_L_SFT, 1, 1), 1331 }; 1332 1333 static const struct snd_kcontrol_new rt5682_sto1_dac_r_mix[] = { 1334 SOC_DAPM_SINGLE("DAC L1 Switch", RT5682_STO1_DAC_MIXER, 1335 RT5682_M_DAC_L1_STO_R_SFT, 1, 1), 1336 SOC_DAPM_SINGLE("DAC R1 Switch", RT5682_STO1_DAC_MIXER, 1337 RT5682_M_DAC_R1_STO_R_SFT, 1, 1), 1338 }; 1339 1340 /* Analog Input Mixer */ 1341 static const struct snd_kcontrol_new rt5682_rec1_l_mix[] = { 1342 SOC_DAPM_SINGLE("CBJ Switch", RT5682_REC_MIXER, 1343 RT5682_M_CBJ_RM1_L_SFT, 1, 1), 1344 }; 1345 1346 /* STO1 ADC1 Source */ 1347 /* MX-26 [13] [5] */ 1348 static const char * const rt5682_sto1_adc1_src[] = { 1349 "DAC MIX", "ADC" 1350 }; 1351 1352 static SOC_ENUM_SINGLE_DECL( 1353 rt5682_sto1_adc1l_enum, RT5682_STO1_ADC_MIXER, 1354 RT5682_STO1_ADC1L_SRC_SFT, rt5682_sto1_adc1_src); 1355 1356 static const struct snd_kcontrol_new rt5682_sto1_adc1l_mux = 1357 SOC_DAPM_ENUM("Stereo1 ADC1L Source", rt5682_sto1_adc1l_enum); 1358 1359 static SOC_ENUM_SINGLE_DECL( 1360 rt5682_sto1_adc1r_enum, RT5682_STO1_ADC_MIXER, 1361 RT5682_STO1_ADC1R_SRC_SFT, rt5682_sto1_adc1_src); 1362 1363 static const struct snd_kcontrol_new rt5682_sto1_adc1r_mux = 1364 SOC_DAPM_ENUM("Stereo1 ADC1L Source", rt5682_sto1_adc1r_enum); 1365 1366 /* STO1 ADC Source */ 1367 /* MX-26 [11:10] [3:2] */ 1368 static const char * const rt5682_sto1_adc_src[] = { 1369 "ADC1 L", "ADC1 R" 1370 }; 1371 1372 static SOC_ENUM_SINGLE_DECL( 1373 rt5682_sto1_adcl_enum, RT5682_STO1_ADC_MIXER, 1374 RT5682_STO1_ADCL_SRC_SFT, rt5682_sto1_adc_src); 1375 1376 static const struct snd_kcontrol_new rt5682_sto1_adcl_mux = 1377 SOC_DAPM_ENUM("Stereo1 ADCL Source", rt5682_sto1_adcl_enum); 1378 1379 static SOC_ENUM_SINGLE_DECL( 1380 rt5682_sto1_adcr_enum, RT5682_STO1_ADC_MIXER, 1381 RT5682_STO1_ADCR_SRC_SFT, rt5682_sto1_adc_src); 1382 1383 static const struct snd_kcontrol_new rt5682_sto1_adcr_mux = 1384 SOC_DAPM_ENUM("Stereo1 ADCR Source", rt5682_sto1_adcr_enum); 1385 1386 /* STO1 ADC2 Source */ 1387 /* MX-26 [12] [4] */ 1388 static const char * const rt5682_sto1_adc2_src[] = { 1389 "DAC MIX", "DMIC" 1390 }; 1391 1392 static SOC_ENUM_SINGLE_DECL( 1393 rt5682_sto1_adc2l_enum, RT5682_STO1_ADC_MIXER, 1394 RT5682_STO1_ADC2L_SRC_SFT, rt5682_sto1_adc2_src); 1395 1396 static const struct snd_kcontrol_new rt5682_sto1_adc2l_mux = 1397 SOC_DAPM_ENUM("Stereo1 ADC2L Source", rt5682_sto1_adc2l_enum); 1398 1399 static SOC_ENUM_SINGLE_DECL( 1400 rt5682_sto1_adc2r_enum, RT5682_STO1_ADC_MIXER, 1401 RT5682_STO1_ADC2R_SRC_SFT, rt5682_sto1_adc2_src); 1402 1403 static const struct snd_kcontrol_new rt5682_sto1_adc2r_mux = 1404 SOC_DAPM_ENUM("Stereo1 ADC2R Source", rt5682_sto1_adc2r_enum); 1405 1406 /* MX-79 [6:4] I2S1 ADC data location */ 1407 static const unsigned int rt5682_if1_adc_slot_values[] = { 1408 0, 1409 2, 1410 4, 1411 6, 1412 }; 1413 1414 static const char * const rt5682_if1_adc_slot_src[] = { 1415 "Slot 0", "Slot 2", "Slot 4", "Slot 6" 1416 }; 1417 1418 static SOC_VALUE_ENUM_SINGLE_DECL(rt5682_if1_adc_slot_enum, 1419 RT5682_TDM_CTRL, RT5682_TDM_ADC_LCA_SFT, RT5682_TDM_ADC_LCA_MASK, 1420 rt5682_if1_adc_slot_src, rt5682_if1_adc_slot_values); 1421 1422 static const struct snd_kcontrol_new rt5682_if1_adc_slot_mux = 1423 SOC_DAPM_ENUM("IF1 ADC Slot location", rt5682_if1_adc_slot_enum); 1424 1425 /* Analog DAC L1 Source, Analog DAC R1 Source*/ 1426 /* MX-2B [4], MX-2B [0]*/ 1427 static const char * const rt5682_alg_dac1_src[] = { 1428 "Stereo1 DAC Mixer", "DAC1" 1429 }; 1430 1431 static SOC_ENUM_SINGLE_DECL( 1432 rt5682_alg_dac_l1_enum, RT5682_A_DAC1_MUX, 1433 RT5682_A_DACL1_SFT, rt5682_alg_dac1_src); 1434 1435 static const struct snd_kcontrol_new rt5682_alg_dac_l1_mux = 1436 SOC_DAPM_ENUM("Analog DAC L1 Source", rt5682_alg_dac_l1_enum); 1437 1438 static SOC_ENUM_SINGLE_DECL( 1439 rt5682_alg_dac_r1_enum, RT5682_A_DAC1_MUX, 1440 RT5682_A_DACR1_SFT, rt5682_alg_dac1_src); 1441 1442 static const struct snd_kcontrol_new rt5682_alg_dac_r1_mux = 1443 SOC_DAPM_ENUM("Analog DAC R1 Source", rt5682_alg_dac_r1_enum); 1444 1445 /* Out Switch */ 1446 static const struct snd_kcontrol_new hpol_switch = 1447 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5682_HP_CTRL_1, 1448 RT5682_L_MUTE_SFT, 1, 1); 1449 static const struct snd_kcontrol_new hpor_switch = 1450 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5682_HP_CTRL_1, 1451 RT5682_R_MUTE_SFT, 1, 1); 1452 1453 static int rt5682_charge_pump_event(struct snd_soc_dapm_widget *w, 1454 struct snd_kcontrol *kcontrol, int event) 1455 { 1456 struct snd_soc_component *component = 1457 snd_soc_dapm_to_component(w->dapm); 1458 1459 switch (event) { 1460 case SND_SOC_DAPM_PRE_PMU: 1461 snd_soc_component_update_bits(component, 1462 RT5682_HP_CHARGE_PUMP_1, RT5682_PM_HP_MASK, RT5682_PM_HP_HV); 1463 break; 1464 case SND_SOC_DAPM_POST_PMD: 1465 snd_soc_component_update_bits(component, 1466 RT5682_HP_CHARGE_PUMP_1, RT5682_PM_HP_MASK, RT5682_PM_HP_LV); 1467 break; 1468 default: 1469 return 0; 1470 } 1471 1472 return 0; 1473 } 1474 1475 static int rt5682_hp_event(struct snd_soc_dapm_widget *w, 1476 struct snd_kcontrol *kcontrol, int event) 1477 { 1478 struct snd_soc_component *component = 1479 snd_soc_dapm_to_component(w->dapm); 1480 1481 switch (event) { 1482 case SND_SOC_DAPM_PRE_PMU: 1483 snd_soc_component_write(component, 1484 RT5682_HP_LOGIC_CTRL_2, 0x0012); 1485 snd_soc_component_write(component, 1486 RT5682_HP_CTRL_2, 0x6000); 1487 snd_soc_component_update_bits(component, 1488 RT5682_DEPOP_1, 0x60, 0x60); 1489 snd_soc_component_update_bits(component, 1490 RT5682_DAC_ADC_DIG_VOL1, 0x00c0, 0x0080); 1491 break; 1492 1493 case SND_SOC_DAPM_POST_PMD: 1494 snd_soc_component_update_bits(component, 1495 RT5682_DEPOP_1, 0x60, 0x0); 1496 snd_soc_component_write(component, 1497 RT5682_HP_CTRL_2, 0x0000); 1498 snd_soc_component_update_bits(component, 1499 RT5682_DAC_ADC_DIG_VOL1, 0x00c0, 0x0000); 1500 break; 1501 1502 default: 1503 return 0; 1504 } 1505 1506 return 0; 1507 1508 } 1509 1510 static int set_dmic_power(struct snd_soc_dapm_widget *w, 1511 struct snd_kcontrol *kcontrol, int event) 1512 { 1513 switch (event) { 1514 case SND_SOC_DAPM_POST_PMU: 1515 /*Add delay to avoid pop noise*/ 1516 msleep(150); 1517 break; 1518 1519 default: 1520 return 0; 1521 } 1522 1523 return 0; 1524 } 1525 1526 static int rt5655_set_verf(struct snd_soc_dapm_widget *w, 1527 struct snd_kcontrol *kcontrol, int event) 1528 { 1529 struct snd_soc_component *component = 1530 snd_soc_dapm_to_component(w->dapm); 1531 1532 switch (event) { 1533 case SND_SOC_DAPM_PRE_PMU: 1534 switch (w->shift) { 1535 case RT5682_PWR_VREF1_BIT: 1536 snd_soc_component_update_bits(component, 1537 RT5682_PWR_ANLG_1, RT5682_PWR_FV1, 0); 1538 break; 1539 1540 case RT5682_PWR_VREF2_BIT: 1541 snd_soc_component_update_bits(component, 1542 RT5682_PWR_ANLG_1, RT5682_PWR_FV2, 0); 1543 break; 1544 1545 default: 1546 break; 1547 } 1548 break; 1549 1550 case SND_SOC_DAPM_POST_PMU: 1551 usleep_range(15000, 20000); 1552 switch (w->shift) { 1553 case RT5682_PWR_VREF1_BIT: 1554 snd_soc_component_update_bits(component, 1555 RT5682_PWR_ANLG_1, RT5682_PWR_FV1, 1556 RT5682_PWR_FV1); 1557 break; 1558 1559 case RT5682_PWR_VREF2_BIT: 1560 snd_soc_component_update_bits(component, 1561 RT5682_PWR_ANLG_1, RT5682_PWR_FV2, 1562 RT5682_PWR_FV2); 1563 break; 1564 1565 default: 1566 break; 1567 } 1568 break; 1569 1570 default: 1571 return 0; 1572 } 1573 1574 return 0; 1575 } 1576 1577 static const unsigned int rt5682_adcdat_pin_values[] = { 1578 1, 1579 3, 1580 }; 1581 1582 static const char * const rt5682_adcdat_pin_select[] = { 1583 "ADCDAT1", 1584 "ADCDAT2", 1585 }; 1586 1587 static SOC_VALUE_ENUM_SINGLE_DECL(rt5682_adcdat_pin_enum, 1588 RT5682_GPIO_CTRL_1, RT5682_GP4_PIN_SFT, RT5682_GP4_PIN_MASK, 1589 rt5682_adcdat_pin_select, rt5682_adcdat_pin_values); 1590 1591 static const struct snd_kcontrol_new rt5682_adcdat_pin_ctrl = 1592 SOC_DAPM_ENUM("ADCDAT", rt5682_adcdat_pin_enum); 1593 1594 static const struct snd_soc_dapm_widget rt5682_dapm_widgets[] = { 1595 SND_SOC_DAPM_SUPPLY("LDO2", RT5682_PWR_ANLG_3, RT5682_PWR_LDO2_BIT, 1596 0, NULL, 0), 1597 SND_SOC_DAPM_SUPPLY("PLL1", RT5682_PWR_ANLG_3, RT5682_PWR_PLL_BIT, 1598 0, NULL, 0), 1599 SND_SOC_DAPM_SUPPLY("PLL2B", RT5682_PWR_ANLG_3, RT5682_PWR_PLL2B_BIT, 1600 0, NULL, 0), 1601 SND_SOC_DAPM_SUPPLY("PLL2F", RT5682_PWR_ANLG_3, RT5682_PWR_PLL2F_BIT, 1602 0, NULL, 0), 1603 SND_SOC_DAPM_SUPPLY("Vref1", RT5682_PWR_ANLG_1, RT5682_PWR_VREF1_BIT, 0, 1604 rt5655_set_verf, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), 1605 1606 /* ASRC */ 1607 SND_SOC_DAPM_SUPPLY_S("DAC STO1 ASRC", 1, RT5682_PLL_TRACK_1, 1608 RT5682_DAC_STO1_ASRC_SFT, 0, NULL, 0), 1609 SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5682_PLL_TRACK_1, 1610 RT5682_ADC_STO1_ASRC_SFT, 0, NULL, 0), 1611 SND_SOC_DAPM_SUPPLY_S("AD ASRC", 1, RT5682_PLL_TRACK_1, 1612 RT5682_AD_ASRC_SFT, 0, NULL, 0), 1613 SND_SOC_DAPM_SUPPLY_S("DA ASRC", 1, RT5682_PLL_TRACK_1, 1614 RT5682_DA_ASRC_SFT, 0, NULL, 0), 1615 SND_SOC_DAPM_SUPPLY_S("DMIC ASRC", 1, RT5682_PLL_TRACK_1, 1616 RT5682_DMIC_ASRC_SFT, 0, NULL, 0), 1617 1618 /* Input Side */ 1619 SND_SOC_DAPM_SUPPLY("MICBIAS1", RT5682_PWR_ANLG_2, RT5682_PWR_MB1_BIT, 1620 0, NULL, 0), 1621 SND_SOC_DAPM_SUPPLY("MICBIAS2", RT5682_PWR_ANLG_2, RT5682_PWR_MB2_BIT, 1622 0, NULL, 0), 1623 1624 /* Input Lines */ 1625 SND_SOC_DAPM_INPUT("DMIC L1"), 1626 SND_SOC_DAPM_INPUT("DMIC R1"), 1627 1628 SND_SOC_DAPM_INPUT("IN1P"), 1629 1630 SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0, 1631 set_dmic_clk, SND_SOC_DAPM_PRE_PMU), 1632 SND_SOC_DAPM_SUPPLY("DMIC1 Power", RT5682_DMIC_CTRL_1, 1633 RT5682_DMIC_1_EN_SFT, 0, set_dmic_power, SND_SOC_DAPM_POST_PMU), 1634 1635 /* Boost */ 1636 SND_SOC_DAPM_PGA("BST1 CBJ", SND_SOC_NOPM, 1637 0, 0, NULL, 0), 1638 1639 /* REC Mixer */ 1640 SND_SOC_DAPM_MIXER("RECMIX1L", SND_SOC_NOPM, 0, 0, rt5682_rec1_l_mix, 1641 ARRAY_SIZE(rt5682_rec1_l_mix)), 1642 SND_SOC_DAPM_SUPPLY("RECMIX1L Power", RT5682_PWR_ANLG_2, 1643 RT5682_PWR_RM1_L_BIT, 0, NULL, 0), 1644 1645 /* ADCs */ 1646 SND_SOC_DAPM_ADC("ADC1 L", NULL, SND_SOC_NOPM, 0, 0), 1647 SND_SOC_DAPM_ADC("ADC1 R", NULL, SND_SOC_NOPM, 0, 0), 1648 1649 SND_SOC_DAPM_SUPPLY("ADC1 L Power", RT5682_PWR_DIG_1, 1650 RT5682_PWR_ADC_L1_BIT, 0, NULL, 0), 1651 SND_SOC_DAPM_SUPPLY("ADC1 R Power", RT5682_PWR_DIG_1, 1652 RT5682_PWR_ADC_R1_BIT, 0, NULL, 0), 1653 SND_SOC_DAPM_SUPPLY("ADC1 clock", RT5682_CHOP_ADC, 1654 RT5682_CKGEN_ADC1_SFT, 0, NULL, 0), 1655 1656 /* ADC Mux */ 1657 SND_SOC_DAPM_MUX("Stereo1 ADC L1 Mux", SND_SOC_NOPM, 0, 0, 1658 &rt5682_sto1_adc1l_mux), 1659 SND_SOC_DAPM_MUX("Stereo1 ADC R1 Mux", SND_SOC_NOPM, 0, 0, 1660 &rt5682_sto1_adc1r_mux), 1661 SND_SOC_DAPM_MUX("Stereo1 ADC L2 Mux", SND_SOC_NOPM, 0, 0, 1662 &rt5682_sto1_adc2l_mux), 1663 SND_SOC_DAPM_MUX("Stereo1 ADC R2 Mux", SND_SOC_NOPM, 0, 0, 1664 &rt5682_sto1_adc2r_mux), 1665 SND_SOC_DAPM_MUX("Stereo1 ADC L Mux", SND_SOC_NOPM, 0, 0, 1666 &rt5682_sto1_adcl_mux), 1667 SND_SOC_DAPM_MUX("Stereo1 ADC R Mux", SND_SOC_NOPM, 0, 0, 1668 &rt5682_sto1_adcr_mux), 1669 SND_SOC_DAPM_MUX("IF1_ADC Mux", SND_SOC_NOPM, 0, 0, 1670 &rt5682_if1_adc_slot_mux), 1671 1672 /* ADC Mixer */ 1673 SND_SOC_DAPM_SUPPLY("ADC Stereo1 Filter", RT5682_PWR_DIG_2, 1674 RT5682_PWR_ADC_S1F_BIT, 0, set_filter_clk, 1675 SND_SOC_DAPM_PRE_PMU), 1676 SND_SOC_DAPM_MIXER("Stereo1 ADC MIXL", RT5682_STO1_ADC_DIG_VOL, 1677 RT5682_L_MUTE_SFT, 1, rt5682_sto1_adc_l_mix, 1678 ARRAY_SIZE(rt5682_sto1_adc_l_mix)), 1679 SND_SOC_DAPM_MIXER("Stereo1 ADC MIXR", RT5682_STO1_ADC_DIG_VOL, 1680 RT5682_R_MUTE_SFT, 1, rt5682_sto1_adc_r_mix, 1681 ARRAY_SIZE(rt5682_sto1_adc_r_mix)), 1682 SND_SOC_DAPM_SUPPLY("BTN Detection Mode", RT5682_SAR_IL_CMD_1, 1683 14, 1, NULL, 0), 1684 1685 /* ADC PGA */ 1686 SND_SOC_DAPM_PGA("Stereo1 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 1687 1688 /* Digital Interface */ 1689 SND_SOC_DAPM_SUPPLY("I2S1", RT5682_PWR_DIG_1, RT5682_PWR_I2S1_BIT, 1690 0, NULL, 0), 1691 SND_SOC_DAPM_SUPPLY("I2S2", RT5682_PWR_DIG_1, RT5682_PWR_I2S2_BIT, 1692 0, NULL, 0), 1693 SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0), 1694 SND_SOC_DAPM_PGA("IF1 DAC1 L", SND_SOC_NOPM, 0, 0, NULL, 0), 1695 SND_SOC_DAPM_PGA("IF1 DAC1 R", SND_SOC_NOPM, 0, 0, NULL, 0), 1696 1697 /* Digital Interface Select */ 1698 SND_SOC_DAPM_MUX("IF1 01 ADC Swap Mux", SND_SOC_NOPM, 0, 0, 1699 &rt5682_if1_01_adc_swap_mux), 1700 SND_SOC_DAPM_MUX("IF1 23 ADC Swap Mux", SND_SOC_NOPM, 0, 0, 1701 &rt5682_if1_23_adc_swap_mux), 1702 SND_SOC_DAPM_MUX("IF1 45 ADC Swap Mux", SND_SOC_NOPM, 0, 0, 1703 &rt5682_if1_45_adc_swap_mux), 1704 SND_SOC_DAPM_MUX("IF1 67 ADC Swap Mux", SND_SOC_NOPM, 0, 0, 1705 &rt5682_if1_67_adc_swap_mux), 1706 SND_SOC_DAPM_MUX("IF2 ADC Swap Mux", SND_SOC_NOPM, 0, 0, 1707 &rt5682_if2_adc_swap_mux), 1708 1709 SND_SOC_DAPM_MUX("ADCDAT Mux", SND_SOC_NOPM, 0, 0, 1710 &rt5682_adcdat_pin_ctrl), 1711 1712 /* Audio Interface */ 1713 SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, 1714 RT5682_I2S1_SDP, RT5682_SEL_ADCDAT_SFT, 1), 1715 SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, 1716 RT5682_I2S2_SDP, RT5682_I2S2_PIN_CFG_SFT, 1), 1717 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0), 1718 1719 /* Output Side */ 1720 /* DAC mixer before sound effect */ 1721 SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0, 1722 rt5682_dac_l_mix, ARRAY_SIZE(rt5682_dac_l_mix)), 1723 SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0, 1724 rt5682_dac_r_mix, ARRAY_SIZE(rt5682_dac_r_mix)), 1725 1726 /* DAC channel Mux */ 1727 SND_SOC_DAPM_MUX("DAC L1 Source", SND_SOC_NOPM, 0, 0, 1728 &rt5682_alg_dac_l1_mux), 1729 SND_SOC_DAPM_MUX("DAC R1 Source", SND_SOC_NOPM, 0, 0, 1730 &rt5682_alg_dac_r1_mux), 1731 1732 /* DAC Mixer */ 1733 SND_SOC_DAPM_SUPPLY("DAC Stereo1 Filter", RT5682_PWR_DIG_2, 1734 RT5682_PWR_DAC_S1F_BIT, 0, set_filter_clk, 1735 SND_SOC_DAPM_PRE_PMU), 1736 SND_SOC_DAPM_MIXER("Stereo1 DAC MIXL", SND_SOC_NOPM, 0, 0, 1737 rt5682_sto1_dac_l_mix, ARRAY_SIZE(rt5682_sto1_dac_l_mix)), 1738 SND_SOC_DAPM_MIXER("Stereo1 DAC MIXR", SND_SOC_NOPM, 0, 0, 1739 rt5682_sto1_dac_r_mix, ARRAY_SIZE(rt5682_sto1_dac_r_mix)), 1740 1741 /* DACs */ 1742 SND_SOC_DAPM_DAC("DAC L1", NULL, RT5682_PWR_DIG_1, 1743 RT5682_PWR_DAC_L1_BIT, 0), 1744 SND_SOC_DAPM_DAC("DAC R1", NULL, RT5682_PWR_DIG_1, 1745 RT5682_PWR_DAC_R1_BIT, 0), 1746 SND_SOC_DAPM_SUPPLY_S("DAC 1 Clock", 3, RT5682_CHOP_DAC, 1747 RT5682_CKGEN_DAC1_SFT, 0, NULL, 0), 1748 1749 /* HPO */ 1750 SND_SOC_DAPM_PGA_S("HP Amp", 1, SND_SOC_NOPM, 0, 0, rt5682_hp_event, 1751 SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_PRE_PMU), 1752 1753 SND_SOC_DAPM_SUPPLY("HP Amp L", RT5682_PWR_ANLG_1, 1754 RT5682_PWR_HA_L_BIT, 0, NULL, 0), 1755 SND_SOC_DAPM_SUPPLY("HP Amp R", RT5682_PWR_ANLG_1, 1756 RT5682_PWR_HA_R_BIT, 0, NULL, 0), 1757 SND_SOC_DAPM_SUPPLY_S("Charge Pump", 1, RT5682_DEPOP_1, 1758 RT5682_PUMP_EN_SFT, 0, rt5682_charge_pump_event, 1759 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 1760 SND_SOC_DAPM_SUPPLY_S("Capless", 2, RT5682_DEPOP_1, 1761 RT5682_CAPLESS_EN_SFT, 0, NULL, 0), 1762 1763 SND_SOC_DAPM_SWITCH("HPOL Playback", SND_SOC_NOPM, 0, 0, 1764 &hpol_switch), 1765 SND_SOC_DAPM_SWITCH("HPOR Playback", SND_SOC_NOPM, 0, 0, 1766 &hpor_switch), 1767 1768 /* CLK DET */ 1769 SND_SOC_DAPM_SUPPLY("CLKDET SYS", RT5682_CLK_DET, 1770 RT5682_SYS_CLK_DET_SFT, 0, NULL, 0), 1771 SND_SOC_DAPM_SUPPLY("CLKDET PLL1", RT5682_CLK_DET, 1772 RT5682_PLL1_CLK_DET_SFT, 0, NULL, 0), 1773 SND_SOC_DAPM_SUPPLY("CLKDET PLL2", RT5682_CLK_DET, 1774 RT5682_PLL2_CLK_DET_SFT, 0, NULL, 0), 1775 SND_SOC_DAPM_SUPPLY("CLKDET", RT5682_CLK_DET, 1776 RT5682_POW_CLK_DET_SFT, 0, NULL, 0), 1777 1778 /* Output Lines */ 1779 SND_SOC_DAPM_OUTPUT("HPOL"), 1780 SND_SOC_DAPM_OUTPUT("HPOR"), 1781 1782 }; 1783 1784 static const struct snd_soc_dapm_route rt5682_dapm_routes[] = { 1785 /*PLL*/ 1786 {"ADC Stereo1 Filter", NULL, "PLL1", is_sys_clk_from_pll1}, 1787 {"DAC Stereo1 Filter", NULL, "PLL1", is_sys_clk_from_pll1}, 1788 1789 /*ASRC*/ 1790 {"ADC Stereo1 Filter", NULL, "ADC STO1 ASRC", is_using_asrc}, 1791 {"DAC Stereo1 Filter", NULL, "DAC STO1 ASRC", is_using_asrc}, 1792 {"ADC STO1 ASRC", NULL, "AD ASRC"}, 1793 {"ADC STO1 ASRC", NULL, "DA ASRC"}, 1794 {"ADC STO1 ASRC", NULL, "CLKDET"}, 1795 {"DAC STO1 ASRC", NULL, "AD ASRC"}, 1796 {"DAC STO1 ASRC", NULL, "DA ASRC"}, 1797 {"DAC STO1 ASRC", NULL, "CLKDET"}, 1798 1799 /*Vref*/ 1800 {"MICBIAS1", NULL, "Vref1"}, 1801 {"MICBIAS2", NULL, "Vref1"}, 1802 1803 {"CLKDET SYS", NULL, "CLKDET"}, 1804 1805 {"IN1P", NULL, "LDO2"}, 1806 1807 {"BST1 CBJ", NULL, "IN1P"}, 1808 1809 {"RECMIX1L", "CBJ Switch", "BST1 CBJ"}, 1810 {"RECMIX1L", NULL, "RECMIX1L Power"}, 1811 1812 {"ADC1 L", NULL, "RECMIX1L"}, 1813 {"ADC1 L", NULL, "ADC1 L Power"}, 1814 {"ADC1 L", NULL, "ADC1 clock"}, 1815 1816 {"DMIC L1", NULL, "DMIC CLK"}, 1817 {"DMIC L1", NULL, "DMIC1 Power"}, 1818 {"DMIC R1", NULL, "DMIC CLK"}, 1819 {"DMIC R1", NULL, "DMIC1 Power"}, 1820 {"DMIC CLK", NULL, "DMIC ASRC"}, 1821 1822 {"Stereo1 ADC L Mux", "ADC1 L", "ADC1 L"}, 1823 {"Stereo1 ADC L Mux", "ADC1 R", "ADC1 R"}, 1824 {"Stereo1 ADC R Mux", "ADC1 L", "ADC1 L"}, 1825 {"Stereo1 ADC R Mux", "ADC1 R", "ADC1 R"}, 1826 1827 {"Stereo1 ADC L1 Mux", "ADC", "Stereo1 ADC L Mux"}, 1828 {"Stereo1 ADC L1 Mux", "DAC MIX", "Stereo1 DAC MIXL"}, 1829 {"Stereo1 ADC L2 Mux", "DMIC", "DMIC L1"}, 1830 {"Stereo1 ADC L2 Mux", "DAC MIX", "Stereo1 DAC MIXL"}, 1831 1832 {"Stereo1 ADC R1 Mux", "ADC", "Stereo1 ADC R Mux"}, 1833 {"Stereo1 ADC R1 Mux", "DAC MIX", "Stereo1 DAC MIXR"}, 1834 {"Stereo1 ADC R2 Mux", "DMIC", "DMIC R1"}, 1835 {"Stereo1 ADC R2 Mux", "DAC MIX", "Stereo1 DAC MIXR"}, 1836 1837 {"Stereo1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC L1 Mux"}, 1838 {"Stereo1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC L2 Mux"}, 1839 {"Stereo1 ADC MIXL", NULL, "ADC Stereo1 Filter"}, 1840 1841 {"Stereo1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC R1 Mux"}, 1842 {"Stereo1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC R2 Mux"}, 1843 {"Stereo1 ADC MIXR", NULL, "ADC Stereo1 Filter"}, 1844 1845 {"ADC Stereo1 Filter", NULL, "BTN Detection Mode"}, 1846 1847 {"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXL"}, 1848 {"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXR"}, 1849 1850 {"IF1 01 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"}, 1851 {"IF1 01 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"}, 1852 {"IF1 01 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"}, 1853 {"IF1 01 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"}, 1854 {"IF1 23 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"}, 1855 {"IF1 23 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"}, 1856 {"IF1 23 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"}, 1857 {"IF1 23 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"}, 1858 {"IF1 45 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"}, 1859 {"IF1 45 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"}, 1860 {"IF1 45 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"}, 1861 {"IF1 45 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"}, 1862 {"IF1 67 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"}, 1863 {"IF1 67 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"}, 1864 {"IF1 67 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"}, 1865 {"IF1 67 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"}, 1866 1867 {"IF1_ADC Mux", "Slot 0", "IF1 01 ADC Swap Mux"}, 1868 {"IF1_ADC Mux", "Slot 2", "IF1 23 ADC Swap Mux"}, 1869 {"IF1_ADC Mux", "Slot 4", "IF1 45 ADC Swap Mux"}, 1870 {"IF1_ADC Mux", "Slot 6", "IF1 67 ADC Swap Mux"}, 1871 {"IF1_ADC Mux", NULL, "I2S1"}, 1872 {"ADCDAT Mux", "ADCDAT1", "IF1_ADC Mux"}, 1873 {"AIF1TX", NULL, "ADCDAT Mux"}, 1874 {"IF2 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"}, 1875 {"IF2 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"}, 1876 {"IF2 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"}, 1877 {"IF2 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"}, 1878 {"ADCDAT Mux", "ADCDAT2", "IF2 ADC Swap Mux"}, 1879 {"AIF2TX", NULL, "ADCDAT Mux"}, 1880 1881 {"IF1 DAC1 L", NULL, "AIF1RX"}, 1882 {"IF1 DAC1 L", NULL, "I2S1"}, 1883 {"IF1 DAC1 L", NULL, "DAC Stereo1 Filter"}, 1884 {"IF1 DAC1 R", NULL, "AIF1RX"}, 1885 {"IF1 DAC1 R", NULL, "I2S1"}, 1886 {"IF1 DAC1 R", NULL, "DAC Stereo1 Filter"}, 1887 1888 {"DAC1 MIXL", "Stereo ADC Switch", "Stereo1 ADC MIXL"}, 1889 {"DAC1 MIXL", "DAC1 Switch", "IF1 DAC1 L"}, 1890 {"DAC1 MIXR", "Stereo ADC Switch", "Stereo1 ADC MIXR"}, 1891 {"DAC1 MIXR", "DAC1 Switch", "IF1 DAC1 R"}, 1892 1893 {"Stereo1 DAC MIXL", "DAC L1 Switch", "DAC1 MIXL"}, 1894 {"Stereo1 DAC MIXL", "DAC R1 Switch", "DAC1 MIXR"}, 1895 1896 {"Stereo1 DAC MIXR", "DAC R1 Switch", "DAC1 MIXR"}, 1897 {"Stereo1 DAC MIXR", "DAC L1 Switch", "DAC1 MIXL"}, 1898 1899 {"DAC L1 Source", "DAC1", "DAC1 MIXL"}, 1900 {"DAC L1 Source", "Stereo1 DAC Mixer", "Stereo1 DAC MIXL"}, 1901 {"DAC R1 Source", "DAC1", "DAC1 MIXR"}, 1902 {"DAC R1 Source", "Stereo1 DAC Mixer", "Stereo1 DAC MIXR"}, 1903 1904 {"DAC L1", NULL, "DAC L1 Source"}, 1905 {"DAC R1", NULL, "DAC R1 Source"}, 1906 1907 {"DAC L1", NULL, "DAC 1 Clock"}, 1908 {"DAC R1", NULL, "DAC 1 Clock"}, 1909 1910 {"HP Amp", NULL, "DAC L1"}, 1911 {"HP Amp", NULL, "DAC R1"}, 1912 {"HP Amp", NULL, "HP Amp L"}, 1913 {"HP Amp", NULL, "HP Amp R"}, 1914 {"HP Amp", NULL, "Capless"}, 1915 {"HP Amp", NULL, "Charge Pump"}, 1916 {"HP Amp", NULL, "CLKDET SYS"}, 1917 {"HP Amp", NULL, "Vref1"}, 1918 {"HPOL Playback", "Switch", "HP Amp"}, 1919 {"HPOR Playback", "Switch", "HP Amp"}, 1920 {"HPOL", NULL, "HPOL Playback"}, 1921 {"HPOR", NULL, "HPOR Playback"}, 1922 }; 1923 1924 static int rt5682_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask, 1925 unsigned int rx_mask, int slots, int slot_width) 1926 { 1927 struct snd_soc_component *component = dai->component; 1928 unsigned int cl, val = 0; 1929 1930 if (tx_mask || rx_mask) 1931 snd_soc_component_update_bits(component, RT5682_TDM_ADDA_CTRL_2, 1932 RT5682_TDM_EN, RT5682_TDM_EN); 1933 else 1934 snd_soc_component_update_bits(component, RT5682_TDM_ADDA_CTRL_2, 1935 RT5682_TDM_EN, 0); 1936 1937 switch (slots) { 1938 case 4: 1939 val |= RT5682_TDM_TX_CH_4; 1940 val |= RT5682_TDM_RX_CH_4; 1941 break; 1942 case 6: 1943 val |= RT5682_TDM_TX_CH_6; 1944 val |= RT5682_TDM_RX_CH_6; 1945 break; 1946 case 8: 1947 val |= RT5682_TDM_TX_CH_8; 1948 val |= RT5682_TDM_RX_CH_8; 1949 break; 1950 case 2: 1951 break; 1952 default: 1953 return -EINVAL; 1954 } 1955 1956 snd_soc_component_update_bits(component, RT5682_TDM_CTRL, 1957 RT5682_TDM_TX_CH_MASK | RT5682_TDM_RX_CH_MASK, val); 1958 1959 switch (slot_width) { 1960 case 8: 1961 if (tx_mask || rx_mask) 1962 return -EINVAL; 1963 cl = RT5682_I2S1_TX_CHL_8 | RT5682_I2S1_RX_CHL_8; 1964 break; 1965 case 16: 1966 val = RT5682_TDM_CL_16; 1967 cl = RT5682_I2S1_TX_CHL_16 | RT5682_I2S1_RX_CHL_16; 1968 break; 1969 case 20: 1970 val = RT5682_TDM_CL_20; 1971 cl = RT5682_I2S1_TX_CHL_20 | RT5682_I2S1_RX_CHL_20; 1972 break; 1973 case 24: 1974 val = RT5682_TDM_CL_24; 1975 cl = RT5682_I2S1_TX_CHL_24 | RT5682_I2S1_RX_CHL_24; 1976 break; 1977 case 32: 1978 val = RT5682_TDM_CL_32; 1979 cl = RT5682_I2S1_TX_CHL_32 | RT5682_I2S1_RX_CHL_32; 1980 break; 1981 default: 1982 return -EINVAL; 1983 } 1984 1985 snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL, 1986 RT5682_TDM_CL_MASK, val); 1987 snd_soc_component_update_bits(component, RT5682_I2S1_SDP, 1988 RT5682_I2S1_TX_CHL_MASK | RT5682_I2S1_RX_CHL_MASK, cl); 1989 1990 return 0; 1991 } 1992 1993 1994 static int rt5682_hw_params(struct snd_pcm_substream *substream, 1995 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) 1996 { 1997 struct snd_soc_component *component = dai->component; 1998 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 1999 unsigned int len_1 = 0, len_2 = 0; 2000 int pre_div, frame_size; 2001 2002 rt5682->lrck[dai->id] = params_rate(params); 2003 pre_div = rl6231_get_clk_info(rt5682->sysclk, rt5682->lrck[dai->id]); 2004 2005 frame_size = snd_soc_params_to_frame_size(params); 2006 if (frame_size < 0) { 2007 dev_err(component->dev, "Unsupported frame size: %d\n", 2008 frame_size); 2009 return -EINVAL; 2010 } 2011 2012 dev_dbg(dai->dev, "lrck is %dHz and pre_div is %d for iis %d\n", 2013 rt5682->lrck[dai->id], pre_div, dai->id); 2014 2015 switch (params_width(params)) { 2016 case 16: 2017 break; 2018 case 20: 2019 len_1 |= RT5682_I2S1_DL_20; 2020 len_2 |= RT5682_I2S2_DL_20; 2021 break; 2022 case 24: 2023 len_1 |= RT5682_I2S1_DL_24; 2024 len_2 |= RT5682_I2S2_DL_24; 2025 break; 2026 case 32: 2027 len_1 |= RT5682_I2S1_DL_32; 2028 len_2 |= RT5682_I2S2_DL_24; 2029 break; 2030 case 8: 2031 len_1 |= RT5682_I2S2_DL_8; 2032 len_2 |= RT5682_I2S2_DL_8; 2033 break; 2034 default: 2035 return -EINVAL; 2036 } 2037 2038 switch (dai->id) { 2039 case RT5682_AIF1: 2040 snd_soc_component_update_bits(component, RT5682_I2S1_SDP, 2041 RT5682_I2S1_DL_MASK, len_1); 2042 if (rt5682->master[RT5682_AIF1]) { 2043 snd_soc_component_update_bits(component, 2044 RT5682_ADDA_CLK_1, RT5682_I2S_M_DIV_MASK, 2045 pre_div << RT5682_I2S_M_DIV_SFT); 2046 } 2047 if (params_channels(params) == 1) /* mono mode */ 2048 snd_soc_component_update_bits(component, 2049 RT5682_I2S1_SDP, RT5682_I2S1_MONO_MASK, 2050 RT5682_I2S1_MONO_EN); 2051 else 2052 snd_soc_component_update_bits(component, 2053 RT5682_I2S1_SDP, RT5682_I2S1_MONO_MASK, 2054 RT5682_I2S1_MONO_DIS); 2055 break; 2056 case RT5682_AIF2: 2057 snd_soc_component_update_bits(component, RT5682_I2S2_SDP, 2058 RT5682_I2S2_DL_MASK, len_2); 2059 if (rt5682->master[RT5682_AIF2]) { 2060 snd_soc_component_update_bits(component, 2061 RT5682_I2S_M_CLK_CTRL_1, RT5682_I2S2_M_PD_MASK, 2062 pre_div << RT5682_I2S2_M_PD_SFT); 2063 } 2064 if (params_channels(params) == 1) /* mono mode */ 2065 snd_soc_component_update_bits(component, 2066 RT5682_I2S2_SDP, RT5682_I2S2_MONO_MASK, 2067 RT5682_I2S2_MONO_EN); 2068 else 2069 snd_soc_component_update_bits(component, 2070 RT5682_I2S2_SDP, RT5682_I2S2_MONO_MASK, 2071 RT5682_I2S2_MONO_DIS); 2072 break; 2073 default: 2074 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id); 2075 return -EINVAL; 2076 } 2077 2078 return 0; 2079 } 2080 2081 static int rt5682_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) 2082 { 2083 struct snd_soc_component *component = dai->component; 2084 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 2085 unsigned int reg_val = 0, tdm_ctrl = 0; 2086 2087 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 2088 case SND_SOC_DAIFMT_CBM_CFM: 2089 rt5682->master[dai->id] = 1; 2090 break; 2091 case SND_SOC_DAIFMT_CBS_CFS: 2092 rt5682->master[dai->id] = 0; 2093 break; 2094 default: 2095 return -EINVAL; 2096 } 2097 2098 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 2099 case SND_SOC_DAIFMT_NB_NF: 2100 break; 2101 case SND_SOC_DAIFMT_IB_NF: 2102 reg_val |= RT5682_I2S_BP_INV; 2103 tdm_ctrl |= RT5682_TDM_S_BP_INV; 2104 break; 2105 case SND_SOC_DAIFMT_NB_IF: 2106 if (dai->id == RT5682_AIF1) 2107 tdm_ctrl |= RT5682_TDM_S_LP_INV | RT5682_TDM_M_BP_INV; 2108 else 2109 return -EINVAL; 2110 break; 2111 case SND_SOC_DAIFMT_IB_IF: 2112 if (dai->id == RT5682_AIF1) 2113 tdm_ctrl |= RT5682_TDM_S_BP_INV | RT5682_TDM_S_LP_INV | 2114 RT5682_TDM_M_BP_INV | RT5682_TDM_M_LP_INV; 2115 else 2116 return -EINVAL; 2117 break; 2118 default: 2119 return -EINVAL; 2120 } 2121 2122 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 2123 case SND_SOC_DAIFMT_I2S: 2124 break; 2125 case SND_SOC_DAIFMT_LEFT_J: 2126 reg_val |= RT5682_I2S_DF_LEFT; 2127 tdm_ctrl |= RT5682_TDM_DF_LEFT; 2128 break; 2129 case SND_SOC_DAIFMT_DSP_A: 2130 reg_val |= RT5682_I2S_DF_PCM_A; 2131 tdm_ctrl |= RT5682_TDM_DF_PCM_A; 2132 break; 2133 case SND_SOC_DAIFMT_DSP_B: 2134 reg_val |= RT5682_I2S_DF_PCM_B; 2135 tdm_ctrl |= RT5682_TDM_DF_PCM_B; 2136 break; 2137 default: 2138 return -EINVAL; 2139 } 2140 2141 switch (dai->id) { 2142 case RT5682_AIF1: 2143 snd_soc_component_update_bits(component, RT5682_I2S1_SDP, 2144 RT5682_I2S_DF_MASK, reg_val); 2145 snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL, 2146 RT5682_TDM_MS_MASK | RT5682_TDM_S_BP_MASK | 2147 RT5682_TDM_DF_MASK | RT5682_TDM_M_BP_MASK | 2148 RT5682_TDM_M_LP_MASK | RT5682_TDM_S_LP_MASK, 2149 tdm_ctrl | rt5682->master[dai->id]); 2150 break; 2151 case RT5682_AIF2: 2152 if (rt5682->master[dai->id] == 0) 2153 reg_val |= RT5682_I2S2_MS_S; 2154 snd_soc_component_update_bits(component, RT5682_I2S2_SDP, 2155 RT5682_I2S2_MS_MASK | RT5682_I2S_BP_MASK | 2156 RT5682_I2S_DF_MASK, reg_val); 2157 break; 2158 default: 2159 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id); 2160 return -EINVAL; 2161 } 2162 return 0; 2163 } 2164 2165 static int rt5682_set_component_sysclk(struct snd_soc_component *component, 2166 int clk_id, int source, unsigned int freq, int dir) 2167 { 2168 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 2169 unsigned int reg_val = 0, src = 0; 2170 2171 if (freq == rt5682->sysclk && clk_id == rt5682->sysclk_src) 2172 return 0; 2173 2174 switch (clk_id) { 2175 case RT5682_SCLK_S_MCLK: 2176 reg_val |= RT5682_SCLK_SRC_MCLK; 2177 src = RT5682_CLK_SRC_MCLK; 2178 break; 2179 case RT5682_SCLK_S_PLL1: 2180 reg_val |= RT5682_SCLK_SRC_PLL1; 2181 src = RT5682_CLK_SRC_PLL1; 2182 break; 2183 case RT5682_SCLK_S_PLL2: 2184 reg_val |= RT5682_SCLK_SRC_PLL2; 2185 src = RT5682_CLK_SRC_PLL2; 2186 break; 2187 case RT5682_SCLK_S_RCCLK: 2188 reg_val |= RT5682_SCLK_SRC_RCCLK; 2189 src = RT5682_CLK_SRC_RCCLK; 2190 break; 2191 default: 2192 dev_err(component->dev, "Invalid clock id (%d)\n", clk_id); 2193 return -EINVAL; 2194 } 2195 snd_soc_component_update_bits(component, RT5682_GLB_CLK, 2196 RT5682_SCLK_SRC_MASK, reg_val); 2197 2198 if (rt5682->master[RT5682_AIF2]) { 2199 snd_soc_component_update_bits(component, 2200 RT5682_I2S_M_CLK_CTRL_1, RT5682_I2S2_SRC_MASK, 2201 src << RT5682_I2S2_SRC_SFT); 2202 } 2203 2204 rt5682->sysclk = freq; 2205 rt5682->sysclk_src = clk_id; 2206 2207 dev_dbg(component->dev, "Sysclk is %dHz and clock id is %d\n", 2208 freq, clk_id); 2209 2210 return 0; 2211 } 2212 2213 static int rt5682_set_component_pll(struct snd_soc_component *component, 2214 int pll_id, int source, unsigned int freq_in, 2215 unsigned int freq_out) 2216 { 2217 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 2218 struct rl6231_pll_code pll_code; 2219 int ret; 2220 2221 if (source == rt5682->pll_src && freq_in == rt5682->pll_in && 2222 freq_out == rt5682->pll_out) 2223 return 0; 2224 2225 if (!freq_in || !freq_out) { 2226 dev_dbg(component->dev, "PLL disabled\n"); 2227 2228 rt5682->pll_in = 0; 2229 rt5682->pll_out = 0; 2230 snd_soc_component_update_bits(component, RT5682_GLB_CLK, 2231 RT5682_SCLK_SRC_MASK, RT5682_SCLK_SRC_MCLK); 2232 return 0; 2233 } 2234 2235 switch (source) { 2236 case RT5682_PLL1_S_MCLK: 2237 snd_soc_component_update_bits(component, RT5682_GLB_CLK, 2238 RT5682_PLL1_SRC_MASK, RT5682_PLL1_SRC_MCLK); 2239 break; 2240 case RT5682_PLL1_S_BCLK1: 2241 snd_soc_component_update_bits(component, RT5682_GLB_CLK, 2242 RT5682_PLL1_SRC_MASK, RT5682_PLL1_SRC_BCLK1); 2243 break; 2244 default: 2245 dev_err(component->dev, "Unknown PLL Source %d\n", source); 2246 return -EINVAL; 2247 } 2248 2249 ret = rl6231_pll_calc(freq_in, freq_out, &pll_code); 2250 if (ret < 0) { 2251 dev_err(component->dev, "Unsupport input clock %d\n", freq_in); 2252 return ret; 2253 } 2254 2255 dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n", 2256 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code), 2257 pll_code.n_code, pll_code.k_code); 2258 2259 snd_soc_component_write(component, RT5682_PLL_CTRL_1, 2260 pll_code.n_code << RT5682_PLL_N_SFT | pll_code.k_code); 2261 snd_soc_component_write(component, RT5682_PLL_CTRL_2, 2262 (pll_code.m_bp ? 0 : pll_code.m_code) << RT5682_PLL_M_SFT | 2263 pll_code.m_bp << RT5682_PLL_M_BP_SFT | RT5682_PLL_RST); 2264 2265 rt5682->pll_in = freq_in; 2266 rt5682->pll_out = freq_out; 2267 rt5682->pll_src = source; 2268 2269 return 0; 2270 } 2271 2272 static int rt5682_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio) 2273 { 2274 struct snd_soc_component *component = dai->component; 2275 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 2276 2277 rt5682->bclk[dai->id] = ratio; 2278 2279 switch (ratio) { 2280 case 64: 2281 snd_soc_component_update_bits(component, RT5682_ADDA_CLK_2, 2282 RT5682_I2S2_BCLK_MS2_MASK, 2283 RT5682_I2S2_BCLK_MS2_64); 2284 break; 2285 case 32: 2286 snd_soc_component_update_bits(component, RT5682_ADDA_CLK_2, 2287 RT5682_I2S2_BCLK_MS2_MASK, 2288 RT5682_I2S2_BCLK_MS2_32); 2289 break; 2290 default: 2291 dev_err(dai->dev, "Invalid bclk ratio %d\n", ratio); 2292 return -EINVAL; 2293 } 2294 2295 return 0; 2296 } 2297 2298 static int rt5682_set_bias_level(struct snd_soc_component *component, 2299 enum snd_soc_bias_level level) 2300 { 2301 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 2302 2303 switch (level) { 2304 case SND_SOC_BIAS_PREPARE: 2305 regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_1, 2306 RT5682_PWR_BG, RT5682_PWR_BG); 2307 regmap_update_bits(rt5682->regmap, RT5682_PWR_DIG_1, 2308 RT5682_DIG_GATE_CTRL | RT5682_PWR_LDO, 2309 RT5682_DIG_GATE_CTRL | RT5682_PWR_LDO); 2310 break; 2311 2312 case SND_SOC_BIAS_STANDBY: 2313 regmap_update_bits(rt5682->regmap, RT5682_PWR_DIG_1, 2314 RT5682_DIG_GATE_CTRL, RT5682_DIG_GATE_CTRL); 2315 break; 2316 case SND_SOC_BIAS_OFF: 2317 regmap_update_bits(rt5682->regmap, RT5682_PWR_DIG_1, 2318 RT5682_DIG_GATE_CTRL | RT5682_PWR_LDO, 0); 2319 regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_1, 2320 RT5682_PWR_BG, 0); 2321 break; 2322 2323 default: 2324 break; 2325 } 2326 2327 return 0; 2328 } 2329 2330 static int rt5682_probe(struct snd_soc_component *component) 2331 { 2332 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 2333 2334 rt5682->component = component; 2335 2336 return 0; 2337 } 2338 2339 static void rt5682_remove(struct snd_soc_component *component) 2340 { 2341 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 2342 2343 rt5682_reset(rt5682->regmap); 2344 } 2345 2346 #ifdef CONFIG_PM 2347 static int rt5682_suspend(struct snd_soc_component *component) 2348 { 2349 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 2350 2351 regcache_cache_only(rt5682->regmap, true); 2352 regcache_mark_dirty(rt5682->regmap); 2353 return 0; 2354 } 2355 2356 static int rt5682_resume(struct snd_soc_component *component) 2357 { 2358 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 2359 2360 regcache_cache_only(rt5682->regmap, false); 2361 regcache_sync(rt5682->regmap); 2362 2363 rt5682_irq(0, rt5682); 2364 2365 return 0; 2366 } 2367 #else 2368 #define rt5682_suspend NULL 2369 #define rt5682_resume NULL 2370 #endif 2371 2372 #define RT5682_STEREO_RATES SNDRV_PCM_RATE_8000_192000 2373 #define RT5682_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ 2374 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8) 2375 2376 static const struct snd_soc_dai_ops rt5682_aif1_dai_ops = { 2377 .hw_params = rt5682_hw_params, 2378 .set_fmt = rt5682_set_dai_fmt, 2379 .set_tdm_slot = rt5682_set_tdm_slot, 2380 }; 2381 2382 static const struct snd_soc_dai_ops rt5682_aif2_dai_ops = { 2383 .hw_params = rt5682_hw_params, 2384 .set_fmt = rt5682_set_dai_fmt, 2385 .set_bclk_ratio = rt5682_set_bclk_ratio, 2386 }; 2387 2388 static struct snd_soc_dai_driver rt5682_dai[] = { 2389 { 2390 .name = "rt5682-aif1", 2391 .id = RT5682_AIF1, 2392 .playback = { 2393 .stream_name = "AIF1 Playback", 2394 .channels_min = 1, 2395 .channels_max = 2, 2396 .rates = RT5682_STEREO_RATES, 2397 .formats = RT5682_FORMATS, 2398 }, 2399 .capture = { 2400 .stream_name = "AIF1 Capture", 2401 .channels_min = 1, 2402 .channels_max = 2, 2403 .rates = RT5682_STEREO_RATES, 2404 .formats = RT5682_FORMATS, 2405 }, 2406 .ops = &rt5682_aif1_dai_ops, 2407 }, 2408 { 2409 .name = "rt5682-aif2", 2410 .id = RT5682_AIF2, 2411 .capture = { 2412 .stream_name = "AIF2 Capture", 2413 .channels_min = 1, 2414 .channels_max = 2, 2415 .rates = RT5682_STEREO_RATES, 2416 .formats = RT5682_FORMATS, 2417 }, 2418 .ops = &rt5682_aif2_dai_ops, 2419 }, 2420 }; 2421 2422 static const struct snd_soc_component_driver soc_component_dev_rt5682 = { 2423 .probe = rt5682_probe, 2424 .remove = rt5682_remove, 2425 .suspend = rt5682_suspend, 2426 .resume = rt5682_resume, 2427 .set_bias_level = rt5682_set_bias_level, 2428 .controls = rt5682_snd_controls, 2429 .num_controls = ARRAY_SIZE(rt5682_snd_controls), 2430 .dapm_widgets = rt5682_dapm_widgets, 2431 .num_dapm_widgets = ARRAY_SIZE(rt5682_dapm_widgets), 2432 .dapm_routes = rt5682_dapm_routes, 2433 .num_dapm_routes = ARRAY_SIZE(rt5682_dapm_routes), 2434 .set_sysclk = rt5682_set_component_sysclk, 2435 .set_pll = rt5682_set_component_pll, 2436 .set_jack = rt5682_set_jack_detect, 2437 .use_pmdown_time = 1, 2438 .endianness = 1, 2439 .non_legacy_dai_naming = 1, 2440 }; 2441 2442 static const struct regmap_config rt5682_regmap = { 2443 .reg_bits = 16, 2444 .val_bits = 16, 2445 .max_register = RT5682_I2C_MODE, 2446 .volatile_reg = rt5682_volatile_register, 2447 .readable_reg = rt5682_readable_register, 2448 .cache_type = REGCACHE_RBTREE, 2449 .reg_defaults = rt5682_reg, 2450 .num_reg_defaults = ARRAY_SIZE(rt5682_reg), 2451 .use_single_read = true, 2452 .use_single_write = true, 2453 }; 2454 2455 static const struct i2c_device_id rt5682_i2c_id[] = { 2456 {"rt5682", 0}, 2457 {} 2458 }; 2459 MODULE_DEVICE_TABLE(i2c, rt5682_i2c_id); 2460 2461 static int rt5682_parse_dt(struct rt5682_priv *rt5682, struct device *dev) 2462 { 2463 2464 device_property_read_u32(dev, "realtek,dmic1-data-pin", 2465 &rt5682->pdata.dmic1_data_pin); 2466 device_property_read_u32(dev, "realtek,dmic1-clk-pin", 2467 &rt5682->pdata.dmic1_clk_pin); 2468 device_property_read_u32(dev, "realtek,jd-src", 2469 &rt5682->pdata.jd_src); 2470 2471 rt5682->pdata.ldo1_en = of_get_named_gpio(dev->of_node, 2472 "realtek,ldo1-en-gpios", 0); 2473 2474 return 0; 2475 } 2476 2477 static void rt5682_calibrate(struct rt5682_priv *rt5682) 2478 { 2479 int value, count; 2480 2481 mutex_lock(&rt5682->calibrate_mutex); 2482 2483 rt5682_reset(rt5682->regmap); 2484 regmap_write(rt5682->regmap, RT5682_PWR_ANLG_1, 0xa2af); 2485 usleep_range(15000, 20000); 2486 regmap_write(rt5682->regmap, RT5682_PWR_ANLG_1, 0xf2af); 2487 regmap_write(rt5682->regmap, RT5682_MICBIAS_2, 0x0300); 2488 regmap_write(rt5682->regmap, RT5682_GLB_CLK, 0x8000); 2489 regmap_write(rt5682->regmap, RT5682_PWR_DIG_1, 0x0100); 2490 regmap_write(rt5682->regmap, RT5682_HP_IMP_SENS_CTRL_19, 0x3800); 2491 regmap_write(rt5682->regmap, RT5682_CHOP_DAC, 0x3000); 2492 regmap_write(rt5682->regmap, RT5682_CALIB_ADC_CTRL, 0x7005); 2493 regmap_write(rt5682->regmap, RT5682_STO1_ADC_MIXER, 0x686c); 2494 regmap_write(rt5682->regmap, RT5682_CAL_REC, 0x0d0d); 2495 regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_2, 0x0321); 2496 regmap_write(rt5682->regmap, RT5682_HP_LOGIC_CTRL_2, 0x0004); 2497 regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_1, 0x7c00); 2498 regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_3, 0x06a1); 2499 regmap_write(rt5682->regmap, RT5682_A_DAC1_MUX, 0x0311); 2500 regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_1, 0x7c00); 2501 2502 regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_1, 0xfc00); 2503 2504 for (count = 0; count < 60; count++) { 2505 regmap_read(rt5682->regmap, RT5682_HP_CALIB_STA_1, &value); 2506 if (!(value & 0x8000)) 2507 break; 2508 2509 usleep_range(10000, 10005); 2510 } 2511 2512 if (count >= 60) 2513 pr_err("HP Calibration Failure\n"); 2514 2515 /* restore settings */ 2516 regmap_write(rt5682->regmap, RT5682_PWR_ANLG_1, 0x02af); 2517 regmap_write(rt5682->regmap, RT5682_MICBIAS_2, 0x0080); 2518 regmap_write(rt5682->regmap, RT5682_GLB_CLK, 0x0000); 2519 regmap_write(rt5682->regmap, RT5682_PWR_DIG_1, 0x0000); 2520 regmap_write(rt5682->regmap, RT5682_CHOP_DAC, 0x2000); 2521 regmap_write(rt5682->regmap, RT5682_CALIB_ADC_CTRL, 0x2005); 2522 regmap_write(rt5682->regmap, RT5682_STO1_ADC_MIXER, 0xc0c4); 2523 2524 mutex_unlock(&rt5682->calibrate_mutex); 2525 2526 } 2527 2528 static int rt5682_i2c_probe(struct i2c_client *i2c, 2529 const struct i2c_device_id *id) 2530 { 2531 struct rt5682_platform_data *pdata = dev_get_platdata(&i2c->dev); 2532 struct rt5682_priv *rt5682; 2533 int i, ret; 2534 unsigned int val; 2535 2536 rt5682 = devm_kzalloc(&i2c->dev, sizeof(struct rt5682_priv), 2537 GFP_KERNEL); 2538 2539 if (rt5682 == NULL) 2540 return -ENOMEM; 2541 2542 i2c_set_clientdata(i2c, rt5682); 2543 2544 rt5682->pdata = i2s_default_platform_data; 2545 2546 if (pdata) 2547 rt5682->pdata = *pdata; 2548 else 2549 rt5682_parse_dt(rt5682, &i2c->dev); 2550 2551 rt5682->regmap = devm_regmap_init_i2c(i2c, &rt5682_regmap); 2552 if (IS_ERR(rt5682->regmap)) { 2553 ret = PTR_ERR(rt5682->regmap); 2554 dev_err(&i2c->dev, "Failed to allocate register map: %d\n", 2555 ret); 2556 return ret; 2557 } 2558 2559 for (i = 0; i < ARRAY_SIZE(rt5682->supplies); i++) 2560 rt5682->supplies[i].supply = rt5682_supply_names[i]; 2561 2562 ret = devm_regulator_bulk_get(&i2c->dev, ARRAY_SIZE(rt5682->supplies), 2563 rt5682->supplies); 2564 if (ret != 0) { 2565 dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret); 2566 return ret; 2567 } 2568 2569 ret = regulator_bulk_enable(ARRAY_SIZE(rt5682->supplies), 2570 rt5682->supplies); 2571 if (ret != 0) { 2572 dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret); 2573 return ret; 2574 } 2575 2576 if (gpio_is_valid(rt5682->pdata.ldo1_en)) { 2577 if (devm_gpio_request_one(&i2c->dev, rt5682->pdata.ldo1_en, 2578 GPIOF_OUT_INIT_HIGH, "rt5682")) 2579 dev_err(&i2c->dev, "Fail gpio_request gpio_ldo\n"); 2580 } 2581 2582 /* Sleep for 300 ms miniumum */ 2583 usleep_range(300000, 350000); 2584 2585 regmap_write(rt5682->regmap, RT5682_I2C_MODE, 0x1); 2586 usleep_range(10000, 15000); 2587 2588 regmap_read(rt5682->regmap, RT5682_DEVICE_ID, &val); 2589 if (val != DEVICE_ID) { 2590 pr_err("Device with ID register %x is not rt5682\n", val); 2591 return -ENODEV; 2592 } 2593 2594 rt5682_reset(rt5682->regmap); 2595 2596 mutex_init(&rt5682->calibrate_mutex); 2597 rt5682_calibrate(rt5682); 2598 2599 ret = regmap_multi_reg_write(rt5682->regmap, patch_list, 2600 ARRAY_SIZE(patch_list)); 2601 if (ret != 0) 2602 dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret); 2603 2604 regmap_write(rt5682->regmap, RT5682_DEPOP_1, 0x0000); 2605 2606 /* DMIC pin*/ 2607 if (rt5682->pdata.dmic1_data_pin != RT5682_DMIC1_NULL) { 2608 switch (rt5682->pdata.dmic1_data_pin) { 2609 case RT5682_DMIC1_DATA_GPIO2: /* share with LRCK2 */ 2610 regmap_update_bits(rt5682->regmap, RT5682_DMIC_CTRL_1, 2611 RT5682_DMIC_1_DP_MASK, RT5682_DMIC_1_DP_GPIO2); 2612 regmap_update_bits(rt5682->regmap, RT5682_GPIO_CTRL_1, 2613 RT5682_GP2_PIN_MASK, RT5682_GP2_PIN_DMIC_SDA); 2614 break; 2615 2616 case RT5682_DMIC1_DATA_GPIO5: /* share with DACDAT1 */ 2617 regmap_update_bits(rt5682->regmap, RT5682_DMIC_CTRL_1, 2618 RT5682_DMIC_1_DP_MASK, RT5682_DMIC_1_DP_GPIO5); 2619 regmap_update_bits(rt5682->regmap, RT5682_GPIO_CTRL_1, 2620 RT5682_GP5_PIN_MASK, RT5682_GP5_PIN_DMIC_SDA); 2621 break; 2622 2623 default: 2624 dev_warn(&i2c->dev, "invalid DMIC_DAT pin\n"); 2625 break; 2626 } 2627 2628 switch (rt5682->pdata.dmic1_clk_pin) { 2629 case RT5682_DMIC1_CLK_GPIO1: /* share with IRQ */ 2630 regmap_update_bits(rt5682->regmap, RT5682_GPIO_CTRL_1, 2631 RT5682_GP1_PIN_MASK, RT5682_GP1_PIN_DMIC_CLK); 2632 break; 2633 2634 case RT5682_DMIC1_CLK_GPIO3: /* share with BCLK2 */ 2635 regmap_update_bits(rt5682->regmap, RT5682_GPIO_CTRL_1, 2636 RT5682_GP3_PIN_MASK, RT5682_GP3_PIN_DMIC_CLK); 2637 break; 2638 2639 default: 2640 dev_warn(&i2c->dev, "invalid DMIC_CLK pin\n"); 2641 break; 2642 } 2643 } 2644 2645 regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_1, 2646 RT5682_LDO1_DVO_MASK | RT5682_HP_DRIVER_MASK, 2647 RT5682_LDO1_DVO_12 | RT5682_HP_DRIVER_5X); 2648 regmap_write(rt5682->regmap, RT5682_MICBIAS_2, 0x0380); 2649 regmap_update_bits(rt5682->regmap, RT5682_GPIO_CTRL_1, 2650 RT5682_GP4_PIN_MASK | RT5682_GP5_PIN_MASK, 2651 RT5682_GP4_PIN_ADCDAT1 | RT5682_GP5_PIN_DACDAT1); 2652 regmap_write(rt5682->regmap, RT5682_TEST_MODE_CTRL_1, 0x0000); 2653 regmap_update_bits(rt5682->regmap, RT5682_BIAS_CUR_CTRL_8, 2654 RT5682_HPA_CP_BIAS_CTRL_MASK, RT5682_HPA_CP_BIAS_3UA); 2655 regmap_update_bits(rt5682->regmap, RT5682_CHARGE_PUMP_1, 2656 RT5682_CP_CLK_HP_MASK, RT5682_CP_CLK_HP_300KHZ); 2657 2658 INIT_DELAYED_WORK(&rt5682->jack_detect_work, 2659 rt5682_jack_detect_handler); 2660 INIT_DELAYED_WORK(&rt5682->jd_check_work, 2661 rt5682_jd_check_handler); 2662 2663 2664 if (i2c->irq) { 2665 ret = devm_request_threaded_irq(&i2c->dev, i2c->irq, NULL, 2666 rt5682_irq, IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING 2667 | IRQF_ONESHOT, "rt5682", rt5682); 2668 if (ret) 2669 dev_err(&i2c->dev, "Failed to reguest IRQ: %d\n", ret); 2670 2671 } 2672 2673 return devm_snd_soc_register_component(&i2c->dev, 2674 &soc_component_dev_rt5682, 2675 rt5682_dai, ARRAY_SIZE(rt5682_dai)); 2676 } 2677 2678 static void rt5682_i2c_shutdown(struct i2c_client *client) 2679 { 2680 struct rt5682_priv *rt5682 = i2c_get_clientdata(client); 2681 2682 rt5682_reset(rt5682->regmap); 2683 } 2684 2685 #ifdef CONFIG_OF 2686 static const struct of_device_id rt5682_of_match[] = { 2687 {.compatible = "realtek,rt5682i"}, 2688 {}, 2689 }; 2690 MODULE_DEVICE_TABLE(of, rt5682_of_match); 2691 #endif 2692 2693 #ifdef CONFIG_ACPI 2694 static const struct acpi_device_id rt5682_acpi_match[] = { 2695 {"10EC5682", 0,}, 2696 {}, 2697 }; 2698 MODULE_DEVICE_TABLE(acpi, rt5682_acpi_match); 2699 #endif 2700 2701 static struct i2c_driver rt5682_i2c_driver = { 2702 .driver = { 2703 .name = "rt5682", 2704 .of_match_table = of_match_ptr(rt5682_of_match), 2705 .acpi_match_table = ACPI_PTR(rt5682_acpi_match), 2706 }, 2707 .probe = rt5682_i2c_probe, 2708 .shutdown = rt5682_i2c_shutdown, 2709 .id_table = rt5682_i2c_id, 2710 }; 2711 module_i2c_driver(rt5682_i2c_driver); 2712 2713 MODULE_DESCRIPTION("ASoC RT5682 driver"); 2714 MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>"); 2715 MODULE_LICENSE("GPL v2"); 2716