1 /* 2 * rt5682.c -- RT5682 ALSA SoC audio component driver 3 * 4 * Copyright 2018 Realtek Semiconductor Corp. 5 * Author: Bard Liao <bardliao@realtek.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11 12 #include <linux/module.h> 13 #include <linux/moduleparam.h> 14 #include <linux/init.h> 15 #include <linux/delay.h> 16 #include <linux/pm.h> 17 #include <linux/i2c.h> 18 #include <linux/platform_device.h> 19 #include <linux/spi/spi.h> 20 #include <linux/acpi.h> 21 #include <linux/gpio.h> 22 #include <linux/of_gpio.h> 23 #include <linux/regulator/consumer.h> 24 #include <linux/mutex.h> 25 #include <sound/core.h> 26 #include <sound/pcm.h> 27 #include <sound/pcm_params.h> 28 #include <sound/jack.h> 29 #include <sound/soc.h> 30 #include <sound/soc-dapm.h> 31 #include <sound/initval.h> 32 #include <sound/tlv.h> 33 #include <sound/rt5682.h> 34 35 #include "rl6231.h" 36 #include "rt5682.h" 37 38 #define RT5682_NUM_SUPPLIES 3 39 40 static const char *rt5682_supply_names[RT5682_NUM_SUPPLIES] = { 41 "AVDD", 42 "MICVDD", 43 "VBAT", 44 }; 45 46 static const struct rt5682_platform_data i2s_default_platform_data = { 47 .dmic1_data_pin = RT5682_DMIC1_DATA_GPIO2, 48 .dmic1_clk_pin = RT5682_DMIC1_CLK_GPIO3, 49 .jd_src = RT5682_JD1, 50 }; 51 52 struct rt5682_priv { 53 struct snd_soc_component *component; 54 struct rt5682_platform_data pdata; 55 struct regmap *regmap; 56 struct snd_soc_jack *hs_jack; 57 struct regulator_bulk_data supplies[RT5682_NUM_SUPPLIES]; 58 struct delayed_work jack_detect_work; 59 struct delayed_work jd_check_work; 60 struct mutex calibrate_mutex; 61 62 int sysclk; 63 int sysclk_src; 64 int lrck[RT5682_AIFS]; 65 int bclk[RT5682_AIFS]; 66 int master[RT5682_AIFS]; 67 68 int pll_src; 69 int pll_in; 70 int pll_out; 71 72 int jack_type; 73 }; 74 75 static const struct reg_sequence patch_list[] = { 76 {RT5682_HP_IMP_SENS_CTRL_19, 0x1000}, 77 {RT5682_DAC_ADC_DIG_VOL1, 0xa020}, 78 }; 79 80 static const struct reg_default rt5682_reg[] = { 81 {0x0002, 0x8080}, 82 {0x0003, 0x8000}, 83 {0x0005, 0x0000}, 84 {0x0006, 0x0000}, 85 {0x0008, 0x800f}, 86 {0x000b, 0x0000}, 87 {0x0010, 0x4040}, 88 {0x0011, 0x0000}, 89 {0x0012, 0x1404}, 90 {0x0013, 0x1000}, 91 {0x0014, 0xa00a}, 92 {0x0015, 0x0404}, 93 {0x0016, 0x0404}, 94 {0x0019, 0xafaf}, 95 {0x001c, 0x2f2f}, 96 {0x001f, 0x0000}, 97 {0x0022, 0x5757}, 98 {0x0023, 0x0039}, 99 {0x0024, 0x000b}, 100 {0x0026, 0xc0c4}, 101 {0x0029, 0x8080}, 102 {0x002a, 0xa0a0}, 103 {0x002b, 0x0300}, 104 {0x0030, 0x0000}, 105 {0x003c, 0x0080}, 106 {0x0044, 0x0c0c}, 107 {0x0049, 0x0000}, 108 {0x0061, 0x0000}, 109 {0x0062, 0x0000}, 110 {0x0063, 0x003f}, 111 {0x0064, 0x0000}, 112 {0x0065, 0x0000}, 113 {0x0066, 0x0030}, 114 {0x0067, 0x0000}, 115 {0x006b, 0x0000}, 116 {0x006c, 0x0000}, 117 {0x006d, 0x2200}, 118 {0x006e, 0x0a10}, 119 {0x0070, 0x8000}, 120 {0x0071, 0x8000}, 121 {0x0073, 0x0000}, 122 {0x0074, 0x0000}, 123 {0x0075, 0x0002}, 124 {0x0076, 0x0001}, 125 {0x0079, 0x0000}, 126 {0x007a, 0x0000}, 127 {0x007b, 0x0000}, 128 {0x007c, 0x0100}, 129 {0x007e, 0x0000}, 130 {0x0080, 0x0000}, 131 {0x0081, 0x0000}, 132 {0x0082, 0x0000}, 133 {0x0083, 0x0000}, 134 {0x0084, 0x0000}, 135 {0x0085, 0x0000}, 136 {0x0086, 0x0005}, 137 {0x0087, 0x0000}, 138 {0x0088, 0x0000}, 139 {0x008c, 0x0003}, 140 {0x008d, 0x0000}, 141 {0x008e, 0x0060}, 142 {0x008f, 0x1000}, 143 {0x0091, 0x0c26}, 144 {0x0092, 0x0073}, 145 {0x0093, 0x0000}, 146 {0x0094, 0x0080}, 147 {0x0098, 0x0000}, 148 {0x009a, 0x0000}, 149 {0x009b, 0x0000}, 150 {0x009c, 0x0000}, 151 {0x009d, 0x0000}, 152 {0x009e, 0x100c}, 153 {0x009f, 0x0000}, 154 {0x00a0, 0x0000}, 155 {0x00a3, 0x0002}, 156 {0x00a4, 0x0001}, 157 {0x00ae, 0x2040}, 158 {0x00af, 0x0000}, 159 {0x00b6, 0x0000}, 160 {0x00b7, 0x0000}, 161 {0x00b8, 0x0000}, 162 {0x00b9, 0x0002}, 163 {0x00be, 0x0000}, 164 {0x00c0, 0x0160}, 165 {0x00c1, 0x82a0}, 166 {0x00c2, 0x0000}, 167 {0x00d0, 0x0000}, 168 {0x00d1, 0x2244}, 169 {0x00d2, 0x3300}, 170 {0x00d3, 0x2200}, 171 {0x00d4, 0x0000}, 172 {0x00d9, 0x0009}, 173 {0x00da, 0x0000}, 174 {0x00db, 0x0000}, 175 {0x00dc, 0x00c0}, 176 {0x00dd, 0x2220}, 177 {0x00de, 0x3131}, 178 {0x00df, 0x3131}, 179 {0x00e0, 0x3131}, 180 {0x00e2, 0x0000}, 181 {0x00e3, 0x4000}, 182 {0x00e4, 0x0aa0}, 183 {0x00e5, 0x3131}, 184 {0x00e6, 0x3131}, 185 {0x00e7, 0x3131}, 186 {0x00e8, 0x3131}, 187 {0x00ea, 0xb320}, 188 {0x00eb, 0x0000}, 189 {0x00f0, 0x0000}, 190 {0x00f1, 0x00d0}, 191 {0x00f2, 0x00d0}, 192 {0x00f6, 0x0000}, 193 {0x00fa, 0x0000}, 194 {0x00fb, 0x0000}, 195 {0x00fc, 0x0000}, 196 {0x00fd, 0x0000}, 197 {0x00fe, 0x10ec}, 198 {0x00ff, 0x6530}, 199 {0x0100, 0xa0a0}, 200 {0x010b, 0x0000}, 201 {0x010c, 0xae00}, 202 {0x010d, 0xaaa0}, 203 {0x010e, 0x8aa2}, 204 {0x010f, 0x02a2}, 205 {0x0110, 0xc000}, 206 {0x0111, 0x04a2}, 207 {0x0112, 0x2800}, 208 {0x0113, 0x0000}, 209 {0x0117, 0x0100}, 210 {0x0125, 0x0410}, 211 {0x0132, 0x6026}, 212 {0x0136, 0x5555}, 213 {0x0138, 0x3700}, 214 {0x013a, 0x2000}, 215 {0x013b, 0x2000}, 216 {0x013c, 0x2005}, 217 {0x013f, 0x0000}, 218 {0x0142, 0x0000}, 219 {0x0145, 0x0002}, 220 {0x0146, 0x0000}, 221 {0x0147, 0x0000}, 222 {0x0148, 0x0000}, 223 {0x0149, 0x0000}, 224 {0x0150, 0x79a1}, 225 {0x0151, 0x0000}, 226 {0x0160, 0x4ec0}, 227 {0x0161, 0x0080}, 228 {0x0162, 0x0200}, 229 {0x0163, 0x0800}, 230 {0x0164, 0x0000}, 231 {0x0165, 0x0000}, 232 {0x0166, 0x0000}, 233 {0x0167, 0x000f}, 234 {0x0168, 0x000f}, 235 {0x0169, 0x0021}, 236 {0x0190, 0x413d}, 237 {0x0194, 0x0000}, 238 {0x0195, 0x0000}, 239 {0x0197, 0x0022}, 240 {0x0198, 0x0000}, 241 {0x0199, 0x0000}, 242 {0x01af, 0x0000}, 243 {0x01b0, 0x0400}, 244 {0x01b1, 0x0000}, 245 {0x01b2, 0x0000}, 246 {0x01b3, 0x0000}, 247 {0x01b4, 0x0000}, 248 {0x01b5, 0x0000}, 249 {0x01b6, 0x01c3}, 250 {0x01b7, 0x02a0}, 251 {0x01b8, 0x03e9}, 252 {0x01b9, 0x1389}, 253 {0x01ba, 0xc351}, 254 {0x01bb, 0x0009}, 255 {0x01bc, 0x0018}, 256 {0x01bd, 0x002a}, 257 {0x01be, 0x004c}, 258 {0x01bf, 0x0097}, 259 {0x01c0, 0x433d}, 260 {0x01c2, 0x0000}, 261 {0x01c3, 0x0000}, 262 {0x01c4, 0x0000}, 263 {0x01c5, 0x0000}, 264 {0x01c6, 0x0000}, 265 {0x01c7, 0x0000}, 266 {0x01c8, 0x40af}, 267 {0x01c9, 0x0702}, 268 {0x01ca, 0x0000}, 269 {0x01cb, 0x0000}, 270 {0x01cc, 0x5757}, 271 {0x01cd, 0x5757}, 272 {0x01ce, 0x5757}, 273 {0x01cf, 0x5757}, 274 {0x01d0, 0x5757}, 275 {0x01d1, 0x5757}, 276 {0x01d2, 0x5757}, 277 {0x01d3, 0x5757}, 278 {0x01d4, 0x5757}, 279 {0x01d5, 0x5757}, 280 {0x01d6, 0x0000}, 281 {0x01d7, 0x0008}, 282 {0x01d8, 0x0029}, 283 {0x01d9, 0x3333}, 284 {0x01da, 0x0000}, 285 {0x01db, 0x0004}, 286 {0x01dc, 0x0000}, 287 {0x01de, 0x7c00}, 288 {0x01df, 0x0320}, 289 {0x01e0, 0x06a1}, 290 {0x01e1, 0x0000}, 291 {0x01e2, 0x0000}, 292 {0x01e3, 0x0000}, 293 {0x01e4, 0x0000}, 294 {0x01e6, 0x0001}, 295 {0x01e7, 0x0000}, 296 {0x01e8, 0x0000}, 297 {0x01ea, 0x0000}, 298 {0x01eb, 0x0000}, 299 {0x01ec, 0x0000}, 300 {0x01ed, 0x0000}, 301 {0x01ee, 0x0000}, 302 {0x01ef, 0x0000}, 303 {0x01f0, 0x0000}, 304 {0x01f1, 0x0000}, 305 {0x01f2, 0x0000}, 306 {0x01f3, 0x0000}, 307 {0x01f4, 0x0000}, 308 {0x0210, 0x6297}, 309 {0x0211, 0xa005}, 310 {0x0212, 0x824c}, 311 {0x0213, 0xf7ff}, 312 {0x0214, 0xf24c}, 313 {0x0215, 0x0102}, 314 {0x0216, 0x00a3}, 315 {0x0217, 0x0048}, 316 {0x0218, 0xa2c0}, 317 {0x0219, 0x0400}, 318 {0x021a, 0x00c8}, 319 {0x021b, 0x00c0}, 320 {0x021c, 0x0000}, 321 {0x0250, 0x4500}, 322 {0x0251, 0x40b3}, 323 {0x0252, 0x0000}, 324 {0x0253, 0x0000}, 325 {0x0254, 0x0000}, 326 {0x0255, 0x0000}, 327 {0x0256, 0x0000}, 328 {0x0257, 0x0000}, 329 {0x0258, 0x0000}, 330 {0x0259, 0x0000}, 331 {0x025a, 0x0005}, 332 {0x0270, 0x0000}, 333 {0x02ff, 0x0110}, 334 {0x0300, 0x001f}, 335 {0x0301, 0x032c}, 336 {0x0302, 0x5f21}, 337 {0x0303, 0x4000}, 338 {0x0304, 0x4000}, 339 {0x0305, 0x06d5}, 340 {0x0306, 0x8000}, 341 {0x0307, 0x0700}, 342 {0x0310, 0x4560}, 343 {0x0311, 0xa4a8}, 344 {0x0312, 0x7418}, 345 {0x0313, 0x0000}, 346 {0x0314, 0x0006}, 347 {0x0315, 0xffff}, 348 {0x0316, 0xc400}, 349 {0x0317, 0x0000}, 350 {0x03c0, 0x7e00}, 351 {0x03c1, 0x8000}, 352 {0x03c2, 0x8000}, 353 {0x03c3, 0x8000}, 354 {0x03c4, 0x8000}, 355 {0x03c5, 0x8000}, 356 {0x03c6, 0x8000}, 357 {0x03c7, 0x8000}, 358 {0x03c8, 0x8000}, 359 {0x03c9, 0x8000}, 360 {0x03ca, 0x8000}, 361 {0x03cb, 0x8000}, 362 {0x03cc, 0x8000}, 363 {0x03d0, 0x0000}, 364 {0x03d1, 0x0000}, 365 {0x03d2, 0x0000}, 366 {0x03d3, 0x0000}, 367 {0x03d4, 0x2000}, 368 {0x03d5, 0x2000}, 369 {0x03d6, 0x0000}, 370 {0x03d7, 0x0000}, 371 {0x03d8, 0x2000}, 372 {0x03d9, 0x2000}, 373 {0x03da, 0x2000}, 374 {0x03db, 0x2000}, 375 {0x03dc, 0x0000}, 376 {0x03dd, 0x0000}, 377 {0x03de, 0x0000}, 378 {0x03df, 0x2000}, 379 {0x03e0, 0x0000}, 380 {0x03e1, 0x0000}, 381 {0x03e2, 0x0000}, 382 {0x03e3, 0x0000}, 383 {0x03e4, 0x0000}, 384 {0x03e5, 0x0000}, 385 {0x03e6, 0x0000}, 386 {0x03e7, 0x0000}, 387 {0x03e8, 0x0000}, 388 {0x03e9, 0x0000}, 389 {0x03ea, 0x0000}, 390 {0x03eb, 0x0000}, 391 {0x03ec, 0x0000}, 392 {0x03ed, 0x0000}, 393 {0x03ee, 0x0000}, 394 {0x03ef, 0x0000}, 395 {0x03f0, 0x0800}, 396 {0x03f1, 0x0800}, 397 {0x03f2, 0x0800}, 398 {0x03f3, 0x0800}, 399 }; 400 401 static bool rt5682_volatile_register(struct device *dev, unsigned int reg) 402 { 403 switch (reg) { 404 case RT5682_RESET: 405 case RT5682_CBJ_CTRL_2: 406 case RT5682_INT_ST_1: 407 case RT5682_4BTN_IL_CMD_1: 408 case RT5682_AJD1_CTRL: 409 case RT5682_HP_CALIB_CTRL_1: 410 case RT5682_DEVICE_ID: 411 case RT5682_I2C_MODE: 412 case RT5682_HP_CALIB_CTRL_10: 413 case RT5682_EFUSE_CTRL_2: 414 case RT5682_JD_TOP_VC_VTRL: 415 case RT5682_HP_IMP_SENS_CTRL_19: 416 case RT5682_IL_CMD_1: 417 case RT5682_SAR_IL_CMD_2: 418 case RT5682_SAR_IL_CMD_4: 419 case RT5682_SAR_IL_CMD_10: 420 case RT5682_SAR_IL_CMD_11: 421 case RT5682_EFUSE_CTRL_6...RT5682_EFUSE_CTRL_11: 422 case RT5682_HP_CALIB_STA_1...RT5682_HP_CALIB_STA_11: 423 return true; 424 default: 425 return false; 426 } 427 } 428 429 static bool rt5682_readable_register(struct device *dev, unsigned int reg) 430 { 431 switch (reg) { 432 case RT5682_RESET: 433 case RT5682_VERSION_ID: 434 case RT5682_VENDOR_ID: 435 case RT5682_DEVICE_ID: 436 case RT5682_HP_CTRL_1: 437 case RT5682_HP_CTRL_2: 438 case RT5682_HPL_GAIN: 439 case RT5682_HPR_GAIN: 440 case RT5682_I2C_CTRL: 441 case RT5682_CBJ_BST_CTRL: 442 case RT5682_CBJ_CTRL_1: 443 case RT5682_CBJ_CTRL_2: 444 case RT5682_CBJ_CTRL_3: 445 case RT5682_CBJ_CTRL_4: 446 case RT5682_CBJ_CTRL_5: 447 case RT5682_CBJ_CTRL_6: 448 case RT5682_CBJ_CTRL_7: 449 case RT5682_DAC1_DIG_VOL: 450 case RT5682_STO1_ADC_DIG_VOL: 451 case RT5682_STO1_ADC_BOOST: 452 case RT5682_HP_IMP_GAIN_1: 453 case RT5682_HP_IMP_GAIN_2: 454 case RT5682_SIDETONE_CTRL: 455 case RT5682_STO1_ADC_MIXER: 456 case RT5682_AD_DA_MIXER: 457 case RT5682_STO1_DAC_MIXER: 458 case RT5682_A_DAC1_MUX: 459 case RT5682_DIG_INF2_DATA: 460 case RT5682_REC_MIXER: 461 case RT5682_CAL_REC: 462 case RT5682_ALC_BACK_GAIN: 463 case RT5682_PWR_DIG_1: 464 case RT5682_PWR_DIG_2: 465 case RT5682_PWR_ANLG_1: 466 case RT5682_PWR_ANLG_2: 467 case RT5682_PWR_ANLG_3: 468 case RT5682_PWR_MIXER: 469 case RT5682_PWR_VOL: 470 case RT5682_CLK_DET: 471 case RT5682_RESET_LPF_CTRL: 472 case RT5682_RESET_HPF_CTRL: 473 case RT5682_DMIC_CTRL_1: 474 case RT5682_I2S1_SDP: 475 case RT5682_I2S2_SDP: 476 case RT5682_ADDA_CLK_1: 477 case RT5682_ADDA_CLK_2: 478 case RT5682_I2S1_F_DIV_CTRL_1: 479 case RT5682_I2S1_F_DIV_CTRL_2: 480 case RT5682_TDM_CTRL: 481 case RT5682_TDM_ADDA_CTRL_1: 482 case RT5682_TDM_ADDA_CTRL_2: 483 case RT5682_DATA_SEL_CTRL_1: 484 case RT5682_TDM_TCON_CTRL: 485 case RT5682_GLB_CLK: 486 case RT5682_PLL_CTRL_1: 487 case RT5682_PLL_CTRL_2: 488 case RT5682_PLL_TRACK_1: 489 case RT5682_PLL_TRACK_2: 490 case RT5682_PLL_TRACK_3: 491 case RT5682_PLL_TRACK_4: 492 case RT5682_PLL_TRACK_5: 493 case RT5682_PLL_TRACK_6: 494 case RT5682_PLL_TRACK_11: 495 case RT5682_SDW_REF_CLK: 496 case RT5682_DEPOP_1: 497 case RT5682_DEPOP_2: 498 case RT5682_HP_CHARGE_PUMP_1: 499 case RT5682_HP_CHARGE_PUMP_2: 500 case RT5682_MICBIAS_1: 501 case RT5682_MICBIAS_2: 502 case RT5682_PLL_TRACK_12: 503 case RT5682_PLL_TRACK_14: 504 case RT5682_PLL2_CTRL_1: 505 case RT5682_PLL2_CTRL_2: 506 case RT5682_PLL2_CTRL_3: 507 case RT5682_PLL2_CTRL_4: 508 case RT5682_RC_CLK_CTRL: 509 case RT5682_I2S_M_CLK_CTRL_1: 510 case RT5682_I2S2_F_DIV_CTRL_1: 511 case RT5682_I2S2_F_DIV_CTRL_2: 512 case RT5682_EQ_CTRL_1: 513 case RT5682_EQ_CTRL_2: 514 case RT5682_IRQ_CTRL_1: 515 case RT5682_IRQ_CTRL_2: 516 case RT5682_IRQ_CTRL_3: 517 case RT5682_IRQ_CTRL_4: 518 case RT5682_INT_ST_1: 519 case RT5682_GPIO_CTRL_1: 520 case RT5682_GPIO_CTRL_2: 521 case RT5682_GPIO_CTRL_3: 522 case RT5682_HP_AMP_DET_CTRL_1: 523 case RT5682_HP_AMP_DET_CTRL_2: 524 case RT5682_MID_HP_AMP_DET: 525 case RT5682_LOW_HP_AMP_DET: 526 case RT5682_DELAY_BUF_CTRL: 527 case RT5682_SV_ZCD_1: 528 case RT5682_SV_ZCD_2: 529 case RT5682_IL_CMD_1: 530 case RT5682_IL_CMD_2: 531 case RT5682_IL_CMD_3: 532 case RT5682_IL_CMD_4: 533 case RT5682_IL_CMD_5: 534 case RT5682_IL_CMD_6: 535 case RT5682_4BTN_IL_CMD_1: 536 case RT5682_4BTN_IL_CMD_2: 537 case RT5682_4BTN_IL_CMD_3: 538 case RT5682_4BTN_IL_CMD_4: 539 case RT5682_4BTN_IL_CMD_5: 540 case RT5682_4BTN_IL_CMD_6: 541 case RT5682_4BTN_IL_CMD_7: 542 case RT5682_ADC_STO1_HP_CTRL_1: 543 case RT5682_ADC_STO1_HP_CTRL_2: 544 case RT5682_AJD1_CTRL: 545 case RT5682_JD1_THD: 546 case RT5682_JD2_THD: 547 case RT5682_JD_CTRL_1: 548 case RT5682_DUMMY_1: 549 case RT5682_DUMMY_2: 550 case RT5682_DUMMY_3: 551 case RT5682_DAC_ADC_DIG_VOL1: 552 case RT5682_BIAS_CUR_CTRL_2: 553 case RT5682_BIAS_CUR_CTRL_3: 554 case RT5682_BIAS_CUR_CTRL_4: 555 case RT5682_BIAS_CUR_CTRL_5: 556 case RT5682_BIAS_CUR_CTRL_6: 557 case RT5682_BIAS_CUR_CTRL_7: 558 case RT5682_BIAS_CUR_CTRL_8: 559 case RT5682_BIAS_CUR_CTRL_9: 560 case RT5682_BIAS_CUR_CTRL_10: 561 case RT5682_VREF_REC_OP_FB_CAP_CTRL: 562 case RT5682_CHARGE_PUMP_1: 563 case RT5682_DIG_IN_CTRL_1: 564 case RT5682_PAD_DRIVING_CTRL: 565 case RT5682_SOFT_RAMP_DEPOP: 566 case RT5682_CHOP_DAC: 567 case RT5682_CHOP_ADC: 568 case RT5682_CALIB_ADC_CTRL: 569 case RT5682_VOL_TEST: 570 case RT5682_SPKVDD_DET_STA: 571 case RT5682_TEST_MODE_CTRL_1: 572 case RT5682_TEST_MODE_CTRL_2: 573 case RT5682_TEST_MODE_CTRL_3: 574 case RT5682_TEST_MODE_CTRL_4: 575 case RT5682_TEST_MODE_CTRL_5: 576 case RT5682_PLL1_INTERNAL: 577 case RT5682_PLL2_INTERNAL: 578 case RT5682_STO_NG2_CTRL_1: 579 case RT5682_STO_NG2_CTRL_2: 580 case RT5682_STO_NG2_CTRL_3: 581 case RT5682_STO_NG2_CTRL_4: 582 case RT5682_STO_NG2_CTRL_5: 583 case RT5682_STO_NG2_CTRL_6: 584 case RT5682_STO_NG2_CTRL_7: 585 case RT5682_STO_NG2_CTRL_8: 586 case RT5682_STO_NG2_CTRL_9: 587 case RT5682_STO_NG2_CTRL_10: 588 case RT5682_STO1_DAC_SIL_DET: 589 case RT5682_SIL_PSV_CTRL1: 590 case RT5682_SIL_PSV_CTRL2: 591 case RT5682_SIL_PSV_CTRL3: 592 case RT5682_SIL_PSV_CTRL4: 593 case RT5682_SIL_PSV_CTRL5: 594 case RT5682_HP_IMP_SENS_CTRL_01: 595 case RT5682_HP_IMP_SENS_CTRL_02: 596 case RT5682_HP_IMP_SENS_CTRL_03: 597 case RT5682_HP_IMP_SENS_CTRL_04: 598 case RT5682_HP_IMP_SENS_CTRL_05: 599 case RT5682_HP_IMP_SENS_CTRL_06: 600 case RT5682_HP_IMP_SENS_CTRL_07: 601 case RT5682_HP_IMP_SENS_CTRL_08: 602 case RT5682_HP_IMP_SENS_CTRL_09: 603 case RT5682_HP_IMP_SENS_CTRL_10: 604 case RT5682_HP_IMP_SENS_CTRL_11: 605 case RT5682_HP_IMP_SENS_CTRL_12: 606 case RT5682_HP_IMP_SENS_CTRL_13: 607 case RT5682_HP_IMP_SENS_CTRL_14: 608 case RT5682_HP_IMP_SENS_CTRL_15: 609 case RT5682_HP_IMP_SENS_CTRL_16: 610 case RT5682_HP_IMP_SENS_CTRL_17: 611 case RT5682_HP_IMP_SENS_CTRL_18: 612 case RT5682_HP_IMP_SENS_CTRL_19: 613 case RT5682_HP_IMP_SENS_CTRL_20: 614 case RT5682_HP_IMP_SENS_CTRL_21: 615 case RT5682_HP_IMP_SENS_CTRL_22: 616 case RT5682_HP_IMP_SENS_CTRL_23: 617 case RT5682_HP_IMP_SENS_CTRL_24: 618 case RT5682_HP_IMP_SENS_CTRL_25: 619 case RT5682_HP_IMP_SENS_CTRL_26: 620 case RT5682_HP_IMP_SENS_CTRL_27: 621 case RT5682_HP_IMP_SENS_CTRL_28: 622 case RT5682_HP_IMP_SENS_CTRL_29: 623 case RT5682_HP_IMP_SENS_CTRL_30: 624 case RT5682_HP_IMP_SENS_CTRL_31: 625 case RT5682_HP_IMP_SENS_CTRL_32: 626 case RT5682_HP_IMP_SENS_CTRL_33: 627 case RT5682_HP_IMP_SENS_CTRL_34: 628 case RT5682_HP_IMP_SENS_CTRL_35: 629 case RT5682_HP_IMP_SENS_CTRL_36: 630 case RT5682_HP_IMP_SENS_CTRL_37: 631 case RT5682_HP_IMP_SENS_CTRL_38: 632 case RT5682_HP_IMP_SENS_CTRL_39: 633 case RT5682_HP_IMP_SENS_CTRL_40: 634 case RT5682_HP_IMP_SENS_CTRL_41: 635 case RT5682_HP_IMP_SENS_CTRL_42: 636 case RT5682_HP_IMP_SENS_CTRL_43: 637 case RT5682_HP_LOGIC_CTRL_1: 638 case RT5682_HP_LOGIC_CTRL_2: 639 case RT5682_HP_LOGIC_CTRL_3: 640 case RT5682_HP_CALIB_CTRL_1: 641 case RT5682_HP_CALIB_CTRL_2: 642 case RT5682_HP_CALIB_CTRL_3: 643 case RT5682_HP_CALIB_CTRL_4: 644 case RT5682_HP_CALIB_CTRL_5: 645 case RT5682_HP_CALIB_CTRL_6: 646 case RT5682_HP_CALIB_CTRL_7: 647 case RT5682_HP_CALIB_CTRL_9: 648 case RT5682_HP_CALIB_CTRL_10: 649 case RT5682_HP_CALIB_CTRL_11: 650 case RT5682_HP_CALIB_STA_1: 651 case RT5682_HP_CALIB_STA_2: 652 case RT5682_HP_CALIB_STA_3: 653 case RT5682_HP_CALIB_STA_4: 654 case RT5682_HP_CALIB_STA_5: 655 case RT5682_HP_CALIB_STA_6: 656 case RT5682_HP_CALIB_STA_7: 657 case RT5682_HP_CALIB_STA_8: 658 case RT5682_HP_CALIB_STA_9: 659 case RT5682_HP_CALIB_STA_10: 660 case RT5682_HP_CALIB_STA_11: 661 case RT5682_SAR_IL_CMD_1: 662 case RT5682_SAR_IL_CMD_2: 663 case RT5682_SAR_IL_CMD_3: 664 case RT5682_SAR_IL_CMD_4: 665 case RT5682_SAR_IL_CMD_5: 666 case RT5682_SAR_IL_CMD_6: 667 case RT5682_SAR_IL_CMD_7: 668 case RT5682_SAR_IL_CMD_8: 669 case RT5682_SAR_IL_CMD_9: 670 case RT5682_SAR_IL_CMD_10: 671 case RT5682_SAR_IL_CMD_11: 672 case RT5682_SAR_IL_CMD_12: 673 case RT5682_SAR_IL_CMD_13: 674 case RT5682_EFUSE_CTRL_1: 675 case RT5682_EFUSE_CTRL_2: 676 case RT5682_EFUSE_CTRL_3: 677 case RT5682_EFUSE_CTRL_4: 678 case RT5682_EFUSE_CTRL_5: 679 case RT5682_EFUSE_CTRL_6: 680 case RT5682_EFUSE_CTRL_7: 681 case RT5682_EFUSE_CTRL_8: 682 case RT5682_EFUSE_CTRL_9: 683 case RT5682_EFUSE_CTRL_10: 684 case RT5682_EFUSE_CTRL_11: 685 case RT5682_JD_TOP_VC_VTRL: 686 case RT5682_DRC1_CTRL_0: 687 case RT5682_DRC1_CTRL_1: 688 case RT5682_DRC1_CTRL_2: 689 case RT5682_DRC1_CTRL_3: 690 case RT5682_DRC1_CTRL_4: 691 case RT5682_DRC1_CTRL_5: 692 case RT5682_DRC1_CTRL_6: 693 case RT5682_DRC1_HARD_LMT_CTRL_1: 694 case RT5682_DRC1_HARD_LMT_CTRL_2: 695 case RT5682_DRC1_PRIV_1: 696 case RT5682_DRC1_PRIV_2: 697 case RT5682_DRC1_PRIV_3: 698 case RT5682_DRC1_PRIV_4: 699 case RT5682_DRC1_PRIV_5: 700 case RT5682_DRC1_PRIV_6: 701 case RT5682_DRC1_PRIV_7: 702 case RT5682_DRC1_PRIV_8: 703 case RT5682_EQ_AUTO_RCV_CTRL1: 704 case RT5682_EQ_AUTO_RCV_CTRL2: 705 case RT5682_EQ_AUTO_RCV_CTRL3: 706 case RT5682_EQ_AUTO_RCV_CTRL4: 707 case RT5682_EQ_AUTO_RCV_CTRL5: 708 case RT5682_EQ_AUTO_RCV_CTRL6: 709 case RT5682_EQ_AUTO_RCV_CTRL7: 710 case RT5682_EQ_AUTO_RCV_CTRL8: 711 case RT5682_EQ_AUTO_RCV_CTRL9: 712 case RT5682_EQ_AUTO_RCV_CTRL10: 713 case RT5682_EQ_AUTO_RCV_CTRL11: 714 case RT5682_EQ_AUTO_RCV_CTRL12: 715 case RT5682_EQ_AUTO_RCV_CTRL13: 716 case RT5682_ADC_L_EQ_LPF1_A1: 717 case RT5682_R_EQ_LPF1_A1: 718 case RT5682_L_EQ_LPF1_H0: 719 case RT5682_R_EQ_LPF1_H0: 720 case RT5682_L_EQ_BPF1_A1: 721 case RT5682_R_EQ_BPF1_A1: 722 case RT5682_L_EQ_BPF1_A2: 723 case RT5682_R_EQ_BPF1_A2: 724 case RT5682_L_EQ_BPF1_H0: 725 case RT5682_R_EQ_BPF1_H0: 726 case RT5682_L_EQ_BPF2_A1: 727 case RT5682_R_EQ_BPF2_A1: 728 case RT5682_L_EQ_BPF2_A2: 729 case RT5682_R_EQ_BPF2_A2: 730 case RT5682_L_EQ_BPF2_H0: 731 case RT5682_R_EQ_BPF2_H0: 732 case RT5682_L_EQ_BPF3_A1: 733 case RT5682_R_EQ_BPF3_A1: 734 case RT5682_L_EQ_BPF3_A2: 735 case RT5682_R_EQ_BPF3_A2: 736 case RT5682_L_EQ_BPF3_H0: 737 case RT5682_R_EQ_BPF3_H0: 738 case RT5682_L_EQ_BPF4_A1: 739 case RT5682_R_EQ_BPF4_A1: 740 case RT5682_L_EQ_BPF4_A2: 741 case RT5682_R_EQ_BPF4_A2: 742 case RT5682_L_EQ_BPF4_H0: 743 case RT5682_R_EQ_BPF4_H0: 744 case RT5682_L_EQ_HPF1_A1: 745 case RT5682_R_EQ_HPF1_A1: 746 case RT5682_L_EQ_HPF1_H0: 747 case RT5682_R_EQ_HPF1_H0: 748 case RT5682_L_EQ_PRE_VOL: 749 case RT5682_R_EQ_PRE_VOL: 750 case RT5682_L_EQ_POST_VOL: 751 case RT5682_R_EQ_POST_VOL: 752 case RT5682_I2C_MODE: 753 return true; 754 default: 755 return false; 756 } 757 } 758 759 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6525, 75, 0); 760 static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0); 761 static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0); 762 763 /* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */ 764 static const DECLARE_TLV_DB_RANGE(bst_tlv, 765 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0), 766 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0), 767 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0), 768 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0), 769 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0), 770 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0), 771 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0) 772 ); 773 774 /* Interface data select */ 775 static const char * const rt5682_data_select[] = { 776 "L/R", "R/L", "L/L", "R/R" 777 }; 778 779 static SOC_ENUM_SINGLE_DECL(rt5682_if2_adc_enum, 780 RT5682_DIG_INF2_DATA, RT5682_IF2_ADC_SEL_SFT, rt5682_data_select); 781 782 static SOC_ENUM_SINGLE_DECL(rt5682_if1_01_adc_enum, 783 RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC1_SEL_SFT, rt5682_data_select); 784 785 static SOC_ENUM_SINGLE_DECL(rt5682_if1_23_adc_enum, 786 RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC2_SEL_SFT, rt5682_data_select); 787 788 static SOC_ENUM_SINGLE_DECL(rt5682_if1_45_adc_enum, 789 RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC3_SEL_SFT, rt5682_data_select); 790 791 static SOC_ENUM_SINGLE_DECL(rt5682_if1_67_adc_enum, 792 RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC4_SEL_SFT, rt5682_data_select); 793 794 static const struct snd_kcontrol_new rt5682_if2_adc_swap_mux = 795 SOC_DAPM_ENUM("IF2 ADC Swap Mux", rt5682_if2_adc_enum); 796 797 static const struct snd_kcontrol_new rt5682_if1_01_adc_swap_mux = 798 SOC_DAPM_ENUM("IF1 01 ADC Swap Mux", rt5682_if1_01_adc_enum); 799 800 static const struct snd_kcontrol_new rt5682_if1_23_adc_swap_mux = 801 SOC_DAPM_ENUM("IF1 23 ADC Swap Mux", rt5682_if1_23_adc_enum); 802 803 static const struct snd_kcontrol_new rt5682_if1_45_adc_swap_mux = 804 SOC_DAPM_ENUM("IF1 45 ADC Swap Mux", rt5682_if1_45_adc_enum); 805 806 static const struct snd_kcontrol_new rt5682_if1_67_adc_swap_mux = 807 SOC_DAPM_ENUM("IF1 67 ADC Swap Mux", rt5682_if1_67_adc_enum); 808 809 static void rt5682_reset(struct regmap *regmap) 810 { 811 regmap_write(regmap, RT5682_RESET, 0); 812 regmap_write(regmap, RT5682_I2C_MODE, 1); 813 } 814 /** 815 * rt5682_sel_asrc_clk_src - select ASRC clock source for a set of filters 816 * @component: SoC audio component device. 817 * @filter_mask: mask of filters. 818 * @clk_src: clock source 819 * 820 * The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5682 can 821 * only support standard 32fs or 64fs i2s format, ASRC should be enabled to 822 * support special i2s clock format such as Intel's 100fs(100 * sampling rate). 823 * ASRC function will track i2s clock and generate a corresponding system clock 824 * for codec. This function provides an API to select the clock source for a 825 * set of filters specified by the mask. And the component driver will turn on 826 * ASRC for these filters if ASRC is selected as their clock source. 827 */ 828 int rt5682_sel_asrc_clk_src(struct snd_soc_component *component, 829 unsigned int filter_mask, unsigned int clk_src) 830 { 831 832 switch (clk_src) { 833 case RT5682_CLK_SEL_SYS: 834 case RT5682_CLK_SEL_I2S1_ASRC: 835 case RT5682_CLK_SEL_I2S2_ASRC: 836 break; 837 838 default: 839 return -EINVAL; 840 } 841 842 if (filter_mask & RT5682_DA_STEREO1_FILTER) { 843 snd_soc_component_update_bits(component, RT5682_PLL_TRACK_2, 844 RT5682_FILTER_CLK_SEL_MASK, 845 clk_src << RT5682_FILTER_CLK_SEL_SFT); 846 } 847 848 if (filter_mask & RT5682_AD_STEREO1_FILTER) { 849 snd_soc_component_update_bits(component, RT5682_PLL_TRACK_3, 850 RT5682_FILTER_CLK_SEL_MASK, 851 clk_src << RT5682_FILTER_CLK_SEL_SFT); 852 } 853 854 return 0; 855 } 856 EXPORT_SYMBOL_GPL(rt5682_sel_asrc_clk_src); 857 858 static int rt5682_button_detect(struct snd_soc_component *component) 859 { 860 int btn_type, val; 861 862 val = snd_soc_component_read32(component, RT5682_4BTN_IL_CMD_1); 863 btn_type = val & 0xfff0; 864 snd_soc_component_write(component, RT5682_4BTN_IL_CMD_1, val); 865 pr_debug("%s btn_type=%x\n", __func__, btn_type); 866 snd_soc_component_update_bits(component, 867 RT5682_SAR_IL_CMD_2, 0x10, 0x10); 868 869 return btn_type; 870 } 871 872 static void rt5682_enable_push_button_irq(struct snd_soc_component *component, 873 bool enable) 874 { 875 if (enable) { 876 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1, 877 RT5682_SAR_BUTT_DET_MASK, RT5682_SAR_BUTT_DET_EN); 878 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_13, 879 RT5682_SAR_SOUR_MASK, RT5682_SAR_SOUR_BTN); 880 snd_soc_component_write(component, RT5682_IL_CMD_1, 0x0040); 881 snd_soc_component_update_bits(component, RT5682_4BTN_IL_CMD_2, 882 RT5682_4BTN_IL_MASK | RT5682_4BTN_IL_RST_MASK, 883 RT5682_4BTN_IL_EN | RT5682_4BTN_IL_NOR); 884 snd_soc_component_update_bits(component, RT5682_IRQ_CTRL_3, 885 RT5682_IL_IRQ_MASK, RT5682_IL_IRQ_EN); 886 } else { 887 snd_soc_component_update_bits(component, RT5682_IRQ_CTRL_3, 888 RT5682_IL_IRQ_MASK, RT5682_IL_IRQ_DIS); 889 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1, 890 RT5682_SAR_BUTT_DET_MASK, RT5682_SAR_BUTT_DET_DIS); 891 snd_soc_component_update_bits(component, RT5682_4BTN_IL_CMD_2, 892 RT5682_4BTN_IL_MASK, RT5682_4BTN_IL_DIS); 893 snd_soc_component_update_bits(component, RT5682_4BTN_IL_CMD_2, 894 RT5682_4BTN_IL_RST_MASK, RT5682_4BTN_IL_RST); 895 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_13, 896 RT5682_SAR_SOUR_MASK, RT5682_SAR_SOUR_TYPE); 897 } 898 } 899 900 /** 901 * rt5682_headset_detect - Detect headset. 902 * @component: SoC audio component device. 903 * @jack_insert: Jack insert or not. 904 * 905 * Detect whether is headset or not when jack inserted. 906 * 907 * Returns detect status. 908 */ 909 static int rt5682_headset_detect(struct snd_soc_component *component, 910 int jack_insert) 911 { 912 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 913 struct snd_soc_dapm_context *dapm = 914 snd_soc_component_get_dapm(component); 915 unsigned int val, count; 916 917 if (jack_insert) { 918 snd_soc_dapm_force_enable_pin(dapm, "CBJ Power"); 919 snd_soc_dapm_sync(dapm); 920 snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1, 921 RT5682_TRIG_JD_MASK, RT5682_TRIG_JD_HIGH); 922 923 count = 0; 924 val = snd_soc_component_read32(component, RT5682_CBJ_CTRL_2) 925 & RT5682_JACK_TYPE_MASK; 926 while (val == 0 && count < 50) { 927 usleep_range(10000, 15000); 928 val = snd_soc_component_read32(component, 929 RT5682_CBJ_CTRL_2) & RT5682_JACK_TYPE_MASK; 930 count++; 931 } 932 933 switch (val) { 934 case 0x1: 935 case 0x2: 936 rt5682->jack_type = SND_JACK_HEADSET; 937 rt5682_enable_push_button_irq(component, true); 938 break; 939 default: 940 rt5682->jack_type = SND_JACK_HEADPHONE; 941 } 942 943 } else { 944 rt5682_enable_push_button_irq(component, false); 945 snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1, 946 RT5682_TRIG_JD_MASK, RT5682_TRIG_JD_LOW); 947 snd_soc_dapm_disable_pin(dapm, "CBJ Power"); 948 snd_soc_dapm_sync(dapm); 949 950 rt5682->jack_type = 0; 951 } 952 953 dev_dbg(component->dev, "jack_type = %d\n", rt5682->jack_type); 954 return rt5682->jack_type; 955 } 956 957 static irqreturn_t rt5682_irq(int irq, void *data) 958 { 959 struct rt5682_priv *rt5682 = data; 960 961 mod_delayed_work(system_power_efficient_wq, 962 &rt5682->jack_detect_work, msecs_to_jiffies(250)); 963 964 return IRQ_HANDLED; 965 } 966 967 static void rt5682_jd_check_handler(struct work_struct *work) 968 { 969 struct rt5682_priv *rt5682 = container_of(work, struct rt5682_priv, 970 jd_check_work.work); 971 972 if (snd_soc_component_read32(rt5682->component, RT5682_AJD1_CTRL) 973 & RT5682_JDH_RS_MASK) { 974 /* jack out */ 975 rt5682->jack_type = rt5682_headset_detect(rt5682->component, 0); 976 977 snd_soc_jack_report(rt5682->hs_jack, rt5682->jack_type, 978 SND_JACK_HEADSET | 979 SND_JACK_BTN_0 | SND_JACK_BTN_1 | 980 SND_JACK_BTN_2 | SND_JACK_BTN_3); 981 } else { 982 schedule_delayed_work(&rt5682->jd_check_work, 500); 983 } 984 } 985 986 static int rt5682_set_jack_detect(struct snd_soc_component *component, 987 struct snd_soc_jack *hs_jack, void *data) 988 { 989 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 990 991 switch (rt5682->pdata.jd_src) { 992 case RT5682_JD1: 993 snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_2, 994 RT5682_EXT_JD_SRC, RT5682_EXT_JD_SRC_MANUAL); 995 snd_soc_component_write(component, RT5682_CBJ_CTRL_1, 0xd042); 996 snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_3, 997 RT5682_CBJ_IN_BUF_EN, RT5682_CBJ_IN_BUF_EN); 998 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1, 999 RT5682_SAR_POW_MASK, RT5682_SAR_POW_EN); 1000 regmap_update_bits(rt5682->regmap, RT5682_GPIO_CTRL_1, 1001 RT5682_GP1_PIN_MASK, RT5682_GP1_PIN_IRQ); 1002 regmap_update_bits(rt5682->regmap, RT5682_RC_CLK_CTRL, 1003 RT5682_POW_IRQ | RT5682_POW_JDH | 1004 RT5682_POW_ANA, RT5682_POW_IRQ | 1005 RT5682_POW_JDH | RT5682_POW_ANA); 1006 regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_2, 1007 RT5682_PWR_JDH | RT5682_PWR_JDL, 1008 RT5682_PWR_JDH | RT5682_PWR_JDL); 1009 regmap_update_bits(rt5682->regmap, RT5682_IRQ_CTRL_2, 1010 RT5682_JD1_EN_MASK | RT5682_JD1_POL_MASK, 1011 RT5682_JD1_EN | RT5682_JD1_POL_NOR); 1012 mod_delayed_work(system_power_efficient_wq, 1013 &rt5682->jack_detect_work, msecs_to_jiffies(250)); 1014 break; 1015 1016 case RT5682_JD_NULL: 1017 regmap_update_bits(rt5682->regmap, RT5682_IRQ_CTRL_2, 1018 RT5682_JD1_EN_MASK, RT5682_JD1_DIS); 1019 regmap_update_bits(rt5682->regmap, RT5682_RC_CLK_CTRL, 1020 RT5682_POW_JDH | RT5682_POW_JDL, 0); 1021 break; 1022 1023 default: 1024 dev_warn(component->dev, "Wrong JD source\n"); 1025 break; 1026 } 1027 1028 rt5682->hs_jack = hs_jack; 1029 1030 return 0; 1031 } 1032 1033 static void rt5682_jack_detect_handler(struct work_struct *work) 1034 { 1035 struct rt5682_priv *rt5682 = 1036 container_of(work, struct rt5682_priv, jack_detect_work.work); 1037 int val, btn_type; 1038 1039 while (!rt5682->component) 1040 usleep_range(10000, 15000); 1041 1042 while (!rt5682->component->card->instantiated) 1043 usleep_range(10000, 15000); 1044 1045 mutex_lock(&rt5682->calibrate_mutex); 1046 1047 val = snd_soc_component_read32(rt5682->component, RT5682_AJD1_CTRL) 1048 & RT5682_JDH_RS_MASK; 1049 if (!val) { 1050 /* jack in */ 1051 if (rt5682->jack_type == 0) { 1052 /* jack was out, report jack type */ 1053 rt5682->jack_type = 1054 rt5682_headset_detect(rt5682->component, 1); 1055 } else { 1056 /* jack is already in, report button event */ 1057 rt5682->jack_type = SND_JACK_HEADSET; 1058 btn_type = rt5682_button_detect(rt5682->component); 1059 /** 1060 * rt5682 can report three kinds of button behavior, 1061 * one click, double click and hold. However, 1062 * currently we will report button pressed/released 1063 * event. So all the three button behaviors are 1064 * treated as button pressed. 1065 */ 1066 switch (btn_type) { 1067 case 0x8000: 1068 case 0x4000: 1069 case 0x2000: 1070 rt5682->jack_type |= SND_JACK_BTN_0; 1071 break; 1072 case 0x1000: 1073 case 0x0800: 1074 case 0x0400: 1075 rt5682->jack_type |= SND_JACK_BTN_1; 1076 break; 1077 case 0x0200: 1078 case 0x0100: 1079 case 0x0080: 1080 rt5682->jack_type |= SND_JACK_BTN_2; 1081 break; 1082 case 0x0040: 1083 case 0x0020: 1084 case 0x0010: 1085 rt5682->jack_type |= SND_JACK_BTN_3; 1086 break; 1087 case 0x0000: /* unpressed */ 1088 break; 1089 default: 1090 btn_type = 0; 1091 dev_err(rt5682->component->dev, 1092 "Unexpected button code 0x%04x\n", 1093 btn_type); 1094 break; 1095 } 1096 } 1097 } else { 1098 /* jack out */ 1099 rt5682->jack_type = rt5682_headset_detect(rt5682->component, 0); 1100 } 1101 1102 snd_soc_jack_report(rt5682->hs_jack, rt5682->jack_type, 1103 SND_JACK_HEADSET | 1104 SND_JACK_BTN_0 | SND_JACK_BTN_1 | 1105 SND_JACK_BTN_2 | SND_JACK_BTN_3); 1106 1107 if (rt5682->jack_type & (SND_JACK_BTN_0 | SND_JACK_BTN_1 | 1108 SND_JACK_BTN_2 | SND_JACK_BTN_3)) 1109 schedule_delayed_work(&rt5682->jd_check_work, 0); 1110 else 1111 cancel_delayed_work_sync(&rt5682->jd_check_work); 1112 1113 mutex_unlock(&rt5682->calibrate_mutex); 1114 } 1115 1116 static const struct snd_kcontrol_new rt5682_snd_controls[] = { 1117 /* DAC Digital Volume */ 1118 SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5682_DAC1_DIG_VOL, 1119 RT5682_L_VOL_SFT + 1, RT5682_R_VOL_SFT + 1, 86, 0, dac_vol_tlv), 1120 1121 /* IN Boost Volume */ 1122 SOC_SINGLE_TLV("CBJ Boost Volume", RT5682_CBJ_BST_CTRL, 1123 RT5682_BST_CBJ_SFT, 8, 0, bst_tlv), 1124 1125 /* ADC Digital Volume Control */ 1126 SOC_DOUBLE("STO1 ADC Capture Switch", RT5682_STO1_ADC_DIG_VOL, 1127 RT5682_L_MUTE_SFT, RT5682_R_MUTE_SFT, 1, 1), 1128 SOC_DOUBLE_TLV("STO1 ADC Capture Volume", RT5682_STO1_ADC_DIG_VOL, 1129 RT5682_L_VOL_SFT + 1, RT5682_R_VOL_SFT + 1, 63, 0, adc_vol_tlv), 1130 1131 /* ADC Boost Volume Control */ 1132 SOC_DOUBLE_TLV("STO1 ADC Boost Gain Volume", RT5682_STO1_ADC_BOOST, 1133 RT5682_STO1_ADC_L_BST_SFT, RT5682_STO1_ADC_R_BST_SFT, 1134 3, 0, adc_bst_tlv), 1135 }; 1136 1137 1138 static int rt5682_div_sel(struct rt5682_priv *rt5682, 1139 int target, const int div[], int size) 1140 { 1141 int i; 1142 1143 if (rt5682->sysclk < target) { 1144 pr_err("sysclk rate %d is too low\n", 1145 rt5682->sysclk); 1146 return 0; 1147 } 1148 1149 for (i = 0; i < size - 1; i++) { 1150 pr_info("div[%d]=%d\n", i, div[i]); 1151 if (target * div[i] == rt5682->sysclk) 1152 return i; 1153 if (target * div[i + 1] > rt5682->sysclk) { 1154 pr_err("can't find div for sysclk %d\n", 1155 rt5682->sysclk); 1156 return i; 1157 } 1158 } 1159 1160 if (target * div[i] < rt5682->sysclk) 1161 pr_err("sysclk rate %d is too high\n", 1162 rt5682->sysclk); 1163 1164 return size - 1; 1165 1166 } 1167 1168 /** 1169 * set_dmic_clk - Set parameter of dmic. 1170 * 1171 * @w: DAPM widget. 1172 * @kcontrol: The kcontrol of this widget. 1173 * @event: Event id. 1174 * 1175 * Choose dmic clock between 1MHz and 3MHz. 1176 * It is better for clock to approximate 3MHz. 1177 */ 1178 static int set_dmic_clk(struct snd_soc_dapm_widget *w, 1179 struct snd_kcontrol *kcontrol, int event) 1180 { 1181 struct snd_soc_component *component = 1182 snd_soc_dapm_to_component(w->dapm); 1183 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 1184 int idx = -EINVAL; 1185 static const int div[] = {2, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, 128}; 1186 1187 idx = rt5682_div_sel(rt5682, 1500000, div, ARRAY_SIZE(div)); 1188 1189 snd_soc_component_update_bits(component, RT5682_DMIC_CTRL_1, 1190 RT5682_DMIC_CLK_MASK, idx << RT5682_DMIC_CLK_SFT); 1191 1192 return 0; 1193 } 1194 1195 static int set_filter_clk(struct snd_soc_dapm_widget *w, 1196 struct snd_kcontrol *kcontrol, int event) 1197 { 1198 struct snd_soc_component *component = 1199 snd_soc_dapm_to_component(w->dapm); 1200 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 1201 int ref, val, reg, sft, mask, idx = -EINVAL; 1202 static const int div_f[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32, 48}; 1203 static const int div_o[] = {1, 2, 4, 6, 8, 12, 16, 24, 32, 48}; 1204 1205 val = snd_soc_component_read32(component, RT5682_GPIO_CTRL_1) & 1206 RT5682_GP4_PIN_MASK; 1207 if (w->shift == RT5682_PWR_ADC_S1F_BIT && 1208 val == RT5682_GP4_PIN_ADCDAT2) 1209 ref = 256 * rt5682->lrck[RT5682_AIF2]; 1210 else 1211 ref = 256 * rt5682->lrck[RT5682_AIF1]; 1212 1213 idx = rt5682_div_sel(rt5682, ref, div_f, ARRAY_SIZE(div_f)); 1214 1215 if (w->shift == RT5682_PWR_ADC_S1F_BIT) { 1216 reg = RT5682_PLL_TRACK_3; 1217 sft = RT5682_ADC_OSR_SFT; 1218 mask = RT5682_ADC_OSR_MASK; 1219 } else { 1220 reg = RT5682_PLL_TRACK_2; 1221 sft = RT5682_DAC_OSR_SFT; 1222 mask = RT5682_DAC_OSR_MASK; 1223 } 1224 1225 snd_soc_component_update_bits(component, reg, 1226 RT5682_FILTER_CLK_DIV_MASK, idx << RT5682_FILTER_CLK_DIV_SFT); 1227 1228 /* select over sample rate */ 1229 for (idx = 0; idx < ARRAY_SIZE(div_o); idx++) { 1230 if (rt5682->sysclk <= 12288000 * div_o[idx]) 1231 break; 1232 } 1233 1234 snd_soc_component_update_bits(component, RT5682_ADDA_CLK_1, 1235 mask, idx << sft); 1236 1237 return 0; 1238 } 1239 1240 static int is_sys_clk_from_pll1(struct snd_soc_dapm_widget *w, 1241 struct snd_soc_dapm_widget *sink) 1242 { 1243 unsigned int val; 1244 struct snd_soc_component *component = 1245 snd_soc_dapm_to_component(w->dapm); 1246 1247 val = snd_soc_component_read32(component, RT5682_GLB_CLK); 1248 val &= RT5682_SCLK_SRC_MASK; 1249 if (val == RT5682_SCLK_SRC_PLL1) 1250 return 1; 1251 else 1252 return 0; 1253 } 1254 1255 static int is_using_asrc(struct snd_soc_dapm_widget *w, 1256 struct snd_soc_dapm_widget *sink) 1257 { 1258 unsigned int reg, shift, val; 1259 struct snd_soc_component *component = 1260 snd_soc_dapm_to_component(w->dapm); 1261 1262 switch (w->shift) { 1263 case RT5682_ADC_STO1_ASRC_SFT: 1264 reg = RT5682_PLL_TRACK_3; 1265 shift = RT5682_FILTER_CLK_SEL_SFT; 1266 break; 1267 case RT5682_DAC_STO1_ASRC_SFT: 1268 reg = RT5682_PLL_TRACK_2; 1269 shift = RT5682_FILTER_CLK_SEL_SFT; 1270 break; 1271 default: 1272 return 0; 1273 } 1274 1275 val = (snd_soc_component_read32(component, reg) >> shift) & 0xf; 1276 switch (val) { 1277 case RT5682_CLK_SEL_I2S1_ASRC: 1278 case RT5682_CLK_SEL_I2S2_ASRC: 1279 return 1; 1280 default: 1281 return 0; 1282 } 1283 1284 } 1285 1286 /* Digital Mixer */ 1287 static const struct snd_kcontrol_new rt5682_sto1_adc_l_mix[] = { 1288 SOC_DAPM_SINGLE("ADC1 Switch", RT5682_STO1_ADC_MIXER, 1289 RT5682_M_STO1_ADC_L1_SFT, 1, 1), 1290 SOC_DAPM_SINGLE("ADC2 Switch", RT5682_STO1_ADC_MIXER, 1291 RT5682_M_STO1_ADC_L2_SFT, 1, 1), 1292 }; 1293 1294 static const struct snd_kcontrol_new rt5682_sto1_adc_r_mix[] = { 1295 SOC_DAPM_SINGLE("ADC1 Switch", RT5682_STO1_ADC_MIXER, 1296 RT5682_M_STO1_ADC_R1_SFT, 1, 1), 1297 SOC_DAPM_SINGLE("ADC2 Switch", RT5682_STO1_ADC_MIXER, 1298 RT5682_M_STO1_ADC_R2_SFT, 1, 1), 1299 }; 1300 1301 static const struct snd_kcontrol_new rt5682_dac_l_mix[] = { 1302 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5682_AD_DA_MIXER, 1303 RT5682_M_ADCMIX_L_SFT, 1, 1), 1304 SOC_DAPM_SINGLE("DAC1 Switch", RT5682_AD_DA_MIXER, 1305 RT5682_M_DAC1_L_SFT, 1, 1), 1306 }; 1307 1308 static const struct snd_kcontrol_new rt5682_dac_r_mix[] = { 1309 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5682_AD_DA_MIXER, 1310 RT5682_M_ADCMIX_R_SFT, 1, 1), 1311 SOC_DAPM_SINGLE("DAC1 Switch", RT5682_AD_DA_MIXER, 1312 RT5682_M_DAC1_R_SFT, 1, 1), 1313 }; 1314 1315 static const struct snd_kcontrol_new rt5682_sto1_dac_l_mix[] = { 1316 SOC_DAPM_SINGLE("DAC L1 Switch", RT5682_STO1_DAC_MIXER, 1317 RT5682_M_DAC_L1_STO_L_SFT, 1, 1), 1318 SOC_DAPM_SINGLE("DAC R1 Switch", RT5682_STO1_DAC_MIXER, 1319 RT5682_M_DAC_R1_STO_L_SFT, 1, 1), 1320 }; 1321 1322 static const struct snd_kcontrol_new rt5682_sto1_dac_r_mix[] = { 1323 SOC_DAPM_SINGLE("DAC L1 Switch", RT5682_STO1_DAC_MIXER, 1324 RT5682_M_DAC_L1_STO_R_SFT, 1, 1), 1325 SOC_DAPM_SINGLE("DAC R1 Switch", RT5682_STO1_DAC_MIXER, 1326 RT5682_M_DAC_R1_STO_R_SFT, 1, 1), 1327 }; 1328 1329 /* Analog Input Mixer */ 1330 static const struct snd_kcontrol_new rt5682_rec1_l_mix[] = { 1331 SOC_DAPM_SINGLE("CBJ Switch", RT5682_REC_MIXER, 1332 RT5682_M_CBJ_RM1_L_SFT, 1, 1), 1333 }; 1334 1335 /* STO1 ADC1 Source */ 1336 /* MX-26 [13] [5] */ 1337 static const char * const rt5682_sto1_adc1_src[] = { 1338 "DAC MIX", "ADC" 1339 }; 1340 1341 static SOC_ENUM_SINGLE_DECL( 1342 rt5682_sto1_adc1l_enum, RT5682_STO1_ADC_MIXER, 1343 RT5682_STO1_ADC1L_SRC_SFT, rt5682_sto1_adc1_src); 1344 1345 static const struct snd_kcontrol_new rt5682_sto1_adc1l_mux = 1346 SOC_DAPM_ENUM("Stereo1 ADC1L Source", rt5682_sto1_adc1l_enum); 1347 1348 static SOC_ENUM_SINGLE_DECL( 1349 rt5682_sto1_adc1r_enum, RT5682_STO1_ADC_MIXER, 1350 RT5682_STO1_ADC1R_SRC_SFT, rt5682_sto1_adc1_src); 1351 1352 static const struct snd_kcontrol_new rt5682_sto1_adc1r_mux = 1353 SOC_DAPM_ENUM("Stereo1 ADC1L Source", rt5682_sto1_adc1r_enum); 1354 1355 /* STO1 ADC Source */ 1356 /* MX-26 [11:10] [3:2] */ 1357 static const char * const rt5682_sto1_adc_src[] = { 1358 "ADC1 L", "ADC1 R" 1359 }; 1360 1361 static SOC_ENUM_SINGLE_DECL( 1362 rt5682_sto1_adcl_enum, RT5682_STO1_ADC_MIXER, 1363 RT5682_STO1_ADCL_SRC_SFT, rt5682_sto1_adc_src); 1364 1365 static const struct snd_kcontrol_new rt5682_sto1_adcl_mux = 1366 SOC_DAPM_ENUM("Stereo1 ADCL Source", rt5682_sto1_adcl_enum); 1367 1368 static SOC_ENUM_SINGLE_DECL( 1369 rt5682_sto1_adcr_enum, RT5682_STO1_ADC_MIXER, 1370 RT5682_STO1_ADCR_SRC_SFT, rt5682_sto1_adc_src); 1371 1372 static const struct snd_kcontrol_new rt5682_sto1_adcr_mux = 1373 SOC_DAPM_ENUM("Stereo1 ADCR Source", rt5682_sto1_adcr_enum); 1374 1375 /* STO1 ADC2 Source */ 1376 /* MX-26 [12] [4] */ 1377 static const char * const rt5682_sto1_adc2_src[] = { 1378 "DAC MIX", "DMIC" 1379 }; 1380 1381 static SOC_ENUM_SINGLE_DECL( 1382 rt5682_sto1_adc2l_enum, RT5682_STO1_ADC_MIXER, 1383 RT5682_STO1_ADC2L_SRC_SFT, rt5682_sto1_adc2_src); 1384 1385 static const struct snd_kcontrol_new rt5682_sto1_adc2l_mux = 1386 SOC_DAPM_ENUM("Stereo1 ADC2L Source", rt5682_sto1_adc2l_enum); 1387 1388 static SOC_ENUM_SINGLE_DECL( 1389 rt5682_sto1_adc2r_enum, RT5682_STO1_ADC_MIXER, 1390 RT5682_STO1_ADC2R_SRC_SFT, rt5682_sto1_adc2_src); 1391 1392 static const struct snd_kcontrol_new rt5682_sto1_adc2r_mux = 1393 SOC_DAPM_ENUM("Stereo1 ADC2R Source", rt5682_sto1_adc2r_enum); 1394 1395 /* MX-79 [6:4] I2S1 ADC data location */ 1396 static const unsigned int rt5682_if1_adc_slot_values[] = { 1397 0, 1398 2, 1399 4, 1400 6, 1401 }; 1402 1403 static const char * const rt5682_if1_adc_slot_src[] = { 1404 "Slot 0", "Slot 2", "Slot 4", "Slot 6" 1405 }; 1406 1407 static SOC_VALUE_ENUM_SINGLE_DECL(rt5682_if1_adc_slot_enum, 1408 RT5682_TDM_CTRL, RT5682_TDM_ADC_LCA_SFT, RT5682_TDM_ADC_LCA_MASK, 1409 rt5682_if1_adc_slot_src, rt5682_if1_adc_slot_values); 1410 1411 static const struct snd_kcontrol_new rt5682_if1_adc_slot_mux = 1412 SOC_DAPM_ENUM("IF1 ADC Slot location", rt5682_if1_adc_slot_enum); 1413 1414 /* Analog DAC L1 Source, Analog DAC R1 Source*/ 1415 /* MX-2B [4], MX-2B [0]*/ 1416 static const char * const rt5682_alg_dac1_src[] = { 1417 "Stereo1 DAC Mixer", "DAC1" 1418 }; 1419 1420 static SOC_ENUM_SINGLE_DECL( 1421 rt5682_alg_dac_l1_enum, RT5682_A_DAC1_MUX, 1422 RT5682_A_DACL1_SFT, rt5682_alg_dac1_src); 1423 1424 static const struct snd_kcontrol_new rt5682_alg_dac_l1_mux = 1425 SOC_DAPM_ENUM("Analog DAC L1 Source", rt5682_alg_dac_l1_enum); 1426 1427 static SOC_ENUM_SINGLE_DECL( 1428 rt5682_alg_dac_r1_enum, RT5682_A_DAC1_MUX, 1429 RT5682_A_DACR1_SFT, rt5682_alg_dac1_src); 1430 1431 static const struct snd_kcontrol_new rt5682_alg_dac_r1_mux = 1432 SOC_DAPM_ENUM("Analog DAC R1 Source", rt5682_alg_dac_r1_enum); 1433 1434 /* Out Switch */ 1435 static const struct snd_kcontrol_new hpol_switch = 1436 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5682_HP_CTRL_1, 1437 RT5682_L_MUTE_SFT, 1, 1); 1438 static const struct snd_kcontrol_new hpor_switch = 1439 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5682_HP_CTRL_1, 1440 RT5682_R_MUTE_SFT, 1, 1); 1441 1442 static int rt5682_charge_pump_event(struct snd_soc_dapm_widget *w, 1443 struct snd_kcontrol *kcontrol, int event) 1444 { 1445 struct snd_soc_component *component = 1446 snd_soc_dapm_to_component(w->dapm); 1447 1448 switch (event) { 1449 case SND_SOC_DAPM_PRE_PMU: 1450 snd_soc_component_update_bits(component, 1451 RT5682_HP_CHARGE_PUMP_1, RT5682_PM_HP_MASK, RT5682_PM_HP_HV); 1452 break; 1453 case SND_SOC_DAPM_POST_PMD: 1454 snd_soc_component_update_bits(component, 1455 RT5682_HP_CHARGE_PUMP_1, RT5682_PM_HP_MASK, RT5682_PM_HP_LV); 1456 break; 1457 default: 1458 return 0; 1459 } 1460 1461 return 0; 1462 } 1463 1464 static int rt5682_hp_event(struct snd_soc_dapm_widget *w, 1465 struct snd_kcontrol *kcontrol, int event) 1466 { 1467 struct snd_soc_component *component = 1468 snd_soc_dapm_to_component(w->dapm); 1469 1470 switch (event) { 1471 case SND_SOC_DAPM_PRE_PMU: 1472 snd_soc_component_write(component, 1473 RT5682_HP_LOGIC_CTRL_2, 0x0012); 1474 snd_soc_component_write(component, 1475 RT5682_HP_CTRL_2, 0x6000); 1476 snd_soc_component_update_bits(component, 1477 RT5682_DEPOP_1, 0x60, 0x60); 1478 snd_soc_component_update_bits(component, 1479 RT5682_DAC_ADC_DIG_VOL1, 0x00c0, 0x0080); 1480 break; 1481 1482 case SND_SOC_DAPM_POST_PMD: 1483 snd_soc_component_update_bits(component, 1484 RT5682_DEPOP_1, 0x60, 0x0); 1485 snd_soc_component_write(component, 1486 RT5682_HP_CTRL_2, 0x0000); 1487 snd_soc_component_update_bits(component, 1488 RT5682_DAC_ADC_DIG_VOL1, 0x00c0, 0x0000); 1489 break; 1490 1491 default: 1492 return 0; 1493 } 1494 1495 return 0; 1496 1497 } 1498 1499 static int set_dmic_power(struct snd_soc_dapm_widget *w, 1500 struct snd_kcontrol *kcontrol, int event) 1501 { 1502 switch (event) { 1503 case SND_SOC_DAPM_POST_PMU: 1504 /*Add delay to avoid pop noise*/ 1505 msleep(150); 1506 break; 1507 1508 default: 1509 return 0; 1510 } 1511 1512 return 0; 1513 } 1514 1515 static int rt5655_set_verf(struct snd_soc_dapm_widget *w, 1516 struct snd_kcontrol *kcontrol, int event) 1517 { 1518 struct snd_soc_component *component = 1519 snd_soc_dapm_to_component(w->dapm); 1520 1521 switch (event) { 1522 case SND_SOC_DAPM_PRE_PMU: 1523 switch (w->shift) { 1524 case RT5682_PWR_VREF1_BIT: 1525 snd_soc_component_update_bits(component, 1526 RT5682_PWR_ANLG_1, RT5682_PWR_FV1, 0); 1527 break; 1528 1529 case RT5682_PWR_VREF2_BIT: 1530 snd_soc_component_update_bits(component, 1531 RT5682_PWR_ANLG_1, RT5682_PWR_FV2, 0); 1532 break; 1533 1534 default: 1535 break; 1536 } 1537 break; 1538 1539 case SND_SOC_DAPM_POST_PMU: 1540 usleep_range(15000, 20000); 1541 switch (w->shift) { 1542 case RT5682_PWR_VREF1_BIT: 1543 snd_soc_component_update_bits(component, 1544 RT5682_PWR_ANLG_1, RT5682_PWR_FV1, 1545 RT5682_PWR_FV1); 1546 break; 1547 1548 case RT5682_PWR_VREF2_BIT: 1549 snd_soc_component_update_bits(component, 1550 RT5682_PWR_ANLG_1, RT5682_PWR_FV2, 1551 RT5682_PWR_FV2); 1552 break; 1553 1554 default: 1555 break; 1556 } 1557 break; 1558 1559 default: 1560 return 0; 1561 } 1562 1563 return 0; 1564 } 1565 1566 static const unsigned int rt5682_adcdat_pin_values[] = { 1567 1, 1568 3, 1569 }; 1570 1571 static const char * const rt5682_adcdat_pin_select[] = { 1572 "ADCDAT1", 1573 "ADCDAT2", 1574 }; 1575 1576 static SOC_VALUE_ENUM_SINGLE_DECL(rt5682_adcdat_pin_enum, 1577 RT5682_GPIO_CTRL_1, RT5682_GP4_PIN_SFT, RT5682_GP4_PIN_MASK, 1578 rt5682_adcdat_pin_select, rt5682_adcdat_pin_values); 1579 1580 static const struct snd_kcontrol_new rt5682_adcdat_pin_ctrl = 1581 SOC_DAPM_ENUM("ADCDAT", rt5682_adcdat_pin_enum); 1582 1583 static const struct snd_soc_dapm_widget rt5682_dapm_widgets[] = { 1584 SND_SOC_DAPM_SUPPLY("LDO2", RT5682_PWR_ANLG_3, RT5682_PWR_LDO2_BIT, 1585 0, NULL, 0), 1586 SND_SOC_DAPM_SUPPLY("PLL1", RT5682_PWR_ANLG_3, RT5682_PWR_PLL_BIT, 1587 0, NULL, 0), 1588 SND_SOC_DAPM_SUPPLY("PLL2B", RT5682_PWR_ANLG_3, RT5682_PWR_PLL2B_BIT, 1589 0, NULL, 0), 1590 SND_SOC_DAPM_SUPPLY("PLL2F", RT5682_PWR_ANLG_3, RT5682_PWR_PLL2F_BIT, 1591 0, NULL, 0), 1592 SND_SOC_DAPM_SUPPLY("Vref1", RT5682_PWR_ANLG_1, RT5682_PWR_VREF1_BIT, 0, 1593 rt5655_set_verf, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), 1594 SND_SOC_DAPM_SUPPLY("Vref2", RT5682_PWR_ANLG_1, RT5682_PWR_VREF2_BIT, 0, 1595 rt5655_set_verf, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), 1596 1597 /* ASRC */ 1598 SND_SOC_DAPM_SUPPLY_S("DAC STO1 ASRC", 1, RT5682_PLL_TRACK_1, 1599 RT5682_DAC_STO1_ASRC_SFT, 0, NULL, 0), 1600 SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5682_PLL_TRACK_1, 1601 RT5682_ADC_STO1_ASRC_SFT, 0, NULL, 0), 1602 SND_SOC_DAPM_SUPPLY_S("AD ASRC", 1, RT5682_PLL_TRACK_1, 1603 RT5682_AD_ASRC_SFT, 0, NULL, 0), 1604 SND_SOC_DAPM_SUPPLY_S("DA ASRC", 1, RT5682_PLL_TRACK_1, 1605 RT5682_DA_ASRC_SFT, 0, NULL, 0), 1606 SND_SOC_DAPM_SUPPLY_S("DMIC ASRC", 1, RT5682_PLL_TRACK_1, 1607 RT5682_DMIC_ASRC_SFT, 0, NULL, 0), 1608 1609 /* Input Side */ 1610 SND_SOC_DAPM_SUPPLY("MICBIAS1", RT5682_PWR_ANLG_2, RT5682_PWR_MB1_BIT, 1611 0, NULL, 0), 1612 SND_SOC_DAPM_SUPPLY("MICBIAS2", RT5682_PWR_ANLG_2, RT5682_PWR_MB2_BIT, 1613 0, NULL, 0), 1614 1615 /* Input Lines */ 1616 SND_SOC_DAPM_INPUT("DMIC L1"), 1617 SND_SOC_DAPM_INPUT("DMIC R1"), 1618 1619 SND_SOC_DAPM_INPUT("IN1P"), 1620 1621 SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0, 1622 set_dmic_clk, SND_SOC_DAPM_PRE_PMU), 1623 SND_SOC_DAPM_SUPPLY("DMIC1 Power", RT5682_DMIC_CTRL_1, 1624 RT5682_DMIC_1_EN_SFT, 0, set_dmic_power, SND_SOC_DAPM_POST_PMU), 1625 1626 /* Boost */ 1627 SND_SOC_DAPM_PGA("BST1 CBJ", SND_SOC_NOPM, 1628 0, 0, NULL, 0), 1629 1630 SND_SOC_DAPM_SUPPLY("CBJ Power", RT5682_PWR_ANLG_3, 1631 RT5682_PWR_CBJ_BIT, 0, NULL, 0), 1632 1633 /* REC Mixer */ 1634 SND_SOC_DAPM_MIXER("RECMIX1L", SND_SOC_NOPM, 0, 0, rt5682_rec1_l_mix, 1635 ARRAY_SIZE(rt5682_rec1_l_mix)), 1636 SND_SOC_DAPM_SUPPLY("RECMIX1L Power", RT5682_PWR_ANLG_2, 1637 RT5682_PWR_RM1_L_BIT, 0, NULL, 0), 1638 1639 /* ADCs */ 1640 SND_SOC_DAPM_ADC("ADC1 L", NULL, SND_SOC_NOPM, 0, 0), 1641 SND_SOC_DAPM_ADC("ADC1 R", NULL, SND_SOC_NOPM, 0, 0), 1642 1643 SND_SOC_DAPM_SUPPLY("ADC1 L Power", RT5682_PWR_DIG_1, 1644 RT5682_PWR_ADC_L1_BIT, 0, NULL, 0), 1645 SND_SOC_DAPM_SUPPLY("ADC1 R Power", RT5682_PWR_DIG_1, 1646 RT5682_PWR_ADC_R1_BIT, 0, NULL, 0), 1647 SND_SOC_DAPM_SUPPLY("ADC1 clock", RT5682_CHOP_ADC, 1648 RT5682_CKGEN_ADC1_SFT, 0, NULL, 0), 1649 1650 /* ADC Mux */ 1651 SND_SOC_DAPM_MUX("Stereo1 ADC L1 Mux", SND_SOC_NOPM, 0, 0, 1652 &rt5682_sto1_adc1l_mux), 1653 SND_SOC_DAPM_MUX("Stereo1 ADC R1 Mux", SND_SOC_NOPM, 0, 0, 1654 &rt5682_sto1_adc1r_mux), 1655 SND_SOC_DAPM_MUX("Stereo1 ADC L2 Mux", SND_SOC_NOPM, 0, 0, 1656 &rt5682_sto1_adc2l_mux), 1657 SND_SOC_DAPM_MUX("Stereo1 ADC R2 Mux", SND_SOC_NOPM, 0, 0, 1658 &rt5682_sto1_adc2r_mux), 1659 SND_SOC_DAPM_MUX("Stereo1 ADC L Mux", SND_SOC_NOPM, 0, 0, 1660 &rt5682_sto1_adcl_mux), 1661 SND_SOC_DAPM_MUX("Stereo1 ADC R Mux", SND_SOC_NOPM, 0, 0, 1662 &rt5682_sto1_adcr_mux), 1663 SND_SOC_DAPM_MUX("IF1_ADC Mux", SND_SOC_NOPM, 0, 0, 1664 &rt5682_if1_adc_slot_mux), 1665 1666 /* ADC Mixer */ 1667 SND_SOC_DAPM_SUPPLY("ADC Stereo1 Filter", RT5682_PWR_DIG_2, 1668 RT5682_PWR_ADC_S1F_BIT, 0, set_filter_clk, 1669 SND_SOC_DAPM_PRE_PMU), 1670 SND_SOC_DAPM_MIXER("Stereo1 ADC MIXL", RT5682_STO1_ADC_DIG_VOL, 1671 RT5682_L_MUTE_SFT, 1, rt5682_sto1_adc_l_mix, 1672 ARRAY_SIZE(rt5682_sto1_adc_l_mix)), 1673 SND_SOC_DAPM_MIXER("Stereo1 ADC MIXR", RT5682_STO1_ADC_DIG_VOL, 1674 RT5682_R_MUTE_SFT, 1, rt5682_sto1_adc_r_mix, 1675 ARRAY_SIZE(rt5682_sto1_adc_r_mix)), 1676 SND_SOC_DAPM_SUPPLY("BTN Detection Mode", RT5682_SAR_IL_CMD_1, 1677 14, 1, NULL, 0), 1678 1679 /* ADC PGA */ 1680 SND_SOC_DAPM_PGA("Stereo1 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 1681 1682 /* Digital Interface */ 1683 SND_SOC_DAPM_SUPPLY("I2S1", RT5682_PWR_DIG_1, RT5682_PWR_I2S1_BIT, 1684 0, NULL, 0), 1685 SND_SOC_DAPM_SUPPLY("I2S2", RT5682_PWR_DIG_1, RT5682_PWR_I2S2_BIT, 1686 0, NULL, 0), 1687 SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0), 1688 SND_SOC_DAPM_PGA("IF1 DAC1 L", SND_SOC_NOPM, 0, 0, NULL, 0), 1689 SND_SOC_DAPM_PGA("IF1 DAC1 R", SND_SOC_NOPM, 0, 0, NULL, 0), 1690 1691 /* Digital Interface Select */ 1692 SND_SOC_DAPM_MUX("IF1 01 ADC Swap Mux", SND_SOC_NOPM, 0, 0, 1693 &rt5682_if1_01_adc_swap_mux), 1694 SND_SOC_DAPM_MUX("IF1 23 ADC Swap Mux", SND_SOC_NOPM, 0, 0, 1695 &rt5682_if1_23_adc_swap_mux), 1696 SND_SOC_DAPM_MUX("IF1 45 ADC Swap Mux", SND_SOC_NOPM, 0, 0, 1697 &rt5682_if1_45_adc_swap_mux), 1698 SND_SOC_DAPM_MUX("IF1 67 ADC Swap Mux", SND_SOC_NOPM, 0, 0, 1699 &rt5682_if1_67_adc_swap_mux), 1700 SND_SOC_DAPM_MUX("IF2 ADC Swap Mux", SND_SOC_NOPM, 0, 0, 1701 &rt5682_if2_adc_swap_mux), 1702 1703 SND_SOC_DAPM_MUX("ADCDAT Mux", SND_SOC_NOPM, 0, 0, 1704 &rt5682_adcdat_pin_ctrl), 1705 1706 /* Audio Interface */ 1707 SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, 1708 RT5682_I2S1_SDP, RT5682_SEL_ADCDAT_SFT, 1), 1709 SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, 1710 RT5682_I2S2_SDP, RT5682_I2S2_PIN_CFG_SFT, 1), 1711 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0), 1712 1713 /* Output Side */ 1714 /* DAC mixer before sound effect */ 1715 SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0, 1716 rt5682_dac_l_mix, ARRAY_SIZE(rt5682_dac_l_mix)), 1717 SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0, 1718 rt5682_dac_r_mix, ARRAY_SIZE(rt5682_dac_r_mix)), 1719 1720 /* DAC channel Mux */ 1721 SND_SOC_DAPM_MUX("DAC L1 Source", SND_SOC_NOPM, 0, 0, 1722 &rt5682_alg_dac_l1_mux), 1723 SND_SOC_DAPM_MUX("DAC R1 Source", SND_SOC_NOPM, 0, 0, 1724 &rt5682_alg_dac_r1_mux), 1725 1726 /* DAC Mixer */ 1727 SND_SOC_DAPM_SUPPLY("DAC Stereo1 Filter", RT5682_PWR_DIG_2, 1728 RT5682_PWR_DAC_S1F_BIT, 0, set_filter_clk, 1729 SND_SOC_DAPM_PRE_PMU), 1730 SND_SOC_DAPM_MIXER("Stereo1 DAC MIXL", SND_SOC_NOPM, 0, 0, 1731 rt5682_sto1_dac_l_mix, ARRAY_SIZE(rt5682_sto1_dac_l_mix)), 1732 SND_SOC_DAPM_MIXER("Stereo1 DAC MIXR", SND_SOC_NOPM, 0, 0, 1733 rt5682_sto1_dac_r_mix, ARRAY_SIZE(rt5682_sto1_dac_r_mix)), 1734 1735 /* DACs */ 1736 SND_SOC_DAPM_DAC("DAC L1", NULL, RT5682_PWR_DIG_1, 1737 RT5682_PWR_DAC_L1_BIT, 0), 1738 SND_SOC_DAPM_DAC("DAC R1", NULL, RT5682_PWR_DIG_1, 1739 RT5682_PWR_DAC_R1_BIT, 0), 1740 SND_SOC_DAPM_SUPPLY_S("DAC 1 Clock", 3, RT5682_CHOP_DAC, 1741 RT5682_CKGEN_DAC1_SFT, 0, NULL, 0), 1742 1743 /* HPO */ 1744 SND_SOC_DAPM_PGA_S("HP Amp", 1, SND_SOC_NOPM, 0, 0, rt5682_hp_event, 1745 SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_PRE_PMU), 1746 1747 SND_SOC_DAPM_SUPPLY("HP Amp L", RT5682_PWR_ANLG_1, 1748 RT5682_PWR_HA_L_BIT, 0, NULL, 0), 1749 SND_SOC_DAPM_SUPPLY("HP Amp R", RT5682_PWR_ANLG_1, 1750 RT5682_PWR_HA_R_BIT, 0, NULL, 0), 1751 SND_SOC_DAPM_SUPPLY_S("Charge Pump", 1, RT5682_DEPOP_1, 1752 RT5682_PUMP_EN_SFT, 0, rt5682_charge_pump_event, 1753 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 1754 SND_SOC_DAPM_SUPPLY_S("Capless", 2, RT5682_DEPOP_1, 1755 RT5682_CAPLESS_EN_SFT, 0, NULL, 0), 1756 1757 SND_SOC_DAPM_SWITCH("HPOL Playback", SND_SOC_NOPM, 0, 0, 1758 &hpol_switch), 1759 SND_SOC_DAPM_SWITCH("HPOR Playback", SND_SOC_NOPM, 0, 0, 1760 &hpor_switch), 1761 1762 /* CLK DET */ 1763 SND_SOC_DAPM_SUPPLY("CLKDET SYS", RT5682_CLK_DET, 1764 RT5682_SYS_CLK_DET_SFT, 0, NULL, 0), 1765 SND_SOC_DAPM_SUPPLY("CLKDET PLL1", RT5682_CLK_DET, 1766 RT5682_PLL1_CLK_DET_SFT, 0, NULL, 0), 1767 SND_SOC_DAPM_SUPPLY("CLKDET PLL2", RT5682_CLK_DET, 1768 RT5682_PLL2_CLK_DET_SFT, 0, NULL, 0), 1769 SND_SOC_DAPM_SUPPLY("CLKDET", RT5682_CLK_DET, 1770 RT5682_POW_CLK_DET_SFT, 0, NULL, 0), 1771 1772 /* Output Lines */ 1773 SND_SOC_DAPM_OUTPUT("HPOL"), 1774 SND_SOC_DAPM_OUTPUT("HPOR"), 1775 1776 }; 1777 1778 static const struct snd_soc_dapm_route rt5682_dapm_routes[] = { 1779 /*PLL*/ 1780 {"ADC Stereo1 Filter", NULL, "PLL1", is_sys_clk_from_pll1}, 1781 {"DAC Stereo1 Filter", NULL, "PLL1", is_sys_clk_from_pll1}, 1782 1783 /*ASRC*/ 1784 {"ADC Stereo1 Filter", NULL, "ADC STO1 ASRC", is_using_asrc}, 1785 {"DAC Stereo1 Filter", NULL, "DAC STO1 ASRC", is_using_asrc}, 1786 {"ADC STO1 ASRC", NULL, "AD ASRC"}, 1787 {"ADC STO1 ASRC", NULL, "DA ASRC"}, 1788 {"ADC STO1 ASRC", NULL, "CLKDET"}, 1789 {"DAC STO1 ASRC", NULL, "AD ASRC"}, 1790 {"DAC STO1 ASRC", NULL, "DA ASRC"}, 1791 {"DAC STO1 ASRC", NULL, "CLKDET"}, 1792 1793 /*Vref*/ 1794 {"MICBIAS1", NULL, "Vref1"}, 1795 {"MICBIAS1", NULL, "Vref2"}, 1796 {"MICBIAS2", NULL, "Vref1"}, 1797 {"MICBIAS2", NULL, "Vref2"}, 1798 1799 {"CLKDET SYS", NULL, "CLKDET"}, 1800 1801 {"IN1P", NULL, "LDO2"}, 1802 1803 {"BST1 CBJ", NULL, "IN1P"}, 1804 {"BST1 CBJ", NULL, "CBJ Power"}, 1805 {"CBJ Power", NULL, "Vref2"}, 1806 1807 {"RECMIX1L", "CBJ Switch", "BST1 CBJ"}, 1808 {"RECMIX1L", NULL, "RECMIX1L Power"}, 1809 1810 {"ADC1 L", NULL, "RECMIX1L"}, 1811 {"ADC1 L", NULL, "ADC1 L Power"}, 1812 {"ADC1 L", NULL, "ADC1 clock"}, 1813 1814 {"DMIC L1", NULL, "DMIC CLK"}, 1815 {"DMIC L1", NULL, "DMIC1 Power"}, 1816 {"DMIC R1", NULL, "DMIC CLK"}, 1817 {"DMIC R1", NULL, "DMIC1 Power"}, 1818 {"DMIC CLK", NULL, "DMIC ASRC"}, 1819 1820 {"Stereo1 ADC L Mux", "ADC1 L", "ADC1 L"}, 1821 {"Stereo1 ADC L Mux", "ADC1 R", "ADC1 R"}, 1822 {"Stereo1 ADC R Mux", "ADC1 L", "ADC1 L"}, 1823 {"Stereo1 ADC R Mux", "ADC1 R", "ADC1 R"}, 1824 1825 {"Stereo1 ADC L1 Mux", "ADC", "Stereo1 ADC L Mux"}, 1826 {"Stereo1 ADC L1 Mux", "DAC MIX", "Stereo1 DAC MIXL"}, 1827 {"Stereo1 ADC L2 Mux", "DMIC", "DMIC L1"}, 1828 {"Stereo1 ADC L2 Mux", "DAC MIX", "Stereo1 DAC MIXL"}, 1829 1830 {"Stereo1 ADC R1 Mux", "ADC", "Stereo1 ADC R Mux"}, 1831 {"Stereo1 ADC R1 Mux", "DAC MIX", "Stereo1 DAC MIXR"}, 1832 {"Stereo1 ADC R2 Mux", "DMIC", "DMIC R1"}, 1833 {"Stereo1 ADC R2 Mux", "DAC MIX", "Stereo1 DAC MIXR"}, 1834 1835 {"Stereo1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC L1 Mux"}, 1836 {"Stereo1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC L2 Mux"}, 1837 {"Stereo1 ADC MIXL", NULL, "ADC Stereo1 Filter"}, 1838 1839 {"Stereo1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC R1 Mux"}, 1840 {"Stereo1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC R2 Mux"}, 1841 {"Stereo1 ADC MIXR", NULL, "ADC Stereo1 Filter"}, 1842 1843 {"ADC Stereo1 Filter", NULL, "BTN Detection Mode"}, 1844 1845 {"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXL"}, 1846 {"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXR"}, 1847 1848 {"IF1 01 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"}, 1849 {"IF1 01 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"}, 1850 {"IF1 01 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"}, 1851 {"IF1 01 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"}, 1852 {"IF1 23 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"}, 1853 {"IF1 23 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"}, 1854 {"IF1 23 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"}, 1855 {"IF1 23 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"}, 1856 {"IF1 45 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"}, 1857 {"IF1 45 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"}, 1858 {"IF1 45 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"}, 1859 {"IF1 45 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"}, 1860 {"IF1 67 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"}, 1861 {"IF1 67 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"}, 1862 {"IF1 67 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"}, 1863 {"IF1 67 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"}, 1864 1865 {"IF1_ADC Mux", "Slot 0", "IF1 01 ADC Swap Mux"}, 1866 {"IF1_ADC Mux", "Slot 2", "IF1 23 ADC Swap Mux"}, 1867 {"IF1_ADC Mux", "Slot 4", "IF1 45 ADC Swap Mux"}, 1868 {"IF1_ADC Mux", "Slot 6", "IF1 67 ADC Swap Mux"}, 1869 {"IF1_ADC Mux", NULL, "I2S1"}, 1870 {"ADCDAT Mux", "ADCDAT1", "IF1_ADC Mux"}, 1871 {"AIF1TX", NULL, "ADCDAT Mux"}, 1872 {"IF2 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"}, 1873 {"IF2 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"}, 1874 {"IF2 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"}, 1875 {"IF2 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"}, 1876 {"ADCDAT Mux", "ADCDAT2", "IF2 ADC Swap Mux"}, 1877 {"AIF2TX", NULL, "ADCDAT Mux"}, 1878 1879 {"IF1 DAC1 L", NULL, "AIF1RX"}, 1880 {"IF1 DAC1 L", NULL, "I2S1"}, 1881 {"IF1 DAC1 L", NULL, "DAC Stereo1 Filter"}, 1882 {"IF1 DAC1 R", NULL, "AIF1RX"}, 1883 {"IF1 DAC1 R", NULL, "I2S1"}, 1884 {"IF1 DAC1 R", NULL, "DAC Stereo1 Filter"}, 1885 1886 {"DAC1 MIXL", "Stereo ADC Switch", "Stereo1 ADC MIXL"}, 1887 {"DAC1 MIXL", "DAC1 Switch", "IF1 DAC1 L"}, 1888 {"DAC1 MIXR", "Stereo ADC Switch", "Stereo1 ADC MIXR"}, 1889 {"DAC1 MIXR", "DAC1 Switch", "IF1 DAC1 R"}, 1890 1891 {"Stereo1 DAC MIXL", "DAC L1 Switch", "DAC1 MIXL"}, 1892 {"Stereo1 DAC MIXL", "DAC R1 Switch", "DAC1 MIXR"}, 1893 1894 {"Stereo1 DAC MIXR", "DAC R1 Switch", "DAC1 MIXR"}, 1895 {"Stereo1 DAC MIXR", "DAC L1 Switch", "DAC1 MIXL"}, 1896 1897 {"DAC L1 Source", "DAC1", "DAC1 MIXL"}, 1898 {"DAC L1 Source", "Stereo1 DAC Mixer", "Stereo1 DAC MIXL"}, 1899 {"DAC R1 Source", "DAC1", "DAC1 MIXR"}, 1900 {"DAC R1 Source", "Stereo1 DAC Mixer", "Stereo1 DAC MIXR"}, 1901 1902 {"DAC L1", NULL, "DAC L1 Source"}, 1903 {"DAC R1", NULL, "DAC R1 Source"}, 1904 1905 {"DAC L1", NULL, "DAC 1 Clock"}, 1906 {"DAC R1", NULL, "DAC 1 Clock"}, 1907 1908 {"HP Amp", NULL, "DAC L1"}, 1909 {"HP Amp", NULL, "DAC R1"}, 1910 {"HP Amp", NULL, "HP Amp L"}, 1911 {"HP Amp", NULL, "HP Amp R"}, 1912 {"HP Amp", NULL, "Capless"}, 1913 {"HP Amp", NULL, "Charge Pump"}, 1914 {"HP Amp", NULL, "CLKDET SYS"}, 1915 {"HP Amp", NULL, "CBJ Power"}, 1916 {"HP Amp", NULL, "Vref1"}, 1917 {"HP Amp", NULL, "Vref2"}, 1918 {"HPOL Playback", "Switch", "HP Amp"}, 1919 {"HPOR Playback", "Switch", "HP Amp"}, 1920 {"HPOL", NULL, "HPOL Playback"}, 1921 {"HPOR", NULL, "HPOR Playback"}, 1922 }; 1923 1924 static int rt5682_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask, 1925 unsigned int rx_mask, int slots, int slot_width) 1926 { 1927 struct snd_soc_component *component = dai->component; 1928 unsigned int cl, val = 0; 1929 1930 if (tx_mask || rx_mask) 1931 snd_soc_component_update_bits(component, RT5682_TDM_ADDA_CTRL_2, 1932 RT5682_TDM_EN, RT5682_TDM_EN); 1933 else 1934 snd_soc_component_update_bits(component, RT5682_TDM_ADDA_CTRL_2, 1935 RT5682_TDM_EN, 0); 1936 1937 switch (slots) { 1938 case 4: 1939 val |= RT5682_TDM_TX_CH_4; 1940 val |= RT5682_TDM_RX_CH_4; 1941 break; 1942 case 6: 1943 val |= RT5682_TDM_TX_CH_6; 1944 val |= RT5682_TDM_RX_CH_6; 1945 break; 1946 case 8: 1947 val |= RT5682_TDM_TX_CH_8; 1948 val |= RT5682_TDM_RX_CH_8; 1949 break; 1950 case 2: 1951 break; 1952 default: 1953 return -EINVAL; 1954 } 1955 1956 snd_soc_component_update_bits(component, RT5682_TDM_CTRL, 1957 RT5682_TDM_TX_CH_MASK | RT5682_TDM_RX_CH_MASK, val); 1958 1959 switch (slot_width) { 1960 case 8: 1961 if (tx_mask || rx_mask) 1962 return -EINVAL; 1963 cl = RT5682_I2S1_TX_CHL_8 | RT5682_I2S1_RX_CHL_8; 1964 break; 1965 case 16: 1966 val = RT5682_TDM_CL_16; 1967 cl = RT5682_I2S1_TX_CHL_16 | RT5682_I2S1_RX_CHL_16; 1968 break; 1969 case 20: 1970 val = RT5682_TDM_CL_20; 1971 cl = RT5682_I2S1_TX_CHL_20 | RT5682_I2S1_RX_CHL_20; 1972 break; 1973 case 24: 1974 val = RT5682_TDM_CL_24; 1975 cl = RT5682_I2S1_TX_CHL_24 | RT5682_I2S1_RX_CHL_24; 1976 break; 1977 case 32: 1978 val = RT5682_TDM_CL_32; 1979 cl = RT5682_I2S1_TX_CHL_32 | RT5682_I2S1_RX_CHL_32; 1980 break; 1981 default: 1982 return -EINVAL; 1983 } 1984 1985 snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL, 1986 RT5682_TDM_CL_MASK, val); 1987 snd_soc_component_update_bits(component, RT5682_I2S1_SDP, 1988 RT5682_I2S1_TX_CHL_MASK | RT5682_I2S1_RX_CHL_MASK, cl); 1989 1990 return 0; 1991 } 1992 1993 1994 static int rt5682_hw_params(struct snd_pcm_substream *substream, 1995 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) 1996 { 1997 struct snd_soc_component *component = dai->component; 1998 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 1999 unsigned int len_1 = 0, len_2 = 0; 2000 int pre_div, frame_size; 2001 2002 rt5682->lrck[dai->id] = params_rate(params); 2003 pre_div = rl6231_get_clk_info(rt5682->sysclk, rt5682->lrck[dai->id]); 2004 2005 frame_size = snd_soc_params_to_frame_size(params); 2006 if (frame_size < 0) { 2007 dev_err(component->dev, "Unsupported frame size: %d\n", 2008 frame_size); 2009 return -EINVAL; 2010 } 2011 2012 dev_dbg(dai->dev, "lrck is %dHz and pre_div is %d for iis %d\n", 2013 rt5682->lrck[dai->id], pre_div, dai->id); 2014 2015 switch (params_width(params)) { 2016 case 16: 2017 break; 2018 case 20: 2019 len_1 |= RT5682_I2S1_DL_20; 2020 len_2 |= RT5682_I2S2_DL_20; 2021 break; 2022 case 24: 2023 len_1 |= RT5682_I2S1_DL_24; 2024 len_2 |= RT5682_I2S2_DL_24; 2025 break; 2026 case 32: 2027 len_1 |= RT5682_I2S1_DL_32; 2028 len_2 |= RT5682_I2S2_DL_24; 2029 break; 2030 case 8: 2031 len_1 |= RT5682_I2S2_DL_8; 2032 len_2 |= RT5682_I2S2_DL_8; 2033 break; 2034 default: 2035 return -EINVAL; 2036 } 2037 2038 switch (dai->id) { 2039 case RT5682_AIF1: 2040 snd_soc_component_update_bits(component, RT5682_I2S1_SDP, 2041 RT5682_I2S1_DL_MASK, len_1); 2042 if (rt5682->master[RT5682_AIF1]) { 2043 snd_soc_component_update_bits(component, 2044 RT5682_ADDA_CLK_1, RT5682_I2S_M_DIV_MASK, 2045 pre_div << RT5682_I2S_M_DIV_SFT); 2046 } 2047 if (params_channels(params) == 1) /* mono mode */ 2048 snd_soc_component_update_bits(component, 2049 RT5682_I2S1_SDP, RT5682_I2S1_MONO_MASK, 2050 RT5682_I2S1_MONO_EN); 2051 else 2052 snd_soc_component_update_bits(component, 2053 RT5682_I2S1_SDP, RT5682_I2S1_MONO_MASK, 2054 RT5682_I2S1_MONO_DIS); 2055 break; 2056 case RT5682_AIF2: 2057 snd_soc_component_update_bits(component, RT5682_I2S2_SDP, 2058 RT5682_I2S2_DL_MASK, len_2); 2059 if (rt5682->master[RT5682_AIF2]) { 2060 snd_soc_component_update_bits(component, 2061 RT5682_I2S_M_CLK_CTRL_1, RT5682_I2S2_M_PD_MASK, 2062 pre_div << RT5682_I2S2_M_PD_SFT); 2063 } 2064 if (params_channels(params) == 1) /* mono mode */ 2065 snd_soc_component_update_bits(component, 2066 RT5682_I2S2_SDP, RT5682_I2S2_MONO_MASK, 2067 RT5682_I2S2_MONO_EN); 2068 else 2069 snd_soc_component_update_bits(component, 2070 RT5682_I2S2_SDP, RT5682_I2S2_MONO_MASK, 2071 RT5682_I2S2_MONO_DIS); 2072 break; 2073 default: 2074 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id); 2075 return -EINVAL; 2076 } 2077 2078 return 0; 2079 } 2080 2081 static int rt5682_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) 2082 { 2083 struct snd_soc_component *component = dai->component; 2084 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 2085 unsigned int reg_val = 0, tdm_ctrl = 0; 2086 2087 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 2088 case SND_SOC_DAIFMT_CBM_CFM: 2089 rt5682->master[dai->id] = 1; 2090 break; 2091 case SND_SOC_DAIFMT_CBS_CFS: 2092 rt5682->master[dai->id] = 0; 2093 break; 2094 default: 2095 return -EINVAL; 2096 } 2097 2098 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 2099 case SND_SOC_DAIFMT_NB_NF: 2100 break; 2101 case SND_SOC_DAIFMT_IB_NF: 2102 reg_val |= RT5682_I2S_BP_INV; 2103 tdm_ctrl |= RT5682_TDM_S_BP_INV; 2104 break; 2105 case SND_SOC_DAIFMT_NB_IF: 2106 if (dai->id == RT5682_AIF1) 2107 tdm_ctrl |= RT5682_TDM_S_LP_INV | RT5682_TDM_M_BP_INV; 2108 else 2109 return -EINVAL; 2110 break; 2111 case SND_SOC_DAIFMT_IB_IF: 2112 if (dai->id == RT5682_AIF1) 2113 tdm_ctrl |= RT5682_TDM_S_BP_INV | RT5682_TDM_S_LP_INV | 2114 RT5682_TDM_M_BP_INV | RT5682_TDM_M_LP_INV; 2115 else 2116 return -EINVAL; 2117 break; 2118 default: 2119 return -EINVAL; 2120 } 2121 2122 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 2123 case SND_SOC_DAIFMT_I2S: 2124 break; 2125 case SND_SOC_DAIFMT_LEFT_J: 2126 reg_val |= RT5682_I2S_DF_LEFT; 2127 tdm_ctrl |= RT5682_TDM_DF_LEFT; 2128 break; 2129 case SND_SOC_DAIFMT_DSP_A: 2130 reg_val |= RT5682_I2S_DF_PCM_A; 2131 tdm_ctrl |= RT5682_TDM_DF_PCM_A; 2132 break; 2133 case SND_SOC_DAIFMT_DSP_B: 2134 reg_val |= RT5682_I2S_DF_PCM_B; 2135 tdm_ctrl |= RT5682_TDM_DF_PCM_B; 2136 break; 2137 default: 2138 return -EINVAL; 2139 } 2140 2141 switch (dai->id) { 2142 case RT5682_AIF1: 2143 snd_soc_component_update_bits(component, RT5682_I2S1_SDP, 2144 RT5682_I2S_DF_MASK, reg_val); 2145 snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL, 2146 RT5682_TDM_MS_MASK | RT5682_TDM_S_BP_MASK | 2147 RT5682_TDM_DF_MASK | RT5682_TDM_M_BP_MASK | 2148 RT5682_TDM_M_LP_MASK | RT5682_TDM_S_LP_MASK, 2149 tdm_ctrl | rt5682->master[dai->id]); 2150 break; 2151 case RT5682_AIF2: 2152 if (rt5682->master[dai->id] == 0) 2153 reg_val |= RT5682_I2S2_MS_S; 2154 snd_soc_component_update_bits(component, RT5682_I2S2_SDP, 2155 RT5682_I2S2_MS_MASK | RT5682_I2S_BP_MASK | 2156 RT5682_I2S_DF_MASK, reg_val); 2157 break; 2158 default: 2159 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id); 2160 return -EINVAL; 2161 } 2162 return 0; 2163 } 2164 2165 static int rt5682_set_component_sysclk(struct snd_soc_component *component, 2166 int clk_id, int source, unsigned int freq, int dir) 2167 { 2168 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 2169 unsigned int reg_val = 0, src = 0; 2170 2171 if (freq == rt5682->sysclk && clk_id == rt5682->sysclk_src) 2172 return 0; 2173 2174 switch (clk_id) { 2175 case RT5682_SCLK_S_MCLK: 2176 reg_val |= RT5682_SCLK_SRC_MCLK; 2177 src = RT5682_CLK_SRC_MCLK; 2178 break; 2179 case RT5682_SCLK_S_PLL1: 2180 reg_val |= RT5682_SCLK_SRC_PLL1; 2181 src = RT5682_CLK_SRC_PLL1; 2182 break; 2183 case RT5682_SCLK_S_PLL2: 2184 reg_val |= RT5682_SCLK_SRC_PLL2; 2185 src = RT5682_CLK_SRC_PLL2; 2186 break; 2187 case RT5682_SCLK_S_RCCLK: 2188 reg_val |= RT5682_SCLK_SRC_RCCLK; 2189 src = RT5682_CLK_SRC_RCCLK; 2190 break; 2191 default: 2192 dev_err(component->dev, "Invalid clock id (%d)\n", clk_id); 2193 return -EINVAL; 2194 } 2195 snd_soc_component_update_bits(component, RT5682_GLB_CLK, 2196 RT5682_SCLK_SRC_MASK, reg_val); 2197 2198 if (rt5682->master[RT5682_AIF2]) { 2199 snd_soc_component_update_bits(component, 2200 RT5682_I2S_M_CLK_CTRL_1, RT5682_I2S2_SRC_MASK, 2201 src << RT5682_I2S2_SRC_SFT); 2202 } 2203 2204 rt5682->sysclk = freq; 2205 rt5682->sysclk_src = clk_id; 2206 2207 dev_dbg(component->dev, "Sysclk is %dHz and clock id is %d\n", 2208 freq, clk_id); 2209 2210 return 0; 2211 } 2212 2213 static int rt5682_set_component_pll(struct snd_soc_component *component, 2214 int pll_id, int source, unsigned int freq_in, 2215 unsigned int freq_out) 2216 { 2217 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 2218 struct rl6231_pll_code pll_code; 2219 int ret; 2220 2221 if (source == rt5682->pll_src && freq_in == rt5682->pll_in && 2222 freq_out == rt5682->pll_out) 2223 return 0; 2224 2225 if (!freq_in || !freq_out) { 2226 dev_dbg(component->dev, "PLL disabled\n"); 2227 2228 rt5682->pll_in = 0; 2229 rt5682->pll_out = 0; 2230 snd_soc_component_update_bits(component, RT5682_GLB_CLK, 2231 RT5682_SCLK_SRC_MASK, RT5682_SCLK_SRC_MCLK); 2232 return 0; 2233 } 2234 2235 switch (source) { 2236 case RT5682_PLL1_S_MCLK: 2237 snd_soc_component_update_bits(component, RT5682_GLB_CLK, 2238 RT5682_PLL1_SRC_MASK, RT5682_PLL1_SRC_MCLK); 2239 break; 2240 case RT5682_PLL1_S_BCLK1: 2241 snd_soc_component_update_bits(component, RT5682_GLB_CLK, 2242 RT5682_PLL1_SRC_MASK, RT5682_PLL1_SRC_BCLK1); 2243 break; 2244 default: 2245 dev_err(component->dev, "Unknown PLL Source %d\n", source); 2246 return -EINVAL; 2247 } 2248 2249 ret = rl6231_pll_calc(freq_in, freq_out, &pll_code); 2250 if (ret < 0) { 2251 dev_err(component->dev, "Unsupport input clock %d\n", freq_in); 2252 return ret; 2253 } 2254 2255 dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n", 2256 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code), 2257 pll_code.n_code, pll_code.k_code); 2258 2259 snd_soc_component_write(component, RT5682_PLL_CTRL_1, 2260 pll_code.n_code << RT5682_PLL_N_SFT | pll_code.k_code); 2261 snd_soc_component_write(component, RT5682_PLL_CTRL_2, 2262 (pll_code.m_bp ? 0 : pll_code.m_code) << RT5682_PLL_M_SFT | 2263 pll_code.m_bp << RT5682_PLL_M_BP_SFT | RT5682_PLL_RST); 2264 2265 rt5682->pll_in = freq_in; 2266 rt5682->pll_out = freq_out; 2267 rt5682->pll_src = source; 2268 2269 return 0; 2270 } 2271 2272 static int rt5682_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio) 2273 { 2274 struct snd_soc_component *component = dai->component; 2275 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 2276 2277 rt5682->bclk[dai->id] = ratio; 2278 2279 switch (ratio) { 2280 case 64: 2281 snd_soc_component_update_bits(component, RT5682_ADDA_CLK_2, 2282 RT5682_I2S2_BCLK_MS2_MASK, 2283 RT5682_I2S2_BCLK_MS2_64); 2284 break; 2285 case 32: 2286 snd_soc_component_update_bits(component, RT5682_ADDA_CLK_2, 2287 RT5682_I2S2_BCLK_MS2_MASK, 2288 RT5682_I2S2_BCLK_MS2_32); 2289 break; 2290 default: 2291 dev_err(dai->dev, "Invalid bclk ratio %d\n", ratio); 2292 return -EINVAL; 2293 } 2294 2295 return 0; 2296 } 2297 2298 static int rt5682_set_bias_level(struct snd_soc_component *component, 2299 enum snd_soc_bias_level level) 2300 { 2301 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 2302 2303 switch (level) { 2304 case SND_SOC_BIAS_PREPARE: 2305 regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_1, 2306 RT5682_PWR_MB | RT5682_PWR_BG, 2307 RT5682_PWR_MB | RT5682_PWR_BG); 2308 regmap_update_bits(rt5682->regmap, RT5682_PWR_DIG_1, 2309 RT5682_DIG_GATE_CTRL | RT5682_PWR_LDO, 2310 RT5682_DIG_GATE_CTRL | RT5682_PWR_LDO); 2311 break; 2312 2313 case SND_SOC_BIAS_STANDBY: 2314 regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_1, 2315 RT5682_PWR_MB, RT5682_PWR_MB); 2316 regmap_update_bits(rt5682->regmap, RT5682_PWR_DIG_1, 2317 RT5682_DIG_GATE_CTRL, RT5682_DIG_GATE_CTRL); 2318 break; 2319 case SND_SOC_BIAS_OFF: 2320 regmap_update_bits(rt5682->regmap, RT5682_PWR_DIG_1, 2321 RT5682_DIG_GATE_CTRL | RT5682_PWR_LDO, 0); 2322 regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_1, 2323 RT5682_PWR_MB | RT5682_PWR_BG, 0); 2324 break; 2325 2326 default: 2327 break; 2328 } 2329 2330 return 0; 2331 } 2332 2333 static int rt5682_probe(struct snd_soc_component *component) 2334 { 2335 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 2336 2337 rt5682->component = component; 2338 2339 return 0; 2340 } 2341 2342 static void rt5682_remove(struct snd_soc_component *component) 2343 { 2344 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 2345 2346 rt5682_reset(rt5682->regmap); 2347 } 2348 2349 #ifdef CONFIG_PM 2350 static int rt5682_suspend(struct snd_soc_component *component) 2351 { 2352 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 2353 2354 regcache_cache_only(rt5682->regmap, true); 2355 regcache_mark_dirty(rt5682->regmap); 2356 return 0; 2357 } 2358 2359 static int rt5682_resume(struct snd_soc_component *component) 2360 { 2361 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 2362 2363 regcache_cache_only(rt5682->regmap, false); 2364 regcache_sync(rt5682->regmap); 2365 2366 return 0; 2367 } 2368 #else 2369 #define rt5682_suspend NULL 2370 #define rt5682_resume NULL 2371 #endif 2372 2373 #define RT5682_STEREO_RATES SNDRV_PCM_RATE_8000_192000 2374 #define RT5682_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ 2375 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8) 2376 2377 static const struct snd_soc_dai_ops rt5682_aif1_dai_ops = { 2378 .hw_params = rt5682_hw_params, 2379 .set_fmt = rt5682_set_dai_fmt, 2380 .set_tdm_slot = rt5682_set_tdm_slot, 2381 }; 2382 2383 static const struct snd_soc_dai_ops rt5682_aif2_dai_ops = { 2384 .hw_params = rt5682_hw_params, 2385 .set_fmt = rt5682_set_dai_fmt, 2386 .set_bclk_ratio = rt5682_set_bclk_ratio, 2387 }; 2388 2389 static struct snd_soc_dai_driver rt5682_dai[] = { 2390 { 2391 .name = "rt5682-aif1", 2392 .id = RT5682_AIF1, 2393 .playback = { 2394 .stream_name = "AIF1 Playback", 2395 .channels_min = 1, 2396 .channels_max = 2, 2397 .rates = RT5682_STEREO_RATES, 2398 .formats = RT5682_FORMATS, 2399 }, 2400 .capture = { 2401 .stream_name = "AIF1 Capture", 2402 .channels_min = 1, 2403 .channels_max = 2, 2404 .rates = RT5682_STEREO_RATES, 2405 .formats = RT5682_FORMATS, 2406 }, 2407 .ops = &rt5682_aif1_dai_ops, 2408 }, 2409 { 2410 .name = "rt5682-aif2", 2411 .id = RT5682_AIF2, 2412 .capture = { 2413 .stream_name = "AIF2 Capture", 2414 .channels_min = 1, 2415 .channels_max = 2, 2416 .rates = RT5682_STEREO_RATES, 2417 .formats = RT5682_FORMATS, 2418 }, 2419 .ops = &rt5682_aif2_dai_ops, 2420 }, 2421 }; 2422 2423 static const struct snd_soc_component_driver soc_component_dev_rt5682 = { 2424 .probe = rt5682_probe, 2425 .remove = rt5682_remove, 2426 .suspend = rt5682_suspend, 2427 .resume = rt5682_resume, 2428 .set_bias_level = rt5682_set_bias_level, 2429 .controls = rt5682_snd_controls, 2430 .num_controls = ARRAY_SIZE(rt5682_snd_controls), 2431 .dapm_widgets = rt5682_dapm_widgets, 2432 .num_dapm_widgets = ARRAY_SIZE(rt5682_dapm_widgets), 2433 .dapm_routes = rt5682_dapm_routes, 2434 .num_dapm_routes = ARRAY_SIZE(rt5682_dapm_routes), 2435 .set_sysclk = rt5682_set_component_sysclk, 2436 .set_pll = rt5682_set_component_pll, 2437 .set_jack = rt5682_set_jack_detect, 2438 .use_pmdown_time = 1, 2439 .endianness = 1, 2440 .non_legacy_dai_naming = 1, 2441 }; 2442 2443 static const struct regmap_config rt5682_regmap = { 2444 .reg_bits = 16, 2445 .val_bits = 16, 2446 .max_register = RT5682_I2C_MODE, 2447 .volatile_reg = rt5682_volatile_register, 2448 .readable_reg = rt5682_readable_register, 2449 .cache_type = REGCACHE_RBTREE, 2450 .reg_defaults = rt5682_reg, 2451 .num_reg_defaults = ARRAY_SIZE(rt5682_reg), 2452 .use_single_read = true, 2453 .use_single_write = true, 2454 }; 2455 2456 static const struct i2c_device_id rt5682_i2c_id[] = { 2457 {"rt5682", 0}, 2458 {} 2459 }; 2460 MODULE_DEVICE_TABLE(i2c, rt5682_i2c_id); 2461 2462 static int rt5682_parse_dt(struct rt5682_priv *rt5682, struct device *dev) 2463 { 2464 2465 device_property_read_u32(dev, "realtek,dmic1-data-pin", 2466 &rt5682->pdata.dmic1_data_pin); 2467 device_property_read_u32(dev, "realtek,dmic1-clk-pin", 2468 &rt5682->pdata.dmic1_clk_pin); 2469 device_property_read_u32(dev, "realtek,jd-src", 2470 &rt5682->pdata.jd_src); 2471 2472 rt5682->pdata.ldo1_en = of_get_named_gpio(dev->of_node, 2473 "realtek,ldo1-en-gpios", 0); 2474 2475 return 0; 2476 } 2477 2478 static void rt5682_calibrate(struct rt5682_priv *rt5682) 2479 { 2480 int value, count; 2481 2482 mutex_lock(&rt5682->calibrate_mutex); 2483 2484 rt5682_reset(rt5682->regmap); 2485 regmap_write(rt5682->regmap, RT5682_PWR_ANLG_1, 0xa2af); 2486 usleep_range(15000, 20000); 2487 regmap_write(rt5682->regmap, RT5682_PWR_ANLG_1, 0xf2af); 2488 regmap_write(rt5682->regmap, RT5682_MICBIAS_2, 0x0300); 2489 regmap_write(rt5682->regmap, RT5682_GLB_CLK, 0x8000); 2490 regmap_write(rt5682->regmap, RT5682_PWR_DIG_1, 0x0100); 2491 regmap_write(rt5682->regmap, RT5682_HP_IMP_SENS_CTRL_19, 0x3800); 2492 regmap_write(rt5682->regmap, RT5682_CHOP_DAC, 0x3000); 2493 regmap_write(rt5682->regmap, RT5682_CALIB_ADC_CTRL, 0x7005); 2494 regmap_write(rt5682->regmap, RT5682_STO1_ADC_MIXER, 0x686c); 2495 regmap_write(rt5682->regmap, RT5682_CAL_REC, 0x0d0d); 2496 regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_2, 0x0321); 2497 regmap_write(rt5682->regmap, RT5682_HP_LOGIC_CTRL_2, 0x0004); 2498 regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_1, 0x7c00); 2499 regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_3, 0x06a1); 2500 regmap_write(rt5682->regmap, RT5682_A_DAC1_MUX, 0x0311); 2501 regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_1, 0x7c00); 2502 2503 regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_1, 0xfc00); 2504 2505 for (count = 0; count < 60; count++) { 2506 regmap_read(rt5682->regmap, RT5682_HP_CALIB_STA_1, &value); 2507 if (!(value & 0x8000)) 2508 break; 2509 2510 usleep_range(10000, 10005); 2511 } 2512 2513 if (count >= 60) 2514 pr_err("HP Calibration Failure\n"); 2515 2516 /* restore settings */ 2517 regmap_write(rt5682->regmap, RT5682_PWR_ANLG_1, 0x02af); 2518 regmap_write(rt5682->regmap, RT5682_MICBIAS_2, 0x0080); 2519 regmap_write(rt5682->regmap, RT5682_GLB_CLK, 0x0000); 2520 regmap_write(rt5682->regmap, RT5682_PWR_DIG_1, 0x0000); 2521 regmap_write(rt5682->regmap, RT5682_CHOP_DAC, 0x2000); 2522 regmap_write(rt5682->regmap, RT5682_CALIB_ADC_CTRL, 0x2005); 2523 regmap_write(rt5682->regmap, RT5682_STO1_ADC_MIXER, 0xc0c4); 2524 2525 mutex_unlock(&rt5682->calibrate_mutex); 2526 2527 } 2528 2529 static int rt5682_i2c_probe(struct i2c_client *i2c, 2530 const struct i2c_device_id *id) 2531 { 2532 struct rt5682_platform_data *pdata = dev_get_platdata(&i2c->dev); 2533 struct rt5682_priv *rt5682; 2534 int i, ret; 2535 unsigned int val; 2536 2537 rt5682 = devm_kzalloc(&i2c->dev, sizeof(struct rt5682_priv), 2538 GFP_KERNEL); 2539 2540 if (rt5682 == NULL) 2541 return -ENOMEM; 2542 2543 i2c_set_clientdata(i2c, rt5682); 2544 2545 rt5682->pdata = i2s_default_platform_data; 2546 2547 if (pdata) 2548 rt5682->pdata = *pdata; 2549 else 2550 rt5682_parse_dt(rt5682, &i2c->dev); 2551 2552 rt5682->regmap = devm_regmap_init_i2c(i2c, &rt5682_regmap); 2553 if (IS_ERR(rt5682->regmap)) { 2554 ret = PTR_ERR(rt5682->regmap); 2555 dev_err(&i2c->dev, "Failed to allocate register map: %d\n", 2556 ret); 2557 return ret; 2558 } 2559 2560 for (i = 0; i < ARRAY_SIZE(rt5682->supplies); i++) 2561 rt5682->supplies[i].supply = rt5682_supply_names[i]; 2562 2563 ret = devm_regulator_bulk_get(&i2c->dev, ARRAY_SIZE(rt5682->supplies), 2564 rt5682->supplies); 2565 if (ret != 0) { 2566 dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret); 2567 return ret; 2568 } 2569 2570 ret = regulator_bulk_enable(ARRAY_SIZE(rt5682->supplies), 2571 rt5682->supplies); 2572 if (ret != 0) { 2573 dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret); 2574 return ret; 2575 } 2576 2577 if (gpio_is_valid(rt5682->pdata.ldo1_en)) { 2578 if (devm_gpio_request_one(&i2c->dev, rt5682->pdata.ldo1_en, 2579 GPIOF_OUT_INIT_HIGH, "rt5682")) 2580 dev_err(&i2c->dev, "Fail gpio_request gpio_ldo\n"); 2581 } 2582 2583 /* Sleep for 300 ms miniumum */ 2584 usleep_range(300000, 350000); 2585 2586 regmap_write(rt5682->regmap, RT5682_I2C_MODE, 0x1); 2587 usleep_range(10000, 15000); 2588 2589 regmap_read(rt5682->regmap, RT5682_DEVICE_ID, &val); 2590 if (val != DEVICE_ID) { 2591 pr_err("Device with ID register %x is not rt5682\n", val); 2592 return -ENODEV; 2593 } 2594 2595 rt5682_reset(rt5682->regmap); 2596 2597 rt5682_calibrate(rt5682); 2598 2599 ret = regmap_multi_reg_write(rt5682->regmap, patch_list, 2600 ARRAY_SIZE(patch_list)); 2601 if (ret != 0) 2602 dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret); 2603 2604 regmap_write(rt5682->regmap, RT5682_DEPOP_1, 0x0000); 2605 2606 /* DMIC pin*/ 2607 if (rt5682->pdata.dmic1_data_pin != RT5682_DMIC1_NULL) { 2608 switch (rt5682->pdata.dmic1_data_pin) { 2609 case RT5682_DMIC1_DATA_GPIO2: /* share with LRCK2 */ 2610 regmap_update_bits(rt5682->regmap, RT5682_DMIC_CTRL_1, 2611 RT5682_DMIC_1_DP_MASK, RT5682_DMIC_1_DP_GPIO2); 2612 regmap_update_bits(rt5682->regmap, RT5682_GPIO_CTRL_1, 2613 RT5682_GP2_PIN_MASK, RT5682_GP2_PIN_DMIC_SDA); 2614 break; 2615 2616 case RT5682_DMIC1_DATA_GPIO5: /* share with DACDAT1 */ 2617 regmap_update_bits(rt5682->regmap, RT5682_DMIC_CTRL_1, 2618 RT5682_DMIC_1_DP_MASK, RT5682_DMIC_1_DP_GPIO5); 2619 regmap_update_bits(rt5682->regmap, RT5682_GPIO_CTRL_1, 2620 RT5682_GP5_PIN_MASK, RT5682_GP5_PIN_DMIC_SDA); 2621 break; 2622 2623 default: 2624 dev_warn(&i2c->dev, "invalid DMIC_DAT pin\n"); 2625 break; 2626 } 2627 2628 switch (rt5682->pdata.dmic1_clk_pin) { 2629 case RT5682_DMIC1_CLK_GPIO1: /* share with IRQ */ 2630 regmap_update_bits(rt5682->regmap, RT5682_GPIO_CTRL_1, 2631 RT5682_GP1_PIN_MASK, RT5682_GP1_PIN_DMIC_CLK); 2632 break; 2633 2634 case RT5682_DMIC1_CLK_GPIO3: /* share with BCLK2 */ 2635 regmap_update_bits(rt5682->regmap, RT5682_GPIO_CTRL_1, 2636 RT5682_GP3_PIN_MASK, RT5682_GP3_PIN_DMIC_CLK); 2637 break; 2638 2639 default: 2640 dev_warn(&i2c->dev, "invalid DMIC_CLK pin\n"); 2641 break; 2642 } 2643 } 2644 2645 regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_1, 2646 RT5682_LDO1_DVO_MASK | RT5682_HP_DRIVER_MASK, 2647 RT5682_LDO1_DVO_12 | RT5682_HP_DRIVER_5X); 2648 regmap_write(rt5682->regmap, RT5682_MICBIAS_2, 0x0380); 2649 regmap_update_bits(rt5682->regmap, RT5682_GPIO_CTRL_1, 2650 RT5682_GP4_PIN_MASK | RT5682_GP5_PIN_MASK, 2651 RT5682_GP4_PIN_ADCDAT1 | RT5682_GP5_PIN_DACDAT1); 2652 regmap_write(rt5682->regmap, RT5682_TEST_MODE_CTRL_1, 0x0000); 2653 regmap_update_bits(rt5682->regmap, RT5682_BIAS_CUR_CTRL_8, 2654 RT5682_HPA_CP_BIAS_CTRL_MASK, RT5682_HPA_CP_BIAS_3UA); 2655 regmap_update_bits(rt5682->regmap, RT5682_CHARGE_PUMP_1, 2656 RT5682_CP_CLK_HP_MASK, RT5682_CP_CLK_HP_300KHZ); 2657 2658 INIT_DELAYED_WORK(&rt5682->jack_detect_work, 2659 rt5682_jack_detect_handler); 2660 INIT_DELAYED_WORK(&rt5682->jd_check_work, 2661 rt5682_jd_check_handler); 2662 2663 mutex_init(&rt5682->calibrate_mutex); 2664 2665 if (i2c->irq) { 2666 ret = devm_request_threaded_irq(&i2c->dev, i2c->irq, NULL, 2667 rt5682_irq, IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING 2668 | IRQF_ONESHOT, "rt5682", rt5682); 2669 if (ret) 2670 dev_err(&i2c->dev, "Failed to reguest IRQ: %d\n", ret); 2671 2672 } 2673 2674 return snd_soc_register_component(&i2c->dev, &soc_component_dev_rt5682, 2675 rt5682_dai, ARRAY_SIZE(rt5682_dai)); 2676 } 2677 2678 static int rt5682_i2c_remove(struct i2c_client *i2c) 2679 { 2680 snd_soc_unregister_component(&i2c->dev); 2681 2682 return 0; 2683 } 2684 2685 static void rt5682_i2c_shutdown(struct i2c_client *client) 2686 { 2687 struct rt5682_priv *rt5682 = i2c_get_clientdata(client); 2688 2689 rt5682_reset(rt5682->regmap); 2690 } 2691 2692 #ifdef CONFIG_OF 2693 static const struct of_device_id rt5682_of_match[] = { 2694 {.compatible = "realtek,rt5682i"}, 2695 {}, 2696 }; 2697 MODULE_DEVICE_TABLE(of, rt5682_of_match); 2698 #endif 2699 2700 #ifdef CONFIG_ACPI 2701 static const struct acpi_device_id rt5682_acpi_match[] = { 2702 {"10EC5682", 0,}, 2703 {}, 2704 }; 2705 MODULE_DEVICE_TABLE(acpi, rt5682_acpi_match); 2706 #endif 2707 2708 static struct i2c_driver rt5682_i2c_driver = { 2709 .driver = { 2710 .name = "rt5682", 2711 .of_match_table = of_match_ptr(rt5682_of_match), 2712 .acpi_match_table = ACPI_PTR(rt5682_acpi_match), 2713 }, 2714 .probe = rt5682_i2c_probe, 2715 .remove = rt5682_i2c_remove, 2716 .shutdown = rt5682_i2c_shutdown, 2717 .id_table = rt5682_i2c_id, 2718 }; 2719 module_i2c_driver(rt5682_i2c_driver); 2720 2721 MODULE_DESCRIPTION("ASoC RT5682 driver"); 2722 MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>"); 2723 MODULE_LICENSE("GPL v2"); 2724