1 // SPDX-License-Identifier: GPL-2.0-only 2 // 3 // rt5682.c -- RT5682 ALSA SoC audio component driver 4 // 5 // Copyright 2018 Realtek Semiconductor Corp. 6 // Author: Bard Liao <bardliao@realtek.com> 7 // 8 9 #include <linux/module.h> 10 #include <linux/moduleparam.h> 11 #include <linux/init.h> 12 #include <linux/delay.h> 13 #include <linux/pm.h> 14 #include <linux/pm_runtime.h> 15 #include <linux/platform_device.h> 16 #include <linux/spi/spi.h> 17 #include <linux/acpi.h> 18 #include <linux/gpio.h> 19 #include <linux/of_gpio.h> 20 #include <linux/mutex.h> 21 #include <sound/core.h> 22 #include <sound/pcm.h> 23 #include <sound/pcm_params.h> 24 #include <sound/jack.h> 25 #include <sound/soc.h> 26 #include <sound/soc-dapm.h> 27 #include <sound/initval.h> 28 #include <sound/tlv.h> 29 #include <sound/rt5682.h> 30 31 #include "rl6231.h" 32 #include "rt5682.h" 33 34 const char *rt5682_supply_names[RT5682_NUM_SUPPLIES] = { 35 "AVDD", 36 "MICVDD", 37 "VBAT", 38 }; 39 EXPORT_SYMBOL_GPL(rt5682_supply_names); 40 41 static const struct reg_sequence patch_list[] = { 42 {RT5682_HP_IMP_SENS_CTRL_19, 0x1000}, 43 {RT5682_DAC_ADC_DIG_VOL1, 0xa020}, 44 {RT5682_I2C_CTRL, 0x000f}, 45 {RT5682_PLL2_INTERNAL, 0x8266}, 46 {RT5682_SAR_IL_CMD_1, 0x22b7}, 47 {RT5682_SAR_IL_CMD_3, 0x0365}, 48 {RT5682_SAR_IL_CMD_6, 0x0110}, 49 {RT5682_CHARGE_PUMP_1, 0x0210}, 50 {RT5682_HP_LOGIC_CTRL_2, 0x0007}, 51 }; 52 53 void rt5682_apply_patch_list(struct rt5682_priv *rt5682, struct device *dev) 54 { 55 int ret; 56 57 ret = regmap_multi_reg_write(rt5682->regmap, patch_list, 58 ARRAY_SIZE(patch_list)); 59 if (ret) 60 dev_warn(dev, "Failed to apply regmap patch: %d\n", ret); 61 } 62 EXPORT_SYMBOL_GPL(rt5682_apply_patch_list); 63 64 const struct reg_default rt5682_reg[RT5682_REG_NUM] = { 65 {0x0002, 0x8080}, 66 {0x0003, 0x8000}, 67 {0x0005, 0x0000}, 68 {0x0006, 0x0000}, 69 {0x0008, 0x800f}, 70 {0x000b, 0x0000}, 71 {0x0010, 0x4040}, 72 {0x0011, 0x0000}, 73 {0x0012, 0x1404}, 74 {0x0013, 0x1000}, 75 {0x0014, 0xa00a}, 76 {0x0015, 0x0404}, 77 {0x0016, 0x0404}, 78 {0x0019, 0xafaf}, 79 {0x001c, 0x2f2f}, 80 {0x001f, 0x0000}, 81 {0x0022, 0x5757}, 82 {0x0023, 0x0039}, 83 {0x0024, 0x000b}, 84 {0x0026, 0xc0c4}, 85 {0x0029, 0x8080}, 86 {0x002a, 0xa0a0}, 87 {0x002b, 0x0300}, 88 {0x0030, 0x0000}, 89 {0x003c, 0x0080}, 90 {0x0044, 0x0c0c}, 91 {0x0049, 0x0000}, 92 {0x0061, 0x0000}, 93 {0x0062, 0x0000}, 94 {0x0063, 0x003f}, 95 {0x0064, 0x0000}, 96 {0x0065, 0x0000}, 97 {0x0066, 0x0030}, 98 {0x0067, 0x0000}, 99 {0x006b, 0x0000}, 100 {0x006c, 0x0000}, 101 {0x006d, 0x2200}, 102 {0x006e, 0x0a10}, 103 {0x0070, 0x8000}, 104 {0x0071, 0x8000}, 105 {0x0073, 0x0000}, 106 {0x0074, 0x0000}, 107 {0x0075, 0x0002}, 108 {0x0076, 0x0001}, 109 {0x0079, 0x0000}, 110 {0x007a, 0x0000}, 111 {0x007b, 0x0000}, 112 {0x007c, 0x0100}, 113 {0x007e, 0x0000}, 114 {0x0080, 0x0000}, 115 {0x0081, 0x0000}, 116 {0x0082, 0x0000}, 117 {0x0083, 0x0000}, 118 {0x0084, 0x0000}, 119 {0x0085, 0x0000}, 120 {0x0086, 0x0005}, 121 {0x0087, 0x0000}, 122 {0x0088, 0x0000}, 123 {0x008c, 0x0003}, 124 {0x008d, 0x0000}, 125 {0x008e, 0x0060}, 126 {0x008f, 0x1000}, 127 {0x0091, 0x0c26}, 128 {0x0092, 0x0073}, 129 {0x0093, 0x0000}, 130 {0x0094, 0x0080}, 131 {0x0098, 0x0000}, 132 {0x009a, 0x0000}, 133 {0x009b, 0x0000}, 134 {0x009c, 0x0000}, 135 {0x009d, 0x0000}, 136 {0x009e, 0x100c}, 137 {0x009f, 0x0000}, 138 {0x00a0, 0x0000}, 139 {0x00a3, 0x0002}, 140 {0x00a4, 0x0001}, 141 {0x00ae, 0x2040}, 142 {0x00af, 0x0000}, 143 {0x00b6, 0x0000}, 144 {0x00b7, 0x0000}, 145 {0x00b8, 0x0000}, 146 {0x00b9, 0x0002}, 147 {0x00be, 0x0000}, 148 {0x00c0, 0x0160}, 149 {0x00c1, 0x82a0}, 150 {0x00c2, 0x0000}, 151 {0x00d0, 0x0000}, 152 {0x00d1, 0x2244}, 153 {0x00d2, 0x3300}, 154 {0x00d3, 0x2200}, 155 {0x00d4, 0x0000}, 156 {0x00d9, 0x0009}, 157 {0x00da, 0x0000}, 158 {0x00db, 0x0000}, 159 {0x00dc, 0x00c0}, 160 {0x00dd, 0x2220}, 161 {0x00de, 0x3131}, 162 {0x00df, 0x3131}, 163 {0x00e0, 0x3131}, 164 {0x00e2, 0x0000}, 165 {0x00e3, 0x4000}, 166 {0x00e4, 0x0aa0}, 167 {0x00e5, 0x3131}, 168 {0x00e6, 0x3131}, 169 {0x00e7, 0x3131}, 170 {0x00e8, 0x3131}, 171 {0x00ea, 0xb320}, 172 {0x00eb, 0x0000}, 173 {0x00f0, 0x0000}, 174 {0x00f1, 0x00d0}, 175 {0x00f2, 0x00d0}, 176 {0x00f6, 0x0000}, 177 {0x00fa, 0x0000}, 178 {0x00fb, 0x0000}, 179 {0x00fc, 0x0000}, 180 {0x00fd, 0x0000}, 181 {0x00fe, 0x10ec}, 182 {0x00ff, 0x6530}, 183 {0x0100, 0xa0a0}, 184 {0x010b, 0x0000}, 185 {0x010c, 0xae00}, 186 {0x010d, 0xaaa0}, 187 {0x010e, 0x8aa2}, 188 {0x010f, 0x02a2}, 189 {0x0110, 0xc000}, 190 {0x0111, 0x04a2}, 191 {0x0112, 0x2800}, 192 {0x0113, 0x0000}, 193 {0x0117, 0x0100}, 194 {0x0125, 0x0410}, 195 {0x0132, 0x6026}, 196 {0x0136, 0x5555}, 197 {0x0138, 0x3700}, 198 {0x013a, 0x2000}, 199 {0x013b, 0x2000}, 200 {0x013c, 0x2005}, 201 {0x013f, 0x0000}, 202 {0x0142, 0x0000}, 203 {0x0145, 0x0002}, 204 {0x0146, 0x0000}, 205 {0x0147, 0x0000}, 206 {0x0148, 0x0000}, 207 {0x0149, 0x0000}, 208 {0x0150, 0x79a1}, 209 {0x0156, 0xaaaa}, 210 {0x0160, 0x4ec0}, 211 {0x0161, 0x0080}, 212 {0x0162, 0x0200}, 213 {0x0163, 0x0800}, 214 {0x0164, 0x0000}, 215 {0x0165, 0x0000}, 216 {0x0166, 0x0000}, 217 {0x0167, 0x000f}, 218 {0x0168, 0x000f}, 219 {0x0169, 0x0021}, 220 {0x0190, 0x413d}, 221 {0x0194, 0x0000}, 222 {0x0195, 0x0000}, 223 {0x0197, 0x0022}, 224 {0x0198, 0x0000}, 225 {0x0199, 0x0000}, 226 {0x01af, 0x0000}, 227 {0x01b0, 0x0400}, 228 {0x01b1, 0x0000}, 229 {0x01b2, 0x0000}, 230 {0x01b3, 0x0000}, 231 {0x01b4, 0x0000}, 232 {0x01b5, 0x0000}, 233 {0x01b6, 0x01c3}, 234 {0x01b7, 0x02a0}, 235 {0x01b8, 0x03e9}, 236 {0x01b9, 0x1389}, 237 {0x01ba, 0xc351}, 238 {0x01bb, 0x0009}, 239 {0x01bc, 0x0018}, 240 {0x01bd, 0x002a}, 241 {0x01be, 0x004c}, 242 {0x01bf, 0x0097}, 243 {0x01c0, 0x433d}, 244 {0x01c2, 0x0000}, 245 {0x01c3, 0x0000}, 246 {0x01c4, 0x0000}, 247 {0x01c5, 0x0000}, 248 {0x01c6, 0x0000}, 249 {0x01c7, 0x0000}, 250 {0x01c8, 0x40af}, 251 {0x01c9, 0x0702}, 252 {0x01ca, 0x0000}, 253 {0x01cb, 0x0000}, 254 {0x01cc, 0x5757}, 255 {0x01cd, 0x5757}, 256 {0x01ce, 0x5757}, 257 {0x01cf, 0x5757}, 258 {0x01d0, 0x5757}, 259 {0x01d1, 0x5757}, 260 {0x01d2, 0x5757}, 261 {0x01d3, 0x5757}, 262 {0x01d4, 0x5757}, 263 {0x01d5, 0x5757}, 264 {0x01d6, 0x0000}, 265 {0x01d7, 0x0008}, 266 {0x01d8, 0x0029}, 267 {0x01d9, 0x3333}, 268 {0x01da, 0x0000}, 269 {0x01db, 0x0004}, 270 {0x01dc, 0x0000}, 271 {0x01de, 0x7c00}, 272 {0x01df, 0x0320}, 273 {0x01e0, 0x06a1}, 274 {0x01e1, 0x0000}, 275 {0x01e2, 0x0000}, 276 {0x01e3, 0x0000}, 277 {0x01e4, 0x0000}, 278 {0x01e6, 0x0001}, 279 {0x01e7, 0x0000}, 280 {0x01e8, 0x0000}, 281 {0x01ea, 0x0000}, 282 {0x01eb, 0x0000}, 283 {0x01ec, 0x0000}, 284 {0x01ed, 0x0000}, 285 {0x01ee, 0x0000}, 286 {0x01ef, 0x0000}, 287 {0x01f0, 0x0000}, 288 {0x01f1, 0x0000}, 289 {0x01f2, 0x0000}, 290 {0x01f3, 0x0000}, 291 {0x01f4, 0x0000}, 292 {0x0210, 0x6297}, 293 {0x0211, 0xa005}, 294 {0x0212, 0x824c}, 295 {0x0213, 0xf7ff}, 296 {0x0214, 0xf24c}, 297 {0x0215, 0x0102}, 298 {0x0216, 0x00a3}, 299 {0x0217, 0x0048}, 300 {0x0218, 0xa2c0}, 301 {0x0219, 0x0400}, 302 {0x021a, 0x00c8}, 303 {0x021b, 0x00c0}, 304 {0x021c, 0x0000}, 305 {0x0250, 0x4500}, 306 {0x0251, 0x40b3}, 307 {0x0252, 0x0000}, 308 {0x0253, 0x0000}, 309 {0x0254, 0x0000}, 310 {0x0255, 0x0000}, 311 {0x0256, 0x0000}, 312 {0x0257, 0x0000}, 313 {0x0258, 0x0000}, 314 {0x0259, 0x0000}, 315 {0x025a, 0x0005}, 316 {0x0270, 0x0000}, 317 {0x02ff, 0x0110}, 318 {0x0300, 0x001f}, 319 {0x0301, 0x032c}, 320 {0x0302, 0x5f21}, 321 {0x0303, 0x4000}, 322 {0x0304, 0x4000}, 323 {0x0305, 0x06d5}, 324 {0x0306, 0x8000}, 325 {0x0307, 0x0700}, 326 {0x0310, 0x4560}, 327 {0x0311, 0xa4a8}, 328 {0x0312, 0x7418}, 329 {0x0313, 0x0000}, 330 {0x0314, 0x0006}, 331 {0x0315, 0xffff}, 332 {0x0316, 0xc400}, 333 {0x0317, 0x0000}, 334 {0x03c0, 0x7e00}, 335 {0x03c1, 0x8000}, 336 {0x03c2, 0x8000}, 337 {0x03c3, 0x8000}, 338 {0x03c4, 0x8000}, 339 {0x03c5, 0x8000}, 340 {0x03c6, 0x8000}, 341 {0x03c7, 0x8000}, 342 {0x03c8, 0x8000}, 343 {0x03c9, 0x8000}, 344 {0x03ca, 0x8000}, 345 {0x03cb, 0x8000}, 346 {0x03cc, 0x8000}, 347 {0x03d0, 0x0000}, 348 {0x03d1, 0x0000}, 349 {0x03d2, 0x0000}, 350 {0x03d3, 0x0000}, 351 {0x03d4, 0x2000}, 352 {0x03d5, 0x2000}, 353 {0x03d6, 0x0000}, 354 {0x03d7, 0x0000}, 355 {0x03d8, 0x2000}, 356 {0x03d9, 0x2000}, 357 {0x03da, 0x2000}, 358 {0x03db, 0x2000}, 359 {0x03dc, 0x0000}, 360 {0x03dd, 0x0000}, 361 {0x03de, 0x0000}, 362 {0x03df, 0x2000}, 363 {0x03e0, 0x0000}, 364 {0x03e1, 0x0000}, 365 {0x03e2, 0x0000}, 366 {0x03e3, 0x0000}, 367 {0x03e4, 0x0000}, 368 {0x03e5, 0x0000}, 369 {0x03e6, 0x0000}, 370 {0x03e7, 0x0000}, 371 {0x03e8, 0x0000}, 372 {0x03e9, 0x0000}, 373 {0x03ea, 0x0000}, 374 {0x03eb, 0x0000}, 375 {0x03ec, 0x0000}, 376 {0x03ed, 0x0000}, 377 {0x03ee, 0x0000}, 378 {0x03ef, 0x0000}, 379 {0x03f0, 0x0800}, 380 {0x03f1, 0x0800}, 381 {0x03f2, 0x0800}, 382 {0x03f3, 0x0800}, 383 }; 384 EXPORT_SYMBOL_GPL(rt5682_reg); 385 386 bool rt5682_volatile_register(struct device *dev, unsigned int reg) 387 { 388 switch (reg) { 389 case RT5682_RESET: 390 case RT5682_CBJ_CTRL_2: 391 case RT5682_INT_ST_1: 392 case RT5682_4BTN_IL_CMD_1: 393 case RT5682_AJD1_CTRL: 394 case RT5682_HP_CALIB_CTRL_1: 395 case RT5682_DEVICE_ID: 396 case RT5682_I2C_MODE: 397 case RT5682_HP_CALIB_CTRL_10: 398 case RT5682_EFUSE_CTRL_2: 399 case RT5682_JD_TOP_VC_VTRL: 400 case RT5682_HP_IMP_SENS_CTRL_19: 401 case RT5682_IL_CMD_1: 402 case RT5682_SAR_IL_CMD_2: 403 case RT5682_SAR_IL_CMD_4: 404 case RT5682_SAR_IL_CMD_10: 405 case RT5682_SAR_IL_CMD_11: 406 case RT5682_EFUSE_CTRL_6...RT5682_EFUSE_CTRL_11: 407 case RT5682_HP_CALIB_STA_1...RT5682_HP_CALIB_STA_11: 408 return true; 409 default: 410 return false; 411 } 412 } 413 EXPORT_SYMBOL_GPL(rt5682_volatile_register); 414 415 bool rt5682_readable_register(struct device *dev, unsigned int reg) 416 { 417 switch (reg) { 418 case RT5682_RESET: 419 case RT5682_VERSION_ID: 420 case RT5682_VENDOR_ID: 421 case RT5682_DEVICE_ID: 422 case RT5682_HP_CTRL_1: 423 case RT5682_HP_CTRL_2: 424 case RT5682_HPL_GAIN: 425 case RT5682_HPR_GAIN: 426 case RT5682_I2C_CTRL: 427 case RT5682_CBJ_BST_CTRL: 428 case RT5682_CBJ_CTRL_1: 429 case RT5682_CBJ_CTRL_2: 430 case RT5682_CBJ_CTRL_3: 431 case RT5682_CBJ_CTRL_4: 432 case RT5682_CBJ_CTRL_5: 433 case RT5682_CBJ_CTRL_6: 434 case RT5682_CBJ_CTRL_7: 435 case RT5682_DAC1_DIG_VOL: 436 case RT5682_STO1_ADC_DIG_VOL: 437 case RT5682_STO1_ADC_BOOST: 438 case RT5682_HP_IMP_GAIN_1: 439 case RT5682_HP_IMP_GAIN_2: 440 case RT5682_SIDETONE_CTRL: 441 case RT5682_STO1_ADC_MIXER: 442 case RT5682_AD_DA_MIXER: 443 case RT5682_STO1_DAC_MIXER: 444 case RT5682_A_DAC1_MUX: 445 case RT5682_DIG_INF2_DATA: 446 case RT5682_REC_MIXER: 447 case RT5682_CAL_REC: 448 case RT5682_ALC_BACK_GAIN: 449 case RT5682_PWR_DIG_1: 450 case RT5682_PWR_DIG_2: 451 case RT5682_PWR_ANLG_1: 452 case RT5682_PWR_ANLG_2: 453 case RT5682_PWR_ANLG_3: 454 case RT5682_PWR_MIXER: 455 case RT5682_PWR_VOL: 456 case RT5682_CLK_DET: 457 case RT5682_RESET_LPF_CTRL: 458 case RT5682_RESET_HPF_CTRL: 459 case RT5682_DMIC_CTRL_1: 460 case RT5682_I2S1_SDP: 461 case RT5682_I2S2_SDP: 462 case RT5682_ADDA_CLK_1: 463 case RT5682_ADDA_CLK_2: 464 case RT5682_I2S1_F_DIV_CTRL_1: 465 case RT5682_I2S1_F_DIV_CTRL_2: 466 case RT5682_TDM_CTRL: 467 case RT5682_TDM_ADDA_CTRL_1: 468 case RT5682_TDM_ADDA_CTRL_2: 469 case RT5682_DATA_SEL_CTRL_1: 470 case RT5682_TDM_TCON_CTRL: 471 case RT5682_GLB_CLK: 472 case RT5682_PLL_CTRL_1: 473 case RT5682_PLL_CTRL_2: 474 case RT5682_PLL_TRACK_1: 475 case RT5682_PLL_TRACK_2: 476 case RT5682_PLL_TRACK_3: 477 case RT5682_PLL_TRACK_4: 478 case RT5682_PLL_TRACK_5: 479 case RT5682_PLL_TRACK_6: 480 case RT5682_PLL_TRACK_11: 481 case RT5682_SDW_REF_CLK: 482 case RT5682_DEPOP_1: 483 case RT5682_DEPOP_2: 484 case RT5682_HP_CHARGE_PUMP_1: 485 case RT5682_HP_CHARGE_PUMP_2: 486 case RT5682_MICBIAS_1: 487 case RT5682_MICBIAS_2: 488 case RT5682_PLL_TRACK_12: 489 case RT5682_PLL_TRACK_14: 490 case RT5682_PLL2_CTRL_1: 491 case RT5682_PLL2_CTRL_2: 492 case RT5682_PLL2_CTRL_3: 493 case RT5682_PLL2_CTRL_4: 494 case RT5682_RC_CLK_CTRL: 495 case RT5682_I2S_M_CLK_CTRL_1: 496 case RT5682_I2S2_F_DIV_CTRL_1: 497 case RT5682_I2S2_F_DIV_CTRL_2: 498 case RT5682_EQ_CTRL_1: 499 case RT5682_EQ_CTRL_2: 500 case RT5682_IRQ_CTRL_1: 501 case RT5682_IRQ_CTRL_2: 502 case RT5682_IRQ_CTRL_3: 503 case RT5682_IRQ_CTRL_4: 504 case RT5682_INT_ST_1: 505 case RT5682_GPIO_CTRL_1: 506 case RT5682_GPIO_CTRL_2: 507 case RT5682_GPIO_CTRL_3: 508 case RT5682_HP_AMP_DET_CTRL_1: 509 case RT5682_HP_AMP_DET_CTRL_2: 510 case RT5682_MID_HP_AMP_DET: 511 case RT5682_LOW_HP_AMP_DET: 512 case RT5682_DELAY_BUF_CTRL: 513 case RT5682_SV_ZCD_1: 514 case RT5682_SV_ZCD_2: 515 case RT5682_IL_CMD_1: 516 case RT5682_IL_CMD_2: 517 case RT5682_IL_CMD_3: 518 case RT5682_IL_CMD_4: 519 case RT5682_IL_CMD_5: 520 case RT5682_IL_CMD_6: 521 case RT5682_4BTN_IL_CMD_1: 522 case RT5682_4BTN_IL_CMD_2: 523 case RT5682_4BTN_IL_CMD_3: 524 case RT5682_4BTN_IL_CMD_4: 525 case RT5682_4BTN_IL_CMD_5: 526 case RT5682_4BTN_IL_CMD_6: 527 case RT5682_4BTN_IL_CMD_7: 528 case RT5682_ADC_STO1_HP_CTRL_1: 529 case RT5682_ADC_STO1_HP_CTRL_2: 530 case RT5682_AJD1_CTRL: 531 case RT5682_JD1_THD: 532 case RT5682_JD2_THD: 533 case RT5682_JD_CTRL_1: 534 case RT5682_DUMMY_1: 535 case RT5682_DUMMY_2: 536 case RT5682_DUMMY_3: 537 case RT5682_DAC_ADC_DIG_VOL1: 538 case RT5682_BIAS_CUR_CTRL_2: 539 case RT5682_BIAS_CUR_CTRL_3: 540 case RT5682_BIAS_CUR_CTRL_4: 541 case RT5682_BIAS_CUR_CTRL_5: 542 case RT5682_BIAS_CUR_CTRL_6: 543 case RT5682_BIAS_CUR_CTRL_7: 544 case RT5682_BIAS_CUR_CTRL_8: 545 case RT5682_BIAS_CUR_CTRL_9: 546 case RT5682_BIAS_CUR_CTRL_10: 547 case RT5682_VREF_REC_OP_FB_CAP_CTRL: 548 case RT5682_CHARGE_PUMP_1: 549 case RT5682_DIG_IN_CTRL_1: 550 case RT5682_PAD_DRIVING_CTRL: 551 case RT5682_SOFT_RAMP_DEPOP: 552 case RT5682_CHOP_DAC: 553 case RT5682_CHOP_ADC: 554 case RT5682_CALIB_ADC_CTRL: 555 case RT5682_VOL_TEST: 556 case RT5682_SPKVDD_DET_STA: 557 case RT5682_TEST_MODE_CTRL_1: 558 case RT5682_TEST_MODE_CTRL_2: 559 case RT5682_TEST_MODE_CTRL_3: 560 case RT5682_TEST_MODE_CTRL_4: 561 case RT5682_TEST_MODE_CTRL_5: 562 case RT5682_PLL1_INTERNAL: 563 case RT5682_PLL2_INTERNAL: 564 case RT5682_STO_NG2_CTRL_1: 565 case RT5682_STO_NG2_CTRL_2: 566 case RT5682_STO_NG2_CTRL_3: 567 case RT5682_STO_NG2_CTRL_4: 568 case RT5682_STO_NG2_CTRL_5: 569 case RT5682_STO_NG2_CTRL_6: 570 case RT5682_STO_NG2_CTRL_7: 571 case RT5682_STO_NG2_CTRL_8: 572 case RT5682_STO_NG2_CTRL_9: 573 case RT5682_STO_NG2_CTRL_10: 574 case RT5682_STO1_DAC_SIL_DET: 575 case RT5682_SIL_PSV_CTRL1: 576 case RT5682_SIL_PSV_CTRL2: 577 case RT5682_SIL_PSV_CTRL3: 578 case RT5682_SIL_PSV_CTRL4: 579 case RT5682_SIL_PSV_CTRL5: 580 case RT5682_HP_IMP_SENS_CTRL_01: 581 case RT5682_HP_IMP_SENS_CTRL_02: 582 case RT5682_HP_IMP_SENS_CTRL_03: 583 case RT5682_HP_IMP_SENS_CTRL_04: 584 case RT5682_HP_IMP_SENS_CTRL_05: 585 case RT5682_HP_IMP_SENS_CTRL_06: 586 case RT5682_HP_IMP_SENS_CTRL_07: 587 case RT5682_HP_IMP_SENS_CTRL_08: 588 case RT5682_HP_IMP_SENS_CTRL_09: 589 case RT5682_HP_IMP_SENS_CTRL_10: 590 case RT5682_HP_IMP_SENS_CTRL_11: 591 case RT5682_HP_IMP_SENS_CTRL_12: 592 case RT5682_HP_IMP_SENS_CTRL_13: 593 case RT5682_HP_IMP_SENS_CTRL_14: 594 case RT5682_HP_IMP_SENS_CTRL_15: 595 case RT5682_HP_IMP_SENS_CTRL_16: 596 case RT5682_HP_IMP_SENS_CTRL_17: 597 case RT5682_HP_IMP_SENS_CTRL_18: 598 case RT5682_HP_IMP_SENS_CTRL_19: 599 case RT5682_HP_IMP_SENS_CTRL_20: 600 case RT5682_HP_IMP_SENS_CTRL_21: 601 case RT5682_HP_IMP_SENS_CTRL_22: 602 case RT5682_HP_IMP_SENS_CTRL_23: 603 case RT5682_HP_IMP_SENS_CTRL_24: 604 case RT5682_HP_IMP_SENS_CTRL_25: 605 case RT5682_HP_IMP_SENS_CTRL_26: 606 case RT5682_HP_IMP_SENS_CTRL_27: 607 case RT5682_HP_IMP_SENS_CTRL_28: 608 case RT5682_HP_IMP_SENS_CTRL_29: 609 case RT5682_HP_IMP_SENS_CTRL_30: 610 case RT5682_HP_IMP_SENS_CTRL_31: 611 case RT5682_HP_IMP_SENS_CTRL_32: 612 case RT5682_HP_IMP_SENS_CTRL_33: 613 case RT5682_HP_IMP_SENS_CTRL_34: 614 case RT5682_HP_IMP_SENS_CTRL_35: 615 case RT5682_HP_IMP_SENS_CTRL_36: 616 case RT5682_HP_IMP_SENS_CTRL_37: 617 case RT5682_HP_IMP_SENS_CTRL_38: 618 case RT5682_HP_IMP_SENS_CTRL_39: 619 case RT5682_HP_IMP_SENS_CTRL_40: 620 case RT5682_HP_IMP_SENS_CTRL_41: 621 case RT5682_HP_IMP_SENS_CTRL_42: 622 case RT5682_HP_IMP_SENS_CTRL_43: 623 case RT5682_HP_LOGIC_CTRL_1: 624 case RT5682_HP_LOGIC_CTRL_2: 625 case RT5682_HP_LOGIC_CTRL_3: 626 case RT5682_HP_CALIB_CTRL_1: 627 case RT5682_HP_CALIB_CTRL_2: 628 case RT5682_HP_CALIB_CTRL_3: 629 case RT5682_HP_CALIB_CTRL_4: 630 case RT5682_HP_CALIB_CTRL_5: 631 case RT5682_HP_CALIB_CTRL_6: 632 case RT5682_HP_CALIB_CTRL_7: 633 case RT5682_HP_CALIB_CTRL_9: 634 case RT5682_HP_CALIB_CTRL_10: 635 case RT5682_HP_CALIB_CTRL_11: 636 case RT5682_HP_CALIB_STA_1: 637 case RT5682_HP_CALIB_STA_2: 638 case RT5682_HP_CALIB_STA_3: 639 case RT5682_HP_CALIB_STA_4: 640 case RT5682_HP_CALIB_STA_5: 641 case RT5682_HP_CALIB_STA_6: 642 case RT5682_HP_CALIB_STA_7: 643 case RT5682_HP_CALIB_STA_8: 644 case RT5682_HP_CALIB_STA_9: 645 case RT5682_HP_CALIB_STA_10: 646 case RT5682_HP_CALIB_STA_11: 647 case RT5682_SAR_IL_CMD_1: 648 case RT5682_SAR_IL_CMD_2: 649 case RT5682_SAR_IL_CMD_3: 650 case RT5682_SAR_IL_CMD_4: 651 case RT5682_SAR_IL_CMD_5: 652 case RT5682_SAR_IL_CMD_6: 653 case RT5682_SAR_IL_CMD_7: 654 case RT5682_SAR_IL_CMD_8: 655 case RT5682_SAR_IL_CMD_9: 656 case RT5682_SAR_IL_CMD_10: 657 case RT5682_SAR_IL_CMD_11: 658 case RT5682_SAR_IL_CMD_12: 659 case RT5682_SAR_IL_CMD_13: 660 case RT5682_EFUSE_CTRL_1: 661 case RT5682_EFUSE_CTRL_2: 662 case RT5682_EFUSE_CTRL_3: 663 case RT5682_EFUSE_CTRL_4: 664 case RT5682_EFUSE_CTRL_5: 665 case RT5682_EFUSE_CTRL_6: 666 case RT5682_EFUSE_CTRL_7: 667 case RT5682_EFUSE_CTRL_8: 668 case RT5682_EFUSE_CTRL_9: 669 case RT5682_EFUSE_CTRL_10: 670 case RT5682_EFUSE_CTRL_11: 671 case RT5682_JD_TOP_VC_VTRL: 672 case RT5682_DRC1_CTRL_0: 673 case RT5682_DRC1_CTRL_1: 674 case RT5682_DRC1_CTRL_2: 675 case RT5682_DRC1_CTRL_3: 676 case RT5682_DRC1_CTRL_4: 677 case RT5682_DRC1_CTRL_5: 678 case RT5682_DRC1_CTRL_6: 679 case RT5682_DRC1_HARD_LMT_CTRL_1: 680 case RT5682_DRC1_HARD_LMT_CTRL_2: 681 case RT5682_DRC1_PRIV_1: 682 case RT5682_DRC1_PRIV_2: 683 case RT5682_DRC1_PRIV_3: 684 case RT5682_DRC1_PRIV_4: 685 case RT5682_DRC1_PRIV_5: 686 case RT5682_DRC1_PRIV_6: 687 case RT5682_DRC1_PRIV_7: 688 case RT5682_DRC1_PRIV_8: 689 case RT5682_EQ_AUTO_RCV_CTRL1: 690 case RT5682_EQ_AUTO_RCV_CTRL2: 691 case RT5682_EQ_AUTO_RCV_CTRL3: 692 case RT5682_EQ_AUTO_RCV_CTRL4: 693 case RT5682_EQ_AUTO_RCV_CTRL5: 694 case RT5682_EQ_AUTO_RCV_CTRL6: 695 case RT5682_EQ_AUTO_RCV_CTRL7: 696 case RT5682_EQ_AUTO_RCV_CTRL8: 697 case RT5682_EQ_AUTO_RCV_CTRL9: 698 case RT5682_EQ_AUTO_RCV_CTRL10: 699 case RT5682_EQ_AUTO_RCV_CTRL11: 700 case RT5682_EQ_AUTO_RCV_CTRL12: 701 case RT5682_EQ_AUTO_RCV_CTRL13: 702 case RT5682_ADC_L_EQ_LPF1_A1: 703 case RT5682_R_EQ_LPF1_A1: 704 case RT5682_L_EQ_LPF1_H0: 705 case RT5682_R_EQ_LPF1_H0: 706 case RT5682_L_EQ_BPF1_A1: 707 case RT5682_R_EQ_BPF1_A1: 708 case RT5682_L_EQ_BPF1_A2: 709 case RT5682_R_EQ_BPF1_A2: 710 case RT5682_L_EQ_BPF1_H0: 711 case RT5682_R_EQ_BPF1_H0: 712 case RT5682_L_EQ_BPF2_A1: 713 case RT5682_R_EQ_BPF2_A1: 714 case RT5682_L_EQ_BPF2_A2: 715 case RT5682_R_EQ_BPF2_A2: 716 case RT5682_L_EQ_BPF2_H0: 717 case RT5682_R_EQ_BPF2_H0: 718 case RT5682_L_EQ_BPF3_A1: 719 case RT5682_R_EQ_BPF3_A1: 720 case RT5682_L_EQ_BPF3_A2: 721 case RT5682_R_EQ_BPF3_A2: 722 case RT5682_L_EQ_BPF3_H0: 723 case RT5682_R_EQ_BPF3_H0: 724 case RT5682_L_EQ_BPF4_A1: 725 case RT5682_R_EQ_BPF4_A1: 726 case RT5682_L_EQ_BPF4_A2: 727 case RT5682_R_EQ_BPF4_A2: 728 case RT5682_L_EQ_BPF4_H0: 729 case RT5682_R_EQ_BPF4_H0: 730 case RT5682_L_EQ_HPF1_A1: 731 case RT5682_R_EQ_HPF1_A1: 732 case RT5682_L_EQ_HPF1_H0: 733 case RT5682_R_EQ_HPF1_H0: 734 case RT5682_L_EQ_PRE_VOL: 735 case RT5682_R_EQ_PRE_VOL: 736 case RT5682_L_EQ_POST_VOL: 737 case RT5682_R_EQ_POST_VOL: 738 case RT5682_I2C_MODE: 739 return true; 740 default: 741 return false; 742 } 743 } 744 EXPORT_SYMBOL_GPL(rt5682_readable_register); 745 746 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6525, 75, 0); 747 static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0); 748 static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0); 749 750 /* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */ 751 static const DECLARE_TLV_DB_RANGE(bst_tlv, 752 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0), 753 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0), 754 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0), 755 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0), 756 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0), 757 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0), 758 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0) 759 ); 760 761 /* Interface data select */ 762 static const char * const rt5682_data_select[] = { 763 "L/R", "R/L", "L/L", "R/R" 764 }; 765 766 static SOC_ENUM_SINGLE_DECL(rt5682_if2_adc_enum, 767 RT5682_DIG_INF2_DATA, RT5682_IF2_ADC_SEL_SFT, rt5682_data_select); 768 769 static SOC_ENUM_SINGLE_DECL(rt5682_if1_01_adc_enum, 770 RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC1_SEL_SFT, rt5682_data_select); 771 772 static SOC_ENUM_SINGLE_DECL(rt5682_if1_23_adc_enum, 773 RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC2_SEL_SFT, rt5682_data_select); 774 775 static SOC_ENUM_SINGLE_DECL(rt5682_if1_45_adc_enum, 776 RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC3_SEL_SFT, rt5682_data_select); 777 778 static SOC_ENUM_SINGLE_DECL(rt5682_if1_67_adc_enum, 779 RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC4_SEL_SFT, rt5682_data_select); 780 781 static const struct snd_kcontrol_new rt5682_if2_adc_swap_mux = 782 SOC_DAPM_ENUM("IF2 ADC Swap Mux", rt5682_if2_adc_enum); 783 784 static const struct snd_kcontrol_new rt5682_if1_01_adc_swap_mux = 785 SOC_DAPM_ENUM("IF1 01 ADC Swap Mux", rt5682_if1_01_adc_enum); 786 787 static const struct snd_kcontrol_new rt5682_if1_23_adc_swap_mux = 788 SOC_DAPM_ENUM("IF1 23 ADC Swap Mux", rt5682_if1_23_adc_enum); 789 790 static const struct snd_kcontrol_new rt5682_if1_45_adc_swap_mux = 791 SOC_DAPM_ENUM("IF1 45 ADC Swap Mux", rt5682_if1_45_adc_enum); 792 793 static const struct snd_kcontrol_new rt5682_if1_67_adc_swap_mux = 794 SOC_DAPM_ENUM("IF1 67 ADC Swap Mux", rt5682_if1_67_adc_enum); 795 796 static const char * const rt5682_dac_select[] = { 797 "IF1", "SOUND" 798 }; 799 800 static SOC_ENUM_SINGLE_DECL(rt5682_dacl_enum, 801 RT5682_AD_DA_MIXER, RT5682_DAC1_L_SEL_SFT, rt5682_dac_select); 802 803 static const struct snd_kcontrol_new rt5682_dac_l_mux = 804 SOC_DAPM_ENUM("DAC L Mux", rt5682_dacl_enum); 805 806 static SOC_ENUM_SINGLE_DECL(rt5682_dacr_enum, 807 RT5682_AD_DA_MIXER, RT5682_DAC1_R_SEL_SFT, rt5682_dac_select); 808 809 static const struct snd_kcontrol_new rt5682_dac_r_mux = 810 SOC_DAPM_ENUM("DAC R Mux", rt5682_dacr_enum); 811 812 void rt5682_reset(struct rt5682_priv *rt5682) 813 { 814 regmap_write(rt5682->regmap, RT5682_RESET, 0); 815 if (!rt5682->is_sdw) 816 regmap_write(rt5682->regmap, RT5682_I2C_MODE, 1); 817 } 818 EXPORT_SYMBOL_GPL(rt5682_reset); 819 820 /** 821 * rt5682_sel_asrc_clk_src - select ASRC clock source for a set of filters 822 * @component: SoC audio component device. 823 * @filter_mask: mask of filters. 824 * @clk_src: clock source 825 * 826 * The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5682 can 827 * only support standard 32fs or 64fs i2s format, ASRC should be enabled to 828 * support special i2s clock format such as Intel's 100fs(100 * sampling rate). 829 * ASRC function will track i2s clock and generate a corresponding system clock 830 * for codec. This function provides an API to select the clock source for a 831 * set of filters specified by the mask. And the component driver will turn on 832 * ASRC for these filters if ASRC is selected as their clock source. 833 */ 834 int rt5682_sel_asrc_clk_src(struct snd_soc_component *component, 835 unsigned int filter_mask, unsigned int clk_src) 836 { 837 switch (clk_src) { 838 case RT5682_CLK_SEL_SYS: 839 case RT5682_CLK_SEL_I2S1_ASRC: 840 case RT5682_CLK_SEL_I2S2_ASRC: 841 break; 842 843 default: 844 return -EINVAL; 845 } 846 847 if (filter_mask & RT5682_DA_STEREO1_FILTER) { 848 snd_soc_component_update_bits(component, RT5682_PLL_TRACK_2, 849 RT5682_FILTER_CLK_SEL_MASK, 850 clk_src << RT5682_FILTER_CLK_SEL_SFT); 851 } 852 853 if (filter_mask & RT5682_AD_STEREO1_FILTER) { 854 snd_soc_component_update_bits(component, RT5682_PLL_TRACK_3, 855 RT5682_FILTER_CLK_SEL_MASK, 856 clk_src << RT5682_FILTER_CLK_SEL_SFT); 857 } 858 859 return 0; 860 } 861 EXPORT_SYMBOL_GPL(rt5682_sel_asrc_clk_src); 862 863 static int rt5682_button_detect(struct snd_soc_component *component) 864 { 865 int btn_type, val; 866 867 val = snd_soc_component_read(component, RT5682_4BTN_IL_CMD_1); 868 btn_type = val & 0xfff0; 869 snd_soc_component_write(component, RT5682_4BTN_IL_CMD_1, val); 870 dev_dbg(component->dev, "%s btn_type=%x\n", __func__, btn_type); 871 snd_soc_component_update_bits(component, 872 RT5682_SAR_IL_CMD_2, 0x10, 0x10); 873 874 return btn_type; 875 } 876 877 static void rt5682_enable_push_button_irq(struct snd_soc_component *component, 878 bool enable) 879 { 880 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 881 882 if (enable) { 883 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1, 884 RT5682_SAR_BUTT_DET_MASK, RT5682_SAR_BUTT_DET_EN); 885 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_13, 886 RT5682_SAR_SOUR_MASK, RT5682_SAR_SOUR_BTN); 887 snd_soc_component_write(component, RT5682_IL_CMD_1, 0x0040); 888 snd_soc_component_update_bits(component, RT5682_4BTN_IL_CMD_2, 889 RT5682_4BTN_IL_MASK | RT5682_4BTN_IL_RST_MASK, 890 RT5682_4BTN_IL_EN | RT5682_4BTN_IL_NOR); 891 if (rt5682->is_sdw) 892 snd_soc_component_update_bits(component, 893 RT5682_IRQ_CTRL_3, 894 RT5682_IL_IRQ_MASK | RT5682_IL_IRQ_TYPE_MASK, 895 RT5682_IL_IRQ_EN | RT5682_IL_IRQ_PUL); 896 else 897 snd_soc_component_update_bits(component, 898 RT5682_IRQ_CTRL_3, RT5682_IL_IRQ_MASK, 899 RT5682_IL_IRQ_EN); 900 } else { 901 snd_soc_component_update_bits(component, RT5682_IRQ_CTRL_3, 902 RT5682_IL_IRQ_MASK, RT5682_IL_IRQ_DIS); 903 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1, 904 RT5682_SAR_BUTT_DET_MASK, RT5682_SAR_BUTT_DET_DIS); 905 snd_soc_component_update_bits(component, RT5682_4BTN_IL_CMD_2, 906 RT5682_4BTN_IL_MASK, RT5682_4BTN_IL_DIS); 907 snd_soc_component_update_bits(component, RT5682_4BTN_IL_CMD_2, 908 RT5682_4BTN_IL_RST_MASK, RT5682_4BTN_IL_RST); 909 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_13, 910 RT5682_SAR_SOUR_MASK, RT5682_SAR_SOUR_TYPE); 911 } 912 } 913 914 /** 915 * rt5682_headset_detect - Detect headset. 916 * @component: SoC audio component device. 917 * @jack_insert: Jack insert or not. 918 * 919 * Detect whether is headset or not when jack inserted. 920 * 921 * Returns detect status. 922 */ 923 int rt5682_headset_detect(struct snd_soc_component *component, int jack_insert) 924 { 925 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 926 struct snd_soc_dapm_context *dapm = &component->dapm; 927 unsigned int val, count; 928 929 if (jack_insert) { 930 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_1, 931 RT5682_PWR_VREF2 | RT5682_PWR_MB, 932 RT5682_PWR_VREF2 | RT5682_PWR_MB); 933 snd_soc_component_update_bits(component, 934 RT5682_PWR_ANLG_1, RT5682_PWR_FV2, 0); 935 usleep_range(15000, 20000); 936 snd_soc_component_update_bits(component, 937 RT5682_PWR_ANLG_1, RT5682_PWR_FV2, RT5682_PWR_FV2); 938 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_3, 939 RT5682_PWR_CBJ, RT5682_PWR_CBJ); 940 snd_soc_component_update_bits(component, 941 RT5682_HP_CHARGE_PUMP_1, 942 RT5682_OSW_L_MASK | RT5682_OSW_R_MASK, 0); 943 snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1, 944 RT5682_TRIG_JD_MASK, RT5682_TRIG_JD_HIGH); 945 946 count = 0; 947 val = snd_soc_component_read(component, RT5682_CBJ_CTRL_2) 948 & RT5682_JACK_TYPE_MASK; 949 while (val == 0 && count < 50) { 950 usleep_range(10000, 15000); 951 val = snd_soc_component_read(component, 952 RT5682_CBJ_CTRL_2) & RT5682_JACK_TYPE_MASK; 953 count++; 954 } 955 956 switch (val) { 957 case 0x1: 958 case 0x2: 959 rt5682->jack_type = SND_JACK_HEADSET; 960 snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1, 961 RT5682_FAST_OFF_MASK, RT5682_FAST_OFF_EN); 962 rt5682_enable_push_button_irq(component, true); 963 break; 964 default: 965 rt5682->jack_type = SND_JACK_HEADPHONE; 966 break; 967 } 968 969 snd_soc_component_update_bits(component, 970 RT5682_HP_CHARGE_PUMP_1, 971 RT5682_OSW_L_MASK | RT5682_OSW_R_MASK, 972 RT5682_OSW_L_EN | RT5682_OSW_R_EN); 973 snd_soc_component_update_bits(component, RT5682_MICBIAS_2, 974 RT5682_PWR_CLK25M_MASK | RT5682_PWR_CLK1M_MASK, 975 RT5682_PWR_CLK25M_PU | RT5682_PWR_CLK1M_PU); 976 } else { 977 rt5682_enable_push_button_irq(component, false); 978 snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1, 979 RT5682_TRIG_JD_MASK, RT5682_TRIG_JD_LOW); 980 if (!snd_soc_dapm_get_pin_status(dapm, "MICBIAS") && 981 !snd_soc_dapm_get_pin_status(dapm, "PLL1") && 982 !snd_soc_dapm_get_pin_status(dapm, "PLL2B")) 983 snd_soc_component_update_bits(component, 984 RT5682_PWR_ANLG_1, RT5682_PWR_MB, 0); 985 if (!snd_soc_dapm_get_pin_status(dapm, "Vref2") && 986 !snd_soc_dapm_get_pin_status(dapm, "PLL1") && 987 !snd_soc_dapm_get_pin_status(dapm, "PLL2B")) 988 snd_soc_component_update_bits(component, 989 RT5682_PWR_ANLG_1, RT5682_PWR_VREF2, 0); 990 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_3, 991 RT5682_PWR_CBJ, 0); 992 snd_soc_component_update_bits(component, RT5682_MICBIAS_2, 993 RT5682_PWR_CLK25M_MASK | RT5682_PWR_CLK1M_MASK, 994 RT5682_PWR_CLK25M_PD | RT5682_PWR_CLK1M_PD); 995 snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1, 996 RT5682_FAST_OFF_MASK, RT5682_FAST_OFF_DIS); 997 998 rt5682->jack_type = 0; 999 } 1000 1001 dev_dbg(component->dev, "jack_type = %d\n", rt5682->jack_type); 1002 return rt5682->jack_type; 1003 } 1004 EXPORT_SYMBOL_GPL(rt5682_headset_detect); 1005 1006 static int rt5682_set_jack_detect(struct snd_soc_component *component, 1007 struct snd_soc_jack *hs_jack, void *data) 1008 { 1009 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 1010 1011 rt5682->hs_jack = hs_jack; 1012 1013 if (!hs_jack) { 1014 regmap_update_bits(rt5682->regmap, RT5682_IRQ_CTRL_2, 1015 RT5682_JD1_EN_MASK, RT5682_JD1_DIS); 1016 regmap_update_bits(rt5682->regmap, RT5682_RC_CLK_CTRL, 1017 RT5682_POW_JDH | RT5682_POW_JDL, 0); 1018 cancel_delayed_work_sync(&rt5682->jack_detect_work); 1019 1020 return 0; 1021 } 1022 1023 if (!rt5682->is_sdw) { 1024 switch (rt5682->pdata.jd_src) { 1025 case RT5682_JD1: 1026 snd_soc_component_update_bits(component, 1027 RT5682_CBJ_CTRL_5, 0x0700, 0x0600); 1028 snd_soc_component_update_bits(component, 1029 RT5682_CBJ_CTRL_2, RT5682_EXT_JD_SRC, 1030 RT5682_EXT_JD_SRC_MANUAL); 1031 snd_soc_component_write(component, RT5682_CBJ_CTRL_1, 1032 0xd142); 1033 snd_soc_component_update_bits(component, 1034 RT5682_CBJ_CTRL_3, RT5682_CBJ_IN_BUF_EN, 1035 RT5682_CBJ_IN_BUF_EN); 1036 snd_soc_component_update_bits(component, 1037 RT5682_SAR_IL_CMD_1, RT5682_SAR_POW_MASK, 1038 RT5682_SAR_POW_EN); 1039 regmap_update_bits(rt5682->regmap, RT5682_GPIO_CTRL_1, 1040 RT5682_GP1_PIN_MASK, RT5682_GP1_PIN_IRQ); 1041 regmap_update_bits(rt5682->regmap, RT5682_RC_CLK_CTRL, 1042 RT5682_POW_IRQ | RT5682_POW_JDH | 1043 RT5682_POW_ANA, RT5682_POW_IRQ | 1044 RT5682_POW_JDH | RT5682_POW_ANA); 1045 regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_2, 1046 RT5682_PWR_JDH, RT5682_PWR_JDH); 1047 regmap_update_bits(rt5682->regmap, RT5682_IRQ_CTRL_2, 1048 RT5682_JD1_EN_MASK | RT5682_JD1_POL_MASK, 1049 RT5682_JD1_EN | RT5682_JD1_POL_NOR); 1050 regmap_update_bits(rt5682->regmap, RT5682_4BTN_IL_CMD_4, 1051 0x7f7f, (rt5682->pdata.btndet_delay << 8 | 1052 rt5682->pdata.btndet_delay)); 1053 regmap_update_bits(rt5682->regmap, RT5682_4BTN_IL_CMD_5, 1054 0x7f7f, (rt5682->pdata.btndet_delay << 8 | 1055 rt5682->pdata.btndet_delay)); 1056 regmap_update_bits(rt5682->regmap, RT5682_4BTN_IL_CMD_6, 1057 0x7f7f, (rt5682->pdata.btndet_delay << 8 | 1058 rt5682->pdata.btndet_delay)); 1059 regmap_update_bits(rt5682->regmap, RT5682_4BTN_IL_CMD_7, 1060 0x7f7f, (rt5682->pdata.btndet_delay << 8 | 1061 rt5682->pdata.btndet_delay)); 1062 mod_delayed_work(system_power_efficient_wq, 1063 &rt5682->jack_detect_work, 1064 msecs_to_jiffies(250)); 1065 break; 1066 1067 case RT5682_JD_NULL: 1068 regmap_update_bits(rt5682->regmap, RT5682_IRQ_CTRL_2, 1069 RT5682_JD1_EN_MASK, RT5682_JD1_DIS); 1070 regmap_update_bits(rt5682->regmap, RT5682_RC_CLK_CTRL, 1071 RT5682_POW_JDH | RT5682_POW_JDL, 0); 1072 break; 1073 1074 default: 1075 dev_warn(component->dev, "Wrong JD source\n"); 1076 break; 1077 } 1078 } 1079 1080 return 0; 1081 } 1082 1083 void rt5682_jack_detect_handler(struct work_struct *work) 1084 { 1085 struct rt5682_priv *rt5682 = 1086 container_of(work, struct rt5682_priv, jack_detect_work.work); 1087 int val, btn_type; 1088 1089 while (!rt5682->component) 1090 usleep_range(10000, 15000); 1091 1092 while (!rt5682->component->card->instantiated) 1093 usleep_range(10000, 15000); 1094 1095 mutex_lock(&rt5682->calibrate_mutex); 1096 1097 val = snd_soc_component_read(rt5682->component, RT5682_AJD1_CTRL) 1098 & RT5682_JDH_RS_MASK; 1099 if (!val) { 1100 /* jack in */ 1101 if (rt5682->jack_type == 0) { 1102 /* jack was out, report jack type */ 1103 rt5682->jack_type = 1104 rt5682_headset_detect(rt5682->component, 1); 1105 rt5682->irq_work_delay_time = 0; 1106 } else if ((rt5682->jack_type & SND_JACK_HEADSET) == 1107 SND_JACK_HEADSET) { 1108 /* jack is already in, report button event */ 1109 rt5682->jack_type = SND_JACK_HEADSET; 1110 btn_type = rt5682_button_detect(rt5682->component); 1111 /** 1112 * rt5682 can report three kinds of button behavior, 1113 * one click, double click and hold. However, 1114 * currently we will report button pressed/released 1115 * event. So all the three button behaviors are 1116 * treated as button pressed. 1117 */ 1118 switch (btn_type) { 1119 case 0x8000: 1120 case 0x4000: 1121 case 0x2000: 1122 rt5682->jack_type |= SND_JACK_BTN_0; 1123 break; 1124 case 0x1000: 1125 case 0x0800: 1126 case 0x0400: 1127 rt5682->jack_type |= SND_JACK_BTN_1; 1128 break; 1129 case 0x0200: 1130 case 0x0100: 1131 case 0x0080: 1132 rt5682->jack_type |= SND_JACK_BTN_2; 1133 break; 1134 case 0x0040: 1135 case 0x0020: 1136 case 0x0010: 1137 rt5682->jack_type |= SND_JACK_BTN_3; 1138 break; 1139 case 0x0000: /* unpressed */ 1140 break; 1141 default: 1142 dev_err(rt5682->component->dev, 1143 "Unexpected button code 0x%04x\n", 1144 btn_type); 1145 break; 1146 } 1147 } 1148 } else { 1149 /* jack out */ 1150 rt5682->jack_type = rt5682_headset_detect(rt5682->component, 0); 1151 rt5682->irq_work_delay_time = 50; 1152 } 1153 1154 snd_soc_jack_report(rt5682->hs_jack, rt5682->jack_type, 1155 SND_JACK_HEADSET | 1156 SND_JACK_BTN_0 | SND_JACK_BTN_1 | 1157 SND_JACK_BTN_2 | SND_JACK_BTN_3); 1158 1159 if (!rt5682->is_sdw) { 1160 if (rt5682->jack_type & (SND_JACK_BTN_0 | SND_JACK_BTN_1 | 1161 SND_JACK_BTN_2 | SND_JACK_BTN_3)) 1162 schedule_delayed_work(&rt5682->jd_check_work, 0); 1163 else 1164 cancel_delayed_work_sync(&rt5682->jd_check_work); 1165 } 1166 1167 mutex_unlock(&rt5682->calibrate_mutex); 1168 } 1169 EXPORT_SYMBOL_GPL(rt5682_jack_detect_handler); 1170 1171 static const struct snd_kcontrol_new rt5682_snd_controls[] = { 1172 /* DAC Digital Volume */ 1173 SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5682_DAC1_DIG_VOL, 1174 RT5682_L_VOL_SFT + 1, RT5682_R_VOL_SFT + 1, 87, 0, dac_vol_tlv), 1175 1176 /* IN Boost Volume */ 1177 SOC_SINGLE_TLV("CBJ Boost Volume", RT5682_CBJ_BST_CTRL, 1178 RT5682_BST_CBJ_SFT, 8, 0, bst_tlv), 1179 1180 /* ADC Digital Volume Control */ 1181 SOC_DOUBLE("STO1 ADC Capture Switch", RT5682_STO1_ADC_DIG_VOL, 1182 RT5682_L_MUTE_SFT, RT5682_R_MUTE_SFT, 1, 1), 1183 SOC_DOUBLE_TLV("STO1 ADC Capture Volume", RT5682_STO1_ADC_DIG_VOL, 1184 RT5682_L_VOL_SFT + 1, RT5682_R_VOL_SFT + 1, 63, 0, adc_vol_tlv), 1185 1186 /* ADC Boost Volume Control */ 1187 SOC_DOUBLE_TLV("STO1 ADC Boost Gain Volume", RT5682_STO1_ADC_BOOST, 1188 RT5682_STO1_ADC_L_BST_SFT, RT5682_STO1_ADC_R_BST_SFT, 1189 3, 0, adc_bst_tlv), 1190 }; 1191 1192 static int rt5682_div_sel(struct rt5682_priv *rt5682, 1193 int target, const int div[], int size) 1194 { 1195 int i; 1196 1197 if (rt5682->sysclk < target) { 1198 dev_err(rt5682->component->dev, 1199 "sysclk rate %d is too low\n", rt5682->sysclk); 1200 return 0; 1201 } 1202 1203 for (i = 0; i < size - 1; i++) { 1204 dev_dbg(rt5682->component->dev, "div[%d]=%d\n", i, div[i]); 1205 if (target * div[i] == rt5682->sysclk) 1206 return i; 1207 if (target * div[i + 1] > rt5682->sysclk) { 1208 dev_dbg(rt5682->component->dev, 1209 "can't find div for sysclk %d\n", 1210 rt5682->sysclk); 1211 return i; 1212 } 1213 } 1214 1215 if (target * div[i] < rt5682->sysclk) 1216 dev_err(rt5682->component->dev, 1217 "sysclk rate %d is too high\n", rt5682->sysclk); 1218 1219 return size - 1; 1220 } 1221 1222 /** 1223 * set_dmic_clk - Set parameter of dmic. 1224 * 1225 * @w: DAPM widget. 1226 * @kcontrol: The kcontrol of this widget. 1227 * @event: Event id. 1228 * 1229 * Choose dmic clock between 1MHz and 3MHz. 1230 * It is better for clock to approximate 3MHz. 1231 */ 1232 static int set_dmic_clk(struct snd_soc_dapm_widget *w, 1233 struct snd_kcontrol *kcontrol, int event) 1234 { 1235 struct snd_soc_component *component = 1236 snd_soc_dapm_to_component(w->dapm); 1237 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 1238 int idx, dmic_clk_rate = 3072000; 1239 static const int div[] = {2, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, 128}; 1240 1241 if (rt5682->pdata.dmic_clk_rate) 1242 dmic_clk_rate = rt5682->pdata.dmic_clk_rate; 1243 1244 idx = rt5682_div_sel(rt5682, dmic_clk_rate, div, ARRAY_SIZE(div)); 1245 1246 snd_soc_component_update_bits(component, RT5682_DMIC_CTRL_1, 1247 RT5682_DMIC_CLK_MASK, idx << RT5682_DMIC_CLK_SFT); 1248 1249 return 0; 1250 } 1251 1252 static int set_filter_clk(struct snd_soc_dapm_widget *w, 1253 struct snd_kcontrol *kcontrol, int event) 1254 { 1255 struct snd_soc_component *component = 1256 snd_soc_dapm_to_component(w->dapm); 1257 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 1258 int ref, val, reg, idx; 1259 static const int div_f[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32, 48}; 1260 static const int div_o[] = {1, 2, 4, 6, 8, 12, 16, 24, 32, 48}; 1261 1262 if (rt5682->is_sdw) 1263 return 0; 1264 1265 val = snd_soc_component_read(component, RT5682_GPIO_CTRL_1) & 1266 RT5682_GP4_PIN_MASK; 1267 if (w->shift == RT5682_PWR_ADC_S1F_BIT && 1268 val == RT5682_GP4_PIN_ADCDAT2) 1269 ref = 256 * rt5682->lrck[RT5682_AIF2]; 1270 else 1271 ref = 256 * rt5682->lrck[RT5682_AIF1]; 1272 1273 idx = rt5682_div_sel(rt5682, ref, div_f, ARRAY_SIZE(div_f)); 1274 1275 if (w->shift == RT5682_PWR_ADC_S1F_BIT) 1276 reg = RT5682_PLL_TRACK_3; 1277 else 1278 reg = RT5682_PLL_TRACK_2; 1279 1280 snd_soc_component_update_bits(component, reg, 1281 RT5682_FILTER_CLK_DIV_MASK, idx << RT5682_FILTER_CLK_DIV_SFT); 1282 1283 /* select over sample rate */ 1284 for (idx = 0; idx < ARRAY_SIZE(div_o); idx++) { 1285 if (rt5682->sysclk <= 12288000 * div_o[idx]) 1286 break; 1287 } 1288 1289 snd_soc_component_update_bits(component, RT5682_ADDA_CLK_1, 1290 RT5682_ADC_OSR_MASK | RT5682_DAC_OSR_MASK, 1291 (idx << RT5682_ADC_OSR_SFT) | (idx << RT5682_DAC_OSR_SFT)); 1292 1293 return 0; 1294 } 1295 1296 static int is_sys_clk_from_pll1(struct snd_soc_dapm_widget *w, 1297 struct snd_soc_dapm_widget *sink) 1298 { 1299 unsigned int val; 1300 struct snd_soc_component *component = 1301 snd_soc_dapm_to_component(w->dapm); 1302 1303 val = snd_soc_component_read(component, RT5682_GLB_CLK); 1304 val &= RT5682_SCLK_SRC_MASK; 1305 if (val == RT5682_SCLK_SRC_PLL1) 1306 return 1; 1307 else 1308 return 0; 1309 } 1310 1311 static int is_sys_clk_from_pll2(struct snd_soc_dapm_widget *w, 1312 struct snd_soc_dapm_widget *sink) 1313 { 1314 unsigned int val; 1315 struct snd_soc_component *component = 1316 snd_soc_dapm_to_component(w->dapm); 1317 1318 val = snd_soc_component_read(component, RT5682_GLB_CLK); 1319 val &= RT5682_SCLK_SRC_MASK; 1320 if (val == RT5682_SCLK_SRC_PLL2) 1321 return 1; 1322 else 1323 return 0; 1324 } 1325 1326 static int is_using_asrc(struct snd_soc_dapm_widget *w, 1327 struct snd_soc_dapm_widget *sink) 1328 { 1329 unsigned int reg, shift, val; 1330 struct snd_soc_component *component = 1331 snd_soc_dapm_to_component(w->dapm); 1332 1333 switch (w->shift) { 1334 case RT5682_ADC_STO1_ASRC_SFT: 1335 reg = RT5682_PLL_TRACK_3; 1336 shift = RT5682_FILTER_CLK_SEL_SFT; 1337 break; 1338 case RT5682_DAC_STO1_ASRC_SFT: 1339 reg = RT5682_PLL_TRACK_2; 1340 shift = RT5682_FILTER_CLK_SEL_SFT; 1341 break; 1342 default: 1343 return 0; 1344 } 1345 1346 val = (snd_soc_component_read(component, reg) >> shift) & 0xf; 1347 switch (val) { 1348 case RT5682_CLK_SEL_I2S1_ASRC: 1349 case RT5682_CLK_SEL_I2S2_ASRC: 1350 return 1; 1351 default: 1352 return 0; 1353 } 1354 } 1355 1356 /* Digital Mixer */ 1357 static const struct snd_kcontrol_new rt5682_sto1_adc_l_mix[] = { 1358 SOC_DAPM_SINGLE("ADC1 Switch", RT5682_STO1_ADC_MIXER, 1359 RT5682_M_STO1_ADC_L1_SFT, 1, 1), 1360 SOC_DAPM_SINGLE("ADC2 Switch", RT5682_STO1_ADC_MIXER, 1361 RT5682_M_STO1_ADC_L2_SFT, 1, 1), 1362 }; 1363 1364 static const struct snd_kcontrol_new rt5682_sto1_adc_r_mix[] = { 1365 SOC_DAPM_SINGLE("ADC1 Switch", RT5682_STO1_ADC_MIXER, 1366 RT5682_M_STO1_ADC_R1_SFT, 1, 1), 1367 SOC_DAPM_SINGLE("ADC2 Switch", RT5682_STO1_ADC_MIXER, 1368 RT5682_M_STO1_ADC_R2_SFT, 1, 1), 1369 }; 1370 1371 static const struct snd_kcontrol_new rt5682_dac_l_mix[] = { 1372 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5682_AD_DA_MIXER, 1373 RT5682_M_ADCMIX_L_SFT, 1, 1), 1374 SOC_DAPM_SINGLE("DAC1 Switch", RT5682_AD_DA_MIXER, 1375 RT5682_M_DAC1_L_SFT, 1, 1), 1376 }; 1377 1378 static const struct snd_kcontrol_new rt5682_dac_r_mix[] = { 1379 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5682_AD_DA_MIXER, 1380 RT5682_M_ADCMIX_R_SFT, 1, 1), 1381 SOC_DAPM_SINGLE("DAC1 Switch", RT5682_AD_DA_MIXER, 1382 RT5682_M_DAC1_R_SFT, 1, 1), 1383 }; 1384 1385 static const struct snd_kcontrol_new rt5682_sto1_dac_l_mix[] = { 1386 SOC_DAPM_SINGLE("DAC L1 Switch", RT5682_STO1_DAC_MIXER, 1387 RT5682_M_DAC_L1_STO_L_SFT, 1, 1), 1388 SOC_DAPM_SINGLE("DAC R1 Switch", RT5682_STO1_DAC_MIXER, 1389 RT5682_M_DAC_R1_STO_L_SFT, 1, 1), 1390 }; 1391 1392 static const struct snd_kcontrol_new rt5682_sto1_dac_r_mix[] = { 1393 SOC_DAPM_SINGLE("DAC L1 Switch", RT5682_STO1_DAC_MIXER, 1394 RT5682_M_DAC_L1_STO_R_SFT, 1, 1), 1395 SOC_DAPM_SINGLE("DAC R1 Switch", RT5682_STO1_DAC_MIXER, 1396 RT5682_M_DAC_R1_STO_R_SFT, 1, 1), 1397 }; 1398 1399 /* Analog Input Mixer */ 1400 static const struct snd_kcontrol_new rt5682_rec1_l_mix[] = { 1401 SOC_DAPM_SINGLE("CBJ Switch", RT5682_REC_MIXER, 1402 RT5682_M_CBJ_RM1_L_SFT, 1, 1), 1403 }; 1404 1405 /* STO1 ADC1 Source */ 1406 /* MX-26 [13] [5] */ 1407 static const char * const rt5682_sto1_adc1_src[] = { 1408 "DAC MIX", "ADC" 1409 }; 1410 1411 static SOC_ENUM_SINGLE_DECL( 1412 rt5682_sto1_adc1l_enum, RT5682_STO1_ADC_MIXER, 1413 RT5682_STO1_ADC1L_SRC_SFT, rt5682_sto1_adc1_src); 1414 1415 static const struct snd_kcontrol_new rt5682_sto1_adc1l_mux = 1416 SOC_DAPM_ENUM("Stereo1 ADC1L Source", rt5682_sto1_adc1l_enum); 1417 1418 static SOC_ENUM_SINGLE_DECL( 1419 rt5682_sto1_adc1r_enum, RT5682_STO1_ADC_MIXER, 1420 RT5682_STO1_ADC1R_SRC_SFT, rt5682_sto1_adc1_src); 1421 1422 static const struct snd_kcontrol_new rt5682_sto1_adc1r_mux = 1423 SOC_DAPM_ENUM("Stereo1 ADC1L Source", rt5682_sto1_adc1r_enum); 1424 1425 /* STO1 ADC Source */ 1426 /* MX-26 [11:10] [3:2] */ 1427 static const char * const rt5682_sto1_adc_src[] = { 1428 "ADC1 L", "ADC1 R" 1429 }; 1430 1431 static SOC_ENUM_SINGLE_DECL( 1432 rt5682_sto1_adcl_enum, RT5682_STO1_ADC_MIXER, 1433 RT5682_STO1_ADCL_SRC_SFT, rt5682_sto1_adc_src); 1434 1435 static const struct snd_kcontrol_new rt5682_sto1_adcl_mux = 1436 SOC_DAPM_ENUM("Stereo1 ADCL Source", rt5682_sto1_adcl_enum); 1437 1438 static SOC_ENUM_SINGLE_DECL( 1439 rt5682_sto1_adcr_enum, RT5682_STO1_ADC_MIXER, 1440 RT5682_STO1_ADCR_SRC_SFT, rt5682_sto1_adc_src); 1441 1442 static const struct snd_kcontrol_new rt5682_sto1_adcr_mux = 1443 SOC_DAPM_ENUM("Stereo1 ADCR Source", rt5682_sto1_adcr_enum); 1444 1445 /* STO1 ADC2 Source */ 1446 /* MX-26 [12] [4] */ 1447 static const char * const rt5682_sto1_adc2_src[] = { 1448 "DAC MIX", "DMIC" 1449 }; 1450 1451 static SOC_ENUM_SINGLE_DECL( 1452 rt5682_sto1_adc2l_enum, RT5682_STO1_ADC_MIXER, 1453 RT5682_STO1_ADC2L_SRC_SFT, rt5682_sto1_adc2_src); 1454 1455 static const struct snd_kcontrol_new rt5682_sto1_adc2l_mux = 1456 SOC_DAPM_ENUM("Stereo1 ADC2L Source", rt5682_sto1_adc2l_enum); 1457 1458 static SOC_ENUM_SINGLE_DECL( 1459 rt5682_sto1_adc2r_enum, RT5682_STO1_ADC_MIXER, 1460 RT5682_STO1_ADC2R_SRC_SFT, rt5682_sto1_adc2_src); 1461 1462 static const struct snd_kcontrol_new rt5682_sto1_adc2r_mux = 1463 SOC_DAPM_ENUM("Stereo1 ADC2R Source", rt5682_sto1_adc2r_enum); 1464 1465 /* MX-79 [6:4] I2S1 ADC data location */ 1466 static const unsigned int rt5682_if1_adc_slot_values[] = { 1467 0, 1468 2, 1469 4, 1470 6, 1471 }; 1472 1473 static const char * const rt5682_if1_adc_slot_src[] = { 1474 "Slot 0", "Slot 2", "Slot 4", "Slot 6" 1475 }; 1476 1477 static SOC_VALUE_ENUM_SINGLE_DECL(rt5682_if1_adc_slot_enum, 1478 RT5682_TDM_CTRL, RT5682_TDM_ADC_LCA_SFT, RT5682_TDM_ADC_LCA_MASK, 1479 rt5682_if1_adc_slot_src, rt5682_if1_adc_slot_values); 1480 1481 static const struct snd_kcontrol_new rt5682_if1_adc_slot_mux = 1482 SOC_DAPM_ENUM("IF1 ADC Slot location", rt5682_if1_adc_slot_enum); 1483 1484 /* Analog DAC L1 Source, Analog DAC R1 Source*/ 1485 /* MX-2B [4], MX-2B [0]*/ 1486 static const char * const rt5682_alg_dac1_src[] = { 1487 "Stereo1 DAC Mixer", "DAC1" 1488 }; 1489 1490 static SOC_ENUM_SINGLE_DECL( 1491 rt5682_alg_dac_l1_enum, RT5682_A_DAC1_MUX, 1492 RT5682_A_DACL1_SFT, rt5682_alg_dac1_src); 1493 1494 static const struct snd_kcontrol_new rt5682_alg_dac_l1_mux = 1495 SOC_DAPM_ENUM("Analog DAC L1 Source", rt5682_alg_dac_l1_enum); 1496 1497 static SOC_ENUM_SINGLE_DECL( 1498 rt5682_alg_dac_r1_enum, RT5682_A_DAC1_MUX, 1499 RT5682_A_DACR1_SFT, rt5682_alg_dac1_src); 1500 1501 static const struct snd_kcontrol_new rt5682_alg_dac_r1_mux = 1502 SOC_DAPM_ENUM("Analog DAC R1 Source", rt5682_alg_dac_r1_enum); 1503 1504 /* Out Switch */ 1505 static const struct snd_kcontrol_new hpol_switch = 1506 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5682_HP_CTRL_1, 1507 RT5682_L_MUTE_SFT, 1, 1); 1508 static const struct snd_kcontrol_new hpor_switch = 1509 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5682_HP_CTRL_1, 1510 RT5682_R_MUTE_SFT, 1, 1); 1511 1512 static int rt5682_hp_event(struct snd_soc_dapm_widget *w, 1513 struct snd_kcontrol *kcontrol, int event) 1514 { 1515 struct snd_soc_component *component = 1516 snd_soc_dapm_to_component(w->dapm); 1517 1518 switch (event) { 1519 case SND_SOC_DAPM_PRE_PMU: 1520 snd_soc_component_update_bits(component, RT5682_HP_CTRL_2, 1521 RT5682_HP_C2_DAC_AMP_MUTE, 0); 1522 snd_soc_component_update_bits(component, RT5682_HP_LOGIC_CTRL_2, 1523 RT5682_HP_LC2_SIG_SOUR2_MASK, RT5682_HP_LC2_SIG_SOUR2_REG); 1524 snd_soc_component_update_bits(component, 1525 RT5682_DEPOP_1, 0x60, 0x60); 1526 snd_soc_component_update_bits(component, 1527 RT5682_DAC_ADC_DIG_VOL1, 0x00c0, 0x0080); 1528 snd_soc_component_update_bits(component, RT5682_HP_CTRL_2, 1529 RT5682_HP_C2_DAC_L_EN | RT5682_HP_C2_DAC_R_EN, 1530 RT5682_HP_C2_DAC_L_EN | RT5682_HP_C2_DAC_R_EN); 1531 usleep_range(5000, 10000); 1532 snd_soc_component_update_bits(component, RT5682_CHARGE_PUMP_1, 1533 RT5682_CP_SW_SIZE_MASK, RT5682_CP_SW_SIZE_L); 1534 break; 1535 1536 case SND_SOC_DAPM_POST_PMD: 1537 snd_soc_component_update_bits(component, RT5682_HP_CTRL_2, 1538 RT5682_HP_C2_DAC_L_EN | RT5682_HP_C2_DAC_R_EN, 0); 1539 snd_soc_component_update_bits(component, RT5682_CHARGE_PUMP_1, 1540 RT5682_CP_SW_SIZE_MASK, RT5682_CP_SW_SIZE_M); 1541 snd_soc_component_update_bits(component, 1542 RT5682_DEPOP_1, 0x60, 0x0); 1543 snd_soc_component_update_bits(component, 1544 RT5682_DAC_ADC_DIG_VOL1, 0x00c0, 0x0000); 1545 break; 1546 } 1547 1548 return 0; 1549 } 1550 1551 static int set_dmic_power(struct snd_soc_dapm_widget *w, 1552 struct snd_kcontrol *kcontrol, int event) 1553 { 1554 struct snd_soc_component *component = 1555 snd_soc_dapm_to_component(w->dapm); 1556 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 1557 unsigned int delay = 50, val; 1558 1559 if (rt5682->pdata.dmic_delay) 1560 delay = rt5682->pdata.dmic_delay; 1561 1562 switch (event) { 1563 case SND_SOC_DAPM_POST_PMU: 1564 val = snd_soc_component_read(component, RT5682_GLB_CLK); 1565 val &= RT5682_SCLK_SRC_MASK; 1566 if (val == RT5682_SCLK_SRC_PLL1 || val == RT5682_SCLK_SRC_PLL2) 1567 snd_soc_component_update_bits(component, 1568 RT5682_PWR_ANLG_1, 1569 RT5682_PWR_VREF2 | RT5682_PWR_MB, 1570 RT5682_PWR_VREF2 | RT5682_PWR_MB); 1571 1572 /*Add delay to avoid pop noise*/ 1573 msleep(delay); 1574 break; 1575 1576 case SND_SOC_DAPM_POST_PMD: 1577 if (!rt5682->jack_type) { 1578 if (!snd_soc_dapm_get_pin_status(w->dapm, "MICBIAS")) 1579 snd_soc_component_update_bits(component, 1580 RT5682_PWR_ANLG_1, RT5682_PWR_MB, 0); 1581 if (!snd_soc_dapm_get_pin_status(w->dapm, "Vref2")) 1582 snd_soc_component_update_bits(component, 1583 RT5682_PWR_ANLG_1, RT5682_PWR_VREF2, 0); 1584 } 1585 break; 1586 } 1587 1588 return 0; 1589 } 1590 1591 static int rt5682_set_verf(struct snd_soc_dapm_widget *w, 1592 struct snd_kcontrol *kcontrol, int event) 1593 { 1594 struct snd_soc_component *component = 1595 snd_soc_dapm_to_component(w->dapm); 1596 1597 switch (event) { 1598 case SND_SOC_DAPM_PRE_PMU: 1599 switch (w->shift) { 1600 case RT5682_PWR_VREF1_BIT: 1601 snd_soc_component_update_bits(component, 1602 RT5682_PWR_ANLG_1, RT5682_PWR_FV1, 0); 1603 break; 1604 1605 case RT5682_PWR_VREF2_BIT: 1606 snd_soc_component_update_bits(component, 1607 RT5682_PWR_ANLG_1, RT5682_PWR_FV2, 0); 1608 break; 1609 } 1610 break; 1611 1612 case SND_SOC_DAPM_POST_PMU: 1613 usleep_range(15000, 20000); 1614 switch (w->shift) { 1615 case RT5682_PWR_VREF1_BIT: 1616 snd_soc_component_update_bits(component, 1617 RT5682_PWR_ANLG_1, RT5682_PWR_FV1, 1618 RT5682_PWR_FV1); 1619 break; 1620 1621 case RT5682_PWR_VREF2_BIT: 1622 snd_soc_component_update_bits(component, 1623 RT5682_PWR_ANLG_1, RT5682_PWR_FV2, 1624 RT5682_PWR_FV2); 1625 break; 1626 } 1627 break; 1628 } 1629 1630 return 0; 1631 } 1632 1633 static const unsigned int rt5682_adcdat_pin_values[] = { 1634 1, 1635 3, 1636 }; 1637 1638 static const char * const rt5682_adcdat_pin_select[] = { 1639 "ADCDAT1", 1640 "ADCDAT2", 1641 }; 1642 1643 static SOC_VALUE_ENUM_SINGLE_DECL(rt5682_adcdat_pin_enum, 1644 RT5682_GPIO_CTRL_1, RT5682_GP4_PIN_SFT, RT5682_GP4_PIN_MASK, 1645 rt5682_adcdat_pin_select, rt5682_adcdat_pin_values); 1646 1647 static const struct snd_kcontrol_new rt5682_adcdat_pin_ctrl = 1648 SOC_DAPM_ENUM("ADCDAT", rt5682_adcdat_pin_enum); 1649 1650 static const unsigned int rt5682_hpo_sig_out_values[] = { 1651 2, 1652 7, 1653 }; 1654 1655 static const char * const rt5682_hpo_sig_out_mode[] = { 1656 "Legacy", 1657 "OneBit", 1658 }; 1659 1660 static SOC_VALUE_ENUM_SINGLE_DECL(rt5682_hpo_sig_out_enum, 1661 RT5682_HP_LOGIC_CTRL_2, 0, RT5682_HP_LC2_SIG_SOUR1_MASK, 1662 rt5682_hpo_sig_out_mode, rt5682_hpo_sig_out_values); 1663 1664 static const struct snd_kcontrol_new rt5682_hpo_sig_demux = 1665 SOC_DAPM_ENUM("HPO Signal Demux", rt5682_hpo_sig_out_enum); 1666 1667 static const struct snd_soc_dapm_widget rt5682_dapm_widgets[] = { 1668 SND_SOC_DAPM_SUPPLY("LDO2", RT5682_PWR_ANLG_3, RT5682_PWR_LDO2_BIT, 1669 0, NULL, 0), 1670 SND_SOC_DAPM_SUPPLY("PLL1", RT5682_PWR_ANLG_3, RT5682_PWR_PLL_BIT, 1671 0, NULL, 0), 1672 SND_SOC_DAPM_SUPPLY("PLL2B", RT5682_PWR_ANLG_3, RT5682_PWR_PLL2B_BIT, 1673 0, NULL, 0), 1674 SND_SOC_DAPM_SUPPLY("PLL2F", RT5682_PWR_ANLG_3, RT5682_PWR_PLL2F_BIT, 1675 0, set_filter_clk, SND_SOC_DAPM_PRE_PMU), 1676 SND_SOC_DAPM_SUPPLY("Vref1", RT5682_PWR_ANLG_1, RT5682_PWR_VREF1_BIT, 0, 1677 rt5682_set_verf, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), 1678 SND_SOC_DAPM_SUPPLY("Vref2", SND_SOC_NOPM, 0, 0, NULL, 0), 1679 SND_SOC_DAPM_SUPPLY("MICBIAS", SND_SOC_NOPM, 0, 0, NULL, 0), 1680 1681 /* ASRC */ 1682 SND_SOC_DAPM_SUPPLY_S("DAC STO1 ASRC", 1, RT5682_PLL_TRACK_1, 1683 RT5682_DAC_STO1_ASRC_SFT, 0, NULL, 0), 1684 SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5682_PLL_TRACK_1, 1685 RT5682_ADC_STO1_ASRC_SFT, 0, NULL, 0), 1686 SND_SOC_DAPM_SUPPLY_S("AD ASRC", 1, RT5682_PLL_TRACK_1, 1687 RT5682_AD_ASRC_SFT, 0, NULL, 0), 1688 SND_SOC_DAPM_SUPPLY_S("DA ASRC", 1, RT5682_PLL_TRACK_1, 1689 RT5682_DA_ASRC_SFT, 0, NULL, 0), 1690 SND_SOC_DAPM_SUPPLY_S("DMIC ASRC", 1, RT5682_PLL_TRACK_1, 1691 RT5682_DMIC_ASRC_SFT, 0, NULL, 0), 1692 1693 /* Input Side */ 1694 SND_SOC_DAPM_SUPPLY("MICBIAS1", RT5682_PWR_ANLG_2, RT5682_PWR_MB1_BIT, 1695 0, NULL, 0), 1696 SND_SOC_DAPM_SUPPLY("MICBIAS2", RT5682_PWR_ANLG_2, RT5682_PWR_MB2_BIT, 1697 0, NULL, 0), 1698 1699 /* Input Lines */ 1700 SND_SOC_DAPM_INPUT("DMIC L1"), 1701 SND_SOC_DAPM_INPUT("DMIC R1"), 1702 1703 SND_SOC_DAPM_INPUT("IN1P"), 1704 1705 SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0, 1706 set_dmic_clk, SND_SOC_DAPM_PRE_PMU), 1707 SND_SOC_DAPM_SUPPLY("DMIC1 Power", RT5682_DMIC_CTRL_1, 1708 RT5682_DMIC_1_EN_SFT, 0, set_dmic_power, 1709 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 1710 1711 /* Boost */ 1712 SND_SOC_DAPM_PGA("BST1 CBJ", SND_SOC_NOPM, 1713 0, 0, NULL, 0), 1714 1715 /* REC Mixer */ 1716 SND_SOC_DAPM_MIXER("RECMIX1L", SND_SOC_NOPM, 0, 0, rt5682_rec1_l_mix, 1717 ARRAY_SIZE(rt5682_rec1_l_mix)), 1718 SND_SOC_DAPM_SUPPLY("RECMIX1L Power", RT5682_PWR_ANLG_2, 1719 RT5682_PWR_RM1_L_BIT, 0, NULL, 0), 1720 1721 /* ADCs */ 1722 SND_SOC_DAPM_ADC("ADC1 L", NULL, SND_SOC_NOPM, 0, 0), 1723 SND_SOC_DAPM_ADC("ADC1 R", NULL, SND_SOC_NOPM, 0, 0), 1724 1725 SND_SOC_DAPM_SUPPLY("ADC1 L Power", RT5682_PWR_DIG_1, 1726 RT5682_PWR_ADC_L1_BIT, 0, NULL, 0), 1727 SND_SOC_DAPM_SUPPLY("ADC1 R Power", RT5682_PWR_DIG_1, 1728 RT5682_PWR_ADC_R1_BIT, 0, NULL, 0), 1729 SND_SOC_DAPM_SUPPLY("ADC1 clock", RT5682_CHOP_ADC, 1730 RT5682_CKGEN_ADC1_SFT, 0, NULL, 0), 1731 1732 /* ADC Mux */ 1733 SND_SOC_DAPM_MUX("Stereo1 ADC L1 Mux", SND_SOC_NOPM, 0, 0, 1734 &rt5682_sto1_adc1l_mux), 1735 SND_SOC_DAPM_MUX("Stereo1 ADC R1 Mux", SND_SOC_NOPM, 0, 0, 1736 &rt5682_sto1_adc1r_mux), 1737 SND_SOC_DAPM_MUX("Stereo1 ADC L2 Mux", SND_SOC_NOPM, 0, 0, 1738 &rt5682_sto1_adc2l_mux), 1739 SND_SOC_DAPM_MUX("Stereo1 ADC R2 Mux", SND_SOC_NOPM, 0, 0, 1740 &rt5682_sto1_adc2r_mux), 1741 SND_SOC_DAPM_MUX("Stereo1 ADC L Mux", SND_SOC_NOPM, 0, 0, 1742 &rt5682_sto1_adcl_mux), 1743 SND_SOC_DAPM_MUX("Stereo1 ADC R Mux", SND_SOC_NOPM, 0, 0, 1744 &rt5682_sto1_adcr_mux), 1745 SND_SOC_DAPM_MUX("IF1_ADC Mux", SND_SOC_NOPM, 0, 0, 1746 &rt5682_if1_adc_slot_mux), 1747 1748 /* ADC Mixer */ 1749 SND_SOC_DAPM_SUPPLY("ADC Stereo1 Filter", RT5682_PWR_DIG_2, 1750 RT5682_PWR_ADC_S1F_BIT, 0, set_filter_clk, 1751 SND_SOC_DAPM_PRE_PMU), 1752 SND_SOC_DAPM_MIXER("Stereo1 ADC MIXL", RT5682_STO1_ADC_DIG_VOL, 1753 RT5682_L_MUTE_SFT, 1, rt5682_sto1_adc_l_mix, 1754 ARRAY_SIZE(rt5682_sto1_adc_l_mix)), 1755 SND_SOC_DAPM_MIXER("Stereo1 ADC MIXR", RT5682_STO1_ADC_DIG_VOL, 1756 RT5682_R_MUTE_SFT, 1, rt5682_sto1_adc_r_mix, 1757 ARRAY_SIZE(rt5682_sto1_adc_r_mix)), 1758 1759 /* ADC PGA */ 1760 SND_SOC_DAPM_PGA("Stereo1 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 1761 1762 /* Digital Interface */ 1763 SND_SOC_DAPM_SUPPLY("I2S1", RT5682_PWR_DIG_1, RT5682_PWR_I2S1_BIT, 1764 0, NULL, 0), 1765 SND_SOC_DAPM_SUPPLY("I2S2", RT5682_PWR_DIG_1, RT5682_PWR_I2S2_BIT, 1766 0, NULL, 0), 1767 SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0), 1768 SND_SOC_DAPM_PGA("IF1 DAC1 L", SND_SOC_NOPM, 0, 0, NULL, 0), 1769 SND_SOC_DAPM_PGA("IF1 DAC1 R", SND_SOC_NOPM, 0, 0, NULL, 0), 1770 SND_SOC_DAPM_PGA("SOUND DAC L", SND_SOC_NOPM, 0, 0, NULL, 0), 1771 SND_SOC_DAPM_PGA("SOUND DAC R", SND_SOC_NOPM, 0, 0, NULL, 0), 1772 1773 /* Digital Interface Select */ 1774 SND_SOC_DAPM_MUX("IF1 01 ADC Swap Mux", SND_SOC_NOPM, 0, 0, 1775 &rt5682_if1_01_adc_swap_mux), 1776 SND_SOC_DAPM_MUX("IF1 23 ADC Swap Mux", SND_SOC_NOPM, 0, 0, 1777 &rt5682_if1_23_adc_swap_mux), 1778 SND_SOC_DAPM_MUX("IF1 45 ADC Swap Mux", SND_SOC_NOPM, 0, 0, 1779 &rt5682_if1_45_adc_swap_mux), 1780 SND_SOC_DAPM_MUX("IF1 67 ADC Swap Mux", SND_SOC_NOPM, 0, 0, 1781 &rt5682_if1_67_adc_swap_mux), 1782 SND_SOC_DAPM_MUX("IF2 ADC Swap Mux", SND_SOC_NOPM, 0, 0, 1783 &rt5682_if2_adc_swap_mux), 1784 1785 SND_SOC_DAPM_MUX("ADCDAT Mux", SND_SOC_NOPM, 0, 0, 1786 &rt5682_adcdat_pin_ctrl), 1787 1788 SND_SOC_DAPM_MUX("DAC L Mux", SND_SOC_NOPM, 0, 0, 1789 &rt5682_dac_l_mux), 1790 SND_SOC_DAPM_MUX("DAC R Mux", SND_SOC_NOPM, 0, 0, 1791 &rt5682_dac_r_mux), 1792 1793 /* Audio Interface */ 1794 SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, 1795 RT5682_I2S1_SDP, RT5682_SEL_ADCDAT_SFT, 1), 1796 SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, 1797 RT5682_I2S2_SDP, RT5682_I2S2_PIN_CFG_SFT, 1), 1798 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0), 1799 SND_SOC_DAPM_AIF_IN("SDWRX", "SDW Playback", 0, SND_SOC_NOPM, 0, 0), 1800 SND_SOC_DAPM_AIF_OUT("SDWTX", "SDW Capture", 0, SND_SOC_NOPM, 0, 0), 1801 1802 /* Output Side */ 1803 /* DAC mixer before sound effect */ 1804 SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0, 1805 rt5682_dac_l_mix, ARRAY_SIZE(rt5682_dac_l_mix)), 1806 SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0, 1807 rt5682_dac_r_mix, ARRAY_SIZE(rt5682_dac_r_mix)), 1808 1809 /* DAC channel Mux */ 1810 SND_SOC_DAPM_MUX("DAC L1 Source", SND_SOC_NOPM, 0, 0, 1811 &rt5682_alg_dac_l1_mux), 1812 SND_SOC_DAPM_MUX("DAC R1 Source", SND_SOC_NOPM, 0, 0, 1813 &rt5682_alg_dac_r1_mux), 1814 1815 /* DAC Mixer */ 1816 SND_SOC_DAPM_SUPPLY("DAC Stereo1 Filter", RT5682_PWR_DIG_2, 1817 RT5682_PWR_DAC_S1F_BIT, 0, set_filter_clk, 1818 SND_SOC_DAPM_PRE_PMU), 1819 SND_SOC_DAPM_MIXER("Stereo1 DAC MIXL", SND_SOC_NOPM, 0, 0, 1820 rt5682_sto1_dac_l_mix, ARRAY_SIZE(rt5682_sto1_dac_l_mix)), 1821 SND_SOC_DAPM_MIXER("Stereo1 DAC MIXR", SND_SOC_NOPM, 0, 0, 1822 rt5682_sto1_dac_r_mix, ARRAY_SIZE(rt5682_sto1_dac_r_mix)), 1823 1824 /* DACs */ 1825 SND_SOC_DAPM_DAC("DAC L1", NULL, RT5682_PWR_DIG_1, 1826 RT5682_PWR_DAC_L1_BIT, 0), 1827 SND_SOC_DAPM_DAC("DAC R1", NULL, RT5682_PWR_DIG_1, 1828 RT5682_PWR_DAC_R1_BIT, 0), 1829 SND_SOC_DAPM_SUPPLY_S("DAC 1 Clock", 3, RT5682_CHOP_DAC, 1830 RT5682_CKGEN_DAC1_SFT, 0, NULL, 0), 1831 1832 /* HPO */ 1833 SND_SOC_DAPM_PGA_S("HP Amp", 1, SND_SOC_NOPM, 0, 0, rt5682_hp_event, 1834 SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_PRE_PMU), 1835 1836 SND_SOC_DAPM_SUPPLY("HP Amp L", RT5682_PWR_ANLG_1, 1837 RT5682_PWR_HA_L_BIT, 0, NULL, 0), 1838 SND_SOC_DAPM_SUPPLY("HP Amp R", RT5682_PWR_ANLG_1, 1839 RT5682_PWR_HA_R_BIT, 0, NULL, 0), 1840 SND_SOC_DAPM_SUPPLY_S("Charge Pump", 1, RT5682_DEPOP_1, 1841 RT5682_PUMP_EN_SFT, 0, NULL, 0), 1842 SND_SOC_DAPM_SUPPLY_S("Capless", 2, RT5682_DEPOP_1, 1843 RT5682_CAPLESS_EN_SFT, 0, NULL, 0), 1844 1845 SND_SOC_DAPM_SWITCH("HPOL Playback", SND_SOC_NOPM, 0, 0, 1846 &hpol_switch), 1847 SND_SOC_DAPM_SWITCH("HPOR Playback", SND_SOC_NOPM, 0, 0, 1848 &hpor_switch), 1849 1850 SND_SOC_DAPM_OUT_DRV("HPO Legacy", SND_SOC_NOPM, 0, 0, NULL, 0), 1851 SND_SOC_DAPM_OUT_DRV("HPO OneBit", SND_SOC_NOPM, 0, 0, NULL, 0), 1852 SND_SOC_DAPM_DEMUX("HPO Signal Demux", SND_SOC_NOPM, 0, 0, &rt5682_hpo_sig_demux), 1853 1854 /* CLK DET */ 1855 SND_SOC_DAPM_SUPPLY("CLKDET SYS", RT5682_CLK_DET, 1856 RT5682_SYS_CLK_DET_SFT, 0, NULL, 0), 1857 SND_SOC_DAPM_SUPPLY("CLKDET PLL1", RT5682_CLK_DET, 1858 RT5682_PLL1_CLK_DET_SFT, 0, NULL, 0), 1859 SND_SOC_DAPM_SUPPLY("CLKDET PLL2", RT5682_CLK_DET, 1860 RT5682_PLL2_CLK_DET_SFT, 0, NULL, 0), 1861 SND_SOC_DAPM_SUPPLY("CLKDET", RT5682_CLK_DET, 1862 RT5682_POW_CLK_DET_SFT, 0, NULL, 0), 1863 1864 /* Output Lines */ 1865 SND_SOC_DAPM_OUTPUT("HPOL"), 1866 SND_SOC_DAPM_OUTPUT("HPOR"), 1867 }; 1868 1869 static const struct snd_soc_dapm_route rt5682_dapm_routes[] = { 1870 /*PLL*/ 1871 {"ADC Stereo1 Filter", NULL, "PLL1", is_sys_clk_from_pll1}, 1872 {"ADC Stereo1 Filter", NULL, "PLL2B", is_sys_clk_from_pll2}, 1873 {"ADC Stereo1 Filter", NULL, "PLL2F", is_sys_clk_from_pll2}, 1874 {"DAC Stereo1 Filter", NULL, "PLL1", is_sys_clk_from_pll1}, 1875 {"DAC Stereo1 Filter", NULL, "PLL2B", is_sys_clk_from_pll2}, 1876 {"DAC Stereo1 Filter", NULL, "PLL2F", is_sys_clk_from_pll2}, 1877 1878 /*ASRC*/ 1879 {"ADC Stereo1 Filter", NULL, "ADC STO1 ASRC", is_using_asrc}, 1880 {"DAC Stereo1 Filter", NULL, "DAC STO1 ASRC", is_using_asrc}, 1881 {"ADC STO1 ASRC", NULL, "AD ASRC"}, 1882 {"ADC STO1 ASRC", NULL, "DA ASRC"}, 1883 {"ADC STO1 ASRC", NULL, "CLKDET"}, 1884 {"DAC STO1 ASRC", NULL, "AD ASRC"}, 1885 {"DAC STO1 ASRC", NULL, "DA ASRC"}, 1886 {"DAC STO1 ASRC", NULL, "CLKDET"}, 1887 1888 /*Vref*/ 1889 {"MICBIAS1", NULL, "Vref1"}, 1890 {"MICBIAS2", NULL, "Vref1"}, 1891 1892 {"CLKDET SYS", NULL, "CLKDET"}, 1893 1894 {"BST1 CBJ", NULL, "IN1P"}, 1895 1896 {"RECMIX1L", "CBJ Switch", "BST1 CBJ"}, 1897 {"RECMIX1L", NULL, "RECMIX1L Power"}, 1898 1899 {"ADC1 L", NULL, "RECMIX1L"}, 1900 {"ADC1 L", NULL, "ADC1 L Power"}, 1901 {"ADC1 L", NULL, "ADC1 clock"}, 1902 1903 {"DMIC L1", NULL, "DMIC CLK"}, 1904 {"DMIC L1", NULL, "DMIC1 Power"}, 1905 {"DMIC R1", NULL, "DMIC CLK"}, 1906 {"DMIC R1", NULL, "DMIC1 Power"}, 1907 {"DMIC CLK", NULL, "DMIC ASRC"}, 1908 1909 {"Stereo1 ADC L Mux", "ADC1 L", "ADC1 L"}, 1910 {"Stereo1 ADC L Mux", "ADC1 R", "ADC1 R"}, 1911 {"Stereo1 ADC R Mux", "ADC1 L", "ADC1 L"}, 1912 {"Stereo1 ADC R Mux", "ADC1 R", "ADC1 R"}, 1913 1914 {"Stereo1 ADC L1 Mux", "ADC", "Stereo1 ADC L Mux"}, 1915 {"Stereo1 ADC L1 Mux", "DAC MIX", "Stereo1 DAC MIXL"}, 1916 {"Stereo1 ADC L2 Mux", "DMIC", "DMIC L1"}, 1917 {"Stereo1 ADC L2 Mux", "DAC MIX", "Stereo1 DAC MIXL"}, 1918 1919 {"Stereo1 ADC R1 Mux", "ADC", "Stereo1 ADC R Mux"}, 1920 {"Stereo1 ADC R1 Mux", "DAC MIX", "Stereo1 DAC MIXR"}, 1921 {"Stereo1 ADC R2 Mux", "DMIC", "DMIC R1"}, 1922 {"Stereo1 ADC R2 Mux", "DAC MIX", "Stereo1 DAC MIXR"}, 1923 1924 {"Stereo1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC L1 Mux"}, 1925 {"Stereo1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC L2 Mux"}, 1926 {"Stereo1 ADC MIXL", NULL, "ADC Stereo1 Filter"}, 1927 1928 {"Stereo1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC R1 Mux"}, 1929 {"Stereo1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC R2 Mux"}, 1930 {"Stereo1 ADC MIXR", NULL, "ADC Stereo1 Filter"}, 1931 1932 {"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXL"}, 1933 {"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXR"}, 1934 1935 {"IF1 01 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"}, 1936 {"IF1 01 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"}, 1937 {"IF1 01 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"}, 1938 {"IF1 01 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"}, 1939 {"IF1 23 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"}, 1940 {"IF1 23 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"}, 1941 {"IF1 23 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"}, 1942 {"IF1 23 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"}, 1943 {"IF1 45 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"}, 1944 {"IF1 45 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"}, 1945 {"IF1 45 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"}, 1946 {"IF1 45 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"}, 1947 {"IF1 67 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"}, 1948 {"IF1 67 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"}, 1949 {"IF1 67 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"}, 1950 {"IF1 67 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"}, 1951 1952 {"IF1_ADC Mux", "Slot 0", "IF1 01 ADC Swap Mux"}, 1953 {"IF1_ADC Mux", "Slot 2", "IF1 23 ADC Swap Mux"}, 1954 {"IF1_ADC Mux", "Slot 4", "IF1 45 ADC Swap Mux"}, 1955 {"IF1_ADC Mux", "Slot 6", "IF1 67 ADC Swap Mux"}, 1956 {"ADCDAT Mux", "ADCDAT1", "IF1_ADC Mux"}, 1957 {"AIF1TX", NULL, "I2S1"}, 1958 {"AIF1TX", NULL, "ADCDAT Mux"}, 1959 {"IF2 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"}, 1960 {"IF2 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"}, 1961 {"IF2 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"}, 1962 {"IF2 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"}, 1963 {"ADCDAT Mux", "ADCDAT2", "IF2 ADC Swap Mux"}, 1964 {"AIF2TX", NULL, "ADCDAT Mux"}, 1965 1966 {"SDWTX", NULL, "PLL2B"}, 1967 {"SDWTX", NULL, "PLL2F"}, 1968 {"SDWTX", NULL, "ADCDAT Mux"}, 1969 1970 {"IF1 DAC1 L", NULL, "AIF1RX"}, 1971 {"IF1 DAC1 L", NULL, "I2S1"}, 1972 {"IF1 DAC1 L", NULL, "DAC Stereo1 Filter"}, 1973 {"IF1 DAC1 R", NULL, "AIF1RX"}, 1974 {"IF1 DAC1 R", NULL, "I2S1"}, 1975 {"IF1 DAC1 R", NULL, "DAC Stereo1 Filter"}, 1976 1977 {"SOUND DAC L", NULL, "SDWRX"}, 1978 {"SOUND DAC L", NULL, "DAC Stereo1 Filter"}, 1979 {"SOUND DAC L", NULL, "PLL2B"}, 1980 {"SOUND DAC L", NULL, "PLL2F"}, 1981 {"SOUND DAC R", NULL, "SDWRX"}, 1982 {"SOUND DAC R", NULL, "DAC Stereo1 Filter"}, 1983 {"SOUND DAC R", NULL, "PLL2B"}, 1984 {"SOUND DAC R", NULL, "PLL2F"}, 1985 1986 {"DAC L Mux", "IF1", "IF1 DAC1 L"}, 1987 {"DAC L Mux", "SOUND", "SOUND DAC L"}, 1988 {"DAC R Mux", "IF1", "IF1 DAC1 R"}, 1989 {"DAC R Mux", "SOUND", "SOUND DAC R"}, 1990 1991 {"DAC1 MIXL", "Stereo ADC Switch", "Stereo1 ADC MIXL"}, 1992 {"DAC1 MIXL", "DAC1 Switch", "DAC L Mux"}, 1993 {"DAC1 MIXR", "Stereo ADC Switch", "Stereo1 ADC MIXR"}, 1994 {"DAC1 MIXR", "DAC1 Switch", "DAC R Mux"}, 1995 1996 {"Stereo1 DAC MIXL", "DAC L1 Switch", "DAC1 MIXL"}, 1997 {"Stereo1 DAC MIXL", "DAC R1 Switch", "DAC1 MIXR"}, 1998 1999 {"Stereo1 DAC MIXR", "DAC R1 Switch", "DAC1 MIXR"}, 2000 {"Stereo1 DAC MIXR", "DAC L1 Switch", "DAC1 MIXL"}, 2001 2002 {"DAC L1 Source", "DAC1", "DAC1 MIXL"}, 2003 {"DAC L1 Source", "Stereo1 DAC Mixer", "Stereo1 DAC MIXL"}, 2004 {"DAC R1 Source", "DAC1", "DAC1 MIXR"}, 2005 {"DAC R1 Source", "Stereo1 DAC Mixer", "Stereo1 DAC MIXR"}, 2006 2007 {"DAC L1", NULL, "DAC L1 Source"}, 2008 {"DAC R1", NULL, "DAC R1 Source"}, 2009 2010 {"DAC L1", NULL, "DAC 1 Clock"}, 2011 {"DAC R1", NULL, "DAC 1 Clock"}, 2012 2013 {"HP Amp", NULL, "DAC L1"}, 2014 {"HP Amp", NULL, "DAC R1"}, 2015 {"HP Amp", NULL, "HP Amp L"}, 2016 {"HP Amp", NULL, "HP Amp R"}, 2017 {"HP Amp", NULL, "Capless"}, 2018 {"HP Amp", NULL, "Charge Pump"}, 2019 {"HP Amp", NULL, "CLKDET SYS"}, 2020 {"HP Amp", NULL, "Vref1"}, 2021 2022 {"HPO Signal Demux", NULL, "HP Amp"}, 2023 2024 {"HPO Legacy", "Legacy", "HPO Signal Demux"}, 2025 {"HPO OneBit", "OneBit", "HPO Signal Demux"}, 2026 2027 {"HPOL Playback", "Switch", "HPO Legacy"}, 2028 {"HPOR Playback", "Switch", "HPO Legacy"}, 2029 2030 {"HPOL", NULL, "HPOL Playback"}, 2031 {"HPOR", NULL, "HPOR Playback"}, 2032 {"HPOL", NULL, "HPO OneBit"}, 2033 {"HPOR", NULL, "HPO OneBit"}, 2034 }; 2035 2036 static int rt5682_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask, 2037 unsigned int rx_mask, int slots, int slot_width) 2038 { 2039 struct snd_soc_component *component = dai->component; 2040 unsigned int cl, val = 0; 2041 2042 if (tx_mask || rx_mask) 2043 snd_soc_component_update_bits(component, RT5682_TDM_ADDA_CTRL_2, 2044 RT5682_TDM_EN, RT5682_TDM_EN); 2045 else 2046 snd_soc_component_update_bits(component, RT5682_TDM_ADDA_CTRL_2, 2047 RT5682_TDM_EN, 0); 2048 2049 switch (slots) { 2050 case 4: 2051 val |= RT5682_TDM_TX_CH_4; 2052 val |= RT5682_TDM_RX_CH_4; 2053 break; 2054 case 6: 2055 val |= RT5682_TDM_TX_CH_6; 2056 val |= RT5682_TDM_RX_CH_6; 2057 break; 2058 case 8: 2059 val |= RT5682_TDM_TX_CH_8; 2060 val |= RT5682_TDM_RX_CH_8; 2061 break; 2062 case 2: 2063 break; 2064 default: 2065 return -EINVAL; 2066 } 2067 2068 snd_soc_component_update_bits(component, RT5682_TDM_CTRL, 2069 RT5682_TDM_TX_CH_MASK | RT5682_TDM_RX_CH_MASK, val); 2070 2071 switch (slot_width) { 2072 case 8: 2073 if (tx_mask || rx_mask) 2074 return -EINVAL; 2075 cl = RT5682_I2S1_TX_CHL_8 | RT5682_I2S1_RX_CHL_8; 2076 break; 2077 case 16: 2078 val = RT5682_TDM_CL_16; 2079 cl = RT5682_I2S1_TX_CHL_16 | RT5682_I2S1_RX_CHL_16; 2080 break; 2081 case 20: 2082 val = RT5682_TDM_CL_20; 2083 cl = RT5682_I2S1_TX_CHL_20 | RT5682_I2S1_RX_CHL_20; 2084 break; 2085 case 24: 2086 val = RT5682_TDM_CL_24; 2087 cl = RT5682_I2S1_TX_CHL_24 | RT5682_I2S1_RX_CHL_24; 2088 break; 2089 case 32: 2090 val = RT5682_TDM_CL_32; 2091 cl = RT5682_I2S1_TX_CHL_32 | RT5682_I2S1_RX_CHL_32; 2092 break; 2093 default: 2094 return -EINVAL; 2095 } 2096 2097 snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL, 2098 RT5682_TDM_CL_MASK, val); 2099 snd_soc_component_update_bits(component, RT5682_I2S1_SDP, 2100 RT5682_I2S1_TX_CHL_MASK | RT5682_I2S1_RX_CHL_MASK, cl); 2101 2102 return 0; 2103 } 2104 2105 static int rt5682_hw_params(struct snd_pcm_substream *substream, 2106 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) 2107 { 2108 struct snd_soc_component *component = dai->component; 2109 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 2110 unsigned int len_1 = 0, len_2 = 0; 2111 int pre_div, frame_size; 2112 2113 rt5682->lrck[dai->id] = params_rate(params); 2114 pre_div = rl6231_get_clk_info(rt5682->sysclk, rt5682->lrck[dai->id]); 2115 2116 frame_size = snd_soc_params_to_frame_size(params); 2117 if (frame_size < 0) { 2118 dev_err(component->dev, "Unsupported frame size: %d\n", 2119 frame_size); 2120 return -EINVAL; 2121 } 2122 2123 dev_dbg(dai->dev, "lrck is %dHz and pre_div is %d for iis %d\n", 2124 rt5682->lrck[dai->id], pre_div, dai->id); 2125 2126 switch (params_width(params)) { 2127 case 16: 2128 break; 2129 case 20: 2130 len_1 |= RT5682_I2S1_DL_20; 2131 len_2 |= RT5682_I2S2_DL_20; 2132 break; 2133 case 24: 2134 len_1 |= RT5682_I2S1_DL_24; 2135 len_2 |= RT5682_I2S2_DL_24; 2136 break; 2137 case 32: 2138 len_1 |= RT5682_I2S1_DL_32; 2139 len_2 |= RT5682_I2S2_DL_24; 2140 break; 2141 case 8: 2142 len_1 |= RT5682_I2S2_DL_8; 2143 len_2 |= RT5682_I2S2_DL_8; 2144 break; 2145 default: 2146 return -EINVAL; 2147 } 2148 2149 switch (dai->id) { 2150 case RT5682_AIF1: 2151 snd_soc_component_update_bits(component, RT5682_I2S1_SDP, 2152 RT5682_I2S1_DL_MASK, len_1); 2153 if (rt5682->master[RT5682_AIF1]) { 2154 snd_soc_component_update_bits(component, 2155 RT5682_ADDA_CLK_1, RT5682_I2S_M_DIV_MASK | 2156 RT5682_I2S_CLK_SRC_MASK, 2157 pre_div << RT5682_I2S_M_DIV_SFT | 2158 (rt5682->sysclk_src) << RT5682_I2S_CLK_SRC_SFT); 2159 } 2160 if (params_channels(params) == 1) /* mono mode */ 2161 snd_soc_component_update_bits(component, 2162 RT5682_I2S1_SDP, RT5682_I2S1_MONO_MASK, 2163 RT5682_I2S1_MONO_EN); 2164 else 2165 snd_soc_component_update_bits(component, 2166 RT5682_I2S1_SDP, RT5682_I2S1_MONO_MASK, 2167 RT5682_I2S1_MONO_DIS); 2168 break; 2169 case RT5682_AIF2: 2170 snd_soc_component_update_bits(component, RT5682_I2S2_SDP, 2171 RT5682_I2S2_DL_MASK, len_2); 2172 if (rt5682->master[RT5682_AIF2]) { 2173 snd_soc_component_update_bits(component, 2174 RT5682_I2S_M_CLK_CTRL_1, RT5682_I2S2_M_PD_MASK, 2175 pre_div << RT5682_I2S2_M_PD_SFT); 2176 } 2177 if (params_channels(params) == 1) /* mono mode */ 2178 snd_soc_component_update_bits(component, 2179 RT5682_I2S2_SDP, RT5682_I2S2_MONO_MASK, 2180 RT5682_I2S2_MONO_EN); 2181 else 2182 snd_soc_component_update_bits(component, 2183 RT5682_I2S2_SDP, RT5682_I2S2_MONO_MASK, 2184 RT5682_I2S2_MONO_DIS); 2185 break; 2186 default: 2187 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id); 2188 return -EINVAL; 2189 } 2190 2191 return 0; 2192 } 2193 2194 static int rt5682_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) 2195 { 2196 struct snd_soc_component *component = dai->component; 2197 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 2198 unsigned int reg_val = 0, tdm_ctrl = 0; 2199 2200 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 2201 case SND_SOC_DAIFMT_CBM_CFM: 2202 rt5682->master[dai->id] = 1; 2203 break; 2204 case SND_SOC_DAIFMT_CBS_CFS: 2205 rt5682->master[dai->id] = 0; 2206 break; 2207 default: 2208 return -EINVAL; 2209 } 2210 2211 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 2212 case SND_SOC_DAIFMT_NB_NF: 2213 break; 2214 case SND_SOC_DAIFMT_IB_NF: 2215 reg_val |= RT5682_I2S_BP_INV; 2216 tdm_ctrl |= RT5682_TDM_S_BP_INV; 2217 break; 2218 case SND_SOC_DAIFMT_NB_IF: 2219 if (dai->id == RT5682_AIF1) 2220 tdm_ctrl |= RT5682_TDM_S_LP_INV | RT5682_TDM_M_BP_INV; 2221 else 2222 return -EINVAL; 2223 break; 2224 case SND_SOC_DAIFMT_IB_IF: 2225 if (dai->id == RT5682_AIF1) 2226 tdm_ctrl |= RT5682_TDM_S_BP_INV | RT5682_TDM_S_LP_INV | 2227 RT5682_TDM_M_BP_INV | RT5682_TDM_M_LP_INV; 2228 else 2229 return -EINVAL; 2230 break; 2231 default: 2232 return -EINVAL; 2233 } 2234 2235 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 2236 case SND_SOC_DAIFMT_I2S: 2237 break; 2238 case SND_SOC_DAIFMT_LEFT_J: 2239 reg_val |= RT5682_I2S_DF_LEFT; 2240 tdm_ctrl |= RT5682_TDM_DF_LEFT; 2241 break; 2242 case SND_SOC_DAIFMT_DSP_A: 2243 reg_val |= RT5682_I2S_DF_PCM_A; 2244 tdm_ctrl |= RT5682_TDM_DF_PCM_A; 2245 break; 2246 case SND_SOC_DAIFMT_DSP_B: 2247 reg_val |= RT5682_I2S_DF_PCM_B; 2248 tdm_ctrl |= RT5682_TDM_DF_PCM_B; 2249 break; 2250 default: 2251 return -EINVAL; 2252 } 2253 2254 switch (dai->id) { 2255 case RT5682_AIF1: 2256 snd_soc_component_update_bits(component, RT5682_I2S1_SDP, 2257 RT5682_I2S_DF_MASK, reg_val); 2258 snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL, 2259 RT5682_TDM_MS_MASK | RT5682_TDM_S_BP_MASK | 2260 RT5682_TDM_DF_MASK | RT5682_TDM_M_BP_MASK | 2261 RT5682_TDM_M_LP_MASK | RT5682_TDM_S_LP_MASK, 2262 tdm_ctrl | rt5682->master[dai->id]); 2263 break; 2264 case RT5682_AIF2: 2265 if (rt5682->master[dai->id] == 0) 2266 reg_val |= RT5682_I2S2_MS_S; 2267 snd_soc_component_update_bits(component, RT5682_I2S2_SDP, 2268 RT5682_I2S2_MS_MASK | RT5682_I2S_BP_MASK | 2269 RT5682_I2S_DF_MASK, reg_val); 2270 break; 2271 default: 2272 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id); 2273 return -EINVAL; 2274 } 2275 return 0; 2276 } 2277 2278 static int rt5682_set_component_sysclk(struct snd_soc_component *component, 2279 int clk_id, int source, unsigned int freq, int dir) 2280 { 2281 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 2282 unsigned int reg_val = 0, src = 0; 2283 2284 if (freq == rt5682->sysclk && clk_id == rt5682->sysclk_src) 2285 return 0; 2286 2287 switch (clk_id) { 2288 case RT5682_SCLK_S_MCLK: 2289 reg_val |= RT5682_SCLK_SRC_MCLK; 2290 src = RT5682_CLK_SRC_MCLK; 2291 break; 2292 case RT5682_SCLK_S_PLL1: 2293 reg_val |= RT5682_SCLK_SRC_PLL1; 2294 src = RT5682_CLK_SRC_PLL1; 2295 break; 2296 case RT5682_SCLK_S_PLL2: 2297 reg_val |= RT5682_SCLK_SRC_PLL2; 2298 src = RT5682_CLK_SRC_PLL2; 2299 break; 2300 case RT5682_SCLK_S_RCCLK: 2301 reg_val |= RT5682_SCLK_SRC_RCCLK; 2302 src = RT5682_CLK_SRC_RCCLK; 2303 break; 2304 default: 2305 dev_err(component->dev, "Invalid clock id (%d)\n", clk_id); 2306 return -EINVAL; 2307 } 2308 snd_soc_component_update_bits(component, RT5682_GLB_CLK, 2309 RT5682_SCLK_SRC_MASK, reg_val); 2310 2311 if (rt5682->master[RT5682_AIF2]) { 2312 snd_soc_component_update_bits(component, 2313 RT5682_I2S_M_CLK_CTRL_1, RT5682_I2S2_SRC_MASK, 2314 src << RT5682_I2S2_SRC_SFT); 2315 } 2316 2317 rt5682->sysclk = freq; 2318 rt5682->sysclk_src = clk_id; 2319 2320 dev_dbg(component->dev, "Sysclk is %dHz and clock id is %d\n", 2321 freq, clk_id); 2322 2323 return 0; 2324 } 2325 2326 static int rt5682_set_component_pll(struct snd_soc_component *component, 2327 int pll_id, int source, unsigned int freq_in, 2328 unsigned int freq_out) 2329 { 2330 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 2331 struct rl6231_pll_code pll_code, pll2f_code, pll2b_code; 2332 unsigned int pll2_fout1, pll2_ps_val; 2333 int ret; 2334 2335 if (source == rt5682->pll_src[pll_id] && 2336 freq_in == rt5682->pll_in[pll_id] && 2337 freq_out == rt5682->pll_out[pll_id]) 2338 return 0; 2339 2340 if (!freq_in || !freq_out) { 2341 dev_dbg(component->dev, "PLL disabled\n"); 2342 2343 rt5682->pll_in[pll_id] = 0; 2344 rt5682->pll_out[pll_id] = 0; 2345 snd_soc_component_update_bits(component, RT5682_GLB_CLK, 2346 RT5682_SCLK_SRC_MASK, RT5682_SCLK_SRC_MCLK); 2347 return 0; 2348 } 2349 2350 if (pll_id == RT5682_PLL2) { 2351 switch (source) { 2352 case RT5682_PLL2_S_MCLK: 2353 snd_soc_component_update_bits(component, 2354 RT5682_GLB_CLK, RT5682_PLL2_SRC_MASK, 2355 RT5682_PLL2_SRC_MCLK); 2356 break; 2357 default: 2358 dev_err(component->dev, "Unknown PLL2 Source %d\n", 2359 source); 2360 return -EINVAL; 2361 } 2362 2363 /** 2364 * PLL2 concatenates 2 PLL units. 2365 * We suggest the Fout of the front PLL is 3.84MHz. 2366 */ 2367 pll2_fout1 = 3840000; 2368 ret = rl6231_pll_calc(freq_in, pll2_fout1, &pll2f_code); 2369 if (ret < 0) { 2370 dev_err(component->dev, "Unsupported input clock %d\n", 2371 freq_in); 2372 return ret; 2373 } 2374 dev_dbg(component->dev, "PLL2F: fin=%d fout=%d bypass=%d m=%d n=%d k=%d\n", 2375 freq_in, pll2_fout1, 2376 pll2f_code.m_bp, 2377 (pll2f_code.m_bp ? 0 : pll2f_code.m_code), 2378 pll2f_code.n_code, pll2f_code.k_code); 2379 2380 ret = rl6231_pll_calc(pll2_fout1, freq_out, &pll2b_code); 2381 if (ret < 0) { 2382 dev_err(component->dev, "Unsupported input clock %d\n", 2383 pll2_fout1); 2384 return ret; 2385 } 2386 dev_dbg(component->dev, "PLL2B: fin=%d fout=%d bypass=%d m=%d n=%d k=%d\n", 2387 pll2_fout1, freq_out, 2388 pll2b_code.m_bp, 2389 (pll2b_code.m_bp ? 0 : pll2b_code.m_code), 2390 pll2b_code.n_code, pll2b_code.k_code); 2391 2392 snd_soc_component_write(component, RT5682_PLL2_CTRL_1, 2393 pll2f_code.k_code << RT5682_PLL2F_K_SFT | 2394 pll2b_code.k_code << RT5682_PLL2B_K_SFT | 2395 pll2b_code.m_code); 2396 snd_soc_component_write(component, RT5682_PLL2_CTRL_2, 2397 pll2f_code.m_code << RT5682_PLL2F_M_SFT | 2398 pll2b_code.n_code); 2399 snd_soc_component_write(component, RT5682_PLL2_CTRL_3, 2400 pll2f_code.n_code << RT5682_PLL2F_N_SFT); 2401 2402 if (freq_out == 22579200) 2403 pll2_ps_val = 1 << RT5682_PLL2B_SEL_PS_SFT; 2404 else 2405 pll2_ps_val = 1 << RT5682_PLL2B_PS_BYP_SFT; 2406 snd_soc_component_update_bits(component, RT5682_PLL2_CTRL_4, 2407 RT5682_PLL2B_SEL_PS_MASK | RT5682_PLL2B_PS_BYP_MASK | 2408 RT5682_PLL2B_M_BP_MASK | RT5682_PLL2F_M_BP_MASK | 0xf, 2409 pll2_ps_val | 2410 (pll2b_code.m_bp ? 1 : 0) << RT5682_PLL2B_M_BP_SFT | 2411 (pll2f_code.m_bp ? 1 : 0) << RT5682_PLL2F_M_BP_SFT | 2412 0xf); 2413 } else { 2414 switch (source) { 2415 case RT5682_PLL1_S_MCLK: 2416 snd_soc_component_update_bits(component, 2417 RT5682_GLB_CLK, RT5682_PLL1_SRC_MASK, 2418 RT5682_PLL1_SRC_MCLK); 2419 break; 2420 case RT5682_PLL1_S_BCLK1: 2421 snd_soc_component_update_bits(component, 2422 RT5682_GLB_CLK, RT5682_PLL1_SRC_MASK, 2423 RT5682_PLL1_SRC_BCLK1); 2424 break; 2425 default: 2426 dev_err(component->dev, "Unknown PLL1 Source %d\n", 2427 source); 2428 return -EINVAL; 2429 } 2430 2431 ret = rl6231_pll_calc(freq_in, freq_out, &pll_code); 2432 if (ret < 0) { 2433 dev_err(component->dev, "Unsupported input clock %d\n", 2434 freq_in); 2435 return ret; 2436 } 2437 2438 dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n", 2439 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code), 2440 pll_code.n_code, pll_code.k_code); 2441 2442 snd_soc_component_write(component, RT5682_PLL_CTRL_1, 2443 (pll_code.n_code << RT5682_PLL_N_SFT) | pll_code.k_code); 2444 snd_soc_component_write(component, RT5682_PLL_CTRL_2, 2445 ((pll_code.m_bp ? 0 : pll_code.m_code) << RT5682_PLL_M_SFT) | 2446 ((pll_code.m_bp << RT5682_PLL_M_BP_SFT) | RT5682_PLL_RST)); 2447 } 2448 2449 rt5682->pll_in[pll_id] = freq_in; 2450 rt5682->pll_out[pll_id] = freq_out; 2451 rt5682->pll_src[pll_id] = source; 2452 2453 return 0; 2454 } 2455 2456 static int rt5682_set_bclk1_ratio(struct snd_soc_dai *dai, unsigned int ratio) 2457 { 2458 struct snd_soc_component *component = dai->component; 2459 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 2460 2461 rt5682->bclk[dai->id] = ratio; 2462 2463 switch (ratio) { 2464 case 256: 2465 snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL, 2466 RT5682_TDM_BCLK_MS1_MASK, RT5682_TDM_BCLK_MS1_256); 2467 break; 2468 case 128: 2469 snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL, 2470 RT5682_TDM_BCLK_MS1_MASK, RT5682_TDM_BCLK_MS1_128); 2471 break; 2472 case 64: 2473 snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL, 2474 RT5682_TDM_BCLK_MS1_MASK, RT5682_TDM_BCLK_MS1_64); 2475 break; 2476 case 32: 2477 snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL, 2478 RT5682_TDM_BCLK_MS1_MASK, RT5682_TDM_BCLK_MS1_32); 2479 break; 2480 default: 2481 dev_err(dai->dev, "Invalid bclk1 ratio %d\n", ratio); 2482 return -EINVAL; 2483 } 2484 2485 return 0; 2486 } 2487 2488 static int rt5682_set_bclk2_ratio(struct snd_soc_dai *dai, unsigned int ratio) 2489 { 2490 struct snd_soc_component *component = dai->component; 2491 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 2492 2493 rt5682->bclk[dai->id] = ratio; 2494 2495 switch (ratio) { 2496 case 64: 2497 snd_soc_component_update_bits(component, RT5682_ADDA_CLK_2, 2498 RT5682_I2S2_BCLK_MS2_MASK, 2499 RT5682_I2S2_BCLK_MS2_64); 2500 break; 2501 case 32: 2502 snd_soc_component_update_bits(component, RT5682_ADDA_CLK_2, 2503 RT5682_I2S2_BCLK_MS2_MASK, 2504 RT5682_I2S2_BCLK_MS2_32); 2505 break; 2506 default: 2507 dev_err(dai->dev, "Invalid bclk2 ratio %d\n", ratio); 2508 return -EINVAL; 2509 } 2510 2511 return 0; 2512 } 2513 2514 static int rt5682_set_bias_level(struct snd_soc_component *component, 2515 enum snd_soc_bias_level level) 2516 { 2517 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 2518 2519 switch (level) { 2520 case SND_SOC_BIAS_PREPARE: 2521 regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_1, 2522 RT5682_PWR_BG, RT5682_PWR_BG); 2523 regmap_update_bits(rt5682->regmap, RT5682_PWR_DIG_1, 2524 RT5682_DIG_GATE_CTRL | RT5682_PWR_LDO, 2525 RT5682_DIG_GATE_CTRL | RT5682_PWR_LDO); 2526 break; 2527 2528 case SND_SOC_BIAS_STANDBY: 2529 regmap_update_bits(rt5682->regmap, RT5682_PWR_DIG_1, 2530 RT5682_DIG_GATE_CTRL, RT5682_DIG_GATE_CTRL); 2531 break; 2532 case SND_SOC_BIAS_OFF: 2533 regmap_update_bits(rt5682->regmap, RT5682_PWR_DIG_1, 2534 RT5682_DIG_GATE_CTRL | RT5682_PWR_LDO, 0); 2535 regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_1, 2536 RT5682_PWR_BG, 0); 2537 break; 2538 case SND_SOC_BIAS_ON: 2539 break; 2540 } 2541 2542 return 0; 2543 } 2544 2545 #ifdef CONFIG_COMMON_CLK 2546 #define CLK_PLL2_FIN 48000000 2547 #define CLK_48 48000 2548 #define CLK_44 44100 2549 2550 static bool rt5682_clk_check(struct rt5682_priv *rt5682) 2551 { 2552 if (!rt5682->master[RT5682_AIF1]) { 2553 dev_dbg(rt5682->i2c_dev, "sysclk/dai not set correctly\n"); 2554 return false; 2555 } 2556 return true; 2557 } 2558 2559 static int rt5682_wclk_prepare(struct clk_hw *hw) 2560 { 2561 struct rt5682_priv *rt5682 = 2562 container_of(hw, struct rt5682_priv, 2563 dai_clks_hw[RT5682_DAI_WCLK_IDX]); 2564 struct snd_soc_component *component; 2565 struct snd_soc_dapm_context *dapm; 2566 2567 if (!rt5682_clk_check(rt5682)) 2568 return -EINVAL; 2569 2570 component = rt5682->component; 2571 dapm = snd_soc_component_get_dapm(component); 2572 2573 snd_soc_dapm_mutex_lock(dapm); 2574 2575 snd_soc_dapm_force_enable_pin_unlocked(dapm, "MICBIAS"); 2576 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_1, 2577 RT5682_PWR_MB, RT5682_PWR_MB); 2578 2579 snd_soc_dapm_force_enable_pin_unlocked(dapm, "Vref2"); 2580 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_1, 2581 RT5682_PWR_VREF2 | RT5682_PWR_FV2, 2582 RT5682_PWR_VREF2); 2583 usleep_range(55000, 60000); 2584 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_1, 2585 RT5682_PWR_FV2, RT5682_PWR_FV2); 2586 2587 snd_soc_dapm_force_enable_pin_unlocked(dapm, "I2S1"); 2588 snd_soc_dapm_force_enable_pin_unlocked(dapm, "PLL2F"); 2589 snd_soc_dapm_force_enable_pin_unlocked(dapm, "PLL2B"); 2590 snd_soc_dapm_sync_unlocked(dapm); 2591 2592 snd_soc_dapm_mutex_unlock(dapm); 2593 2594 return 0; 2595 } 2596 2597 static void rt5682_wclk_unprepare(struct clk_hw *hw) 2598 { 2599 struct rt5682_priv *rt5682 = 2600 container_of(hw, struct rt5682_priv, 2601 dai_clks_hw[RT5682_DAI_WCLK_IDX]); 2602 struct snd_soc_component *component; 2603 struct snd_soc_dapm_context *dapm; 2604 2605 if (!rt5682_clk_check(rt5682)) 2606 return; 2607 2608 component = rt5682->component; 2609 dapm = snd_soc_component_get_dapm(component); 2610 2611 snd_soc_dapm_mutex_lock(dapm); 2612 2613 snd_soc_dapm_disable_pin_unlocked(dapm, "MICBIAS"); 2614 snd_soc_dapm_disable_pin_unlocked(dapm, "Vref2"); 2615 if (!rt5682->jack_type) 2616 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_1, 2617 RT5682_PWR_VREF2 | RT5682_PWR_FV2 | 2618 RT5682_PWR_MB, 0); 2619 2620 snd_soc_dapm_disable_pin_unlocked(dapm, "I2S1"); 2621 snd_soc_dapm_disable_pin_unlocked(dapm, "PLL2F"); 2622 snd_soc_dapm_disable_pin_unlocked(dapm, "PLL2B"); 2623 snd_soc_dapm_sync_unlocked(dapm); 2624 2625 snd_soc_dapm_mutex_unlock(dapm); 2626 } 2627 2628 static unsigned long rt5682_wclk_recalc_rate(struct clk_hw *hw, 2629 unsigned long parent_rate) 2630 { 2631 struct rt5682_priv *rt5682 = 2632 container_of(hw, struct rt5682_priv, 2633 dai_clks_hw[RT5682_DAI_WCLK_IDX]); 2634 const char * const clk_name = clk_hw_get_name(hw); 2635 2636 if (!rt5682_clk_check(rt5682)) 2637 return 0; 2638 /* 2639 * Only accept to set wclk rate to 44.1k or 48kHz. 2640 */ 2641 if (rt5682->lrck[RT5682_AIF1] != CLK_48 && 2642 rt5682->lrck[RT5682_AIF1] != CLK_44) { 2643 dev_warn(rt5682->i2c_dev, "%s: clk %s only support %d or %d Hz output\n", 2644 __func__, clk_name, CLK_44, CLK_48); 2645 return 0; 2646 } 2647 2648 return rt5682->lrck[RT5682_AIF1]; 2649 } 2650 2651 static long rt5682_wclk_round_rate(struct clk_hw *hw, unsigned long rate, 2652 unsigned long *parent_rate) 2653 { 2654 struct rt5682_priv *rt5682 = 2655 container_of(hw, struct rt5682_priv, 2656 dai_clks_hw[RT5682_DAI_WCLK_IDX]); 2657 const char * const clk_name = clk_hw_get_name(hw); 2658 2659 if (!rt5682_clk_check(rt5682)) 2660 return -EINVAL; 2661 /* 2662 * Only accept to set wclk rate to 44.1k or 48kHz. 2663 * It will force to 48kHz if not both. 2664 */ 2665 if (rate != CLK_48 && rate != CLK_44) { 2666 dev_warn(rt5682->i2c_dev, "%s: clk %s only support %d or %d Hz output\n", 2667 __func__, clk_name, CLK_44, CLK_48); 2668 rate = CLK_48; 2669 } 2670 2671 return rate; 2672 } 2673 2674 static int rt5682_wclk_set_rate(struct clk_hw *hw, unsigned long rate, 2675 unsigned long parent_rate) 2676 { 2677 struct rt5682_priv *rt5682 = 2678 container_of(hw, struct rt5682_priv, 2679 dai_clks_hw[RT5682_DAI_WCLK_IDX]); 2680 struct snd_soc_component *component; 2681 struct clk_hw *parent_hw; 2682 const char * const clk_name = clk_hw_get_name(hw); 2683 int pre_div; 2684 unsigned int clk_pll2_out; 2685 2686 if (!rt5682_clk_check(rt5682)) 2687 return -EINVAL; 2688 2689 component = rt5682->component; 2690 2691 /* 2692 * Whether the wclk's parent clk (mclk) exists or not, please ensure 2693 * it is fixed or set to 48MHz before setting wclk rate. It's a 2694 * temporary limitation. Only accept 48MHz clk as the clk provider. 2695 * 2696 * It will set the codec anyway by assuming mclk is 48MHz. 2697 */ 2698 parent_hw = clk_hw_get_parent(hw); 2699 if (!parent_hw) 2700 dev_warn(rt5682->i2c_dev, 2701 "Parent mclk of wclk not acquired in driver. Please ensure mclk was provided as %d Hz.\n", 2702 CLK_PLL2_FIN); 2703 2704 if (parent_rate != CLK_PLL2_FIN) 2705 dev_warn(rt5682->i2c_dev, "clk %s only support %d Hz input\n", 2706 clk_name, CLK_PLL2_FIN); 2707 2708 /* 2709 * To achieve the rate conversion from 48MHz to 44.1k or 48kHz, 2710 * PLL2 is needed. 2711 */ 2712 clk_pll2_out = rate * 512; 2713 rt5682_set_component_pll(component, RT5682_PLL2, RT5682_PLL2_S_MCLK, 2714 CLK_PLL2_FIN, clk_pll2_out); 2715 2716 rt5682_set_component_sysclk(component, RT5682_SCLK_S_PLL2, 0, 2717 clk_pll2_out, SND_SOC_CLOCK_IN); 2718 2719 rt5682->lrck[RT5682_AIF1] = rate; 2720 2721 pre_div = rl6231_get_clk_info(rt5682->sysclk, rate); 2722 2723 snd_soc_component_update_bits(component, RT5682_ADDA_CLK_1, 2724 RT5682_I2S_M_DIV_MASK | RT5682_I2S_CLK_SRC_MASK, 2725 pre_div << RT5682_I2S_M_DIV_SFT | 2726 (rt5682->sysclk_src) << RT5682_I2S_CLK_SRC_SFT); 2727 2728 return 0; 2729 } 2730 2731 static unsigned long rt5682_bclk_recalc_rate(struct clk_hw *hw, 2732 unsigned long parent_rate) 2733 { 2734 struct rt5682_priv *rt5682 = 2735 container_of(hw, struct rt5682_priv, 2736 dai_clks_hw[RT5682_DAI_BCLK_IDX]); 2737 unsigned int bclks_per_wclk; 2738 2739 regmap_read(rt5682->regmap, RT5682_TDM_TCON_CTRL, &bclks_per_wclk); 2740 2741 switch (bclks_per_wclk & RT5682_TDM_BCLK_MS1_MASK) { 2742 case RT5682_TDM_BCLK_MS1_256: 2743 return parent_rate * 256; 2744 case RT5682_TDM_BCLK_MS1_128: 2745 return parent_rate * 128; 2746 case RT5682_TDM_BCLK_MS1_64: 2747 return parent_rate * 64; 2748 case RT5682_TDM_BCLK_MS1_32: 2749 return parent_rate * 32; 2750 default: 2751 return 0; 2752 } 2753 } 2754 2755 static unsigned long rt5682_bclk_get_factor(unsigned long rate, 2756 unsigned long parent_rate) 2757 { 2758 unsigned long factor; 2759 2760 factor = rate / parent_rate; 2761 if (factor < 64) 2762 return 32; 2763 else if (factor < 128) 2764 return 64; 2765 else if (factor < 256) 2766 return 128; 2767 else 2768 return 256; 2769 } 2770 2771 static long rt5682_bclk_round_rate(struct clk_hw *hw, unsigned long rate, 2772 unsigned long *parent_rate) 2773 { 2774 struct rt5682_priv *rt5682 = 2775 container_of(hw, struct rt5682_priv, 2776 dai_clks_hw[RT5682_DAI_BCLK_IDX]); 2777 unsigned long factor; 2778 2779 if (!*parent_rate || !rt5682_clk_check(rt5682)) 2780 return -EINVAL; 2781 2782 /* 2783 * BCLK rates are set as a multiplier of WCLK in HW. 2784 * We don't allow changing the parent WCLK. We just do 2785 * some rounding down based on the parent WCLK rate 2786 * and find the appropriate multiplier of BCLK to 2787 * get the rounded down BCLK value. 2788 */ 2789 factor = rt5682_bclk_get_factor(rate, *parent_rate); 2790 2791 return *parent_rate * factor; 2792 } 2793 2794 static int rt5682_bclk_set_rate(struct clk_hw *hw, unsigned long rate, 2795 unsigned long parent_rate) 2796 { 2797 struct rt5682_priv *rt5682 = 2798 container_of(hw, struct rt5682_priv, 2799 dai_clks_hw[RT5682_DAI_BCLK_IDX]); 2800 struct snd_soc_component *component; 2801 struct snd_soc_dai *dai; 2802 unsigned long factor; 2803 2804 if (!rt5682_clk_check(rt5682)) 2805 return -EINVAL; 2806 2807 component = rt5682->component; 2808 2809 factor = rt5682_bclk_get_factor(rate, parent_rate); 2810 2811 for_each_component_dais(component, dai) 2812 if (dai->id == RT5682_AIF1) 2813 break; 2814 if (!dai) { 2815 dev_err(rt5682->i2c_dev, "dai %d not found in component\n", 2816 RT5682_AIF1); 2817 return -ENODEV; 2818 } 2819 2820 return rt5682_set_bclk1_ratio(dai, factor); 2821 } 2822 2823 static const struct clk_ops rt5682_dai_clk_ops[RT5682_DAI_NUM_CLKS] = { 2824 [RT5682_DAI_WCLK_IDX] = { 2825 .prepare = rt5682_wclk_prepare, 2826 .unprepare = rt5682_wclk_unprepare, 2827 .recalc_rate = rt5682_wclk_recalc_rate, 2828 .round_rate = rt5682_wclk_round_rate, 2829 .set_rate = rt5682_wclk_set_rate, 2830 }, 2831 [RT5682_DAI_BCLK_IDX] = { 2832 .recalc_rate = rt5682_bclk_recalc_rate, 2833 .round_rate = rt5682_bclk_round_rate, 2834 .set_rate = rt5682_bclk_set_rate, 2835 }, 2836 }; 2837 2838 int rt5682_register_dai_clks(struct rt5682_priv *rt5682) 2839 { 2840 struct device *dev = rt5682->i2c_dev; 2841 struct rt5682_platform_data *pdata = &rt5682->pdata; 2842 struct clk_hw *dai_clk_hw; 2843 int i, ret; 2844 2845 for (i = 0; i < RT5682_DAI_NUM_CLKS; ++i) { 2846 struct clk_init_data init = { }; 2847 2848 dai_clk_hw = &rt5682->dai_clks_hw[i]; 2849 2850 switch (i) { 2851 case RT5682_DAI_WCLK_IDX: 2852 /* Make MCLK the parent of WCLK */ 2853 if (rt5682->mclk) { 2854 init.parent_data = &(struct clk_parent_data){ 2855 .fw_name = "mclk", 2856 }; 2857 init.num_parents = 1; 2858 } 2859 break; 2860 case RT5682_DAI_BCLK_IDX: 2861 /* Make WCLK the parent of BCLK */ 2862 init.parent_hws = &(const struct clk_hw *){ 2863 &rt5682->dai_clks_hw[RT5682_DAI_WCLK_IDX] 2864 }; 2865 init.num_parents = 1; 2866 break; 2867 default: 2868 dev_err(dev, "Invalid clock index\n"); 2869 return -EINVAL; 2870 } 2871 2872 init.name = pdata->dai_clk_names[i]; 2873 init.ops = &rt5682_dai_clk_ops[i]; 2874 init.flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_GATE; 2875 dai_clk_hw->init = &init; 2876 2877 ret = devm_clk_hw_register(dev, dai_clk_hw); 2878 if (ret) { 2879 dev_warn(dev, "Failed to register %s: %d\n", 2880 init.name, ret); 2881 return ret; 2882 } 2883 2884 if (dev->of_node) { 2885 devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, 2886 dai_clk_hw); 2887 } else { 2888 ret = devm_clk_hw_register_clkdev(dev, dai_clk_hw, 2889 init.name, 2890 dev_name(dev)); 2891 if (ret) 2892 return ret; 2893 } 2894 } 2895 2896 return 0; 2897 } 2898 EXPORT_SYMBOL_GPL(rt5682_register_dai_clks); 2899 #endif /* CONFIG_COMMON_CLK */ 2900 2901 static int rt5682_probe(struct snd_soc_component *component) 2902 { 2903 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 2904 struct sdw_slave *slave; 2905 unsigned long time; 2906 struct snd_soc_dapm_context *dapm = &component->dapm; 2907 2908 rt5682->component = component; 2909 2910 if (rt5682->is_sdw) { 2911 slave = rt5682->slave; 2912 time = wait_for_completion_timeout( 2913 &slave->initialization_complete, 2914 msecs_to_jiffies(RT5682_PROBE_TIMEOUT)); 2915 if (!time) { 2916 dev_err(&slave->dev, "Initialization not complete, timed out\n"); 2917 return -ETIMEDOUT; 2918 } 2919 } 2920 2921 snd_soc_dapm_disable_pin(dapm, "MICBIAS"); 2922 snd_soc_dapm_disable_pin(dapm, "Vref2"); 2923 snd_soc_dapm_sync(dapm); 2924 return 0; 2925 } 2926 2927 static void rt5682_remove(struct snd_soc_component *component) 2928 { 2929 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 2930 2931 rt5682_reset(rt5682); 2932 } 2933 2934 #ifdef CONFIG_PM 2935 static int rt5682_suspend(struct snd_soc_component *component) 2936 { 2937 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 2938 unsigned int val; 2939 2940 if (rt5682->is_sdw) 2941 return 0; 2942 2943 cancel_delayed_work_sync(&rt5682->jack_detect_work); 2944 cancel_delayed_work_sync(&rt5682->jd_check_work); 2945 if (rt5682->hs_jack && rt5682->jack_type == SND_JACK_HEADSET) { 2946 snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1, 2947 RT5682_MB1_PATH_MASK | RT5682_MB2_PATH_MASK, 2948 RT5682_CTRL_MB1_REG | RT5682_CTRL_MB2_REG); 2949 val = snd_soc_component_read(component, 2950 RT5682_CBJ_CTRL_2) & RT5682_JACK_TYPE_MASK; 2951 2952 switch (val) { 2953 case 0x1: 2954 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1, 2955 RT5682_SAR_SEL_MB1_MASK | RT5682_SAR_SEL_MB2_MASK, 2956 RT5682_SAR_SEL_MB1_NOSEL | RT5682_SAR_SEL_MB2_SEL); 2957 break; 2958 case 0x2: 2959 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1, 2960 RT5682_SAR_SEL_MB1_MASK | RT5682_SAR_SEL_MB2_MASK, 2961 RT5682_SAR_SEL_MB1_SEL | RT5682_SAR_SEL_MB2_NOSEL); 2962 break; 2963 default: 2964 break; 2965 } 2966 2967 /* enter SAR ADC power saving mode */ 2968 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1, 2969 RT5682_SAR_BUTT_DET_MASK | RT5682_SAR_BUTDET_MODE_MASK | 2970 RT5682_SAR_BUTDET_RST_MASK | RT5682_SAR_SEL_MB1_MB2_MASK, 0); 2971 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1, 2972 RT5682_SAR_BUTT_DET_MASK | RT5682_SAR_BUTDET_MODE_MASK | RT5682_SAR_BUTDET_RST_MASK, 2973 RT5682_SAR_BUTT_DET_EN | RT5682_SAR_BUTDET_POW_SAV | RT5682_SAR_BUTDET_RST_NORMAL); 2974 } 2975 2976 regcache_cache_only(rt5682->regmap, true); 2977 regcache_mark_dirty(rt5682->regmap); 2978 return 0; 2979 } 2980 2981 static int rt5682_resume(struct snd_soc_component *component) 2982 { 2983 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 2984 2985 if (rt5682->is_sdw) 2986 return 0; 2987 2988 regcache_cache_only(rt5682->regmap, false); 2989 regcache_sync(rt5682->regmap); 2990 2991 if (rt5682->hs_jack && rt5682->jack_type == SND_JACK_HEADSET) { 2992 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1, 2993 RT5682_SAR_BUTDET_MODE_MASK | RT5682_SAR_SEL_MB1_MB2_MASK, 2994 RT5682_SAR_BUTDET_POW_NORM | RT5682_SAR_SEL_MB1_MB2_AUTO); 2995 snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1, 2996 RT5682_MB1_PATH_MASK | RT5682_MB2_PATH_MASK, 2997 RT5682_CTRL_MB1_FSM | RT5682_CTRL_MB2_FSM); 2998 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_3, 2999 RT5682_PWR_CBJ, RT5682_PWR_CBJ); 3000 } 3001 3002 mod_delayed_work(system_power_efficient_wq, 3003 &rt5682->jack_detect_work, msecs_to_jiffies(250)); 3004 3005 return 0; 3006 } 3007 #else 3008 #define rt5682_suspend NULL 3009 #define rt5682_resume NULL 3010 #endif 3011 3012 const struct snd_soc_dai_ops rt5682_aif1_dai_ops = { 3013 .hw_params = rt5682_hw_params, 3014 .set_fmt = rt5682_set_dai_fmt, 3015 .set_tdm_slot = rt5682_set_tdm_slot, 3016 .set_bclk_ratio = rt5682_set_bclk1_ratio, 3017 }; 3018 EXPORT_SYMBOL_GPL(rt5682_aif1_dai_ops); 3019 3020 const struct snd_soc_dai_ops rt5682_aif2_dai_ops = { 3021 .hw_params = rt5682_hw_params, 3022 .set_fmt = rt5682_set_dai_fmt, 3023 .set_bclk_ratio = rt5682_set_bclk2_ratio, 3024 }; 3025 EXPORT_SYMBOL_GPL(rt5682_aif2_dai_ops); 3026 3027 const struct snd_soc_component_driver rt5682_soc_component_dev = { 3028 .probe = rt5682_probe, 3029 .remove = rt5682_remove, 3030 .suspend = rt5682_suspend, 3031 .resume = rt5682_resume, 3032 .set_bias_level = rt5682_set_bias_level, 3033 .controls = rt5682_snd_controls, 3034 .num_controls = ARRAY_SIZE(rt5682_snd_controls), 3035 .dapm_widgets = rt5682_dapm_widgets, 3036 .num_dapm_widgets = ARRAY_SIZE(rt5682_dapm_widgets), 3037 .dapm_routes = rt5682_dapm_routes, 3038 .num_dapm_routes = ARRAY_SIZE(rt5682_dapm_routes), 3039 .set_sysclk = rt5682_set_component_sysclk, 3040 .set_pll = rt5682_set_component_pll, 3041 .set_jack = rt5682_set_jack_detect, 3042 .use_pmdown_time = 1, 3043 .endianness = 1, 3044 .non_legacy_dai_naming = 1, 3045 }; 3046 EXPORT_SYMBOL_GPL(rt5682_soc_component_dev); 3047 3048 int rt5682_parse_dt(struct rt5682_priv *rt5682, struct device *dev) 3049 { 3050 3051 device_property_read_u32(dev, "realtek,dmic1-data-pin", 3052 &rt5682->pdata.dmic1_data_pin); 3053 device_property_read_u32(dev, "realtek,dmic1-clk-pin", 3054 &rt5682->pdata.dmic1_clk_pin); 3055 device_property_read_u32(dev, "realtek,jd-src", 3056 &rt5682->pdata.jd_src); 3057 device_property_read_u32(dev, "realtek,btndet-delay", 3058 &rt5682->pdata.btndet_delay); 3059 device_property_read_u32(dev, "realtek,dmic-clk-rate-hz", 3060 &rt5682->pdata.dmic_clk_rate); 3061 device_property_read_u32(dev, "realtek,dmic-delay-ms", 3062 &rt5682->pdata.dmic_delay); 3063 3064 rt5682->pdata.ldo1_en = of_get_named_gpio(dev->of_node, 3065 "realtek,ldo1-en-gpios", 0); 3066 3067 if (device_property_read_string_array(dev, "clock-output-names", 3068 rt5682->pdata.dai_clk_names, 3069 RT5682_DAI_NUM_CLKS) < 0) 3070 dev_warn(dev, "Using default DAI clk names: %s, %s\n", 3071 rt5682->pdata.dai_clk_names[RT5682_DAI_WCLK_IDX], 3072 rt5682->pdata.dai_clk_names[RT5682_DAI_BCLK_IDX]); 3073 3074 rt5682->pdata.dmic_clk_driving_high = device_property_read_bool(dev, 3075 "realtek,dmic-clk-driving-high"); 3076 3077 return 0; 3078 } 3079 EXPORT_SYMBOL_GPL(rt5682_parse_dt); 3080 3081 void rt5682_calibrate(struct rt5682_priv *rt5682) 3082 { 3083 int value, count; 3084 3085 mutex_lock(&rt5682->calibrate_mutex); 3086 3087 rt5682_reset(rt5682); 3088 regmap_write(rt5682->regmap, RT5682_I2C_CTRL, 0x000f); 3089 regmap_write(rt5682->regmap, RT5682_PWR_ANLG_1, 0xa2af); 3090 usleep_range(15000, 20000); 3091 regmap_write(rt5682->regmap, RT5682_PWR_ANLG_1, 0xf2af); 3092 regmap_write(rt5682->regmap, RT5682_MICBIAS_2, 0x0300); 3093 regmap_write(rt5682->regmap, RT5682_GLB_CLK, 0x8000); 3094 regmap_write(rt5682->regmap, RT5682_PWR_DIG_1, 0x0100); 3095 regmap_write(rt5682->regmap, RT5682_HP_IMP_SENS_CTRL_19, 0x3800); 3096 regmap_write(rt5682->regmap, RT5682_CHOP_DAC, 0x3000); 3097 regmap_write(rt5682->regmap, RT5682_CALIB_ADC_CTRL, 0x7005); 3098 regmap_write(rt5682->regmap, RT5682_STO1_ADC_MIXER, 0x686c); 3099 regmap_write(rt5682->regmap, RT5682_CAL_REC, 0x0d0d); 3100 regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_2, 0x0321); 3101 regmap_write(rt5682->regmap, RT5682_HP_LOGIC_CTRL_2, 0x0004); 3102 regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_1, 0x7c00); 3103 regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_3, 0x06a1); 3104 regmap_write(rt5682->regmap, RT5682_A_DAC1_MUX, 0x0311); 3105 regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_1, 0x7c00); 3106 3107 regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_1, 0xfc00); 3108 3109 for (count = 0; count < 60; count++) { 3110 regmap_read(rt5682->regmap, RT5682_HP_CALIB_STA_1, &value); 3111 if (!(value & 0x8000)) 3112 break; 3113 3114 usleep_range(10000, 10005); 3115 } 3116 3117 if (count >= 60) 3118 dev_err(rt5682->component->dev, "HP Calibration Failure\n"); 3119 3120 /* restore settings */ 3121 regmap_write(rt5682->regmap, RT5682_PWR_ANLG_1, 0x002f); 3122 regmap_write(rt5682->regmap, RT5682_MICBIAS_2, 0x0080); 3123 regmap_write(rt5682->regmap, RT5682_GLB_CLK, 0x0000); 3124 regmap_write(rt5682->regmap, RT5682_PWR_DIG_1, 0x0000); 3125 regmap_write(rt5682->regmap, RT5682_CHOP_DAC, 0x2000); 3126 regmap_write(rt5682->regmap, RT5682_CALIB_ADC_CTRL, 0x2005); 3127 regmap_write(rt5682->regmap, RT5682_STO1_ADC_MIXER, 0xc0c4); 3128 regmap_write(rt5682->regmap, RT5682_CAL_REC, 0x0c0c); 3129 3130 mutex_unlock(&rt5682->calibrate_mutex); 3131 } 3132 EXPORT_SYMBOL_GPL(rt5682_calibrate); 3133 3134 MODULE_DESCRIPTION("ASoC RT5682 driver"); 3135 MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>"); 3136 MODULE_LICENSE("GPL v2"); 3137