1 // SPDX-License-Identifier: GPL-2.0-only 2 // 3 // rt5682.c -- RT5682 ALSA SoC audio component driver 4 // 5 // Copyright 2018 Realtek Semiconductor Corp. 6 // Author: Bard Liao <bardliao@realtek.com> 7 // 8 9 #include <linux/module.h> 10 #include <linux/moduleparam.h> 11 #include <linux/init.h> 12 #include <linux/delay.h> 13 #include <linux/pm.h> 14 #include <linux/pm_runtime.h> 15 #include <linux/platform_device.h> 16 #include <linux/spi/spi.h> 17 #include <linux/acpi.h> 18 #include <linux/gpio.h> 19 #include <linux/of_gpio.h> 20 #include <linux/mutex.h> 21 #include <sound/core.h> 22 #include <sound/pcm.h> 23 #include <sound/pcm_params.h> 24 #include <sound/jack.h> 25 #include <sound/soc.h> 26 #include <sound/soc-dapm.h> 27 #include <sound/initval.h> 28 #include <sound/tlv.h> 29 #include <sound/rt5682.h> 30 31 #include "rl6231.h" 32 #include "rt5682.h" 33 34 const char *rt5682_supply_names[RT5682_NUM_SUPPLIES] = { 35 "AVDD", 36 "MICVDD", 37 "VBAT", 38 }; 39 EXPORT_SYMBOL_GPL(rt5682_supply_names); 40 41 static const struct reg_sequence patch_list[] = { 42 {RT5682_HP_IMP_SENS_CTRL_19, 0x1000}, 43 {RT5682_DAC_ADC_DIG_VOL1, 0xa020}, 44 {RT5682_I2C_CTRL, 0x000f}, 45 {RT5682_PLL2_INTERNAL, 0x8266}, 46 }; 47 48 void rt5682_apply_patch_list(struct rt5682_priv *rt5682, struct device *dev) 49 { 50 int ret; 51 52 ret = regmap_multi_reg_write(rt5682->regmap, patch_list, 53 ARRAY_SIZE(patch_list)); 54 if (ret) 55 dev_warn(dev, "Failed to apply regmap patch: %d\n", ret); 56 } 57 EXPORT_SYMBOL_GPL(rt5682_apply_patch_list); 58 59 const struct reg_default rt5682_reg[RT5682_REG_NUM] = { 60 {0x0002, 0x8080}, 61 {0x0003, 0x8000}, 62 {0x0005, 0x0000}, 63 {0x0006, 0x0000}, 64 {0x0008, 0x800f}, 65 {0x000b, 0x0000}, 66 {0x0010, 0x4040}, 67 {0x0011, 0x0000}, 68 {0x0012, 0x1404}, 69 {0x0013, 0x1000}, 70 {0x0014, 0xa00a}, 71 {0x0015, 0x0404}, 72 {0x0016, 0x0404}, 73 {0x0019, 0xafaf}, 74 {0x001c, 0x2f2f}, 75 {0x001f, 0x0000}, 76 {0x0022, 0x5757}, 77 {0x0023, 0x0039}, 78 {0x0024, 0x000b}, 79 {0x0026, 0xc0c4}, 80 {0x0029, 0x8080}, 81 {0x002a, 0xa0a0}, 82 {0x002b, 0x0300}, 83 {0x0030, 0x0000}, 84 {0x003c, 0x0080}, 85 {0x0044, 0x0c0c}, 86 {0x0049, 0x0000}, 87 {0x0061, 0x0000}, 88 {0x0062, 0x0000}, 89 {0x0063, 0x003f}, 90 {0x0064, 0x0000}, 91 {0x0065, 0x0000}, 92 {0x0066, 0x0030}, 93 {0x0067, 0x0000}, 94 {0x006b, 0x0000}, 95 {0x006c, 0x0000}, 96 {0x006d, 0x2200}, 97 {0x006e, 0x0a10}, 98 {0x0070, 0x8000}, 99 {0x0071, 0x8000}, 100 {0x0073, 0x0000}, 101 {0x0074, 0x0000}, 102 {0x0075, 0x0002}, 103 {0x0076, 0x0001}, 104 {0x0079, 0x0000}, 105 {0x007a, 0x0000}, 106 {0x007b, 0x0000}, 107 {0x007c, 0x0100}, 108 {0x007e, 0x0000}, 109 {0x0080, 0x0000}, 110 {0x0081, 0x0000}, 111 {0x0082, 0x0000}, 112 {0x0083, 0x0000}, 113 {0x0084, 0x0000}, 114 {0x0085, 0x0000}, 115 {0x0086, 0x0005}, 116 {0x0087, 0x0000}, 117 {0x0088, 0x0000}, 118 {0x008c, 0x0003}, 119 {0x008d, 0x0000}, 120 {0x008e, 0x0060}, 121 {0x008f, 0x1000}, 122 {0x0091, 0x0c26}, 123 {0x0092, 0x0073}, 124 {0x0093, 0x0000}, 125 {0x0094, 0x0080}, 126 {0x0098, 0x0000}, 127 {0x009a, 0x0000}, 128 {0x009b, 0x0000}, 129 {0x009c, 0x0000}, 130 {0x009d, 0x0000}, 131 {0x009e, 0x100c}, 132 {0x009f, 0x0000}, 133 {0x00a0, 0x0000}, 134 {0x00a3, 0x0002}, 135 {0x00a4, 0x0001}, 136 {0x00ae, 0x2040}, 137 {0x00af, 0x0000}, 138 {0x00b6, 0x0000}, 139 {0x00b7, 0x0000}, 140 {0x00b8, 0x0000}, 141 {0x00b9, 0x0002}, 142 {0x00be, 0x0000}, 143 {0x00c0, 0x0160}, 144 {0x00c1, 0x82a0}, 145 {0x00c2, 0x0000}, 146 {0x00d0, 0x0000}, 147 {0x00d1, 0x2244}, 148 {0x00d2, 0x3300}, 149 {0x00d3, 0x2200}, 150 {0x00d4, 0x0000}, 151 {0x00d9, 0x0009}, 152 {0x00da, 0x0000}, 153 {0x00db, 0x0000}, 154 {0x00dc, 0x00c0}, 155 {0x00dd, 0x2220}, 156 {0x00de, 0x3131}, 157 {0x00df, 0x3131}, 158 {0x00e0, 0x3131}, 159 {0x00e2, 0x0000}, 160 {0x00e3, 0x4000}, 161 {0x00e4, 0x0aa0}, 162 {0x00e5, 0x3131}, 163 {0x00e6, 0x3131}, 164 {0x00e7, 0x3131}, 165 {0x00e8, 0x3131}, 166 {0x00ea, 0xb320}, 167 {0x00eb, 0x0000}, 168 {0x00f0, 0x0000}, 169 {0x00f1, 0x00d0}, 170 {0x00f2, 0x00d0}, 171 {0x00f6, 0x0000}, 172 {0x00fa, 0x0000}, 173 {0x00fb, 0x0000}, 174 {0x00fc, 0x0000}, 175 {0x00fd, 0x0000}, 176 {0x00fe, 0x10ec}, 177 {0x00ff, 0x6530}, 178 {0x0100, 0xa0a0}, 179 {0x010b, 0x0000}, 180 {0x010c, 0xae00}, 181 {0x010d, 0xaaa0}, 182 {0x010e, 0x8aa2}, 183 {0x010f, 0x02a2}, 184 {0x0110, 0xc000}, 185 {0x0111, 0x04a2}, 186 {0x0112, 0x2800}, 187 {0x0113, 0x0000}, 188 {0x0117, 0x0100}, 189 {0x0125, 0x0410}, 190 {0x0132, 0x6026}, 191 {0x0136, 0x5555}, 192 {0x0138, 0x3700}, 193 {0x013a, 0x2000}, 194 {0x013b, 0x2000}, 195 {0x013c, 0x2005}, 196 {0x013f, 0x0000}, 197 {0x0142, 0x0000}, 198 {0x0145, 0x0002}, 199 {0x0146, 0x0000}, 200 {0x0147, 0x0000}, 201 {0x0148, 0x0000}, 202 {0x0149, 0x0000}, 203 {0x0150, 0x79a1}, 204 {0x0156, 0xaaaa}, 205 {0x0160, 0x4ec0}, 206 {0x0161, 0x0080}, 207 {0x0162, 0x0200}, 208 {0x0163, 0x0800}, 209 {0x0164, 0x0000}, 210 {0x0165, 0x0000}, 211 {0x0166, 0x0000}, 212 {0x0167, 0x000f}, 213 {0x0168, 0x000f}, 214 {0x0169, 0x0021}, 215 {0x0190, 0x413d}, 216 {0x0194, 0x0000}, 217 {0x0195, 0x0000}, 218 {0x0197, 0x0022}, 219 {0x0198, 0x0000}, 220 {0x0199, 0x0000}, 221 {0x01af, 0x0000}, 222 {0x01b0, 0x0400}, 223 {0x01b1, 0x0000}, 224 {0x01b2, 0x0000}, 225 {0x01b3, 0x0000}, 226 {0x01b4, 0x0000}, 227 {0x01b5, 0x0000}, 228 {0x01b6, 0x01c3}, 229 {0x01b7, 0x02a0}, 230 {0x01b8, 0x03e9}, 231 {0x01b9, 0x1389}, 232 {0x01ba, 0xc351}, 233 {0x01bb, 0x0009}, 234 {0x01bc, 0x0018}, 235 {0x01bd, 0x002a}, 236 {0x01be, 0x004c}, 237 {0x01bf, 0x0097}, 238 {0x01c0, 0x433d}, 239 {0x01c2, 0x0000}, 240 {0x01c3, 0x0000}, 241 {0x01c4, 0x0000}, 242 {0x01c5, 0x0000}, 243 {0x01c6, 0x0000}, 244 {0x01c7, 0x0000}, 245 {0x01c8, 0x40af}, 246 {0x01c9, 0x0702}, 247 {0x01ca, 0x0000}, 248 {0x01cb, 0x0000}, 249 {0x01cc, 0x5757}, 250 {0x01cd, 0x5757}, 251 {0x01ce, 0x5757}, 252 {0x01cf, 0x5757}, 253 {0x01d0, 0x5757}, 254 {0x01d1, 0x5757}, 255 {0x01d2, 0x5757}, 256 {0x01d3, 0x5757}, 257 {0x01d4, 0x5757}, 258 {0x01d5, 0x5757}, 259 {0x01d6, 0x0000}, 260 {0x01d7, 0x0008}, 261 {0x01d8, 0x0029}, 262 {0x01d9, 0x3333}, 263 {0x01da, 0x0000}, 264 {0x01db, 0x0004}, 265 {0x01dc, 0x0000}, 266 {0x01de, 0x7c00}, 267 {0x01df, 0x0320}, 268 {0x01e0, 0x06a1}, 269 {0x01e1, 0x0000}, 270 {0x01e2, 0x0000}, 271 {0x01e3, 0x0000}, 272 {0x01e4, 0x0000}, 273 {0x01e6, 0x0001}, 274 {0x01e7, 0x0000}, 275 {0x01e8, 0x0000}, 276 {0x01ea, 0x0000}, 277 {0x01eb, 0x0000}, 278 {0x01ec, 0x0000}, 279 {0x01ed, 0x0000}, 280 {0x01ee, 0x0000}, 281 {0x01ef, 0x0000}, 282 {0x01f0, 0x0000}, 283 {0x01f1, 0x0000}, 284 {0x01f2, 0x0000}, 285 {0x01f3, 0x0000}, 286 {0x01f4, 0x0000}, 287 {0x0210, 0x6297}, 288 {0x0211, 0xa005}, 289 {0x0212, 0x824c}, 290 {0x0213, 0xf7ff}, 291 {0x0214, 0xf24c}, 292 {0x0215, 0x0102}, 293 {0x0216, 0x00a3}, 294 {0x0217, 0x0048}, 295 {0x0218, 0xa2c0}, 296 {0x0219, 0x0400}, 297 {0x021a, 0x00c8}, 298 {0x021b, 0x00c0}, 299 {0x021c, 0x0000}, 300 {0x0250, 0x4500}, 301 {0x0251, 0x40b3}, 302 {0x0252, 0x0000}, 303 {0x0253, 0x0000}, 304 {0x0254, 0x0000}, 305 {0x0255, 0x0000}, 306 {0x0256, 0x0000}, 307 {0x0257, 0x0000}, 308 {0x0258, 0x0000}, 309 {0x0259, 0x0000}, 310 {0x025a, 0x0005}, 311 {0x0270, 0x0000}, 312 {0x02ff, 0x0110}, 313 {0x0300, 0x001f}, 314 {0x0301, 0x032c}, 315 {0x0302, 0x5f21}, 316 {0x0303, 0x4000}, 317 {0x0304, 0x4000}, 318 {0x0305, 0x06d5}, 319 {0x0306, 0x8000}, 320 {0x0307, 0x0700}, 321 {0x0310, 0x4560}, 322 {0x0311, 0xa4a8}, 323 {0x0312, 0x7418}, 324 {0x0313, 0x0000}, 325 {0x0314, 0x0006}, 326 {0x0315, 0xffff}, 327 {0x0316, 0xc400}, 328 {0x0317, 0x0000}, 329 {0x03c0, 0x7e00}, 330 {0x03c1, 0x8000}, 331 {0x03c2, 0x8000}, 332 {0x03c3, 0x8000}, 333 {0x03c4, 0x8000}, 334 {0x03c5, 0x8000}, 335 {0x03c6, 0x8000}, 336 {0x03c7, 0x8000}, 337 {0x03c8, 0x8000}, 338 {0x03c9, 0x8000}, 339 {0x03ca, 0x8000}, 340 {0x03cb, 0x8000}, 341 {0x03cc, 0x8000}, 342 {0x03d0, 0x0000}, 343 {0x03d1, 0x0000}, 344 {0x03d2, 0x0000}, 345 {0x03d3, 0x0000}, 346 {0x03d4, 0x2000}, 347 {0x03d5, 0x2000}, 348 {0x03d6, 0x0000}, 349 {0x03d7, 0x0000}, 350 {0x03d8, 0x2000}, 351 {0x03d9, 0x2000}, 352 {0x03da, 0x2000}, 353 {0x03db, 0x2000}, 354 {0x03dc, 0x0000}, 355 {0x03dd, 0x0000}, 356 {0x03de, 0x0000}, 357 {0x03df, 0x2000}, 358 {0x03e0, 0x0000}, 359 {0x03e1, 0x0000}, 360 {0x03e2, 0x0000}, 361 {0x03e3, 0x0000}, 362 {0x03e4, 0x0000}, 363 {0x03e5, 0x0000}, 364 {0x03e6, 0x0000}, 365 {0x03e7, 0x0000}, 366 {0x03e8, 0x0000}, 367 {0x03e9, 0x0000}, 368 {0x03ea, 0x0000}, 369 {0x03eb, 0x0000}, 370 {0x03ec, 0x0000}, 371 {0x03ed, 0x0000}, 372 {0x03ee, 0x0000}, 373 {0x03ef, 0x0000}, 374 {0x03f0, 0x0800}, 375 {0x03f1, 0x0800}, 376 {0x03f2, 0x0800}, 377 {0x03f3, 0x0800}, 378 }; 379 EXPORT_SYMBOL_GPL(rt5682_reg); 380 381 bool rt5682_volatile_register(struct device *dev, unsigned int reg) 382 { 383 switch (reg) { 384 case RT5682_RESET: 385 case RT5682_CBJ_CTRL_2: 386 case RT5682_INT_ST_1: 387 case RT5682_4BTN_IL_CMD_1: 388 case RT5682_AJD1_CTRL: 389 case RT5682_HP_CALIB_CTRL_1: 390 case RT5682_DEVICE_ID: 391 case RT5682_I2C_MODE: 392 case RT5682_HP_CALIB_CTRL_10: 393 case RT5682_EFUSE_CTRL_2: 394 case RT5682_JD_TOP_VC_VTRL: 395 case RT5682_HP_IMP_SENS_CTRL_19: 396 case RT5682_IL_CMD_1: 397 case RT5682_SAR_IL_CMD_2: 398 case RT5682_SAR_IL_CMD_4: 399 case RT5682_SAR_IL_CMD_10: 400 case RT5682_SAR_IL_CMD_11: 401 case RT5682_EFUSE_CTRL_6...RT5682_EFUSE_CTRL_11: 402 case RT5682_HP_CALIB_STA_1...RT5682_HP_CALIB_STA_11: 403 return true; 404 default: 405 return false; 406 } 407 } 408 EXPORT_SYMBOL_GPL(rt5682_volatile_register); 409 410 bool rt5682_readable_register(struct device *dev, unsigned int reg) 411 { 412 switch (reg) { 413 case RT5682_RESET: 414 case RT5682_VERSION_ID: 415 case RT5682_VENDOR_ID: 416 case RT5682_DEVICE_ID: 417 case RT5682_HP_CTRL_1: 418 case RT5682_HP_CTRL_2: 419 case RT5682_HPL_GAIN: 420 case RT5682_HPR_GAIN: 421 case RT5682_I2C_CTRL: 422 case RT5682_CBJ_BST_CTRL: 423 case RT5682_CBJ_CTRL_1: 424 case RT5682_CBJ_CTRL_2: 425 case RT5682_CBJ_CTRL_3: 426 case RT5682_CBJ_CTRL_4: 427 case RT5682_CBJ_CTRL_5: 428 case RT5682_CBJ_CTRL_6: 429 case RT5682_CBJ_CTRL_7: 430 case RT5682_DAC1_DIG_VOL: 431 case RT5682_STO1_ADC_DIG_VOL: 432 case RT5682_STO1_ADC_BOOST: 433 case RT5682_HP_IMP_GAIN_1: 434 case RT5682_HP_IMP_GAIN_2: 435 case RT5682_SIDETONE_CTRL: 436 case RT5682_STO1_ADC_MIXER: 437 case RT5682_AD_DA_MIXER: 438 case RT5682_STO1_DAC_MIXER: 439 case RT5682_A_DAC1_MUX: 440 case RT5682_DIG_INF2_DATA: 441 case RT5682_REC_MIXER: 442 case RT5682_CAL_REC: 443 case RT5682_ALC_BACK_GAIN: 444 case RT5682_PWR_DIG_1: 445 case RT5682_PWR_DIG_2: 446 case RT5682_PWR_ANLG_1: 447 case RT5682_PWR_ANLG_2: 448 case RT5682_PWR_ANLG_3: 449 case RT5682_PWR_MIXER: 450 case RT5682_PWR_VOL: 451 case RT5682_CLK_DET: 452 case RT5682_RESET_LPF_CTRL: 453 case RT5682_RESET_HPF_CTRL: 454 case RT5682_DMIC_CTRL_1: 455 case RT5682_I2S1_SDP: 456 case RT5682_I2S2_SDP: 457 case RT5682_ADDA_CLK_1: 458 case RT5682_ADDA_CLK_2: 459 case RT5682_I2S1_F_DIV_CTRL_1: 460 case RT5682_I2S1_F_DIV_CTRL_2: 461 case RT5682_TDM_CTRL: 462 case RT5682_TDM_ADDA_CTRL_1: 463 case RT5682_TDM_ADDA_CTRL_2: 464 case RT5682_DATA_SEL_CTRL_1: 465 case RT5682_TDM_TCON_CTRL: 466 case RT5682_GLB_CLK: 467 case RT5682_PLL_CTRL_1: 468 case RT5682_PLL_CTRL_2: 469 case RT5682_PLL_TRACK_1: 470 case RT5682_PLL_TRACK_2: 471 case RT5682_PLL_TRACK_3: 472 case RT5682_PLL_TRACK_4: 473 case RT5682_PLL_TRACK_5: 474 case RT5682_PLL_TRACK_6: 475 case RT5682_PLL_TRACK_11: 476 case RT5682_SDW_REF_CLK: 477 case RT5682_DEPOP_1: 478 case RT5682_DEPOP_2: 479 case RT5682_HP_CHARGE_PUMP_1: 480 case RT5682_HP_CHARGE_PUMP_2: 481 case RT5682_MICBIAS_1: 482 case RT5682_MICBIAS_2: 483 case RT5682_PLL_TRACK_12: 484 case RT5682_PLL_TRACK_14: 485 case RT5682_PLL2_CTRL_1: 486 case RT5682_PLL2_CTRL_2: 487 case RT5682_PLL2_CTRL_3: 488 case RT5682_PLL2_CTRL_4: 489 case RT5682_RC_CLK_CTRL: 490 case RT5682_I2S_M_CLK_CTRL_1: 491 case RT5682_I2S2_F_DIV_CTRL_1: 492 case RT5682_I2S2_F_DIV_CTRL_2: 493 case RT5682_EQ_CTRL_1: 494 case RT5682_EQ_CTRL_2: 495 case RT5682_IRQ_CTRL_1: 496 case RT5682_IRQ_CTRL_2: 497 case RT5682_IRQ_CTRL_3: 498 case RT5682_IRQ_CTRL_4: 499 case RT5682_INT_ST_1: 500 case RT5682_GPIO_CTRL_1: 501 case RT5682_GPIO_CTRL_2: 502 case RT5682_GPIO_CTRL_3: 503 case RT5682_HP_AMP_DET_CTRL_1: 504 case RT5682_HP_AMP_DET_CTRL_2: 505 case RT5682_MID_HP_AMP_DET: 506 case RT5682_LOW_HP_AMP_DET: 507 case RT5682_DELAY_BUF_CTRL: 508 case RT5682_SV_ZCD_1: 509 case RT5682_SV_ZCD_2: 510 case RT5682_IL_CMD_1: 511 case RT5682_IL_CMD_2: 512 case RT5682_IL_CMD_3: 513 case RT5682_IL_CMD_4: 514 case RT5682_IL_CMD_5: 515 case RT5682_IL_CMD_6: 516 case RT5682_4BTN_IL_CMD_1: 517 case RT5682_4BTN_IL_CMD_2: 518 case RT5682_4BTN_IL_CMD_3: 519 case RT5682_4BTN_IL_CMD_4: 520 case RT5682_4BTN_IL_CMD_5: 521 case RT5682_4BTN_IL_CMD_6: 522 case RT5682_4BTN_IL_CMD_7: 523 case RT5682_ADC_STO1_HP_CTRL_1: 524 case RT5682_ADC_STO1_HP_CTRL_2: 525 case RT5682_AJD1_CTRL: 526 case RT5682_JD1_THD: 527 case RT5682_JD2_THD: 528 case RT5682_JD_CTRL_1: 529 case RT5682_DUMMY_1: 530 case RT5682_DUMMY_2: 531 case RT5682_DUMMY_3: 532 case RT5682_DAC_ADC_DIG_VOL1: 533 case RT5682_BIAS_CUR_CTRL_2: 534 case RT5682_BIAS_CUR_CTRL_3: 535 case RT5682_BIAS_CUR_CTRL_4: 536 case RT5682_BIAS_CUR_CTRL_5: 537 case RT5682_BIAS_CUR_CTRL_6: 538 case RT5682_BIAS_CUR_CTRL_7: 539 case RT5682_BIAS_CUR_CTRL_8: 540 case RT5682_BIAS_CUR_CTRL_9: 541 case RT5682_BIAS_CUR_CTRL_10: 542 case RT5682_VREF_REC_OP_FB_CAP_CTRL: 543 case RT5682_CHARGE_PUMP_1: 544 case RT5682_DIG_IN_CTRL_1: 545 case RT5682_PAD_DRIVING_CTRL: 546 case RT5682_SOFT_RAMP_DEPOP: 547 case RT5682_CHOP_DAC: 548 case RT5682_CHOP_ADC: 549 case RT5682_CALIB_ADC_CTRL: 550 case RT5682_VOL_TEST: 551 case RT5682_SPKVDD_DET_STA: 552 case RT5682_TEST_MODE_CTRL_1: 553 case RT5682_TEST_MODE_CTRL_2: 554 case RT5682_TEST_MODE_CTRL_3: 555 case RT5682_TEST_MODE_CTRL_4: 556 case RT5682_TEST_MODE_CTRL_5: 557 case RT5682_PLL1_INTERNAL: 558 case RT5682_PLL2_INTERNAL: 559 case RT5682_STO_NG2_CTRL_1: 560 case RT5682_STO_NG2_CTRL_2: 561 case RT5682_STO_NG2_CTRL_3: 562 case RT5682_STO_NG2_CTRL_4: 563 case RT5682_STO_NG2_CTRL_5: 564 case RT5682_STO_NG2_CTRL_6: 565 case RT5682_STO_NG2_CTRL_7: 566 case RT5682_STO_NG2_CTRL_8: 567 case RT5682_STO_NG2_CTRL_9: 568 case RT5682_STO_NG2_CTRL_10: 569 case RT5682_STO1_DAC_SIL_DET: 570 case RT5682_SIL_PSV_CTRL1: 571 case RT5682_SIL_PSV_CTRL2: 572 case RT5682_SIL_PSV_CTRL3: 573 case RT5682_SIL_PSV_CTRL4: 574 case RT5682_SIL_PSV_CTRL5: 575 case RT5682_HP_IMP_SENS_CTRL_01: 576 case RT5682_HP_IMP_SENS_CTRL_02: 577 case RT5682_HP_IMP_SENS_CTRL_03: 578 case RT5682_HP_IMP_SENS_CTRL_04: 579 case RT5682_HP_IMP_SENS_CTRL_05: 580 case RT5682_HP_IMP_SENS_CTRL_06: 581 case RT5682_HP_IMP_SENS_CTRL_07: 582 case RT5682_HP_IMP_SENS_CTRL_08: 583 case RT5682_HP_IMP_SENS_CTRL_09: 584 case RT5682_HP_IMP_SENS_CTRL_10: 585 case RT5682_HP_IMP_SENS_CTRL_11: 586 case RT5682_HP_IMP_SENS_CTRL_12: 587 case RT5682_HP_IMP_SENS_CTRL_13: 588 case RT5682_HP_IMP_SENS_CTRL_14: 589 case RT5682_HP_IMP_SENS_CTRL_15: 590 case RT5682_HP_IMP_SENS_CTRL_16: 591 case RT5682_HP_IMP_SENS_CTRL_17: 592 case RT5682_HP_IMP_SENS_CTRL_18: 593 case RT5682_HP_IMP_SENS_CTRL_19: 594 case RT5682_HP_IMP_SENS_CTRL_20: 595 case RT5682_HP_IMP_SENS_CTRL_21: 596 case RT5682_HP_IMP_SENS_CTRL_22: 597 case RT5682_HP_IMP_SENS_CTRL_23: 598 case RT5682_HP_IMP_SENS_CTRL_24: 599 case RT5682_HP_IMP_SENS_CTRL_25: 600 case RT5682_HP_IMP_SENS_CTRL_26: 601 case RT5682_HP_IMP_SENS_CTRL_27: 602 case RT5682_HP_IMP_SENS_CTRL_28: 603 case RT5682_HP_IMP_SENS_CTRL_29: 604 case RT5682_HP_IMP_SENS_CTRL_30: 605 case RT5682_HP_IMP_SENS_CTRL_31: 606 case RT5682_HP_IMP_SENS_CTRL_32: 607 case RT5682_HP_IMP_SENS_CTRL_33: 608 case RT5682_HP_IMP_SENS_CTRL_34: 609 case RT5682_HP_IMP_SENS_CTRL_35: 610 case RT5682_HP_IMP_SENS_CTRL_36: 611 case RT5682_HP_IMP_SENS_CTRL_37: 612 case RT5682_HP_IMP_SENS_CTRL_38: 613 case RT5682_HP_IMP_SENS_CTRL_39: 614 case RT5682_HP_IMP_SENS_CTRL_40: 615 case RT5682_HP_IMP_SENS_CTRL_41: 616 case RT5682_HP_IMP_SENS_CTRL_42: 617 case RT5682_HP_IMP_SENS_CTRL_43: 618 case RT5682_HP_LOGIC_CTRL_1: 619 case RT5682_HP_LOGIC_CTRL_2: 620 case RT5682_HP_LOGIC_CTRL_3: 621 case RT5682_HP_CALIB_CTRL_1: 622 case RT5682_HP_CALIB_CTRL_2: 623 case RT5682_HP_CALIB_CTRL_3: 624 case RT5682_HP_CALIB_CTRL_4: 625 case RT5682_HP_CALIB_CTRL_5: 626 case RT5682_HP_CALIB_CTRL_6: 627 case RT5682_HP_CALIB_CTRL_7: 628 case RT5682_HP_CALIB_CTRL_9: 629 case RT5682_HP_CALIB_CTRL_10: 630 case RT5682_HP_CALIB_CTRL_11: 631 case RT5682_HP_CALIB_STA_1: 632 case RT5682_HP_CALIB_STA_2: 633 case RT5682_HP_CALIB_STA_3: 634 case RT5682_HP_CALIB_STA_4: 635 case RT5682_HP_CALIB_STA_5: 636 case RT5682_HP_CALIB_STA_6: 637 case RT5682_HP_CALIB_STA_7: 638 case RT5682_HP_CALIB_STA_8: 639 case RT5682_HP_CALIB_STA_9: 640 case RT5682_HP_CALIB_STA_10: 641 case RT5682_HP_CALIB_STA_11: 642 case RT5682_SAR_IL_CMD_1: 643 case RT5682_SAR_IL_CMD_2: 644 case RT5682_SAR_IL_CMD_3: 645 case RT5682_SAR_IL_CMD_4: 646 case RT5682_SAR_IL_CMD_5: 647 case RT5682_SAR_IL_CMD_6: 648 case RT5682_SAR_IL_CMD_7: 649 case RT5682_SAR_IL_CMD_8: 650 case RT5682_SAR_IL_CMD_9: 651 case RT5682_SAR_IL_CMD_10: 652 case RT5682_SAR_IL_CMD_11: 653 case RT5682_SAR_IL_CMD_12: 654 case RT5682_SAR_IL_CMD_13: 655 case RT5682_EFUSE_CTRL_1: 656 case RT5682_EFUSE_CTRL_2: 657 case RT5682_EFUSE_CTRL_3: 658 case RT5682_EFUSE_CTRL_4: 659 case RT5682_EFUSE_CTRL_5: 660 case RT5682_EFUSE_CTRL_6: 661 case RT5682_EFUSE_CTRL_7: 662 case RT5682_EFUSE_CTRL_8: 663 case RT5682_EFUSE_CTRL_9: 664 case RT5682_EFUSE_CTRL_10: 665 case RT5682_EFUSE_CTRL_11: 666 case RT5682_JD_TOP_VC_VTRL: 667 case RT5682_DRC1_CTRL_0: 668 case RT5682_DRC1_CTRL_1: 669 case RT5682_DRC1_CTRL_2: 670 case RT5682_DRC1_CTRL_3: 671 case RT5682_DRC1_CTRL_4: 672 case RT5682_DRC1_CTRL_5: 673 case RT5682_DRC1_CTRL_6: 674 case RT5682_DRC1_HARD_LMT_CTRL_1: 675 case RT5682_DRC1_HARD_LMT_CTRL_2: 676 case RT5682_DRC1_PRIV_1: 677 case RT5682_DRC1_PRIV_2: 678 case RT5682_DRC1_PRIV_3: 679 case RT5682_DRC1_PRIV_4: 680 case RT5682_DRC1_PRIV_5: 681 case RT5682_DRC1_PRIV_6: 682 case RT5682_DRC1_PRIV_7: 683 case RT5682_DRC1_PRIV_8: 684 case RT5682_EQ_AUTO_RCV_CTRL1: 685 case RT5682_EQ_AUTO_RCV_CTRL2: 686 case RT5682_EQ_AUTO_RCV_CTRL3: 687 case RT5682_EQ_AUTO_RCV_CTRL4: 688 case RT5682_EQ_AUTO_RCV_CTRL5: 689 case RT5682_EQ_AUTO_RCV_CTRL6: 690 case RT5682_EQ_AUTO_RCV_CTRL7: 691 case RT5682_EQ_AUTO_RCV_CTRL8: 692 case RT5682_EQ_AUTO_RCV_CTRL9: 693 case RT5682_EQ_AUTO_RCV_CTRL10: 694 case RT5682_EQ_AUTO_RCV_CTRL11: 695 case RT5682_EQ_AUTO_RCV_CTRL12: 696 case RT5682_EQ_AUTO_RCV_CTRL13: 697 case RT5682_ADC_L_EQ_LPF1_A1: 698 case RT5682_R_EQ_LPF1_A1: 699 case RT5682_L_EQ_LPF1_H0: 700 case RT5682_R_EQ_LPF1_H0: 701 case RT5682_L_EQ_BPF1_A1: 702 case RT5682_R_EQ_BPF1_A1: 703 case RT5682_L_EQ_BPF1_A2: 704 case RT5682_R_EQ_BPF1_A2: 705 case RT5682_L_EQ_BPF1_H0: 706 case RT5682_R_EQ_BPF1_H0: 707 case RT5682_L_EQ_BPF2_A1: 708 case RT5682_R_EQ_BPF2_A1: 709 case RT5682_L_EQ_BPF2_A2: 710 case RT5682_R_EQ_BPF2_A2: 711 case RT5682_L_EQ_BPF2_H0: 712 case RT5682_R_EQ_BPF2_H0: 713 case RT5682_L_EQ_BPF3_A1: 714 case RT5682_R_EQ_BPF3_A1: 715 case RT5682_L_EQ_BPF3_A2: 716 case RT5682_R_EQ_BPF3_A2: 717 case RT5682_L_EQ_BPF3_H0: 718 case RT5682_R_EQ_BPF3_H0: 719 case RT5682_L_EQ_BPF4_A1: 720 case RT5682_R_EQ_BPF4_A1: 721 case RT5682_L_EQ_BPF4_A2: 722 case RT5682_R_EQ_BPF4_A2: 723 case RT5682_L_EQ_BPF4_H0: 724 case RT5682_R_EQ_BPF4_H0: 725 case RT5682_L_EQ_HPF1_A1: 726 case RT5682_R_EQ_HPF1_A1: 727 case RT5682_L_EQ_HPF1_H0: 728 case RT5682_R_EQ_HPF1_H0: 729 case RT5682_L_EQ_PRE_VOL: 730 case RT5682_R_EQ_PRE_VOL: 731 case RT5682_L_EQ_POST_VOL: 732 case RT5682_R_EQ_POST_VOL: 733 case RT5682_I2C_MODE: 734 return true; 735 default: 736 return false; 737 } 738 } 739 EXPORT_SYMBOL_GPL(rt5682_readable_register); 740 741 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6525, 75, 0); 742 static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0); 743 static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0); 744 745 /* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */ 746 static const DECLARE_TLV_DB_RANGE(bst_tlv, 747 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0), 748 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0), 749 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0), 750 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0), 751 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0), 752 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0), 753 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0) 754 ); 755 756 /* Interface data select */ 757 static const char * const rt5682_data_select[] = { 758 "L/R", "R/L", "L/L", "R/R" 759 }; 760 761 static SOC_ENUM_SINGLE_DECL(rt5682_if2_adc_enum, 762 RT5682_DIG_INF2_DATA, RT5682_IF2_ADC_SEL_SFT, rt5682_data_select); 763 764 static SOC_ENUM_SINGLE_DECL(rt5682_if1_01_adc_enum, 765 RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC1_SEL_SFT, rt5682_data_select); 766 767 static SOC_ENUM_SINGLE_DECL(rt5682_if1_23_adc_enum, 768 RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC2_SEL_SFT, rt5682_data_select); 769 770 static SOC_ENUM_SINGLE_DECL(rt5682_if1_45_adc_enum, 771 RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC3_SEL_SFT, rt5682_data_select); 772 773 static SOC_ENUM_SINGLE_DECL(rt5682_if1_67_adc_enum, 774 RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC4_SEL_SFT, rt5682_data_select); 775 776 static const struct snd_kcontrol_new rt5682_if2_adc_swap_mux = 777 SOC_DAPM_ENUM("IF2 ADC Swap Mux", rt5682_if2_adc_enum); 778 779 static const struct snd_kcontrol_new rt5682_if1_01_adc_swap_mux = 780 SOC_DAPM_ENUM("IF1 01 ADC Swap Mux", rt5682_if1_01_adc_enum); 781 782 static const struct snd_kcontrol_new rt5682_if1_23_adc_swap_mux = 783 SOC_DAPM_ENUM("IF1 23 ADC Swap Mux", rt5682_if1_23_adc_enum); 784 785 static const struct snd_kcontrol_new rt5682_if1_45_adc_swap_mux = 786 SOC_DAPM_ENUM("IF1 45 ADC Swap Mux", rt5682_if1_45_adc_enum); 787 788 static const struct snd_kcontrol_new rt5682_if1_67_adc_swap_mux = 789 SOC_DAPM_ENUM("IF1 67 ADC Swap Mux", rt5682_if1_67_adc_enum); 790 791 static const char * const rt5682_dac_select[] = { 792 "IF1", "SOUND" 793 }; 794 795 static SOC_ENUM_SINGLE_DECL(rt5682_dacl_enum, 796 RT5682_AD_DA_MIXER, RT5682_DAC1_L_SEL_SFT, rt5682_dac_select); 797 798 static const struct snd_kcontrol_new rt5682_dac_l_mux = 799 SOC_DAPM_ENUM("DAC L Mux", rt5682_dacl_enum); 800 801 static SOC_ENUM_SINGLE_DECL(rt5682_dacr_enum, 802 RT5682_AD_DA_MIXER, RT5682_DAC1_R_SEL_SFT, rt5682_dac_select); 803 804 static const struct snd_kcontrol_new rt5682_dac_r_mux = 805 SOC_DAPM_ENUM("DAC R Mux", rt5682_dacr_enum); 806 807 void rt5682_reset(struct rt5682_priv *rt5682) 808 { 809 regmap_write(rt5682->regmap, RT5682_RESET, 0); 810 if (!rt5682->is_sdw) 811 regmap_write(rt5682->regmap, RT5682_I2C_MODE, 1); 812 } 813 EXPORT_SYMBOL_GPL(rt5682_reset); 814 815 /** 816 * rt5682_sel_asrc_clk_src - select ASRC clock source for a set of filters 817 * @component: SoC audio component device. 818 * @filter_mask: mask of filters. 819 * @clk_src: clock source 820 * 821 * The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5682 can 822 * only support standard 32fs or 64fs i2s format, ASRC should be enabled to 823 * support special i2s clock format such as Intel's 100fs(100 * sampling rate). 824 * ASRC function will track i2s clock and generate a corresponding system clock 825 * for codec. This function provides an API to select the clock source for a 826 * set of filters specified by the mask. And the component driver will turn on 827 * ASRC for these filters if ASRC is selected as their clock source. 828 */ 829 int rt5682_sel_asrc_clk_src(struct snd_soc_component *component, 830 unsigned int filter_mask, unsigned int clk_src) 831 { 832 switch (clk_src) { 833 case RT5682_CLK_SEL_SYS: 834 case RT5682_CLK_SEL_I2S1_ASRC: 835 case RT5682_CLK_SEL_I2S2_ASRC: 836 break; 837 838 default: 839 return -EINVAL; 840 } 841 842 if (filter_mask & RT5682_DA_STEREO1_FILTER) { 843 snd_soc_component_update_bits(component, RT5682_PLL_TRACK_2, 844 RT5682_FILTER_CLK_SEL_MASK, 845 clk_src << RT5682_FILTER_CLK_SEL_SFT); 846 } 847 848 if (filter_mask & RT5682_AD_STEREO1_FILTER) { 849 snd_soc_component_update_bits(component, RT5682_PLL_TRACK_3, 850 RT5682_FILTER_CLK_SEL_MASK, 851 clk_src << RT5682_FILTER_CLK_SEL_SFT); 852 } 853 854 return 0; 855 } 856 EXPORT_SYMBOL_GPL(rt5682_sel_asrc_clk_src); 857 858 static int rt5682_button_detect(struct snd_soc_component *component) 859 { 860 int btn_type, val; 861 862 val = snd_soc_component_read32(component, RT5682_4BTN_IL_CMD_1); 863 btn_type = val & 0xfff0; 864 snd_soc_component_write(component, RT5682_4BTN_IL_CMD_1, val); 865 dev_dbg(component->dev, "%s btn_type=%x\n", __func__, btn_type); 866 snd_soc_component_update_bits(component, 867 RT5682_SAR_IL_CMD_2, 0x10, 0x10); 868 869 return btn_type; 870 } 871 872 static void rt5682_enable_push_button_irq(struct snd_soc_component *component, 873 bool enable) 874 { 875 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 876 877 if (enable) { 878 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1, 879 RT5682_SAR_BUTT_DET_MASK, RT5682_SAR_BUTT_DET_EN); 880 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_13, 881 RT5682_SAR_SOUR_MASK, RT5682_SAR_SOUR_BTN); 882 snd_soc_component_write(component, RT5682_IL_CMD_1, 0x0040); 883 snd_soc_component_update_bits(component, RT5682_4BTN_IL_CMD_2, 884 RT5682_4BTN_IL_MASK | RT5682_4BTN_IL_RST_MASK, 885 RT5682_4BTN_IL_EN | RT5682_4BTN_IL_NOR); 886 if (rt5682->is_sdw) 887 snd_soc_component_update_bits(component, 888 RT5682_IRQ_CTRL_3, 889 RT5682_IL_IRQ_MASK | RT5682_IL_IRQ_TYPE_MASK, 890 RT5682_IL_IRQ_EN | RT5682_IL_IRQ_PUL); 891 else 892 snd_soc_component_update_bits(component, 893 RT5682_IRQ_CTRL_3, RT5682_IL_IRQ_MASK, 894 RT5682_IL_IRQ_EN); 895 } else { 896 snd_soc_component_update_bits(component, RT5682_IRQ_CTRL_3, 897 RT5682_IL_IRQ_MASK, RT5682_IL_IRQ_DIS); 898 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1, 899 RT5682_SAR_BUTT_DET_MASK, RT5682_SAR_BUTT_DET_DIS); 900 snd_soc_component_update_bits(component, RT5682_4BTN_IL_CMD_2, 901 RT5682_4BTN_IL_MASK, RT5682_4BTN_IL_DIS); 902 snd_soc_component_update_bits(component, RT5682_4BTN_IL_CMD_2, 903 RT5682_4BTN_IL_RST_MASK, RT5682_4BTN_IL_RST); 904 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_13, 905 RT5682_SAR_SOUR_MASK, RT5682_SAR_SOUR_TYPE); 906 } 907 } 908 909 /** 910 * rt5682_headset_detect - Detect headset. 911 * @component: SoC audio component device. 912 * @jack_insert: Jack insert or not. 913 * 914 * Detect whether is headset or not when jack inserted. 915 * 916 * Returns detect status. 917 */ 918 int rt5682_headset_detect(struct snd_soc_component *component, int jack_insert) 919 { 920 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 921 struct snd_soc_dapm_context *dapm = &component->dapm; 922 unsigned int val, count; 923 924 if (jack_insert) { 925 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_1, 926 RT5682_PWR_VREF2 | RT5682_PWR_MB, 927 RT5682_PWR_VREF2 | RT5682_PWR_MB); 928 snd_soc_component_update_bits(component, 929 RT5682_PWR_ANLG_1, RT5682_PWR_FV2, 0); 930 usleep_range(15000, 20000); 931 snd_soc_component_update_bits(component, 932 RT5682_PWR_ANLG_1, RT5682_PWR_FV2, RT5682_PWR_FV2); 933 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_3, 934 RT5682_PWR_CBJ, RT5682_PWR_CBJ); 935 936 snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1, 937 RT5682_TRIG_JD_MASK, RT5682_TRIG_JD_HIGH); 938 939 count = 0; 940 val = snd_soc_component_read32(component, RT5682_CBJ_CTRL_2) 941 & RT5682_JACK_TYPE_MASK; 942 while (val == 0 && count < 50) { 943 usleep_range(10000, 15000); 944 val = snd_soc_component_read32(component, 945 RT5682_CBJ_CTRL_2) & RT5682_JACK_TYPE_MASK; 946 count++; 947 } 948 949 switch (val) { 950 case 0x1: 951 case 0x2: 952 rt5682->jack_type = SND_JACK_HEADSET; 953 rt5682_enable_push_button_irq(component, true); 954 break; 955 default: 956 rt5682->jack_type = SND_JACK_HEADPHONE; 957 break; 958 } 959 } else { 960 rt5682_enable_push_button_irq(component, false); 961 snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1, 962 RT5682_TRIG_JD_MASK, RT5682_TRIG_JD_LOW); 963 if (snd_soc_dapm_get_pin_status(dapm, "MICBIAS")) 964 snd_soc_component_update_bits(component, 965 RT5682_PWR_ANLG_1, RT5682_PWR_VREF2, 0); 966 else 967 snd_soc_component_update_bits(component, 968 RT5682_PWR_ANLG_1, 969 RT5682_PWR_VREF2 | RT5682_PWR_MB, 0); 970 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_3, 971 RT5682_PWR_CBJ, 0); 972 973 rt5682->jack_type = 0; 974 } 975 976 dev_dbg(component->dev, "jack_type = %d\n", rt5682->jack_type); 977 return rt5682->jack_type; 978 } 979 EXPORT_SYMBOL_GPL(rt5682_headset_detect); 980 981 static int rt5682_set_jack_detect(struct snd_soc_component *component, 982 struct snd_soc_jack *hs_jack, void *data) 983 { 984 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 985 986 rt5682->hs_jack = hs_jack; 987 988 if (!rt5682->is_sdw) { 989 if (!hs_jack) { 990 regmap_update_bits(rt5682->regmap, RT5682_IRQ_CTRL_2, 991 RT5682_JD1_EN_MASK, RT5682_JD1_DIS); 992 regmap_update_bits(rt5682->regmap, RT5682_RC_CLK_CTRL, 993 RT5682_POW_JDH | RT5682_POW_JDL, 0); 994 cancel_delayed_work_sync(&rt5682->jack_detect_work); 995 return 0; 996 } 997 998 switch (rt5682->pdata.jd_src) { 999 case RT5682_JD1: 1000 snd_soc_component_update_bits(component, 1001 RT5682_CBJ_CTRL_2, RT5682_EXT_JD_SRC, 1002 RT5682_EXT_JD_SRC_MANUAL); 1003 snd_soc_component_write(component, RT5682_CBJ_CTRL_1, 1004 0xd042); 1005 snd_soc_component_update_bits(component, 1006 RT5682_CBJ_CTRL_3, RT5682_CBJ_IN_BUF_EN, 1007 RT5682_CBJ_IN_BUF_EN); 1008 snd_soc_component_update_bits(component, 1009 RT5682_SAR_IL_CMD_1, RT5682_SAR_POW_MASK, 1010 RT5682_SAR_POW_EN); 1011 regmap_update_bits(rt5682->regmap, RT5682_GPIO_CTRL_1, 1012 RT5682_GP1_PIN_MASK, RT5682_GP1_PIN_IRQ); 1013 regmap_update_bits(rt5682->regmap, RT5682_RC_CLK_CTRL, 1014 RT5682_POW_IRQ | RT5682_POW_JDH | 1015 RT5682_POW_ANA, RT5682_POW_IRQ | 1016 RT5682_POW_JDH | RT5682_POW_ANA); 1017 regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_2, 1018 RT5682_PWR_JDH | RT5682_PWR_JDL, 1019 RT5682_PWR_JDH | RT5682_PWR_JDL); 1020 regmap_update_bits(rt5682->regmap, RT5682_IRQ_CTRL_2, 1021 RT5682_JD1_EN_MASK | RT5682_JD1_POL_MASK, 1022 RT5682_JD1_EN | RT5682_JD1_POL_NOR); 1023 regmap_update_bits(rt5682->regmap, RT5682_4BTN_IL_CMD_4, 1024 0x7f7f, (rt5682->pdata.btndet_delay << 8 | 1025 rt5682->pdata.btndet_delay)); 1026 regmap_update_bits(rt5682->regmap, RT5682_4BTN_IL_CMD_5, 1027 0x7f7f, (rt5682->pdata.btndet_delay << 8 | 1028 rt5682->pdata.btndet_delay)); 1029 regmap_update_bits(rt5682->regmap, RT5682_4BTN_IL_CMD_6, 1030 0x7f7f, (rt5682->pdata.btndet_delay << 8 | 1031 rt5682->pdata.btndet_delay)); 1032 regmap_update_bits(rt5682->regmap, RT5682_4BTN_IL_CMD_7, 1033 0x7f7f, (rt5682->pdata.btndet_delay << 8 | 1034 rt5682->pdata.btndet_delay)); 1035 mod_delayed_work(system_power_efficient_wq, 1036 &rt5682->jack_detect_work, 1037 msecs_to_jiffies(250)); 1038 break; 1039 1040 case RT5682_JD_NULL: 1041 regmap_update_bits(rt5682->regmap, RT5682_IRQ_CTRL_2, 1042 RT5682_JD1_EN_MASK, RT5682_JD1_DIS); 1043 regmap_update_bits(rt5682->regmap, RT5682_RC_CLK_CTRL, 1044 RT5682_POW_JDH | RT5682_POW_JDL, 0); 1045 break; 1046 1047 default: 1048 dev_warn(component->dev, "Wrong JD source\n"); 1049 break; 1050 } 1051 } 1052 1053 return 0; 1054 } 1055 1056 void rt5682_jack_detect_handler(struct work_struct *work) 1057 { 1058 struct rt5682_priv *rt5682 = 1059 container_of(work, struct rt5682_priv, jack_detect_work.work); 1060 int val, btn_type; 1061 1062 while (!rt5682->component) 1063 usleep_range(10000, 15000); 1064 1065 while (!rt5682->component->card->instantiated) 1066 usleep_range(10000, 15000); 1067 1068 mutex_lock(&rt5682->calibrate_mutex); 1069 1070 val = snd_soc_component_read32(rt5682->component, RT5682_AJD1_CTRL) 1071 & RT5682_JDH_RS_MASK; 1072 if (!val) { 1073 /* jack in */ 1074 if (rt5682->jack_type == 0) { 1075 /* jack was out, report jack type */ 1076 rt5682->jack_type = 1077 rt5682_headset_detect(rt5682->component, 1); 1078 } else { 1079 /* jack is already in, report button event */ 1080 rt5682->jack_type = SND_JACK_HEADSET; 1081 btn_type = rt5682_button_detect(rt5682->component); 1082 /** 1083 * rt5682 can report three kinds of button behavior, 1084 * one click, double click and hold. However, 1085 * currently we will report button pressed/released 1086 * event. So all the three button behaviors are 1087 * treated as button pressed. 1088 */ 1089 switch (btn_type) { 1090 case 0x8000: 1091 case 0x4000: 1092 case 0x2000: 1093 rt5682->jack_type |= SND_JACK_BTN_0; 1094 break; 1095 case 0x1000: 1096 case 0x0800: 1097 case 0x0400: 1098 rt5682->jack_type |= SND_JACK_BTN_1; 1099 break; 1100 case 0x0200: 1101 case 0x0100: 1102 case 0x0080: 1103 rt5682->jack_type |= SND_JACK_BTN_2; 1104 break; 1105 case 0x0040: 1106 case 0x0020: 1107 case 0x0010: 1108 rt5682->jack_type |= SND_JACK_BTN_3; 1109 break; 1110 case 0x0000: /* unpressed */ 1111 break; 1112 default: 1113 dev_err(rt5682->component->dev, 1114 "Unexpected button code 0x%04x\n", 1115 btn_type); 1116 break; 1117 } 1118 } 1119 } else { 1120 /* jack out */ 1121 rt5682->jack_type = rt5682_headset_detect(rt5682->component, 0); 1122 } 1123 1124 snd_soc_jack_report(rt5682->hs_jack, rt5682->jack_type, 1125 SND_JACK_HEADSET | 1126 SND_JACK_BTN_0 | SND_JACK_BTN_1 | 1127 SND_JACK_BTN_2 | SND_JACK_BTN_3); 1128 1129 if (!rt5682->is_sdw) { 1130 if (rt5682->jack_type & (SND_JACK_BTN_0 | SND_JACK_BTN_1 | 1131 SND_JACK_BTN_2 | SND_JACK_BTN_3)) 1132 schedule_delayed_work(&rt5682->jd_check_work, 0); 1133 else 1134 cancel_delayed_work_sync(&rt5682->jd_check_work); 1135 } 1136 1137 mutex_unlock(&rt5682->calibrate_mutex); 1138 } 1139 EXPORT_SYMBOL_GPL(rt5682_jack_detect_handler); 1140 1141 static const struct snd_kcontrol_new rt5682_snd_controls[] = { 1142 /* DAC Digital Volume */ 1143 SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5682_DAC1_DIG_VOL, 1144 RT5682_L_VOL_SFT + 1, RT5682_R_VOL_SFT + 1, 87, 0, dac_vol_tlv), 1145 1146 /* IN Boost Volume */ 1147 SOC_SINGLE_TLV("CBJ Boost Volume", RT5682_CBJ_BST_CTRL, 1148 RT5682_BST_CBJ_SFT, 8, 0, bst_tlv), 1149 1150 /* ADC Digital Volume Control */ 1151 SOC_DOUBLE("STO1 ADC Capture Switch", RT5682_STO1_ADC_DIG_VOL, 1152 RT5682_L_MUTE_SFT, RT5682_R_MUTE_SFT, 1, 1), 1153 SOC_DOUBLE_TLV("STO1 ADC Capture Volume", RT5682_STO1_ADC_DIG_VOL, 1154 RT5682_L_VOL_SFT + 1, RT5682_R_VOL_SFT + 1, 63, 0, adc_vol_tlv), 1155 1156 /* ADC Boost Volume Control */ 1157 SOC_DOUBLE_TLV("STO1 ADC Boost Gain Volume", RT5682_STO1_ADC_BOOST, 1158 RT5682_STO1_ADC_L_BST_SFT, RT5682_STO1_ADC_R_BST_SFT, 1159 3, 0, adc_bst_tlv), 1160 }; 1161 1162 static int rt5682_div_sel(struct rt5682_priv *rt5682, 1163 int target, const int div[], int size) 1164 { 1165 int i; 1166 1167 if (rt5682->sysclk < target) { 1168 dev_err(rt5682->component->dev, 1169 "sysclk rate %d is too low\n", rt5682->sysclk); 1170 return 0; 1171 } 1172 1173 for (i = 0; i < size - 1; i++) { 1174 dev_dbg(rt5682->component->dev, "div[%d]=%d\n", i, div[i]); 1175 if (target * div[i] == rt5682->sysclk) 1176 return i; 1177 if (target * div[i + 1] > rt5682->sysclk) { 1178 dev_dbg(rt5682->component->dev, 1179 "can't find div for sysclk %d\n", 1180 rt5682->sysclk); 1181 return i; 1182 } 1183 } 1184 1185 if (target * div[i] < rt5682->sysclk) 1186 dev_err(rt5682->component->dev, 1187 "sysclk rate %d is too high\n", rt5682->sysclk); 1188 1189 return size - 1; 1190 } 1191 1192 /** 1193 * set_dmic_clk - Set parameter of dmic. 1194 * 1195 * @w: DAPM widget. 1196 * @kcontrol: The kcontrol of this widget. 1197 * @event: Event id. 1198 * 1199 * Choose dmic clock between 1MHz and 3MHz. 1200 * It is better for clock to approximate 3MHz. 1201 */ 1202 static int set_dmic_clk(struct snd_soc_dapm_widget *w, 1203 struct snd_kcontrol *kcontrol, int event) 1204 { 1205 struct snd_soc_component *component = 1206 snd_soc_dapm_to_component(w->dapm); 1207 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 1208 int idx = -EINVAL, dmic_clk_rate = 3072000; 1209 static const int div[] = {2, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, 128}; 1210 1211 if (rt5682->pdata.dmic_clk_rate) 1212 dmic_clk_rate = rt5682->pdata.dmic_clk_rate; 1213 1214 idx = rt5682_div_sel(rt5682, dmic_clk_rate, div, ARRAY_SIZE(div)); 1215 1216 snd_soc_component_update_bits(component, RT5682_DMIC_CTRL_1, 1217 RT5682_DMIC_CLK_MASK, idx << RT5682_DMIC_CLK_SFT); 1218 1219 return 0; 1220 } 1221 1222 static int set_filter_clk(struct snd_soc_dapm_widget *w, 1223 struct snd_kcontrol *kcontrol, int event) 1224 { 1225 struct snd_soc_component *component = 1226 snd_soc_dapm_to_component(w->dapm); 1227 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 1228 int ref, val, reg, idx = -EINVAL; 1229 static const int div_f[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32, 48}; 1230 static const int div_o[] = {1, 2, 4, 6, 8, 12, 16, 24, 32, 48}; 1231 1232 if (rt5682->is_sdw) 1233 return 0; 1234 1235 val = snd_soc_component_read32(component, RT5682_GPIO_CTRL_1) & 1236 RT5682_GP4_PIN_MASK; 1237 if (w->shift == RT5682_PWR_ADC_S1F_BIT && 1238 val == RT5682_GP4_PIN_ADCDAT2) 1239 ref = 256 * rt5682->lrck[RT5682_AIF2]; 1240 else 1241 ref = 256 * rt5682->lrck[RT5682_AIF1]; 1242 1243 idx = rt5682_div_sel(rt5682, ref, div_f, ARRAY_SIZE(div_f)); 1244 1245 if (w->shift == RT5682_PWR_ADC_S1F_BIT) 1246 reg = RT5682_PLL_TRACK_3; 1247 else 1248 reg = RT5682_PLL_TRACK_2; 1249 1250 snd_soc_component_update_bits(component, reg, 1251 RT5682_FILTER_CLK_DIV_MASK, idx << RT5682_FILTER_CLK_DIV_SFT); 1252 1253 /* select over sample rate */ 1254 for (idx = 0; idx < ARRAY_SIZE(div_o); idx++) { 1255 if (rt5682->sysclk <= 12288000 * div_o[idx]) 1256 break; 1257 } 1258 1259 snd_soc_component_update_bits(component, RT5682_ADDA_CLK_1, 1260 RT5682_ADC_OSR_MASK | RT5682_DAC_OSR_MASK, 1261 (idx << RT5682_ADC_OSR_SFT) | (idx << RT5682_DAC_OSR_SFT)); 1262 1263 return 0; 1264 } 1265 1266 static int is_sys_clk_from_pll1(struct snd_soc_dapm_widget *w, 1267 struct snd_soc_dapm_widget *sink) 1268 { 1269 unsigned int val; 1270 struct snd_soc_component *component = 1271 snd_soc_dapm_to_component(w->dapm); 1272 1273 val = snd_soc_component_read32(component, RT5682_GLB_CLK); 1274 val &= RT5682_SCLK_SRC_MASK; 1275 if (val == RT5682_SCLK_SRC_PLL1) 1276 return 1; 1277 else 1278 return 0; 1279 } 1280 1281 static int is_sys_clk_from_pll2(struct snd_soc_dapm_widget *w, 1282 struct snd_soc_dapm_widget *sink) 1283 { 1284 unsigned int val; 1285 struct snd_soc_component *component = 1286 snd_soc_dapm_to_component(w->dapm); 1287 1288 val = snd_soc_component_read32(component, RT5682_GLB_CLK); 1289 val &= RT5682_SCLK_SRC_MASK; 1290 if (val == RT5682_SCLK_SRC_PLL2) 1291 return 1; 1292 else 1293 return 0; 1294 } 1295 1296 static int is_using_asrc(struct snd_soc_dapm_widget *w, 1297 struct snd_soc_dapm_widget *sink) 1298 { 1299 unsigned int reg, shift, val; 1300 struct snd_soc_component *component = 1301 snd_soc_dapm_to_component(w->dapm); 1302 1303 switch (w->shift) { 1304 case RT5682_ADC_STO1_ASRC_SFT: 1305 reg = RT5682_PLL_TRACK_3; 1306 shift = RT5682_FILTER_CLK_SEL_SFT; 1307 break; 1308 case RT5682_DAC_STO1_ASRC_SFT: 1309 reg = RT5682_PLL_TRACK_2; 1310 shift = RT5682_FILTER_CLK_SEL_SFT; 1311 break; 1312 default: 1313 return 0; 1314 } 1315 1316 val = (snd_soc_component_read32(component, reg) >> shift) & 0xf; 1317 switch (val) { 1318 case RT5682_CLK_SEL_I2S1_ASRC: 1319 case RT5682_CLK_SEL_I2S2_ASRC: 1320 return 1; 1321 default: 1322 return 0; 1323 } 1324 } 1325 1326 /* Digital Mixer */ 1327 static const struct snd_kcontrol_new rt5682_sto1_adc_l_mix[] = { 1328 SOC_DAPM_SINGLE("ADC1 Switch", RT5682_STO1_ADC_MIXER, 1329 RT5682_M_STO1_ADC_L1_SFT, 1, 1), 1330 SOC_DAPM_SINGLE("ADC2 Switch", RT5682_STO1_ADC_MIXER, 1331 RT5682_M_STO1_ADC_L2_SFT, 1, 1), 1332 }; 1333 1334 static const struct snd_kcontrol_new rt5682_sto1_adc_r_mix[] = { 1335 SOC_DAPM_SINGLE("ADC1 Switch", RT5682_STO1_ADC_MIXER, 1336 RT5682_M_STO1_ADC_R1_SFT, 1, 1), 1337 SOC_DAPM_SINGLE("ADC2 Switch", RT5682_STO1_ADC_MIXER, 1338 RT5682_M_STO1_ADC_R2_SFT, 1, 1), 1339 }; 1340 1341 static const struct snd_kcontrol_new rt5682_dac_l_mix[] = { 1342 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5682_AD_DA_MIXER, 1343 RT5682_M_ADCMIX_L_SFT, 1, 1), 1344 SOC_DAPM_SINGLE("DAC1 Switch", RT5682_AD_DA_MIXER, 1345 RT5682_M_DAC1_L_SFT, 1, 1), 1346 }; 1347 1348 static const struct snd_kcontrol_new rt5682_dac_r_mix[] = { 1349 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5682_AD_DA_MIXER, 1350 RT5682_M_ADCMIX_R_SFT, 1, 1), 1351 SOC_DAPM_SINGLE("DAC1 Switch", RT5682_AD_DA_MIXER, 1352 RT5682_M_DAC1_R_SFT, 1, 1), 1353 }; 1354 1355 static const struct snd_kcontrol_new rt5682_sto1_dac_l_mix[] = { 1356 SOC_DAPM_SINGLE("DAC L1 Switch", RT5682_STO1_DAC_MIXER, 1357 RT5682_M_DAC_L1_STO_L_SFT, 1, 1), 1358 SOC_DAPM_SINGLE("DAC R1 Switch", RT5682_STO1_DAC_MIXER, 1359 RT5682_M_DAC_R1_STO_L_SFT, 1, 1), 1360 }; 1361 1362 static const struct snd_kcontrol_new rt5682_sto1_dac_r_mix[] = { 1363 SOC_DAPM_SINGLE("DAC L1 Switch", RT5682_STO1_DAC_MIXER, 1364 RT5682_M_DAC_L1_STO_R_SFT, 1, 1), 1365 SOC_DAPM_SINGLE("DAC R1 Switch", RT5682_STO1_DAC_MIXER, 1366 RT5682_M_DAC_R1_STO_R_SFT, 1, 1), 1367 }; 1368 1369 /* Analog Input Mixer */ 1370 static const struct snd_kcontrol_new rt5682_rec1_l_mix[] = { 1371 SOC_DAPM_SINGLE("CBJ Switch", RT5682_REC_MIXER, 1372 RT5682_M_CBJ_RM1_L_SFT, 1, 1), 1373 }; 1374 1375 /* STO1 ADC1 Source */ 1376 /* MX-26 [13] [5] */ 1377 static const char * const rt5682_sto1_adc1_src[] = { 1378 "DAC MIX", "ADC" 1379 }; 1380 1381 static SOC_ENUM_SINGLE_DECL( 1382 rt5682_sto1_adc1l_enum, RT5682_STO1_ADC_MIXER, 1383 RT5682_STO1_ADC1L_SRC_SFT, rt5682_sto1_adc1_src); 1384 1385 static const struct snd_kcontrol_new rt5682_sto1_adc1l_mux = 1386 SOC_DAPM_ENUM("Stereo1 ADC1L Source", rt5682_sto1_adc1l_enum); 1387 1388 static SOC_ENUM_SINGLE_DECL( 1389 rt5682_sto1_adc1r_enum, RT5682_STO1_ADC_MIXER, 1390 RT5682_STO1_ADC1R_SRC_SFT, rt5682_sto1_adc1_src); 1391 1392 static const struct snd_kcontrol_new rt5682_sto1_adc1r_mux = 1393 SOC_DAPM_ENUM("Stereo1 ADC1L Source", rt5682_sto1_adc1r_enum); 1394 1395 /* STO1 ADC Source */ 1396 /* MX-26 [11:10] [3:2] */ 1397 static const char * const rt5682_sto1_adc_src[] = { 1398 "ADC1 L", "ADC1 R" 1399 }; 1400 1401 static SOC_ENUM_SINGLE_DECL( 1402 rt5682_sto1_adcl_enum, RT5682_STO1_ADC_MIXER, 1403 RT5682_STO1_ADCL_SRC_SFT, rt5682_sto1_adc_src); 1404 1405 static const struct snd_kcontrol_new rt5682_sto1_adcl_mux = 1406 SOC_DAPM_ENUM("Stereo1 ADCL Source", rt5682_sto1_adcl_enum); 1407 1408 static SOC_ENUM_SINGLE_DECL( 1409 rt5682_sto1_adcr_enum, RT5682_STO1_ADC_MIXER, 1410 RT5682_STO1_ADCR_SRC_SFT, rt5682_sto1_adc_src); 1411 1412 static const struct snd_kcontrol_new rt5682_sto1_adcr_mux = 1413 SOC_DAPM_ENUM("Stereo1 ADCR Source", rt5682_sto1_adcr_enum); 1414 1415 /* STO1 ADC2 Source */ 1416 /* MX-26 [12] [4] */ 1417 static const char * const rt5682_sto1_adc2_src[] = { 1418 "DAC MIX", "DMIC" 1419 }; 1420 1421 static SOC_ENUM_SINGLE_DECL( 1422 rt5682_sto1_adc2l_enum, RT5682_STO1_ADC_MIXER, 1423 RT5682_STO1_ADC2L_SRC_SFT, rt5682_sto1_adc2_src); 1424 1425 static const struct snd_kcontrol_new rt5682_sto1_adc2l_mux = 1426 SOC_DAPM_ENUM("Stereo1 ADC2L Source", rt5682_sto1_adc2l_enum); 1427 1428 static SOC_ENUM_SINGLE_DECL( 1429 rt5682_sto1_adc2r_enum, RT5682_STO1_ADC_MIXER, 1430 RT5682_STO1_ADC2R_SRC_SFT, rt5682_sto1_adc2_src); 1431 1432 static const struct snd_kcontrol_new rt5682_sto1_adc2r_mux = 1433 SOC_DAPM_ENUM("Stereo1 ADC2R Source", rt5682_sto1_adc2r_enum); 1434 1435 /* MX-79 [6:4] I2S1 ADC data location */ 1436 static const unsigned int rt5682_if1_adc_slot_values[] = { 1437 0, 1438 2, 1439 4, 1440 6, 1441 }; 1442 1443 static const char * const rt5682_if1_adc_slot_src[] = { 1444 "Slot 0", "Slot 2", "Slot 4", "Slot 6" 1445 }; 1446 1447 static SOC_VALUE_ENUM_SINGLE_DECL(rt5682_if1_adc_slot_enum, 1448 RT5682_TDM_CTRL, RT5682_TDM_ADC_LCA_SFT, RT5682_TDM_ADC_LCA_MASK, 1449 rt5682_if1_adc_slot_src, rt5682_if1_adc_slot_values); 1450 1451 static const struct snd_kcontrol_new rt5682_if1_adc_slot_mux = 1452 SOC_DAPM_ENUM("IF1 ADC Slot location", rt5682_if1_adc_slot_enum); 1453 1454 /* Analog DAC L1 Source, Analog DAC R1 Source*/ 1455 /* MX-2B [4], MX-2B [0]*/ 1456 static const char * const rt5682_alg_dac1_src[] = { 1457 "Stereo1 DAC Mixer", "DAC1" 1458 }; 1459 1460 static SOC_ENUM_SINGLE_DECL( 1461 rt5682_alg_dac_l1_enum, RT5682_A_DAC1_MUX, 1462 RT5682_A_DACL1_SFT, rt5682_alg_dac1_src); 1463 1464 static const struct snd_kcontrol_new rt5682_alg_dac_l1_mux = 1465 SOC_DAPM_ENUM("Analog DAC L1 Source", rt5682_alg_dac_l1_enum); 1466 1467 static SOC_ENUM_SINGLE_DECL( 1468 rt5682_alg_dac_r1_enum, RT5682_A_DAC1_MUX, 1469 RT5682_A_DACR1_SFT, rt5682_alg_dac1_src); 1470 1471 static const struct snd_kcontrol_new rt5682_alg_dac_r1_mux = 1472 SOC_DAPM_ENUM("Analog DAC R1 Source", rt5682_alg_dac_r1_enum); 1473 1474 /* Out Switch */ 1475 static const struct snd_kcontrol_new hpol_switch = 1476 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5682_HP_CTRL_1, 1477 RT5682_L_MUTE_SFT, 1, 1); 1478 static const struct snd_kcontrol_new hpor_switch = 1479 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5682_HP_CTRL_1, 1480 RT5682_R_MUTE_SFT, 1, 1); 1481 1482 static int rt5682_hp_event(struct snd_soc_dapm_widget *w, 1483 struct snd_kcontrol *kcontrol, int event) 1484 { 1485 struct snd_soc_component *component = 1486 snd_soc_dapm_to_component(w->dapm); 1487 1488 switch (event) { 1489 case SND_SOC_DAPM_PRE_PMU: 1490 snd_soc_component_write(component, 1491 RT5682_HP_LOGIC_CTRL_2, 0x0012); 1492 snd_soc_component_write(component, 1493 RT5682_HP_CTRL_2, 0x6000); 1494 snd_soc_component_update_bits(component, 1495 RT5682_DEPOP_1, 0x60, 0x60); 1496 snd_soc_component_update_bits(component, 1497 RT5682_DAC_ADC_DIG_VOL1, 0x00c0, 0x0080); 1498 break; 1499 1500 case SND_SOC_DAPM_POST_PMD: 1501 snd_soc_component_update_bits(component, 1502 RT5682_DEPOP_1, 0x60, 0x0); 1503 snd_soc_component_write(component, 1504 RT5682_HP_CTRL_2, 0x0000); 1505 snd_soc_component_update_bits(component, 1506 RT5682_DAC_ADC_DIG_VOL1, 0x00c0, 0x0000); 1507 break; 1508 } 1509 1510 return 0; 1511 } 1512 1513 static int set_dmic_power(struct snd_soc_dapm_widget *w, 1514 struct snd_kcontrol *kcontrol, int event) 1515 { 1516 struct snd_soc_component *component = 1517 snd_soc_dapm_to_component(w->dapm); 1518 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 1519 unsigned int delay = 50; 1520 1521 if (rt5682->pdata.dmic_delay) 1522 delay = rt5682->pdata.dmic_delay; 1523 1524 switch (event) { 1525 case SND_SOC_DAPM_POST_PMU: 1526 /*Add delay to avoid pop noise*/ 1527 msleep(delay); 1528 break; 1529 } 1530 1531 return 0; 1532 } 1533 1534 static int rt5682_set_verf(struct snd_soc_dapm_widget *w, 1535 struct snd_kcontrol *kcontrol, int event) 1536 { 1537 struct snd_soc_component *component = 1538 snd_soc_dapm_to_component(w->dapm); 1539 1540 switch (event) { 1541 case SND_SOC_DAPM_PRE_PMU: 1542 switch (w->shift) { 1543 case RT5682_PWR_VREF1_BIT: 1544 snd_soc_component_update_bits(component, 1545 RT5682_PWR_ANLG_1, RT5682_PWR_FV1, 0); 1546 break; 1547 1548 case RT5682_PWR_VREF2_BIT: 1549 snd_soc_component_update_bits(component, 1550 RT5682_PWR_ANLG_1, RT5682_PWR_FV2, 0); 1551 break; 1552 } 1553 break; 1554 1555 case SND_SOC_DAPM_POST_PMU: 1556 usleep_range(15000, 20000); 1557 switch (w->shift) { 1558 case RT5682_PWR_VREF1_BIT: 1559 snd_soc_component_update_bits(component, 1560 RT5682_PWR_ANLG_1, RT5682_PWR_FV1, 1561 RT5682_PWR_FV1); 1562 break; 1563 1564 case RT5682_PWR_VREF2_BIT: 1565 snd_soc_component_update_bits(component, 1566 RT5682_PWR_ANLG_1, RT5682_PWR_FV2, 1567 RT5682_PWR_FV2); 1568 break; 1569 } 1570 break; 1571 } 1572 1573 return 0; 1574 } 1575 1576 static const unsigned int rt5682_adcdat_pin_values[] = { 1577 1, 1578 3, 1579 }; 1580 1581 static const char * const rt5682_adcdat_pin_select[] = { 1582 "ADCDAT1", 1583 "ADCDAT2", 1584 }; 1585 1586 static SOC_VALUE_ENUM_SINGLE_DECL(rt5682_adcdat_pin_enum, 1587 RT5682_GPIO_CTRL_1, RT5682_GP4_PIN_SFT, RT5682_GP4_PIN_MASK, 1588 rt5682_adcdat_pin_select, rt5682_adcdat_pin_values); 1589 1590 static const struct snd_kcontrol_new rt5682_adcdat_pin_ctrl = 1591 SOC_DAPM_ENUM("ADCDAT", rt5682_adcdat_pin_enum); 1592 1593 static const struct snd_soc_dapm_widget rt5682_dapm_widgets[] = { 1594 SND_SOC_DAPM_SUPPLY("LDO2", RT5682_PWR_ANLG_3, RT5682_PWR_LDO2_BIT, 1595 0, NULL, 0), 1596 SND_SOC_DAPM_SUPPLY("PLL1", RT5682_PWR_ANLG_3, RT5682_PWR_PLL_BIT, 1597 0, NULL, 0), 1598 SND_SOC_DAPM_SUPPLY("PLL2B", RT5682_PWR_ANLG_3, RT5682_PWR_PLL2B_BIT, 1599 0, NULL, 0), 1600 SND_SOC_DAPM_SUPPLY("PLL2F", RT5682_PWR_ANLG_3, RT5682_PWR_PLL2F_BIT, 1601 0, set_filter_clk, SND_SOC_DAPM_PRE_PMU), 1602 SND_SOC_DAPM_SUPPLY("Vref1", RT5682_PWR_ANLG_1, RT5682_PWR_VREF1_BIT, 0, 1603 rt5682_set_verf, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), 1604 SND_SOC_DAPM_SUPPLY("Vref2", RT5682_PWR_ANLG_1, RT5682_PWR_VREF2_BIT, 0, 1605 NULL, 0), 1606 SND_SOC_DAPM_SUPPLY("MICBIAS", SND_SOC_NOPM, 0, 0, NULL, 0), 1607 1608 /* ASRC */ 1609 SND_SOC_DAPM_SUPPLY_S("DAC STO1 ASRC", 1, RT5682_PLL_TRACK_1, 1610 RT5682_DAC_STO1_ASRC_SFT, 0, NULL, 0), 1611 SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5682_PLL_TRACK_1, 1612 RT5682_ADC_STO1_ASRC_SFT, 0, NULL, 0), 1613 SND_SOC_DAPM_SUPPLY_S("AD ASRC", 1, RT5682_PLL_TRACK_1, 1614 RT5682_AD_ASRC_SFT, 0, NULL, 0), 1615 SND_SOC_DAPM_SUPPLY_S("DA ASRC", 1, RT5682_PLL_TRACK_1, 1616 RT5682_DA_ASRC_SFT, 0, NULL, 0), 1617 SND_SOC_DAPM_SUPPLY_S("DMIC ASRC", 1, RT5682_PLL_TRACK_1, 1618 RT5682_DMIC_ASRC_SFT, 0, NULL, 0), 1619 1620 /* Input Side */ 1621 SND_SOC_DAPM_SUPPLY("MICBIAS1", RT5682_PWR_ANLG_2, RT5682_PWR_MB1_BIT, 1622 0, NULL, 0), 1623 SND_SOC_DAPM_SUPPLY("MICBIAS2", RT5682_PWR_ANLG_2, RT5682_PWR_MB2_BIT, 1624 0, NULL, 0), 1625 1626 /* Input Lines */ 1627 SND_SOC_DAPM_INPUT("DMIC L1"), 1628 SND_SOC_DAPM_INPUT("DMIC R1"), 1629 1630 SND_SOC_DAPM_INPUT("IN1P"), 1631 1632 SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0, 1633 set_dmic_clk, SND_SOC_DAPM_PRE_PMU), 1634 SND_SOC_DAPM_SUPPLY("DMIC1 Power", RT5682_DMIC_CTRL_1, 1635 RT5682_DMIC_1_EN_SFT, 0, set_dmic_power, SND_SOC_DAPM_POST_PMU), 1636 1637 /* Boost */ 1638 SND_SOC_DAPM_PGA("BST1 CBJ", SND_SOC_NOPM, 1639 0, 0, NULL, 0), 1640 1641 /* REC Mixer */ 1642 SND_SOC_DAPM_MIXER("RECMIX1L", SND_SOC_NOPM, 0, 0, rt5682_rec1_l_mix, 1643 ARRAY_SIZE(rt5682_rec1_l_mix)), 1644 SND_SOC_DAPM_SUPPLY("RECMIX1L Power", RT5682_PWR_ANLG_2, 1645 RT5682_PWR_RM1_L_BIT, 0, NULL, 0), 1646 1647 /* ADCs */ 1648 SND_SOC_DAPM_ADC("ADC1 L", NULL, SND_SOC_NOPM, 0, 0), 1649 SND_SOC_DAPM_ADC("ADC1 R", NULL, SND_SOC_NOPM, 0, 0), 1650 1651 SND_SOC_DAPM_SUPPLY("ADC1 L Power", RT5682_PWR_DIG_1, 1652 RT5682_PWR_ADC_L1_BIT, 0, NULL, 0), 1653 SND_SOC_DAPM_SUPPLY("ADC1 R Power", RT5682_PWR_DIG_1, 1654 RT5682_PWR_ADC_R1_BIT, 0, NULL, 0), 1655 SND_SOC_DAPM_SUPPLY("ADC1 clock", RT5682_CHOP_ADC, 1656 RT5682_CKGEN_ADC1_SFT, 0, NULL, 0), 1657 1658 /* ADC Mux */ 1659 SND_SOC_DAPM_MUX("Stereo1 ADC L1 Mux", SND_SOC_NOPM, 0, 0, 1660 &rt5682_sto1_adc1l_mux), 1661 SND_SOC_DAPM_MUX("Stereo1 ADC R1 Mux", SND_SOC_NOPM, 0, 0, 1662 &rt5682_sto1_adc1r_mux), 1663 SND_SOC_DAPM_MUX("Stereo1 ADC L2 Mux", SND_SOC_NOPM, 0, 0, 1664 &rt5682_sto1_adc2l_mux), 1665 SND_SOC_DAPM_MUX("Stereo1 ADC R2 Mux", SND_SOC_NOPM, 0, 0, 1666 &rt5682_sto1_adc2r_mux), 1667 SND_SOC_DAPM_MUX("Stereo1 ADC L Mux", SND_SOC_NOPM, 0, 0, 1668 &rt5682_sto1_adcl_mux), 1669 SND_SOC_DAPM_MUX("Stereo1 ADC R Mux", SND_SOC_NOPM, 0, 0, 1670 &rt5682_sto1_adcr_mux), 1671 SND_SOC_DAPM_MUX("IF1_ADC Mux", SND_SOC_NOPM, 0, 0, 1672 &rt5682_if1_adc_slot_mux), 1673 1674 /* ADC Mixer */ 1675 SND_SOC_DAPM_SUPPLY("ADC Stereo1 Filter", RT5682_PWR_DIG_2, 1676 RT5682_PWR_ADC_S1F_BIT, 0, set_filter_clk, 1677 SND_SOC_DAPM_PRE_PMU), 1678 SND_SOC_DAPM_MIXER("Stereo1 ADC MIXL", RT5682_STO1_ADC_DIG_VOL, 1679 RT5682_L_MUTE_SFT, 1, rt5682_sto1_adc_l_mix, 1680 ARRAY_SIZE(rt5682_sto1_adc_l_mix)), 1681 SND_SOC_DAPM_MIXER("Stereo1 ADC MIXR", RT5682_STO1_ADC_DIG_VOL, 1682 RT5682_R_MUTE_SFT, 1, rt5682_sto1_adc_r_mix, 1683 ARRAY_SIZE(rt5682_sto1_adc_r_mix)), 1684 SND_SOC_DAPM_SUPPLY("BTN Detection Mode", RT5682_SAR_IL_CMD_1, 1685 14, 1, NULL, 0), 1686 1687 /* ADC PGA */ 1688 SND_SOC_DAPM_PGA("Stereo1 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 1689 1690 /* Digital Interface */ 1691 SND_SOC_DAPM_SUPPLY("I2S1", RT5682_PWR_DIG_1, RT5682_PWR_I2S1_BIT, 1692 0, NULL, 0), 1693 SND_SOC_DAPM_SUPPLY("I2S2", RT5682_PWR_DIG_1, RT5682_PWR_I2S2_BIT, 1694 0, NULL, 0), 1695 SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0), 1696 SND_SOC_DAPM_PGA("IF1 DAC1 L", SND_SOC_NOPM, 0, 0, NULL, 0), 1697 SND_SOC_DAPM_PGA("IF1 DAC1 R", SND_SOC_NOPM, 0, 0, NULL, 0), 1698 SND_SOC_DAPM_PGA("SOUND DAC L", SND_SOC_NOPM, 0, 0, NULL, 0), 1699 SND_SOC_DAPM_PGA("SOUND DAC R", SND_SOC_NOPM, 0, 0, NULL, 0), 1700 1701 /* Digital Interface Select */ 1702 SND_SOC_DAPM_MUX("IF1 01 ADC Swap Mux", SND_SOC_NOPM, 0, 0, 1703 &rt5682_if1_01_adc_swap_mux), 1704 SND_SOC_DAPM_MUX("IF1 23 ADC Swap Mux", SND_SOC_NOPM, 0, 0, 1705 &rt5682_if1_23_adc_swap_mux), 1706 SND_SOC_DAPM_MUX("IF1 45 ADC Swap Mux", SND_SOC_NOPM, 0, 0, 1707 &rt5682_if1_45_adc_swap_mux), 1708 SND_SOC_DAPM_MUX("IF1 67 ADC Swap Mux", SND_SOC_NOPM, 0, 0, 1709 &rt5682_if1_67_adc_swap_mux), 1710 SND_SOC_DAPM_MUX("IF2 ADC Swap Mux", SND_SOC_NOPM, 0, 0, 1711 &rt5682_if2_adc_swap_mux), 1712 1713 SND_SOC_DAPM_MUX("ADCDAT Mux", SND_SOC_NOPM, 0, 0, 1714 &rt5682_adcdat_pin_ctrl), 1715 1716 SND_SOC_DAPM_MUX("DAC L Mux", SND_SOC_NOPM, 0, 0, 1717 &rt5682_dac_l_mux), 1718 SND_SOC_DAPM_MUX("DAC R Mux", SND_SOC_NOPM, 0, 0, 1719 &rt5682_dac_r_mux), 1720 1721 /* Audio Interface */ 1722 SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, 1723 RT5682_I2S1_SDP, RT5682_SEL_ADCDAT_SFT, 1), 1724 SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, 1725 RT5682_I2S2_SDP, RT5682_I2S2_PIN_CFG_SFT, 1), 1726 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0), 1727 SND_SOC_DAPM_AIF_IN("SDWRX", "SDW Playback", 0, SND_SOC_NOPM, 0, 0), 1728 SND_SOC_DAPM_AIF_OUT("SDWTX", "SDW Capture", 0, SND_SOC_NOPM, 0, 0), 1729 1730 /* Output Side */ 1731 /* DAC mixer before sound effect */ 1732 SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0, 1733 rt5682_dac_l_mix, ARRAY_SIZE(rt5682_dac_l_mix)), 1734 SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0, 1735 rt5682_dac_r_mix, ARRAY_SIZE(rt5682_dac_r_mix)), 1736 1737 /* DAC channel Mux */ 1738 SND_SOC_DAPM_MUX("DAC L1 Source", SND_SOC_NOPM, 0, 0, 1739 &rt5682_alg_dac_l1_mux), 1740 SND_SOC_DAPM_MUX("DAC R1 Source", SND_SOC_NOPM, 0, 0, 1741 &rt5682_alg_dac_r1_mux), 1742 1743 /* DAC Mixer */ 1744 SND_SOC_DAPM_SUPPLY("DAC Stereo1 Filter", RT5682_PWR_DIG_2, 1745 RT5682_PWR_DAC_S1F_BIT, 0, set_filter_clk, 1746 SND_SOC_DAPM_PRE_PMU), 1747 SND_SOC_DAPM_MIXER("Stereo1 DAC MIXL", SND_SOC_NOPM, 0, 0, 1748 rt5682_sto1_dac_l_mix, ARRAY_SIZE(rt5682_sto1_dac_l_mix)), 1749 SND_SOC_DAPM_MIXER("Stereo1 DAC MIXR", SND_SOC_NOPM, 0, 0, 1750 rt5682_sto1_dac_r_mix, ARRAY_SIZE(rt5682_sto1_dac_r_mix)), 1751 1752 /* DACs */ 1753 SND_SOC_DAPM_DAC("DAC L1", NULL, RT5682_PWR_DIG_1, 1754 RT5682_PWR_DAC_L1_BIT, 0), 1755 SND_SOC_DAPM_DAC("DAC R1", NULL, RT5682_PWR_DIG_1, 1756 RT5682_PWR_DAC_R1_BIT, 0), 1757 SND_SOC_DAPM_SUPPLY_S("DAC 1 Clock", 3, RT5682_CHOP_DAC, 1758 RT5682_CKGEN_DAC1_SFT, 0, NULL, 0), 1759 1760 /* HPO */ 1761 SND_SOC_DAPM_PGA_S("HP Amp", 1, SND_SOC_NOPM, 0, 0, rt5682_hp_event, 1762 SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_PRE_PMU), 1763 1764 SND_SOC_DAPM_SUPPLY("HP Amp L", RT5682_PWR_ANLG_1, 1765 RT5682_PWR_HA_L_BIT, 0, NULL, 0), 1766 SND_SOC_DAPM_SUPPLY("HP Amp R", RT5682_PWR_ANLG_1, 1767 RT5682_PWR_HA_R_BIT, 0, NULL, 0), 1768 SND_SOC_DAPM_SUPPLY_S("Charge Pump", 1, RT5682_DEPOP_1, 1769 RT5682_PUMP_EN_SFT, 0, NULL, 0), 1770 SND_SOC_DAPM_SUPPLY_S("Capless", 2, RT5682_DEPOP_1, 1771 RT5682_CAPLESS_EN_SFT, 0, NULL, 0), 1772 1773 SND_SOC_DAPM_SWITCH("HPOL Playback", SND_SOC_NOPM, 0, 0, 1774 &hpol_switch), 1775 SND_SOC_DAPM_SWITCH("HPOR Playback", SND_SOC_NOPM, 0, 0, 1776 &hpor_switch), 1777 1778 /* CLK DET */ 1779 SND_SOC_DAPM_SUPPLY("CLKDET SYS", RT5682_CLK_DET, 1780 RT5682_SYS_CLK_DET_SFT, 0, NULL, 0), 1781 SND_SOC_DAPM_SUPPLY("CLKDET PLL1", RT5682_CLK_DET, 1782 RT5682_PLL1_CLK_DET_SFT, 0, NULL, 0), 1783 SND_SOC_DAPM_SUPPLY("CLKDET PLL2", RT5682_CLK_DET, 1784 RT5682_PLL2_CLK_DET_SFT, 0, NULL, 0), 1785 SND_SOC_DAPM_SUPPLY("CLKDET", RT5682_CLK_DET, 1786 RT5682_POW_CLK_DET_SFT, 0, NULL, 0), 1787 1788 /* Output Lines */ 1789 SND_SOC_DAPM_OUTPUT("HPOL"), 1790 SND_SOC_DAPM_OUTPUT("HPOR"), 1791 }; 1792 1793 static const struct snd_soc_dapm_route rt5682_dapm_routes[] = { 1794 /*PLL*/ 1795 {"ADC Stereo1 Filter", NULL, "PLL1", is_sys_clk_from_pll1}, 1796 {"ADC Stereo1 Filter", NULL, "PLL2B", is_sys_clk_from_pll2}, 1797 {"ADC Stereo1 Filter", NULL, "PLL2F", is_sys_clk_from_pll2}, 1798 {"DAC Stereo1 Filter", NULL, "PLL1", is_sys_clk_from_pll1}, 1799 {"DAC Stereo1 Filter", NULL, "PLL2B", is_sys_clk_from_pll2}, 1800 {"DAC Stereo1 Filter", NULL, "PLL2F", is_sys_clk_from_pll2}, 1801 1802 /*ASRC*/ 1803 {"ADC Stereo1 Filter", NULL, "ADC STO1 ASRC", is_using_asrc}, 1804 {"DAC Stereo1 Filter", NULL, "DAC STO1 ASRC", is_using_asrc}, 1805 {"ADC STO1 ASRC", NULL, "AD ASRC"}, 1806 {"ADC STO1 ASRC", NULL, "DA ASRC"}, 1807 {"ADC STO1 ASRC", NULL, "CLKDET"}, 1808 {"DAC STO1 ASRC", NULL, "AD ASRC"}, 1809 {"DAC STO1 ASRC", NULL, "DA ASRC"}, 1810 {"DAC STO1 ASRC", NULL, "CLKDET"}, 1811 1812 /*Vref*/ 1813 {"MICBIAS1", NULL, "Vref1"}, 1814 {"MICBIAS2", NULL, "Vref1"}, 1815 1816 {"CLKDET SYS", NULL, "CLKDET"}, 1817 1818 {"IN1P", NULL, "LDO2"}, 1819 1820 {"BST1 CBJ", NULL, "IN1P"}, 1821 1822 {"RECMIX1L", "CBJ Switch", "BST1 CBJ"}, 1823 {"RECMIX1L", NULL, "RECMIX1L Power"}, 1824 1825 {"ADC1 L", NULL, "RECMIX1L"}, 1826 {"ADC1 L", NULL, "ADC1 L Power"}, 1827 {"ADC1 L", NULL, "ADC1 clock"}, 1828 1829 {"DMIC L1", NULL, "DMIC CLK"}, 1830 {"DMIC L1", NULL, "DMIC1 Power"}, 1831 {"DMIC R1", NULL, "DMIC CLK"}, 1832 {"DMIC R1", NULL, "DMIC1 Power"}, 1833 {"DMIC CLK", NULL, "DMIC ASRC"}, 1834 1835 {"Stereo1 ADC L Mux", "ADC1 L", "ADC1 L"}, 1836 {"Stereo1 ADC L Mux", "ADC1 R", "ADC1 R"}, 1837 {"Stereo1 ADC R Mux", "ADC1 L", "ADC1 L"}, 1838 {"Stereo1 ADC R Mux", "ADC1 R", "ADC1 R"}, 1839 1840 {"Stereo1 ADC L1 Mux", "ADC", "Stereo1 ADC L Mux"}, 1841 {"Stereo1 ADC L1 Mux", "DAC MIX", "Stereo1 DAC MIXL"}, 1842 {"Stereo1 ADC L2 Mux", "DMIC", "DMIC L1"}, 1843 {"Stereo1 ADC L2 Mux", "DAC MIX", "Stereo1 DAC MIXL"}, 1844 1845 {"Stereo1 ADC R1 Mux", "ADC", "Stereo1 ADC R Mux"}, 1846 {"Stereo1 ADC R1 Mux", "DAC MIX", "Stereo1 DAC MIXR"}, 1847 {"Stereo1 ADC R2 Mux", "DMIC", "DMIC R1"}, 1848 {"Stereo1 ADC R2 Mux", "DAC MIX", "Stereo1 DAC MIXR"}, 1849 1850 {"Stereo1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC L1 Mux"}, 1851 {"Stereo1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC L2 Mux"}, 1852 {"Stereo1 ADC MIXL", NULL, "ADC Stereo1 Filter"}, 1853 1854 {"Stereo1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC R1 Mux"}, 1855 {"Stereo1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC R2 Mux"}, 1856 {"Stereo1 ADC MIXR", NULL, "ADC Stereo1 Filter"}, 1857 1858 {"ADC Stereo1 Filter", NULL, "BTN Detection Mode"}, 1859 1860 {"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXL"}, 1861 {"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXR"}, 1862 1863 {"IF1 01 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"}, 1864 {"IF1 01 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"}, 1865 {"IF1 01 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"}, 1866 {"IF1 01 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"}, 1867 {"IF1 23 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"}, 1868 {"IF1 23 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"}, 1869 {"IF1 23 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"}, 1870 {"IF1 23 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"}, 1871 {"IF1 45 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"}, 1872 {"IF1 45 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"}, 1873 {"IF1 45 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"}, 1874 {"IF1 45 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"}, 1875 {"IF1 67 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"}, 1876 {"IF1 67 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"}, 1877 {"IF1 67 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"}, 1878 {"IF1 67 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"}, 1879 1880 {"IF1_ADC Mux", "Slot 0", "IF1 01 ADC Swap Mux"}, 1881 {"IF1_ADC Mux", "Slot 2", "IF1 23 ADC Swap Mux"}, 1882 {"IF1_ADC Mux", "Slot 4", "IF1 45 ADC Swap Mux"}, 1883 {"IF1_ADC Mux", "Slot 6", "IF1 67 ADC Swap Mux"}, 1884 {"ADCDAT Mux", "ADCDAT1", "IF1_ADC Mux"}, 1885 {"AIF1TX", NULL, "I2S1"}, 1886 {"AIF1TX", NULL, "ADCDAT Mux"}, 1887 {"IF2 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"}, 1888 {"IF2 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"}, 1889 {"IF2 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"}, 1890 {"IF2 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"}, 1891 {"ADCDAT Mux", "ADCDAT2", "IF2 ADC Swap Mux"}, 1892 {"AIF2TX", NULL, "ADCDAT Mux"}, 1893 1894 {"SDWTX", NULL, "PLL2B"}, 1895 {"SDWTX", NULL, "PLL2F"}, 1896 {"SDWTX", NULL, "ADCDAT Mux"}, 1897 1898 {"IF1 DAC1 L", NULL, "AIF1RX"}, 1899 {"IF1 DAC1 L", NULL, "I2S1"}, 1900 {"IF1 DAC1 L", NULL, "DAC Stereo1 Filter"}, 1901 {"IF1 DAC1 R", NULL, "AIF1RX"}, 1902 {"IF1 DAC1 R", NULL, "I2S1"}, 1903 {"IF1 DAC1 R", NULL, "DAC Stereo1 Filter"}, 1904 1905 {"SOUND DAC L", NULL, "SDWRX"}, 1906 {"SOUND DAC L", NULL, "DAC Stereo1 Filter"}, 1907 {"SOUND DAC L", NULL, "PLL2B"}, 1908 {"SOUND DAC L", NULL, "PLL2F"}, 1909 {"SOUND DAC R", NULL, "SDWRX"}, 1910 {"SOUND DAC R", NULL, "DAC Stereo1 Filter"}, 1911 {"SOUND DAC R", NULL, "PLL2B"}, 1912 {"SOUND DAC R", NULL, "PLL2F"}, 1913 1914 {"DAC L Mux", "IF1", "IF1 DAC1 L"}, 1915 {"DAC L Mux", "SOUND", "SOUND DAC L"}, 1916 {"DAC R Mux", "IF1", "IF1 DAC1 R"}, 1917 {"DAC R Mux", "SOUND", "SOUND DAC R"}, 1918 1919 {"DAC1 MIXL", "Stereo ADC Switch", "Stereo1 ADC MIXL"}, 1920 {"DAC1 MIXL", "DAC1 Switch", "DAC L Mux"}, 1921 {"DAC1 MIXR", "Stereo ADC Switch", "Stereo1 ADC MIXR"}, 1922 {"DAC1 MIXR", "DAC1 Switch", "DAC R Mux"}, 1923 1924 {"Stereo1 DAC MIXL", "DAC L1 Switch", "DAC1 MIXL"}, 1925 {"Stereo1 DAC MIXL", "DAC R1 Switch", "DAC1 MIXR"}, 1926 1927 {"Stereo1 DAC MIXR", "DAC R1 Switch", "DAC1 MIXR"}, 1928 {"Stereo1 DAC MIXR", "DAC L1 Switch", "DAC1 MIXL"}, 1929 1930 {"DAC L1 Source", "DAC1", "DAC1 MIXL"}, 1931 {"DAC L1 Source", "Stereo1 DAC Mixer", "Stereo1 DAC MIXL"}, 1932 {"DAC R1 Source", "DAC1", "DAC1 MIXR"}, 1933 {"DAC R1 Source", "Stereo1 DAC Mixer", "Stereo1 DAC MIXR"}, 1934 1935 {"DAC L1", NULL, "DAC L1 Source"}, 1936 {"DAC R1", NULL, "DAC R1 Source"}, 1937 1938 {"DAC L1", NULL, "DAC 1 Clock"}, 1939 {"DAC R1", NULL, "DAC 1 Clock"}, 1940 1941 {"HP Amp", NULL, "DAC L1"}, 1942 {"HP Amp", NULL, "DAC R1"}, 1943 {"HP Amp", NULL, "HP Amp L"}, 1944 {"HP Amp", NULL, "HP Amp R"}, 1945 {"HP Amp", NULL, "Capless"}, 1946 {"HP Amp", NULL, "Charge Pump"}, 1947 {"HP Amp", NULL, "CLKDET SYS"}, 1948 {"HP Amp", NULL, "Vref1"}, 1949 {"HPOL Playback", "Switch", "HP Amp"}, 1950 {"HPOR Playback", "Switch", "HP Amp"}, 1951 {"HPOL", NULL, "HPOL Playback"}, 1952 {"HPOR", NULL, "HPOR Playback"}, 1953 }; 1954 1955 static int rt5682_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask, 1956 unsigned int rx_mask, int slots, int slot_width) 1957 { 1958 struct snd_soc_component *component = dai->component; 1959 unsigned int cl, val = 0; 1960 1961 if (tx_mask || rx_mask) 1962 snd_soc_component_update_bits(component, RT5682_TDM_ADDA_CTRL_2, 1963 RT5682_TDM_EN, RT5682_TDM_EN); 1964 else 1965 snd_soc_component_update_bits(component, RT5682_TDM_ADDA_CTRL_2, 1966 RT5682_TDM_EN, 0); 1967 1968 switch (slots) { 1969 case 4: 1970 val |= RT5682_TDM_TX_CH_4; 1971 val |= RT5682_TDM_RX_CH_4; 1972 break; 1973 case 6: 1974 val |= RT5682_TDM_TX_CH_6; 1975 val |= RT5682_TDM_RX_CH_6; 1976 break; 1977 case 8: 1978 val |= RT5682_TDM_TX_CH_8; 1979 val |= RT5682_TDM_RX_CH_8; 1980 break; 1981 case 2: 1982 break; 1983 default: 1984 return -EINVAL; 1985 } 1986 1987 snd_soc_component_update_bits(component, RT5682_TDM_CTRL, 1988 RT5682_TDM_TX_CH_MASK | RT5682_TDM_RX_CH_MASK, val); 1989 1990 switch (slot_width) { 1991 case 8: 1992 if (tx_mask || rx_mask) 1993 return -EINVAL; 1994 cl = RT5682_I2S1_TX_CHL_8 | RT5682_I2S1_RX_CHL_8; 1995 break; 1996 case 16: 1997 val = RT5682_TDM_CL_16; 1998 cl = RT5682_I2S1_TX_CHL_16 | RT5682_I2S1_RX_CHL_16; 1999 break; 2000 case 20: 2001 val = RT5682_TDM_CL_20; 2002 cl = RT5682_I2S1_TX_CHL_20 | RT5682_I2S1_RX_CHL_20; 2003 break; 2004 case 24: 2005 val = RT5682_TDM_CL_24; 2006 cl = RT5682_I2S1_TX_CHL_24 | RT5682_I2S1_RX_CHL_24; 2007 break; 2008 case 32: 2009 val = RT5682_TDM_CL_32; 2010 cl = RT5682_I2S1_TX_CHL_32 | RT5682_I2S1_RX_CHL_32; 2011 break; 2012 default: 2013 return -EINVAL; 2014 } 2015 2016 snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL, 2017 RT5682_TDM_CL_MASK, val); 2018 snd_soc_component_update_bits(component, RT5682_I2S1_SDP, 2019 RT5682_I2S1_TX_CHL_MASK | RT5682_I2S1_RX_CHL_MASK, cl); 2020 2021 return 0; 2022 } 2023 2024 static int rt5682_hw_params(struct snd_pcm_substream *substream, 2025 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) 2026 { 2027 struct snd_soc_component *component = dai->component; 2028 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 2029 unsigned int len_1 = 0, len_2 = 0; 2030 int pre_div, frame_size; 2031 2032 rt5682->lrck[dai->id] = params_rate(params); 2033 pre_div = rl6231_get_clk_info(rt5682->sysclk, rt5682->lrck[dai->id]); 2034 2035 frame_size = snd_soc_params_to_frame_size(params); 2036 if (frame_size < 0) { 2037 dev_err(component->dev, "Unsupported frame size: %d\n", 2038 frame_size); 2039 return -EINVAL; 2040 } 2041 2042 dev_dbg(dai->dev, "lrck is %dHz and pre_div is %d for iis %d\n", 2043 rt5682->lrck[dai->id], pre_div, dai->id); 2044 2045 switch (params_width(params)) { 2046 case 16: 2047 break; 2048 case 20: 2049 len_1 |= RT5682_I2S1_DL_20; 2050 len_2 |= RT5682_I2S2_DL_20; 2051 break; 2052 case 24: 2053 len_1 |= RT5682_I2S1_DL_24; 2054 len_2 |= RT5682_I2S2_DL_24; 2055 break; 2056 case 32: 2057 len_1 |= RT5682_I2S1_DL_32; 2058 len_2 |= RT5682_I2S2_DL_24; 2059 break; 2060 case 8: 2061 len_1 |= RT5682_I2S2_DL_8; 2062 len_2 |= RT5682_I2S2_DL_8; 2063 break; 2064 default: 2065 return -EINVAL; 2066 } 2067 2068 switch (dai->id) { 2069 case RT5682_AIF1: 2070 snd_soc_component_update_bits(component, RT5682_I2S1_SDP, 2071 RT5682_I2S1_DL_MASK, len_1); 2072 if (rt5682->master[RT5682_AIF1]) { 2073 snd_soc_component_update_bits(component, 2074 RT5682_ADDA_CLK_1, RT5682_I2S_M_DIV_MASK | 2075 RT5682_I2S_CLK_SRC_MASK, 2076 pre_div << RT5682_I2S_M_DIV_SFT | 2077 (rt5682->sysclk_src) << RT5682_I2S_CLK_SRC_SFT); 2078 } 2079 if (params_channels(params) == 1) /* mono mode */ 2080 snd_soc_component_update_bits(component, 2081 RT5682_I2S1_SDP, RT5682_I2S1_MONO_MASK, 2082 RT5682_I2S1_MONO_EN); 2083 else 2084 snd_soc_component_update_bits(component, 2085 RT5682_I2S1_SDP, RT5682_I2S1_MONO_MASK, 2086 RT5682_I2S1_MONO_DIS); 2087 break; 2088 case RT5682_AIF2: 2089 snd_soc_component_update_bits(component, RT5682_I2S2_SDP, 2090 RT5682_I2S2_DL_MASK, len_2); 2091 if (rt5682->master[RT5682_AIF2]) { 2092 snd_soc_component_update_bits(component, 2093 RT5682_I2S_M_CLK_CTRL_1, RT5682_I2S2_M_PD_MASK, 2094 pre_div << RT5682_I2S2_M_PD_SFT); 2095 } 2096 if (params_channels(params) == 1) /* mono mode */ 2097 snd_soc_component_update_bits(component, 2098 RT5682_I2S2_SDP, RT5682_I2S2_MONO_MASK, 2099 RT5682_I2S2_MONO_EN); 2100 else 2101 snd_soc_component_update_bits(component, 2102 RT5682_I2S2_SDP, RT5682_I2S2_MONO_MASK, 2103 RT5682_I2S2_MONO_DIS); 2104 break; 2105 default: 2106 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id); 2107 return -EINVAL; 2108 } 2109 2110 return 0; 2111 } 2112 2113 static int rt5682_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) 2114 { 2115 struct snd_soc_component *component = dai->component; 2116 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 2117 unsigned int reg_val = 0, tdm_ctrl = 0; 2118 2119 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 2120 case SND_SOC_DAIFMT_CBM_CFM: 2121 rt5682->master[dai->id] = 1; 2122 break; 2123 case SND_SOC_DAIFMT_CBS_CFS: 2124 rt5682->master[dai->id] = 0; 2125 break; 2126 default: 2127 return -EINVAL; 2128 } 2129 2130 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 2131 case SND_SOC_DAIFMT_NB_NF: 2132 break; 2133 case SND_SOC_DAIFMT_IB_NF: 2134 reg_val |= RT5682_I2S_BP_INV; 2135 tdm_ctrl |= RT5682_TDM_S_BP_INV; 2136 break; 2137 case SND_SOC_DAIFMT_NB_IF: 2138 if (dai->id == RT5682_AIF1) 2139 tdm_ctrl |= RT5682_TDM_S_LP_INV | RT5682_TDM_M_BP_INV; 2140 else 2141 return -EINVAL; 2142 break; 2143 case SND_SOC_DAIFMT_IB_IF: 2144 if (dai->id == RT5682_AIF1) 2145 tdm_ctrl |= RT5682_TDM_S_BP_INV | RT5682_TDM_S_LP_INV | 2146 RT5682_TDM_M_BP_INV | RT5682_TDM_M_LP_INV; 2147 else 2148 return -EINVAL; 2149 break; 2150 default: 2151 return -EINVAL; 2152 } 2153 2154 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 2155 case SND_SOC_DAIFMT_I2S: 2156 break; 2157 case SND_SOC_DAIFMT_LEFT_J: 2158 reg_val |= RT5682_I2S_DF_LEFT; 2159 tdm_ctrl |= RT5682_TDM_DF_LEFT; 2160 break; 2161 case SND_SOC_DAIFMT_DSP_A: 2162 reg_val |= RT5682_I2S_DF_PCM_A; 2163 tdm_ctrl |= RT5682_TDM_DF_PCM_A; 2164 break; 2165 case SND_SOC_DAIFMT_DSP_B: 2166 reg_val |= RT5682_I2S_DF_PCM_B; 2167 tdm_ctrl |= RT5682_TDM_DF_PCM_B; 2168 break; 2169 default: 2170 return -EINVAL; 2171 } 2172 2173 switch (dai->id) { 2174 case RT5682_AIF1: 2175 snd_soc_component_update_bits(component, RT5682_I2S1_SDP, 2176 RT5682_I2S_DF_MASK, reg_val); 2177 snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL, 2178 RT5682_TDM_MS_MASK | RT5682_TDM_S_BP_MASK | 2179 RT5682_TDM_DF_MASK | RT5682_TDM_M_BP_MASK | 2180 RT5682_TDM_M_LP_MASK | RT5682_TDM_S_LP_MASK, 2181 tdm_ctrl | rt5682->master[dai->id]); 2182 break; 2183 case RT5682_AIF2: 2184 if (rt5682->master[dai->id] == 0) 2185 reg_val |= RT5682_I2S2_MS_S; 2186 snd_soc_component_update_bits(component, RT5682_I2S2_SDP, 2187 RT5682_I2S2_MS_MASK | RT5682_I2S_BP_MASK | 2188 RT5682_I2S_DF_MASK, reg_val); 2189 break; 2190 default: 2191 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id); 2192 return -EINVAL; 2193 } 2194 return 0; 2195 } 2196 2197 static int rt5682_set_component_sysclk(struct snd_soc_component *component, 2198 int clk_id, int source, unsigned int freq, int dir) 2199 { 2200 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 2201 unsigned int reg_val = 0, src = 0; 2202 2203 if (freq == rt5682->sysclk && clk_id == rt5682->sysclk_src) 2204 return 0; 2205 2206 switch (clk_id) { 2207 case RT5682_SCLK_S_MCLK: 2208 reg_val |= RT5682_SCLK_SRC_MCLK; 2209 src = RT5682_CLK_SRC_MCLK; 2210 break; 2211 case RT5682_SCLK_S_PLL1: 2212 reg_val |= RT5682_SCLK_SRC_PLL1; 2213 src = RT5682_CLK_SRC_PLL1; 2214 break; 2215 case RT5682_SCLK_S_PLL2: 2216 reg_val |= RT5682_SCLK_SRC_PLL2; 2217 src = RT5682_CLK_SRC_PLL2; 2218 break; 2219 case RT5682_SCLK_S_RCCLK: 2220 reg_val |= RT5682_SCLK_SRC_RCCLK; 2221 src = RT5682_CLK_SRC_RCCLK; 2222 break; 2223 default: 2224 dev_err(component->dev, "Invalid clock id (%d)\n", clk_id); 2225 return -EINVAL; 2226 } 2227 snd_soc_component_update_bits(component, RT5682_GLB_CLK, 2228 RT5682_SCLK_SRC_MASK, reg_val); 2229 2230 if (rt5682->master[RT5682_AIF2]) { 2231 snd_soc_component_update_bits(component, 2232 RT5682_I2S_M_CLK_CTRL_1, RT5682_I2S2_SRC_MASK, 2233 src << RT5682_I2S2_SRC_SFT); 2234 } 2235 2236 rt5682->sysclk = freq; 2237 rt5682->sysclk_src = clk_id; 2238 2239 dev_dbg(component->dev, "Sysclk is %dHz and clock id is %d\n", 2240 freq, clk_id); 2241 2242 return 0; 2243 } 2244 2245 static int rt5682_set_component_pll(struct snd_soc_component *component, 2246 int pll_id, int source, unsigned int freq_in, 2247 unsigned int freq_out) 2248 { 2249 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 2250 struct rl6231_pll_code pll_code, pll2f_code, pll2b_code; 2251 unsigned int pll2_fout1; 2252 int ret; 2253 2254 if (source == rt5682->pll_src[pll_id] && 2255 freq_in == rt5682->pll_in[pll_id] && 2256 freq_out == rt5682->pll_out[pll_id]) 2257 return 0; 2258 2259 if (!freq_in || !freq_out) { 2260 dev_dbg(component->dev, "PLL disabled\n"); 2261 2262 rt5682->pll_in[pll_id] = 0; 2263 rt5682->pll_out[pll_id] = 0; 2264 snd_soc_component_update_bits(component, RT5682_GLB_CLK, 2265 RT5682_SCLK_SRC_MASK, RT5682_SCLK_SRC_MCLK); 2266 return 0; 2267 } 2268 2269 if (pll_id == RT5682_PLL2) { 2270 switch (source) { 2271 case RT5682_PLL2_S_MCLK: 2272 snd_soc_component_update_bits(component, 2273 RT5682_GLB_CLK, RT5682_PLL2_SRC_MASK, 2274 RT5682_PLL2_SRC_MCLK); 2275 break; 2276 default: 2277 dev_err(component->dev, "Unknown PLL2 Source %d\n", 2278 source); 2279 return -EINVAL; 2280 } 2281 2282 /** 2283 * PLL2 concatenates 2 PLL units. 2284 * We suggest the Fout of the front PLL is 3.84MHz. 2285 */ 2286 pll2_fout1 = 3840000; 2287 ret = rl6231_pll_calc(freq_in, pll2_fout1, &pll2f_code); 2288 if (ret < 0) { 2289 dev_err(component->dev, "Unsupport input clock %d\n", 2290 freq_in); 2291 return ret; 2292 } 2293 dev_dbg(component->dev, "PLL2F: fin=%d fout=%d bypass=%d m=%d n=%d k=%d\n", 2294 freq_in, pll2_fout1, 2295 pll2f_code.m_bp, 2296 (pll2f_code.m_bp ? 0 : pll2f_code.m_code), 2297 pll2f_code.n_code, pll2f_code.k_code); 2298 2299 ret = rl6231_pll_calc(pll2_fout1, freq_out, &pll2b_code); 2300 if (ret < 0) { 2301 dev_err(component->dev, "Unsupport input clock %d\n", 2302 pll2_fout1); 2303 return ret; 2304 } 2305 dev_dbg(component->dev, "PLL2B: fin=%d fout=%d bypass=%d m=%d n=%d k=%d\n", 2306 pll2_fout1, freq_out, 2307 pll2b_code.m_bp, 2308 (pll2b_code.m_bp ? 0 : pll2b_code.m_code), 2309 pll2b_code.n_code, pll2b_code.k_code); 2310 2311 snd_soc_component_write(component, RT5682_PLL2_CTRL_1, 2312 pll2f_code.k_code << RT5682_PLL2F_K_SFT | 2313 pll2b_code.k_code << RT5682_PLL2B_K_SFT | 2314 pll2b_code.m_code); 2315 snd_soc_component_write(component, RT5682_PLL2_CTRL_2, 2316 pll2f_code.m_code << RT5682_PLL2F_M_SFT | 2317 pll2b_code.n_code); 2318 snd_soc_component_write(component, RT5682_PLL2_CTRL_3, 2319 pll2f_code.n_code << RT5682_PLL2F_N_SFT); 2320 snd_soc_component_update_bits(component, RT5682_PLL2_CTRL_4, 2321 RT5682_PLL2B_M_BP_MASK | RT5682_PLL2F_M_BP_MASK | 0xf, 2322 (pll2b_code.m_bp ? 1 : 0) << RT5682_PLL2B_M_BP_SFT | 2323 (pll2f_code.m_bp ? 1 : 0) << RT5682_PLL2F_M_BP_SFT | 2324 0xf); 2325 } else { 2326 switch (source) { 2327 case RT5682_PLL1_S_MCLK: 2328 snd_soc_component_update_bits(component, 2329 RT5682_GLB_CLK, RT5682_PLL1_SRC_MASK, 2330 RT5682_PLL1_SRC_MCLK); 2331 break; 2332 case RT5682_PLL1_S_BCLK1: 2333 snd_soc_component_update_bits(component, 2334 RT5682_GLB_CLK, RT5682_PLL1_SRC_MASK, 2335 RT5682_PLL1_SRC_BCLK1); 2336 break; 2337 default: 2338 dev_err(component->dev, "Unknown PLL1 Source %d\n", 2339 source); 2340 return -EINVAL; 2341 } 2342 2343 ret = rl6231_pll_calc(freq_in, freq_out, &pll_code); 2344 if (ret < 0) { 2345 dev_err(component->dev, "Unsupport input clock %d\n", 2346 freq_in); 2347 return ret; 2348 } 2349 2350 dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n", 2351 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code), 2352 pll_code.n_code, pll_code.k_code); 2353 2354 snd_soc_component_write(component, RT5682_PLL_CTRL_1, 2355 pll_code.n_code << RT5682_PLL_N_SFT | pll_code.k_code); 2356 snd_soc_component_write(component, RT5682_PLL_CTRL_2, 2357 (pll_code.m_bp ? 0 : pll_code.m_code) << RT5682_PLL_M_SFT | 2358 pll_code.m_bp << RT5682_PLL_M_BP_SFT | RT5682_PLL_RST); 2359 } 2360 2361 rt5682->pll_in[pll_id] = freq_in; 2362 rt5682->pll_out[pll_id] = freq_out; 2363 rt5682->pll_src[pll_id] = source; 2364 2365 return 0; 2366 } 2367 2368 static int rt5682_set_bclk1_ratio(struct snd_soc_dai *dai, unsigned int ratio) 2369 { 2370 struct snd_soc_component *component = dai->component; 2371 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 2372 2373 rt5682->bclk[dai->id] = ratio; 2374 2375 switch (ratio) { 2376 case 256: 2377 snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL, 2378 RT5682_TDM_BCLK_MS1_MASK, RT5682_TDM_BCLK_MS1_256); 2379 break; 2380 case 128: 2381 snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL, 2382 RT5682_TDM_BCLK_MS1_MASK, RT5682_TDM_BCLK_MS1_128); 2383 break; 2384 case 64: 2385 snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL, 2386 RT5682_TDM_BCLK_MS1_MASK, RT5682_TDM_BCLK_MS1_64); 2387 break; 2388 case 32: 2389 snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL, 2390 RT5682_TDM_BCLK_MS1_MASK, RT5682_TDM_BCLK_MS1_32); 2391 break; 2392 default: 2393 dev_err(dai->dev, "Invalid bclk1 ratio %d\n", ratio); 2394 return -EINVAL; 2395 } 2396 2397 return 0; 2398 } 2399 2400 static int rt5682_set_bclk2_ratio(struct snd_soc_dai *dai, unsigned int ratio) 2401 { 2402 struct snd_soc_component *component = dai->component; 2403 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 2404 2405 rt5682->bclk[dai->id] = ratio; 2406 2407 switch (ratio) { 2408 case 64: 2409 snd_soc_component_update_bits(component, RT5682_ADDA_CLK_2, 2410 RT5682_I2S2_BCLK_MS2_MASK, 2411 RT5682_I2S2_BCLK_MS2_64); 2412 break; 2413 case 32: 2414 snd_soc_component_update_bits(component, RT5682_ADDA_CLK_2, 2415 RT5682_I2S2_BCLK_MS2_MASK, 2416 RT5682_I2S2_BCLK_MS2_32); 2417 break; 2418 default: 2419 dev_err(dai->dev, "Invalid bclk2 ratio %d\n", ratio); 2420 return -EINVAL; 2421 } 2422 2423 return 0; 2424 } 2425 2426 static int rt5682_set_bias_level(struct snd_soc_component *component, 2427 enum snd_soc_bias_level level) 2428 { 2429 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 2430 2431 switch (level) { 2432 case SND_SOC_BIAS_PREPARE: 2433 regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_1, 2434 RT5682_PWR_BG, RT5682_PWR_BG); 2435 regmap_update_bits(rt5682->regmap, RT5682_PWR_DIG_1, 2436 RT5682_DIG_GATE_CTRL | RT5682_PWR_LDO, 2437 RT5682_DIG_GATE_CTRL | RT5682_PWR_LDO); 2438 break; 2439 2440 case SND_SOC_BIAS_STANDBY: 2441 regmap_update_bits(rt5682->regmap, RT5682_PWR_DIG_1, 2442 RT5682_DIG_GATE_CTRL, RT5682_DIG_GATE_CTRL); 2443 break; 2444 case SND_SOC_BIAS_OFF: 2445 regmap_update_bits(rt5682->regmap, RT5682_PWR_DIG_1, 2446 RT5682_DIG_GATE_CTRL | RT5682_PWR_LDO, 0); 2447 regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_1, 2448 RT5682_PWR_BG, 0); 2449 break; 2450 case SND_SOC_BIAS_ON: 2451 break; 2452 } 2453 2454 return 0; 2455 } 2456 2457 #ifdef CONFIG_COMMON_CLK 2458 #define CLK_PLL2_FIN 48000000 2459 #define CLK_PLL2_FOUT 24576000 2460 #define CLK_48 48000 2461 2462 static bool rt5682_clk_check(struct rt5682_priv *rt5682) 2463 { 2464 if (!rt5682->master[RT5682_AIF1]) { 2465 dev_err(rt5682->component->dev, "sysclk/dai not set correctly\n"); 2466 return false; 2467 } 2468 return true; 2469 } 2470 2471 static int rt5682_wclk_prepare(struct clk_hw *hw) 2472 { 2473 struct rt5682_priv *rt5682 = 2474 container_of(hw, struct rt5682_priv, 2475 dai_clks_hw[RT5682_DAI_WCLK_IDX]); 2476 struct snd_soc_component *component = rt5682->component; 2477 struct snd_soc_dapm_context *dapm = 2478 snd_soc_component_get_dapm(component); 2479 2480 if (!rt5682_clk_check(rt5682)) 2481 return -EINVAL; 2482 2483 snd_soc_dapm_mutex_lock(dapm); 2484 2485 snd_soc_dapm_force_enable_pin_unlocked(dapm, "MICBIAS"); 2486 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_1, 2487 RT5682_PWR_MB, RT5682_PWR_MB); 2488 snd_soc_dapm_force_enable_pin_unlocked(dapm, "I2S1"); 2489 snd_soc_dapm_force_enable_pin_unlocked(dapm, "PLL2F"); 2490 snd_soc_dapm_force_enable_pin_unlocked(dapm, "PLL2B"); 2491 snd_soc_dapm_sync_unlocked(dapm); 2492 2493 snd_soc_dapm_mutex_unlock(dapm); 2494 2495 return 0; 2496 } 2497 2498 static void rt5682_wclk_unprepare(struct clk_hw *hw) 2499 { 2500 struct rt5682_priv *rt5682 = 2501 container_of(hw, struct rt5682_priv, 2502 dai_clks_hw[RT5682_DAI_WCLK_IDX]); 2503 struct snd_soc_component *component = rt5682->component; 2504 struct snd_soc_dapm_context *dapm = 2505 snd_soc_component_get_dapm(component); 2506 2507 if (!rt5682_clk_check(rt5682)) 2508 return; 2509 2510 snd_soc_dapm_mutex_lock(dapm); 2511 2512 snd_soc_dapm_disable_pin_unlocked(dapm, "MICBIAS"); 2513 if (!rt5682->jack_type) 2514 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_1, 2515 RT5682_PWR_MB, 0); 2516 snd_soc_dapm_disable_pin_unlocked(dapm, "I2S1"); 2517 snd_soc_dapm_disable_pin_unlocked(dapm, "PLL2F"); 2518 snd_soc_dapm_disable_pin_unlocked(dapm, "PLL2B"); 2519 snd_soc_dapm_sync_unlocked(dapm); 2520 2521 snd_soc_dapm_mutex_unlock(dapm); 2522 } 2523 2524 static unsigned long rt5682_wclk_recalc_rate(struct clk_hw *hw, 2525 unsigned long parent_rate) 2526 { 2527 struct rt5682_priv *rt5682 = 2528 container_of(hw, struct rt5682_priv, 2529 dai_clks_hw[RT5682_DAI_WCLK_IDX]); 2530 2531 if (!rt5682_clk_check(rt5682)) 2532 return 0; 2533 /* 2534 * Only accept to set wclk rate to 48kHz temporarily. 2535 */ 2536 return CLK_48; 2537 } 2538 2539 static long rt5682_wclk_round_rate(struct clk_hw *hw, unsigned long rate, 2540 unsigned long *parent_rate) 2541 { 2542 struct rt5682_priv *rt5682 = 2543 container_of(hw, struct rt5682_priv, 2544 dai_clks_hw[RT5682_DAI_WCLK_IDX]); 2545 2546 if (!rt5682_clk_check(rt5682)) 2547 return -EINVAL; 2548 /* 2549 * Only accept to set wclk rate to 48kHz temporarily. 2550 */ 2551 return CLK_48; 2552 } 2553 2554 static int rt5682_wclk_set_rate(struct clk_hw *hw, unsigned long rate, 2555 unsigned long parent_rate) 2556 { 2557 struct rt5682_priv *rt5682 = 2558 container_of(hw, struct rt5682_priv, 2559 dai_clks_hw[RT5682_DAI_WCLK_IDX]); 2560 struct snd_soc_component *component = rt5682->component; 2561 struct clk *parent_clk; 2562 const char * const clk_name = __clk_get_name(hw->clk); 2563 int pre_div; 2564 2565 if (!rt5682_clk_check(rt5682)) 2566 return -EINVAL; 2567 2568 /* 2569 * Whether the wclk's parent clk (mclk) exists or not, please ensure 2570 * it is fixed or set to 48MHz before setting wclk rate. It's a 2571 * temporary limitation. Only accept 48MHz clk as the clk provider. 2572 * 2573 * It will set the codec anyway by assuming mclk is 48MHz. 2574 */ 2575 parent_clk = clk_get_parent(hw->clk); 2576 if (!parent_clk) 2577 dev_warn(component->dev, 2578 "Parent mclk of wclk not acquired in driver. Please ensure mclk was provided as %d Hz.\n", 2579 CLK_PLL2_FIN); 2580 2581 if (parent_rate != CLK_PLL2_FIN) 2582 dev_warn(component->dev, "clk %s only support %d Hz input\n", 2583 clk_name, CLK_PLL2_FIN); 2584 2585 /* 2586 * It's a temporary limitation. Only accept to set wclk rate to 48kHz. 2587 * It will force wclk to 48kHz even it's not. 2588 */ 2589 if (rate != CLK_48) { 2590 dev_warn(component->dev, "clk %s only support %d Hz output\n", 2591 clk_name, CLK_48); 2592 rate = CLK_48; 2593 } 2594 2595 /* 2596 * To achieve the rate conversion from 48MHz to 48kHz, PLL2 is needed. 2597 */ 2598 rt5682_set_component_pll(component, RT5682_PLL2, RT5682_PLL2_S_MCLK, 2599 CLK_PLL2_FIN, CLK_PLL2_FOUT); 2600 2601 rt5682_set_component_sysclk(component, RT5682_SCLK_S_PLL2, 0, 2602 CLK_PLL2_FOUT, SND_SOC_CLOCK_IN); 2603 2604 pre_div = rl6231_get_clk_info(rt5682->sysclk, rate); 2605 2606 snd_soc_component_update_bits(component, RT5682_ADDA_CLK_1, 2607 RT5682_I2S_M_DIV_MASK | RT5682_I2S_CLK_SRC_MASK, 2608 pre_div << RT5682_I2S_M_DIV_SFT | 2609 (rt5682->sysclk_src) << RT5682_I2S_CLK_SRC_SFT); 2610 2611 return 0; 2612 } 2613 2614 static unsigned long rt5682_bclk_recalc_rate(struct clk_hw *hw, 2615 unsigned long parent_rate) 2616 { 2617 struct rt5682_priv *rt5682 = 2618 container_of(hw, struct rt5682_priv, 2619 dai_clks_hw[RT5682_DAI_BCLK_IDX]); 2620 struct snd_soc_component *component = rt5682->component; 2621 unsigned int bclks_per_wclk; 2622 2623 snd_soc_component_read(component, RT5682_TDM_TCON_CTRL, 2624 &bclks_per_wclk); 2625 2626 switch (bclks_per_wclk & RT5682_TDM_BCLK_MS1_MASK) { 2627 case RT5682_TDM_BCLK_MS1_256: 2628 return parent_rate * 256; 2629 case RT5682_TDM_BCLK_MS1_128: 2630 return parent_rate * 128; 2631 case RT5682_TDM_BCLK_MS1_64: 2632 return parent_rate * 64; 2633 case RT5682_TDM_BCLK_MS1_32: 2634 return parent_rate * 32; 2635 default: 2636 return 0; 2637 } 2638 } 2639 2640 static unsigned long rt5682_bclk_get_factor(unsigned long rate, 2641 unsigned long parent_rate) 2642 { 2643 unsigned long factor; 2644 2645 factor = rate / parent_rate; 2646 if (factor < 64) 2647 return 32; 2648 else if (factor < 128) 2649 return 64; 2650 else if (factor < 256) 2651 return 128; 2652 else 2653 return 256; 2654 } 2655 2656 static long rt5682_bclk_round_rate(struct clk_hw *hw, unsigned long rate, 2657 unsigned long *parent_rate) 2658 { 2659 struct rt5682_priv *rt5682 = 2660 container_of(hw, struct rt5682_priv, 2661 dai_clks_hw[RT5682_DAI_BCLK_IDX]); 2662 unsigned long factor; 2663 2664 if (!*parent_rate || !rt5682_clk_check(rt5682)) 2665 return -EINVAL; 2666 2667 /* 2668 * BCLK rates are set as a multiplier of WCLK in HW. 2669 * We don't allow changing the parent WCLK. We just do 2670 * some rounding down based on the parent WCLK rate 2671 * and find the appropriate multiplier of BCLK to 2672 * get the rounded down BCLK value. 2673 */ 2674 factor = rt5682_bclk_get_factor(rate, *parent_rate); 2675 2676 return *parent_rate * factor; 2677 } 2678 2679 static int rt5682_bclk_set_rate(struct clk_hw *hw, unsigned long rate, 2680 unsigned long parent_rate) 2681 { 2682 struct rt5682_priv *rt5682 = 2683 container_of(hw, struct rt5682_priv, 2684 dai_clks_hw[RT5682_DAI_BCLK_IDX]); 2685 struct snd_soc_component *component = rt5682->component; 2686 struct snd_soc_dai *dai = NULL; 2687 unsigned long factor; 2688 2689 if (!rt5682_clk_check(rt5682)) 2690 return -EINVAL; 2691 2692 factor = rt5682_bclk_get_factor(rate, parent_rate); 2693 2694 for_each_component_dais(component, dai) 2695 if (dai->id == RT5682_AIF1) 2696 break; 2697 if (!dai) { 2698 dev_err(component->dev, "dai %d not found in component\n", 2699 RT5682_AIF1); 2700 return -ENODEV; 2701 } 2702 2703 return rt5682_set_bclk1_ratio(dai, factor); 2704 } 2705 2706 static const struct clk_ops rt5682_dai_clk_ops[RT5682_DAI_NUM_CLKS] = { 2707 [RT5682_DAI_WCLK_IDX] = { 2708 .prepare = rt5682_wclk_prepare, 2709 .unprepare = rt5682_wclk_unprepare, 2710 .recalc_rate = rt5682_wclk_recalc_rate, 2711 .round_rate = rt5682_wclk_round_rate, 2712 .set_rate = rt5682_wclk_set_rate, 2713 }, 2714 [RT5682_DAI_BCLK_IDX] = { 2715 .recalc_rate = rt5682_bclk_recalc_rate, 2716 .round_rate = rt5682_bclk_round_rate, 2717 .set_rate = rt5682_bclk_set_rate, 2718 }, 2719 }; 2720 2721 static int rt5682_register_dai_clks(struct snd_soc_component *component) 2722 { 2723 struct device *dev = component->dev; 2724 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 2725 struct rt5682_platform_data *pdata = &rt5682->pdata; 2726 struct clk_init_data init; 2727 struct clk *dai_clk; 2728 struct clk_lookup *dai_clk_lookup; 2729 struct clk_hw *dai_clk_hw; 2730 const char *parent_name; 2731 int i, ret; 2732 2733 for (i = 0; i < RT5682_DAI_NUM_CLKS; ++i) { 2734 dai_clk_hw = &rt5682->dai_clks_hw[i]; 2735 2736 switch (i) { 2737 case RT5682_DAI_WCLK_IDX: 2738 /* Make MCLK the parent of WCLK */ 2739 if (rt5682->mclk) { 2740 parent_name = __clk_get_name(rt5682->mclk); 2741 init.parent_names = &parent_name; 2742 init.num_parents = 1; 2743 } else { 2744 init.parent_names = NULL; 2745 init.num_parents = 0; 2746 } 2747 break; 2748 case RT5682_DAI_BCLK_IDX: 2749 /* Make WCLK the parent of BCLK */ 2750 parent_name = __clk_get_name( 2751 rt5682->dai_clks[RT5682_DAI_WCLK_IDX]); 2752 init.parent_names = &parent_name; 2753 init.num_parents = 1; 2754 break; 2755 default: 2756 dev_err(dev, "Invalid clock index\n"); 2757 ret = -EINVAL; 2758 goto err; 2759 } 2760 2761 init.name = pdata->dai_clk_names[i]; 2762 init.ops = &rt5682_dai_clk_ops[i]; 2763 init.flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_GATE; 2764 dai_clk_hw->init = &init; 2765 2766 dai_clk = devm_clk_register(dev, dai_clk_hw); 2767 if (IS_ERR(dai_clk)) { 2768 dev_warn(dev, "Failed to register %s: %ld\n", 2769 init.name, PTR_ERR(dai_clk)); 2770 ret = PTR_ERR(dai_clk); 2771 goto err; 2772 } 2773 rt5682->dai_clks[i] = dai_clk; 2774 2775 if (dev->of_node) { 2776 devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, 2777 dai_clk_hw); 2778 } else { 2779 dai_clk_lookup = clkdev_create(dai_clk, init.name, 2780 "%s", dev_name(dev)); 2781 if (!dai_clk_lookup) { 2782 ret = -ENOMEM; 2783 goto err; 2784 } else { 2785 rt5682->dai_clks_lookup[i] = dai_clk_lookup; 2786 } 2787 } 2788 } 2789 2790 return 0; 2791 2792 err: 2793 do { 2794 if (rt5682->dai_clks_lookup[i]) 2795 clkdev_drop(rt5682->dai_clks_lookup[i]); 2796 } while (i-- > 0); 2797 2798 return ret; 2799 } 2800 #endif /* CONFIG_COMMON_CLK */ 2801 2802 static int rt5682_probe(struct snd_soc_component *component) 2803 { 2804 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 2805 struct sdw_slave *slave; 2806 unsigned long time; 2807 2808 #ifdef CONFIG_COMMON_CLK 2809 int ret; 2810 #endif 2811 rt5682->component = component; 2812 2813 if (rt5682->is_sdw) { 2814 slave = rt5682->slave; 2815 time = wait_for_completion_timeout( 2816 &slave->initialization_complete, 2817 msecs_to_jiffies(RT5682_PROBE_TIMEOUT)); 2818 if (!time) { 2819 dev_err(&slave->dev, "Initialization not complete, timed out\n"); 2820 return -ETIMEDOUT; 2821 } 2822 } else { 2823 #ifdef CONFIG_COMMON_CLK 2824 /* Check if MCLK provided */ 2825 rt5682->mclk = devm_clk_get(component->dev, "mclk"); 2826 if (IS_ERR(rt5682->mclk)) { 2827 if (PTR_ERR(rt5682->mclk) != -ENOENT) { 2828 ret = PTR_ERR(rt5682->mclk); 2829 return ret; 2830 } 2831 rt5682->mclk = NULL; 2832 } 2833 2834 /* Register CCF DAI clock control */ 2835 ret = rt5682_register_dai_clks(component); 2836 if (ret) 2837 return ret; 2838 2839 /* Initial setup for CCF */ 2840 rt5682->lrck[RT5682_AIF1] = CLK_48; 2841 #endif 2842 } 2843 2844 return 0; 2845 } 2846 2847 static void rt5682_remove(struct snd_soc_component *component) 2848 { 2849 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 2850 2851 #ifdef CONFIG_COMMON_CLK 2852 int i; 2853 2854 for (i = RT5682_DAI_NUM_CLKS - 1; i >= 0; --i) { 2855 if (rt5682->dai_clks_lookup[i]) 2856 clkdev_drop(rt5682->dai_clks_lookup[i]); 2857 } 2858 #endif 2859 2860 rt5682_reset(rt5682); 2861 } 2862 2863 #ifdef CONFIG_PM 2864 static int rt5682_suspend(struct snd_soc_component *component) 2865 { 2866 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 2867 2868 regcache_cache_only(rt5682->regmap, true); 2869 regcache_mark_dirty(rt5682->regmap); 2870 return 0; 2871 } 2872 2873 static int rt5682_resume(struct snd_soc_component *component) 2874 { 2875 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 2876 2877 regcache_cache_only(rt5682->regmap, false); 2878 regcache_sync(rt5682->regmap); 2879 2880 mod_delayed_work(system_power_efficient_wq, 2881 &rt5682->jack_detect_work, msecs_to_jiffies(250)); 2882 2883 return 0; 2884 } 2885 #else 2886 #define rt5682_suspend NULL 2887 #define rt5682_resume NULL 2888 #endif 2889 2890 const struct snd_soc_dai_ops rt5682_aif1_dai_ops = { 2891 .hw_params = rt5682_hw_params, 2892 .set_fmt = rt5682_set_dai_fmt, 2893 .set_tdm_slot = rt5682_set_tdm_slot, 2894 .set_bclk_ratio = rt5682_set_bclk1_ratio, 2895 }; 2896 EXPORT_SYMBOL_GPL(rt5682_aif1_dai_ops); 2897 2898 const struct snd_soc_dai_ops rt5682_aif2_dai_ops = { 2899 .hw_params = rt5682_hw_params, 2900 .set_fmt = rt5682_set_dai_fmt, 2901 .set_bclk_ratio = rt5682_set_bclk2_ratio, 2902 }; 2903 EXPORT_SYMBOL_GPL(rt5682_aif2_dai_ops); 2904 2905 const struct snd_soc_component_driver rt5682_soc_component_dev = { 2906 .probe = rt5682_probe, 2907 .remove = rt5682_remove, 2908 .suspend = rt5682_suspend, 2909 .resume = rt5682_resume, 2910 .set_bias_level = rt5682_set_bias_level, 2911 .controls = rt5682_snd_controls, 2912 .num_controls = ARRAY_SIZE(rt5682_snd_controls), 2913 .dapm_widgets = rt5682_dapm_widgets, 2914 .num_dapm_widgets = ARRAY_SIZE(rt5682_dapm_widgets), 2915 .dapm_routes = rt5682_dapm_routes, 2916 .num_dapm_routes = ARRAY_SIZE(rt5682_dapm_routes), 2917 .set_sysclk = rt5682_set_component_sysclk, 2918 .set_pll = rt5682_set_component_pll, 2919 .set_jack = rt5682_set_jack_detect, 2920 .use_pmdown_time = 1, 2921 .endianness = 1, 2922 .non_legacy_dai_naming = 1, 2923 }; 2924 EXPORT_SYMBOL_GPL(rt5682_soc_component_dev); 2925 2926 int rt5682_parse_dt(struct rt5682_priv *rt5682, struct device *dev) 2927 { 2928 2929 device_property_read_u32(dev, "realtek,dmic1-data-pin", 2930 &rt5682->pdata.dmic1_data_pin); 2931 device_property_read_u32(dev, "realtek,dmic1-clk-pin", 2932 &rt5682->pdata.dmic1_clk_pin); 2933 device_property_read_u32(dev, "realtek,jd-src", 2934 &rt5682->pdata.jd_src); 2935 device_property_read_u32(dev, "realtek,btndet-delay", 2936 &rt5682->pdata.btndet_delay); 2937 device_property_read_u32(dev, "realtek,dmic-clk-rate-hz", 2938 &rt5682->pdata.dmic_clk_rate); 2939 device_property_read_u32(dev, "realtek,dmic-delay-ms", 2940 &rt5682->pdata.dmic_delay); 2941 2942 rt5682->pdata.ldo1_en = of_get_named_gpio(dev->of_node, 2943 "realtek,ldo1-en-gpios", 0); 2944 2945 if (device_property_read_string_array(dev, "clock-output-names", 2946 rt5682->pdata.dai_clk_names, 2947 RT5682_DAI_NUM_CLKS) < 0) 2948 dev_warn(dev, "Using default DAI clk names: %s, %s\n", 2949 rt5682->pdata.dai_clk_names[RT5682_DAI_WCLK_IDX], 2950 rt5682->pdata.dai_clk_names[RT5682_DAI_BCLK_IDX]); 2951 2952 return 0; 2953 } 2954 EXPORT_SYMBOL_GPL(rt5682_parse_dt); 2955 2956 void rt5682_calibrate(struct rt5682_priv *rt5682) 2957 { 2958 int value, count; 2959 2960 mutex_lock(&rt5682->calibrate_mutex); 2961 2962 rt5682_reset(rt5682); 2963 regmap_write(rt5682->regmap, RT5682_I2C_CTRL, 0x000f); 2964 regmap_write(rt5682->regmap, RT5682_PWR_ANLG_1, 0xa2af); 2965 usleep_range(15000, 20000); 2966 regmap_write(rt5682->regmap, RT5682_PWR_ANLG_1, 0xf2af); 2967 regmap_write(rt5682->regmap, RT5682_MICBIAS_2, 0x0300); 2968 regmap_write(rt5682->regmap, RT5682_GLB_CLK, 0x8000); 2969 regmap_write(rt5682->regmap, RT5682_PWR_DIG_1, 0x0100); 2970 regmap_write(rt5682->regmap, RT5682_HP_IMP_SENS_CTRL_19, 0x3800); 2971 regmap_write(rt5682->regmap, RT5682_CHOP_DAC, 0x3000); 2972 regmap_write(rt5682->regmap, RT5682_CALIB_ADC_CTRL, 0x7005); 2973 regmap_write(rt5682->regmap, RT5682_STO1_ADC_MIXER, 0x686c); 2974 regmap_write(rt5682->regmap, RT5682_CAL_REC, 0x0d0d); 2975 regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_2, 0x0321); 2976 regmap_write(rt5682->regmap, RT5682_HP_LOGIC_CTRL_2, 0x0004); 2977 regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_1, 0x7c00); 2978 regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_3, 0x06a1); 2979 regmap_write(rt5682->regmap, RT5682_A_DAC1_MUX, 0x0311); 2980 regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_1, 0x7c00); 2981 2982 regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_1, 0xfc00); 2983 2984 for (count = 0; count < 60; count++) { 2985 regmap_read(rt5682->regmap, RT5682_HP_CALIB_STA_1, &value); 2986 if (!(value & 0x8000)) 2987 break; 2988 2989 usleep_range(10000, 10005); 2990 } 2991 2992 if (count >= 60) 2993 dev_err(rt5682->component->dev, "HP Calibration Failure\n"); 2994 2995 /* restore settings */ 2996 regmap_write(rt5682->regmap, RT5682_PWR_ANLG_1, 0x02af); 2997 regmap_write(rt5682->regmap, RT5682_MICBIAS_2, 0x0080); 2998 regmap_write(rt5682->regmap, RT5682_GLB_CLK, 0x0000); 2999 regmap_write(rt5682->regmap, RT5682_PWR_DIG_1, 0x0000); 3000 regmap_write(rt5682->regmap, RT5682_CHOP_DAC, 0x2000); 3001 regmap_write(rt5682->regmap, RT5682_CALIB_ADC_CTRL, 0x2005); 3002 regmap_write(rt5682->regmap, RT5682_STO1_ADC_MIXER, 0xc0c4); 3003 3004 mutex_unlock(&rt5682->calibrate_mutex); 3005 } 3006 EXPORT_SYMBOL_GPL(rt5682_calibrate); 3007 3008 MODULE_DESCRIPTION("ASoC RT5682 driver"); 3009 MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>"); 3010 MODULE_LICENSE("GPL v2"); 3011