1 // SPDX-License-Identifier: GPL-2.0-only 2 // 3 // rt5682.c -- RT5682 ALSA SoC audio component driver 4 // 5 // Copyright 2018 Realtek Semiconductor Corp. 6 // Author: Bard Liao <bardliao@realtek.com> 7 // 8 9 #include <linux/module.h> 10 #include <linux/moduleparam.h> 11 #include <linux/init.h> 12 #include <linux/delay.h> 13 #include <linux/pm.h> 14 #include <linux/pm_runtime.h> 15 #include <linux/platform_device.h> 16 #include <linux/spi/spi.h> 17 #include <linux/acpi.h> 18 #include <linux/gpio.h> 19 #include <linux/of_gpio.h> 20 #include <linux/mutex.h> 21 #include <sound/core.h> 22 #include <sound/pcm.h> 23 #include <sound/pcm_params.h> 24 #include <sound/jack.h> 25 #include <sound/soc.h> 26 #include <sound/soc-dapm.h> 27 #include <sound/initval.h> 28 #include <sound/tlv.h> 29 #include <sound/rt5682.h> 30 31 #include "rl6231.h" 32 #include "rt5682.h" 33 34 const char *rt5682_supply_names[RT5682_NUM_SUPPLIES] = { 35 "AVDD", 36 "MICVDD", 37 "VBAT", 38 }; 39 EXPORT_SYMBOL_GPL(rt5682_supply_names); 40 41 static const struct reg_sequence patch_list[] = { 42 {RT5682_HP_IMP_SENS_CTRL_19, 0x1000}, 43 {RT5682_DAC_ADC_DIG_VOL1, 0xa020}, 44 {RT5682_I2C_CTRL, 0x000f}, 45 {RT5682_PLL2_INTERNAL, 0x8266}, 46 {RT5682_SAR_IL_CMD_1, 0x22b7}, 47 {RT5682_SAR_IL_CMD_3, 0x0365}, 48 {RT5682_SAR_IL_CMD_6, 0x0110}, 49 {RT5682_CHARGE_PUMP_1, 0x0210}, 50 {RT5682_HP_LOGIC_CTRL_2, 0x0007}, 51 {RT5682_SAR_IL_CMD_2, 0xac00}, 52 {RT5682_CBJ_CTRL_7, 0x0104}, 53 }; 54 55 void rt5682_apply_patch_list(struct rt5682_priv *rt5682, struct device *dev) 56 { 57 int ret; 58 59 ret = regmap_multi_reg_write(rt5682->regmap, patch_list, 60 ARRAY_SIZE(patch_list)); 61 if (ret) 62 dev_warn(dev, "Failed to apply regmap patch: %d\n", ret); 63 } 64 EXPORT_SYMBOL_GPL(rt5682_apply_patch_list); 65 66 const struct reg_default rt5682_reg[RT5682_REG_NUM] = { 67 {0x0002, 0x8080}, 68 {0x0003, 0x8000}, 69 {0x0005, 0x0000}, 70 {0x0006, 0x0000}, 71 {0x0008, 0x800f}, 72 {0x000b, 0x0000}, 73 {0x0010, 0x4040}, 74 {0x0011, 0x0000}, 75 {0x0012, 0x1404}, 76 {0x0013, 0x1000}, 77 {0x0014, 0xa00a}, 78 {0x0015, 0x0404}, 79 {0x0016, 0x0404}, 80 {0x0019, 0xafaf}, 81 {0x001c, 0x2f2f}, 82 {0x001f, 0x0000}, 83 {0x0022, 0x5757}, 84 {0x0023, 0x0039}, 85 {0x0024, 0x000b}, 86 {0x0026, 0xc0c4}, 87 {0x0029, 0x8080}, 88 {0x002a, 0xa0a0}, 89 {0x002b, 0x0300}, 90 {0x0030, 0x0000}, 91 {0x003c, 0x0080}, 92 {0x0044, 0x0c0c}, 93 {0x0049, 0x0000}, 94 {0x0061, 0x0000}, 95 {0x0062, 0x0000}, 96 {0x0063, 0x003f}, 97 {0x0064, 0x0000}, 98 {0x0065, 0x0000}, 99 {0x0066, 0x0030}, 100 {0x0067, 0x0000}, 101 {0x006b, 0x0000}, 102 {0x006c, 0x0000}, 103 {0x006d, 0x2200}, 104 {0x006e, 0x0a10}, 105 {0x0070, 0x8000}, 106 {0x0071, 0x8000}, 107 {0x0073, 0x0000}, 108 {0x0074, 0x0000}, 109 {0x0075, 0x0002}, 110 {0x0076, 0x0001}, 111 {0x0079, 0x0000}, 112 {0x007a, 0x0000}, 113 {0x007b, 0x0000}, 114 {0x007c, 0x0100}, 115 {0x007e, 0x0000}, 116 {0x0080, 0x0000}, 117 {0x0081, 0x0000}, 118 {0x0082, 0x0000}, 119 {0x0083, 0x0000}, 120 {0x0084, 0x0000}, 121 {0x0085, 0x0000}, 122 {0x0086, 0x0005}, 123 {0x0087, 0x0000}, 124 {0x0088, 0x0000}, 125 {0x008c, 0x0003}, 126 {0x008d, 0x0000}, 127 {0x008e, 0x0060}, 128 {0x008f, 0x1000}, 129 {0x0091, 0x0c26}, 130 {0x0092, 0x0073}, 131 {0x0093, 0x0000}, 132 {0x0094, 0x0080}, 133 {0x0098, 0x0000}, 134 {0x009a, 0x0000}, 135 {0x009b, 0x0000}, 136 {0x009c, 0x0000}, 137 {0x009d, 0x0000}, 138 {0x009e, 0x100c}, 139 {0x009f, 0x0000}, 140 {0x00a0, 0x0000}, 141 {0x00a3, 0x0002}, 142 {0x00a4, 0x0001}, 143 {0x00ae, 0x2040}, 144 {0x00af, 0x0000}, 145 {0x00b6, 0x0000}, 146 {0x00b7, 0x0000}, 147 {0x00b8, 0x0000}, 148 {0x00b9, 0x0002}, 149 {0x00be, 0x0000}, 150 {0x00c0, 0x0160}, 151 {0x00c1, 0x82a0}, 152 {0x00c2, 0x0000}, 153 {0x00d0, 0x0000}, 154 {0x00d1, 0x2244}, 155 {0x00d2, 0x3300}, 156 {0x00d3, 0x2200}, 157 {0x00d4, 0x0000}, 158 {0x00d9, 0x0009}, 159 {0x00da, 0x0000}, 160 {0x00db, 0x0000}, 161 {0x00dc, 0x00c0}, 162 {0x00dd, 0x2220}, 163 {0x00de, 0x3131}, 164 {0x00df, 0x3131}, 165 {0x00e0, 0x3131}, 166 {0x00e2, 0x0000}, 167 {0x00e3, 0x4000}, 168 {0x00e4, 0x0aa0}, 169 {0x00e5, 0x3131}, 170 {0x00e6, 0x3131}, 171 {0x00e7, 0x3131}, 172 {0x00e8, 0x3131}, 173 {0x00ea, 0xb320}, 174 {0x00eb, 0x0000}, 175 {0x00f0, 0x0000}, 176 {0x00f1, 0x00d0}, 177 {0x00f2, 0x00d0}, 178 {0x00f6, 0x0000}, 179 {0x00fa, 0x0000}, 180 {0x00fb, 0x0000}, 181 {0x00fc, 0x0000}, 182 {0x00fd, 0x0000}, 183 {0x00fe, 0x10ec}, 184 {0x00ff, 0x6530}, 185 {0x0100, 0xa0a0}, 186 {0x010b, 0x0000}, 187 {0x010c, 0xae00}, 188 {0x010d, 0xaaa0}, 189 {0x010e, 0x8aa2}, 190 {0x010f, 0x02a2}, 191 {0x0110, 0xc000}, 192 {0x0111, 0x04a2}, 193 {0x0112, 0x2800}, 194 {0x0113, 0x0000}, 195 {0x0117, 0x0100}, 196 {0x0125, 0x0410}, 197 {0x0132, 0x6026}, 198 {0x0136, 0x5555}, 199 {0x0138, 0x3700}, 200 {0x013a, 0x2000}, 201 {0x013b, 0x2000}, 202 {0x013c, 0x2005}, 203 {0x013f, 0x0000}, 204 {0x0142, 0x0000}, 205 {0x0145, 0x0002}, 206 {0x0146, 0x0000}, 207 {0x0147, 0x0000}, 208 {0x0148, 0x0000}, 209 {0x0149, 0x0000}, 210 {0x0150, 0x79a1}, 211 {0x0156, 0xaaaa}, 212 {0x0160, 0x4ec0}, 213 {0x0161, 0x0080}, 214 {0x0162, 0x0200}, 215 {0x0163, 0x0800}, 216 {0x0164, 0x0000}, 217 {0x0165, 0x0000}, 218 {0x0166, 0x0000}, 219 {0x0167, 0x000f}, 220 {0x0168, 0x000f}, 221 {0x0169, 0x0021}, 222 {0x0190, 0x413d}, 223 {0x0194, 0x0000}, 224 {0x0195, 0x0000}, 225 {0x0197, 0x0022}, 226 {0x0198, 0x0000}, 227 {0x0199, 0x0000}, 228 {0x01af, 0x0000}, 229 {0x01b0, 0x0400}, 230 {0x01b1, 0x0000}, 231 {0x01b2, 0x0000}, 232 {0x01b3, 0x0000}, 233 {0x01b4, 0x0000}, 234 {0x01b5, 0x0000}, 235 {0x01b6, 0x01c3}, 236 {0x01b7, 0x02a0}, 237 {0x01b8, 0x03e9}, 238 {0x01b9, 0x1389}, 239 {0x01ba, 0xc351}, 240 {0x01bb, 0x0009}, 241 {0x01bc, 0x0018}, 242 {0x01bd, 0x002a}, 243 {0x01be, 0x004c}, 244 {0x01bf, 0x0097}, 245 {0x01c0, 0x433d}, 246 {0x01c2, 0x0000}, 247 {0x01c3, 0x0000}, 248 {0x01c4, 0x0000}, 249 {0x01c5, 0x0000}, 250 {0x01c6, 0x0000}, 251 {0x01c7, 0x0000}, 252 {0x01c8, 0x40af}, 253 {0x01c9, 0x0702}, 254 {0x01ca, 0x0000}, 255 {0x01cb, 0x0000}, 256 {0x01cc, 0x5757}, 257 {0x01cd, 0x5757}, 258 {0x01ce, 0x5757}, 259 {0x01cf, 0x5757}, 260 {0x01d0, 0x5757}, 261 {0x01d1, 0x5757}, 262 {0x01d2, 0x5757}, 263 {0x01d3, 0x5757}, 264 {0x01d4, 0x5757}, 265 {0x01d5, 0x5757}, 266 {0x01d6, 0x0000}, 267 {0x01d7, 0x0008}, 268 {0x01d8, 0x0029}, 269 {0x01d9, 0x3333}, 270 {0x01da, 0x0000}, 271 {0x01db, 0x0004}, 272 {0x01dc, 0x0000}, 273 {0x01de, 0x7c00}, 274 {0x01df, 0x0320}, 275 {0x01e0, 0x06a1}, 276 {0x01e1, 0x0000}, 277 {0x01e2, 0x0000}, 278 {0x01e3, 0x0000}, 279 {0x01e4, 0x0000}, 280 {0x01e6, 0x0001}, 281 {0x01e7, 0x0000}, 282 {0x01e8, 0x0000}, 283 {0x01ea, 0x0000}, 284 {0x01eb, 0x0000}, 285 {0x01ec, 0x0000}, 286 {0x01ed, 0x0000}, 287 {0x01ee, 0x0000}, 288 {0x01ef, 0x0000}, 289 {0x01f0, 0x0000}, 290 {0x01f1, 0x0000}, 291 {0x01f2, 0x0000}, 292 {0x01f3, 0x0000}, 293 {0x01f4, 0x0000}, 294 {0x0210, 0x6297}, 295 {0x0211, 0xa005}, 296 {0x0212, 0x824c}, 297 {0x0213, 0xf7ff}, 298 {0x0214, 0xf24c}, 299 {0x0215, 0x0102}, 300 {0x0216, 0x00a3}, 301 {0x0217, 0x0048}, 302 {0x0218, 0xa2c0}, 303 {0x0219, 0x0400}, 304 {0x021a, 0x00c8}, 305 {0x021b, 0x00c0}, 306 {0x021c, 0x0000}, 307 {0x0250, 0x4500}, 308 {0x0251, 0x40b3}, 309 {0x0252, 0x0000}, 310 {0x0253, 0x0000}, 311 {0x0254, 0x0000}, 312 {0x0255, 0x0000}, 313 {0x0256, 0x0000}, 314 {0x0257, 0x0000}, 315 {0x0258, 0x0000}, 316 {0x0259, 0x0000}, 317 {0x025a, 0x0005}, 318 {0x0270, 0x0000}, 319 {0x02ff, 0x0110}, 320 {0x0300, 0x001f}, 321 {0x0301, 0x032c}, 322 {0x0302, 0x5f21}, 323 {0x0303, 0x4000}, 324 {0x0304, 0x4000}, 325 {0x0305, 0x06d5}, 326 {0x0306, 0x8000}, 327 {0x0307, 0x0700}, 328 {0x0310, 0x4560}, 329 {0x0311, 0xa4a8}, 330 {0x0312, 0x7418}, 331 {0x0313, 0x0000}, 332 {0x0314, 0x0006}, 333 {0x0315, 0xffff}, 334 {0x0316, 0xc400}, 335 {0x0317, 0x0000}, 336 {0x03c0, 0x7e00}, 337 {0x03c1, 0x8000}, 338 {0x03c2, 0x8000}, 339 {0x03c3, 0x8000}, 340 {0x03c4, 0x8000}, 341 {0x03c5, 0x8000}, 342 {0x03c6, 0x8000}, 343 {0x03c7, 0x8000}, 344 {0x03c8, 0x8000}, 345 {0x03c9, 0x8000}, 346 {0x03ca, 0x8000}, 347 {0x03cb, 0x8000}, 348 {0x03cc, 0x8000}, 349 {0x03d0, 0x0000}, 350 {0x03d1, 0x0000}, 351 {0x03d2, 0x0000}, 352 {0x03d3, 0x0000}, 353 {0x03d4, 0x2000}, 354 {0x03d5, 0x2000}, 355 {0x03d6, 0x0000}, 356 {0x03d7, 0x0000}, 357 {0x03d8, 0x2000}, 358 {0x03d9, 0x2000}, 359 {0x03da, 0x2000}, 360 {0x03db, 0x2000}, 361 {0x03dc, 0x0000}, 362 {0x03dd, 0x0000}, 363 {0x03de, 0x0000}, 364 {0x03df, 0x2000}, 365 {0x03e0, 0x0000}, 366 {0x03e1, 0x0000}, 367 {0x03e2, 0x0000}, 368 {0x03e3, 0x0000}, 369 {0x03e4, 0x0000}, 370 {0x03e5, 0x0000}, 371 {0x03e6, 0x0000}, 372 {0x03e7, 0x0000}, 373 {0x03e8, 0x0000}, 374 {0x03e9, 0x0000}, 375 {0x03ea, 0x0000}, 376 {0x03eb, 0x0000}, 377 {0x03ec, 0x0000}, 378 {0x03ed, 0x0000}, 379 {0x03ee, 0x0000}, 380 {0x03ef, 0x0000}, 381 {0x03f0, 0x0800}, 382 {0x03f1, 0x0800}, 383 {0x03f2, 0x0800}, 384 {0x03f3, 0x0800}, 385 }; 386 EXPORT_SYMBOL_GPL(rt5682_reg); 387 388 bool rt5682_volatile_register(struct device *dev, unsigned int reg) 389 { 390 switch (reg) { 391 case RT5682_RESET: 392 case RT5682_CBJ_CTRL_2: 393 case RT5682_INT_ST_1: 394 case RT5682_4BTN_IL_CMD_1: 395 case RT5682_AJD1_CTRL: 396 case RT5682_HP_CALIB_CTRL_1: 397 case RT5682_DEVICE_ID: 398 case RT5682_I2C_MODE: 399 case RT5682_HP_CALIB_CTRL_10: 400 case RT5682_EFUSE_CTRL_2: 401 case RT5682_JD_TOP_VC_VTRL: 402 case RT5682_HP_IMP_SENS_CTRL_19: 403 case RT5682_IL_CMD_1: 404 case RT5682_SAR_IL_CMD_2: 405 case RT5682_SAR_IL_CMD_4: 406 case RT5682_SAR_IL_CMD_10: 407 case RT5682_SAR_IL_CMD_11: 408 case RT5682_EFUSE_CTRL_6...RT5682_EFUSE_CTRL_11: 409 case RT5682_HP_CALIB_STA_1...RT5682_HP_CALIB_STA_11: 410 return true; 411 default: 412 return false; 413 } 414 } 415 EXPORT_SYMBOL_GPL(rt5682_volatile_register); 416 417 bool rt5682_readable_register(struct device *dev, unsigned int reg) 418 { 419 switch (reg) { 420 case RT5682_RESET: 421 case RT5682_VERSION_ID: 422 case RT5682_VENDOR_ID: 423 case RT5682_DEVICE_ID: 424 case RT5682_HP_CTRL_1: 425 case RT5682_HP_CTRL_2: 426 case RT5682_HPL_GAIN: 427 case RT5682_HPR_GAIN: 428 case RT5682_I2C_CTRL: 429 case RT5682_CBJ_BST_CTRL: 430 case RT5682_CBJ_CTRL_1: 431 case RT5682_CBJ_CTRL_2: 432 case RT5682_CBJ_CTRL_3: 433 case RT5682_CBJ_CTRL_4: 434 case RT5682_CBJ_CTRL_5: 435 case RT5682_CBJ_CTRL_6: 436 case RT5682_CBJ_CTRL_7: 437 case RT5682_DAC1_DIG_VOL: 438 case RT5682_STO1_ADC_DIG_VOL: 439 case RT5682_STO1_ADC_BOOST: 440 case RT5682_HP_IMP_GAIN_1: 441 case RT5682_HP_IMP_GAIN_2: 442 case RT5682_SIDETONE_CTRL: 443 case RT5682_STO1_ADC_MIXER: 444 case RT5682_AD_DA_MIXER: 445 case RT5682_STO1_DAC_MIXER: 446 case RT5682_A_DAC1_MUX: 447 case RT5682_DIG_INF2_DATA: 448 case RT5682_REC_MIXER: 449 case RT5682_CAL_REC: 450 case RT5682_ALC_BACK_GAIN: 451 case RT5682_PWR_DIG_1: 452 case RT5682_PWR_DIG_2: 453 case RT5682_PWR_ANLG_1: 454 case RT5682_PWR_ANLG_2: 455 case RT5682_PWR_ANLG_3: 456 case RT5682_PWR_MIXER: 457 case RT5682_PWR_VOL: 458 case RT5682_CLK_DET: 459 case RT5682_RESET_LPF_CTRL: 460 case RT5682_RESET_HPF_CTRL: 461 case RT5682_DMIC_CTRL_1: 462 case RT5682_I2S1_SDP: 463 case RT5682_I2S2_SDP: 464 case RT5682_ADDA_CLK_1: 465 case RT5682_ADDA_CLK_2: 466 case RT5682_I2S1_F_DIV_CTRL_1: 467 case RT5682_I2S1_F_DIV_CTRL_2: 468 case RT5682_TDM_CTRL: 469 case RT5682_TDM_ADDA_CTRL_1: 470 case RT5682_TDM_ADDA_CTRL_2: 471 case RT5682_DATA_SEL_CTRL_1: 472 case RT5682_TDM_TCON_CTRL: 473 case RT5682_GLB_CLK: 474 case RT5682_PLL_CTRL_1: 475 case RT5682_PLL_CTRL_2: 476 case RT5682_PLL_TRACK_1: 477 case RT5682_PLL_TRACK_2: 478 case RT5682_PLL_TRACK_3: 479 case RT5682_PLL_TRACK_4: 480 case RT5682_PLL_TRACK_5: 481 case RT5682_PLL_TRACK_6: 482 case RT5682_PLL_TRACK_11: 483 case RT5682_SDW_REF_CLK: 484 case RT5682_DEPOP_1: 485 case RT5682_DEPOP_2: 486 case RT5682_HP_CHARGE_PUMP_1: 487 case RT5682_HP_CHARGE_PUMP_2: 488 case RT5682_MICBIAS_1: 489 case RT5682_MICBIAS_2: 490 case RT5682_PLL_TRACK_12: 491 case RT5682_PLL_TRACK_14: 492 case RT5682_PLL2_CTRL_1: 493 case RT5682_PLL2_CTRL_2: 494 case RT5682_PLL2_CTRL_3: 495 case RT5682_PLL2_CTRL_4: 496 case RT5682_RC_CLK_CTRL: 497 case RT5682_I2S_M_CLK_CTRL_1: 498 case RT5682_I2S2_F_DIV_CTRL_1: 499 case RT5682_I2S2_F_DIV_CTRL_2: 500 case RT5682_EQ_CTRL_1: 501 case RT5682_EQ_CTRL_2: 502 case RT5682_IRQ_CTRL_1: 503 case RT5682_IRQ_CTRL_2: 504 case RT5682_IRQ_CTRL_3: 505 case RT5682_IRQ_CTRL_4: 506 case RT5682_INT_ST_1: 507 case RT5682_GPIO_CTRL_1: 508 case RT5682_GPIO_CTRL_2: 509 case RT5682_GPIO_CTRL_3: 510 case RT5682_HP_AMP_DET_CTRL_1: 511 case RT5682_HP_AMP_DET_CTRL_2: 512 case RT5682_MID_HP_AMP_DET: 513 case RT5682_LOW_HP_AMP_DET: 514 case RT5682_DELAY_BUF_CTRL: 515 case RT5682_SV_ZCD_1: 516 case RT5682_SV_ZCD_2: 517 case RT5682_IL_CMD_1: 518 case RT5682_IL_CMD_2: 519 case RT5682_IL_CMD_3: 520 case RT5682_IL_CMD_4: 521 case RT5682_IL_CMD_5: 522 case RT5682_IL_CMD_6: 523 case RT5682_4BTN_IL_CMD_1: 524 case RT5682_4BTN_IL_CMD_2: 525 case RT5682_4BTN_IL_CMD_3: 526 case RT5682_4BTN_IL_CMD_4: 527 case RT5682_4BTN_IL_CMD_5: 528 case RT5682_4BTN_IL_CMD_6: 529 case RT5682_4BTN_IL_CMD_7: 530 case RT5682_ADC_STO1_HP_CTRL_1: 531 case RT5682_ADC_STO1_HP_CTRL_2: 532 case RT5682_AJD1_CTRL: 533 case RT5682_JD1_THD: 534 case RT5682_JD2_THD: 535 case RT5682_JD_CTRL_1: 536 case RT5682_DUMMY_1: 537 case RT5682_DUMMY_2: 538 case RT5682_DUMMY_3: 539 case RT5682_DAC_ADC_DIG_VOL1: 540 case RT5682_BIAS_CUR_CTRL_2: 541 case RT5682_BIAS_CUR_CTRL_3: 542 case RT5682_BIAS_CUR_CTRL_4: 543 case RT5682_BIAS_CUR_CTRL_5: 544 case RT5682_BIAS_CUR_CTRL_6: 545 case RT5682_BIAS_CUR_CTRL_7: 546 case RT5682_BIAS_CUR_CTRL_8: 547 case RT5682_BIAS_CUR_CTRL_9: 548 case RT5682_BIAS_CUR_CTRL_10: 549 case RT5682_VREF_REC_OP_FB_CAP_CTRL: 550 case RT5682_CHARGE_PUMP_1: 551 case RT5682_DIG_IN_CTRL_1: 552 case RT5682_PAD_DRIVING_CTRL: 553 case RT5682_SOFT_RAMP_DEPOP: 554 case RT5682_CHOP_DAC: 555 case RT5682_CHOP_ADC: 556 case RT5682_CALIB_ADC_CTRL: 557 case RT5682_VOL_TEST: 558 case RT5682_SPKVDD_DET_STA: 559 case RT5682_TEST_MODE_CTRL_1: 560 case RT5682_TEST_MODE_CTRL_2: 561 case RT5682_TEST_MODE_CTRL_3: 562 case RT5682_TEST_MODE_CTRL_4: 563 case RT5682_TEST_MODE_CTRL_5: 564 case RT5682_PLL1_INTERNAL: 565 case RT5682_PLL2_INTERNAL: 566 case RT5682_STO_NG2_CTRL_1: 567 case RT5682_STO_NG2_CTRL_2: 568 case RT5682_STO_NG2_CTRL_3: 569 case RT5682_STO_NG2_CTRL_4: 570 case RT5682_STO_NG2_CTRL_5: 571 case RT5682_STO_NG2_CTRL_6: 572 case RT5682_STO_NG2_CTRL_7: 573 case RT5682_STO_NG2_CTRL_8: 574 case RT5682_STO_NG2_CTRL_9: 575 case RT5682_STO_NG2_CTRL_10: 576 case RT5682_STO1_DAC_SIL_DET: 577 case RT5682_SIL_PSV_CTRL1: 578 case RT5682_SIL_PSV_CTRL2: 579 case RT5682_SIL_PSV_CTRL3: 580 case RT5682_SIL_PSV_CTRL4: 581 case RT5682_SIL_PSV_CTRL5: 582 case RT5682_HP_IMP_SENS_CTRL_01: 583 case RT5682_HP_IMP_SENS_CTRL_02: 584 case RT5682_HP_IMP_SENS_CTRL_03: 585 case RT5682_HP_IMP_SENS_CTRL_04: 586 case RT5682_HP_IMP_SENS_CTRL_05: 587 case RT5682_HP_IMP_SENS_CTRL_06: 588 case RT5682_HP_IMP_SENS_CTRL_07: 589 case RT5682_HP_IMP_SENS_CTRL_08: 590 case RT5682_HP_IMP_SENS_CTRL_09: 591 case RT5682_HP_IMP_SENS_CTRL_10: 592 case RT5682_HP_IMP_SENS_CTRL_11: 593 case RT5682_HP_IMP_SENS_CTRL_12: 594 case RT5682_HP_IMP_SENS_CTRL_13: 595 case RT5682_HP_IMP_SENS_CTRL_14: 596 case RT5682_HP_IMP_SENS_CTRL_15: 597 case RT5682_HP_IMP_SENS_CTRL_16: 598 case RT5682_HP_IMP_SENS_CTRL_17: 599 case RT5682_HP_IMP_SENS_CTRL_18: 600 case RT5682_HP_IMP_SENS_CTRL_19: 601 case RT5682_HP_IMP_SENS_CTRL_20: 602 case RT5682_HP_IMP_SENS_CTRL_21: 603 case RT5682_HP_IMP_SENS_CTRL_22: 604 case RT5682_HP_IMP_SENS_CTRL_23: 605 case RT5682_HP_IMP_SENS_CTRL_24: 606 case RT5682_HP_IMP_SENS_CTRL_25: 607 case RT5682_HP_IMP_SENS_CTRL_26: 608 case RT5682_HP_IMP_SENS_CTRL_27: 609 case RT5682_HP_IMP_SENS_CTRL_28: 610 case RT5682_HP_IMP_SENS_CTRL_29: 611 case RT5682_HP_IMP_SENS_CTRL_30: 612 case RT5682_HP_IMP_SENS_CTRL_31: 613 case RT5682_HP_IMP_SENS_CTRL_32: 614 case RT5682_HP_IMP_SENS_CTRL_33: 615 case RT5682_HP_IMP_SENS_CTRL_34: 616 case RT5682_HP_IMP_SENS_CTRL_35: 617 case RT5682_HP_IMP_SENS_CTRL_36: 618 case RT5682_HP_IMP_SENS_CTRL_37: 619 case RT5682_HP_IMP_SENS_CTRL_38: 620 case RT5682_HP_IMP_SENS_CTRL_39: 621 case RT5682_HP_IMP_SENS_CTRL_40: 622 case RT5682_HP_IMP_SENS_CTRL_41: 623 case RT5682_HP_IMP_SENS_CTRL_42: 624 case RT5682_HP_IMP_SENS_CTRL_43: 625 case RT5682_HP_LOGIC_CTRL_1: 626 case RT5682_HP_LOGIC_CTRL_2: 627 case RT5682_HP_LOGIC_CTRL_3: 628 case RT5682_HP_CALIB_CTRL_1: 629 case RT5682_HP_CALIB_CTRL_2: 630 case RT5682_HP_CALIB_CTRL_3: 631 case RT5682_HP_CALIB_CTRL_4: 632 case RT5682_HP_CALIB_CTRL_5: 633 case RT5682_HP_CALIB_CTRL_6: 634 case RT5682_HP_CALIB_CTRL_7: 635 case RT5682_HP_CALIB_CTRL_9: 636 case RT5682_HP_CALIB_CTRL_10: 637 case RT5682_HP_CALIB_CTRL_11: 638 case RT5682_HP_CALIB_STA_1: 639 case RT5682_HP_CALIB_STA_2: 640 case RT5682_HP_CALIB_STA_3: 641 case RT5682_HP_CALIB_STA_4: 642 case RT5682_HP_CALIB_STA_5: 643 case RT5682_HP_CALIB_STA_6: 644 case RT5682_HP_CALIB_STA_7: 645 case RT5682_HP_CALIB_STA_8: 646 case RT5682_HP_CALIB_STA_9: 647 case RT5682_HP_CALIB_STA_10: 648 case RT5682_HP_CALIB_STA_11: 649 case RT5682_SAR_IL_CMD_1: 650 case RT5682_SAR_IL_CMD_2: 651 case RT5682_SAR_IL_CMD_3: 652 case RT5682_SAR_IL_CMD_4: 653 case RT5682_SAR_IL_CMD_5: 654 case RT5682_SAR_IL_CMD_6: 655 case RT5682_SAR_IL_CMD_7: 656 case RT5682_SAR_IL_CMD_8: 657 case RT5682_SAR_IL_CMD_9: 658 case RT5682_SAR_IL_CMD_10: 659 case RT5682_SAR_IL_CMD_11: 660 case RT5682_SAR_IL_CMD_12: 661 case RT5682_SAR_IL_CMD_13: 662 case RT5682_EFUSE_CTRL_1: 663 case RT5682_EFUSE_CTRL_2: 664 case RT5682_EFUSE_CTRL_3: 665 case RT5682_EFUSE_CTRL_4: 666 case RT5682_EFUSE_CTRL_5: 667 case RT5682_EFUSE_CTRL_6: 668 case RT5682_EFUSE_CTRL_7: 669 case RT5682_EFUSE_CTRL_8: 670 case RT5682_EFUSE_CTRL_9: 671 case RT5682_EFUSE_CTRL_10: 672 case RT5682_EFUSE_CTRL_11: 673 case RT5682_JD_TOP_VC_VTRL: 674 case RT5682_DRC1_CTRL_0: 675 case RT5682_DRC1_CTRL_1: 676 case RT5682_DRC1_CTRL_2: 677 case RT5682_DRC1_CTRL_3: 678 case RT5682_DRC1_CTRL_4: 679 case RT5682_DRC1_CTRL_5: 680 case RT5682_DRC1_CTRL_6: 681 case RT5682_DRC1_HARD_LMT_CTRL_1: 682 case RT5682_DRC1_HARD_LMT_CTRL_2: 683 case RT5682_DRC1_PRIV_1: 684 case RT5682_DRC1_PRIV_2: 685 case RT5682_DRC1_PRIV_3: 686 case RT5682_DRC1_PRIV_4: 687 case RT5682_DRC1_PRIV_5: 688 case RT5682_DRC1_PRIV_6: 689 case RT5682_DRC1_PRIV_7: 690 case RT5682_DRC1_PRIV_8: 691 case RT5682_EQ_AUTO_RCV_CTRL1: 692 case RT5682_EQ_AUTO_RCV_CTRL2: 693 case RT5682_EQ_AUTO_RCV_CTRL3: 694 case RT5682_EQ_AUTO_RCV_CTRL4: 695 case RT5682_EQ_AUTO_RCV_CTRL5: 696 case RT5682_EQ_AUTO_RCV_CTRL6: 697 case RT5682_EQ_AUTO_RCV_CTRL7: 698 case RT5682_EQ_AUTO_RCV_CTRL8: 699 case RT5682_EQ_AUTO_RCV_CTRL9: 700 case RT5682_EQ_AUTO_RCV_CTRL10: 701 case RT5682_EQ_AUTO_RCV_CTRL11: 702 case RT5682_EQ_AUTO_RCV_CTRL12: 703 case RT5682_EQ_AUTO_RCV_CTRL13: 704 case RT5682_ADC_L_EQ_LPF1_A1: 705 case RT5682_R_EQ_LPF1_A1: 706 case RT5682_L_EQ_LPF1_H0: 707 case RT5682_R_EQ_LPF1_H0: 708 case RT5682_L_EQ_BPF1_A1: 709 case RT5682_R_EQ_BPF1_A1: 710 case RT5682_L_EQ_BPF1_A2: 711 case RT5682_R_EQ_BPF1_A2: 712 case RT5682_L_EQ_BPF1_H0: 713 case RT5682_R_EQ_BPF1_H0: 714 case RT5682_L_EQ_BPF2_A1: 715 case RT5682_R_EQ_BPF2_A1: 716 case RT5682_L_EQ_BPF2_A2: 717 case RT5682_R_EQ_BPF2_A2: 718 case RT5682_L_EQ_BPF2_H0: 719 case RT5682_R_EQ_BPF2_H0: 720 case RT5682_L_EQ_BPF3_A1: 721 case RT5682_R_EQ_BPF3_A1: 722 case RT5682_L_EQ_BPF3_A2: 723 case RT5682_R_EQ_BPF3_A2: 724 case RT5682_L_EQ_BPF3_H0: 725 case RT5682_R_EQ_BPF3_H0: 726 case RT5682_L_EQ_BPF4_A1: 727 case RT5682_R_EQ_BPF4_A1: 728 case RT5682_L_EQ_BPF4_A2: 729 case RT5682_R_EQ_BPF4_A2: 730 case RT5682_L_EQ_BPF4_H0: 731 case RT5682_R_EQ_BPF4_H0: 732 case RT5682_L_EQ_HPF1_A1: 733 case RT5682_R_EQ_HPF1_A1: 734 case RT5682_L_EQ_HPF1_H0: 735 case RT5682_R_EQ_HPF1_H0: 736 case RT5682_L_EQ_PRE_VOL: 737 case RT5682_R_EQ_PRE_VOL: 738 case RT5682_L_EQ_POST_VOL: 739 case RT5682_R_EQ_POST_VOL: 740 case RT5682_I2C_MODE: 741 return true; 742 default: 743 return false; 744 } 745 } 746 EXPORT_SYMBOL_GPL(rt5682_readable_register); 747 748 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6525, 75, 0); 749 static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0); 750 static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0); 751 752 /* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */ 753 static const DECLARE_TLV_DB_RANGE(bst_tlv, 754 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0), 755 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0), 756 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0), 757 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0), 758 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0), 759 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0), 760 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0) 761 ); 762 763 /* Interface data select */ 764 static const char * const rt5682_data_select[] = { 765 "L/R", "R/L", "L/L", "R/R" 766 }; 767 768 static SOC_ENUM_SINGLE_DECL(rt5682_if2_adc_enum, 769 RT5682_DIG_INF2_DATA, RT5682_IF2_ADC_SEL_SFT, rt5682_data_select); 770 771 static SOC_ENUM_SINGLE_DECL(rt5682_if1_01_adc_enum, 772 RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC1_SEL_SFT, rt5682_data_select); 773 774 static SOC_ENUM_SINGLE_DECL(rt5682_if1_23_adc_enum, 775 RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC2_SEL_SFT, rt5682_data_select); 776 777 static SOC_ENUM_SINGLE_DECL(rt5682_if1_45_adc_enum, 778 RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC3_SEL_SFT, rt5682_data_select); 779 780 static SOC_ENUM_SINGLE_DECL(rt5682_if1_67_adc_enum, 781 RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC4_SEL_SFT, rt5682_data_select); 782 783 static const struct snd_kcontrol_new rt5682_if2_adc_swap_mux = 784 SOC_DAPM_ENUM("IF2 ADC Swap Mux", rt5682_if2_adc_enum); 785 786 static const struct snd_kcontrol_new rt5682_if1_01_adc_swap_mux = 787 SOC_DAPM_ENUM("IF1 01 ADC Swap Mux", rt5682_if1_01_adc_enum); 788 789 static const struct snd_kcontrol_new rt5682_if1_23_adc_swap_mux = 790 SOC_DAPM_ENUM("IF1 23 ADC Swap Mux", rt5682_if1_23_adc_enum); 791 792 static const struct snd_kcontrol_new rt5682_if1_45_adc_swap_mux = 793 SOC_DAPM_ENUM("IF1 45 ADC Swap Mux", rt5682_if1_45_adc_enum); 794 795 static const struct snd_kcontrol_new rt5682_if1_67_adc_swap_mux = 796 SOC_DAPM_ENUM("IF1 67 ADC Swap Mux", rt5682_if1_67_adc_enum); 797 798 static const char * const rt5682_dac_select[] = { 799 "IF1", "SOUND" 800 }; 801 802 static SOC_ENUM_SINGLE_DECL(rt5682_dacl_enum, 803 RT5682_AD_DA_MIXER, RT5682_DAC1_L_SEL_SFT, rt5682_dac_select); 804 805 static const struct snd_kcontrol_new rt5682_dac_l_mux = 806 SOC_DAPM_ENUM("DAC L Mux", rt5682_dacl_enum); 807 808 static SOC_ENUM_SINGLE_DECL(rt5682_dacr_enum, 809 RT5682_AD_DA_MIXER, RT5682_DAC1_R_SEL_SFT, rt5682_dac_select); 810 811 static const struct snd_kcontrol_new rt5682_dac_r_mux = 812 SOC_DAPM_ENUM("DAC R Mux", rt5682_dacr_enum); 813 814 void rt5682_reset(struct rt5682_priv *rt5682) 815 { 816 regmap_write(rt5682->regmap, RT5682_RESET, 0); 817 if (!rt5682->is_sdw) 818 regmap_write(rt5682->regmap, RT5682_I2C_MODE, 1); 819 } 820 EXPORT_SYMBOL_GPL(rt5682_reset); 821 822 /** 823 * rt5682_sel_asrc_clk_src - select ASRC clock source for a set of filters 824 * @component: SoC audio component device. 825 * @filter_mask: mask of filters. 826 * @clk_src: clock source 827 * 828 * The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5682 can 829 * only support standard 32fs or 64fs i2s format, ASRC should be enabled to 830 * support special i2s clock format such as Intel's 100fs(100 * sampling rate). 831 * ASRC function will track i2s clock and generate a corresponding system clock 832 * for codec. This function provides an API to select the clock source for a 833 * set of filters specified by the mask. And the component driver will turn on 834 * ASRC for these filters if ASRC is selected as their clock source. 835 */ 836 int rt5682_sel_asrc_clk_src(struct snd_soc_component *component, 837 unsigned int filter_mask, unsigned int clk_src) 838 { 839 switch (clk_src) { 840 case RT5682_CLK_SEL_SYS: 841 case RT5682_CLK_SEL_I2S1_ASRC: 842 case RT5682_CLK_SEL_I2S2_ASRC: 843 break; 844 845 default: 846 return -EINVAL; 847 } 848 849 if (filter_mask & RT5682_DA_STEREO1_FILTER) { 850 snd_soc_component_update_bits(component, RT5682_PLL_TRACK_2, 851 RT5682_FILTER_CLK_SEL_MASK, 852 clk_src << RT5682_FILTER_CLK_SEL_SFT); 853 } 854 855 if (filter_mask & RT5682_AD_STEREO1_FILTER) { 856 snd_soc_component_update_bits(component, RT5682_PLL_TRACK_3, 857 RT5682_FILTER_CLK_SEL_MASK, 858 clk_src << RT5682_FILTER_CLK_SEL_SFT); 859 } 860 861 return 0; 862 } 863 EXPORT_SYMBOL_GPL(rt5682_sel_asrc_clk_src); 864 865 static int rt5682_button_detect(struct snd_soc_component *component) 866 { 867 int btn_type, val; 868 869 val = snd_soc_component_read(component, RT5682_4BTN_IL_CMD_1); 870 btn_type = val & 0xfff0; 871 snd_soc_component_write(component, RT5682_4BTN_IL_CMD_1, val); 872 dev_dbg(component->dev, "%s btn_type=%x\n", __func__, btn_type); 873 snd_soc_component_update_bits(component, 874 RT5682_SAR_IL_CMD_2, 0x10, 0x10); 875 876 return btn_type; 877 } 878 879 static void rt5682_enable_push_button_irq(struct snd_soc_component *component, 880 bool enable) 881 { 882 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 883 884 if (enable) { 885 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1, 886 RT5682_SAR_BUTT_DET_MASK, RT5682_SAR_BUTT_DET_EN); 887 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_13, 888 RT5682_SAR_SOUR_MASK, RT5682_SAR_SOUR_BTN); 889 snd_soc_component_write(component, RT5682_IL_CMD_1, 0x0040); 890 snd_soc_component_update_bits(component, RT5682_4BTN_IL_CMD_2, 891 RT5682_4BTN_IL_MASK | RT5682_4BTN_IL_RST_MASK, 892 RT5682_4BTN_IL_EN | RT5682_4BTN_IL_NOR); 893 if (rt5682->is_sdw) 894 snd_soc_component_update_bits(component, 895 RT5682_IRQ_CTRL_3, 896 RT5682_IL_IRQ_MASK | RT5682_IL_IRQ_TYPE_MASK, 897 RT5682_IL_IRQ_EN | RT5682_IL_IRQ_PUL); 898 else 899 snd_soc_component_update_bits(component, 900 RT5682_IRQ_CTRL_3, RT5682_IL_IRQ_MASK, 901 RT5682_IL_IRQ_EN); 902 } else { 903 snd_soc_component_update_bits(component, RT5682_IRQ_CTRL_3, 904 RT5682_IL_IRQ_MASK, RT5682_IL_IRQ_DIS); 905 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1, 906 RT5682_SAR_BUTT_DET_MASK, RT5682_SAR_BUTT_DET_DIS); 907 snd_soc_component_update_bits(component, RT5682_4BTN_IL_CMD_2, 908 RT5682_4BTN_IL_MASK, RT5682_4BTN_IL_DIS); 909 snd_soc_component_update_bits(component, RT5682_4BTN_IL_CMD_2, 910 RT5682_4BTN_IL_RST_MASK, RT5682_4BTN_IL_RST); 911 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_13, 912 RT5682_SAR_SOUR_MASK, RT5682_SAR_SOUR_TYPE); 913 } 914 } 915 916 /** 917 * rt5682_headset_detect - Detect headset. 918 * @component: SoC audio component device. 919 * @jack_insert: Jack insert or not. 920 * 921 * Detect whether is headset or not when jack inserted. 922 * 923 * Returns detect status. 924 */ 925 int rt5682_headset_detect(struct snd_soc_component *component, int jack_insert) 926 { 927 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 928 struct snd_soc_dapm_context *dapm = &component->dapm; 929 unsigned int val, count; 930 931 if (jack_insert) { 932 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_1, 933 RT5682_PWR_VREF2 | RT5682_PWR_MB, 934 RT5682_PWR_VREF2 | RT5682_PWR_MB); 935 snd_soc_component_update_bits(component, 936 RT5682_PWR_ANLG_1, RT5682_PWR_FV2, 0); 937 usleep_range(15000, 20000); 938 snd_soc_component_update_bits(component, 939 RT5682_PWR_ANLG_1, RT5682_PWR_FV2, RT5682_PWR_FV2); 940 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_3, 941 RT5682_PWR_CBJ, RT5682_PWR_CBJ); 942 snd_soc_component_update_bits(component, 943 RT5682_HP_CHARGE_PUMP_1, 944 RT5682_OSW_L_MASK | RT5682_OSW_R_MASK, 0); 945 rt5682_enable_push_button_irq(component, false); 946 snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1, 947 RT5682_TRIG_JD_MASK, RT5682_TRIG_JD_LOW); 948 usleep_range(55000, 60000); 949 snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1, 950 RT5682_TRIG_JD_MASK, RT5682_TRIG_JD_HIGH); 951 952 count = 0; 953 val = snd_soc_component_read(component, RT5682_CBJ_CTRL_2) 954 & RT5682_JACK_TYPE_MASK; 955 while (val == 0 && count < 50) { 956 usleep_range(10000, 15000); 957 val = snd_soc_component_read(component, 958 RT5682_CBJ_CTRL_2) & RT5682_JACK_TYPE_MASK; 959 count++; 960 } 961 962 switch (val) { 963 case 0x1: 964 case 0x2: 965 rt5682->jack_type = SND_JACK_HEADSET; 966 snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1, 967 RT5682_FAST_OFF_MASK, RT5682_FAST_OFF_EN); 968 rt5682_enable_push_button_irq(component, true); 969 break; 970 default: 971 rt5682->jack_type = SND_JACK_HEADPHONE; 972 break; 973 } 974 975 snd_soc_component_update_bits(component, 976 RT5682_HP_CHARGE_PUMP_1, 977 RT5682_OSW_L_MASK | RT5682_OSW_R_MASK, 978 RT5682_OSW_L_EN | RT5682_OSW_R_EN); 979 snd_soc_component_update_bits(component, RT5682_MICBIAS_2, 980 RT5682_PWR_CLK25M_MASK | RT5682_PWR_CLK1M_MASK, 981 RT5682_PWR_CLK25M_PU | RT5682_PWR_CLK1M_PU); 982 } else { 983 rt5682_enable_push_button_irq(component, false); 984 snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1, 985 RT5682_TRIG_JD_MASK, RT5682_TRIG_JD_LOW); 986 if (!snd_soc_dapm_get_pin_status(dapm, "MICBIAS") && 987 !snd_soc_dapm_get_pin_status(dapm, "PLL1") && 988 !snd_soc_dapm_get_pin_status(dapm, "PLL2B")) 989 snd_soc_component_update_bits(component, 990 RT5682_PWR_ANLG_1, RT5682_PWR_MB, 0); 991 if (!snd_soc_dapm_get_pin_status(dapm, "Vref2") && 992 !snd_soc_dapm_get_pin_status(dapm, "PLL1") && 993 !snd_soc_dapm_get_pin_status(dapm, "PLL2B")) 994 snd_soc_component_update_bits(component, 995 RT5682_PWR_ANLG_1, RT5682_PWR_VREF2, 0); 996 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_3, 997 RT5682_PWR_CBJ, 0); 998 snd_soc_component_update_bits(component, RT5682_MICBIAS_2, 999 RT5682_PWR_CLK25M_MASK | RT5682_PWR_CLK1M_MASK, 1000 RT5682_PWR_CLK25M_PD | RT5682_PWR_CLK1M_PD); 1001 snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1, 1002 RT5682_FAST_OFF_MASK, RT5682_FAST_OFF_DIS); 1003 1004 rt5682->jack_type = 0; 1005 } 1006 1007 dev_dbg(component->dev, "jack_type = %d\n", rt5682->jack_type); 1008 return rt5682->jack_type; 1009 } 1010 EXPORT_SYMBOL_GPL(rt5682_headset_detect); 1011 1012 static int rt5682_set_jack_detect(struct snd_soc_component *component, 1013 struct snd_soc_jack *hs_jack, void *data) 1014 { 1015 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 1016 1017 rt5682->hs_jack = hs_jack; 1018 1019 if (!hs_jack) { 1020 regmap_update_bits(rt5682->regmap, RT5682_IRQ_CTRL_2, 1021 RT5682_JD1_EN_MASK, RT5682_JD1_DIS); 1022 regmap_update_bits(rt5682->regmap, RT5682_RC_CLK_CTRL, 1023 RT5682_POW_JDH | RT5682_POW_JDL, 0); 1024 cancel_delayed_work_sync(&rt5682->jack_detect_work); 1025 1026 return 0; 1027 } 1028 1029 if (!rt5682->is_sdw) { 1030 switch (rt5682->pdata.jd_src) { 1031 case RT5682_JD1: 1032 snd_soc_component_update_bits(component, 1033 RT5682_CBJ_CTRL_5, 0x0700, 0x0600); 1034 snd_soc_component_update_bits(component, 1035 RT5682_CBJ_CTRL_2, RT5682_EXT_JD_SRC, 1036 RT5682_EXT_JD_SRC_MANUAL); 1037 snd_soc_component_write(component, RT5682_CBJ_CTRL_1, 1038 0xd142); 1039 snd_soc_component_update_bits(component, 1040 RT5682_CBJ_CTRL_3, RT5682_CBJ_IN_BUF_EN, 1041 RT5682_CBJ_IN_BUF_EN); 1042 snd_soc_component_update_bits(component, 1043 RT5682_SAR_IL_CMD_1, RT5682_SAR_POW_MASK, 1044 RT5682_SAR_POW_EN); 1045 regmap_update_bits(rt5682->regmap, RT5682_GPIO_CTRL_1, 1046 RT5682_GP1_PIN_MASK, RT5682_GP1_PIN_IRQ); 1047 regmap_update_bits(rt5682->regmap, RT5682_RC_CLK_CTRL, 1048 RT5682_POW_IRQ | RT5682_POW_JDH | 1049 RT5682_POW_ANA, RT5682_POW_IRQ | 1050 RT5682_POW_JDH | RT5682_POW_ANA); 1051 regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_2, 1052 RT5682_PWR_JDH, RT5682_PWR_JDH); 1053 regmap_update_bits(rt5682->regmap, RT5682_IRQ_CTRL_2, 1054 RT5682_JD1_EN_MASK | RT5682_JD1_POL_MASK, 1055 RT5682_JD1_EN | RT5682_JD1_POL_NOR); 1056 regmap_update_bits(rt5682->regmap, RT5682_4BTN_IL_CMD_4, 1057 0x7f7f, (rt5682->pdata.btndet_delay << 8 | 1058 rt5682->pdata.btndet_delay)); 1059 regmap_update_bits(rt5682->regmap, RT5682_4BTN_IL_CMD_5, 1060 0x7f7f, (rt5682->pdata.btndet_delay << 8 | 1061 rt5682->pdata.btndet_delay)); 1062 regmap_update_bits(rt5682->regmap, RT5682_4BTN_IL_CMD_6, 1063 0x7f7f, (rt5682->pdata.btndet_delay << 8 | 1064 rt5682->pdata.btndet_delay)); 1065 regmap_update_bits(rt5682->regmap, RT5682_4BTN_IL_CMD_7, 1066 0x7f7f, (rt5682->pdata.btndet_delay << 8 | 1067 rt5682->pdata.btndet_delay)); 1068 mod_delayed_work(system_power_efficient_wq, 1069 &rt5682->jack_detect_work, 1070 msecs_to_jiffies(250)); 1071 break; 1072 1073 case RT5682_JD_NULL: 1074 regmap_update_bits(rt5682->regmap, RT5682_IRQ_CTRL_2, 1075 RT5682_JD1_EN_MASK, RT5682_JD1_DIS); 1076 regmap_update_bits(rt5682->regmap, RT5682_RC_CLK_CTRL, 1077 RT5682_POW_JDH | RT5682_POW_JDL, 0); 1078 break; 1079 1080 default: 1081 dev_warn(component->dev, "Wrong JD source\n"); 1082 break; 1083 } 1084 } 1085 1086 return 0; 1087 } 1088 1089 void rt5682_jack_detect_handler(struct work_struct *work) 1090 { 1091 struct rt5682_priv *rt5682 = 1092 container_of(work, struct rt5682_priv, jack_detect_work.work); 1093 int val, btn_type; 1094 1095 while (!rt5682->component) 1096 usleep_range(10000, 15000); 1097 1098 while (!rt5682->component->card->instantiated) 1099 usleep_range(10000, 15000); 1100 1101 mutex_lock(&rt5682->jdet_mutex); 1102 mutex_lock(&rt5682->calibrate_mutex); 1103 1104 val = snd_soc_component_read(rt5682->component, RT5682_AJD1_CTRL) 1105 & RT5682_JDH_RS_MASK; 1106 if (!val) { 1107 /* jack in */ 1108 if (rt5682->jack_type == 0) { 1109 /* jack was out, report jack type */ 1110 rt5682->jack_type = 1111 rt5682_headset_detect(rt5682->component, 1); 1112 rt5682->irq_work_delay_time = 0; 1113 } else if ((rt5682->jack_type & SND_JACK_HEADSET) == 1114 SND_JACK_HEADSET) { 1115 /* jack is already in, report button event */ 1116 rt5682->jack_type = SND_JACK_HEADSET; 1117 btn_type = rt5682_button_detect(rt5682->component); 1118 /** 1119 * rt5682 can report three kinds of button behavior, 1120 * one click, double click and hold. However, 1121 * currently we will report button pressed/released 1122 * event. So all the three button behaviors are 1123 * treated as button pressed. 1124 */ 1125 switch (btn_type) { 1126 case 0x8000: 1127 case 0x4000: 1128 case 0x2000: 1129 rt5682->jack_type |= SND_JACK_BTN_0; 1130 break; 1131 case 0x1000: 1132 case 0x0800: 1133 case 0x0400: 1134 rt5682->jack_type |= SND_JACK_BTN_1; 1135 break; 1136 case 0x0200: 1137 case 0x0100: 1138 case 0x0080: 1139 rt5682->jack_type |= SND_JACK_BTN_2; 1140 break; 1141 case 0x0040: 1142 case 0x0020: 1143 case 0x0010: 1144 rt5682->jack_type |= SND_JACK_BTN_3; 1145 break; 1146 case 0x0000: /* unpressed */ 1147 break; 1148 default: 1149 dev_err(rt5682->component->dev, 1150 "Unexpected button code 0x%04x\n", 1151 btn_type); 1152 break; 1153 } 1154 } 1155 } else { 1156 /* jack out */ 1157 rt5682->jack_type = rt5682_headset_detect(rt5682->component, 0); 1158 rt5682->irq_work_delay_time = 50; 1159 } 1160 1161 snd_soc_jack_report(rt5682->hs_jack, rt5682->jack_type, 1162 SND_JACK_HEADSET | 1163 SND_JACK_BTN_0 | SND_JACK_BTN_1 | 1164 SND_JACK_BTN_2 | SND_JACK_BTN_3); 1165 1166 if (!rt5682->is_sdw) { 1167 if (rt5682->jack_type & (SND_JACK_BTN_0 | SND_JACK_BTN_1 | 1168 SND_JACK_BTN_2 | SND_JACK_BTN_3)) 1169 schedule_delayed_work(&rt5682->jd_check_work, 0); 1170 else 1171 cancel_delayed_work_sync(&rt5682->jd_check_work); 1172 } 1173 1174 mutex_unlock(&rt5682->calibrate_mutex); 1175 mutex_unlock(&rt5682->jdet_mutex); 1176 } 1177 EXPORT_SYMBOL_GPL(rt5682_jack_detect_handler); 1178 1179 static const struct snd_kcontrol_new rt5682_snd_controls[] = { 1180 /* DAC Digital Volume */ 1181 SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5682_DAC1_DIG_VOL, 1182 RT5682_L_VOL_SFT + 1, RT5682_R_VOL_SFT + 1, 87, 0, dac_vol_tlv), 1183 1184 /* IN Boost Volume */ 1185 SOC_SINGLE_TLV("CBJ Boost Volume", RT5682_CBJ_BST_CTRL, 1186 RT5682_BST_CBJ_SFT, 8, 0, bst_tlv), 1187 1188 /* ADC Digital Volume Control */ 1189 SOC_DOUBLE("STO1 ADC Capture Switch", RT5682_STO1_ADC_DIG_VOL, 1190 RT5682_L_MUTE_SFT, RT5682_R_MUTE_SFT, 1, 1), 1191 SOC_DOUBLE_TLV("STO1 ADC Capture Volume", RT5682_STO1_ADC_DIG_VOL, 1192 RT5682_L_VOL_SFT + 1, RT5682_R_VOL_SFT + 1, 63, 0, adc_vol_tlv), 1193 1194 /* ADC Boost Volume Control */ 1195 SOC_DOUBLE_TLV("STO1 ADC Boost Gain Volume", RT5682_STO1_ADC_BOOST, 1196 RT5682_STO1_ADC_L_BST_SFT, RT5682_STO1_ADC_R_BST_SFT, 1197 3, 0, adc_bst_tlv), 1198 }; 1199 1200 static int rt5682_div_sel(struct rt5682_priv *rt5682, 1201 int target, const int div[], int size) 1202 { 1203 int i; 1204 1205 if (rt5682->sysclk < target) { 1206 dev_err(rt5682->component->dev, 1207 "sysclk rate %d is too low\n", rt5682->sysclk); 1208 return 0; 1209 } 1210 1211 for (i = 0; i < size - 1; i++) { 1212 dev_dbg(rt5682->component->dev, "div[%d]=%d\n", i, div[i]); 1213 if (target * div[i] == rt5682->sysclk) 1214 return i; 1215 if (target * div[i + 1] > rt5682->sysclk) { 1216 dev_dbg(rt5682->component->dev, 1217 "can't find div for sysclk %d\n", 1218 rt5682->sysclk); 1219 return i; 1220 } 1221 } 1222 1223 if (target * div[i] < rt5682->sysclk) 1224 dev_err(rt5682->component->dev, 1225 "sysclk rate %d is too high\n", rt5682->sysclk); 1226 1227 return size - 1; 1228 } 1229 1230 /** 1231 * set_dmic_clk - Set parameter of dmic. 1232 * 1233 * @w: DAPM widget. 1234 * @kcontrol: The kcontrol of this widget. 1235 * @event: Event id. 1236 * 1237 * Choose dmic clock between 1MHz and 3MHz. 1238 * It is better for clock to approximate 3MHz. 1239 */ 1240 static int set_dmic_clk(struct snd_soc_dapm_widget *w, 1241 struct snd_kcontrol *kcontrol, int event) 1242 { 1243 struct snd_soc_component *component = 1244 snd_soc_dapm_to_component(w->dapm); 1245 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 1246 int idx, dmic_clk_rate = 3072000; 1247 static const int div[] = {2, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, 128}; 1248 1249 if (rt5682->pdata.dmic_clk_rate) 1250 dmic_clk_rate = rt5682->pdata.dmic_clk_rate; 1251 1252 idx = rt5682_div_sel(rt5682, dmic_clk_rate, div, ARRAY_SIZE(div)); 1253 1254 snd_soc_component_update_bits(component, RT5682_DMIC_CTRL_1, 1255 RT5682_DMIC_CLK_MASK, idx << RT5682_DMIC_CLK_SFT); 1256 1257 return 0; 1258 } 1259 1260 static int set_filter_clk(struct snd_soc_dapm_widget *w, 1261 struct snd_kcontrol *kcontrol, int event) 1262 { 1263 struct snd_soc_component *component = 1264 snd_soc_dapm_to_component(w->dapm); 1265 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 1266 int ref, val, reg, idx; 1267 static const int div_f[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32, 48}; 1268 static const int div_o[] = {1, 2, 4, 6, 8, 12, 16, 24, 32, 48}; 1269 1270 if (rt5682->is_sdw) 1271 return 0; 1272 1273 val = snd_soc_component_read(component, RT5682_GPIO_CTRL_1) & 1274 RT5682_GP4_PIN_MASK; 1275 if (w->shift == RT5682_PWR_ADC_S1F_BIT && 1276 val == RT5682_GP4_PIN_ADCDAT2) 1277 ref = 256 * rt5682->lrck[RT5682_AIF2]; 1278 else 1279 ref = 256 * rt5682->lrck[RT5682_AIF1]; 1280 1281 idx = rt5682_div_sel(rt5682, ref, div_f, ARRAY_SIZE(div_f)); 1282 1283 if (w->shift == RT5682_PWR_ADC_S1F_BIT) 1284 reg = RT5682_PLL_TRACK_3; 1285 else 1286 reg = RT5682_PLL_TRACK_2; 1287 1288 snd_soc_component_update_bits(component, reg, 1289 RT5682_FILTER_CLK_DIV_MASK, idx << RT5682_FILTER_CLK_DIV_SFT); 1290 1291 /* select over sample rate */ 1292 for (idx = 0; idx < ARRAY_SIZE(div_o); idx++) { 1293 if (rt5682->sysclk <= 12288000 * div_o[idx]) 1294 break; 1295 } 1296 1297 snd_soc_component_update_bits(component, RT5682_ADDA_CLK_1, 1298 RT5682_ADC_OSR_MASK | RT5682_DAC_OSR_MASK, 1299 (idx << RT5682_ADC_OSR_SFT) | (idx << RT5682_DAC_OSR_SFT)); 1300 1301 return 0; 1302 } 1303 1304 static int is_sys_clk_from_pll1(struct snd_soc_dapm_widget *w, 1305 struct snd_soc_dapm_widget *sink) 1306 { 1307 unsigned int val; 1308 struct snd_soc_component *component = 1309 snd_soc_dapm_to_component(w->dapm); 1310 1311 val = snd_soc_component_read(component, RT5682_GLB_CLK); 1312 val &= RT5682_SCLK_SRC_MASK; 1313 if (val == RT5682_SCLK_SRC_PLL1) 1314 return 1; 1315 else 1316 return 0; 1317 } 1318 1319 static int is_sys_clk_from_pll2(struct snd_soc_dapm_widget *w, 1320 struct snd_soc_dapm_widget *sink) 1321 { 1322 unsigned int val; 1323 struct snd_soc_component *component = 1324 snd_soc_dapm_to_component(w->dapm); 1325 1326 val = snd_soc_component_read(component, RT5682_GLB_CLK); 1327 val &= RT5682_SCLK_SRC_MASK; 1328 if (val == RT5682_SCLK_SRC_PLL2) 1329 return 1; 1330 else 1331 return 0; 1332 } 1333 1334 static int is_using_asrc(struct snd_soc_dapm_widget *w, 1335 struct snd_soc_dapm_widget *sink) 1336 { 1337 unsigned int reg, shift, val; 1338 struct snd_soc_component *component = 1339 snd_soc_dapm_to_component(w->dapm); 1340 1341 switch (w->shift) { 1342 case RT5682_ADC_STO1_ASRC_SFT: 1343 reg = RT5682_PLL_TRACK_3; 1344 shift = RT5682_FILTER_CLK_SEL_SFT; 1345 break; 1346 case RT5682_DAC_STO1_ASRC_SFT: 1347 reg = RT5682_PLL_TRACK_2; 1348 shift = RT5682_FILTER_CLK_SEL_SFT; 1349 break; 1350 default: 1351 return 0; 1352 } 1353 1354 val = (snd_soc_component_read(component, reg) >> shift) & 0xf; 1355 switch (val) { 1356 case RT5682_CLK_SEL_I2S1_ASRC: 1357 case RT5682_CLK_SEL_I2S2_ASRC: 1358 return 1; 1359 default: 1360 return 0; 1361 } 1362 } 1363 1364 /* Digital Mixer */ 1365 static const struct snd_kcontrol_new rt5682_sto1_adc_l_mix[] = { 1366 SOC_DAPM_SINGLE("ADC1 Switch", RT5682_STO1_ADC_MIXER, 1367 RT5682_M_STO1_ADC_L1_SFT, 1, 1), 1368 SOC_DAPM_SINGLE("ADC2 Switch", RT5682_STO1_ADC_MIXER, 1369 RT5682_M_STO1_ADC_L2_SFT, 1, 1), 1370 }; 1371 1372 static const struct snd_kcontrol_new rt5682_sto1_adc_r_mix[] = { 1373 SOC_DAPM_SINGLE("ADC1 Switch", RT5682_STO1_ADC_MIXER, 1374 RT5682_M_STO1_ADC_R1_SFT, 1, 1), 1375 SOC_DAPM_SINGLE("ADC2 Switch", RT5682_STO1_ADC_MIXER, 1376 RT5682_M_STO1_ADC_R2_SFT, 1, 1), 1377 }; 1378 1379 static const struct snd_kcontrol_new rt5682_dac_l_mix[] = { 1380 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5682_AD_DA_MIXER, 1381 RT5682_M_ADCMIX_L_SFT, 1, 1), 1382 SOC_DAPM_SINGLE("DAC1 Switch", RT5682_AD_DA_MIXER, 1383 RT5682_M_DAC1_L_SFT, 1, 1), 1384 }; 1385 1386 static const struct snd_kcontrol_new rt5682_dac_r_mix[] = { 1387 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5682_AD_DA_MIXER, 1388 RT5682_M_ADCMIX_R_SFT, 1, 1), 1389 SOC_DAPM_SINGLE("DAC1 Switch", RT5682_AD_DA_MIXER, 1390 RT5682_M_DAC1_R_SFT, 1, 1), 1391 }; 1392 1393 static const struct snd_kcontrol_new rt5682_sto1_dac_l_mix[] = { 1394 SOC_DAPM_SINGLE("DAC L1 Switch", RT5682_STO1_DAC_MIXER, 1395 RT5682_M_DAC_L1_STO_L_SFT, 1, 1), 1396 SOC_DAPM_SINGLE("DAC R1 Switch", RT5682_STO1_DAC_MIXER, 1397 RT5682_M_DAC_R1_STO_L_SFT, 1, 1), 1398 }; 1399 1400 static const struct snd_kcontrol_new rt5682_sto1_dac_r_mix[] = { 1401 SOC_DAPM_SINGLE("DAC L1 Switch", RT5682_STO1_DAC_MIXER, 1402 RT5682_M_DAC_L1_STO_R_SFT, 1, 1), 1403 SOC_DAPM_SINGLE("DAC R1 Switch", RT5682_STO1_DAC_MIXER, 1404 RT5682_M_DAC_R1_STO_R_SFT, 1, 1), 1405 }; 1406 1407 /* Analog Input Mixer */ 1408 static const struct snd_kcontrol_new rt5682_rec1_l_mix[] = { 1409 SOC_DAPM_SINGLE("CBJ Switch", RT5682_REC_MIXER, 1410 RT5682_M_CBJ_RM1_L_SFT, 1, 1), 1411 }; 1412 1413 /* STO1 ADC1 Source */ 1414 /* MX-26 [13] [5] */ 1415 static const char * const rt5682_sto1_adc1_src[] = { 1416 "DAC MIX", "ADC" 1417 }; 1418 1419 static SOC_ENUM_SINGLE_DECL( 1420 rt5682_sto1_adc1l_enum, RT5682_STO1_ADC_MIXER, 1421 RT5682_STO1_ADC1L_SRC_SFT, rt5682_sto1_adc1_src); 1422 1423 static const struct snd_kcontrol_new rt5682_sto1_adc1l_mux = 1424 SOC_DAPM_ENUM("Stereo1 ADC1L Source", rt5682_sto1_adc1l_enum); 1425 1426 static SOC_ENUM_SINGLE_DECL( 1427 rt5682_sto1_adc1r_enum, RT5682_STO1_ADC_MIXER, 1428 RT5682_STO1_ADC1R_SRC_SFT, rt5682_sto1_adc1_src); 1429 1430 static const struct snd_kcontrol_new rt5682_sto1_adc1r_mux = 1431 SOC_DAPM_ENUM("Stereo1 ADC1L Source", rt5682_sto1_adc1r_enum); 1432 1433 /* STO1 ADC Source */ 1434 /* MX-26 [11:10] [3:2] */ 1435 static const char * const rt5682_sto1_adc_src[] = { 1436 "ADC1 L", "ADC1 R" 1437 }; 1438 1439 static SOC_ENUM_SINGLE_DECL( 1440 rt5682_sto1_adcl_enum, RT5682_STO1_ADC_MIXER, 1441 RT5682_STO1_ADCL_SRC_SFT, rt5682_sto1_adc_src); 1442 1443 static const struct snd_kcontrol_new rt5682_sto1_adcl_mux = 1444 SOC_DAPM_ENUM("Stereo1 ADCL Source", rt5682_sto1_adcl_enum); 1445 1446 static SOC_ENUM_SINGLE_DECL( 1447 rt5682_sto1_adcr_enum, RT5682_STO1_ADC_MIXER, 1448 RT5682_STO1_ADCR_SRC_SFT, rt5682_sto1_adc_src); 1449 1450 static const struct snd_kcontrol_new rt5682_sto1_adcr_mux = 1451 SOC_DAPM_ENUM("Stereo1 ADCR Source", rt5682_sto1_adcr_enum); 1452 1453 /* STO1 ADC2 Source */ 1454 /* MX-26 [12] [4] */ 1455 static const char * const rt5682_sto1_adc2_src[] = { 1456 "DAC MIX", "DMIC" 1457 }; 1458 1459 static SOC_ENUM_SINGLE_DECL( 1460 rt5682_sto1_adc2l_enum, RT5682_STO1_ADC_MIXER, 1461 RT5682_STO1_ADC2L_SRC_SFT, rt5682_sto1_adc2_src); 1462 1463 static const struct snd_kcontrol_new rt5682_sto1_adc2l_mux = 1464 SOC_DAPM_ENUM("Stereo1 ADC2L Source", rt5682_sto1_adc2l_enum); 1465 1466 static SOC_ENUM_SINGLE_DECL( 1467 rt5682_sto1_adc2r_enum, RT5682_STO1_ADC_MIXER, 1468 RT5682_STO1_ADC2R_SRC_SFT, rt5682_sto1_adc2_src); 1469 1470 static const struct snd_kcontrol_new rt5682_sto1_adc2r_mux = 1471 SOC_DAPM_ENUM("Stereo1 ADC2R Source", rt5682_sto1_adc2r_enum); 1472 1473 /* MX-79 [6:4] I2S1 ADC data location */ 1474 static const unsigned int rt5682_if1_adc_slot_values[] = { 1475 0, 1476 2, 1477 4, 1478 6, 1479 }; 1480 1481 static const char * const rt5682_if1_adc_slot_src[] = { 1482 "Slot 0", "Slot 2", "Slot 4", "Slot 6" 1483 }; 1484 1485 static SOC_VALUE_ENUM_SINGLE_DECL(rt5682_if1_adc_slot_enum, 1486 RT5682_TDM_CTRL, RT5682_TDM_ADC_LCA_SFT, RT5682_TDM_ADC_LCA_MASK, 1487 rt5682_if1_adc_slot_src, rt5682_if1_adc_slot_values); 1488 1489 static const struct snd_kcontrol_new rt5682_if1_adc_slot_mux = 1490 SOC_DAPM_ENUM("IF1 ADC Slot location", rt5682_if1_adc_slot_enum); 1491 1492 /* Analog DAC L1 Source, Analog DAC R1 Source*/ 1493 /* MX-2B [4], MX-2B [0]*/ 1494 static const char * const rt5682_alg_dac1_src[] = { 1495 "Stereo1 DAC Mixer", "DAC1" 1496 }; 1497 1498 static SOC_ENUM_SINGLE_DECL( 1499 rt5682_alg_dac_l1_enum, RT5682_A_DAC1_MUX, 1500 RT5682_A_DACL1_SFT, rt5682_alg_dac1_src); 1501 1502 static const struct snd_kcontrol_new rt5682_alg_dac_l1_mux = 1503 SOC_DAPM_ENUM("Analog DAC L1 Source", rt5682_alg_dac_l1_enum); 1504 1505 static SOC_ENUM_SINGLE_DECL( 1506 rt5682_alg_dac_r1_enum, RT5682_A_DAC1_MUX, 1507 RT5682_A_DACR1_SFT, rt5682_alg_dac1_src); 1508 1509 static const struct snd_kcontrol_new rt5682_alg_dac_r1_mux = 1510 SOC_DAPM_ENUM("Analog DAC R1 Source", rt5682_alg_dac_r1_enum); 1511 1512 /* Out Switch */ 1513 static const struct snd_kcontrol_new hpol_switch = 1514 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5682_HP_CTRL_1, 1515 RT5682_L_MUTE_SFT, 1, 1); 1516 static const struct snd_kcontrol_new hpor_switch = 1517 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5682_HP_CTRL_1, 1518 RT5682_R_MUTE_SFT, 1, 1); 1519 1520 static int rt5682_hp_event(struct snd_soc_dapm_widget *w, 1521 struct snd_kcontrol *kcontrol, int event) 1522 { 1523 struct snd_soc_component *component = 1524 snd_soc_dapm_to_component(w->dapm); 1525 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 1526 1527 switch (event) { 1528 case SND_SOC_DAPM_PRE_PMU: 1529 snd_soc_component_update_bits(component, RT5682_HP_CTRL_2, 1530 RT5682_HP_C2_DAC_AMP_MUTE, 0); 1531 snd_soc_component_update_bits(component, RT5682_HP_LOGIC_CTRL_2, 1532 RT5682_HP_LC2_SIG_SOUR2_MASK, RT5682_HP_LC2_SIG_SOUR2_REG); 1533 snd_soc_component_update_bits(component, 1534 RT5682_DEPOP_1, 0x60, 0x60); 1535 snd_soc_component_update_bits(component, 1536 RT5682_DAC_ADC_DIG_VOL1, 0x00c0, 0x0080); 1537 1538 mutex_lock(&rt5682->jdet_mutex); 1539 1540 snd_soc_component_update_bits(component, RT5682_HP_CTRL_2, 1541 RT5682_HP_C2_DAC_L_EN | RT5682_HP_C2_DAC_R_EN, 1542 RT5682_HP_C2_DAC_L_EN | RT5682_HP_C2_DAC_R_EN); 1543 usleep_range(5000, 10000); 1544 snd_soc_component_update_bits(component, RT5682_CHARGE_PUMP_1, 1545 RT5682_CP_SW_SIZE_MASK, RT5682_CP_SW_SIZE_L); 1546 1547 mutex_unlock(&rt5682->jdet_mutex); 1548 break; 1549 1550 case SND_SOC_DAPM_POST_PMD: 1551 snd_soc_component_update_bits(component, RT5682_HP_CTRL_2, 1552 RT5682_HP_C2_DAC_L_EN | RT5682_HP_C2_DAC_R_EN, 0); 1553 snd_soc_component_update_bits(component, RT5682_CHARGE_PUMP_1, 1554 RT5682_CP_SW_SIZE_MASK, RT5682_CP_SW_SIZE_M); 1555 snd_soc_component_update_bits(component, 1556 RT5682_DEPOP_1, 0x60, 0x0); 1557 snd_soc_component_update_bits(component, 1558 RT5682_DAC_ADC_DIG_VOL1, 0x00c0, 0x0000); 1559 break; 1560 } 1561 1562 return 0; 1563 } 1564 1565 static int set_dmic_power(struct snd_soc_dapm_widget *w, 1566 struct snd_kcontrol *kcontrol, int event) 1567 { 1568 struct snd_soc_component *component = 1569 snd_soc_dapm_to_component(w->dapm); 1570 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 1571 unsigned int delay = 50, val; 1572 1573 if (rt5682->pdata.dmic_delay) 1574 delay = rt5682->pdata.dmic_delay; 1575 1576 switch (event) { 1577 case SND_SOC_DAPM_POST_PMU: 1578 val = snd_soc_component_read(component, RT5682_GLB_CLK); 1579 val &= RT5682_SCLK_SRC_MASK; 1580 if (val == RT5682_SCLK_SRC_PLL1 || val == RT5682_SCLK_SRC_PLL2) 1581 snd_soc_component_update_bits(component, 1582 RT5682_PWR_ANLG_1, 1583 RT5682_PWR_VREF2 | RT5682_PWR_MB, 1584 RT5682_PWR_VREF2 | RT5682_PWR_MB); 1585 1586 /*Add delay to avoid pop noise*/ 1587 msleep(delay); 1588 break; 1589 1590 case SND_SOC_DAPM_POST_PMD: 1591 if (!rt5682->jack_type) { 1592 if (!snd_soc_dapm_get_pin_status(w->dapm, "MICBIAS")) 1593 snd_soc_component_update_bits(component, 1594 RT5682_PWR_ANLG_1, RT5682_PWR_MB, 0); 1595 if (!snd_soc_dapm_get_pin_status(w->dapm, "Vref2")) 1596 snd_soc_component_update_bits(component, 1597 RT5682_PWR_ANLG_1, RT5682_PWR_VREF2, 0); 1598 } 1599 break; 1600 } 1601 1602 return 0; 1603 } 1604 1605 static int rt5682_set_verf(struct snd_soc_dapm_widget *w, 1606 struct snd_kcontrol *kcontrol, int event) 1607 { 1608 struct snd_soc_component *component = 1609 snd_soc_dapm_to_component(w->dapm); 1610 1611 switch (event) { 1612 case SND_SOC_DAPM_PRE_PMU: 1613 switch (w->shift) { 1614 case RT5682_PWR_VREF1_BIT: 1615 snd_soc_component_update_bits(component, 1616 RT5682_PWR_ANLG_1, RT5682_PWR_FV1, 0); 1617 break; 1618 1619 case RT5682_PWR_VREF2_BIT: 1620 snd_soc_component_update_bits(component, 1621 RT5682_PWR_ANLG_1, RT5682_PWR_FV2, 0); 1622 break; 1623 } 1624 break; 1625 1626 case SND_SOC_DAPM_POST_PMU: 1627 usleep_range(15000, 20000); 1628 switch (w->shift) { 1629 case RT5682_PWR_VREF1_BIT: 1630 snd_soc_component_update_bits(component, 1631 RT5682_PWR_ANLG_1, RT5682_PWR_FV1, 1632 RT5682_PWR_FV1); 1633 break; 1634 1635 case RT5682_PWR_VREF2_BIT: 1636 snd_soc_component_update_bits(component, 1637 RT5682_PWR_ANLG_1, RT5682_PWR_FV2, 1638 RT5682_PWR_FV2); 1639 break; 1640 } 1641 break; 1642 } 1643 1644 return 0; 1645 } 1646 1647 static const unsigned int rt5682_adcdat_pin_values[] = { 1648 1, 1649 3, 1650 }; 1651 1652 static const char * const rt5682_adcdat_pin_select[] = { 1653 "ADCDAT1", 1654 "ADCDAT2", 1655 }; 1656 1657 static SOC_VALUE_ENUM_SINGLE_DECL(rt5682_adcdat_pin_enum, 1658 RT5682_GPIO_CTRL_1, RT5682_GP4_PIN_SFT, RT5682_GP4_PIN_MASK, 1659 rt5682_adcdat_pin_select, rt5682_adcdat_pin_values); 1660 1661 static const struct snd_kcontrol_new rt5682_adcdat_pin_ctrl = 1662 SOC_DAPM_ENUM("ADCDAT", rt5682_adcdat_pin_enum); 1663 1664 static const unsigned int rt5682_hpo_sig_out_values[] = { 1665 2, 1666 7, 1667 }; 1668 1669 static const char * const rt5682_hpo_sig_out_mode[] = { 1670 "Legacy", 1671 "OneBit", 1672 }; 1673 1674 static SOC_VALUE_ENUM_SINGLE_DECL(rt5682_hpo_sig_out_enum, 1675 RT5682_HP_LOGIC_CTRL_2, 0, RT5682_HP_LC2_SIG_SOUR1_MASK, 1676 rt5682_hpo_sig_out_mode, rt5682_hpo_sig_out_values); 1677 1678 static const struct snd_kcontrol_new rt5682_hpo_sig_demux = 1679 SOC_DAPM_ENUM("HPO Signal Demux", rt5682_hpo_sig_out_enum); 1680 1681 static const struct snd_soc_dapm_widget rt5682_dapm_widgets[] = { 1682 SND_SOC_DAPM_SUPPLY("LDO2", RT5682_PWR_ANLG_3, RT5682_PWR_LDO2_BIT, 1683 0, NULL, 0), 1684 SND_SOC_DAPM_SUPPLY("PLL1", RT5682_PWR_ANLG_3, RT5682_PWR_PLL_BIT, 1685 0, NULL, 0), 1686 SND_SOC_DAPM_SUPPLY("PLL2B", RT5682_PWR_ANLG_3, RT5682_PWR_PLL2B_BIT, 1687 0, NULL, 0), 1688 SND_SOC_DAPM_SUPPLY("PLL2F", RT5682_PWR_ANLG_3, RT5682_PWR_PLL2F_BIT, 1689 0, set_filter_clk, SND_SOC_DAPM_PRE_PMU), 1690 SND_SOC_DAPM_SUPPLY("Vref1", RT5682_PWR_ANLG_1, RT5682_PWR_VREF1_BIT, 0, 1691 rt5682_set_verf, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), 1692 SND_SOC_DAPM_SUPPLY("Vref2", SND_SOC_NOPM, 0, 0, NULL, 0), 1693 SND_SOC_DAPM_SUPPLY("MICBIAS", SND_SOC_NOPM, 0, 0, NULL, 0), 1694 1695 /* ASRC */ 1696 SND_SOC_DAPM_SUPPLY_S("DAC STO1 ASRC", 1, RT5682_PLL_TRACK_1, 1697 RT5682_DAC_STO1_ASRC_SFT, 0, NULL, 0), 1698 SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5682_PLL_TRACK_1, 1699 RT5682_ADC_STO1_ASRC_SFT, 0, NULL, 0), 1700 SND_SOC_DAPM_SUPPLY_S("AD ASRC", 1, RT5682_PLL_TRACK_1, 1701 RT5682_AD_ASRC_SFT, 0, NULL, 0), 1702 SND_SOC_DAPM_SUPPLY_S("DA ASRC", 1, RT5682_PLL_TRACK_1, 1703 RT5682_DA_ASRC_SFT, 0, NULL, 0), 1704 SND_SOC_DAPM_SUPPLY_S("DMIC ASRC", 1, RT5682_PLL_TRACK_1, 1705 RT5682_DMIC_ASRC_SFT, 0, NULL, 0), 1706 1707 /* Input Side */ 1708 SND_SOC_DAPM_SUPPLY("MICBIAS1", RT5682_PWR_ANLG_2, RT5682_PWR_MB1_BIT, 1709 0, NULL, 0), 1710 SND_SOC_DAPM_SUPPLY("MICBIAS2", RT5682_PWR_ANLG_2, RT5682_PWR_MB2_BIT, 1711 0, NULL, 0), 1712 1713 /* Input Lines */ 1714 SND_SOC_DAPM_INPUT("DMIC L1"), 1715 SND_SOC_DAPM_INPUT("DMIC R1"), 1716 1717 SND_SOC_DAPM_INPUT("IN1P"), 1718 1719 SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0, 1720 set_dmic_clk, SND_SOC_DAPM_PRE_PMU), 1721 SND_SOC_DAPM_SUPPLY("DMIC1 Power", RT5682_DMIC_CTRL_1, 1722 RT5682_DMIC_1_EN_SFT, 0, set_dmic_power, 1723 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 1724 1725 /* Boost */ 1726 SND_SOC_DAPM_PGA("BST1 CBJ", SND_SOC_NOPM, 1727 0, 0, NULL, 0), 1728 1729 /* REC Mixer */ 1730 SND_SOC_DAPM_MIXER("RECMIX1L", SND_SOC_NOPM, 0, 0, rt5682_rec1_l_mix, 1731 ARRAY_SIZE(rt5682_rec1_l_mix)), 1732 SND_SOC_DAPM_SUPPLY("RECMIX1L Power", RT5682_PWR_ANLG_2, 1733 RT5682_PWR_RM1_L_BIT, 0, NULL, 0), 1734 1735 /* ADCs */ 1736 SND_SOC_DAPM_ADC("ADC1 L", NULL, SND_SOC_NOPM, 0, 0), 1737 SND_SOC_DAPM_ADC("ADC1 R", NULL, SND_SOC_NOPM, 0, 0), 1738 1739 SND_SOC_DAPM_SUPPLY("ADC1 L Power", RT5682_PWR_DIG_1, 1740 RT5682_PWR_ADC_L1_BIT, 0, NULL, 0), 1741 SND_SOC_DAPM_SUPPLY("ADC1 R Power", RT5682_PWR_DIG_1, 1742 RT5682_PWR_ADC_R1_BIT, 0, NULL, 0), 1743 SND_SOC_DAPM_SUPPLY("ADC1 clock", RT5682_CHOP_ADC, 1744 RT5682_CKGEN_ADC1_SFT, 0, NULL, 0), 1745 1746 /* ADC Mux */ 1747 SND_SOC_DAPM_MUX("Stereo1 ADC L1 Mux", SND_SOC_NOPM, 0, 0, 1748 &rt5682_sto1_adc1l_mux), 1749 SND_SOC_DAPM_MUX("Stereo1 ADC R1 Mux", SND_SOC_NOPM, 0, 0, 1750 &rt5682_sto1_adc1r_mux), 1751 SND_SOC_DAPM_MUX("Stereo1 ADC L2 Mux", SND_SOC_NOPM, 0, 0, 1752 &rt5682_sto1_adc2l_mux), 1753 SND_SOC_DAPM_MUX("Stereo1 ADC R2 Mux", SND_SOC_NOPM, 0, 0, 1754 &rt5682_sto1_adc2r_mux), 1755 SND_SOC_DAPM_MUX("Stereo1 ADC L Mux", SND_SOC_NOPM, 0, 0, 1756 &rt5682_sto1_adcl_mux), 1757 SND_SOC_DAPM_MUX("Stereo1 ADC R Mux", SND_SOC_NOPM, 0, 0, 1758 &rt5682_sto1_adcr_mux), 1759 SND_SOC_DAPM_MUX("IF1_ADC Mux", SND_SOC_NOPM, 0, 0, 1760 &rt5682_if1_adc_slot_mux), 1761 1762 /* ADC Mixer */ 1763 SND_SOC_DAPM_SUPPLY("ADC Stereo1 Filter", RT5682_PWR_DIG_2, 1764 RT5682_PWR_ADC_S1F_BIT, 0, set_filter_clk, 1765 SND_SOC_DAPM_PRE_PMU), 1766 SND_SOC_DAPM_MIXER("Stereo1 ADC MIXL", RT5682_STO1_ADC_DIG_VOL, 1767 RT5682_L_MUTE_SFT, 1, rt5682_sto1_adc_l_mix, 1768 ARRAY_SIZE(rt5682_sto1_adc_l_mix)), 1769 SND_SOC_DAPM_MIXER("Stereo1 ADC MIXR", RT5682_STO1_ADC_DIG_VOL, 1770 RT5682_R_MUTE_SFT, 1, rt5682_sto1_adc_r_mix, 1771 ARRAY_SIZE(rt5682_sto1_adc_r_mix)), 1772 1773 /* ADC PGA */ 1774 SND_SOC_DAPM_PGA("Stereo1 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 1775 1776 /* Digital Interface */ 1777 SND_SOC_DAPM_SUPPLY("I2S1", RT5682_PWR_DIG_1, RT5682_PWR_I2S1_BIT, 1778 0, NULL, 0), 1779 SND_SOC_DAPM_SUPPLY("I2S2", RT5682_PWR_DIG_1, RT5682_PWR_I2S2_BIT, 1780 0, NULL, 0), 1781 SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0), 1782 SND_SOC_DAPM_PGA("IF1 DAC1 L", SND_SOC_NOPM, 0, 0, NULL, 0), 1783 SND_SOC_DAPM_PGA("IF1 DAC1 R", SND_SOC_NOPM, 0, 0, NULL, 0), 1784 SND_SOC_DAPM_PGA("SOUND DAC L", SND_SOC_NOPM, 0, 0, NULL, 0), 1785 SND_SOC_DAPM_PGA("SOUND DAC R", SND_SOC_NOPM, 0, 0, NULL, 0), 1786 1787 /* Digital Interface Select */ 1788 SND_SOC_DAPM_MUX("IF1 01 ADC Swap Mux", SND_SOC_NOPM, 0, 0, 1789 &rt5682_if1_01_adc_swap_mux), 1790 SND_SOC_DAPM_MUX("IF1 23 ADC Swap Mux", SND_SOC_NOPM, 0, 0, 1791 &rt5682_if1_23_adc_swap_mux), 1792 SND_SOC_DAPM_MUX("IF1 45 ADC Swap Mux", SND_SOC_NOPM, 0, 0, 1793 &rt5682_if1_45_adc_swap_mux), 1794 SND_SOC_DAPM_MUX("IF1 67 ADC Swap Mux", SND_SOC_NOPM, 0, 0, 1795 &rt5682_if1_67_adc_swap_mux), 1796 SND_SOC_DAPM_MUX("IF2 ADC Swap Mux", SND_SOC_NOPM, 0, 0, 1797 &rt5682_if2_adc_swap_mux), 1798 1799 SND_SOC_DAPM_MUX("ADCDAT Mux", SND_SOC_NOPM, 0, 0, 1800 &rt5682_adcdat_pin_ctrl), 1801 1802 SND_SOC_DAPM_MUX("DAC L Mux", SND_SOC_NOPM, 0, 0, 1803 &rt5682_dac_l_mux), 1804 SND_SOC_DAPM_MUX("DAC R Mux", SND_SOC_NOPM, 0, 0, 1805 &rt5682_dac_r_mux), 1806 1807 /* Audio Interface */ 1808 SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, 1809 RT5682_I2S1_SDP, RT5682_SEL_ADCDAT_SFT, 1), 1810 SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, 1811 RT5682_I2S2_SDP, RT5682_I2S2_PIN_CFG_SFT, 1), 1812 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0), 1813 SND_SOC_DAPM_AIF_IN("SDWRX", "SDW Playback", 0, SND_SOC_NOPM, 0, 0), 1814 SND_SOC_DAPM_AIF_OUT("SDWTX", "SDW Capture", 0, SND_SOC_NOPM, 0, 0), 1815 1816 /* Output Side */ 1817 /* DAC mixer before sound effect */ 1818 SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0, 1819 rt5682_dac_l_mix, ARRAY_SIZE(rt5682_dac_l_mix)), 1820 SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0, 1821 rt5682_dac_r_mix, ARRAY_SIZE(rt5682_dac_r_mix)), 1822 1823 /* DAC channel Mux */ 1824 SND_SOC_DAPM_MUX("DAC L1 Source", SND_SOC_NOPM, 0, 0, 1825 &rt5682_alg_dac_l1_mux), 1826 SND_SOC_DAPM_MUX("DAC R1 Source", SND_SOC_NOPM, 0, 0, 1827 &rt5682_alg_dac_r1_mux), 1828 1829 /* DAC Mixer */ 1830 SND_SOC_DAPM_SUPPLY("DAC Stereo1 Filter", RT5682_PWR_DIG_2, 1831 RT5682_PWR_DAC_S1F_BIT, 0, set_filter_clk, 1832 SND_SOC_DAPM_PRE_PMU), 1833 SND_SOC_DAPM_MIXER("Stereo1 DAC MIXL", SND_SOC_NOPM, 0, 0, 1834 rt5682_sto1_dac_l_mix, ARRAY_SIZE(rt5682_sto1_dac_l_mix)), 1835 SND_SOC_DAPM_MIXER("Stereo1 DAC MIXR", SND_SOC_NOPM, 0, 0, 1836 rt5682_sto1_dac_r_mix, ARRAY_SIZE(rt5682_sto1_dac_r_mix)), 1837 1838 /* DACs */ 1839 SND_SOC_DAPM_DAC("DAC L1", NULL, RT5682_PWR_DIG_1, 1840 RT5682_PWR_DAC_L1_BIT, 0), 1841 SND_SOC_DAPM_DAC("DAC R1", NULL, RT5682_PWR_DIG_1, 1842 RT5682_PWR_DAC_R1_BIT, 0), 1843 SND_SOC_DAPM_SUPPLY_S("DAC 1 Clock", 3, RT5682_CHOP_DAC, 1844 RT5682_CKGEN_DAC1_SFT, 0, NULL, 0), 1845 1846 /* HPO */ 1847 SND_SOC_DAPM_PGA_S("HP Amp", 1, SND_SOC_NOPM, 0, 0, rt5682_hp_event, 1848 SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_PRE_PMU), 1849 1850 SND_SOC_DAPM_SUPPLY("HP Amp L", RT5682_PWR_ANLG_1, 1851 RT5682_PWR_HA_L_BIT, 0, NULL, 0), 1852 SND_SOC_DAPM_SUPPLY("HP Amp R", RT5682_PWR_ANLG_1, 1853 RT5682_PWR_HA_R_BIT, 0, NULL, 0), 1854 SND_SOC_DAPM_SUPPLY_S("Charge Pump", 1, RT5682_DEPOP_1, 1855 RT5682_PUMP_EN_SFT, 0, NULL, 0), 1856 SND_SOC_DAPM_SUPPLY_S("Capless", 2, RT5682_DEPOP_1, 1857 RT5682_CAPLESS_EN_SFT, 0, NULL, 0), 1858 1859 SND_SOC_DAPM_SWITCH("HPOL Playback", SND_SOC_NOPM, 0, 0, 1860 &hpol_switch), 1861 SND_SOC_DAPM_SWITCH("HPOR Playback", SND_SOC_NOPM, 0, 0, 1862 &hpor_switch), 1863 1864 SND_SOC_DAPM_OUT_DRV("HPO Legacy", SND_SOC_NOPM, 0, 0, NULL, 0), 1865 SND_SOC_DAPM_OUT_DRV("HPO OneBit", SND_SOC_NOPM, 0, 0, NULL, 0), 1866 SND_SOC_DAPM_DEMUX("HPO Signal Demux", SND_SOC_NOPM, 0, 0, &rt5682_hpo_sig_demux), 1867 1868 /* CLK DET */ 1869 SND_SOC_DAPM_SUPPLY("CLKDET SYS", RT5682_CLK_DET, 1870 RT5682_SYS_CLK_DET_SFT, 0, NULL, 0), 1871 SND_SOC_DAPM_SUPPLY("CLKDET PLL1", RT5682_CLK_DET, 1872 RT5682_PLL1_CLK_DET_SFT, 0, NULL, 0), 1873 SND_SOC_DAPM_SUPPLY("CLKDET PLL2", RT5682_CLK_DET, 1874 RT5682_PLL2_CLK_DET_SFT, 0, NULL, 0), 1875 SND_SOC_DAPM_SUPPLY("CLKDET", RT5682_CLK_DET, 1876 RT5682_POW_CLK_DET_SFT, 0, NULL, 0), 1877 1878 /* Output Lines */ 1879 SND_SOC_DAPM_OUTPUT("HPOL"), 1880 SND_SOC_DAPM_OUTPUT("HPOR"), 1881 }; 1882 1883 static const struct snd_soc_dapm_route rt5682_dapm_routes[] = { 1884 /*PLL*/ 1885 {"ADC Stereo1 Filter", NULL, "PLL1", is_sys_clk_from_pll1}, 1886 {"ADC Stereo1 Filter", NULL, "PLL2B", is_sys_clk_from_pll2}, 1887 {"ADC Stereo1 Filter", NULL, "PLL2F", is_sys_clk_from_pll2}, 1888 {"DAC Stereo1 Filter", NULL, "PLL1", is_sys_clk_from_pll1}, 1889 {"DAC Stereo1 Filter", NULL, "PLL2B", is_sys_clk_from_pll2}, 1890 {"DAC Stereo1 Filter", NULL, "PLL2F", is_sys_clk_from_pll2}, 1891 1892 /*ASRC*/ 1893 {"ADC Stereo1 Filter", NULL, "ADC STO1 ASRC", is_using_asrc}, 1894 {"DAC Stereo1 Filter", NULL, "DAC STO1 ASRC", is_using_asrc}, 1895 {"ADC STO1 ASRC", NULL, "AD ASRC"}, 1896 {"ADC STO1 ASRC", NULL, "DA ASRC"}, 1897 {"ADC STO1 ASRC", NULL, "CLKDET"}, 1898 {"DAC STO1 ASRC", NULL, "AD ASRC"}, 1899 {"DAC STO1 ASRC", NULL, "DA ASRC"}, 1900 {"DAC STO1 ASRC", NULL, "CLKDET"}, 1901 1902 /*Vref*/ 1903 {"MICBIAS1", NULL, "Vref1"}, 1904 {"MICBIAS2", NULL, "Vref1"}, 1905 1906 {"CLKDET SYS", NULL, "CLKDET"}, 1907 1908 {"BST1 CBJ", NULL, "IN1P"}, 1909 1910 {"RECMIX1L", "CBJ Switch", "BST1 CBJ"}, 1911 {"RECMIX1L", NULL, "RECMIX1L Power"}, 1912 1913 {"ADC1 L", NULL, "RECMIX1L"}, 1914 {"ADC1 L", NULL, "ADC1 L Power"}, 1915 {"ADC1 L", NULL, "ADC1 clock"}, 1916 1917 {"DMIC L1", NULL, "DMIC CLK"}, 1918 {"DMIC L1", NULL, "DMIC1 Power"}, 1919 {"DMIC R1", NULL, "DMIC CLK"}, 1920 {"DMIC R1", NULL, "DMIC1 Power"}, 1921 {"DMIC CLK", NULL, "DMIC ASRC"}, 1922 1923 {"Stereo1 ADC L Mux", "ADC1 L", "ADC1 L"}, 1924 {"Stereo1 ADC L Mux", "ADC1 R", "ADC1 R"}, 1925 {"Stereo1 ADC R Mux", "ADC1 L", "ADC1 L"}, 1926 {"Stereo1 ADC R Mux", "ADC1 R", "ADC1 R"}, 1927 1928 {"Stereo1 ADC L1 Mux", "ADC", "Stereo1 ADC L Mux"}, 1929 {"Stereo1 ADC L1 Mux", "DAC MIX", "Stereo1 DAC MIXL"}, 1930 {"Stereo1 ADC L2 Mux", "DMIC", "DMIC L1"}, 1931 {"Stereo1 ADC L2 Mux", "DAC MIX", "Stereo1 DAC MIXL"}, 1932 1933 {"Stereo1 ADC R1 Mux", "ADC", "Stereo1 ADC R Mux"}, 1934 {"Stereo1 ADC R1 Mux", "DAC MIX", "Stereo1 DAC MIXR"}, 1935 {"Stereo1 ADC R2 Mux", "DMIC", "DMIC R1"}, 1936 {"Stereo1 ADC R2 Mux", "DAC MIX", "Stereo1 DAC MIXR"}, 1937 1938 {"Stereo1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC L1 Mux"}, 1939 {"Stereo1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC L2 Mux"}, 1940 {"Stereo1 ADC MIXL", NULL, "ADC Stereo1 Filter"}, 1941 1942 {"Stereo1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC R1 Mux"}, 1943 {"Stereo1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC R2 Mux"}, 1944 {"Stereo1 ADC MIXR", NULL, "ADC Stereo1 Filter"}, 1945 1946 {"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXL"}, 1947 {"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXR"}, 1948 1949 {"IF1 01 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"}, 1950 {"IF1 01 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"}, 1951 {"IF1 01 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"}, 1952 {"IF1 01 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"}, 1953 {"IF1 23 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"}, 1954 {"IF1 23 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"}, 1955 {"IF1 23 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"}, 1956 {"IF1 23 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"}, 1957 {"IF1 45 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"}, 1958 {"IF1 45 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"}, 1959 {"IF1 45 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"}, 1960 {"IF1 45 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"}, 1961 {"IF1 67 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"}, 1962 {"IF1 67 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"}, 1963 {"IF1 67 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"}, 1964 {"IF1 67 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"}, 1965 1966 {"IF1_ADC Mux", "Slot 0", "IF1 01 ADC Swap Mux"}, 1967 {"IF1_ADC Mux", "Slot 2", "IF1 23 ADC Swap Mux"}, 1968 {"IF1_ADC Mux", "Slot 4", "IF1 45 ADC Swap Mux"}, 1969 {"IF1_ADC Mux", "Slot 6", "IF1 67 ADC Swap Mux"}, 1970 {"ADCDAT Mux", "ADCDAT1", "IF1_ADC Mux"}, 1971 {"AIF1TX", NULL, "I2S1"}, 1972 {"AIF1TX", NULL, "ADCDAT Mux"}, 1973 {"IF2 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"}, 1974 {"IF2 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"}, 1975 {"IF2 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"}, 1976 {"IF2 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"}, 1977 {"ADCDAT Mux", "ADCDAT2", "IF2 ADC Swap Mux"}, 1978 {"AIF2TX", NULL, "ADCDAT Mux"}, 1979 1980 {"SDWTX", NULL, "PLL2B"}, 1981 {"SDWTX", NULL, "PLL2F"}, 1982 {"SDWTX", NULL, "ADCDAT Mux"}, 1983 1984 {"IF1 DAC1 L", NULL, "AIF1RX"}, 1985 {"IF1 DAC1 L", NULL, "I2S1"}, 1986 {"IF1 DAC1 L", NULL, "DAC Stereo1 Filter"}, 1987 {"IF1 DAC1 R", NULL, "AIF1RX"}, 1988 {"IF1 DAC1 R", NULL, "I2S1"}, 1989 {"IF1 DAC1 R", NULL, "DAC Stereo1 Filter"}, 1990 1991 {"SOUND DAC L", NULL, "SDWRX"}, 1992 {"SOUND DAC L", NULL, "DAC Stereo1 Filter"}, 1993 {"SOUND DAC L", NULL, "PLL2B"}, 1994 {"SOUND DAC L", NULL, "PLL2F"}, 1995 {"SOUND DAC R", NULL, "SDWRX"}, 1996 {"SOUND DAC R", NULL, "DAC Stereo1 Filter"}, 1997 {"SOUND DAC R", NULL, "PLL2B"}, 1998 {"SOUND DAC R", NULL, "PLL2F"}, 1999 2000 {"DAC L Mux", "IF1", "IF1 DAC1 L"}, 2001 {"DAC L Mux", "SOUND", "SOUND DAC L"}, 2002 {"DAC R Mux", "IF1", "IF1 DAC1 R"}, 2003 {"DAC R Mux", "SOUND", "SOUND DAC R"}, 2004 2005 {"DAC1 MIXL", "Stereo ADC Switch", "Stereo1 ADC MIXL"}, 2006 {"DAC1 MIXL", "DAC1 Switch", "DAC L Mux"}, 2007 {"DAC1 MIXR", "Stereo ADC Switch", "Stereo1 ADC MIXR"}, 2008 {"DAC1 MIXR", "DAC1 Switch", "DAC R Mux"}, 2009 2010 {"Stereo1 DAC MIXL", "DAC L1 Switch", "DAC1 MIXL"}, 2011 {"Stereo1 DAC MIXL", "DAC R1 Switch", "DAC1 MIXR"}, 2012 2013 {"Stereo1 DAC MIXR", "DAC R1 Switch", "DAC1 MIXR"}, 2014 {"Stereo1 DAC MIXR", "DAC L1 Switch", "DAC1 MIXL"}, 2015 2016 {"DAC L1 Source", "DAC1", "DAC1 MIXL"}, 2017 {"DAC L1 Source", "Stereo1 DAC Mixer", "Stereo1 DAC MIXL"}, 2018 {"DAC R1 Source", "DAC1", "DAC1 MIXR"}, 2019 {"DAC R1 Source", "Stereo1 DAC Mixer", "Stereo1 DAC MIXR"}, 2020 2021 {"DAC L1", NULL, "DAC L1 Source"}, 2022 {"DAC R1", NULL, "DAC R1 Source"}, 2023 2024 {"DAC L1", NULL, "DAC 1 Clock"}, 2025 {"DAC R1", NULL, "DAC 1 Clock"}, 2026 2027 {"HP Amp", NULL, "DAC L1"}, 2028 {"HP Amp", NULL, "DAC R1"}, 2029 {"HP Amp", NULL, "HP Amp L"}, 2030 {"HP Amp", NULL, "HP Amp R"}, 2031 {"HP Amp", NULL, "Capless"}, 2032 {"HP Amp", NULL, "Charge Pump"}, 2033 {"HP Amp", NULL, "CLKDET SYS"}, 2034 {"HP Amp", NULL, "Vref1"}, 2035 2036 {"HPO Signal Demux", NULL, "HP Amp"}, 2037 2038 {"HPO Legacy", "Legacy", "HPO Signal Demux"}, 2039 {"HPO OneBit", "OneBit", "HPO Signal Demux"}, 2040 2041 {"HPOL Playback", "Switch", "HPO Legacy"}, 2042 {"HPOR Playback", "Switch", "HPO Legacy"}, 2043 2044 {"HPOL", NULL, "HPOL Playback"}, 2045 {"HPOR", NULL, "HPOR Playback"}, 2046 {"HPOL", NULL, "HPO OneBit"}, 2047 {"HPOR", NULL, "HPO OneBit"}, 2048 }; 2049 2050 static int rt5682_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask, 2051 unsigned int rx_mask, int slots, int slot_width) 2052 { 2053 struct snd_soc_component *component = dai->component; 2054 unsigned int cl, val = 0; 2055 2056 if (tx_mask || rx_mask) 2057 snd_soc_component_update_bits(component, RT5682_TDM_ADDA_CTRL_2, 2058 RT5682_TDM_EN, RT5682_TDM_EN); 2059 else 2060 snd_soc_component_update_bits(component, RT5682_TDM_ADDA_CTRL_2, 2061 RT5682_TDM_EN, 0); 2062 2063 switch (slots) { 2064 case 4: 2065 val |= RT5682_TDM_TX_CH_4; 2066 val |= RT5682_TDM_RX_CH_4; 2067 break; 2068 case 6: 2069 val |= RT5682_TDM_TX_CH_6; 2070 val |= RT5682_TDM_RX_CH_6; 2071 break; 2072 case 8: 2073 val |= RT5682_TDM_TX_CH_8; 2074 val |= RT5682_TDM_RX_CH_8; 2075 break; 2076 case 2: 2077 break; 2078 default: 2079 return -EINVAL; 2080 } 2081 2082 snd_soc_component_update_bits(component, RT5682_TDM_CTRL, 2083 RT5682_TDM_TX_CH_MASK | RT5682_TDM_RX_CH_MASK, val); 2084 2085 switch (slot_width) { 2086 case 8: 2087 if (tx_mask || rx_mask) 2088 return -EINVAL; 2089 cl = RT5682_I2S1_TX_CHL_8 | RT5682_I2S1_RX_CHL_8; 2090 break; 2091 case 16: 2092 val = RT5682_TDM_CL_16; 2093 cl = RT5682_I2S1_TX_CHL_16 | RT5682_I2S1_RX_CHL_16; 2094 break; 2095 case 20: 2096 val = RT5682_TDM_CL_20; 2097 cl = RT5682_I2S1_TX_CHL_20 | RT5682_I2S1_RX_CHL_20; 2098 break; 2099 case 24: 2100 val = RT5682_TDM_CL_24; 2101 cl = RT5682_I2S1_TX_CHL_24 | RT5682_I2S1_RX_CHL_24; 2102 break; 2103 case 32: 2104 val = RT5682_TDM_CL_32; 2105 cl = RT5682_I2S1_TX_CHL_32 | RT5682_I2S1_RX_CHL_32; 2106 break; 2107 default: 2108 return -EINVAL; 2109 } 2110 2111 snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL, 2112 RT5682_TDM_CL_MASK, val); 2113 snd_soc_component_update_bits(component, RT5682_I2S1_SDP, 2114 RT5682_I2S1_TX_CHL_MASK | RT5682_I2S1_RX_CHL_MASK, cl); 2115 2116 return 0; 2117 } 2118 2119 static int rt5682_hw_params(struct snd_pcm_substream *substream, 2120 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) 2121 { 2122 struct snd_soc_component *component = dai->component; 2123 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 2124 unsigned int len_1 = 0, len_2 = 0; 2125 int pre_div, frame_size; 2126 2127 rt5682->lrck[dai->id] = params_rate(params); 2128 pre_div = rl6231_get_clk_info(rt5682->sysclk, rt5682->lrck[dai->id]); 2129 2130 frame_size = snd_soc_params_to_frame_size(params); 2131 if (frame_size < 0) { 2132 dev_err(component->dev, "Unsupported frame size: %d\n", 2133 frame_size); 2134 return -EINVAL; 2135 } 2136 2137 dev_dbg(dai->dev, "lrck is %dHz and pre_div is %d for iis %d\n", 2138 rt5682->lrck[dai->id], pre_div, dai->id); 2139 2140 switch (params_width(params)) { 2141 case 16: 2142 break; 2143 case 20: 2144 len_1 |= RT5682_I2S1_DL_20; 2145 len_2 |= RT5682_I2S2_DL_20; 2146 break; 2147 case 24: 2148 len_1 |= RT5682_I2S1_DL_24; 2149 len_2 |= RT5682_I2S2_DL_24; 2150 break; 2151 case 32: 2152 len_1 |= RT5682_I2S1_DL_32; 2153 len_2 |= RT5682_I2S2_DL_24; 2154 break; 2155 case 8: 2156 len_1 |= RT5682_I2S2_DL_8; 2157 len_2 |= RT5682_I2S2_DL_8; 2158 break; 2159 default: 2160 return -EINVAL; 2161 } 2162 2163 switch (dai->id) { 2164 case RT5682_AIF1: 2165 snd_soc_component_update_bits(component, RT5682_I2S1_SDP, 2166 RT5682_I2S1_DL_MASK, len_1); 2167 if (rt5682->master[RT5682_AIF1]) { 2168 snd_soc_component_update_bits(component, 2169 RT5682_ADDA_CLK_1, RT5682_I2S_M_DIV_MASK | 2170 RT5682_I2S_CLK_SRC_MASK, 2171 pre_div << RT5682_I2S_M_DIV_SFT | 2172 (rt5682->sysclk_src) << RT5682_I2S_CLK_SRC_SFT); 2173 } 2174 if (params_channels(params) == 1) /* mono mode */ 2175 snd_soc_component_update_bits(component, 2176 RT5682_I2S1_SDP, RT5682_I2S1_MONO_MASK, 2177 RT5682_I2S1_MONO_EN); 2178 else 2179 snd_soc_component_update_bits(component, 2180 RT5682_I2S1_SDP, RT5682_I2S1_MONO_MASK, 2181 RT5682_I2S1_MONO_DIS); 2182 break; 2183 case RT5682_AIF2: 2184 snd_soc_component_update_bits(component, RT5682_I2S2_SDP, 2185 RT5682_I2S2_DL_MASK, len_2); 2186 if (rt5682->master[RT5682_AIF2]) { 2187 snd_soc_component_update_bits(component, 2188 RT5682_I2S_M_CLK_CTRL_1, RT5682_I2S2_M_PD_MASK, 2189 pre_div << RT5682_I2S2_M_PD_SFT); 2190 } 2191 if (params_channels(params) == 1) /* mono mode */ 2192 snd_soc_component_update_bits(component, 2193 RT5682_I2S2_SDP, RT5682_I2S2_MONO_MASK, 2194 RT5682_I2S2_MONO_EN); 2195 else 2196 snd_soc_component_update_bits(component, 2197 RT5682_I2S2_SDP, RT5682_I2S2_MONO_MASK, 2198 RT5682_I2S2_MONO_DIS); 2199 break; 2200 default: 2201 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id); 2202 return -EINVAL; 2203 } 2204 2205 return 0; 2206 } 2207 2208 static int rt5682_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) 2209 { 2210 struct snd_soc_component *component = dai->component; 2211 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 2212 unsigned int reg_val = 0, tdm_ctrl = 0; 2213 2214 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 2215 case SND_SOC_DAIFMT_CBM_CFM: 2216 rt5682->master[dai->id] = 1; 2217 break; 2218 case SND_SOC_DAIFMT_CBS_CFS: 2219 rt5682->master[dai->id] = 0; 2220 break; 2221 default: 2222 return -EINVAL; 2223 } 2224 2225 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 2226 case SND_SOC_DAIFMT_NB_NF: 2227 break; 2228 case SND_SOC_DAIFMT_IB_NF: 2229 reg_val |= RT5682_I2S_BP_INV; 2230 tdm_ctrl |= RT5682_TDM_S_BP_INV; 2231 break; 2232 case SND_SOC_DAIFMT_NB_IF: 2233 if (dai->id == RT5682_AIF1) 2234 tdm_ctrl |= RT5682_TDM_S_LP_INV | RT5682_TDM_M_BP_INV; 2235 else 2236 return -EINVAL; 2237 break; 2238 case SND_SOC_DAIFMT_IB_IF: 2239 if (dai->id == RT5682_AIF1) 2240 tdm_ctrl |= RT5682_TDM_S_BP_INV | RT5682_TDM_S_LP_INV | 2241 RT5682_TDM_M_BP_INV | RT5682_TDM_M_LP_INV; 2242 else 2243 return -EINVAL; 2244 break; 2245 default: 2246 return -EINVAL; 2247 } 2248 2249 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 2250 case SND_SOC_DAIFMT_I2S: 2251 break; 2252 case SND_SOC_DAIFMT_LEFT_J: 2253 reg_val |= RT5682_I2S_DF_LEFT; 2254 tdm_ctrl |= RT5682_TDM_DF_LEFT; 2255 break; 2256 case SND_SOC_DAIFMT_DSP_A: 2257 reg_val |= RT5682_I2S_DF_PCM_A; 2258 tdm_ctrl |= RT5682_TDM_DF_PCM_A; 2259 break; 2260 case SND_SOC_DAIFMT_DSP_B: 2261 reg_val |= RT5682_I2S_DF_PCM_B; 2262 tdm_ctrl |= RT5682_TDM_DF_PCM_B; 2263 break; 2264 default: 2265 return -EINVAL; 2266 } 2267 2268 switch (dai->id) { 2269 case RT5682_AIF1: 2270 snd_soc_component_update_bits(component, RT5682_I2S1_SDP, 2271 RT5682_I2S_DF_MASK, reg_val); 2272 snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL, 2273 RT5682_TDM_MS_MASK | RT5682_TDM_S_BP_MASK | 2274 RT5682_TDM_DF_MASK | RT5682_TDM_M_BP_MASK | 2275 RT5682_TDM_M_LP_MASK | RT5682_TDM_S_LP_MASK, 2276 tdm_ctrl | rt5682->master[dai->id]); 2277 break; 2278 case RT5682_AIF2: 2279 if (rt5682->master[dai->id] == 0) 2280 reg_val |= RT5682_I2S2_MS_S; 2281 snd_soc_component_update_bits(component, RT5682_I2S2_SDP, 2282 RT5682_I2S2_MS_MASK | RT5682_I2S_BP_MASK | 2283 RT5682_I2S_DF_MASK, reg_val); 2284 break; 2285 default: 2286 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id); 2287 return -EINVAL; 2288 } 2289 return 0; 2290 } 2291 2292 static int rt5682_set_component_sysclk(struct snd_soc_component *component, 2293 int clk_id, int source, unsigned int freq, int dir) 2294 { 2295 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 2296 unsigned int reg_val = 0, src = 0; 2297 2298 if (freq == rt5682->sysclk && clk_id == rt5682->sysclk_src) 2299 return 0; 2300 2301 switch (clk_id) { 2302 case RT5682_SCLK_S_MCLK: 2303 reg_val |= RT5682_SCLK_SRC_MCLK; 2304 src = RT5682_CLK_SRC_MCLK; 2305 break; 2306 case RT5682_SCLK_S_PLL1: 2307 reg_val |= RT5682_SCLK_SRC_PLL1; 2308 src = RT5682_CLK_SRC_PLL1; 2309 break; 2310 case RT5682_SCLK_S_PLL2: 2311 reg_val |= RT5682_SCLK_SRC_PLL2; 2312 src = RT5682_CLK_SRC_PLL2; 2313 break; 2314 case RT5682_SCLK_S_RCCLK: 2315 reg_val |= RT5682_SCLK_SRC_RCCLK; 2316 src = RT5682_CLK_SRC_RCCLK; 2317 break; 2318 default: 2319 dev_err(component->dev, "Invalid clock id (%d)\n", clk_id); 2320 return -EINVAL; 2321 } 2322 snd_soc_component_update_bits(component, RT5682_GLB_CLK, 2323 RT5682_SCLK_SRC_MASK, reg_val); 2324 2325 if (rt5682->master[RT5682_AIF2]) { 2326 snd_soc_component_update_bits(component, 2327 RT5682_I2S_M_CLK_CTRL_1, RT5682_I2S2_SRC_MASK, 2328 src << RT5682_I2S2_SRC_SFT); 2329 } 2330 2331 rt5682->sysclk = freq; 2332 rt5682->sysclk_src = clk_id; 2333 2334 dev_dbg(component->dev, "Sysclk is %dHz and clock id is %d\n", 2335 freq, clk_id); 2336 2337 return 0; 2338 } 2339 2340 static int rt5682_set_component_pll(struct snd_soc_component *component, 2341 int pll_id, int source, unsigned int freq_in, 2342 unsigned int freq_out) 2343 { 2344 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 2345 struct rl6231_pll_code pll_code, pll2f_code, pll2b_code; 2346 unsigned int pll2_fout1, pll2_ps_val; 2347 int ret; 2348 2349 if (source == rt5682->pll_src[pll_id] && 2350 freq_in == rt5682->pll_in[pll_id] && 2351 freq_out == rt5682->pll_out[pll_id]) 2352 return 0; 2353 2354 if (!freq_in || !freq_out) { 2355 dev_dbg(component->dev, "PLL disabled\n"); 2356 2357 rt5682->pll_in[pll_id] = 0; 2358 rt5682->pll_out[pll_id] = 0; 2359 snd_soc_component_update_bits(component, RT5682_GLB_CLK, 2360 RT5682_SCLK_SRC_MASK, RT5682_SCLK_SRC_MCLK); 2361 return 0; 2362 } 2363 2364 if (pll_id == RT5682_PLL2) { 2365 switch (source) { 2366 case RT5682_PLL2_S_MCLK: 2367 snd_soc_component_update_bits(component, 2368 RT5682_GLB_CLK, RT5682_PLL2_SRC_MASK, 2369 RT5682_PLL2_SRC_MCLK); 2370 break; 2371 default: 2372 dev_err(component->dev, "Unknown PLL2 Source %d\n", 2373 source); 2374 return -EINVAL; 2375 } 2376 2377 /** 2378 * PLL2 concatenates 2 PLL units. 2379 * We suggest the Fout of the front PLL is 3.84MHz. 2380 */ 2381 pll2_fout1 = 3840000; 2382 ret = rl6231_pll_calc(freq_in, pll2_fout1, &pll2f_code); 2383 if (ret < 0) { 2384 dev_err(component->dev, "Unsupported input clock %d\n", 2385 freq_in); 2386 return ret; 2387 } 2388 dev_dbg(component->dev, "PLL2F: fin=%d fout=%d bypass=%d m=%d n=%d k=%d\n", 2389 freq_in, pll2_fout1, 2390 pll2f_code.m_bp, 2391 (pll2f_code.m_bp ? 0 : pll2f_code.m_code), 2392 pll2f_code.n_code, pll2f_code.k_code); 2393 2394 ret = rl6231_pll_calc(pll2_fout1, freq_out, &pll2b_code); 2395 if (ret < 0) { 2396 dev_err(component->dev, "Unsupported input clock %d\n", 2397 pll2_fout1); 2398 return ret; 2399 } 2400 dev_dbg(component->dev, "PLL2B: fin=%d fout=%d bypass=%d m=%d n=%d k=%d\n", 2401 pll2_fout1, freq_out, 2402 pll2b_code.m_bp, 2403 (pll2b_code.m_bp ? 0 : pll2b_code.m_code), 2404 pll2b_code.n_code, pll2b_code.k_code); 2405 2406 snd_soc_component_write(component, RT5682_PLL2_CTRL_1, 2407 pll2f_code.k_code << RT5682_PLL2F_K_SFT | 2408 pll2b_code.k_code << RT5682_PLL2B_K_SFT | 2409 pll2b_code.m_code); 2410 snd_soc_component_write(component, RT5682_PLL2_CTRL_2, 2411 pll2f_code.m_code << RT5682_PLL2F_M_SFT | 2412 pll2b_code.n_code); 2413 snd_soc_component_write(component, RT5682_PLL2_CTRL_3, 2414 pll2f_code.n_code << RT5682_PLL2F_N_SFT); 2415 2416 if (freq_out == 22579200) 2417 pll2_ps_val = 1 << RT5682_PLL2B_SEL_PS_SFT; 2418 else 2419 pll2_ps_val = 1 << RT5682_PLL2B_PS_BYP_SFT; 2420 snd_soc_component_update_bits(component, RT5682_PLL2_CTRL_4, 2421 RT5682_PLL2B_SEL_PS_MASK | RT5682_PLL2B_PS_BYP_MASK | 2422 RT5682_PLL2B_M_BP_MASK | RT5682_PLL2F_M_BP_MASK | 0xf, 2423 pll2_ps_val | 2424 (pll2b_code.m_bp ? 1 : 0) << RT5682_PLL2B_M_BP_SFT | 2425 (pll2f_code.m_bp ? 1 : 0) << RT5682_PLL2F_M_BP_SFT | 2426 0xf); 2427 } else { 2428 switch (source) { 2429 case RT5682_PLL1_S_MCLK: 2430 snd_soc_component_update_bits(component, 2431 RT5682_GLB_CLK, RT5682_PLL1_SRC_MASK, 2432 RT5682_PLL1_SRC_MCLK); 2433 break; 2434 case RT5682_PLL1_S_BCLK1: 2435 snd_soc_component_update_bits(component, 2436 RT5682_GLB_CLK, RT5682_PLL1_SRC_MASK, 2437 RT5682_PLL1_SRC_BCLK1); 2438 break; 2439 default: 2440 dev_err(component->dev, "Unknown PLL1 Source %d\n", 2441 source); 2442 return -EINVAL; 2443 } 2444 2445 ret = rl6231_pll_calc(freq_in, freq_out, &pll_code); 2446 if (ret < 0) { 2447 dev_err(component->dev, "Unsupported input clock %d\n", 2448 freq_in); 2449 return ret; 2450 } 2451 2452 dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n", 2453 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code), 2454 pll_code.n_code, pll_code.k_code); 2455 2456 snd_soc_component_write(component, RT5682_PLL_CTRL_1, 2457 (pll_code.n_code << RT5682_PLL_N_SFT) | pll_code.k_code); 2458 snd_soc_component_write(component, RT5682_PLL_CTRL_2, 2459 ((pll_code.m_bp ? 0 : pll_code.m_code) << RT5682_PLL_M_SFT) | 2460 ((pll_code.m_bp << RT5682_PLL_M_BP_SFT) | RT5682_PLL_RST)); 2461 } 2462 2463 rt5682->pll_in[pll_id] = freq_in; 2464 rt5682->pll_out[pll_id] = freq_out; 2465 rt5682->pll_src[pll_id] = source; 2466 2467 return 0; 2468 } 2469 2470 static int rt5682_set_bclk1_ratio(struct snd_soc_dai *dai, unsigned int ratio) 2471 { 2472 struct snd_soc_component *component = dai->component; 2473 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 2474 2475 rt5682->bclk[dai->id] = ratio; 2476 2477 switch (ratio) { 2478 case 256: 2479 snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL, 2480 RT5682_TDM_BCLK_MS1_MASK, RT5682_TDM_BCLK_MS1_256); 2481 break; 2482 case 128: 2483 snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL, 2484 RT5682_TDM_BCLK_MS1_MASK, RT5682_TDM_BCLK_MS1_128); 2485 break; 2486 case 64: 2487 snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL, 2488 RT5682_TDM_BCLK_MS1_MASK, RT5682_TDM_BCLK_MS1_64); 2489 break; 2490 case 32: 2491 snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL, 2492 RT5682_TDM_BCLK_MS1_MASK, RT5682_TDM_BCLK_MS1_32); 2493 break; 2494 default: 2495 dev_err(dai->dev, "Invalid bclk1 ratio %d\n", ratio); 2496 return -EINVAL; 2497 } 2498 2499 return 0; 2500 } 2501 2502 static int rt5682_set_bclk2_ratio(struct snd_soc_dai *dai, unsigned int ratio) 2503 { 2504 struct snd_soc_component *component = dai->component; 2505 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 2506 2507 rt5682->bclk[dai->id] = ratio; 2508 2509 switch (ratio) { 2510 case 64: 2511 snd_soc_component_update_bits(component, RT5682_ADDA_CLK_2, 2512 RT5682_I2S2_BCLK_MS2_MASK, 2513 RT5682_I2S2_BCLK_MS2_64); 2514 break; 2515 case 32: 2516 snd_soc_component_update_bits(component, RT5682_ADDA_CLK_2, 2517 RT5682_I2S2_BCLK_MS2_MASK, 2518 RT5682_I2S2_BCLK_MS2_32); 2519 break; 2520 default: 2521 dev_err(dai->dev, "Invalid bclk2 ratio %d\n", ratio); 2522 return -EINVAL; 2523 } 2524 2525 return 0; 2526 } 2527 2528 static int rt5682_set_bias_level(struct snd_soc_component *component, 2529 enum snd_soc_bias_level level) 2530 { 2531 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 2532 2533 switch (level) { 2534 case SND_SOC_BIAS_PREPARE: 2535 regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_1, 2536 RT5682_PWR_BG, RT5682_PWR_BG); 2537 regmap_update_bits(rt5682->regmap, RT5682_PWR_DIG_1, 2538 RT5682_DIG_GATE_CTRL | RT5682_PWR_LDO, 2539 RT5682_DIG_GATE_CTRL | RT5682_PWR_LDO); 2540 break; 2541 2542 case SND_SOC_BIAS_STANDBY: 2543 regmap_update_bits(rt5682->regmap, RT5682_PWR_DIG_1, 2544 RT5682_DIG_GATE_CTRL, RT5682_DIG_GATE_CTRL); 2545 break; 2546 case SND_SOC_BIAS_OFF: 2547 regmap_update_bits(rt5682->regmap, RT5682_PWR_DIG_1, 2548 RT5682_DIG_GATE_CTRL | RT5682_PWR_LDO, 0); 2549 regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_1, 2550 RT5682_PWR_BG, 0); 2551 break; 2552 case SND_SOC_BIAS_ON: 2553 break; 2554 } 2555 2556 return 0; 2557 } 2558 2559 #ifdef CONFIG_COMMON_CLK 2560 #define CLK_PLL2_FIN 48000000 2561 #define CLK_48 48000 2562 #define CLK_44 44100 2563 2564 static bool rt5682_clk_check(struct rt5682_priv *rt5682) 2565 { 2566 if (!rt5682->master[RT5682_AIF1]) { 2567 dev_dbg(rt5682->i2c_dev, "sysclk/dai not set correctly\n"); 2568 return false; 2569 } 2570 return true; 2571 } 2572 2573 static int rt5682_wclk_prepare(struct clk_hw *hw) 2574 { 2575 struct rt5682_priv *rt5682 = 2576 container_of(hw, struct rt5682_priv, 2577 dai_clks_hw[RT5682_DAI_WCLK_IDX]); 2578 struct snd_soc_component *component; 2579 struct snd_soc_dapm_context *dapm; 2580 2581 if (!rt5682_clk_check(rt5682)) 2582 return -EINVAL; 2583 2584 component = rt5682->component; 2585 dapm = snd_soc_component_get_dapm(component); 2586 2587 snd_soc_dapm_mutex_lock(dapm); 2588 2589 snd_soc_dapm_force_enable_pin_unlocked(dapm, "MICBIAS"); 2590 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_1, 2591 RT5682_PWR_MB, RT5682_PWR_MB); 2592 2593 snd_soc_dapm_force_enable_pin_unlocked(dapm, "Vref2"); 2594 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_1, 2595 RT5682_PWR_VREF2 | RT5682_PWR_FV2, 2596 RT5682_PWR_VREF2); 2597 usleep_range(55000, 60000); 2598 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_1, 2599 RT5682_PWR_FV2, RT5682_PWR_FV2); 2600 2601 snd_soc_dapm_force_enable_pin_unlocked(dapm, "I2S1"); 2602 snd_soc_dapm_force_enable_pin_unlocked(dapm, "PLL2F"); 2603 snd_soc_dapm_force_enable_pin_unlocked(dapm, "PLL2B"); 2604 snd_soc_dapm_sync_unlocked(dapm); 2605 2606 snd_soc_dapm_mutex_unlock(dapm); 2607 2608 return 0; 2609 } 2610 2611 static void rt5682_wclk_unprepare(struct clk_hw *hw) 2612 { 2613 struct rt5682_priv *rt5682 = 2614 container_of(hw, struct rt5682_priv, 2615 dai_clks_hw[RT5682_DAI_WCLK_IDX]); 2616 struct snd_soc_component *component; 2617 struct snd_soc_dapm_context *dapm; 2618 2619 if (!rt5682_clk_check(rt5682)) 2620 return; 2621 2622 component = rt5682->component; 2623 dapm = snd_soc_component_get_dapm(component); 2624 2625 snd_soc_dapm_mutex_lock(dapm); 2626 2627 snd_soc_dapm_disable_pin_unlocked(dapm, "MICBIAS"); 2628 snd_soc_dapm_disable_pin_unlocked(dapm, "Vref2"); 2629 if (!rt5682->jack_type) 2630 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_1, 2631 RT5682_PWR_VREF2 | RT5682_PWR_FV2 | 2632 RT5682_PWR_MB, 0); 2633 2634 snd_soc_dapm_disable_pin_unlocked(dapm, "I2S1"); 2635 snd_soc_dapm_disable_pin_unlocked(dapm, "PLL2F"); 2636 snd_soc_dapm_disable_pin_unlocked(dapm, "PLL2B"); 2637 snd_soc_dapm_sync_unlocked(dapm); 2638 2639 snd_soc_dapm_mutex_unlock(dapm); 2640 } 2641 2642 static unsigned long rt5682_wclk_recalc_rate(struct clk_hw *hw, 2643 unsigned long parent_rate) 2644 { 2645 struct rt5682_priv *rt5682 = 2646 container_of(hw, struct rt5682_priv, 2647 dai_clks_hw[RT5682_DAI_WCLK_IDX]); 2648 const char * const clk_name = clk_hw_get_name(hw); 2649 2650 if (!rt5682_clk_check(rt5682)) 2651 return 0; 2652 /* 2653 * Only accept to set wclk rate to 44.1k or 48kHz. 2654 */ 2655 if (rt5682->lrck[RT5682_AIF1] != CLK_48 && 2656 rt5682->lrck[RT5682_AIF1] != CLK_44) { 2657 dev_warn(rt5682->i2c_dev, "%s: clk %s only support %d or %d Hz output\n", 2658 __func__, clk_name, CLK_44, CLK_48); 2659 return 0; 2660 } 2661 2662 return rt5682->lrck[RT5682_AIF1]; 2663 } 2664 2665 static long rt5682_wclk_round_rate(struct clk_hw *hw, unsigned long rate, 2666 unsigned long *parent_rate) 2667 { 2668 struct rt5682_priv *rt5682 = 2669 container_of(hw, struct rt5682_priv, 2670 dai_clks_hw[RT5682_DAI_WCLK_IDX]); 2671 const char * const clk_name = clk_hw_get_name(hw); 2672 2673 if (!rt5682_clk_check(rt5682)) 2674 return -EINVAL; 2675 /* 2676 * Only accept to set wclk rate to 44.1k or 48kHz. 2677 * It will force to 48kHz if not both. 2678 */ 2679 if (rate != CLK_48 && rate != CLK_44) { 2680 dev_warn(rt5682->i2c_dev, "%s: clk %s only support %d or %d Hz output\n", 2681 __func__, clk_name, CLK_44, CLK_48); 2682 rate = CLK_48; 2683 } 2684 2685 return rate; 2686 } 2687 2688 static int rt5682_wclk_set_rate(struct clk_hw *hw, unsigned long rate, 2689 unsigned long parent_rate) 2690 { 2691 struct rt5682_priv *rt5682 = 2692 container_of(hw, struct rt5682_priv, 2693 dai_clks_hw[RT5682_DAI_WCLK_IDX]); 2694 struct snd_soc_component *component; 2695 struct clk_hw *parent_hw; 2696 const char * const clk_name = clk_hw_get_name(hw); 2697 int pre_div; 2698 unsigned int clk_pll2_out; 2699 2700 if (!rt5682_clk_check(rt5682)) 2701 return -EINVAL; 2702 2703 component = rt5682->component; 2704 2705 /* 2706 * Whether the wclk's parent clk (mclk) exists or not, please ensure 2707 * it is fixed or set to 48MHz before setting wclk rate. It's a 2708 * temporary limitation. Only accept 48MHz clk as the clk provider. 2709 * 2710 * It will set the codec anyway by assuming mclk is 48MHz. 2711 */ 2712 parent_hw = clk_hw_get_parent(hw); 2713 if (!parent_hw) 2714 dev_warn(rt5682->i2c_dev, 2715 "Parent mclk of wclk not acquired in driver. Please ensure mclk was provided as %d Hz.\n", 2716 CLK_PLL2_FIN); 2717 2718 if (parent_rate != CLK_PLL2_FIN) 2719 dev_warn(rt5682->i2c_dev, "clk %s only support %d Hz input\n", 2720 clk_name, CLK_PLL2_FIN); 2721 2722 /* 2723 * To achieve the rate conversion from 48MHz to 44.1k or 48kHz, 2724 * PLL2 is needed. 2725 */ 2726 clk_pll2_out = rate * 512; 2727 rt5682_set_component_pll(component, RT5682_PLL2, RT5682_PLL2_S_MCLK, 2728 CLK_PLL2_FIN, clk_pll2_out); 2729 2730 rt5682_set_component_sysclk(component, RT5682_SCLK_S_PLL2, 0, 2731 clk_pll2_out, SND_SOC_CLOCK_IN); 2732 2733 rt5682->lrck[RT5682_AIF1] = rate; 2734 2735 pre_div = rl6231_get_clk_info(rt5682->sysclk, rate); 2736 2737 snd_soc_component_update_bits(component, RT5682_ADDA_CLK_1, 2738 RT5682_I2S_M_DIV_MASK | RT5682_I2S_CLK_SRC_MASK, 2739 pre_div << RT5682_I2S_M_DIV_SFT | 2740 (rt5682->sysclk_src) << RT5682_I2S_CLK_SRC_SFT); 2741 2742 return 0; 2743 } 2744 2745 static unsigned long rt5682_bclk_recalc_rate(struct clk_hw *hw, 2746 unsigned long parent_rate) 2747 { 2748 struct rt5682_priv *rt5682 = 2749 container_of(hw, struct rt5682_priv, 2750 dai_clks_hw[RT5682_DAI_BCLK_IDX]); 2751 unsigned int bclks_per_wclk; 2752 2753 regmap_read(rt5682->regmap, RT5682_TDM_TCON_CTRL, &bclks_per_wclk); 2754 2755 switch (bclks_per_wclk & RT5682_TDM_BCLK_MS1_MASK) { 2756 case RT5682_TDM_BCLK_MS1_256: 2757 return parent_rate * 256; 2758 case RT5682_TDM_BCLK_MS1_128: 2759 return parent_rate * 128; 2760 case RT5682_TDM_BCLK_MS1_64: 2761 return parent_rate * 64; 2762 case RT5682_TDM_BCLK_MS1_32: 2763 return parent_rate * 32; 2764 default: 2765 return 0; 2766 } 2767 } 2768 2769 static unsigned long rt5682_bclk_get_factor(unsigned long rate, 2770 unsigned long parent_rate) 2771 { 2772 unsigned long factor; 2773 2774 factor = rate / parent_rate; 2775 if (factor < 64) 2776 return 32; 2777 else if (factor < 128) 2778 return 64; 2779 else if (factor < 256) 2780 return 128; 2781 else 2782 return 256; 2783 } 2784 2785 static long rt5682_bclk_round_rate(struct clk_hw *hw, unsigned long rate, 2786 unsigned long *parent_rate) 2787 { 2788 struct rt5682_priv *rt5682 = 2789 container_of(hw, struct rt5682_priv, 2790 dai_clks_hw[RT5682_DAI_BCLK_IDX]); 2791 unsigned long factor; 2792 2793 if (!*parent_rate || !rt5682_clk_check(rt5682)) 2794 return -EINVAL; 2795 2796 /* 2797 * BCLK rates are set as a multiplier of WCLK in HW. 2798 * We don't allow changing the parent WCLK. We just do 2799 * some rounding down based on the parent WCLK rate 2800 * and find the appropriate multiplier of BCLK to 2801 * get the rounded down BCLK value. 2802 */ 2803 factor = rt5682_bclk_get_factor(rate, *parent_rate); 2804 2805 return *parent_rate * factor; 2806 } 2807 2808 static int rt5682_bclk_set_rate(struct clk_hw *hw, unsigned long rate, 2809 unsigned long parent_rate) 2810 { 2811 struct rt5682_priv *rt5682 = 2812 container_of(hw, struct rt5682_priv, 2813 dai_clks_hw[RT5682_DAI_BCLK_IDX]); 2814 struct snd_soc_component *component; 2815 struct snd_soc_dai *dai; 2816 unsigned long factor; 2817 2818 if (!rt5682_clk_check(rt5682)) 2819 return -EINVAL; 2820 2821 component = rt5682->component; 2822 2823 factor = rt5682_bclk_get_factor(rate, parent_rate); 2824 2825 for_each_component_dais(component, dai) 2826 if (dai->id == RT5682_AIF1) 2827 break; 2828 if (!dai) { 2829 dev_err(rt5682->i2c_dev, "dai %d not found in component\n", 2830 RT5682_AIF1); 2831 return -ENODEV; 2832 } 2833 2834 return rt5682_set_bclk1_ratio(dai, factor); 2835 } 2836 2837 static const struct clk_ops rt5682_dai_clk_ops[RT5682_DAI_NUM_CLKS] = { 2838 [RT5682_DAI_WCLK_IDX] = { 2839 .prepare = rt5682_wclk_prepare, 2840 .unprepare = rt5682_wclk_unprepare, 2841 .recalc_rate = rt5682_wclk_recalc_rate, 2842 .round_rate = rt5682_wclk_round_rate, 2843 .set_rate = rt5682_wclk_set_rate, 2844 }, 2845 [RT5682_DAI_BCLK_IDX] = { 2846 .recalc_rate = rt5682_bclk_recalc_rate, 2847 .round_rate = rt5682_bclk_round_rate, 2848 .set_rate = rt5682_bclk_set_rate, 2849 }, 2850 }; 2851 2852 int rt5682_register_dai_clks(struct rt5682_priv *rt5682) 2853 { 2854 struct device *dev = rt5682->i2c_dev; 2855 struct rt5682_platform_data *pdata = &rt5682->pdata; 2856 struct clk_hw *dai_clk_hw; 2857 int i, ret; 2858 2859 for (i = 0; i < RT5682_DAI_NUM_CLKS; ++i) { 2860 struct clk_init_data init = { }; 2861 2862 dai_clk_hw = &rt5682->dai_clks_hw[i]; 2863 2864 switch (i) { 2865 case RT5682_DAI_WCLK_IDX: 2866 /* Make MCLK the parent of WCLK */ 2867 if (rt5682->mclk) { 2868 init.parent_data = &(struct clk_parent_data){ 2869 .fw_name = "mclk", 2870 }; 2871 init.num_parents = 1; 2872 } 2873 break; 2874 case RT5682_DAI_BCLK_IDX: 2875 /* Make WCLK the parent of BCLK */ 2876 init.parent_hws = &(const struct clk_hw *){ 2877 &rt5682->dai_clks_hw[RT5682_DAI_WCLK_IDX] 2878 }; 2879 init.num_parents = 1; 2880 break; 2881 default: 2882 dev_err(dev, "Invalid clock index\n"); 2883 return -EINVAL; 2884 } 2885 2886 init.name = pdata->dai_clk_names[i]; 2887 init.ops = &rt5682_dai_clk_ops[i]; 2888 init.flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_GATE; 2889 dai_clk_hw->init = &init; 2890 2891 ret = devm_clk_hw_register(dev, dai_clk_hw); 2892 if (ret) { 2893 dev_warn(dev, "Failed to register %s: %d\n", 2894 init.name, ret); 2895 return ret; 2896 } 2897 2898 if (dev->of_node) { 2899 devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, 2900 dai_clk_hw); 2901 } else { 2902 ret = devm_clk_hw_register_clkdev(dev, dai_clk_hw, 2903 init.name, 2904 dev_name(dev)); 2905 if (ret) 2906 return ret; 2907 } 2908 } 2909 2910 return 0; 2911 } 2912 EXPORT_SYMBOL_GPL(rt5682_register_dai_clks); 2913 #endif /* CONFIG_COMMON_CLK */ 2914 2915 static int rt5682_probe(struct snd_soc_component *component) 2916 { 2917 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 2918 struct sdw_slave *slave; 2919 unsigned long time; 2920 struct snd_soc_dapm_context *dapm = &component->dapm; 2921 2922 rt5682->component = component; 2923 2924 if (rt5682->is_sdw) { 2925 slave = rt5682->slave; 2926 time = wait_for_completion_timeout( 2927 &slave->initialization_complete, 2928 msecs_to_jiffies(RT5682_PROBE_TIMEOUT)); 2929 if (!time) { 2930 dev_err(&slave->dev, "Initialization not complete, timed out\n"); 2931 return -ETIMEDOUT; 2932 } 2933 } 2934 2935 snd_soc_dapm_disable_pin(dapm, "MICBIAS"); 2936 snd_soc_dapm_disable_pin(dapm, "Vref2"); 2937 snd_soc_dapm_sync(dapm); 2938 return 0; 2939 } 2940 2941 static void rt5682_remove(struct snd_soc_component *component) 2942 { 2943 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 2944 2945 rt5682_reset(rt5682); 2946 } 2947 2948 #ifdef CONFIG_PM 2949 static int rt5682_suspend(struct snd_soc_component *component) 2950 { 2951 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 2952 unsigned int val; 2953 2954 if (rt5682->is_sdw) 2955 return 0; 2956 2957 cancel_delayed_work_sync(&rt5682->jack_detect_work); 2958 cancel_delayed_work_sync(&rt5682->jd_check_work); 2959 if (rt5682->hs_jack && (rt5682->jack_type & SND_JACK_HEADSET) == SND_JACK_HEADSET) { 2960 val = snd_soc_component_read(component, 2961 RT5682_CBJ_CTRL_2) & RT5682_JACK_TYPE_MASK; 2962 2963 switch (val) { 2964 case 0x1: 2965 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1, 2966 RT5682_SAR_SEL_MB1_MASK | RT5682_SAR_SEL_MB2_MASK, 2967 RT5682_SAR_SEL_MB1_NOSEL | RT5682_SAR_SEL_MB2_SEL); 2968 break; 2969 case 0x2: 2970 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1, 2971 RT5682_SAR_SEL_MB1_MASK | RT5682_SAR_SEL_MB2_MASK, 2972 RT5682_SAR_SEL_MB1_SEL | RT5682_SAR_SEL_MB2_NOSEL); 2973 break; 2974 default: 2975 break; 2976 } 2977 2978 /* enter SAR ADC power saving mode */ 2979 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1, 2980 RT5682_SAR_BUTT_DET_MASK | RT5682_SAR_BUTDET_MODE_MASK | 2981 RT5682_SAR_SEL_MB1_MB2_MASK, 0); 2982 usleep_range(5000, 6000); 2983 snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1, 2984 RT5682_MB1_PATH_MASK | RT5682_MB2_PATH_MASK, 2985 RT5682_CTRL_MB1_REG | RT5682_CTRL_MB2_REG); 2986 usleep_range(10000, 12000); 2987 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1, 2988 RT5682_SAR_BUTT_DET_MASK | RT5682_SAR_BUTDET_MODE_MASK, 2989 RT5682_SAR_BUTT_DET_EN | RT5682_SAR_BUTDET_POW_SAV); 2990 snd_soc_component_update_bits(component, RT5682_HP_CHARGE_PUMP_1, 2991 RT5682_OSW_L_MASK | RT5682_OSW_R_MASK, 0); 2992 } 2993 2994 regcache_cache_only(rt5682->regmap, true); 2995 regcache_mark_dirty(rt5682->regmap); 2996 return 0; 2997 } 2998 2999 static int rt5682_resume(struct snd_soc_component *component) 3000 { 3001 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 3002 3003 if (rt5682->is_sdw) 3004 return 0; 3005 3006 regcache_cache_only(rt5682->regmap, false); 3007 regcache_sync(rt5682->regmap); 3008 3009 if (rt5682->hs_jack && (rt5682->jack_type & SND_JACK_HEADSET) == SND_JACK_HEADSET) { 3010 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1, 3011 RT5682_SAR_BUTDET_MODE_MASK | RT5682_SAR_SEL_MB1_MB2_MASK, 3012 RT5682_SAR_BUTDET_POW_NORM | RT5682_SAR_SEL_MB1_MB2_AUTO); 3013 usleep_range(5000, 6000); 3014 snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1, 3015 RT5682_MB1_PATH_MASK | RT5682_MB2_PATH_MASK, 3016 RT5682_CTRL_MB1_FSM | RT5682_CTRL_MB2_FSM); 3017 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_3, 3018 RT5682_PWR_CBJ, RT5682_PWR_CBJ); 3019 } 3020 3021 rt5682->jack_type = 0; 3022 mod_delayed_work(system_power_efficient_wq, 3023 &rt5682->jack_detect_work, msecs_to_jiffies(0)); 3024 3025 return 0; 3026 } 3027 #else 3028 #define rt5682_suspend NULL 3029 #define rt5682_resume NULL 3030 #endif 3031 3032 const struct snd_soc_dai_ops rt5682_aif1_dai_ops = { 3033 .hw_params = rt5682_hw_params, 3034 .set_fmt = rt5682_set_dai_fmt, 3035 .set_tdm_slot = rt5682_set_tdm_slot, 3036 .set_bclk_ratio = rt5682_set_bclk1_ratio, 3037 }; 3038 EXPORT_SYMBOL_GPL(rt5682_aif1_dai_ops); 3039 3040 const struct snd_soc_dai_ops rt5682_aif2_dai_ops = { 3041 .hw_params = rt5682_hw_params, 3042 .set_fmt = rt5682_set_dai_fmt, 3043 .set_bclk_ratio = rt5682_set_bclk2_ratio, 3044 }; 3045 EXPORT_SYMBOL_GPL(rt5682_aif2_dai_ops); 3046 3047 const struct snd_soc_component_driver rt5682_soc_component_dev = { 3048 .probe = rt5682_probe, 3049 .remove = rt5682_remove, 3050 .suspend = rt5682_suspend, 3051 .resume = rt5682_resume, 3052 .set_bias_level = rt5682_set_bias_level, 3053 .controls = rt5682_snd_controls, 3054 .num_controls = ARRAY_SIZE(rt5682_snd_controls), 3055 .dapm_widgets = rt5682_dapm_widgets, 3056 .num_dapm_widgets = ARRAY_SIZE(rt5682_dapm_widgets), 3057 .dapm_routes = rt5682_dapm_routes, 3058 .num_dapm_routes = ARRAY_SIZE(rt5682_dapm_routes), 3059 .set_sysclk = rt5682_set_component_sysclk, 3060 .set_pll = rt5682_set_component_pll, 3061 .set_jack = rt5682_set_jack_detect, 3062 .use_pmdown_time = 1, 3063 .endianness = 1, 3064 .non_legacy_dai_naming = 1, 3065 }; 3066 EXPORT_SYMBOL_GPL(rt5682_soc_component_dev); 3067 3068 int rt5682_parse_dt(struct rt5682_priv *rt5682, struct device *dev) 3069 { 3070 3071 device_property_read_u32(dev, "realtek,dmic1-data-pin", 3072 &rt5682->pdata.dmic1_data_pin); 3073 device_property_read_u32(dev, "realtek,dmic1-clk-pin", 3074 &rt5682->pdata.dmic1_clk_pin); 3075 device_property_read_u32(dev, "realtek,jd-src", 3076 &rt5682->pdata.jd_src); 3077 device_property_read_u32(dev, "realtek,btndet-delay", 3078 &rt5682->pdata.btndet_delay); 3079 device_property_read_u32(dev, "realtek,dmic-clk-rate-hz", 3080 &rt5682->pdata.dmic_clk_rate); 3081 device_property_read_u32(dev, "realtek,dmic-delay-ms", 3082 &rt5682->pdata.dmic_delay); 3083 3084 rt5682->pdata.ldo1_en = of_get_named_gpio(dev->of_node, 3085 "realtek,ldo1-en-gpios", 0); 3086 3087 if (device_property_read_string_array(dev, "clock-output-names", 3088 rt5682->pdata.dai_clk_names, 3089 RT5682_DAI_NUM_CLKS) < 0) 3090 dev_warn(dev, "Using default DAI clk names: %s, %s\n", 3091 rt5682->pdata.dai_clk_names[RT5682_DAI_WCLK_IDX], 3092 rt5682->pdata.dai_clk_names[RT5682_DAI_BCLK_IDX]); 3093 3094 rt5682->pdata.dmic_clk_driving_high = device_property_read_bool(dev, 3095 "realtek,dmic-clk-driving-high"); 3096 3097 return 0; 3098 } 3099 EXPORT_SYMBOL_GPL(rt5682_parse_dt); 3100 3101 void rt5682_calibrate(struct rt5682_priv *rt5682) 3102 { 3103 int value, count; 3104 3105 mutex_lock(&rt5682->calibrate_mutex); 3106 3107 rt5682_reset(rt5682); 3108 regmap_write(rt5682->regmap, RT5682_I2C_CTRL, 0x000f); 3109 regmap_write(rt5682->regmap, RT5682_PWR_ANLG_1, 0xa2af); 3110 usleep_range(15000, 20000); 3111 regmap_write(rt5682->regmap, RT5682_PWR_ANLG_1, 0xf2af); 3112 regmap_write(rt5682->regmap, RT5682_MICBIAS_2, 0x0300); 3113 regmap_write(rt5682->regmap, RT5682_GLB_CLK, 0x8000); 3114 regmap_write(rt5682->regmap, RT5682_PWR_DIG_1, 0x0100); 3115 regmap_write(rt5682->regmap, RT5682_HP_IMP_SENS_CTRL_19, 0x3800); 3116 regmap_write(rt5682->regmap, RT5682_CHOP_DAC, 0x3000); 3117 regmap_write(rt5682->regmap, RT5682_CALIB_ADC_CTRL, 0x7005); 3118 regmap_write(rt5682->regmap, RT5682_STO1_ADC_MIXER, 0x686c); 3119 regmap_write(rt5682->regmap, RT5682_CAL_REC, 0x0d0d); 3120 regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_2, 0x0321); 3121 regmap_write(rt5682->regmap, RT5682_HP_LOGIC_CTRL_2, 0x0004); 3122 regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_1, 0x7c00); 3123 regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_3, 0x06a1); 3124 regmap_write(rt5682->regmap, RT5682_A_DAC1_MUX, 0x0311); 3125 regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_1, 0x7c00); 3126 3127 regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_1, 0xfc00); 3128 3129 for (count = 0; count < 60; count++) { 3130 regmap_read(rt5682->regmap, RT5682_HP_CALIB_STA_1, &value); 3131 if (!(value & 0x8000)) 3132 break; 3133 3134 usleep_range(10000, 10005); 3135 } 3136 3137 if (count >= 60) 3138 dev_err(rt5682->component->dev, "HP Calibration Failure\n"); 3139 3140 /* restore settings */ 3141 regmap_write(rt5682->regmap, RT5682_PWR_ANLG_1, 0x002f); 3142 regmap_write(rt5682->regmap, RT5682_MICBIAS_2, 0x0080); 3143 regmap_write(rt5682->regmap, RT5682_GLB_CLK, 0x0000); 3144 regmap_write(rt5682->regmap, RT5682_PWR_DIG_1, 0x0000); 3145 regmap_write(rt5682->regmap, RT5682_CHOP_DAC, 0x2000); 3146 regmap_write(rt5682->regmap, RT5682_CALIB_ADC_CTRL, 0x2005); 3147 regmap_write(rt5682->regmap, RT5682_STO1_ADC_MIXER, 0xc0c4); 3148 regmap_write(rt5682->regmap, RT5682_CAL_REC, 0x0c0c); 3149 3150 mutex_unlock(&rt5682->calibrate_mutex); 3151 } 3152 EXPORT_SYMBOL_GPL(rt5682_calibrate); 3153 3154 MODULE_DESCRIPTION("ASoC RT5682 driver"); 3155 MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>"); 3156 MODULE_LICENSE("GPL v2"); 3157