1 /* 2 * rt5682.c -- RT5682 ALSA SoC audio component driver 3 * 4 * Copyright 2018 Realtek Semiconductor Corp. 5 * Author: Bard Liao <bardliao@realtek.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11 12 #include <linux/module.h> 13 #include <linux/moduleparam.h> 14 #include <linux/init.h> 15 #include <linux/delay.h> 16 #include <linux/pm.h> 17 #include <linux/i2c.h> 18 #include <linux/platform_device.h> 19 #include <linux/spi/spi.h> 20 #include <linux/acpi.h> 21 #include <linux/gpio.h> 22 #include <linux/of_gpio.h> 23 #include <linux/regulator/consumer.h> 24 #include <linux/mutex.h> 25 #include <sound/core.h> 26 #include <sound/pcm.h> 27 #include <sound/pcm_params.h> 28 #include <sound/jack.h> 29 #include <sound/soc.h> 30 #include <sound/soc-dapm.h> 31 #include <sound/initval.h> 32 #include <sound/tlv.h> 33 #include <sound/rt5682.h> 34 35 #include "rl6231.h" 36 #include "rt5682.h" 37 38 #define RT5682_NUM_SUPPLIES 3 39 40 static const char *rt5682_supply_names[RT5682_NUM_SUPPLIES] = { 41 "AVDD", 42 "MICVDD", 43 "VBAT", 44 }; 45 46 struct rt5682_priv { 47 struct snd_soc_component *component; 48 struct rt5682_platform_data pdata; 49 struct regmap *regmap; 50 struct snd_soc_jack *hs_jack; 51 struct regulator_bulk_data supplies[RT5682_NUM_SUPPLIES]; 52 struct delayed_work jack_detect_work; 53 struct delayed_work jd_check_work; 54 struct mutex calibrate_mutex; 55 56 int sysclk; 57 int sysclk_src; 58 int lrck[RT5682_AIFS]; 59 int bclk[RT5682_AIFS]; 60 int master[RT5682_AIFS]; 61 62 int pll_src; 63 int pll_in; 64 int pll_out; 65 66 int jack_type; 67 }; 68 69 static const struct reg_sequence patch_list[] = { 70 {RT5682_HP_IMP_SENS_CTRL_19, 0x1000}, 71 {RT5682_DAC_ADC_DIG_VOL1, 0xa020}, 72 }; 73 74 static const struct reg_default rt5682_reg[] = { 75 {0x0002, 0x8080}, 76 {0x0003, 0x8000}, 77 {0x0005, 0x0000}, 78 {0x0006, 0x0000}, 79 {0x0008, 0x800f}, 80 {0x000b, 0x0000}, 81 {0x0010, 0x4040}, 82 {0x0011, 0x0000}, 83 {0x0012, 0x1404}, 84 {0x0013, 0x1000}, 85 {0x0014, 0xa00a}, 86 {0x0015, 0x0404}, 87 {0x0016, 0x0404}, 88 {0x0019, 0xafaf}, 89 {0x001c, 0x2f2f}, 90 {0x001f, 0x0000}, 91 {0x0022, 0x5757}, 92 {0x0023, 0x0039}, 93 {0x0024, 0x000b}, 94 {0x0026, 0xc0c4}, 95 {0x0029, 0x8080}, 96 {0x002a, 0xa0a0}, 97 {0x002b, 0x0300}, 98 {0x0030, 0x0000}, 99 {0x003c, 0x0080}, 100 {0x0044, 0x0c0c}, 101 {0x0049, 0x0000}, 102 {0x0061, 0x0000}, 103 {0x0062, 0x0000}, 104 {0x0063, 0x003f}, 105 {0x0064, 0x0000}, 106 {0x0065, 0x0000}, 107 {0x0066, 0x0030}, 108 {0x0067, 0x0000}, 109 {0x006b, 0x0000}, 110 {0x006c, 0x0000}, 111 {0x006d, 0x2200}, 112 {0x006e, 0x0a10}, 113 {0x0070, 0x8000}, 114 {0x0071, 0x8000}, 115 {0x0073, 0x0000}, 116 {0x0074, 0x0000}, 117 {0x0075, 0x0002}, 118 {0x0076, 0x0001}, 119 {0x0079, 0x0000}, 120 {0x007a, 0x0000}, 121 {0x007b, 0x0000}, 122 {0x007c, 0x0100}, 123 {0x007e, 0x0000}, 124 {0x0080, 0x0000}, 125 {0x0081, 0x0000}, 126 {0x0082, 0x0000}, 127 {0x0083, 0x0000}, 128 {0x0084, 0x0000}, 129 {0x0085, 0x0000}, 130 {0x0086, 0x0005}, 131 {0x0087, 0x0000}, 132 {0x0088, 0x0000}, 133 {0x008c, 0x0003}, 134 {0x008d, 0x0000}, 135 {0x008e, 0x0060}, 136 {0x008f, 0x1000}, 137 {0x0091, 0x0c26}, 138 {0x0092, 0x0073}, 139 {0x0093, 0x0000}, 140 {0x0094, 0x0080}, 141 {0x0098, 0x0000}, 142 {0x009a, 0x0000}, 143 {0x009b, 0x0000}, 144 {0x009c, 0x0000}, 145 {0x009d, 0x0000}, 146 {0x009e, 0x100c}, 147 {0x009f, 0x0000}, 148 {0x00a0, 0x0000}, 149 {0x00a3, 0x0002}, 150 {0x00a4, 0x0001}, 151 {0x00ae, 0x2040}, 152 {0x00af, 0x0000}, 153 {0x00b6, 0x0000}, 154 {0x00b7, 0x0000}, 155 {0x00b8, 0x0000}, 156 {0x00b9, 0x0002}, 157 {0x00be, 0x0000}, 158 {0x00c0, 0x0160}, 159 {0x00c1, 0x82a0}, 160 {0x00c2, 0x0000}, 161 {0x00d0, 0x0000}, 162 {0x00d1, 0x2244}, 163 {0x00d2, 0x3300}, 164 {0x00d3, 0x2200}, 165 {0x00d4, 0x0000}, 166 {0x00d9, 0x0009}, 167 {0x00da, 0x0000}, 168 {0x00db, 0x0000}, 169 {0x00dc, 0x00c0}, 170 {0x00dd, 0x2220}, 171 {0x00de, 0x3131}, 172 {0x00df, 0x3131}, 173 {0x00e0, 0x3131}, 174 {0x00e2, 0x0000}, 175 {0x00e3, 0x4000}, 176 {0x00e4, 0x0aa0}, 177 {0x00e5, 0x3131}, 178 {0x00e6, 0x3131}, 179 {0x00e7, 0x3131}, 180 {0x00e8, 0x3131}, 181 {0x00ea, 0xb320}, 182 {0x00eb, 0x0000}, 183 {0x00f0, 0x0000}, 184 {0x00f1, 0x00d0}, 185 {0x00f2, 0x00d0}, 186 {0x00f6, 0x0000}, 187 {0x00fa, 0x0000}, 188 {0x00fb, 0x0000}, 189 {0x00fc, 0x0000}, 190 {0x00fd, 0x0000}, 191 {0x00fe, 0x10ec}, 192 {0x00ff, 0x6530}, 193 {0x0100, 0xa0a0}, 194 {0x010b, 0x0000}, 195 {0x010c, 0xae00}, 196 {0x010d, 0xaaa0}, 197 {0x010e, 0x8aa2}, 198 {0x010f, 0x02a2}, 199 {0x0110, 0xc000}, 200 {0x0111, 0x04a2}, 201 {0x0112, 0x2800}, 202 {0x0113, 0x0000}, 203 {0x0117, 0x0100}, 204 {0x0125, 0x0410}, 205 {0x0132, 0x6026}, 206 {0x0136, 0x5555}, 207 {0x0138, 0x3700}, 208 {0x013a, 0x2000}, 209 {0x013b, 0x2000}, 210 {0x013c, 0x2005}, 211 {0x013f, 0x0000}, 212 {0x0142, 0x0000}, 213 {0x0145, 0x0002}, 214 {0x0146, 0x0000}, 215 {0x0147, 0x0000}, 216 {0x0148, 0x0000}, 217 {0x0149, 0x0000}, 218 {0x0150, 0x79a1}, 219 {0x0151, 0x0000}, 220 {0x0160, 0x4ec0}, 221 {0x0161, 0x0080}, 222 {0x0162, 0x0200}, 223 {0x0163, 0x0800}, 224 {0x0164, 0x0000}, 225 {0x0165, 0x0000}, 226 {0x0166, 0x0000}, 227 {0x0167, 0x000f}, 228 {0x0168, 0x000f}, 229 {0x0169, 0x0021}, 230 {0x0190, 0x413d}, 231 {0x0194, 0x0000}, 232 {0x0195, 0x0000}, 233 {0x0197, 0x0022}, 234 {0x0198, 0x0000}, 235 {0x0199, 0x0000}, 236 {0x01af, 0x0000}, 237 {0x01b0, 0x0400}, 238 {0x01b1, 0x0000}, 239 {0x01b2, 0x0000}, 240 {0x01b3, 0x0000}, 241 {0x01b4, 0x0000}, 242 {0x01b5, 0x0000}, 243 {0x01b6, 0x01c3}, 244 {0x01b7, 0x02a0}, 245 {0x01b8, 0x03e9}, 246 {0x01b9, 0x1389}, 247 {0x01ba, 0xc351}, 248 {0x01bb, 0x0009}, 249 {0x01bc, 0x0018}, 250 {0x01bd, 0x002a}, 251 {0x01be, 0x004c}, 252 {0x01bf, 0x0097}, 253 {0x01c0, 0x433d}, 254 {0x01c2, 0x0000}, 255 {0x01c3, 0x0000}, 256 {0x01c4, 0x0000}, 257 {0x01c5, 0x0000}, 258 {0x01c6, 0x0000}, 259 {0x01c7, 0x0000}, 260 {0x01c8, 0x40af}, 261 {0x01c9, 0x0702}, 262 {0x01ca, 0x0000}, 263 {0x01cb, 0x0000}, 264 {0x01cc, 0x5757}, 265 {0x01cd, 0x5757}, 266 {0x01ce, 0x5757}, 267 {0x01cf, 0x5757}, 268 {0x01d0, 0x5757}, 269 {0x01d1, 0x5757}, 270 {0x01d2, 0x5757}, 271 {0x01d3, 0x5757}, 272 {0x01d4, 0x5757}, 273 {0x01d5, 0x5757}, 274 {0x01d6, 0x0000}, 275 {0x01d7, 0x0008}, 276 {0x01d8, 0x0029}, 277 {0x01d9, 0x3333}, 278 {0x01da, 0x0000}, 279 {0x01db, 0x0004}, 280 {0x01dc, 0x0000}, 281 {0x01de, 0x7c00}, 282 {0x01df, 0x0320}, 283 {0x01e0, 0x06a1}, 284 {0x01e1, 0x0000}, 285 {0x01e2, 0x0000}, 286 {0x01e3, 0x0000}, 287 {0x01e4, 0x0000}, 288 {0x01e6, 0x0001}, 289 {0x01e7, 0x0000}, 290 {0x01e8, 0x0000}, 291 {0x01ea, 0x0000}, 292 {0x01eb, 0x0000}, 293 {0x01ec, 0x0000}, 294 {0x01ed, 0x0000}, 295 {0x01ee, 0x0000}, 296 {0x01ef, 0x0000}, 297 {0x01f0, 0x0000}, 298 {0x01f1, 0x0000}, 299 {0x01f2, 0x0000}, 300 {0x01f3, 0x0000}, 301 {0x01f4, 0x0000}, 302 {0x0210, 0x6297}, 303 {0x0211, 0xa005}, 304 {0x0212, 0x824c}, 305 {0x0213, 0xf7ff}, 306 {0x0214, 0xf24c}, 307 {0x0215, 0x0102}, 308 {0x0216, 0x00a3}, 309 {0x0217, 0x0048}, 310 {0x0218, 0xa2c0}, 311 {0x0219, 0x0400}, 312 {0x021a, 0x00c8}, 313 {0x021b, 0x00c0}, 314 {0x021c, 0x0000}, 315 {0x0250, 0x4500}, 316 {0x0251, 0x40b3}, 317 {0x0252, 0x0000}, 318 {0x0253, 0x0000}, 319 {0x0254, 0x0000}, 320 {0x0255, 0x0000}, 321 {0x0256, 0x0000}, 322 {0x0257, 0x0000}, 323 {0x0258, 0x0000}, 324 {0x0259, 0x0000}, 325 {0x025a, 0x0005}, 326 {0x0270, 0x0000}, 327 {0x02ff, 0x0110}, 328 {0x0300, 0x001f}, 329 {0x0301, 0x032c}, 330 {0x0302, 0x5f21}, 331 {0x0303, 0x4000}, 332 {0x0304, 0x4000}, 333 {0x0305, 0x06d5}, 334 {0x0306, 0x8000}, 335 {0x0307, 0x0700}, 336 {0x0310, 0x4560}, 337 {0x0311, 0xa4a8}, 338 {0x0312, 0x7418}, 339 {0x0313, 0x0000}, 340 {0x0314, 0x0006}, 341 {0x0315, 0xffff}, 342 {0x0316, 0xc400}, 343 {0x0317, 0x0000}, 344 {0x03c0, 0x7e00}, 345 {0x03c1, 0x8000}, 346 {0x03c2, 0x8000}, 347 {0x03c3, 0x8000}, 348 {0x03c4, 0x8000}, 349 {0x03c5, 0x8000}, 350 {0x03c6, 0x8000}, 351 {0x03c7, 0x8000}, 352 {0x03c8, 0x8000}, 353 {0x03c9, 0x8000}, 354 {0x03ca, 0x8000}, 355 {0x03cb, 0x8000}, 356 {0x03cc, 0x8000}, 357 {0x03d0, 0x0000}, 358 {0x03d1, 0x0000}, 359 {0x03d2, 0x0000}, 360 {0x03d3, 0x0000}, 361 {0x03d4, 0x2000}, 362 {0x03d5, 0x2000}, 363 {0x03d6, 0x0000}, 364 {0x03d7, 0x0000}, 365 {0x03d8, 0x2000}, 366 {0x03d9, 0x2000}, 367 {0x03da, 0x2000}, 368 {0x03db, 0x2000}, 369 {0x03dc, 0x0000}, 370 {0x03dd, 0x0000}, 371 {0x03de, 0x0000}, 372 {0x03df, 0x2000}, 373 {0x03e0, 0x0000}, 374 {0x03e1, 0x0000}, 375 {0x03e2, 0x0000}, 376 {0x03e3, 0x0000}, 377 {0x03e4, 0x0000}, 378 {0x03e5, 0x0000}, 379 {0x03e6, 0x0000}, 380 {0x03e7, 0x0000}, 381 {0x03e8, 0x0000}, 382 {0x03e9, 0x0000}, 383 {0x03ea, 0x0000}, 384 {0x03eb, 0x0000}, 385 {0x03ec, 0x0000}, 386 {0x03ed, 0x0000}, 387 {0x03ee, 0x0000}, 388 {0x03ef, 0x0000}, 389 {0x03f0, 0x0800}, 390 {0x03f1, 0x0800}, 391 {0x03f2, 0x0800}, 392 {0x03f3, 0x0800}, 393 }; 394 395 static bool rt5682_volatile_register(struct device *dev, unsigned int reg) 396 { 397 switch (reg) { 398 case RT5682_RESET: 399 case RT5682_CBJ_CTRL_2: 400 case RT5682_INT_ST_1: 401 case RT5682_4BTN_IL_CMD_1: 402 case RT5682_AJD1_CTRL: 403 case RT5682_HP_CALIB_CTRL_1: 404 case RT5682_DEVICE_ID: 405 case RT5682_I2C_MODE: 406 case RT5682_HP_CALIB_CTRL_10: 407 case RT5682_EFUSE_CTRL_2: 408 case RT5682_JD_TOP_VC_VTRL: 409 case RT5682_HP_IMP_SENS_CTRL_19: 410 case RT5682_IL_CMD_1: 411 case RT5682_SAR_IL_CMD_2: 412 case RT5682_SAR_IL_CMD_4: 413 case RT5682_SAR_IL_CMD_10: 414 case RT5682_SAR_IL_CMD_11: 415 case RT5682_EFUSE_CTRL_6...RT5682_EFUSE_CTRL_11: 416 case RT5682_HP_CALIB_STA_1...RT5682_HP_CALIB_STA_11: 417 return true; 418 default: 419 return false; 420 } 421 } 422 423 static bool rt5682_readable_register(struct device *dev, unsigned int reg) 424 { 425 switch (reg) { 426 case RT5682_RESET: 427 case RT5682_VERSION_ID: 428 case RT5682_VENDOR_ID: 429 case RT5682_DEVICE_ID: 430 case RT5682_HP_CTRL_1: 431 case RT5682_HP_CTRL_2: 432 case RT5682_HPL_GAIN: 433 case RT5682_HPR_GAIN: 434 case RT5682_I2C_CTRL: 435 case RT5682_CBJ_BST_CTRL: 436 case RT5682_CBJ_CTRL_1: 437 case RT5682_CBJ_CTRL_2: 438 case RT5682_CBJ_CTRL_3: 439 case RT5682_CBJ_CTRL_4: 440 case RT5682_CBJ_CTRL_5: 441 case RT5682_CBJ_CTRL_6: 442 case RT5682_CBJ_CTRL_7: 443 case RT5682_DAC1_DIG_VOL: 444 case RT5682_STO1_ADC_DIG_VOL: 445 case RT5682_STO1_ADC_BOOST: 446 case RT5682_HP_IMP_GAIN_1: 447 case RT5682_HP_IMP_GAIN_2: 448 case RT5682_SIDETONE_CTRL: 449 case RT5682_STO1_ADC_MIXER: 450 case RT5682_AD_DA_MIXER: 451 case RT5682_STO1_DAC_MIXER: 452 case RT5682_A_DAC1_MUX: 453 case RT5682_DIG_INF2_DATA: 454 case RT5682_REC_MIXER: 455 case RT5682_CAL_REC: 456 case RT5682_ALC_BACK_GAIN: 457 case RT5682_PWR_DIG_1: 458 case RT5682_PWR_DIG_2: 459 case RT5682_PWR_ANLG_1: 460 case RT5682_PWR_ANLG_2: 461 case RT5682_PWR_ANLG_3: 462 case RT5682_PWR_MIXER: 463 case RT5682_PWR_VOL: 464 case RT5682_CLK_DET: 465 case RT5682_RESET_LPF_CTRL: 466 case RT5682_RESET_HPF_CTRL: 467 case RT5682_DMIC_CTRL_1: 468 case RT5682_I2S1_SDP: 469 case RT5682_I2S2_SDP: 470 case RT5682_ADDA_CLK_1: 471 case RT5682_ADDA_CLK_2: 472 case RT5682_I2S1_F_DIV_CTRL_1: 473 case RT5682_I2S1_F_DIV_CTRL_2: 474 case RT5682_TDM_CTRL: 475 case RT5682_TDM_ADDA_CTRL_1: 476 case RT5682_TDM_ADDA_CTRL_2: 477 case RT5682_DATA_SEL_CTRL_1: 478 case RT5682_TDM_TCON_CTRL: 479 case RT5682_GLB_CLK: 480 case RT5682_PLL_CTRL_1: 481 case RT5682_PLL_CTRL_2: 482 case RT5682_PLL_TRACK_1: 483 case RT5682_PLL_TRACK_2: 484 case RT5682_PLL_TRACK_3: 485 case RT5682_PLL_TRACK_4: 486 case RT5682_PLL_TRACK_5: 487 case RT5682_PLL_TRACK_6: 488 case RT5682_PLL_TRACK_11: 489 case RT5682_SDW_REF_CLK: 490 case RT5682_DEPOP_1: 491 case RT5682_DEPOP_2: 492 case RT5682_HP_CHARGE_PUMP_1: 493 case RT5682_HP_CHARGE_PUMP_2: 494 case RT5682_MICBIAS_1: 495 case RT5682_MICBIAS_2: 496 case RT5682_PLL_TRACK_12: 497 case RT5682_PLL_TRACK_14: 498 case RT5682_PLL2_CTRL_1: 499 case RT5682_PLL2_CTRL_2: 500 case RT5682_PLL2_CTRL_3: 501 case RT5682_PLL2_CTRL_4: 502 case RT5682_RC_CLK_CTRL: 503 case RT5682_I2S_M_CLK_CTRL_1: 504 case RT5682_I2S2_F_DIV_CTRL_1: 505 case RT5682_I2S2_F_DIV_CTRL_2: 506 case RT5682_EQ_CTRL_1: 507 case RT5682_EQ_CTRL_2: 508 case RT5682_IRQ_CTRL_1: 509 case RT5682_IRQ_CTRL_2: 510 case RT5682_IRQ_CTRL_3: 511 case RT5682_IRQ_CTRL_4: 512 case RT5682_INT_ST_1: 513 case RT5682_GPIO_CTRL_1: 514 case RT5682_GPIO_CTRL_2: 515 case RT5682_GPIO_CTRL_3: 516 case RT5682_HP_AMP_DET_CTRL_1: 517 case RT5682_HP_AMP_DET_CTRL_2: 518 case RT5682_MID_HP_AMP_DET: 519 case RT5682_LOW_HP_AMP_DET: 520 case RT5682_DELAY_BUF_CTRL: 521 case RT5682_SV_ZCD_1: 522 case RT5682_SV_ZCD_2: 523 case RT5682_IL_CMD_1: 524 case RT5682_IL_CMD_2: 525 case RT5682_IL_CMD_3: 526 case RT5682_IL_CMD_4: 527 case RT5682_IL_CMD_5: 528 case RT5682_IL_CMD_6: 529 case RT5682_4BTN_IL_CMD_1: 530 case RT5682_4BTN_IL_CMD_2: 531 case RT5682_4BTN_IL_CMD_3: 532 case RT5682_4BTN_IL_CMD_4: 533 case RT5682_4BTN_IL_CMD_5: 534 case RT5682_4BTN_IL_CMD_6: 535 case RT5682_4BTN_IL_CMD_7: 536 case RT5682_ADC_STO1_HP_CTRL_1: 537 case RT5682_ADC_STO1_HP_CTRL_2: 538 case RT5682_AJD1_CTRL: 539 case RT5682_JD1_THD: 540 case RT5682_JD2_THD: 541 case RT5682_JD_CTRL_1: 542 case RT5682_DUMMY_1: 543 case RT5682_DUMMY_2: 544 case RT5682_DUMMY_3: 545 case RT5682_DAC_ADC_DIG_VOL1: 546 case RT5682_BIAS_CUR_CTRL_2: 547 case RT5682_BIAS_CUR_CTRL_3: 548 case RT5682_BIAS_CUR_CTRL_4: 549 case RT5682_BIAS_CUR_CTRL_5: 550 case RT5682_BIAS_CUR_CTRL_6: 551 case RT5682_BIAS_CUR_CTRL_7: 552 case RT5682_BIAS_CUR_CTRL_8: 553 case RT5682_BIAS_CUR_CTRL_9: 554 case RT5682_BIAS_CUR_CTRL_10: 555 case RT5682_VREF_REC_OP_FB_CAP_CTRL: 556 case RT5682_CHARGE_PUMP_1: 557 case RT5682_DIG_IN_CTRL_1: 558 case RT5682_PAD_DRIVING_CTRL: 559 case RT5682_SOFT_RAMP_DEPOP: 560 case RT5682_CHOP_DAC: 561 case RT5682_CHOP_ADC: 562 case RT5682_CALIB_ADC_CTRL: 563 case RT5682_VOL_TEST: 564 case RT5682_SPKVDD_DET_STA: 565 case RT5682_TEST_MODE_CTRL_1: 566 case RT5682_TEST_MODE_CTRL_2: 567 case RT5682_TEST_MODE_CTRL_3: 568 case RT5682_TEST_MODE_CTRL_4: 569 case RT5682_TEST_MODE_CTRL_5: 570 case RT5682_PLL1_INTERNAL: 571 case RT5682_PLL2_INTERNAL: 572 case RT5682_STO_NG2_CTRL_1: 573 case RT5682_STO_NG2_CTRL_2: 574 case RT5682_STO_NG2_CTRL_3: 575 case RT5682_STO_NG2_CTRL_4: 576 case RT5682_STO_NG2_CTRL_5: 577 case RT5682_STO_NG2_CTRL_6: 578 case RT5682_STO_NG2_CTRL_7: 579 case RT5682_STO_NG2_CTRL_8: 580 case RT5682_STO_NG2_CTRL_9: 581 case RT5682_STO_NG2_CTRL_10: 582 case RT5682_STO1_DAC_SIL_DET: 583 case RT5682_SIL_PSV_CTRL1: 584 case RT5682_SIL_PSV_CTRL2: 585 case RT5682_SIL_PSV_CTRL3: 586 case RT5682_SIL_PSV_CTRL4: 587 case RT5682_SIL_PSV_CTRL5: 588 case RT5682_HP_IMP_SENS_CTRL_01: 589 case RT5682_HP_IMP_SENS_CTRL_02: 590 case RT5682_HP_IMP_SENS_CTRL_03: 591 case RT5682_HP_IMP_SENS_CTRL_04: 592 case RT5682_HP_IMP_SENS_CTRL_05: 593 case RT5682_HP_IMP_SENS_CTRL_06: 594 case RT5682_HP_IMP_SENS_CTRL_07: 595 case RT5682_HP_IMP_SENS_CTRL_08: 596 case RT5682_HP_IMP_SENS_CTRL_09: 597 case RT5682_HP_IMP_SENS_CTRL_10: 598 case RT5682_HP_IMP_SENS_CTRL_11: 599 case RT5682_HP_IMP_SENS_CTRL_12: 600 case RT5682_HP_IMP_SENS_CTRL_13: 601 case RT5682_HP_IMP_SENS_CTRL_14: 602 case RT5682_HP_IMP_SENS_CTRL_15: 603 case RT5682_HP_IMP_SENS_CTRL_16: 604 case RT5682_HP_IMP_SENS_CTRL_17: 605 case RT5682_HP_IMP_SENS_CTRL_18: 606 case RT5682_HP_IMP_SENS_CTRL_19: 607 case RT5682_HP_IMP_SENS_CTRL_20: 608 case RT5682_HP_IMP_SENS_CTRL_21: 609 case RT5682_HP_IMP_SENS_CTRL_22: 610 case RT5682_HP_IMP_SENS_CTRL_23: 611 case RT5682_HP_IMP_SENS_CTRL_24: 612 case RT5682_HP_IMP_SENS_CTRL_25: 613 case RT5682_HP_IMP_SENS_CTRL_26: 614 case RT5682_HP_IMP_SENS_CTRL_27: 615 case RT5682_HP_IMP_SENS_CTRL_28: 616 case RT5682_HP_IMP_SENS_CTRL_29: 617 case RT5682_HP_IMP_SENS_CTRL_30: 618 case RT5682_HP_IMP_SENS_CTRL_31: 619 case RT5682_HP_IMP_SENS_CTRL_32: 620 case RT5682_HP_IMP_SENS_CTRL_33: 621 case RT5682_HP_IMP_SENS_CTRL_34: 622 case RT5682_HP_IMP_SENS_CTRL_35: 623 case RT5682_HP_IMP_SENS_CTRL_36: 624 case RT5682_HP_IMP_SENS_CTRL_37: 625 case RT5682_HP_IMP_SENS_CTRL_38: 626 case RT5682_HP_IMP_SENS_CTRL_39: 627 case RT5682_HP_IMP_SENS_CTRL_40: 628 case RT5682_HP_IMP_SENS_CTRL_41: 629 case RT5682_HP_IMP_SENS_CTRL_42: 630 case RT5682_HP_IMP_SENS_CTRL_43: 631 case RT5682_HP_LOGIC_CTRL_1: 632 case RT5682_HP_LOGIC_CTRL_2: 633 case RT5682_HP_LOGIC_CTRL_3: 634 case RT5682_HP_CALIB_CTRL_1: 635 case RT5682_HP_CALIB_CTRL_2: 636 case RT5682_HP_CALIB_CTRL_3: 637 case RT5682_HP_CALIB_CTRL_4: 638 case RT5682_HP_CALIB_CTRL_5: 639 case RT5682_HP_CALIB_CTRL_6: 640 case RT5682_HP_CALIB_CTRL_7: 641 case RT5682_HP_CALIB_CTRL_9: 642 case RT5682_HP_CALIB_CTRL_10: 643 case RT5682_HP_CALIB_CTRL_11: 644 case RT5682_HP_CALIB_STA_1: 645 case RT5682_HP_CALIB_STA_2: 646 case RT5682_HP_CALIB_STA_3: 647 case RT5682_HP_CALIB_STA_4: 648 case RT5682_HP_CALIB_STA_5: 649 case RT5682_HP_CALIB_STA_6: 650 case RT5682_HP_CALIB_STA_7: 651 case RT5682_HP_CALIB_STA_8: 652 case RT5682_HP_CALIB_STA_9: 653 case RT5682_HP_CALIB_STA_10: 654 case RT5682_HP_CALIB_STA_11: 655 case RT5682_SAR_IL_CMD_1: 656 case RT5682_SAR_IL_CMD_2: 657 case RT5682_SAR_IL_CMD_3: 658 case RT5682_SAR_IL_CMD_4: 659 case RT5682_SAR_IL_CMD_5: 660 case RT5682_SAR_IL_CMD_6: 661 case RT5682_SAR_IL_CMD_7: 662 case RT5682_SAR_IL_CMD_8: 663 case RT5682_SAR_IL_CMD_9: 664 case RT5682_SAR_IL_CMD_10: 665 case RT5682_SAR_IL_CMD_11: 666 case RT5682_SAR_IL_CMD_12: 667 case RT5682_SAR_IL_CMD_13: 668 case RT5682_EFUSE_CTRL_1: 669 case RT5682_EFUSE_CTRL_2: 670 case RT5682_EFUSE_CTRL_3: 671 case RT5682_EFUSE_CTRL_4: 672 case RT5682_EFUSE_CTRL_5: 673 case RT5682_EFUSE_CTRL_6: 674 case RT5682_EFUSE_CTRL_7: 675 case RT5682_EFUSE_CTRL_8: 676 case RT5682_EFUSE_CTRL_9: 677 case RT5682_EFUSE_CTRL_10: 678 case RT5682_EFUSE_CTRL_11: 679 case RT5682_JD_TOP_VC_VTRL: 680 case RT5682_DRC1_CTRL_0: 681 case RT5682_DRC1_CTRL_1: 682 case RT5682_DRC1_CTRL_2: 683 case RT5682_DRC1_CTRL_3: 684 case RT5682_DRC1_CTRL_4: 685 case RT5682_DRC1_CTRL_5: 686 case RT5682_DRC1_CTRL_6: 687 case RT5682_DRC1_HARD_LMT_CTRL_1: 688 case RT5682_DRC1_HARD_LMT_CTRL_2: 689 case RT5682_DRC1_PRIV_1: 690 case RT5682_DRC1_PRIV_2: 691 case RT5682_DRC1_PRIV_3: 692 case RT5682_DRC1_PRIV_4: 693 case RT5682_DRC1_PRIV_5: 694 case RT5682_DRC1_PRIV_6: 695 case RT5682_DRC1_PRIV_7: 696 case RT5682_DRC1_PRIV_8: 697 case RT5682_EQ_AUTO_RCV_CTRL1: 698 case RT5682_EQ_AUTO_RCV_CTRL2: 699 case RT5682_EQ_AUTO_RCV_CTRL3: 700 case RT5682_EQ_AUTO_RCV_CTRL4: 701 case RT5682_EQ_AUTO_RCV_CTRL5: 702 case RT5682_EQ_AUTO_RCV_CTRL6: 703 case RT5682_EQ_AUTO_RCV_CTRL7: 704 case RT5682_EQ_AUTO_RCV_CTRL8: 705 case RT5682_EQ_AUTO_RCV_CTRL9: 706 case RT5682_EQ_AUTO_RCV_CTRL10: 707 case RT5682_EQ_AUTO_RCV_CTRL11: 708 case RT5682_EQ_AUTO_RCV_CTRL12: 709 case RT5682_EQ_AUTO_RCV_CTRL13: 710 case RT5682_ADC_L_EQ_LPF1_A1: 711 case RT5682_R_EQ_LPF1_A1: 712 case RT5682_L_EQ_LPF1_H0: 713 case RT5682_R_EQ_LPF1_H0: 714 case RT5682_L_EQ_BPF1_A1: 715 case RT5682_R_EQ_BPF1_A1: 716 case RT5682_L_EQ_BPF1_A2: 717 case RT5682_R_EQ_BPF1_A2: 718 case RT5682_L_EQ_BPF1_H0: 719 case RT5682_R_EQ_BPF1_H0: 720 case RT5682_L_EQ_BPF2_A1: 721 case RT5682_R_EQ_BPF2_A1: 722 case RT5682_L_EQ_BPF2_A2: 723 case RT5682_R_EQ_BPF2_A2: 724 case RT5682_L_EQ_BPF2_H0: 725 case RT5682_R_EQ_BPF2_H0: 726 case RT5682_L_EQ_BPF3_A1: 727 case RT5682_R_EQ_BPF3_A1: 728 case RT5682_L_EQ_BPF3_A2: 729 case RT5682_R_EQ_BPF3_A2: 730 case RT5682_L_EQ_BPF3_H0: 731 case RT5682_R_EQ_BPF3_H0: 732 case RT5682_L_EQ_BPF4_A1: 733 case RT5682_R_EQ_BPF4_A1: 734 case RT5682_L_EQ_BPF4_A2: 735 case RT5682_R_EQ_BPF4_A2: 736 case RT5682_L_EQ_BPF4_H0: 737 case RT5682_R_EQ_BPF4_H0: 738 case RT5682_L_EQ_HPF1_A1: 739 case RT5682_R_EQ_HPF1_A1: 740 case RT5682_L_EQ_HPF1_H0: 741 case RT5682_R_EQ_HPF1_H0: 742 case RT5682_L_EQ_PRE_VOL: 743 case RT5682_R_EQ_PRE_VOL: 744 case RT5682_L_EQ_POST_VOL: 745 case RT5682_R_EQ_POST_VOL: 746 case RT5682_I2C_MODE: 747 return true; 748 default: 749 return false; 750 } 751 } 752 753 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6525, 75, 0); 754 static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0); 755 static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0); 756 757 /* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */ 758 static const DECLARE_TLV_DB_RANGE(bst_tlv, 759 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0), 760 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0), 761 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0), 762 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0), 763 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0), 764 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0), 765 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0) 766 ); 767 768 /* Interface data select */ 769 static const char * const rt5682_data_select[] = { 770 "L/R", "R/L", "L/L", "R/R" 771 }; 772 773 static SOC_ENUM_SINGLE_DECL(rt5682_if2_adc_enum, 774 RT5682_DIG_INF2_DATA, RT5682_IF2_ADC_SEL_SFT, rt5682_data_select); 775 776 static SOC_ENUM_SINGLE_DECL(rt5682_if1_01_adc_enum, 777 RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC1_SEL_SFT, rt5682_data_select); 778 779 static SOC_ENUM_SINGLE_DECL(rt5682_if1_23_adc_enum, 780 RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC2_SEL_SFT, rt5682_data_select); 781 782 static SOC_ENUM_SINGLE_DECL(rt5682_if1_45_adc_enum, 783 RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC3_SEL_SFT, rt5682_data_select); 784 785 static SOC_ENUM_SINGLE_DECL(rt5682_if1_67_adc_enum, 786 RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC4_SEL_SFT, rt5682_data_select); 787 788 static const struct snd_kcontrol_new rt5682_if2_adc_swap_mux = 789 SOC_DAPM_ENUM("IF2 ADC Swap Mux", rt5682_if2_adc_enum); 790 791 static const struct snd_kcontrol_new rt5682_if1_01_adc_swap_mux = 792 SOC_DAPM_ENUM("IF1 01 ADC Swap Mux", rt5682_if1_01_adc_enum); 793 794 static const struct snd_kcontrol_new rt5682_if1_23_adc_swap_mux = 795 SOC_DAPM_ENUM("IF1 23 ADC Swap Mux", rt5682_if1_23_adc_enum); 796 797 static const struct snd_kcontrol_new rt5682_if1_45_adc_swap_mux = 798 SOC_DAPM_ENUM("IF1 45 ADC Swap Mux", rt5682_if1_45_adc_enum); 799 800 static const struct snd_kcontrol_new rt5682_if1_67_adc_swap_mux = 801 SOC_DAPM_ENUM("IF1 67 ADC Swap Mux", rt5682_if1_67_adc_enum); 802 803 static void rt5682_reset(struct regmap *regmap) 804 { 805 regmap_write(regmap, RT5682_RESET, 0); 806 regmap_write(regmap, RT5682_I2C_MODE, 1); 807 } 808 /** 809 * rt5682_sel_asrc_clk_src - select ASRC clock source for a set of filters 810 * @component: SoC audio component device. 811 * @filter_mask: mask of filters. 812 * @clk_src: clock source 813 * 814 * The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5682 can 815 * only support standard 32fs or 64fs i2s format, ASRC should be enabled to 816 * support special i2s clock format such as Intel's 100fs(100 * sampling rate). 817 * ASRC function will track i2s clock and generate a corresponding system clock 818 * for codec. This function provides an API to select the clock source for a 819 * set of filters specified by the mask. And the component driver will turn on 820 * ASRC for these filters if ASRC is selected as their clock source. 821 */ 822 int rt5682_sel_asrc_clk_src(struct snd_soc_component *component, 823 unsigned int filter_mask, unsigned int clk_src) 824 { 825 826 switch (clk_src) { 827 case RT5682_CLK_SEL_SYS: 828 case RT5682_CLK_SEL_I2S1_ASRC: 829 case RT5682_CLK_SEL_I2S2_ASRC: 830 break; 831 832 default: 833 return -EINVAL; 834 } 835 836 if (filter_mask & RT5682_DA_STEREO1_FILTER) { 837 snd_soc_component_update_bits(component, RT5682_PLL_TRACK_2, 838 RT5682_FILTER_CLK_SEL_MASK, 839 clk_src << RT5682_FILTER_CLK_SEL_SFT); 840 } 841 842 if (filter_mask & RT5682_AD_STEREO1_FILTER) { 843 snd_soc_component_update_bits(component, RT5682_PLL_TRACK_3, 844 RT5682_FILTER_CLK_SEL_MASK, 845 clk_src << RT5682_FILTER_CLK_SEL_SFT); 846 } 847 848 return 0; 849 } 850 EXPORT_SYMBOL_GPL(rt5682_sel_asrc_clk_src); 851 852 static int rt5682_button_detect(struct snd_soc_component *component) 853 { 854 int btn_type, val; 855 856 val = snd_soc_component_read32(component, RT5682_4BTN_IL_CMD_1); 857 btn_type = val & 0xfff0; 858 snd_soc_component_write(component, RT5682_4BTN_IL_CMD_1, val); 859 pr_debug("%s btn_type=%x\n", __func__, btn_type); 860 snd_soc_component_update_bits(component, 861 RT5682_SAR_IL_CMD_2, 0x10, 0x10); 862 863 return btn_type; 864 } 865 866 static void rt5682_enable_push_button_irq(struct snd_soc_component *component, 867 bool enable) 868 { 869 if (enable) { 870 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1, 871 RT5682_SAR_BUTT_DET_MASK, RT5682_SAR_BUTT_DET_EN); 872 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_13, 873 RT5682_SAR_SOUR_MASK, RT5682_SAR_SOUR_BTN); 874 snd_soc_component_write(component, RT5682_IL_CMD_1, 0x0040); 875 snd_soc_component_update_bits(component, RT5682_4BTN_IL_CMD_2, 876 RT5682_4BTN_IL_MASK | RT5682_4BTN_IL_RST_MASK, 877 RT5682_4BTN_IL_EN | RT5682_4BTN_IL_NOR); 878 snd_soc_component_update_bits(component, RT5682_IRQ_CTRL_3, 879 RT5682_IL_IRQ_MASK, RT5682_IL_IRQ_EN); 880 } else { 881 snd_soc_component_update_bits(component, RT5682_IRQ_CTRL_3, 882 RT5682_IL_IRQ_MASK, RT5682_IL_IRQ_DIS); 883 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1, 884 RT5682_SAR_BUTT_DET_MASK, RT5682_SAR_BUTT_DET_DIS); 885 snd_soc_component_update_bits(component, RT5682_4BTN_IL_CMD_2, 886 RT5682_4BTN_IL_MASK, RT5682_4BTN_IL_DIS); 887 snd_soc_component_update_bits(component, RT5682_4BTN_IL_CMD_2, 888 RT5682_4BTN_IL_RST_MASK, RT5682_4BTN_IL_RST); 889 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_13, 890 RT5682_SAR_SOUR_MASK, RT5682_SAR_SOUR_TYPE); 891 } 892 } 893 894 /** 895 * rt5682_headset_detect - Detect headset. 896 * @component: SoC audio component device. 897 * @jack_insert: Jack insert or not. 898 * 899 * Detect whether is headset or not when jack inserted. 900 * 901 * Returns detect status. 902 */ 903 static int rt5682_headset_detect(struct snd_soc_component *component, 904 int jack_insert) 905 { 906 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 907 struct snd_soc_dapm_context *dapm = 908 snd_soc_component_get_dapm(component); 909 unsigned int val, count; 910 911 if (jack_insert) { 912 snd_soc_dapm_force_enable_pin(dapm, "CBJ Power"); 913 snd_soc_dapm_sync(dapm); 914 snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1, 915 RT5682_TRIG_JD_MASK, RT5682_TRIG_JD_HIGH); 916 917 count = 0; 918 val = snd_soc_component_read32(component, RT5682_CBJ_CTRL_2) 919 & RT5682_JACK_TYPE_MASK; 920 while (val == 0 && count < 50) { 921 usleep_range(10000, 15000); 922 val = snd_soc_component_read32(component, 923 RT5682_CBJ_CTRL_2) & RT5682_JACK_TYPE_MASK; 924 count++; 925 } 926 927 switch (val) { 928 case 0x1: 929 case 0x2: 930 rt5682->jack_type = SND_JACK_HEADSET; 931 rt5682_enable_push_button_irq(component, true); 932 break; 933 default: 934 rt5682->jack_type = SND_JACK_HEADPHONE; 935 } 936 937 } else { 938 rt5682_enable_push_button_irq(component, false); 939 snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1, 940 RT5682_TRIG_JD_MASK, RT5682_TRIG_JD_LOW); 941 snd_soc_dapm_disable_pin(dapm, "CBJ Power"); 942 snd_soc_dapm_sync(dapm); 943 944 rt5682->jack_type = 0; 945 } 946 947 dev_dbg(component->dev, "jack_type = %d\n", rt5682->jack_type); 948 return rt5682->jack_type; 949 } 950 951 static irqreturn_t rt5682_irq(int irq, void *data) 952 { 953 struct rt5682_priv *rt5682 = data; 954 955 mod_delayed_work(system_power_efficient_wq, 956 &rt5682->jack_detect_work, msecs_to_jiffies(250)); 957 958 return IRQ_HANDLED; 959 } 960 961 static void rt5682_jd_check_handler(struct work_struct *work) 962 { 963 struct rt5682_priv *rt5682 = container_of(work, struct rt5682_priv, 964 jd_check_work.work); 965 966 if (snd_soc_component_read32(rt5682->component, RT5682_AJD1_CTRL) 967 & RT5682_JDH_RS_MASK) { 968 /* jack out */ 969 rt5682->jack_type = rt5682_headset_detect(rt5682->component, 0); 970 971 snd_soc_jack_report(rt5682->hs_jack, rt5682->jack_type, 972 SND_JACK_HEADSET | 973 SND_JACK_BTN_0 | SND_JACK_BTN_1 | 974 SND_JACK_BTN_2 | SND_JACK_BTN_3); 975 } else { 976 schedule_delayed_work(&rt5682->jd_check_work, 500); 977 } 978 } 979 980 static int rt5682_set_jack_detect(struct snd_soc_component *component, 981 struct snd_soc_jack *hs_jack, void *data) 982 { 983 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 984 985 switch (rt5682->pdata.jd_src) { 986 case RT5682_JD1: 987 snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_2, 988 RT5682_EXT_JD_SRC, RT5682_EXT_JD_SRC_MANUAL); 989 snd_soc_component_write(component, RT5682_CBJ_CTRL_1, 0xd042); 990 snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_3, 991 RT5682_CBJ_IN_BUF_EN, RT5682_CBJ_IN_BUF_EN); 992 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1, 993 RT5682_SAR_POW_MASK, RT5682_SAR_POW_EN); 994 regmap_update_bits(rt5682->regmap, RT5682_GPIO_CTRL_1, 995 RT5682_GP1_PIN_MASK, RT5682_GP1_PIN_IRQ); 996 regmap_update_bits(rt5682->regmap, RT5682_RC_CLK_CTRL, 997 RT5682_POW_IRQ | RT5682_POW_JDH | 998 RT5682_POW_ANA, RT5682_POW_IRQ | 999 RT5682_POW_JDH | RT5682_POW_ANA); 1000 regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_2, 1001 RT5682_PWR_JDH | RT5682_PWR_JDL, 1002 RT5682_PWR_JDH | RT5682_PWR_JDL); 1003 regmap_update_bits(rt5682->regmap, RT5682_IRQ_CTRL_2, 1004 RT5682_JD1_EN_MASK | RT5682_JD1_POL_MASK, 1005 RT5682_JD1_EN | RT5682_JD1_POL_NOR); 1006 mod_delayed_work(system_power_efficient_wq, 1007 &rt5682->jack_detect_work, msecs_to_jiffies(250)); 1008 break; 1009 1010 case RT5682_JD_NULL: 1011 regmap_update_bits(rt5682->regmap, RT5682_IRQ_CTRL_2, 1012 RT5682_JD1_EN_MASK, RT5682_JD1_DIS); 1013 regmap_update_bits(rt5682->regmap, RT5682_RC_CLK_CTRL, 1014 RT5682_POW_JDH | RT5682_POW_JDL, 0); 1015 break; 1016 1017 default: 1018 dev_warn(component->dev, "Wrong JD source\n"); 1019 break; 1020 } 1021 1022 rt5682->hs_jack = hs_jack; 1023 1024 return 0; 1025 } 1026 1027 static void rt5682_jack_detect_handler(struct work_struct *work) 1028 { 1029 struct rt5682_priv *rt5682 = 1030 container_of(work, struct rt5682_priv, jack_detect_work.work); 1031 int val, btn_type; 1032 1033 while (!rt5682->component) 1034 usleep_range(10000, 15000); 1035 1036 while (!rt5682->component->card->instantiated) 1037 usleep_range(10000, 15000); 1038 1039 mutex_lock(&rt5682->calibrate_mutex); 1040 1041 val = snd_soc_component_read32(rt5682->component, RT5682_AJD1_CTRL) 1042 & RT5682_JDH_RS_MASK; 1043 if (!val) { 1044 /* jack in */ 1045 if (rt5682->jack_type == 0) { 1046 /* jack was out, report jack type */ 1047 rt5682->jack_type = 1048 rt5682_headset_detect(rt5682->component, 1); 1049 } else { 1050 /* jack is already in, report button event */ 1051 rt5682->jack_type = SND_JACK_HEADSET; 1052 btn_type = rt5682_button_detect(rt5682->component); 1053 /** 1054 * rt5682 can report three kinds of button behavior, 1055 * one click, double click and hold. However, 1056 * currently we will report button pressed/released 1057 * event. So all the three button behaviors are 1058 * treated as button pressed. 1059 */ 1060 switch (btn_type) { 1061 case 0x8000: 1062 case 0x4000: 1063 case 0x2000: 1064 rt5682->jack_type |= SND_JACK_BTN_0; 1065 break; 1066 case 0x1000: 1067 case 0x0800: 1068 case 0x0400: 1069 rt5682->jack_type |= SND_JACK_BTN_1; 1070 break; 1071 case 0x0200: 1072 case 0x0100: 1073 case 0x0080: 1074 rt5682->jack_type |= SND_JACK_BTN_2; 1075 break; 1076 case 0x0040: 1077 case 0x0020: 1078 case 0x0010: 1079 rt5682->jack_type |= SND_JACK_BTN_3; 1080 break; 1081 case 0x0000: /* unpressed */ 1082 break; 1083 default: 1084 btn_type = 0; 1085 dev_err(rt5682->component->dev, 1086 "Unexpected button code 0x%04x\n", 1087 btn_type); 1088 break; 1089 } 1090 } 1091 } else { 1092 /* jack out */ 1093 rt5682->jack_type = rt5682_headset_detect(rt5682->component, 0); 1094 } 1095 1096 snd_soc_jack_report(rt5682->hs_jack, rt5682->jack_type, 1097 SND_JACK_HEADSET | 1098 SND_JACK_BTN_0 | SND_JACK_BTN_1 | 1099 SND_JACK_BTN_2 | SND_JACK_BTN_3); 1100 1101 if (rt5682->jack_type & (SND_JACK_BTN_0 | SND_JACK_BTN_1 | 1102 SND_JACK_BTN_2 | SND_JACK_BTN_3)) 1103 schedule_delayed_work(&rt5682->jd_check_work, 0); 1104 else 1105 cancel_delayed_work_sync(&rt5682->jd_check_work); 1106 1107 mutex_unlock(&rt5682->calibrate_mutex); 1108 } 1109 1110 static const struct snd_kcontrol_new rt5682_snd_controls[] = { 1111 /* DAC Digital Volume */ 1112 SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5682_DAC1_DIG_VOL, 1113 RT5682_L_VOL_SFT + 1, RT5682_R_VOL_SFT + 1, 86, 0, dac_vol_tlv), 1114 1115 /* IN Boost Volume */ 1116 SOC_SINGLE_TLV("CBJ Boost Volume", RT5682_CBJ_BST_CTRL, 1117 RT5682_BST_CBJ_SFT, 8, 0, bst_tlv), 1118 1119 /* ADC Digital Volume Control */ 1120 SOC_DOUBLE("STO1 ADC Capture Switch", RT5682_STO1_ADC_DIG_VOL, 1121 RT5682_L_MUTE_SFT, RT5682_R_MUTE_SFT, 1, 1), 1122 SOC_DOUBLE_TLV("STO1 ADC Capture Volume", RT5682_STO1_ADC_DIG_VOL, 1123 RT5682_L_VOL_SFT + 1, RT5682_R_VOL_SFT + 1, 63, 0, adc_vol_tlv), 1124 1125 /* ADC Boost Volume Control */ 1126 SOC_DOUBLE_TLV("STO1 ADC Boost Gain Volume", RT5682_STO1_ADC_BOOST, 1127 RT5682_STO1_ADC_L_BST_SFT, RT5682_STO1_ADC_R_BST_SFT, 1128 3, 0, adc_bst_tlv), 1129 }; 1130 1131 1132 static int rt5682_div_sel(struct rt5682_priv *rt5682, 1133 int target, const int div[], int size) 1134 { 1135 int i; 1136 1137 if (rt5682->sysclk < target) { 1138 pr_err("sysclk rate %d is too low\n", 1139 rt5682->sysclk); 1140 return 0; 1141 } 1142 1143 for (i = 0; i < size - 1; i++) { 1144 pr_info("div[%d]=%d\n", i, div[i]); 1145 if (target * div[i] == rt5682->sysclk) 1146 return i; 1147 if (target * div[i + 1] > rt5682->sysclk) { 1148 pr_err("can't find div for sysclk %d\n", 1149 rt5682->sysclk); 1150 return i; 1151 } 1152 } 1153 1154 if (target * div[i] < rt5682->sysclk) 1155 pr_err("sysclk rate %d is too high\n", 1156 rt5682->sysclk); 1157 1158 return size - 1; 1159 1160 } 1161 1162 /** 1163 * set_dmic_clk - Set parameter of dmic. 1164 * 1165 * @w: DAPM widget. 1166 * @kcontrol: The kcontrol of this widget. 1167 * @event: Event id. 1168 * 1169 * Choose dmic clock between 1MHz and 3MHz. 1170 * It is better for clock to approximate 3MHz. 1171 */ 1172 static int set_dmic_clk(struct snd_soc_dapm_widget *w, 1173 struct snd_kcontrol *kcontrol, int event) 1174 { 1175 struct snd_soc_component *component = 1176 snd_soc_dapm_to_component(w->dapm); 1177 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 1178 int idx = -EINVAL; 1179 static const int div[] = {2, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, 128}; 1180 1181 idx = rt5682_div_sel(rt5682, 1500000, div, ARRAY_SIZE(div)); 1182 1183 snd_soc_component_update_bits(component, RT5682_DMIC_CTRL_1, 1184 RT5682_DMIC_CLK_MASK, idx << RT5682_DMIC_CLK_SFT); 1185 1186 return 0; 1187 } 1188 1189 static int set_filter_clk(struct snd_soc_dapm_widget *w, 1190 struct snd_kcontrol *kcontrol, int event) 1191 { 1192 struct snd_soc_component *component = 1193 snd_soc_dapm_to_component(w->dapm); 1194 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 1195 int ref, val, reg, sft, mask, idx = -EINVAL; 1196 static const int div_f[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32, 48}; 1197 static const int div_o[] = {1, 2, 4, 6, 8, 12, 16, 24, 32, 48}; 1198 1199 val = snd_soc_component_read32(component, RT5682_GPIO_CTRL_1) & 1200 RT5682_GP4_PIN_MASK; 1201 if (w->shift == RT5682_PWR_ADC_S1F_BIT && 1202 val == RT5682_GP4_PIN_ADCDAT2) 1203 ref = 256 * rt5682->lrck[RT5682_AIF2]; 1204 else 1205 ref = 256 * rt5682->lrck[RT5682_AIF1]; 1206 1207 idx = rt5682_div_sel(rt5682, ref, div_f, ARRAY_SIZE(div_f)); 1208 1209 if (w->shift == RT5682_PWR_ADC_S1F_BIT) { 1210 reg = RT5682_PLL_TRACK_3; 1211 sft = RT5682_ADC_OSR_SFT; 1212 mask = RT5682_ADC_OSR_MASK; 1213 } else { 1214 reg = RT5682_PLL_TRACK_2; 1215 sft = RT5682_DAC_OSR_SFT; 1216 mask = RT5682_DAC_OSR_MASK; 1217 } 1218 1219 snd_soc_component_update_bits(component, reg, 1220 RT5682_FILTER_CLK_DIV_MASK, idx << RT5682_FILTER_CLK_DIV_SFT); 1221 1222 /* select over sample rate */ 1223 for (idx = 0; idx < ARRAY_SIZE(div_o); idx++) { 1224 if (rt5682->sysclk <= 12288000 * div_o[idx]) 1225 break; 1226 } 1227 1228 snd_soc_component_update_bits(component, RT5682_ADDA_CLK_1, 1229 mask, idx << sft); 1230 1231 return 0; 1232 } 1233 1234 static int is_sys_clk_from_pll1(struct snd_soc_dapm_widget *w, 1235 struct snd_soc_dapm_widget *sink) 1236 { 1237 unsigned int val; 1238 struct snd_soc_component *component = 1239 snd_soc_dapm_to_component(w->dapm); 1240 1241 val = snd_soc_component_read32(component, RT5682_GLB_CLK); 1242 val &= RT5682_SCLK_SRC_MASK; 1243 if (val == RT5682_SCLK_SRC_PLL1) 1244 return 1; 1245 else 1246 return 0; 1247 } 1248 1249 static int is_using_asrc(struct snd_soc_dapm_widget *w, 1250 struct snd_soc_dapm_widget *sink) 1251 { 1252 unsigned int reg, shift, val; 1253 struct snd_soc_component *component = 1254 snd_soc_dapm_to_component(w->dapm); 1255 1256 switch (w->shift) { 1257 case RT5682_ADC_STO1_ASRC_SFT: 1258 reg = RT5682_PLL_TRACK_3; 1259 shift = RT5682_FILTER_CLK_SEL_SFT; 1260 break; 1261 case RT5682_DAC_STO1_ASRC_SFT: 1262 reg = RT5682_PLL_TRACK_2; 1263 shift = RT5682_FILTER_CLK_SEL_SFT; 1264 break; 1265 default: 1266 return 0; 1267 } 1268 1269 val = (snd_soc_component_read32(component, reg) >> shift) & 0xf; 1270 switch (val) { 1271 case RT5682_CLK_SEL_I2S1_ASRC: 1272 case RT5682_CLK_SEL_I2S2_ASRC: 1273 return 1; 1274 default: 1275 return 0; 1276 } 1277 1278 } 1279 1280 /* Digital Mixer */ 1281 static const struct snd_kcontrol_new rt5682_sto1_adc_l_mix[] = { 1282 SOC_DAPM_SINGLE("ADC1 Switch", RT5682_STO1_ADC_MIXER, 1283 RT5682_M_STO1_ADC_L1_SFT, 1, 1), 1284 SOC_DAPM_SINGLE("ADC2 Switch", RT5682_STO1_ADC_MIXER, 1285 RT5682_M_STO1_ADC_L2_SFT, 1, 1), 1286 }; 1287 1288 static const struct snd_kcontrol_new rt5682_sto1_adc_r_mix[] = { 1289 SOC_DAPM_SINGLE("ADC1 Switch", RT5682_STO1_ADC_MIXER, 1290 RT5682_M_STO1_ADC_R1_SFT, 1, 1), 1291 SOC_DAPM_SINGLE("ADC2 Switch", RT5682_STO1_ADC_MIXER, 1292 RT5682_M_STO1_ADC_R2_SFT, 1, 1), 1293 }; 1294 1295 static const struct snd_kcontrol_new rt5682_dac_l_mix[] = { 1296 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5682_AD_DA_MIXER, 1297 RT5682_M_ADCMIX_L_SFT, 1, 1), 1298 SOC_DAPM_SINGLE("DAC1 Switch", RT5682_AD_DA_MIXER, 1299 RT5682_M_DAC1_L_SFT, 1, 1), 1300 }; 1301 1302 static const struct snd_kcontrol_new rt5682_dac_r_mix[] = { 1303 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5682_AD_DA_MIXER, 1304 RT5682_M_ADCMIX_R_SFT, 1, 1), 1305 SOC_DAPM_SINGLE("DAC1 Switch", RT5682_AD_DA_MIXER, 1306 RT5682_M_DAC1_R_SFT, 1, 1), 1307 }; 1308 1309 static const struct snd_kcontrol_new rt5682_sto1_dac_l_mix[] = { 1310 SOC_DAPM_SINGLE("DAC L1 Switch", RT5682_STO1_DAC_MIXER, 1311 RT5682_M_DAC_L1_STO_L_SFT, 1, 1), 1312 SOC_DAPM_SINGLE("DAC R1 Switch", RT5682_STO1_DAC_MIXER, 1313 RT5682_M_DAC_R1_STO_L_SFT, 1, 1), 1314 }; 1315 1316 static const struct snd_kcontrol_new rt5682_sto1_dac_r_mix[] = { 1317 SOC_DAPM_SINGLE("DAC L1 Switch", RT5682_STO1_DAC_MIXER, 1318 RT5682_M_DAC_L1_STO_R_SFT, 1, 1), 1319 SOC_DAPM_SINGLE("DAC R1 Switch", RT5682_STO1_DAC_MIXER, 1320 RT5682_M_DAC_R1_STO_R_SFT, 1, 1), 1321 }; 1322 1323 /* Analog Input Mixer */ 1324 static const struct snd_kcontrol_new rt5682_rec1_l_mix[] = { 1325 SOC_DAPM_SINGLE("CBJ Switch", RT5682_REC_MIXER, 1326 RT5682_M_CBJ_RM1_L_SFT, 1, 1), 1327 }; 1328 1329 /* STO1 ADC1 Source */ 1330 /* MX-26 [13] [5] */ 1331 static const char * const rt5682_sto1_adc1_src[] = { 1332 "DAC MIX", "ADC" 1333 }; 1334 1335 static SOC_ENUM_SINGLE_DECL( 1336 rt5682_sto1_adc1l_enum, RT5682_STO1_ADC_MIXER, 1337 RT5682_STO1_ADC1L_SRC_SFT, rt5682_sto1_adc1_src); 1338 1339 static const struct snd_kcontrol_new rt5682_sto1_adc1l_mux = 1340 SOC_DAPM_ENUM("Stereo1 ADC1L Source", rt5682_sto1_adc1l_enum); 1341 1342 static SOC_ENUM_SINGLE_DECL( 1343 rt5682_sto1_adc1r_enum, RT5682_STO1_ADC_MIXER, 1344 RT5682_STO1_ADC1R_SRC_SFT, rt5682_sto1_adc1_src); 1345 1346 static const struct snd_kcontrol_new rt5682_sto1_adc1r_mux = 1347 SOC_DAPM_ENUM("Stereo1 ADC1L Source", rt5682_sto1_adc1r_enum); 1348 1349 /* STO1 ADC Source */ 1350 /* MX-26 [11:10] [3:2] */ 1351 static const char * const rt5682_sto1_adc_src[] = { 1352 "ADC1 L", "ADC1 R" 1353 }; 1354 1355 static SOC_ENUM_SINGLE_DECL( 1356 rt5682_sto1_adcl_enum, RT5682_STO1_ADC_MIXER, 1357 RT5682_STO1_ADCL_SRC_SFT, rt5682_sto1_adc_src); 1358 1359 static const struct snd_kcontrol_new rt5682_sto1_adcl_mux = 1360 SOC_DAPM_ENUM("Stereo1 ADCL Source", rt5682_sto1_adcl_enum); 1361 1362 static SOC_ENUM_SINGLE_DECL( 1363 rt5682_sto1_adcr_enum, RT5682_STO1_ADC_MIXER, 1364 RT5682_STO1_ADCR_SRC_SFT, rt5682_sto1_adc_src); 1365 1366 static const struct snd_kcontrol_new rt5682_sto1_adcr_mux = 1367 SOC_DAPM_ENUM("Stereo1 ADCR Source", rt5682_sto1_adcr_enum); 1368 1369 /* STO1 ADC2 Source */ 1370 /* MX-26 [12] [4] */ 1371 static const char * const rt5682_sto1_adc2_src[] = { 1372 "DAC MIX", "DMIC" 1373 }; 1374 1375 static SOC_ENUM_SINGLE_DECL( 1376 rt5682_sto1_adc2l_enum, RT5682_STO1_ADC_MIXER, 1377 RT5682_STO1_ADC2L_SRC_SFT, rt5682_sto1_adc2_src); 1378 1379 static const struct snd_kcontrol_new rt5682_sto1_adc2l_mux = 1380 SOC_DAPM_ENUM("Stereo1 ADC2L Source", rt5682_sto1_adc2l_enum); 1381 1382 static SOC_ENUM_SINGLE_DECL( 1383 rt5682_sto1_adc2r_enum, RT5682_STO1_ADC_MIXER, 1384 RT5682_STO1_ADC2R_SRC_SFT, rt5682_sto1_adc2_src); 1385 1386 static const struct snd_kcontrol_new rt5682_sto1_adc2r_mux = 1387 SOC_DAPM_ENUM("Stereo1 ADC2R Source", rt5682_sto1_adc2r_enum); 1388 1389 /* MX-79 [6:4] I2S1 ADC data location */ 1390 static const unsigned int rt5682_if1_adc_slot_values[] = { 1391 0, 1392 2, 1393 4, 1394 6, 1395 }; 1396 1397 static const char * const rt5682_if1_adc_slot_src[] = { 1398 "Slot 0", "Slot 2", "Slot 4", "Slot 6" 1399 }; 1400 1401 static SOC_VALUE_ENUM_SINGLE_DECL(rt5682_if1_adc_slot_enum, 1402 RT5682_TDM_CTRL, RT5682_TDM_ADC_LCA_SFT, RT5682_TDM_ADC_LCA_MASK, 1403 rt5682_if1_adc_slot_src, rt5682_if1_adc_slot_values); 1404 1405 static const struct snd_kcontrol_new rt5682_if1_adc_slot_mux = 1406 SOC_DAPM_ENUM("IF1 ADC Slot location", rt5682_if1_adc_slot_enum); 1407 1408 /* Analog DAC L1 Source, Analog DAC R1 Source*/ 1409 /* MX-2B [4], MX-2B [0]*/ 1410 static const char * const rt5682_alg_dac1_src[] = { 1411 "Stereo1 DAC Mixer", "DAC1" 1412 }; 1413 1414 static SOC_ENUM_SINGLE_DECL( 1415 rt5682_alg_dac_l1_enum, RT5682_A_DAC1_MUX, 1416 RT5682_A_DACL1_SFT, rt5682_alg_dac1_src); 1417 1418 static const struct snd_kcontrol_new rt5682_alg_dac_l1_mux = 1419 SOC_DAPM_ENUM("Analog DAC L1 Source", rt5682_alg_dac_l1_enum); 1420 1421 static SOC_ENUM_SINGLE_DECL( 1422 rt5682_alg_dac_r1_enum, RT5682_A_DAC1_MUX, 1423 RT5682_A_DACR1_SFT, rt5682_alg_dac1_src); 1424 1425 static const struct snd_kcontrol_new rt5682_alg_dac_r1_mux = 1426 SOC_DAPM_ENUM("Analog DAC R1 Source", rt5682_alg_dac_r1_enum); 1427 1428 /* Out Switch */ 1429 static const struct snd_kcontrol_new hpol_switch = 1430 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5682_HP_CTRL_1, 1431 RT5682_L_MUTE_SFT, 1, 1); 1432 static const struct snd_kcontrol_new hpor_switch = 1433 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5682_HP_CTRL_1, 1434 RT5682_R_MUTE_SFT, 1, 1); 1435 1436 static int rt5682_charge_pump_event(struct snd_soc_dapm_widget *w, 1437 struct snd_kcontrol *kcontrol, int event) 1438 { 1439 struct snd_soc_component *component = 1440 snd_soc_dapm_to_component(w->dapm); 1441 1442 switch (event) { 1443 case SND_SOC_DAPM_PRE_PMU: 1444 snd_soc_component_update_bits(component, 1445 RT5682_HP_CHARGE_PUMP_1, RT5682_PM_HP_MASK, RT5682_PM_HP_HV); 1446 break; 1447 case SND_SOC_DAPM_POST_PMD: 1448 snd_soc_component_update_bits(component, 1449 RT5682_HP_CHARGE_PUMP_1, RT5682_PM_HP_MASK, RT5682_PM_HP_LV); 1450 break; 1451 default: 1452 return 0; 1453 } 1454 1455 return 0; 1456 } 1457 1458 static int rt5682_hp_event(struct snd_soc_dapm_widget *w, 1459 struct snd_kcontrol *kcontrol, int event) 1460 { 1461 struct snd_soc_component *component = 1462 snd_soc_dapm_to_component(w->dapm); 1463 1464 switch (event) { 1465 case SND_SOC_DAPM_PRE_PMU: 1466 snd_soc_component_write(component, 1467 RT5682_HP_LOGIC_CTRL_2, 0x0012); 1468 snd_soc_component_write(component, 1469 RT5682_HP_CTRL_2, 0x6000); 1470 snd_soc_component_update_bits(component, 1471 RT5682_DEPOP_1, 0x60, 0x60); 1472 snd_soc_component_update_bits(component, 1473 RT5682_DAC_ADC_DIG_VOL1, 0x00c0, 0x0080); 1474 break; 1475 1476 case SND_SOC_DAPM_POST_PMD: 1477 snd_soc_component_update_bits(component, 1478 RT5682_DEPOP_1, 0x60, 0x0); 1479 snd_soc_component_write(component, 1480 RT5682_HP_CTRL_2, 0x0000); 1481 snd_soc_component_update_bits(component, 1482 RT5682_DAC_ADC_DIG_VOL1, 0x00c0, 0x0000); 1483 break; 1484 1485 default: 1486 return 0; 1487 } 1488 1489 return 0; 1490 1491 } 1492 1493 static int set_dmic_power(struct snd_soc_dapm_widget *w, 1494 struct snd_kcontrol *kcontrol, int event) 1495 { 1496 switch (event) { 1497 case SND_SOC_DAPM_POST_PMU: 1498 /*Add delay to avoid pop noise*/ 1499 msleep(150); 1500 break; 1501 1502 default: 1503 return 0; 1504 } 1505 1506 return 0; 1507 } 1508 1509 static int rt5655_set_verf(struct snd_soc_dapm_widget *w, 1510 struct snd_kcontrol *kcontrol, int event) 1511 { 1512 struct snd_soc_component *component = 1513 snd_soc_dapm_to_component(w->dapm); 1514 1515 switch (event) { 1516 case SND_SOC_DAPM_PRE_PMU: 1517 switch (w->shift) { 1518 case RT5682_PWR_VREF1_BIT: 1519 snd_soc_component_update_bits(component, 1520 RT5682_PWR_ANLG_1, RT5682_PWR_FV1, 0); 1521 break; 1522 1523 case RT5682_PWR_VREF2_BIT: 1524 snd_soc_component_update_bits(component, 1525 RT5682_PWR_ANLG_1, RT5682_PWR_FV2, 0); 1526 break; 1527 1528 default: 1529 break; 1530 } 1531 break; 1532 1533 case SND_SOC_DAPM_POST_PMU: 1534 usleep_range(15000, 20000); 1535 switch (w->shift) { 1536 case RT5682_PWR_VREF1_BIT: 1537 snd_soc_component_update_bits(component, 1538 RT5682_PWR_ANLG_1, RT5682_PWR_FV1, 1539 RT5682_PWR_FV1); 1540 break; 1541 1542 case RT5682_PWR_VREF2_BIT: 1543 snd_soc_component_update_bits(component, 1544 RT5682_PWR_ANLG_1, RT5682_PWR_FV2, 1545 RT5682_PWR_FV2); 1546 break; 1547 1548 default: 1549 break; 1550 } 1551 break; 1552 1553 default: 1554 return 0; 1555 } 1556 1557 return 0; 1558 } 1559 1560 static const unsigned int rt5682_adcdat_pin_values[] = { 1561 1, 1562 3, 1563 }; 1564 1565 static const char * const rt5682_adcdat_pin_select[] = { 1566 "ADCDAT1", 1567 "ADCDAT2", 1568 }; 1569 1570 static SOC_VALUE_ENUM_SINGLE_DECL(rt5682_adcdat_pin_enum, 1571 RT5682_GPIO_CTRL_1, RT5682_GP4_PIN_SFT, RT5682_GP4_PIN_MASK, 1572 rt5682_adcdat_pin_select, rt5682_adcdat_pin_values); 1573 1574 static const struct snd_kcontrol_new rt5682_adcdat_pin_ctrl = 1575 SOC_DAPM_ENUM("ADCDAT", rt5682_adcdat_pin_enum); 1576 1577 static const struct snd_soc_dapm_widget rt5682_dapm_widgets[] = { 1578 SND_SOC_DAPM_SUPPLY("LDO2", RT5682_PWR_ANLG_3, RT5682_PWR_LDO2_BIT, 1579 0, NULL, 0), 1580 SND_SOC_DAPM_SUPPLY("PLL1", RT5682_PWR_ANLG_3, RT5682_PWR_PLL_BIT, 1581 0, NULL, 0), 1582 SND_SOC_DAPM_SUPPLY("PLL2B", RT5682_PWR_ANLG_3, RT5682_PWR_PLL2B_BIT, 1583 0, NULL, 0), 1584 SND_SOC_DAPM_SUPPLY("PLL2F", RT5682_PWR_ANLG_3, RT5682_PWR_PLL2F_BIT, 1585 0, NULL, 0), 1586 SND_SOC_DAPM_SUPPLY("Vref1", RT5682_PWR_ANLG_1, RT5682_PWR_VREF1_BIT, 0, 1587 rt5655_set_verf, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), 1588 SND_SOC_DAPM_SUPPLY("Vref2", RT5682_PWR_ANLG_1, RT5682_PWR_VREF2_BIT, 0, 1589 rt5655_set_verf, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), 1590 1591 /* ASRC */ 1592 SND_SOC_DAPM_SUPPLY_S("DAC STO1 ASRC", 1, RT5682_PLL_TRACK_1, 1593 RT5682_DAC_STO1_ASRC_SFT, 0, NULL, 0), 1594 SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5682_PLL_TRACK_1, 1595 RT5682_ADC_STO1_ASRC_SFT, 0, NULL, 0), 1596 SND_SOC_DAPM_SUPPLY_S("AD ASRC", 1, RT5682_PLL_TRACK_1, 1597 RT5682_AD_ASRC_SFT, 0, NULL, 0), 1598 SND_SOC_DAPM_SUPPLY_S("DA ASRC", 1, RT5682_PLL_TRACK_1, 1599 RT5682_DA_ASRC_SFT, 0, NULL, 0), 1600 SND_SOC_DAPM_SUPPLY_S("DMIC ASRC", 1, RT5682_PLL_TRACK_1, 1601 RT5682_DMIC_ASRC_SFT, 0, NULL, 0), 1602 1603 /* Input Side */ 1604 SND_SOC_DAPM_SUPPLY("MICBIAS1", RT5682_PWR_ANLG_2, RT5682_PWR_MB1_BIT, 1605 0, NULL, 0), 1606 SND_SOC_DAPM_SUPPLY("MICBIAS2", RT5682_PWR_ANLG_2, RT5682_PWR_MB2_BIT, 1607 0, NULL, 0), 1608 1609 /* Input Lines */ 1610 SND_SOC_DAPM_INPUT("DMIC L1"), 1611 SND_SOC_DAPM_INPUT("DMIC R1"), 1612 1613 SND_SOC_DAPM_INPUT("IN1P"), 1614 1615 SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0, 1616 set_dmic_clk, SND_SOC_DAPM_PRE_PMU), 1617 SND_SOC_DAPM_SUPPLY("DMIC1 Power", RT5682_DMIC_CTRL_1, 1618 RT5682_DMIC_1_EN_SFT, 0, set_dmic_power, SND_SOC_DAPM_POST_PMU), 1619 1620 /* Boost */ 1621 SND_SOC_DAPM_PGA("BST1 CBJ", SND_SOC_NOPM, 1622 0, 0, NULL, 0), 1623 1624 SND_SOC_DAPM_SUPPLY("CBJ Power", RT5682_PWR_ANLG_3, 1625 RT5682_PWR_CBJ_BIT, 0, NULL, 0), 1626 1627 /* REC Mixer */ 1628 SND_SOC_DAPM_MIXER("RECMIX1L", SND_SOC_NOPM, 0, 0, rt5682_rec1_l_mix, 1629 ARRAY_SIZE(rt5682_rec1_l_mix)), 1630 SND_SOC_DAPM_SUPPLY("RECMIX1L Power", RT5682_PWR_ANLG_2, 1631 RT5682_PWR_RM1_L_BIT, 0, NULL, 0), 1632 1633 /* ADCs */ 1634 SND_SOC_DAPM_ADC("ADC1 L", NULL, SND_SOC_NOPM, 0, 0), 1635 SND_SOC_DAPM_ADC("ADC1 R", NULL, SND_SOC_NOPM, 0, 0), 1636 1637 SND_SOC_DAPM_SUPPLY("ADC1 L Power", RT5682_PWR_DIG_1, 1638 RT5682_PWR_ADC_L1_BIT, 0, NULL, 0), 1639 SND_SOC_DAPM_SUPPLY("ADC1 R Power", RT5682_PWR_DIG_1, 1640 RT5682_PWR_ADC_R1_BIT, 0, NULL, 0), 1641 SND_SOC_DAPM_SUPPLY("ADC1 clock", RT5682_CHOP_ADC, 1642 RT5682_CKGEN_ADC1_SFT, 0, NULL, 0), 1643 1644 /* ADC Mux */ 1645 SND_SOC_DAPM_MUX("Stereo1 ADC L1 Mux", SND_SOC_NOPM, 0, 0, 1646 &rt5682_sto1_adc1l_mux), 1647 SND_SOC_DAPM_MUX("Stereo1 ADC R1 Mux", SND_SOC_NOPM, 0, 0, 1648 &rt5682_sto1_adc1r_mux), 1649 SND_SOC_DAPM_MUX("Stereo1 ADC L2 Mux", SND_SOC_NOPM, 0, 0, 1650 &rt5682_sto1_adc2l_mux), 1651 SND_SOC_DAPM_MUX("Stereo1 ADC R2 Mux", SND_SOC_NOPM, 0, 0, 1652 &rt5682_sto1_adc2r_mux), 1653 SND_SOC_DAPM_MUX("Stereo1 ADC L Mux", SND_SOC_NOPM, 0, 0, 1654 &rt5682_sto1_adcl_mux), 1655 SND_SOC_DAPM_MUX("Stereo1 ADC R Mux", SND_SOC_NOPM, 0, 0, 1656 &rt5682_sto1_adcr_mux), 1657 SND_SOC_DAPM_MUX("IF1_ADC Mux", SND_SOC_NOPM, 0, 0, 1658 &rt5682_if1_adc_slot_mux), 1659 1660 /* ADC Mixer */ 1661 SND_SOC_DAPM_SUPPLY("ADC Stereo1 Filter", RT5682_PWR_DIG_2, 1662 RT5682_PWR_ADC_S1F_BIT, 0, set_filter_clk, 1663 SND_SOC_DAPM_PRE_PMU), 1664 SND_SOC_DAPM_MIXER("Stereo1 ADC MIXL", RT5682_STO1_ADC_DIG_VOL, 1665 RT5682_L_MUTE_SFT, 1, rt5682_sto1_adc_l_mix, 1666 ARRAY_SIZE(rt5682_sto1_adc_l_mix)), 1667 SND_SOC_DAPM_MIXER("Stereo1 ADC MIXR", RT5682_STO1_ADC_DIG_VOL, 1668 RT5682_R_MUTE_SFT, 1, rt5682_sto1_adc_r_mix, 1669 ARRAY_SIZE(rt5682_sto1_adc_r_mix)), 1670 SND_SOC_DAPM_SUPPLY("BTN Detection Mode", RT5682_SAR_IL_CMD_1, 1671 14, 1, NULL, 0), 1672 1673 /* ADC PGA */ 1674 SND_SOC_DAPM_PGA("Stereo1 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 1675 1676 /* Digital Interface */ 1677 SND_SOC_DAPM_SUPPLY("I2S1", RT5682_PWR_DIG_1, RT5682_PWR_I2S1_BIT, 1678 0, NULL, 0), 1679 SND_SOC_DAPM_SUPPLY("I2S2", RT5682_PWR_DIG_1, RT5682_PWR_I2S2_BIT, 1680 0, NULL, 0), 1681 SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0), 1682 SND_SOC_DAPM_PGA("IF1 DAC1 L", SND_SOC_NOPM, 0, 0, NULL, 0), 1683 SND_SOC_DAPM_PGA("IF1 DAC1 R", SND_SOC_NOPM, 0, 0, NULL, 0), 1684 1685 /* Digital Interface Select */ 1686 SND_SOC_DAPM_MUX("IF1 01 ADC Swap Mux", SND_SOC_NOPM, 0, 0, 1687 &rt5682_if1_01_adc_swap_mux), 1688 SND_SOC_DAPM_MUX("IF1 23 ADC Swap Mux", SND_SOC_NOPM, 0, 0, 1689 &rt5682_if1_23_adc_swap_mux), 1690 SND_SOC_DAPM_MUX("IF1 45 ADC Swap Mux", SND_SOC_NOPM, 0, 0, 1691 &rt5682_if1_45_adc_swap_mux), 1692 SND_SOC_DAPM_MUX("IF1 67 ADC Swap Mux", SND_SOC_NOPM, 0, 0, 1693 &rt5682_if1_67_adc_swap_mux), 1694 SND_SOC_DAPM_MUX("IF2 ADC Swap Mux", SND_SOC_NOPM, 0, 0, 1695 &rt5682_if2_adc_swap_mux), 1696 1697 SND_SOC_DAPM_MUX("ADCDAT Mux", SND_SOC_NOPM, 0, 0, 1698 &rt5682_adcdat_pin_ctrl), 1699 1700 /* Audio Interface */ 1701 SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, 1702 RT5682_I2S1_SDP, RT5682_SEL_ADCDAT_SFT, 1), 1703 SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, 1704 RT5682_I2S2_SDP, RT5682_I2S2_PIN_CFG_SFT, 1), 1705 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0), 1706 1707 /* Output Side */ 1708 /* DAC mixer before sound effect */ 1709 SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0, 1710 rt5682_dac_l_mix, ARRAY_SIZE(rt5682_dac_l_mix)), 1711 SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0, 1712 rt5682_dac_r_mix, ARRAY_SIZE(rt5682_dac_r_mix)), 1713 1714 /* DAC channel Mux */ 1715 SND_SOC_DAPM_MUX("DAC L1 Source", SND_SOC_NOPM, 0, 0, 1716 &rt5682_alg_dac_l1_mux), 1717 SND_SOC_DAPM_MUX("DAC R1 Source", SND_SOC_NOPM, 0, 0, 1718 &rt5682_alg_dac_r1_mux), 1719 1720 /* DAC Mixer */ 1721 SND_SOC_DAPM_SUPPLY("DAC Stereo1 Filter", RT5682_PWR_DIG_2, 1722 RT5682_PWR_DAC_S1F_BIT, 0, set_filter_clk, 1723 SND_SOC_DAPM_PRE_PMU), 1724 SND_SOC_DAPM_MIXER("Stereo1 DAC MIXL", SND_SOC_NOPM, 0, 0, 1725 rt5682_sto1_dac_l_mix, ARRAY_SIZE(rt5682_sto1_dac_l_mix)), 1726 SND_SOC_DAPM_MIXER("Stereo1 DAC MIXR", SND_SOC_NOPM, 0, 0, 1727 rt5682_sto1_dac_r_mix, ARRAY_SIZE(rt5682_sto1_dac_r_mix)), 1728 1729 /* DACs */ 1730 SND_SOC_DAPM_DAC("DAC L1", NULL, RT5682_PWR_DIG_1, 1731 RT5682_PWR_DAC_L1_BIT, 0), 1732 SND_SOC_DAPM_DAC("DAC R1", NULL, RT5682_PWR_DIG_1, 1733 RT5682_PWR_DAC_R1_BIT, 0), 1734 SND_SOC_DAPM_SUPPLY_S("DAC 1 Clock", 3, RT5682_CHOP_DAC, 1735 RT5682_CKGEN_DAC1_SFT, 0, NULL, 0), 1736 1737 /* HPO */ 1738 SND_SOC_DAPM_PGA_S("HP Amp", 1, SND_SOC_NOPM, 0, 0, rt5682_hp_event, 1739 SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_PRE_PMU), 1740 1741 SND_SOC_DAPM_SUPPLY("HP Amp L", RT5682_PWR_ANLG_1, 1742 RT5682_PWR_HA_L_BIT, 0, NULL, 0), 1743 SND_SOC_DAPM_SUPPLY("HP Amp R", RT5682_PWR_ANLG_1, 1744 RT5682_PWR_HA_R_BIT, 0, NULL, 0), 1745 SND_SOC_DAPM_SUPPLY_S("Charge Pump", 1, RT5682_DEPOP_1, 1746 RT5682_PUMP_EN_SFT, 0, rt5682_charge_pump_event, 1747 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 1748 SND_SOC_DAPM_SUPPLY_S("Capless", 2, RT5682_DEPOP_1, 1749 RT5682_CAPLESS_EN_SFT, 0, NULL, 0), 1750 1751 SND_SOC_DAPM_SWITCH("HPOL Playback", SND_SOC_NOPM, 0, 0, 1752 &hpol_switch), 1753 SND_SOC_DAPM_SWITCH("HPOR Playback", SND_SOC_NOPM, 0, 0, 1754 &hpor_switch), 1755 1756 /* CLK DET */ 1757 SND_SOC_DAPM_SUPPLY("CLKDET SYS", RT5682_CLK_DET, 1758 RT5682_SYS_CLK_DET_SFT, 0, NULL, 0), 1759 SND_SOC_DAPM_SUPPLY("CLKDET PLL1", RT5682_CLK_DET, 1760 RT5682_PLL1_CLK_DET_SFT, 0, NULL, 0), 1761 SND_SOC_DAPM_SUPPLY("CLKDET PLL2", RT5682_CLK_DET, 1762 RT5682_PLL2_CLK_DET_SFT, 0, NULL, 0), 1763 SND_SOC_DAPM_SUPPLY("CLKDET", RT5682_CLK_DET, 1764 RT5682_POW_CLK_DET_SFT, 0, NULL, 0), 1765 1766 /* Output Lines */ 1767 SND_SOC_DAPM_OUTPUT("HPOL"), 1768 SND_SOC_DAPM_OUTPUT("HPOR"), 1769 1770 }; 1771 1772 static const struct snd_soc_dapm_route rt5682_dapm_routes[] = { 1773 /*PLL*/ 1774 {"ADC Stereo1 Filter", NULL, "PLL1", is_sys_clk_from_pll1}, 1775 {"DAC Stereo1 Filter", NULL, "PLL1", is_sys_clk_from_pll1}, 1776 1777 /*ASRC*/ 1778 {"ADC Stereo1 Filter", NULL, "ADC STO1 ASRC", is_using_asrc}, 1779 {"DAC Stereo1 Filter", NULL, "DAC STO1 ASRC", is_using_asrc}, 1780 {"ADC STO1 ASRC", NULL, "AD ASRC"}, 1781 {"ADC STO1 ASRC", NULL, "CLKDET"}, 1782 {"DAC STO1 ASRC", NULL, "DA ASRC"}, 1783 {"DAC STO1 ASRC", NULL, "CLKDET"}, 1784 1785 /*Vref*/ 1786 {"MICBIAS1", NULL, "Vref1"}, 1787 {"MICBIAS1", NULL, "Vref2"}, 1788 {"MICBIAS2", NULL, "Vref1"}, 1789 {"MICBIAS2", NULL, "Vref2"}, 1790 1791 {"CLKDET SYS", NULL, "CLKDET"}, 1792 1793 {"IN1P", NULL, "LDO2"}, 1794 1795 {"BST1 CBJ", NULL, "IN1P"}, 1796 {"BST1 CBJ", NULL, "CBJ Power"}, 1797 {"CBJ Power", NULL, "Vref2"}, 1798 1799 {"RECMIX1L", "CBJ Switch", "BST1 CBJ"}, 1800 {"RECMIX1L", NULL, "RECMIX1L Power"}, 1801 1802 {"ADC1 L", NULL, "RECMIX1L"}, 1803 {"ADC1 L", NULL, "ADC1 L Power"}, 1804 {"ADC1 L", NULL, "ADC1 clock"}, 1805 1806 {"DMIC L1", NULL, "DMIC CLK"}, 1807 {"DMIC L1", NULL, "DMIC1 Power"}, 1808 {"DMIC R1", NULL, "DMIC CLK"}, 1809 {"DMIC R1", NULL, "DMIC1 Power"}, 1810 {"DMIC CLK", NULL, "DMIC ASRC"}, 1811 1812 {"Stereo1 ADC L Mux", "ADC1 L", "ADC1 L"}, 1813 {"Stereo1 ADC L Mux", "ADC1 R", "ADC1 R"}, 1814 {"Stereo1 ADC R Mux", "ADC1 L", "ADC1 L"}, 1815 {"Stereo1 ADC R Mux", "ADC1 R", "ADC1 R"}, 1816 1817 {"Stereo1 ADC L1 Mux", "ADC", "Stereo1 ADC L Mux"}, 1818 {"Stereo1 ADC L1 Mux", "DAC MIX", "Stereo1 DAC MIXL"}, 1819 {"Stereo1 ADC L2 Mux", "DMIC", "DMIC L1"}, 1820 {"Stereo1 ADC L2 Mux", "DAC MIX", "Stereo1 DAC MIXL"}, 1821 1822 {"Stereo1 ADC R1 Mux", "ADC", "Stereo1 ADC R Mux"}, 1823 {"Stereo1 ADC R1 Mux", "DAC MIX", "Stereo1 DAC MIXR"}, 1824 {"Stereo1 ADC R2 Mux", "DMIC", "DMIC R1"}, 1825 {"Stereo1 ADC R2 Mux", "DAC MIX", "Stereo1 DAC MIXR"}, 1826 1827 {"Stereo1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC L1 Mux"}, 1828 {"Stereo1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC L2 Mux"}, 1829 {"Stereo1 ADC MIXL", NULL, "ADC Stereo1 Filter"}, 1830 1831 {"Stereo1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC R1 Mux"}, 1832 {"Stereo1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC R2 Mux"}, 1833 {"Stereo1 ADC MIXR", NULL, "ADC Stereo1 Filter"}, 1834 1835 {"ADC Stereo1 Filter", NULL, "BTN Detection Mode"}, 1836 1837 {"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXL"}, 1838 {"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXR"}, 1839 1840 {"IF1 01 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"}, 1841 {"IF1 01 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"}, 1842 {"IF1 01 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"}, 1843 {"IF1 01 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"}, 1844 {"IF1 23 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"}, 1845 {"IF1 23 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"}, 1846 {"IF1 23 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"}, 1847 {"IF1 23 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"}, 1848 {"IF1 45 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"}, 1849 {"IF1 45 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"}, 1850 {"IF1 45 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"}, 1851 {"IF1 45 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"}, 1852 {"IF1 67 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"}, 1853 {"IF1 67 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"}, 1854 {"IF1 67 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"}, 1855 {"IF1 67 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"}, 1856 1857 {"IF1_ADC Mux", "Slot 0", "IF1 01 ADC Swap Mux"}, 1858 {"IF1_ADC Mux", "Slot 2", "IF1 23 ADC Swap Mux"}, 1859 {"IF1_ADC Mux", "Slot 4", "IF1 45 ADC Swap Mux"}, 1860 {"IF1_ADC Mux", "Slot 6", "IF1 67 ADC Swap Mux"}, 1861 {"IF1_ADC Mux", NULL, "I2S1"}, 1862 {"ADCDAT Mux", "ADCDAT1", "IF1_ADC Mux"}, 1863 {"AIF1TX", NULL, "ADCDAT Mux"}, 1864 {"IF2 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"}, 1865 {"IF2 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"}, 1866 {"IF2 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"}, 1867 {"IF2 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"}, 1868 {"ADCDAT Mux", "ADCDAT2", "IF2 ADC Swap Mux"}, 1869 {"AIF2TX", NULL, "ADCDAT Mux"}, 1870 1871 {"IF1 DAC1 L", NULL, "AIF1RX"}, 1872 {"IF1 DAC1 L", NULL, "I2S1"}, 1873 {"IF1 DAC1 L", NULL, "DAC Stereo1 Filter"}, 1874 {"IF1 DAC1 R", NULL, "AIF1RX"}, 1875 {"IF1 DAC1 R", NULL, "I2S1"}, 1876 {"IF1 DAC1 R", NULL, "DAC Stereo1 Filter"}, 1877 1878 {"DAC1 MIXL", "Stereo ADC Switch", "Stereo1 ADC MIXL"}, 1879 {"DAC1 MIXL", "DAC1 Switch", "IF1 DAC1 L"}, 1880 {"DAC1 MIXR", "Stereo ADC Switch", "Stereo1 ADC MIXR"}, 1881 {"DAC1 MIXR", "DAC1 Switch", "IF1 DAC1 R"}, 1882 1883 {"Stereo1 DAC MIXL", "DAC L1 Switch", "DAC1 MIXL"}, 1884 {"Stereo1 DAC MIXL", "DAC R1 Switch", "DAC1 MIXR"}, 1885 1886 {"Stereo1 DAC MIXR", "DAC R1 Switch", "DAC1 MIXR"}, 1887 {"Stereo1 DAC MIXR", "DAC L1 Switch", "DAC1 MIXL"}, 1888 1889 {"DAC L1 Source", "DAC1", "DAC1 MIXL"}, 1890 {"DAC L1 Source", "Stereo1 DAC Mixer", "Stereo1 DAC MIXL"}, 1891 {"DAC R1 Source", "DAC1", "DAC1 MIXR"}, 1892 {"DAC R1 Source", "Stereo1 DAC Mixer", "Stereo1 DAC MIXR"}, 1893 1894 {"DAC L1", NULL, "DAC L1 Source"}, 1895 {"DAC R1", NULL, "DAC R1 Source"}, 1896 1897 {"DAC L1", NULL, "DAC 1 Clock"}, 1898 {"DAC R1", NULL, "DAC 1 Clock"}, 1899 1900 {"HP Amp", NULL, "DAC L1"}, 1901 {"HP Amp", NULL, "DAC R1"}, 1902 {"HP Amp", NULL, "HP Amp L"}, 1903 {"HP Amp", NULL, "HP Amp R"}, 1904 {"HP Amp", NULL, "Capless"}, 1905 {"HP Amp", NULL, "Charge Pump"}, 1906 {"HP Amp", NULL, "CLKDET SYS"}, 1907 {"HP Amp", NULL, "CBJ Power"}, 1908 {"HP Amp", NULL, "Vref1"}, 1909 {"HP Amp", NULL, "Vref2"}, 1910 {"HPOL Playback", "Switch", "HP Amp"}, 1911 {"HPOR Playback", "Switch", "HP Amp"}, 1912 {"HPOL", NULL, "HPOL Playback"}, 1913 {"HPOR", NULL, "HPOR Playback"}, 1914 }; 1915 1916 static int rt5682_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask, 1917 unsigned int rx_mask, int slots, int slot_width) 1918 { 1919 struct snd_soc_component *component = dai->component; 1920 unsigned int cl, val = 0; 1921 1922 if (tx_mask || rx_mask) 1923 snd_soc_component_update_bits(component, RT5682_TDM_ADDA_CTRL_2, 1924 RT5682_TDM_EN, RT5682_TDM_EN); 1925 else 1926 snd_soc_component_update_bits(component, RT5682_TDM_ADDA_CTRL_2, 1927 RT5682_TDM_EN, 0); 1928 1929 switch (slots) { 1930 case 4: 1931 val |= RT5682_TDM_TX_CH_4; 1932 val |= RT5682_TDM_RX_CH_4; 1933 break; 1934 case 6: 1935 val |= RT5682_TDM_TX_CH_6; 1936 val |= RT5682_TDM_RX_CH_6; 1937 break; 1938 case 8: 1939 val |= RT5682_TDM_TX_CH_8; 1940 val |= RT5682_TDM_RX_CH_8; 1941 break; 1942 case 2: 1943 break; 1944 default: 1945 return -EINVAL; 1946 } 1947 1948 snd_soc_component_update_bits(component, RT5682_TDM_CTRL, 1949 RT5682_TDM_TX_CH_MASK | RT5682_TDM_RX_CH_MASK, val); 1950 1951 switch (slot_width) { 1952 case 8: 1953 if (tx_mask || rx_mask) 1954 return -EINVAL; 1955 cl = RT5682_I2S1_TX_CHL_8 | RT5682_I2S1_RX_CHL_8; 1956 break; 1957 case 16: 1958 val = RT5682_TDM_CL_16; 1959 cl = RT5682_I2S1_TX_CHL_16 | RT5682_I2S1_RX_CHL_16; 1960 break; 1961 case 20: 1962 val = RT5682_TDM_CL_20; 1963 cl = RT5682_I2S1_TX_CHL_20 | RT5682_I2S1_RX_CHL_20; 1964 break; 1965 case 24: 1966 val = RT5682_TDM_CL_24; 1967 cl = RT5682_I2S1_TX_CHL_24 | RT5682_I2S1_RX_CHL_24; 1968 break; 1969 case 32: 1970 val = RT5682_TDM_CL_32; 1971 cl = RT5682_I2S1_TX_CHL_32 | RT5682_I2S1_RX_CHL_32; 1972 break; 1973 default: 1974 return -EINVAL; 1975 } 1976 1977 snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL, 1978 RT5682_TDM_CL_MASK, val); 1979 snd_soc_component_update_bits(component, RT5682_I2S1_SDP, 1980 RT5682_I2S1_TX_CHL_MASK | RT5682_I2S1_RX_CHL_MASK, cl); 1981 1982 return 0; 1983 } 1984 1985 1986 static int rt5682_hw_params(struct snd_pcm_substream *substream, 1987 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) 1988 { 1989 struct snd_soc_component *component = dai->component; 1990 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 1991 unsigned int len_1 = 0, len_2 = 0; 1992 int pre_div, frame_size; 1993 1994 rt5682->lrck[dai->id] = params_rate(params); 1995 pre_div = rl6231_get_clk_info(rt5682->sysclk, rt5682->lrck[dai->id]); 1996 1997 frame_size = snd_soc_params_to_frame_size(params); 1998 if (frame_size < 0) { 1999 dev_err(component->dev, "Unsupported frame size: %d\n", 2000 frame_size); 2001 return -EINVAL; 2002 } 2003 2004 dev_dbg(dai->dev, "lrck is %dHz and pre_div is %d for iis %d\n", 2005 rt5682->lrck[dai->id], pre_div, dai->id); 2006 2007 switch (params_width(params)) { 2008 case 16: 2009 break; 2010 case 20: 2011 len_1 |= RT5682_I2S1_DL_20; 2012 len_2 |= RT5682_I2S2_DL_20; 2013 break; 2014 case 24: 2015 len_1 |= RT5682_I2S1_DL_24; 2016 len_2 |= RT5682_I2S2_DL_24; 2017 break; 2018 case 32: 2019 len_1 |= RT5682_I2S1_DL_32; 2020 len_2 |= RT5682_I2S2_DL_24; 2021 break; 2022 case 8: 2023 len_1 |= RT5682_I2S2_DL_8; 2024 len_2 |= RT5682_I2S2_DL_8; 2025 break; 2026 default: 2027 return -EINVAL; 2028 } 2029 2030 switch (dai->id) { 2031 case RT5682_AIF1: 2032 snd_soc_component_update_bits(component, RT5682_I2S1_SDP, 2033 RT5682_I2S1_DL_MASK, len_1); 2034 if (rt5682->master[RT5682_AIF1]) { 2035 snd_soc_component_update_bits(component, 2036 RT5682_ADDA_CLK_1, RT5682_I2S_M_DIV_MASK, 2037 pre_div << RT5682_I2S_M_DIV_SFT); 2038 } 2039 if (params_channels(params) == 1) /* mono mode */ 2040 snd_soc_component_update_bits(component, 2041 RT5682_I2S1_SDP, RT5682_I2S1_MONO_MASK, 2042 RT5682_I2S1_MONO_EN); 2043 else 2044 snd_soc_component_update_bits(component, 2045 RT5682_I2S1_SDP, RT5682_I2S1_MONO_MASK, 2046 RT5682_I2S1_MONO_DIS); 2047 break; 2048 case RT5682_AIF2: 2049 snd_soc_component_update_bits(component, RT5682_I2S2_SDP, 2050 RT5682_I2S2_DL_MASK, len_2); 2051 if (rt5682->master[RT5682_AIF2]) { 2052 snd_soc_component_update_bits(component, 2053 RT5682_I2S_M_CLK_CTRL_1, RT5682_I2S2_M_PD_MASK, 2054 pre_div << RT5682_I2S2_M_PD_SFT); 2055 } 2056 if (params_channels(params) == 1) /* mono mode */ 2057 snd_soc_component_update_bits(component, 2058 RT5682_I2S2_SDP, RT5682_I2S2_MONO_MASK, 2059 RT5682_I2S2_MONO_EN); 2060 else 2061 snd_soc_component_update_bits(component, 2062 RT5682_I2S2_SDP, RT5682_I2S2_MONO_MASK, 2063 RT5682_I2S2_MONO_DIS); 2064 break; 2065 default: 2066 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id); 2067 return -EINVAL; 2068 } 2069 2070 return 0; 2071 } 2072 2073 static int rt5682_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) 2074 { 2075 struct snd_soc_component *component = dai->component; 2076 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 2077 unsigned int reg_val = 0, tdm_ctrl = 0; 2078 2079 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 2080 case SND_SOC_DAIFMT_CBM_CFM: 2081 rt5682->master[dai->id] = 1; 2082 break; 2083 case SND_SOC_DAIFMT_CBS_CFS: 2084 rt5682->master[dai->id] = 0; 2085 break; 2086 default: 2087 return -EINVAL; 2088 } 2089 2090 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 2091 case SND_SOC_DAIFMT_NB_NF: 2092 break; 2093 case SND_SOC_DAIFMT_IB_NF: 2094 reg_val |= RT5682_I2S_BP_INV; 2095 tdm_ctrl |= RT5682_TDM_S_BP_INV; 2096 break; 2097 case SND_SOC_DAIFMT_NB_IF: 2098 if (dai->id == RT5682_AIF1) 2099 tdm_ctrl |= RT5682_TDM_S_LP_INV | RT5682_TDM_M_BP_INV; 2100 else 2101 return -EINVAL; 2102 break; 2103 case SND_SOC_DAIFMT_IB_IF: 2104 if (dai->id == RT5682_AIF1) 2105 tdm_ctrl |= RT5682_TDM_S_BP_INV | RT5682_TDM_S_LP_INV | 2106 RT5682_TDM_M_BP_INV | RT5682_TDM_M_LP_INV; 2107 else 2108 return -EINVAL; 2109 break; 2110 default: 2111 return -EINVAL; 2112 } 2113 2114 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 2115 case SND_SOC_DAIFMT_I2S: 2116 break; 2117 case SND_SOC_DAIFMT_LEFT_J: 2118 reg_val |= RT5682_I2S_DF_LEFT; 2119 tdm_ctrl |= RT5682_TDM_DF_LEFT; 2120 break; 2121 case SND_SOC_DAIFMT_DSP_A: 2122 reg_val |= RT5682_I2S_DF_PCM_A; 2123 tdm_ctrl |= RT5682_TDM_DF_PCM_A; 2124 break; 2125 case SND_SOC_DAIFMT_DSP_B: 2126 reg_val |= RT5682_I2S_DF_PCM_B; 2127 tdm_ctrl |= RT5682_TDM_DF_PCM_B; 2128 break; 2129 default: 2130 return -EINVAL; 2131 } 2132 2133 switch (dai->id) { 2134 case RT5682_AIF1: 2135 snd_soc_component_update_bits(component, RT5682_I2S1_SDP, 2136 RT5682_I2S_DF_MASK, reg_val); 2137 snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL, 2138 RT5682_TDM_MS_MASK | RT5682_TDM_S_BP_MASK | 2139 RT5682_TDM_DF_MASK | RT5682_TDM_M_BP_MASK | 2140 RT5682_TDM_M_LP_MASK | RT5682_TDM_S_LP_MASK, 2141 tdm_ctrl | rt5682->master[dai->id]); 2142 break; 2143 case RT5682_AIF2: 2144 if (rt5682->master[dai->id] == 0) 2145 reg_val |= RT5682_I2S2_MS_S; 2146 snd_soc_component_update_bits(component, RT5682_I2S2_SDP, 2147 RT5682_I2S2_MS_MASK | RT5682_I2S_BP_MASK | 2148 RT5682_I2S_DF_MASK, reg_val); 2149 break; 2150 default: 2151 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id); 2152 return -EINVAL; 2153 } 2154 return 0; 2155 } 2156 2157 static int rt5682_set_component_sysclk(struct snd_soc_component *component, 2158 int clk_id, int source, unsigned int freq, int dir) 2159 { 2160 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 2161 unsigned int reg_val = 0, src = 0; 2162 2163 if (freq == rt5682->sysclk && clk_id == rt5682->sysclk_src) 2164 return 0; 2165 2166 switch (clk_id) { 2167 case RT5682_SCLK_S_MCLK: 2168 reg_val |= RT5682_SCLK_SRC_MCLK; 2169 src = RT5682_CLK_SRC_MCLK; 2170 break; 2171 case RT5682_SCLK_S_PLL1: 2172 reg_val |= RT5682_SCLK_SRC_PLL1; 2173 src = RT5682_CLK_SRC_PLL1; 2174 break; 2175 case RT5682_SCLK_S_PLL2: 2176 reg_val |= RT5682_SCLK_SRC_PLL2; 2177 src = RT5682_CLK_SRC_PLL2; 2178 break; 2179 case RT5682_SCLK_S_RCCLK: 2180 reg_val |= RT5682_SCLK_SRC_RCCLK; 2181 src = RT5682_CLK_SRC_RCCLK; 2182 break; 2183 default: 2184 dev_err(component->dev, "Invalid clock id (%d)\n", clk_id); 2185 return -EINVAL; 2186 } 2187 snd_soc_component_update_bits(component, RT5682_GLB_CLK, 2188 RT5682_SCLK_SRC_MASK, reg_val); 2189 2190 if (rt5682->master[RT5682_AIF2]) { 2191 snd_soc_component_update_bits(component, 2192 RT5682_I2S_M_CLK_CTRL_1, RT5682_I2S2_SRC_MASK, 2193 src << RT5682_I2S2_SRC_SFT); 2194 } 2195 2196 rt5682->sysclk = freq; 2197 rt5682->sysclk_src = clk_id; 2198 2199 dev_dbg(component->dev, "Sysclk is %dHz and clock id is %d\n", 2200 freq, clk_id); 2201 2202 return 0; 2203 } 2204 2205 static int rt5682_set_component_pll(struct snd_soc_component *component, 2206 int pll_id, int source, unsigned int freq_in, 2207 unsigned int freq_out) 2208 { 2209 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 2210 struct rl6231_pll_code pll_code; 2211 int ret; 2212 2213 if (source == rt5682->pll_src && freq_in == rt5682->pll_in && 2214 freq_out == rt5682->pll_out) 2215 return 0; 2216 2217 if (!freq_in || !freq_out) { 2218 dev_dbg(component->dev, "PLL disabled\n"); 2219 2220 rt5682->pll_in = 0; 2221 rt5682->pll_out = 0; 2222 snd_soc_component_update_bits(component, RT5682_GLB_CLK, 2223 RT5682_SCLK_SRC_MASK, RT5682_SCLK_SRC_MCLK); 2224 return 0; 2225 } 2226 2227 switch (source) { 2228 case RT5682_PLL1_S_MCLK: 2229 snd_soc_component_update_bits(component, RT5682_GLB_CLK, 2230 RT5682_PLL1_SRC_MASK, RT5682_PLL1_SRC_MCLK); 2231 break; 2232 case RT5682_PLL1_S_BCLK1: 2233 snd_soc_component_update_bits(component, RT5682_GLB_CLK, 2234 RT5682_PLL1_SRC_MASK, RT5682_PLL1_SRC_BCLK1); 2235 break; 2236 default: 2237 dev_err(component->dev, "Unknown PLL Source %d\n", source); 2238 return -EINVAL; 2239 } 2240 2241 ret = rl6231_pll_calc(freq_in, freq_out, &pll_code); 2242 if (ret < 0) { 2243 dev_err(component->dev, "Unsupport input clock %d\n", freq_in); 2244 return ret; 2245 } 2246 2247 dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n", 2248 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code), 2249 pll_code.n_code, pll_code.k_code); 2250 2251 snd_soc_component_write(component, RT5682_PLL_CTRL_1, 2252 pll_code.n_code << RT5682_PLL_N_SFT | pll_code.k_code); 2253 snd_soc_component_write(component, RT5682_PLL_CTRL_2, 2254 (pll_code.m_bp ? 0 : pll_code.m_code) << RT5682_PLL_M_SFT | 2255 pll_code.m_bp << RT5682_PLL_M_BP_SFT | RT5682_PLL_RST); 2256 2257 rt5682->pll_in = freq_in; 2258 rt5682->pll_out = freq_out; 2259 rt5682->pll_src = source; 2260 2261 return 0; 2262 } 2263 2264 static int rt5682_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio) 2265 { 2266 struct snd_soc_component *component = dai->component; 2267 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 2268 2269 rt5682->bclk[dai->id] = ratio; 2270 2271 switch (ratio) { 2272 case 64: 2273 snd_soc_component_update_bits(component, RT5682_ADDA_CLK_2, 2274 RT5682_I2S2_BCLK_MS2_MASK, 2275 RT5682_I2S2_BCLK_MS2_64); 2276 break; 2277 case 32: 2278 snd_soc_component_update_bits(component, RT5682_ADDA_CLK_2, 2279 RT5682_I2S2_BCLK_MS2_MASK, 2280 RT5682_I2S2_BCLK_MS2_32); 2281 break; 2282 default: 2283 dev_err(dai->dev, "Invalid bclk ratio %d\n", ratio); 2284 return -EINVAL; 2285 } 2286 2287 return 0; 2288 } 2289 2290 static int rt5682_set_bias_level(struct snd_soc_component *component, 2291 enum snd_soc_bias_level level) 2292 { 2293 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 2294 2295 switch (level) { 2296 case SND_SOC_BIAS_PREPARE: 2297 regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_1, 2298 RT5682_PWR_MB | RT5682_PWR_BG, 2299 RT5682_PWR_MB | RT5682_PWR_BG); 2300 regmap_update_bits(rt5682->regmap, RT5682_PWR_DIG_1, 2301 RT5682_DIG_GATE_CTRL | RT5682_PWR_LDO, 2302 RT5682_DIG_GATE_CTRL | RT5682_PWR_LDO); 2303 break; 2304 2305 case SND_SOC_BIAS_STANDBY: 2306 regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_1, 2307 RT5682_PWR_MB, RT5682_PWR_MB); 2308 regmap_update_bits(rt5682->regmap, RT5682_PWR_DIG_1, 2309 RT5682_DIG_GATE_CTRL, RT5682_DIG_GATE_CTRL); 2310 break; 2311 case SND_SOC_BIAS_OFF: 2312 regmap_update_bits(rt5682->regmap, RT5682_PWR_DIG_1, 2313 RT5682_DIG_GATE_CTRL | RT5682_PWR_LDO, 0); 2314 regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_1, 2315 RT5682_PWR_MB | RT5682_PWR_BG, 0); 2316 break; 2317 2318 default: 2319 break; 2320 } 2321 2322 return 0; 2323 } 2324 2325 static int rt5682_probe(struct snd_soc_component *component) 2326 { 2327 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 2328 2329 rt5682->component = component; 2330 2331 return 0; 2332 } 2333 2334 static void rt5682_remove(struct snd_soc_component *component) 2335 { 2336 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 2337 2338 rt5682_reset(rt5682->regmap); 2339 } 2340 2341 #ifdef CONFIG_PM 2342 static int rt5682_suspend(struct snd_soc_component *component) 2343 { 2344 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 2345 2346 regcache_cache_only(rt5682->regmap, true); 2347 regcache_mark_dirty(rt5682->regmap); 2348 return 0; 2349 } 2350 2351 static int rt5682_resume(struct snd_soc_component *component) 2352 { 2353 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 2354 2355 regcache_cache_only(rt5682->regmap, false); 2356 regcache_sync(rt5682->regmap); 2357 2358 return 0; 2359 } 2360 #else 2361 #define rt5682_suspend NULL 2362 #define rt5682_resume NULL 2363 #endif 2364 2365 #define RT5682_STEREO_RATES SNDRV_PCM_RATE_8000_192000 2366 #define RT5682_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ 2367 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8) 2368 2369 static const struct snd_soc_dai_ops rt5682_aif1_dai_ops = { 2370 .hw_params = rt5682_hw_params, 2371 .set_fmt = rt5682_set_dai_fmt, 2372 .set_tdm_slot = rt5682_set_tdm_slot, 2373 }; 2374 2375 static const struct snd_soc_dai_ops rt5682_aif2_dai_ops = { 2376 .hw_params = rt5682_hw_params, 2377 .set_fmt = rt5682_set_dai_fmt, 2378 .set_bclk_ratio = rt5682_set_bclk_ratio, 2379 }; 2380 2381 static struct snd_soc_dai_driver rt5682_dai[] = { 2382 { 2383 .name = "rt5682-aif1", 2384 .id = RT5682_AIF1, 2385 .playback = { 2386 .stream_name = "AIF1 Playback", 2387 .channels_min = 1, 2388 .channels_max = 2, 2389 .rates = RT5682_STEREO_RATES, 2390 .formats = RT5682_FORMATS, 2391 }, 2392 .capture = { 2393 .stream_name = "AIF1 Capture", 2394 .channels_min = 1, 2395 .channels_max = 2, 2396 .rates = RT5682_STEREO_RATES, 2397 .formats = RT5682_FORMATS, 2398 }, 2399 .ops = &rt5682_aif1_dai_ops, 2400 }, 2401 { 2402 .name = "rt5682-aif2", 2403 .id = RT5682_AIF2, 2404 .capture = { 2405 .stream_name = "AIF2 Capture", 2406 .channels_min = 1, 2407 .channels_max = 2, 2408 .rates = RT5682_STEREO_RATES, 2409 .formats = RT5682_FORMATS, 2410 }, 2411 .ops = &rt5682_aif2_dai_ops, 2412 }, 2413 }; 2414 2415 static const struct snd_soc_component_driver soc_component_dev_rt5682 = { 2416 .probe = rt5682_probe, 2417 .remove = rt5682_remove, 2418 .suspend = rt5682_suspend, 2419 .resume = rt5682_resume, 2420 .set_bias_level = rt5682_set_bias_level, 2421 .controls = rt5682_snd_controls, 2422 .num_controls = ARRAY_SIZE(rt5682_snd_controls), 2423 .dapm_widgets = rt5682_dapm_widgets, 2424 .num_dapm_widgets = ARRAY_SIZE(rt5682_dapm_widgets), 2425 .dapm_routes = rt5682_dapm_routes, 2426 .num_dapm_routes = ARRAY_SIZE(rt5682_dapm_routes), 2427 .set_sysclk = rt5682_set_component_sysclk, 2428 .set_pll = rt5682_set_component_pll, 2429 .set_jack = rt5682_set_jack_detect, 2430 .use_pmdown_time = 1, 2431 .endianness = 1, 2432 .non_legacy_dai_naming = 1, 2433 }; 2434 2435 static const struct regmap_config rt5682_regmap = { 2436 .reg_bits = 16, 2437 .val_bits = 16, 2438 .max_register = RT5682_I2C_MODE, 2439 .volatile_reg = rt5682_volatile_register, 2440 .readable_reg = rt5682_readable_register, 2441 .cache_type = REGCACHE_RBTREE, 2442 .reg_defaults = rt5682_reg, 2443 .num_reg_defaults = ARRAY_SIZE(rt5682_reg), 2444 .use_single_read = true, 2445 .use_single_write = true, 2446 }; 2447 2448 static const struct i2c_device_id rt5682_i2c_id[] = { 2449 {"rt5682", 0}, 2450 {} 2451 }; 2452 MODULE_DEVICE_TABLE(i2c, rt5682_i2c_id); 2453 2454 static int rt5682_parse_dt(struct rt5682_priv *rt5682, struct device *dev) 2455 { 2456 2457 device_property_read_u32(dev, "realtek,dmic1-data-pin", 2458 &rt5682->pdata.dmic1_data_pin); 2459 device_property_read_u32(dev, "realtek,dmic1-clk-pin", 2460 &rt5682->pdata.dmic1_clk_pin); 2461 device_property_read_u32(dev, "realtek,jd-src", 2462 &rt5682->pdata.jd_src); 2463 2464 rt5682->pdata.ldo1_en = of_get_named_gpio(dev->of_node, 2465 "realtek,ldo1-en-gpios", 0); 2466 2467 return 0; 2468 } 2469 2470 static void rt5682_calibrate(struct rt5682_priv *rt5682) 2471 { 2472 int value, count; 2473 2474 mutex_lock(&rt5682->calibrate_mutex); 2475 2476 rt5682_reset(rt5682->regmap); 2477 regmap_write(rt5682->regmap, RT5682_PWR_ANLG_1, 0xa2af); 2478 usleep_range(15000, 20000); 2479 regmap_write(rt5682->regmap, RT5682_PWR_ANLG_1, 0xf2af); 2480 regmap_write(rt5682->regmap, RT5682_MICBIAS_2, 0x0300); 2481 regmap_write(rt5682->regmap, RT5682_GLB_CLK, 0x8000); 2482 regmap_write(rt5682->regmap, RT5682_PWR_DIG_1, 0x0100); 2483 regmap_write(rt5682->regmap, RT5682_HP_IMP_SENS_CTRL_19, 0x3800); 2484 regmap_write(rt5682->regmap, RT5682_CHOP_DAC, 0x3000); 2485 regmap_write(rt5682->regmap, RT5682_CALIB_ADC_CTRL, 0x7005); 2486 regmap_write(rt5682->regmap, RT5682_STO1_ADC_MIXER, 0x686c); 2487 regmap_write(rt5682->regmap, RT5682_CAL_REC, 0x0d0d); 2488 regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_2, 0x0321); 2489 regmap_write(rt5682->regmap, RT5682_HP_LOGIC_CTRL_2, 0x0004); 2490 regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_1, 0x7c00); 2491 regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_3, 0x06a1); 2492 regmap_write(rt5682->regmap, RT5682_A_DAC1_MUX, 0x0311); 2493 regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_1, 0x7c00); 2494 2495 regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_1, 0xfc00); 2496 2497 for (count = 0; count < 60; count++) { 2498 regmap_read(rt5682->regmap, RT5682_HP_CALIB_STA_1, &value); 2499 if (!(value & 0x8000)) 2500 break; 2501 2502 usleep_range(10000, 10005); 2503 } 2504 2505 if (count >= 60) 2506 pr_err("HP Calibration Failure\n"); 2507 2508 /* restore settings */ 2509 regmap_write(rt5682->regmap, RT5682_PWR_ANLG_1, 0x02af); 2510 regmap_write(rt5682->regmap, RT5682_MICBIAS_2, 0x0080); 2511 regmap_write(rt5682->regmap, RT5682_GLB_CLK, 0x0000); 2512 regmap_write(rt5682->regmap, RT5682_PWR_DIG_1, 0x0000); 2513 regmap_write(rt5682->regmap, RT5682_CHOP_DAC, 0x2000); 2514 regmap_write(rt5682->regmap, RT5682_CALIB_ADC_CTRL, 0x2005); 2515 regmap_write(rt5682->regmap, RT5682_STO1_ADC_MIXER, 0xc0c4); 2516 2517 mutex_unlock(&rt5682->calibrate_mutex); 2518 2519 } 2520 2521 static int rt5682_i2c_probe(struct i2c_client *i2c, 2522 const struct i2c_device_id *id) 2523 { 2524 struct rt5682_platform_data *pdata = dev_get_platdata(&i2c->dev); 2525 struct rt5682_priv *rt5682; 2526 int i, ret; 2527 unsigned int val; 2528 2529 rt5682 = devm_kzalloc(&i2c->dev, sizeof(struct rt5682_priv), 2530 GFP_KERNEL); 2531 2532 if (rt5682 == NULL) 2533 return -ENOMEM; 2534 2535 i2c_set_clientdata(i2c, rt5682); 2536 2537 if (pdata) 2538 rt5682->pdata = *pdata; 2539 else 2540 rt5682_parse_dt(rt5682, &i2c->dev); 2541 2542 rt5682->regmap = devm_regmap_init_i2c(i2c, &rt5682_regmap); 2543 if (IS_ERR(rt5682->regmap)) { 2544 ret = PTR_ERR(rt5682->regmap); 2545 dev_err(&i2c->dev, "Failed to allocate register map: %d\n", 2546 ret); 2547 return ret; 2548 } 2549 2550 for (i = 0; i < ARRAY_SIZE(rt5682->supplies); i++) 2551 rt5682->supplies[i].supply = rt5682_supply_names[i]; 2552 2553 ret = devm_regulator_bulk_get(&i2c->dev, ARRAY_SIZE(rt5682->supplies), 2554 rt5682->supplies); 2555 if (ret != 0) { 2556 dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret); 2557 return ret; 2558 } 2559 2560 ret = regulator_bulk_enable(ARRAY_SIZE(rt5682->supplies), 2561 rt5682->supplies); 2562 if (ret != 0) { 2563 dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret); 2564 return ret; 2565 } 2566 2567 if (gpio_is_valid(rt5682->pdata.ldo1_en)) { 2568 if (devm_gpio_request_one(&i2c->dev, rt5682->pdata.ldo1_en, 2569 GPIOF_OUT_INIT_HIGH, "rt5682")) 2570 dev_err(&i2c->dev, "Fail gpio_request gpio_ldo\n"); 2571 } 2572 2573 /* Sleep for 300 ms miniumum */ 2574 usleep_range(300000, 350000); 2575 2576 regmap_write(rt5682->regmap, RT5682_I2C_MODE, 0x1); 2577 usleep_range(10000, 15000); 2578 2579 regmap_read(rt5682->regmap, RT5682_DEVICE_ID, &val); 2580 if (val != DEVICE_ID) { 2581 pr_err("Device with ID register %x is not rt5682\n", val); 2582 return -ENODEV; 2583 } 2584 2585 rt5682_reset(rt5682->regmap); 2586 2587 rt5682_calibrate(rt5682); 2588 2589 ret = regmap_multi_reg_write(rt5682->regmap, patch_list, 2590 ARRAY_SIZE(patch_list)); 2591 if (ret != 0) 2592 dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret); 2593 2594 regmap_write(rt5682->regmap, RT5682_DEPOP_1, 0x0000); 2595 2596 /* DMIC pin*/ 2597 if (rt5682->pdata.dmic1_data_pin != RT5682_DMIC1_NULL) { 2598 switch (rt5682->pdata.dmic1_data_pin) { 2599 case RT5682_DMIC1_DATA_GPIO2: /* share with LRCK2 */ 2600 regmap_update_bits(rt5682->regmap, RT5682_DMIC_CTRL_1, 2601 RT5682_DMIC_1_DP_MASK, RT5682_DMIC_1_DP_GPIO2); 2602 regmap_update_bits(rt5682->regmap, RT5682_GPIO_CTRL_1, 2603 RT5682_GP2_PIN_MASK, RT5682_GP2_PIN_DMIC_SDA); 2604 break; 2605 2606 case RT5682_DMIC1_DATA_GPIO5: /* share with DACDAT1 */ 2607 regmap_update_bits(rt5682->regmap, RT5682_DMIC_CTRL_1, 2608 RT5682_DMIC_1_DP_MASK, RT5682_DMIC_1_DP_GPIO5); 2609 regmap_update_bits(rt5682->regmap, RT5682_GPIO_CTRL_1, 2610 RT5682_GP5_PIN_MASK, RT5682_GP5_PIN_DMIC_SDA); 2611 break; 2612 2613 default: 2614 dev_warn(&i2c->dev, "invalid DMIC_DAT pin\n"); 2615 break; 2616 } 2617 2618 switch (rt5682->pdata.dmic1_clk_pin) { 2619 case RT5682_DMIC1_CLK_GPIO1: /* share with IRQ */ 2620 regmap_update_bits(rt5682->regmap, RT5682_GPIO_CTRL_1, 2621 RT5682_GP1_PIN_MASK, RT5682_GP1_PIN_DMIC_CLK); 2622 break; 2623 2624 case RT5682_DMIC1_CLK_GPIO3: /* share with BCLK2 */ 2625 regmap_update_bits(rt5682->regmap, RT5682_GPIO_CTRL_1, 2626 RT5682_GP3_PIN_MASK, RT5682_GP3_PIN_DMIC_CLK); 2627 break; 2628 2629 default: 2630 dev_warn(&i2c->dev, "invalid DMIC_CLK pin\n"); 2631 break; 2632 } 2633 } 2634 2635 regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_1, 2636 RT5682_LDO1_DVO_MASK | RT5682_HP_DRIVER_MASK, 2637 RT5682_LDO1_DVO_12 | RT5682_HP_DRIVER_5X); 2638 regmap_write(rt5682->regmap, RT5682_MICBIAS_2, 0x0380); 2639 regmap_update_bits(rt5682->regmap, RT5682_GPIO_CTRL_1, 2640 RT5682_GP4_PIN_MASK | RT5682_GP5_PIN_MASK, 2641 RT5682_GP4_PIN_ADCDAT1 | RT5682_GP5_PIN_DACDAT1); 2642 regmap_write(rt5682->regmap, RT5682_TEST_MODE_CTRL_1, 0x0000); 2643 regmap_update_bits(rt5682->regmap, RT5682_BIAS_CUR_CTRL_8, 2644 RT5682_HPA_CP_BIAS_CTRL_MASK, RT5682_HPA_CP_BIAS_3UA); 2645 regmap_update_bits(rt5682->regmap, RT5682_CHARGE_PUMP_1, 2646 RT5682_CP_CLK_HP_MASK, RT5682_CP_CLK_HP_300KHZ); 2647 2648 INIT_DELAYED_WORK(&rt5682->jack_detect_work, 2649 rt5682_jack_detect_handler); 2650 INIT_DELAYED_WORK(&rt5682->jd_check_work, 2651 rt5682_jd_check_handler); 2652 2653 mutex_init(&rt5682->calibrate_mutex); 2654 2655 if (i2c->irq) { 2656 ret = devm_request_threaded_irq(&i2c->dev, i2c->irq, NULL, 2657 rt5682_irq, IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING 2658 | IRQF_ONESHOT, "rt5682", rt5682); 2659 if (ret) 2660 dev_err(&i2c->dev, "Failed to reguest IRQ: %d\n", ret); 2661 2662 } 2663 2664 return snd_soc_register_component(&i2c->dev, &soc_component_dev_rt5682, 2665 rt5682_dai, ARRAY_SIZE(rt5682_dai)); 2666 } 2667 2668 static int rt5682_i2c_remove(struct i2c_client *i2c) 2669 { 2670 snd_soc_unregister_component(&i2c->dev); 2671 2672 return 0; 2673 } 2674 2675 static void rt5682_i2c_shutdown(struct i2c_client *client) 2676 { 2677 struct rt5682_priv *rt5682 = i2c_get_clientdata(client); 2678 2679 rt5682_reset(rt5682->regmap); 2680 } 2681 2682 #ifdef CONFIG_OF 2683 static const struct of_device_id rt5682_of_match[] = { 2684 {.compatible = "realtek,rt5682i"}, 2685 {}, 2686 }; 2687 MODULE_DEVICE_TABLE(of, rt5682_of_match); 2688 #endif 2689 2690 #ifdef CONFIG_ACPI 2691 static const struct acpi_device_id rt5682_acpi_match[] = { 2692 {"10EC5682", 0,}, 2693 {}, 2694 }; 2695 MODULE_DEVICE_TABLE(acpi, rt5682_acpi_match); 2696 #endif 2697 2698 static struct i2c_driver rt5682_i2c_driver = { 2699 .driver = { 2700 .name = "rt5682", 2701 .of_match_table = of_match_ptr(rt5682_of_match), 2702 .acpi_match_table = ACPI_PTR(rt5682_acpi_match), 2703 }, 2704 .probe = rt5682_i2c_probe, 2705 .remove = rt5682_i2c_remove, 2706 .shutdown = rt5682_i2c_shutdown, 2707 .id_table = rt5682_i2c_id, 2708 }; 2709 module_i2c_driver(rt5682_i2c_driver); 2710 2711 MODULE_DESCRIPTION("ASoC RT5682 driver"); 2712 MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>"); 2713 MODULE_LICENSE("GPL v2"); 2714