1 // SPDX-License-Identifier: GPL-2.0-only 2 // 3 // rt5682.c -- RT5682 ALSA SoC audio component driver 4 // 5 // Copyright 2018 Realtek Semiconductor Corp. 6 // Author: Bard Liao <bardliao@realtek.com> 7 // 8 9 #include <linux/module.h> 10 #include <linux/moduleparam.h> 11 #include <linux/init.h> 12 #include <linux/delay.h> 13 #include <linux/pm.h> 14 #include <linux/pm_runtime.h> 15 #include <linux/platform_device.h> 16 #include <linux/spi/spi.h> 17 #include <linux/acpi.h> 18 #include <linux/gpio.h> 19 #include <linux/of_gpio.h> 20 #include <linux/mutex.h> 21 #include <sound/core.h> 22 #include <sound/pcm.h> 23 #include <sound/pcm_params.h> 24 #include <sound/jack.h> 25 #include <sound/soc.h> 26 #include <sound/soc-dapm.h> 27 #include <sound/initval.h> 28 #include <sound/tlv.h> 29 #include <sound/rt5682.h> 30 31 #include "rl6231.h" 32 #include "rt5682.h" 33 34 const char *rt5682_supply_names[RT5682_NUM_SUPPLIES] = { 35 "AVDD", 36 "MICVDD", 37 "VBAT", 38 }; 39 EXPORT_SYMBOL_GPL(rt5682_supply_names); 40 41 static const struct reg_sequence patch_list[] = { 42 {RT5682_HP_IMP_SENS_CTRL_19, 0x1000}, 43 {RT5682_DAC_ADC_DIG_VOL1, 0xa020}, 44 {RT5682_I2C_CTRL, 0x000f}, 45 {RT5682_PLL2_INTERNAL, 0x8266}, 46 {RT5682_SAR_IL_CMD_1, 0x22b7}, 47 {RT5682_SAR_IL_CMD_3, 0x0365}, 48 {RT5682_SAR_IL_CMD_6, 0x0110}, 49 {RT5682_CHARGE_PUMP_1, 0x0210}, 50 {RT5682_HP_LOGIC_CTRL_2, 0x0007}, 51 {RT5682_SAR_IL_CMD_2, 0xac00}, 52 {RT5682_CBJ_CTRL_7, 0x0104}, 53 }; 54 55 void rt5682_apply_patch_list(struct rt5682_priv *rt5682, struct device *dev) 56 { 57 int ret; 58 59 ret = regmap_multi_reg_write(rt5682->regmap, patch_list, 60 ARRAY_SIZE(patch_list)); 61 if (ret) 62 dev_warn(dev, "Failed to apply regmap patch: %d\n", ret); 63 } 64 EXPORT_SYMBOL_GPL(rt5682_apply_patch_list); 65 66 const struct reg_default rt5682_reg[RT5682_REG_NUM] = { 67 {0x0002, 0x8080}, 68 {0x0003, 0x8000}, 69 {0x0005, 0x0000}, 70 {0x0006, 0x0000}, 71 {0x0008, 0x800f}, 72 {0x000b, 0x0000}, 73 {0x0010, 0x4040}, 74 {0x0011, 0x0000}, 75 {0x0012, 0x1404}, 76 {0x0013, 0x1000}, 77 {0x0014, 0xa00a}, 78 {0x0015, 0x0404}, 79 {0x0016, 0x0404}, 80 {0x0019, 0xafaf}, 81 {0x001c, 0x2f2f}, 82 {0x001f, 0x0000}, 83 {0x0022, 0x5757}, 84 {0x0023, 0x0039}, 85 {0x0024, 0x000b}, 86 {0x0026, 0xc0c4}, 87 {0x0029, 0x8080}, 88 {0x002a, 0xa0a0}, 89 {0x002b, 0x0300}, 90 {0x0030, 0x0000}, 91 {0x003c, 0x0080}, 92 {0x0044, 0x0c0c}, 93 {0x0049, 0x0000}, 94 {0x0061, 0x0000}, 95 {0x0062, 0x0000}, 96 {0x0063, 0x003f}, 97 {0x0064, 0x0000}, 98 {0x0065, 0x0000}, 99 {0x0066, 0x0030}, 100 {0x0067, 0x0000}, 101 {0x006b, 0x0000}, 102 {0x006c, 0x0000}, 103 {0x006d, 0x2200}, 104 {0x006e, 0x0a10}, 105 {0x0070, 0x8000}, 106 {0x0071, 0x8000}, 107 {0x0073, 0x0000}, 108 {0x0074, 0x0000}, 109 {0x0075, 0x0002}, 110 {0x0076, 0x0001}, 111 {0x0079, 0x0000}, 112 {0x007a, 0x0000}, 113 {0x007b, 0x0000}, 114 {0x007c, 0x0100}, 115 {0x007e, 0x0000}, 116 {0x0080, 0x0000}, 117 {0x0081, 0x0000}, 118 {0x0082, 0x0000}, 119 {0x0083, 0x0000}, 120 {0x0084, 0x0000}, 121 {0x0085, 0x0000}, 122 {0x0086, 0x0005}, 123 {0x0087, 0x0000}, 124 {0x0088, 0x0000}, 125 {0x008c, 0x0003}, 126 {0x008d, 0x0000}, 127 {0x008e, 0x0060}, 128 {0x008f, 0x1000}, 129 {0x0091, 0x0c26}, 130 {0x0092, 0x0073}, 131 {0x0093, 0x0000}, 132 {0x0094, 0x0080}, 133 {0x0098, 0x0000}, 134 {0x009a, 0x0000}, 135 {0x009b, 0x0000}, 136 {0x009c, 0x0000}, 137 {0x009d, 0x0000}, 138 {0x009e, 0x100c}, 139 {0x009f, 0x0000}, 140 {0x00a0, 0x0000}, 141 {0x00a3, 0x0002}, 142 {0x00a4, 0x0001}, 143 {0x00ae, 0x2040}, 144 {0x00af, 0x0000}, 145 {0x00b6, 0x0000}, 146 {0x00b7, 0x0000}, 147 {0x00b8, 0x0000}, 148 {0x00b9, 0x0002}, 149 {0x00be, 0x0000}, 150 {0x00c0, 0x0160}, 151 {0x00c1, 0x82a0}, 152 {0x00c2, 0x0000}, 153 {0x00d0, 0x0000}, 154 {0x00d1, 0x2244}, 155 {0x00d2, 0x3300}, 156 {0x00d3, 0x2200}, 157 {0x00d4, 0x0000}, 158 {0x00d9, 0x0009}, 159 {0x00da, 0x0000}, 160 {0x00db, 0x0000}, 161 {0x00dc, 0x00c0}, 162 {0x00dd, 0x2220}, 163 {0x00de, 0x3131}, 164 {0x00df, 0x3131}, 165 {0x00e0, 0x3131}, 166 {0x00e2, 0x0000}, 167 {0x00e3, 0x4000}, 168 {0x00e4, 0x0aa0}, 169 {0x00e5, 0x3131}, 170 {0x00e6, 0x3131}, 171 {0x00e7, 0x3131}, 172 {0x00e8, 0x3131}, 173 {0x00ea, 0xb320}, 174 {0x00eb, 0x0000}, 175 {0x00f0, 0x0000}, 176 {0x00f1, 0x00d0}, 177 {0x00f2, 0x00d0}, 178 {0x00f6, 0x0000}, 179 {0x00fa, 0x0000}, 180 {0x00fb, 0x0000}, 181 {0x00fc, 0x0000}, 182 {0x00fd, 0x0000}, 183 {0x00fe, 0x10ec}, 184 {0x00ff, 0x6530}, 185 {0x0100, 0xa0a0}, 186 {0x010b, 0x0000}, 187 {0x010c, 0xae00}, 188 {0x010d, 0xaaa0}, 189 {0x010e, 0x8aa2}, 190 {0x010f, 0x02a2}, 191 {0x0110, 0xc000}, 192 {0x0111, 0x04a2}, 193 {0x0112, 0x2800}, 194 {0x0113, 0x0000}, 195 {0x0117, 0x0100}, 196 {0x0125, 0x0410}, 197 {0x0132, 0x6026}, 198 {0x0136, 0x5555}, 199 {0x0138, 0x3700}, 200 {0x013a, 0x2000}, 201 {0x013b, 0x2000}, 202 {0x013c, 0x2005}, 203 {0x013f, 0x0000}, 204 {0x0142, 0x0000}, 205 {0x0145, 0x0002}, 206 {0x0146, 0x0000}, 207 {0x0147, 0x0000}, 208 {0x0148, 0x0000}, 209 {0x0149, 0x0000}, 210 {0x0150, 0x79a1}, 211 {0x0156, 0xaaaa}, 212 {0x0160, 0x4ec0}, 213 {0x0161, 0x0080}, 214 {0x0162, 0x0200}, 215 {0x0163, 0x0800}, 216 {0x0164, 0x0000}, 217 {0x0165, 0x0000}, 218 {0x0166, 0x0000}, 219 {0x0167, 0x000f}, 220 {0x0168, 0x000f}, 221 {0x0169, 0x0021}, 222 {0x0190, 0x413d}, 223 {0x0194, 0x0000}, 224 {0x0195, 0x0000}, 225 {0x0197, 0x0022}, 226 {0x0198, 0x0000}, 227 {0x0199, 0x0000}, 228 {0x01af, 0x0000}, 229 {0x01b0, 0x0400}, 230 {0x01b1, 0x0000}, 231 {0x01b2, 0x0000}, 232 {0x01b3, 0x0000}, 233 {0x01b4, 0x0000}, 234 {0x01b5, 0x0000}, 235 {0x01b6, 0x01c3}, 236 {0x01b7, 0x02a0}, 237 {0x01b8, 0x03e9}, 238 {0x01b9, 0x1389}, 239 {0x01ba, 0xc351}, 240 {0x01bb, 0x0009}, 241 {0x01bc, 0x0018}, 242 {0x01bd, 0x002a}, 243 {0x01be, 0x004c}, 244 {0x01bf, 0x0097}, 245 {0x01c0, 0x433d}, 246 {0x01c2, 0x0000}, 247 {0x01c3, 0x0000}, 248 {0x01c4, 0x0000}, 249 {0x01c5, 0x0000}, 250 {0x01c6, 0x0000}, 251 {0x01c7, 0x0000}, 252 {0x01c8, 0x40af}, 253 {0x01c9, 0x0702}, 254 {0x01ca, 0x0000}, 255 {0x01cb, 0x0000}, 256 {0x01cc, 0x5757}, 257 {0x01cd, 0x5757}, 258 {0x01ce, 0x5757}, 259 {0x01cf, 0x5757}, 260 {0x01d0, 0x5757}, 261 {0x01d1, 0x5757}, 262 {0x01d2, 0x5757}, 263 {0x01d3, 0x5757}, 264 {0x01d4, 0x5757}, 265 {0x01d5, 0x5757}, 266 {0x01d6, 0x0000}, 267 {0x01d7, 0x0008}, 268 {0x01d8, 0x0029}, 269 {0x01d9, 0x3333}, 270 {0x01da, 0x0000}, 271 {0x01db, 0x0004}, 272 {0x01dc, 0x0000}, 273 {0x01de, 0x7c00}, 274 {0x01df, 0x0320}, 275 {0x01e0, 0x06a1}, 276 {0x01e1, 0x0000}, 277 {0x01e2, 0x0000}, 278 {0x01e3, 0x0000}, 279 {0x01e4, 0x0000}, 280 {0x01e6, 0x0001}, 281 {0x01e7, 0x0000}, 282 {0x01e8, 0x0000}, 283 {0x01ea, 0x0000}, 284 {0x01eb, 0x0000}, 285 {0x01ec, 0x0000}, 286 {0x01ed, 0x0000}, 287 {0x01ee, 0x0000}, 288 {0x01ef, 0x0000}, 289 {0x01f0, 0x0000}, 290 {0x01f1, 0x0000}, 291 {0x01f2, 0x0000}, 292 {0x01f3, 0x0000}, 293 {0x01f4, 0x0000}, 294 {0x0210, 0x6297}, 295 {0x0211, 0xa005}, 296 {0x0212, 0x824c}, 297 {0x0213, 0xf7ff}, 298 {0x0214, 0xf24c}, 299 {0x0215, 0x0102}, 300 {0x0216, 0x00a3}, 301 {0x0217, 0x0048}, 302 {0x0218, 0xa2c0}, 303 {0x0219, 0x0400}, 304 {0x021a, 0x00c8}, 305 {0x021b, 0x00c0}, 306 {0x021c, 0x0000}, 307 {0x0250, 0x4500}, 308 {0x0251, 0x40b3}, 309 {0x0252, 0x0000}, 310 {0x0253, 0x0000}, 311 {0x0254, 0x0000}, 312 {0x0255, 0x0000}, 313 {0x0256, 0x0000}, 314 {0x0257, 0x0000}, 315 {0x0258, 0x0000}, 316 {0x0259, 0x0000}, 317 {0x025a, 0x0005}, 318 {0x0270, 0x0000}, 319 {0x02ff, 0x0110}, 320 {0x0300, 0x001f}, 321 {0x0301, 0x032c}, 322 {0x0302, 0x5f21}, 323 {0x0303, 0x4000}, 324 {0x0304, 0x4000}, 325 {0x0305, 0x06d5}, 326 {0x0306, 0x8000}, 327 {0x0307, 0x0700}, 328 {0x0310, 0x4560}, 329 {0x0311, 0xa4a8}, 330 {0x0312, 0x7418}, 331 {0x0313, 0x0000}, 332 {0x0314, 0x0006}, 333 {0x0315, 0xffff}, 334 {0x0316, 0xc400}, 335 {0x0317, 0x0000}, 336 {0x03c0, 0x7e00}, 337 {0x03c1, 0x8000}, 338 {0x03c2, 0x8000}, 339 {0x03c3, 0x8000}, 340 {0x03c4, 0x8000}, 341 {0x03c5, 0x8000}, 342 {0x03c6, 0x8000}, 343 {0x03c7, 0x8000}, 344 {0x03c8, 0x8000}, 345 {0x03c9, 0x8000}, 346 {0x03ca, 0x8000}, 347 {0x03cb, 0x8000}, 348 {0x03cc, 0x8000}, 349 {0x03d0, 0x0000}, 350 {0x03d1, 0x0000}, 351 {0x03d2, 0x0000}, 352 {0x03d3, 0x0000}, 353 {0x03d4, 0x2000}, 354 {0x03d5, 0x2000}, 355 {0x03d6, 0x0000}, 356 {0x03d7, 0x0000}, 357 {0x03d8, 0x2000}, 358 {0x03d9, 0x2000}, 359 {0x03da, 0x2000}, 360 {0x03db, 0x2000}, 361 {0x03dc, 0x0000}, 362 {0x03dd, 0x0000}, 363 {0x03de, 0x0000}, 364 {0x03df, 0x2000}, 365 {0x03e0, 0x0000}, 366 {0x03e1, 0x0000}, 367 {0x03e2, 0x0000}, 368 {0x03e3, 0x0000}, 369 {0x03e4, 0x0000}, 370 {0x03e5, 0x0000}, 371 {0x03e6, 0x0000}, 372 {0x03e7, 0x0000}, 373 {0x03e8, 0x0000}, 374 {0x03e9, 0x0000}, 375 {0x03ea, 0x0000}, 376 {0x03eb, 0x0000}, 377 {0x03ec, 0x0000}, 378 {0x03ed, 0x0000}, 379 {0x03ee, 0x0000}, 380 {0x03ef, 0x0000}, 381 {0x03f0, 0x0800}, 382 {0x03f1, 0x0800}, 383 {0x03f2, 0x0800}, 384 {0x03f3, 0x0800}, 385 }; 386 EXPORT_SYMBOL_GPL(rt5682_reg); 387 388 bool rt5682_volatile_register(struct device *dev, unsigned int reg) 389 { 390 switch (reg) { 391 case RT5682_RESET: 392 case RT5682_CBJ_CTRL_2: 393 case RT5682_INT_ST_1: 394 case RT5682_4BTN_IL_CMD_1: 395 case RT5682_AJD1_CTRL: 396 case RT5682_HP_CALIB_CTRL_1: 397 case RT5682_DEVICE_ID: 398 case RT5682_I2C_MODE: 399 case RT5682_HP_CALIB_CTRL_10: 400 case RT5682_EFUSE_CTRL_2: 401 case RT5682_JD_TOP_VC_VTRL: 402 case RT5682_HP_IMP_SENS_CTRL_19: 403 case RT5682_IL_CMD_1: 404 case RT5682_SAR_IL_CMD_2: 405 case RT5682_SAR_IL_CMD_4: 406 case RT5682_SAR_IL_CMD_10: 407 case RT5682_SAR_IL_CMD_11: 408 case RT5682_EFUSE_CTRL_6...RT5682_EFUSE_CTRL_11: 409 case RT5682_HP_CALIB_STA_1...RT5682_HP_CALIB_STA_11: 410 return true; 411 default: 412 return false; 413 } 414 } 415 EXPORT_SYMBOL_GPL(rt5682_volatile_register); 416 417 bool rt5682_readable_register(struct device *dev, unsigned int reg) 418 { 419 switch (reg) { 420 case RT5682_RESET: 421 case RT5682_VERSION_ID: 422 case RT5682_VENDOR_ID: 423 case RT5682_DEVICE_ID: 424 case RT5682_HP_CTRL_1: 425 case RT5682_HP_CTRL_2: 426 case RT5682_HPL_GAIN: 427 case RT5682_HPR_GAIN: 428 case RT5682_I2C_CTRL: 429 case RT5682_CBJ_BST_CTRL: 430 case RT5682_CBJ_CTRL_1: 431 case RT5682_CBJ_CTRL_2: 432 case RT5682_CBJ_CTRL_3: 433 case RT5682_CBJ_CTRL_4: 434 case RT5682_CBJ_CTRL_5: 435 case RT5682_CBJ_CTRL_6: 436 case RT5682_CBJ_CTRL_7: 437 case RT5682_DAC1_DIG_VOL: 438 case RT5682_STO1_ADC_DIG_VOL: 439 case RT5682_STO1_ADC_BOOST: 440 case RT5682_HP_IMP_GAIN_1: 441 case RT5682_HP_IMP_GAIN_2: 442 case RT5682_SIDETONE_CTRL: 443 case RT5682_STO1_ADC_MIXER: 444 case RT5682_AD_DA_MIXER: 445 case RT5682_STO1_DAC_MIXER: 446 case RT5682_A_DAC1_MUX: 447 case RT5682_DIG_INF2_DATA: 448 case RT5682_REC_MIXER: 449 case RT5682_CAL_REC: 450 case RT5682_ALC_BACK_GAIN: 451 case RT5682_PWR_DIG_1: 452 case RT5682_PWR_DIG_2: 453 case RT5682_PWR_ANLG_1: 454 case RT5682_PWR_ANLG_2: 455 case RT5682_PWR_ANLG_3: 456 case RT5682_PWR_MIXER: 457 case RT5682_PWR_VOL: 458 case RT5682_CLK_DET: 459 case RT5682_RESET_LPF_CTRL: 460 case RT5682_RESET_HPF_CTRL: 461 case RT5682_DMIC_CTRL_1: 462 case RT5682_I2S1_SDP: 463 case RT5682_I2S2_SDP: 464 case RT5682_ADDA_CLK_1: 465 case RT5682_ADDA_CLK_2: 466 case RT5682_I2S1_F_DIV_CTRL_1: 467 case RT5682_I2S1_F_DIV_CTRL_2: 468 case RT5682_TDM_CTRL: 469 case RT5682_TDM_ADDA_CTRL_1: 470 case RT5682_TDM_ADDA_CTRL_2: 471 case RT5682_DATA_SEL_CTRL_1: 472 case RT5682_TDM_TCON_CTRL: 473 case RT5682_GLB_CLK: 474 case RT5682_PLL_CTRL_1: 475 case RT5682_PLL_CTRL_2: 476 case RT5682_PLL_TRACK_1: 477 case RT5682_PLL_TRACK_2: 478 case RT5682_PLL_TRACK_3: 479 case RT5682_PLL_TRACK_4: 480 case RT5682_PLL_TRACK_5: 481 case RT5682_PLL_TRACK_6: 482 case RT5682_PLL_TRACK_11: 483 case RT5682_SDW_REF_CLK: 484 case RT5682_DEPOP_1: 485 case RT5682_DEPOP_2: 486 case RT5682_HP_CHARGE_PUMP_1: 487 case RT5682_HP_CHARGE_PUMP_2: 488 case RT5682_MICBIAS_1: 489 case RT5682_MICBIAS_2: 490 case RT5682_PLL_TRACK_12: 491 case RT5682_PLL_TRACK_14: 492 case RT5682_PLL2_CTRL_1: 493 case RT5682_PLL2_CTRL_2: 494 case RT5682_PLL2_CTRL_3: 495 case RT5682_PLL2_CTRL_4: 496 case RT5682_RC_CLK_CTRL: 497 case RT5682_I2S_M_CLK_CTRL_1: 498 case RT5682_I2S2_F_DIV_CTRL_1: 499 case RT5682_I2S2_F_DIV_CTRL_2: 500 case RT5682_EQ_CTRL_1: 501 case RT5682_EQ_CTRL_2: 502 case RT5682_IRQ_CTRL_1: 503 case RT5682_IRQ_CTRL_2: 504 case RT5682_IRQ_CTRL_3: 505 case RT5682_IRQ_CTRL_4: 506 case RT5682_INT_ST_1: 507 case RT5682_GPIO_CTRL_1: 508 case RT5682_GPIO_CTRL_2: 509 case RT5682_GPIO_CTRL_3: 510 case RT5682_HP_AMP_DET_CTRL_1: 511 case RT5682_HP_AMP_DET_CTRL_2: 512 case RT5682_MID_HP_AMP_DET: 513 case RT5682_LOW_HP_AMP_DET: 514 case RT5682_DELAY_BUF_CTRL: 515 case RT5682_SV_ZCD_1: 516 case RT5682_SV_ZCD_2: 517 case RT5682_IL_CMD_1: 518 case RT5682_IL_CMD_2: 519 case RT5682_IL_CMD_3: 520 case RT5682_IL_CMD_4: 521 case RT5682_IL_CMD_5: 522 case RT5682_IL_CMD_6: 523 case RT5682_4BTN_IL_CMD_1: 524 case RT5682_4BTN_IL_CMD_2: 525 case RT5682_4BTN_IL_CMD_3: 526 case RT5682_4BTN_IL_CMD_4: 527 case RT5682_4BTN_IL_CMD_5: 528 case RT5682_4BTN_IL_CMD_6: 529 case RT5682_4BTN_IL_CMD_7: 530 case RT5682_ADC_STO1_HP_CTRL_1: 531 case RT5682_ADC_STO1_HP_CTRL_2: 532 case RT5682_AJD1_CTRL: 533 case RT5682_JD1_THD: 534 case RT5682_JD2_THD: 535 case RT5682_JD_CTRL_1: 536 case RT5682_DUMMY_1: 537 case RT5682_DUMMY_2: 538 case RT5682_DUMMY_3: 539 case RT5682_DAC_ADC_DIG_VOL1: 540 case RT5682_BIAS_CUR_CTRL_2: 541 case RT5682_BIAS_CUR_CTRL_3: 542 case RT5682_BIAS_CUR_CTRL_4: 543 case RT5682_BIAS_CUR_CTRL_5: 544 case RT5682_BIAS_CUR_CTRL_6: 545 case RT5682_BIAS_CUR_CTRL_7: 546 case RT5682_BIAS_CUR_CTRL_8: 547 case RT5682_BIAS_CUR_CTRL_9: 548 case RT5682_BIAS_CUR_CTRL_10: 549 case RT5682_VREF_REC_OP_FB_CAP_CTRL: 550 case RT5682_CHARGE_PUMP_1: 551 case RT5682_DIG_IN_CTRL_1: 552 case RT5682_PAD_DRIVING_CTRL: 553 case RT5682_SOFT_RAMP_DEPOP: 554 case RT5682_CHOP_DAC: 555 case RT5682_CHOP_ADC: 556 case RT5682_CALIB_ADC_CTRL: 557 case RT5682_VOL_TEST: 558 case RT5682_SPKVDD_DET_STA: 559 case RT5682_TEST_MODE_CTRL_1: 560 case RT5682_TEST_MODE_CTRL_2: 561 case RT5682_TEST_MODE_CTRL_3: 562 case RT5682_TEST_MODE_CTRL_4: 563 case RT5682_TEST_MODE_CTRL_5: 564 case RT5682_PLL1_INTERNAL: 565 case RT5682_PLL2_INTERNAL: 566 case RT5682_STO_NG2_CTRL_1: 567 case RT5682_STO_NG2_CTRL_2: 568 case RT5682_STO_NG2_CTRL_3: 569 case RT5682_STO_NG2_CTRL_4: 570 case RT5682_STO_NG2_CTRL_5: 571 case RT5682_STO_NG2_CTRL_6: 572 case RT5682_STO_NG2_CTRL_7: 573 case RT5682_STO_NG2_CTRL_8: 574 case RT5682_STO_NG2_CTRL_9: 575 case RT5682_STO_NG2_CTRL_10: 576 case RT5682_STO1_DAC_SIL_DET: 577 case RT5682_SIL_PSV_CTRL1: 578 case RT5682_SIL_PSV_CTRL2: 579 case RT5682_SIL_PSV_CTRL3: 580 case RT5682_SIL_PSV_CTRL4: 581 case RT5682_SIL_PSV_CTRL5: 582 case RT5682_HP_IMP_SENS_CTRL_01: 583 case RT5682_HP_IMP_SENS_CTRL_02: 584 case RT5682_HP_IMP_SENS_CTRL_03: 585 case RT5682_HP_IMP_SENS_CTRL_04: 586 case RT5682_HP_IMP_SENS_CTRL_05: 587 case RT5682_HP_IMP_SENS_CTRL_06: 588 case RT5682_HP_IMP_SENS_CTRL_07: 589 case RT5682_HP_IMP_SENS_CTRL_08: 590 case RT5682_HP_IMP_SENS_CTRL_09: 591 case RT5682_HP_IMP_SENS_CTRL_10: 592 case RT5682_HP_IMP_SENS_CTRL_11: 593 case RT5682_HP_IMP_SENS_CTRL_12: 594 case RT5682_HP_IMP_SENS_CTRL_13: 595 case RT5682_HP_IMP_SENS_CTRL_14: 596 case RT5682_HP_IMP_SENS_CTRL_15: 597 case RT5682_HP_IMP_SENS_CTRL_16: 598 case RT5682_HP_IMP_SENS_CTRL_17: 599 case RT5682_HP_IMP_SENS_CTRL_18: 600 case RT5682_HP_IMP_SENS_CTRL_19: 601 case RT5682_HP_IMP_SENS_CTRL_20: 602 case RT5682_HP_IMP_SENS_CTRL_21: 603 case RT5682_HP_IMP_SENS_CTRL_22: 604 case RT5682_HP_IMP_SENS_CTRL_23: 605 case RT5682_HP_IMP_SENS_CTRL_24: 606 case RT5682_HP_IMP_SENS_CTRL_25: 607 case RT5682_HP_IMP_SENS_CTRL_26: 608 case RT5682_HP_IMP_SENS_CTRL_27: 609 case RT5682_HP_IMP_SENS_CTRL_28: 610 case RT5682_HP_IMP_SENS_CTRL_29: 611 case RT5682_HP_IMP_SENS_CTRL_30: 612 case RT5682_HP_IMP_SENS_CTRL_31: 613 case RT5682_HP_IMP_SENS_CTRL_32: 614 case RT5682_HP_IMP_SENS_CTRL_33: 615 case RT5682_HP_IMP_SENS_CTRL_34: 616 case RT5682_HP_IMP_SENS_CTRL_35: 617 case RT5682_HP_IMP_SENS_CTRL_36: 618 case RT5682_HP_IMP_SENS_CTRL_37: 619 case RT5682_HP_IMP_SENS_CTRL_38: 620 case RT5682_HP_IMP_SENS_CTRL_39: 621 case RT5682_HP_IMP_SENS_CTRL_40: 622 case RT5682_HP_IMP_SENS_CTRL_41: 623 case RT5682_HP_IMP_SENS_CTRL_42: 624 case RT5682_HP_IMP_SENS_CTRL_43: 625 case RT5682_HP_LOGIC_CTRL_1: 626 case RT5682_HP_LOGIC_CTRL_2: 627 case RT5682_HP_LOGIC_CTRL_3: 628 case RT5682_HP_CALIB_CTRL_1: 629 case RT5682_HP_CALIB_CTRL_2: 630 case RT5682_HP_CALIB_CTRL_3: 631 case RT5682_HP_CALIB_CTRL_4: 632 case RT5682_HP_CALIB_CTRL_5: 633 case RT5682_HP_CALIB_CTRL_6: 634 case RT5682_HP_CALIB_CTRL_7: 635 case RT5682_HP_CALIB_CTRL_9: 636 case RT5682_HP_CALIB_CTRL_10: 637 case RT5682_HP_CALIB_CTRL_11: 638 case RT5682_HP_CALIB_STA_1: 639 case RT5682_HP_CALIB_STA_2: 640 case RT5682_HP_CALIB_STA_3: 641 case RT5682_HP_CALIB_STA_4: 642 case RT5682_HP_CALIB_STA_5: 643 case RT5682_HP_CALIB_STA_6: 644 case RT5682_HP_CALIB_STA_7: 645 case RT5682_HP_CALIB_STA_8: 646 case RT5682_HP_CALIB_STA_9: 647 case RT5682_HP_CALIB_STA_10: 648 case RT5682_HP_CALIB_STA_11: 649 case RT5682_SAR_IL_CMD_1: 650 case RT5682_SAR_IL_CMD_2: 651 case RT5682_SAR_IL_CMD_3: 652 case RT5682_SAR_IL_CMD_4: 653 case RT5682_SAR_IL_CMD_5: 654 case RT5682_SAR_IL_CMD_6: 655 case RT5682_SAR_IL_CMD_7: 656 case RT5682_SAR_IL_CMD_8: 657 case RT5682_SAR_IL_CMD_9: 658 case RT5682_SAR_IL_CMD_10: 659 case RT5682_SAR_IL_CMD_11: 660 case RT5682_SAR_IL_CMD_12: 661 case RT5682_SAR_IL_CMD_13: 662 case RT5682_EFUSE_CTRL_1: 663 case RT5682_EFUSE_CTRL_2: 664 case RT5682_EFUSE_CTRL_3: 665 case RT5682_EFUSE_CTRL_4: 666 case RT5682_EFUSE_CTRL_5: 667 case RT5682_EFUSE_CTRL_6: 668 case RT5682_EFUSE_CTRL_7: 669 case RT5682_EFUSE_CTRL_8: 670 case RT5682_EFUSE_CTRL_9: 671 case RT5682_EFUSE_CTRL_10: 672 case RT5682_EFUSE_CTRL_11: 673 case RT5682_JD_TOP_VC_VTRL: 674 case RT5682_DRC1_CTRL_0: 675 case RT5682_DRC1_CTRL_1: 676 case RT5682_DRC1_CTRL_2: 677 case RT5682_DRC1_CTRL_3: 678 case RT5682_DRC1_CTRL_4: 679 case RT5682_DRC1_CTRL_5: 680 case RT5682_DRC1_CTRL_6: 681 case RT5682_DRC1_HARD_LMT_CTRL_1: 682 case RT5682_DRC1_HARD_LMT_CTRL_2: 683 case RT5682_DRC1_PRIV_1: 684 case RT5682_DRC1_PRIV_2: 685 case RT5682_DRC1_PRIV_3: 686 case RT5682_DRC1_PRIV_4: 687 case RT5682_DRC1_PRIV_5: 688 case RT5682_DRC1_PRIV_6: 689 case RT5682_DRC1_PRIV_7: 690 case RT5682_DRC1_PRIV_8: 691 case RT5682_EQ_AUTO_RCV_CTRL1: 692 case RT5682_EQ_AUTO_RCV_CTRL2: 693 case RT5682_EQ_AUTO_RCV_CTRL3: 694 case RT5682_EQ_AUTO_RCV_CTRL4: 695 case RT5682_EQ_AUTO_RCV_CTRL5: 696 case RT5682_EQ_AUTO_RCV_CTRL6: 697 case RT5682_EQ_AUTO_RCV_CTRL7: 698 case RT5682_EQ_AUTO_RCV_CTRL8: 699 case RT5682_EQ_AUTO_RCV_CTRL9: 700 case RT5682_EQ_AUTO_RCV_CTRL10: 701 case RT5682_EQ_AUTO_RCV_CTRL11: 702 case RT5682_EQ_AUTO_RCV_CTRL12: 703 case RT5682_EQ_AUTO_RCV_CTRL13: 704 case RT5682_ADC_L_EQ_LPF1_A1: 705 case RT5682_R_EQ_LPF1_A1: 706 case RT5682_L_EQ_LPF1_H0: 707 case RT5682_R_EQ_LPF1_H0: 708 case RT5682_L_EQ_BPF1_A1: 709 case RT5682_R_EQ_BPF1_A1: 710 case RT5682_L_EQ_BPF1_A2: 711 case RT5682_R_EQ_BPF1_A2: 712 case RT5682_L_EQ_BPF1_H0: 713 case RT5682_R_EQ_BPF1_H0: 714 case RT5682_L_EQ_BPF2_A1: 715 case RT5682_R_EQ_BPF2_A1: 716 case RT5682_L_EQ_BPF2_A2: 717 case RT5682_R_EQ_BPF2_A2: 718 case RT5682_L_EQ_BPF2_H0: 719 case RT5682_R_EQ_BPF2_H0: 720 case RT5682_L_EQ_BPF3_A1: 721 case RT5682_R_EQ_BPF3_A1: 722 case RT5682_L_EQ_BPF3_A2: 723 case RT5682_R_EQ_BPF3_A2: 724 case RT5682_L_EQ_BPF3_H0: 725 case RT5682_R_EQ_BPF3_H0: 726 case RT5682_L_EQ_BPF4_A1: 727 case RT5682_R_EQ_BPF4_A1: 728 case RT5682_L_EQ_BPF4_A2: 729 case RT5682_R_EQ_BPF4_A2: 730 case RT5682_L_EQ_BPF4_H0: 731 case RT5682_R_EQ_BPF4_H0: 732 case RT5682_L_EQ_HPF1_A1: 733 case RT5682_R_EQ_HPF1_A1: 734 case RT5682_L_EQ_HPF1_H0: 735 case RT5682_R_EQ_HPF1_H0: 736 case RT5682_L_EQ_PRE_VOL: 737 case RT5682_R_EQ_PRE_VOL: 738 case RT5682_L_EQ_POST_VOL: 739 case RT5682_R_EQ_POST_VOL: 740 case RT5682_I2C_MODE: 741 return true; 742 default: 743 return false; 744 } 745 } 746 EXPORT_SYMBOL_GPL(rt5682_readable_register); 747 748 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6525, 75, 0); 749 static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0); 750 static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0); 751 752 /* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */ 753 static const DECLARE_TLV_DB_RANGE(bst_tlv, 754 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0), 755 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0), 756 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0), 757 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0), 758 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0), 759 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0), 760 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0) 761 ); 762 763 /* Interface data select */ 764 static const char * const rt5682_data_select[] = { 765 "L/R", "R/L", "L/L", "R/R" 766 }; 767 768 static SOC_ENUM_SINGLE_DECL(rt5682_if2_adc_enum, 769 RT5682_DIG_INF2_DATA, RT5682_IF2_ADC_SEL_SFT, rt5682_data_select); 770 771 static SOC_ENUM_SINGLE_DECL(rt5682_if1_01_adc_enum, 772 RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC1_SEL_SFT, rt5682_data_select); 773 774 static SOC_ENUM_SINGLE_DECL(rt5682_if1_23_adc_enum, 775 RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC2_SEL_SFT, rt5682_data_select); 776 777 static SOC_ENUM_SINGLE_DECL(rt5682_if1_45_adc_enum, 778 RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC3_SEL_SFT, rt5682_data_select); 779 780 static SOC_ENUM_SINGLE_DECL(rt5682_if1_67_adc_enum, 781 RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC4_SEL_SFT, rt5682_data_select); 782 783 static const struct snd_kcontrol_new rt5682_if2_adc_swap_mux = 784 SOC_DAPM_ENUM("IF2 ADC Swap Mux", rt5682_if2_adc_enum); 785 786 static const struct snd_kcontrol_new rt5682_if1_01_adc_swap_mux = 787 SOC_DAPM_ENUM("IF1 01 ADC Swap Mux", rt5682_if1_01_adc_enum); 788 789 static const struct snd_kcontrol_new rt5682_if1_23_adc_swap_mux = 790 SOC_DAPM_ENUM("IF1 23 ADC Swap Mux", rt5682_if1_23_adc_enum); 791 792 static const struct snd_kcontrol_new rt5682_if1_45_adc_swap_mux = 793 SOC_DAPM_ENUM("IF1 45 ADC Swap Mux", rt5682_if1_45_adc_enum); 794 795 static const struct snd_kcontrol_new rt5682_if1_67_adc_swap_mux = 796 SOC_DAPM_ENUM("IF1 67 ADC Swap Mux", rt5682_if1_67_adc_enum); 797 798 static const char * const rt5682_dac_select[] = { 799 "IF1", "SOUND" 800 }; 801 802 static SOC_ENUM_SINGLE_DECL(rt5682_dacl_enum, 803 RT5682_AD_DA_MIXER, RT5682_DAC1_L_SEL_SFT, rt5682_dac_select); 804 805 static const struct snd_kcontrol_new rt5682_dac_l_mux = 806 SOC_DAPM_ENUM("DAC L Mux", rt5682_dacl_enum); 807 808 static SOC_ENUM_SINGLE_DECL(rt5682_dacr_enum, 809 RT5682_AD_DA_MIXER, RT5682_DAC1_R_SEL_SFT, rt5682_dac_select); 810 811 static const struct snd_kcontrol_new rt5682_dac_r_mux = 812 SOC_DAPM_ENUM("DAC R Mux", rt5682_dacr_enum); 813 814 void rt5682_reset(struct rt5682_priv *rt5682) 815 { 816 regmap_write(rt5682->regmap, RT5682_RESET, 0); 817 if (!rt5682->is_sdw) 818 regmap_write(rt5682->regmap, RT5682_I2C_MODE, 1); 819 } 820 EXPORT_SYMBOL_GPL(rt5682_reset); 821 822 /** 823 * rt5682_sel_asrc_clk_src - select ASRC clock source for a set of filters 824 * @component: SoC audio component device. 825 * @filter_mask: mask of filters. 826 * @clk_src: clock source 827 * 828 * The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5682 can 829 * only support standard 32fs or 64fs i2s format, ASRC should be enabled to 830 * support special i2s clock format such as Intel's 100fs(100 * sampling rate). 831 * ASRC function will track i2s clock and generate a corresponding system clock 832 * for codec. This function provides an API to select the clock source for a 833 * set of filters specified by the mask. And the component driver will turn on 834 * ASRC for these filters if ASRC is selected as their clock source. 835 */ 836 int rt5682_sel_asrc_clk_src(struct snd_soc_component *component, 837 unsigned int filter_mask, unsigned int clk_src) 838 { 839 switch (clk_src) { 840 case RT5682_CLK_SEL_SYS: 841 case RT5682_CLK_SEL_I2S1_ASRC: 842 case RT5682_CLK_SEL_I2S2_ASRC: 843 break; 844 845 default: 846 return -EINVAL; 847 } 848 849 if (filter_mask & RT5682_DA_STEREO1_FILTER) { 850 snd_soc_component_update_bits(component, RT5682_PLL_TRACK_2, 851 RT5682_FILTER_CLK_SEL_MASK, 852 clk_src << RT5682_FILTER_CLK_SEL_SFT); 853 } 854 855 if (filter_mask & RT5682_AD_STEREO1_FILTER) { 856 snd_soc_component_update_bits(component, RT5682_PLL_TRACK_3, 857 RT5682_FILTER_CLK_SEL_MASK, 858 clk_src << RT5682_FILTER_CLK_SEL_SFT); 859 } 860 861 return 0; 862 } 863 EXPORT_SYMBOL_GPL(rt5682_sel_asrc_clk_src); 864 865 static int rt5682_button_detect(struct snd_soc_component *component) 866 { 867 int btn_type, val; 868 869 val = snd_soc_component_read(component, RT5682_4BTN_IL_CMD_1); 870 btn_type = val & 0xfff0; 871 snd_soc_component_write(component, RT5682_4BTN_IL_CMD_1, val); 872 dev_dbg(component->dev, "%s btn_type=%x\n", __func__, btn_type); 873 snd_soc_component_update_bits(component, 874 RT5682_SAR_IL_CMD_2, 0x10, 0x10); 875 876 return btn_type; 877 } 878 879 static void rt5682_enable_push_button_irq(struct snd_soc_component *component, 880 bool enable) 881 { 882 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 883 884 if (enable) { 885 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1, 886 RT5682_SAR_BUTT_DET_MASK, RT5682_SAR_BUTT_DET_EN); 887 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_13, 888 RT5682_SAR_SOUR_MASK, RT5682_SAR_SOUR_BTN); 889 snd_soc_component_write(component, RT5682_IL_CMD_1, 0x0040); 890 snd_soc_component_update_bits(component, RT5682_4BTN_IL_CMD_2, 891 RT5682_4BTN_IL_MASK | RT5682_4BTN_IL_RST_MASK, 892 RT5682_4BTN_IL_EN | RT5682_4BTN_IL_NOR); 893 if (rt5682->is_sdw) 894 snd_soc_component_update_bits(component, 895 RT5682_IRQ_CTRL_3, 896 RT5682_IL_IRQ_MASK | RT5682_IL_IRQ_TYPE_MASK, 897 RT5682_IL_IRQ_EN | RT5682_IL_IRQ_PUL); 898 else 899 snd_soc_component_update_bits(component, 900 RT5682_IRQ_CTRL_3, RT5682_IL_IRQ_MASK, 901 RT5682_IL_IRQ_EN); 902 } else { 903 snd_soc_component_update_bits(component, RT5682_IRQ_CTRL_3, 904 RT5682_IL_IRQ_MASK, RT5682_IL_IRQ_DIS); 905 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1, 906 RT5682_SAR_BUTT_DET_MASK, RT5682_SAR_BUTT_DET_DIS); 907 snd_soc_component_update_bits(component, RT5682_4BTN_IL_CMD_2, 908 RT5682_4BTN_IL_MASK, RT5682_4BTN_IL_DIS); 909 snd_soc_component_update_bits(component, RT5682_4BTN_IL_CMD_2, 910 RT5682_4BTN_IL_RST_MASK, RT5682_4BTN_IL_RST); 911 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_13, 912 RT5682_SAR_SOUR_MASK, RT5682_SAR_SOUR_TYPE); 913 } 914 } 915 916 /** 917 * rt5682_headset_detect - Detect headset. 918 * @component: SoC audio component device. 919 * @jack_insert: Jack insert or not. 920 * 921 * Detect whether is headset or not when jack inserted. 922 * 923 * Returns detect status. 924 */ 925 int rt5682_headset_detect(struct snd_soc_component *component, int jack_insert) 926 { 927 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 928 struct snd_soc_dapm_context *dapm = &component->dapm; 929 unsigned int val, count; 930 931 if (jack_insert) { 932 snd_soc_dapm_mutex_lock(dapm); 933 934 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_1, 935 RT5682_PWR_VREF2 | RT5682_PWR_MB, 936 RT5682_PWR_VREF2 | RT5682_PWR_MB); 937 snd_soc_component_update_bits(component, 938 RT5682_PWR_ANLG_1, RT5682_PWR_FV2, 0); 939 usleep_range(15000, 20000); 940 snd_soc_component_update_bits(component, 941 RT5682_PWR_ANLG_1, RT5682_PWR_FV2, RT5682_PWR_FV2); 942 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_3, 943 RT5682_PWR_CBJ, RT5682_PWR_CBJ); 944 snd_soc_component_update_bits(component, 945 RT5682_HP_CHARGE_PUMP_1, 946 RT5682_OSW_L_MASK | RT5682_OSW_R_MASK, 0); 947 rt5682_enable_push_button_irq(component, false); 948 snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1, 949 RT5682_TRIG_JD_MASK, RT5682_TRIG_JD_LOW); 950 usleep_range(55000, 60000); 951 snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1, 952 RT5682_TRIG_JD_MASK, RT5682_TRIG_JD_HIGH); 953 954 count = 0; 955 val = snd_soc_component_read(component, RT5682_CBJ_CTRL_2) 956 & RT5682_JACK_TYPE_MASK; 957 while (val == 0 && count < 50) { 958 usleep_range(10000, 15000); 959 val = snd_soc_component_read(component, 960 RT5682_CBJ_CTRL_2) & RT5682_JACK_TYPE_MASK; 961 count++; 962 } 963 964 switch (val) { 965 case 0x1: 966 case 0x2: 967 rt5682->jack_type = SND_JACK_HEADSET; 968 snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1, 969 RT5682_FAST_OFF_MASK, RT5682_FAST_OFF_EN); 970 rt5682_enable_push_button_irq(component, true); 971 break; 972 default: 973 rt5682->jack_type = SND_JACK_HEADPHONE; 974 break; 975 } 976 977 snd_soc_component_update_bits(component, 978 RT5682_HP_CHARGE_PUMP_1, 979 RT5682_OSW_L_MASK | RT5682_OSW_R_MASK, 980 RT5682_OSW_L_EN | RT5682_OSW_R_EN); 981 snd_soc_component_update_bits(component, RT5682_MICBIAS_2, 982 RT5682_PWR_CLK25M_MASK | RT5682_PWR_CLK1M_MASK, 983 RT5682_PWR_CLK25M_PU | RT5682_PWR_CLK1M_PU); 984 985 snd_soc_dapm_mutex_unlock(dapm); 986 } else { 987 rt5682_enable_push_button_irq(component, false); 988 snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1, 989 RT5682_TRIG_JD_MASK, RT5682_TRIG_JD_LOW); 990 if (!snd_soc_dapm_get_pin_status(dapm, "MICBIAS") && 991 !snd_soc_dapm_get_pin_status(dapm, "PLL1") && 992 !snd_soc_dapm_get_pin_status(dapm, "PLL2B")) 993 snd_soc_component_update_bits(component, 994 RT5682_PWR_ANLG_1, RT5682_PWR_MB, 0); 995 if (!snd_soc_dapm_get_pin_status(dapm, "Vref2") && 996 !snd_soc_dapm_get_pin_status(dapm, "PLL1") && 997 !snd_soc_dapm_get_pin_status(dapm, "PLL2B")) 998 snd_soc_component_update_bits(component, 999 RT5682_PWR_ANLG_1, RT5682_PWR_VREF2, 0); 1000 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_3, 1001 RT5682_PWR_CBJ, 0); 1002 snd_soc_component_update_bits(component, RT5682_MICBIAS_2, 1003 RT5682_PWR_CLK25M_MASK | RT5682_PWR_CLK1M_MASK, 1004 RT5682_PWR_CLK25M_PD | RT5682_PWR_CLK1M_PD); 1005 snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1, 1006 RT5682_FAST_OFF_MASK, RT5682_FAST_OFF_DIS); 1007 1008 rt5682->jack_type = 0; 1009 } 1010 1011 dev_dbg(component->dev, "jack_type = %d\n", rt5682->jack_type); 1012 return rt5682->jack_type; 1013 } 1014 EXPORT_SYMBOL_GPL(rt5682_headset_detect); 1015 1016 static int rt5682_set_jack_detect(struct snd_soc_component *component, 1017 struct snd_soc_jack *hs_jack, void *data) 1018 { 1019 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 1020 1021 rt5682->hs_jack = hs_jack; 1022 1023 if (!hs_jack) { 1024 regmap_update_bits(rt5682->regmap, RT5682_IRQ_CTRL_2, 1025 RT5682_JD1_EN_MASK, RT5682_JD1_DIS); 1026 regmap_update_bits(rt5682->regmap, RT5682_RC_CLK_CTRL, 1027 RT5682_POW_JDH | RT5682_POW_JDL, 0); 1028 cancel_delayed_work_sync(&rt5682->jack_detect_work); 1029 1030 return 0; 1031 } 1032 1033 if (!rt5682->is_sdw) { 1034 switch (rt5682->pdata.jd_src) { 1035 case RT5682_JD1: 1036 snd_soc_component_update_bits(component, 1037 RT5682_CBJ_CTRL_5, 0x0700, 0x0600); 1038 snd_soc_component_update_bits(component, 1039 RT5682_CBJ_CTRL_2, RT5682_EXT_JD_SRC, 1040 RT5682_EXT_JD_SRC_MANUAL); 1041 snd_soc_component_write(component, RT5682_CBJ_CTRL_1, 1042 0xd142); 1043 snd_soc_component_update_bits(component, 1044 RT5682_CBJ_CTRL_3, RT5682_CBJ_IN_BUF_EN, 1045 RT5682_CBJ_IN_BUF_EN); 1046 snd_soc_component_update_bits(component, 1047 RT5682_SAR_IL_CMD_1, RT5682_SAR_POW_MASK, 1048 RT5682_SAR_POW_EN); 1049 regmap_update_bits(rt5682->regmap, RT5682_GPIO_CTRL_1, 1050 RT5682_GP1_PIN_MASK, RT5682_GP1_PIN_IRQ); 1051 regmap_update_bits(rt5682->regmap, RT5682_RC_CLK_CTRL, 1052 RT5682_POW_IRQ | RT5682_POW_JDH | 1053 RT5682_POW_ANA, RT5682_POW_IRQ | 1054 RT5682_POW_JDH | RT5682_POW_ANA); 1055 regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_2, 1056 RT5682_PWR_JDH, RT5682_PWR_JDH); 1057 regmap_update_bits(rt5682->regmap, RT5682_IRQ_CTRL_2, 1058 RT5682_JD1_EN_MASK | RT5682_JD1_POL_MASK, 1059 RT5682_JD1_EN | RT5682_JD1_POL_NOR); 1060 regmap_update_bits(rt5682->regmap, RT5682_4BTN_IL_CMD_4, 1061 0x7f7f, (rt5682->pdata.btndet_delay << 8 | 1062 rt5682->pdata.btndet_delay)); 1063 regmap_update_bits(rt5682->regmap, RT5682_4BTN_IL_CMD_5, 1064 0x7f7f, (rt5682->pdata.btndet_delay << 8 | 1065 rt5682->pdata.btndet_delay)); 1066 regmap_update_bits(rt5682->regmap, RT5682_4BTN_IL_CMD_6, 1067 0x7f7f, (rt5682->pdata.btndet_delay << 8 | 1068 rt5682->pdata.btndet_delay)); 1069 regmap_update_bits(rt5682->regmap, RT5682_4BTN_IL_CMD_7, 1070 0x7f7f, (rt5682->pdata.btndet_delay << 8 | 1071 rt5682->pdata.btndet_delay)); 1072 mod_delayed_work(system_power_efficient_wq, 1073 &rt5682->jack_detect_work, 1074 msecs_to_jiffies(250)); 1075 break; 1076 1077 case RT5682_JD_NULL: 1078 regmap_update_bits(rt5682->regmap, RT5682_IRQ_CTRL_2, 1079 RT5682_JD1_EN_MASK, RT5682_JD1_DIS); 1080 regmap_update_bits(rt5682->regmap, RT5682_RC_CLK_CTRL, 1081 RT5682_POW_JDH | RT5682_POW_JDL, 0); 1082 break; 1083 1084 default: 1085 dev_warn(component->dev, "Wrong JD source\n"); 1086 break; 1087 } 1088 } 1089 1090 return 0; 1091 } 1092 1093 void rt5682_jack_detect_handler(struct work_struct *work) 1094 { 1095 struct rt5682_priv *rt5682 = 1096 container_of(work, struct rt5682_priv, jack_detect_work.work); 1097 int val, btn_type; 1098 1099 while (!rt5682->component) 1100 usleep_range(10000, 15000); 1101 1102 while (!rt5682->component->card->instantiated) 1103 usleep_range(10000, 15000); 1104 1105 mutex_lock(&rt5682->jdet_mutex); 1106 mutex_lock(&rt5682->calibrate_mutex); 1107 1108 val = snd_soc_component_read(rt5682->component, RT5682_AJD1_CTRL) 1109 & RT5682_JDH_RS_MASK; 1110 if (!val) { 1111 /* jack in */ 1112 if (rt5682->jack_type == 0) { 1113 /* jack was out, report jack type */ 1114 rt5682->jack_type = 1115 rt5682_headset_detect(rt5682->component, 1); 1116 rt5682->irq_work_delay_time = 0; 1117 } else if ((rt5682->jack_type & SND_JACK_HEADSET) == 1118 SND_JACK_HEADSET) { 1119 /* jack is already in, report button event */ 1120 rt5682->jack_type = SND_JACK_HEADSET; 1121 btn_type = rt5682_button_detect(rt5682->component); 1122 /** 1123 * rt5682 can report three kinds of button behavior, 1124 * one click, double click and hold. However, 1125 * currently we will report button pressed/released 1126 * event. So all the three button behaviors are 1127 * treated as button pressed. 1128 */ 1129 switch (btn_type) { 1130 case 0x8000: 1131 case 0x4000: 1132 case 0x2000: 1133 rt5682->jack_type |= SND_JACK_BTN_0; 1134 break; 1135 case 0x1000: 1136 case 0x0800: 1137 case 0x0400: 1138 rt5682->jack_type |= SND_JACK_BTN_1; 1139 break; 1140 case 0x0200: 1141 case 0x0100: 1142 case 0x0080: 1143 rt5682->jack_type |= SND_JACK_BTN_2; 1144 break; 1145 case 0x0040: 1146 case 0x0020: 1147 case 0x0010: 1148 rt5682->jack_type |= SND_JACK_BTN_3; 1149 break; 1150 case 0x0000: /* unpressed */ 1151 break; 1152 default: 1153 dev_err(rt5682->component->dev, 1154 "Unexpected button code 0x%04x\n", 1155 btn_type); 1156 break; 1157 } 1158 } 1159 } else { 1160 /* jack out */ 1161 rt5682->jack_type = rt5682_headset_detect(rt5682->component, 0); 1162 rt5682->irq_work_delay_time = 50; 1163 } 1164 1165 snd_soc_jack_report(rt5682->hs_jack, rt5682->jack_type, 1166 SND_JACK_HEADSET | 1167 SND_JACK_BTN_0 | SND_JACK_BTN_1 | 1168 SND_JACK_BTN_2 | SND_JACK_BTN_3); 1169 1170 if (!rt5682->is_sdw) { 1171 if (rt5682->jack_type & (SND_JACK_BTN_0 | SND_JACK_BTN_1 | 1172 SND_JACK_BTN_2 | SND_JACK_BTN_3)) 1173 schedule_delayed_work(&rt5682->jd_check_work, 0); 1174 else 1175 cancel_delayed_work_sync(&rt5682->jd_check_work); 1176 } 1177 1178 mutex_unlock(&rt5682->calibrate_mutex); 1179 mutex_unlock(&rt5682->jdet_mutex); 1180 } 1181 EXPORT_SYMBOL_GPL(rt5682_jack_detect_handler); 1182 1183 static const struct snd_kcontrol_new rt5682_snd_controls[] = { 1184 /* DAC Digital Volume */ 1185 SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5682_DAC1_DIG_VOL, 1186 RT5682_L_VOL_SFT + 1, RT5682_R_VOL_SFT + 1, 87, 0, dac_vol_tlv), 1187 1188 /* IN Boost Volume */ 1189 SOC_SINGLE_TLV("CBJ Boost Volume", RT5682_CBJ_BST_CTRL, 1190 RT5682_BST_CBJ_SFT, 8, 0, bst_tlv), 1191 1192 /* ADC Digital Volume Control */ 1193 SOC_DOUBLE("STO1 ADC Capture Switch", RT5682_STO1_ADC_DIG_VOL, 1194 RT5682_L_MUTE_SFT, RT5682_R_MUTE_SFT, 1, 1), 1195 SOC_DOUBLE_TLV("STO1 ADC Capture Volume", RT5682_STO1_ADC_DIG_VOL, 1196 RT5682_L_VOL_SFT + 1, RT5682_R_VOL_SFT + 1, 63, 0, adc_vol_tlv), 1197 1198 /* ADC Boost Volume Control */ 1199 SOC_DOUBLE_TLV("STO1 ADC Boost Gain Volume", RT5682_STO1_ADC_BOOST, 1200 RT5682_STO1_ADC_L_BST_SFT, RT5682_STO1_ADC_R_BST_SFT, 1201 3, 0, adc_bst_tlv), 1202 }; 1203 1204 static int rt5682_div_sel(struct rt5682_priv *rt5682, 1205 int target, const int div[], int size) 1206 { 1207 int i; 1208 1209 if (rt5682->sysclk < target) { 1210 dev_err(rt5682->component->dev, 1211 "sysclk rate %d is too low\n", rt5682->sysclk); 1212 return 0; 1213 } 1214 1215 for (i = 0; i < size - 1; i++) { 1216 dev_dbg(rt5682->component->dev, "div[%d]=%d\n", i, div[i]); 1217 if (target * div[i] == rt5682->sysclk) 1218 return i; 1219 if (target * div[i + 1] > rt5682->sysclk) { 1220 dev_dbg(rt5682->component->dev, 1221 "can't find div for sysclk %d\n", 1222 rt5682->sysclk); 1223 return i; 1224 } 1225 } 1226 1227 if (target * div[i] < rt5682->sysclk) 1228 dev_err(rt5682->component->dev, 1229 "sysclk rate %d is too high\n", rt5682->sysclk); 1230 1231 return size - 1; 1232 } 1233 1234 /** 1235 * set_dmic_clk - Set parameter of dmic. 1236 * 1237 * @w: DAPM widget. 1238 * @kcontrol: The kcontrol of this widget. 1239 * @event: Event id. 1240 * 1241 * Choose dmic clock between 1MHz and 3MHz. 1242 * It is better for clock to approximate 3MHz. 1243 */ 1244 static int set_dmic_clk(struct snd_soc_dapm_widget *w, 1245 struct snd_kcontrol *kcontrol, int event) 1246 { 1247 struct snd_soc_component *component = 1248 snd_soc_dapm_to_component(w->dapm); 1249 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 1250 int idx, dmic_clk_rate = 3072000; 1251 static const int div[] = {2, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, 128}; 1252 1253 if (rt5682->pdata.dmic_clk_rate) 1254 dmic_clk_rate = rt5682->pdata.dmic_clk_rate; 1255 1256 idx = rt5682_div_sel(rt5682, dmic_clk_rate, div, ARRAY_SIZE(div)); 1257 1258 snd_soc_component_update_bits(component, RT5682_DMIC_CTRL_1, 1259 RT5682_DMIC_CLK_MASK, idx << RT5682_DMIC_CLK_SFT); 1260 1261 return 0; 1262 } 1263 1264 static int set_filter_clk(struct snd_soc_dapm_widget *w, 1265 struct snd_kcontrol *kcontrol, int event) 1266 { 1267 struct snd_soc_component *component = 1268 snd_soc_dapm_to_component(w->dapm); 1269 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 1270 int ref, val, reg, idx; 1271 static const int div_f[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32, 48}; 1272 static const int div_o[] = {1, 2, 4, 6, 8, 12, 16, 24, 32, 48}; 1273 1274 if (rt5682->is_sdw) 1275 return 0; 1276 1277 val = snd_soc_component_read(component, RT5682_GPIO_CTRL_1) & 1278 RT5682_GP4_PIN_MASK; 1279 if (w->shift == RT5682_PWR_ADC_S1F_BIT && 1280 val == RT5682_GP4_PIN_ADCDAT2) 1281 ref = 256 * rt5682->lrck[RT5682_AIF2]; 1282 else 1283 ref = 256 * rt5682->lrck[RT5682_AIF1]; 1284 1285 idx = rt5682_div_sel(rt5682, ref, div_f, ARRAY_SIZE(div_f)); 1286 1287 if (w->shift == RT5682_PWR_ADC_S1F_BIT) 1288 reg = RT5682_PLL_TRACK_3; 1289 else 1290 reg = RT5682_PLL_TRACK_2; 1291 1292 snd_soc_component_update_bits(component, reg, 1293 RT5682_FILTER_CLK_DIV_MASK, idx << RT5682_FILTER_CLK_DIV_SFT); 1294 1295 /* select over sample rate */ 1296 for (idx = 0; idx < ARRAY_SIZE(div_o); idx++) { 1297 if (rt5682->sysclk <= 12288000 * div_o[idx]) 1298 break; 1299 } 1300 1301 snd_soc_component_update_bits(component, RT5682_ADDA_CLK_1, 1302 RT5682_ADC_OSR_MASK | RT5682_DAC_OSR_MASK, 1303 (idx << RT5682_ADC_OSR_SFT) | (idx << RT5682_DAC_OSR_SFT)); 1304 1305 return 0; 1306 } 1307 1308 static int is_sys_clk_from_pll1(struct snd_soc_dapm_widget *w, 1309 struct snd_soc_dapm_widget *sink) 1310 { 1311 unsigned int val; 1312 struct snd_soc_component *component = 1313 snd_soc_dapm_to_component(w->dapm); 1314 1315 val = snd_soc_component_read(component, RT5682_GLB_CLK); 1316 val &= RT5682_SCLK_SRC_MASK; 1317 if (val == RT5682_SCLK_SRC_PLL1) 1318 return 1; 1319 else 1320 return 0; 1321 } 1322 1323 static int is_sys_clk_from_pll2(struct snd_soc_dapm_widget *w, 1324 struct snd_soc_dapm_widget *sink) 1325 { 1326 unsigned int val; 1327 struct snd_soc_component *component = 1328 snd_soc_dapm_to_component(w->dapm); 1329 1330 val = snd_soc_component_read(component, RT5682_GLB_CLK); 1331 val &= RT5682_SCLK_SRC_MASK; 1332 if (val == RT5682_SCLK_SRC_PLL2) 1333 return 1; 1334 else 1335 return 0; 1336 } 1337 1338 static int is_using_asrc(struct snd_soc_dapm_widget *w, 1339 struct snd_soc_dapm_widget *sink) 1340 { 1341 unsigned int reg, shift, val; 1342 struct snd_soc_component *component = 1343 snd_soc_dapm_to_component(w->dapm); 1344 1345 switch (w->shift) { 1346 case RT5682_ADC_STO1_ASRC_SFT: 1347 reg = RT5682_PLL_TRACK_3; 1348 shift = RT5682_FILTER_CLK_SEL_SFT; 1349 break; 1350 case RT5682_DAC_STO1_ASRC_SFT: 1351 reg = RT5682_PLL_TRACK_2; 1352 shift = RT5682_FILTER_CLK_SEL_SFT; 1353 break; 1354 default: 1355 return 0; 1356 } 1357 1358 val = (snd_soc_component_read(component, reg) >> shift) & 0xf; 1359 switch (val) { 1360 case RT5682_CLK_SEL_I2S1_ASRC: 1361 case RT5682_CLK_SEL_I2S2_ASRC: 1362 return 1; 1363 default: 1364 return 0; 1365 } 1366 } 1367 1368 /* Digital Mixer */ 1369 static const struct snd_kcontrol_new rt5682_sto1_adc_l_mix[] = { 1370 SOC_DAPM_SINGLE("ADC1 Switch", RT5682_STO1_ADC_MIXER, 1371 RT5682_M_STO1_ADC_L1_SFT, 1, 1), 1372 SOC_DAPM_SINGLE("ADC2 Switch", RT5682_STO1_ADC_MIXER, 1373 RT5682_M_STO1_ADC_L2_SFT, 1, 1), 1374 }; 1375 1376 static const struct snd_kcontrol_new rt5682_sto1_adc_r_mix[] = { 1377 SOC_DAPM_SINGLE("ADC1 Switch", RT5682_STO1_ADC_MIXER, 1378 RT5682_M_STO1_ADC_R1_SFT, 1, 1), 1379 SOC_DAPM_SINGLE("ADC2 Switch", RT5682_STO1_ADC_MIXER, 1380 RT5682_M_STO1_ADC_R2_SFT, 1, 1), 1381 }; 1382 1383 static const struct snd_kcontrol_new rt5682_dac_l_mix[] = { 1384 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5682_AD_DA_MIXER, 1385 RT5682_M_ADCMIX_L_SFT, 1, 1), 1386 SOC_DAPM_SINGLE("DAC1 Switch", RT5682_AD_DA_MIXER, 1387 RT5682_M_DAC1_L_SFT, 1, 1), 1388 }; 1389 1390 static const struct snd_kcontrol_new rt5682_dac_r_mix[] = { 1391 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5682_AD_DA_MIXER, 1392 RT5682_M_ADCMIX_R_SFT, 1, 1), 1393 SOC_DAPM_SINGLE("DAC1 Switch", RT5682_AD_DA_MIXER, 1394 RT5682_M_DAC1_R_SFT, 1, 1), 1395 }; 1396 1397 static const struct snd_kcontrol_new rt5682_sto1_dac_l_mix[] = { 1398 SOC_DAPM_SINGLE("DAC L1 Switch", RT5682_STO1_DAC_MIXER, 1399 RT5682_M_DAC_L1_STO_L_SFT, 1, 1), 1400 SOC_DAPM_SINGLE("DAC R1 Switch", RT5682_STO1_DAC_MIXER, 1401 RT5682_M_DAC_R1_STO_L_SFT, 1, 1), 1402 }; 1403 1404 static const struct snd_kcontrol_new rt5682_sto1_dac_r_mix[] = { 1405 SOC_DAPM_SINGLE("DAC L1 Switch", RT5682_STO1_DAC_MIXER, 1406 RT5682_M_DAC_L1_STO_R_SFT, 1, 1), 1407 SOC_DAPM_SINGLE("DAC R1 Switch", RT5682_STO1_DAC_MIXER, 1408 RT5682_M_DAC_R1_STO_R_SFT, 1, 1), 1409 }; 1410 1411 /* Analog Input Mixer */ 1412 static const struct snd_kcontrol_new rt5682_rec1_l_mix[] = { 1413 SOC_DAPM_SINGLE("CBJ Switch", RT5682_REC_MIXER, 1414 RT5682_M_CBJ_RM1_L_SFT, 1, 1), 1415 }; 1416 1417 /* STO1 ADC1 Source */ 1418 /* MX-26 [13] [5] */ 1419 static const char * const rt5682_sto1_adc1_src[] = { 1420 "DAC MIX", "ADC" 1421 }; 1422 1423 static SOC_ENUM_SINGLE_DECL( 1424 rt5682_sto1_adc1l_enum, RT5682_STO1_ADC_MIXER, 1425 RT5682_STO1_ADC1L_SRC_SFT, rt5682_sto1_adc1_src); 1426 1427 static const struct snd_kcontrol_new rt5682_sto1_adc1l_mux = 1428 SOC_DAPM_ENUM("Stereo1 ADC1L Source", rt5682_sto1_adc1l_enum); 1429 1430 static SOC_ENUM_SINGLE_DECL( 1431 rt5682_sto1_adc1r_enum, RT5682_STO1_ADC_MIXER, 1432 RT5682_STO1_ADC1R_SRC_SFT, rt5682_sto1_adc1_src); 1433 1434 static const struct snd_kcontrol_new rt5682_sto1_adc1r_mux = 1435 SOC_DAPM_ENUM("Stereo1 ADC1L Source", rt5682_sto1_adc1r_enum); 1436 1437 /* STO1 ADC Source */ 1438 /* MX-26 [11:10] [3:2] */ 1439 static const char * const rt5682_sto1_adc_src[] = { 1440 "ADC1 L", "ADC1 R" 1441 }; 1442 1443 static SOC_ENUM_SINGLE_DECL( 1444 rt5682_sto1_adcl_enum, RT5682_STO1_ADC_MIXER, 1445 RT5682_STO1_ADCL_SRC_SFT, rt5682_sto1_adc_src); 1446 1447 static const struct snd_kcontrol_new rt5682_sto1_adcl_mux = 1448 SOC_DAPM_ENUM("Stereo1 ADCL Source", rt5682_sto1_adcl_enum); 1449 1450 static SOC_ENUM_SINGLE_DECL( 1451 rt5682_sto1_adcr_enum, RT5682_STO1_ADC_MIXER, 1452 RT5682_STO1_ADCR_SRC_SFT, rt5682_sto1_adc_src); 1453 1454 static const struct snd_kcontrol_new rt5682_sto1_adcr_mux = 1455 SOC_DAPM_ENUM("Stereo1 ADCR Source", rt5682_sto1_adcr_enum); 1456 1457 /* STO1 ADC2 Source */ 1458 /* MX-26 [12] [4] */ 1459 static const char * const rt5682_sto1_adc2_src[] = { 1460 "DAC MIX", "DMIC" 1461 }; 1462 1463 static SOC_ENUM_SINGLE_DECL( 1464 rt5682_sto1_adc2l_enum, RT5682_STO1_ADC_MIXER, 1465 RT5682_STO1_ADC2L_SRC_SFT, rt5682_sto1_adc2_src); 1466 1467 static const struct snd_kcontrol_new rt5682_sto1_adc2l_mux = 1468 SOC_DAPM_ENUM("Stereo1 ADC2L Source", rt5682_sto1_adc2l_enum); 1469 1470 static SOC_ENUM_SINGLE_DECL( 1471 rt5682_sto1_adc2r_enum, RT5682_STO1_ADC_MIXER, 1472 RT5682_STO1_ADC2R_SRC_SFT, rt5682_sto1_adc2_src); 1473 1474 static const struct snd_kcontrol_new rt5682_sto1_adc2r_mux = 1475 SOC_DAPM_ENUM("Stereo1 ADC2R Source", rt5682_sto1_adc2r_enum); 1476 1477 /* MX-79 [6:4] I2S1 ADC data location */ 1478 static const unsigned int rt5682_if1_adc_slot_values[] = { 1479 0, 1480 2, 1481 4, 1482 6, 1483 }; 1484 1485 static const char * const rt5682_if1_adc_slot_src[] = { 1486 "Slot 0", "Slot 2", "Slot 4", "Slot 6" 1487 }; 1488 1489 static SOC_VALUE_ENUM_SINGLE_DECL(rt5682_if1_adc_slot_enum, 1490 RT5682_TDM_CTRL, RT5682_TDM_ADC_LCA_SFT, RT5682_TDM_ADC_LCA_MASK, 1491 rt5682_if1_adc_slot_src, rt5682_if1_adc_slot_values); 1492 1493 static const struct snd_kcontrol_new rt5682_if1_adc_slot_mux = 1494 SOC_DAPM_ENUM("IF1 ADC Slot location", rt5682_if1_adc_slot_enum); 1495 1496 /* Analog DAC L1 Source, Analog DAC R1 Source*/ 1497 /* MX-2B [4], MX-2B [0]*/ 1498 static const char * const rt5682_alg_dac1_src[] = { 1499 "Stereo1 DAC Mixer", "DAC1" 1500 }; 1501 1502 static SOC_ENUM_SINGLE_DECL( 1503 rt5682_alg_dac_l1_enum, RT5682_A_DAC1_MUX, 1504 RT5682_A_DACL1_SFT, rt5682_alg_dac1_src); 1505 1506 static const struct snd_kcontrol_new rt5682_alg_dac_l1_mux = 1507 SOC_DAPM_ENUM("Analog DAC L1 Source", rt5682_alg_dac_l1_enum); 1508 1509 static SOC_ENUM_SINGLE_DECL( 1510 rt5682_alg_dac_r1_enum, RT5682_A_DAC1_MUX, 1511 RT5682_A_DACR1_SFT, rt5682_alg_dac1_src); 1512 1513 static const struct snd_kcontrol_new rt5682_alg_dac_r1_mux = 1514 SOC_DAPM_ENUM("Analog DAC R1 Source", rt5682_alg_dac_r1_enum); 1515 1516 /* Out Switch */ 1517 static const struct snd_kcontrol_new hpol_switch = 1518 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5682_HP_CTRL_1, 1519 RT5682_L_MUTE_SFT, 1, 1); 1520 static const struct snd_kcontrol_new hpor_switch = 1521 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5682_HP_CTRL_1, 1522 RT5682_R_MUTE_SFT, 1, 1); 1523 1524 static int rt5682_hp_event(struct snd_soc_dapm_widget *w, 1525 struct snd_kcontrol *kcontrol, int event) 1526 { 1527 struct snd_soc_component *component = 1528 snd_soc_dapm_to_component(w->dapm); 1529 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 1530 1531 switch (event) { 1532 case SND_SOC_DAPM_PRE_PMU: 1533 snd_soc_component_update_bits(component, RT5682_HP_CTRL_2, 1534 RT5682_HP_C2_DAC_AMP_MUTE, 0); 1535 snd_soc_component_update_bits(component, RT5682_HP_LOGIC_CTRL_2, 1536 RT5682_HP_LC2_SIG_SOUR2_MASK, RT5682_HP_LC2_SIG_SOUR2_REG); 1537 snd_soc_component_update_bits(component, 1538 RT5682_DEPOP_1, 0x60, 0x60); 1539 snd_soc_component_update_bits(component, 1540 RT5682_DAC_ADC_DIG_VOL1, 0x00c0, 0x0080); 1541 1542 mutex_lock(&rt5682->jdet_mutex); 1543 1544 snd_soc_component_update_bits(component, RT5682_HP_CTRL_2, 1545 RT5682_HP_C2_DAC_L_EN | RT5682_HP_C2_DAC_R_EN, 1546 RT5682_HP_C2_DAC_L_EN | RT5682_HP_C2_DAC_R_EN); 1547 usleep_range(5000, 10000); 1548 snd_soc_component_update_bits(component, RT5682_CHARGE_PUMP_1, 1549 RT5682_CP_SW_SIZE_MASK, RT5682_CP_SW_SIZE_L); 1550 1551 mutex_unlock(&rt5682->jdet_mutex); 1552 break; 1553 1554 case SND_SOC_DAPM_POST_PMD: 1555 snd_soc_component_update_bits(component, RT5682_HP_CTRL_2, 1556 RT5682_HP_C2_DAC_L_EN | RT5682_HP_C2_DAC_R_EN, 0); 1557 snd_soc_component_update_bits(component, RT5682_CHARGE_PUMP_1, 1558 RT5682_CP_SW_SIZE_MASK, RT5682_CP_SW_SIZE_M); 1559 snd_soc_component_update_bits(component, 1560 RT5682_DEPOP_1, 0x60, 0x0); 1561 snd_soc_component_update_bits(component, 1562 RT5682_DAC_ADC_DIG_VOL1, 0x00c0, 0x0000); 1563 break; 1564 } 1565 1566 return 0; 1567 } 1568 1569 static int set_dmic_power(struct snd_soc_dapm_widget *w, 1570 struct snd_kcontrol *kcontrol, int event) 1571 { 1572 struct snd_soc_component *component = 1573 snd_soc_dapm_to_component(w->dapm); 1574 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 1575 unsigned int delay = 50, val; 1576 1577 if (rt5682->pdata.dmic_delay) 1578 delay = rt5682->pdata.dmic_delay; 1579 1580 switch (event) { 1581 case SND_SOC_DAPM_POST_PMU: 1582 val = snd_soc_component_read(component, RT5682_GLB_CLK); 1583 val &= RT5682_SCLK_SRC_MASK; 1584 if (val == RT5682_SCLK_SRC_PLL1 || val == RT5682_SCLK_SRC_PLL2) 1585 snd_soc_component_update_bits(component, 1586 RT5682_PWR_ANLG_1, 1587 RT5682_PWR_VREF2 | RT5682_PWR_MB, 1588 RT5682_PWR_VREF2 | RT5682_PWR_MB); 1589 1590 /*Add delay to avoid pop noise*/ 1591 msleep(delay); 1592 break; 1593 1594 case SND_SOC_DAPM_POST_PMD: 1595 if (!rt5682->jack_type) { 1596 if (!snd_soc_dapm_get_pin_status(w->dapm, "MICBIAS")) 1597 snd_soc_component_update_bits(component, 1598 RT5682_PWR_ANLG_1, RT5682_PWR_MB, 0); 1599 if (!snd_soc_dapm_get_pin_status(w->dapm, "Vref2")) 1600 snd_soc_component_update_bits(component, 1601 RT5682_PWR_ANLG_1, RT5682_PWR_VREF2, 0); 1602 } 1603 break; 1604 } 1605 1606 return 0; 1607 } 1608 1609 static int rt5682_set_verf(struct snd_soc_dapm_widget *w, 1610 struct snd_kcontrol *kcontrol, int event) 1611 { 1612 struct snd_soc_component *component = 1613 snd_soc_dapm_to_component(w->dapm); 1614 1615 switch (event) { 1616 case SND_SOC_DAPM_PRE_PMU: 1617 switch (w->shift) { 1618 case RT5682_PWR_VREF1_BIT: 1619 snd_soc_component_update_bits(component, 1620 RT5682_PWR_ANLG_1, RT5682_PWR_FV1, 0); 1621 break; 1622 1623 case RT5682_PWR_VREF2_BIT: 1624 snd_soc_component_update_bits(component, 1625 RT5682_PWR_ANLG_1, RT5682_PWR_FV2, 0); 1626 break; 1627 } 1628 break; 1629 1630 case SND_SOC_DAPM_POST_PMU: 1631 usleep_range(15000, 20000); 1632 switch (w->shift) { 1633 case RT5682_PWR_VREF1_BIT: 1634 snd_soc_component_update_bits(component, 1635 RT5682_PWR_ANLG_1, RT5682_PWR_FV1, 1636 RT5682_PWR_FV1); 1637 break; 1638 1639 case RT5682_PWR_VREF2_BIT: 1640 snd_soc_component_update_bits(component, 1641 RT5682_PWR_ANLG_1, RT5682_PWR_FV2, 1642 RT5682_PWR_FV2); 1643 break; 1644 } 1645 break; 1646 } 1647 1648 return 0; 1649 } 1650 1651 static const unsigned int rt5682_adcdat_pin_values[] = { 1652 1, 1653 3, 1654 }; 1655 1656 static const char * const rt5682_adcdat_pin_select[] = { 1657 "ADCDAT1", 1658 "ADCDAT2", 1659 }; 1660 1661 static SOC_VALUE_ENUM_SINGLE_DECL(rt5682_adcdat_pin_enum, 1662 RT5682_GPIO_CTRL_1, RT5682_GP4_PIN_SFT, RT5682_GP4_PIN_MASK, 1663 rt5682_adcdat_pin_select, rt5682_adcdat_pin_values); 1664 1665 static const struct snd_kcontrol_new rt5682_adcdat_pin_ctrl = 1666 SOC_DAPM_ENUM("ADCDAT", rt5682_adcdat_pin_enum); 1667 1668 static const unsigned int rt5682_hpo_sig_out_values[] = { 1669 2, 1670 7, 1671 }; 1672 1673 static const char * const rt5682_hpo_sig_out_mode[] = { 1674 "Legacy", 1675 "OneBit", 1676 }; 1677 1678 static SOC_VALUE_ENUM_SINGLE_DECL(rt5682_hpo_sig_out_enum, 1679 RT5682_HP_LOGIC_CTRL_2, 0, RT5682_HP_LC2_SIG_SOUR1_MASK, 1680 rt5682_hpo_sig_out_mode, rt5682_hpo_sig_out_values); 1681 1682 static const struct snd_kcontrol_new rt5682_hpo_sig_demux = 1683 SOC_DAPM_ENUM("HPO Signal Demux", rt5682_hpo_sig_out_enum); 1684 1685 static const struct snd_soc_dapm_widget rt5682_dapm_widgets[] = { 1686 SND_SOC_DAPM_SUPPLY("LDO2", RT5682_PWR_ANLG_3, RT5682_PWR_LDO2_BIT, 1687 0, NULL, 0), 1688 SND_SOC_DAPM_SUPPLY("PLL1", RT5682_PWR_ANLG_3, RT5682_PWR_PLL_BIT, 1689 0, NULL, 0), 1690 SND_SOC_DAPM_SUPPLY("PLL2B", RT5682_PWR_ANLG_3, RT5682_PWR_PLL2B_BIT, 1691 0, NULL, 0), 1692 SND_SOC_DAPM_SUPPLY("PLL2F", RT5682_PWR_ANLG_3, RT5682_PWR_PLL2F_BIT, 1693 0, set_filter_clk, SND_SOC_DAPM_PRE_PMU), 1694 SND_SOC_DAPM_SUPPLY("Vref1", RT5682_PWR_ANLG_1, RT5682_PWR_VREF1_BIT, 0, 1695 rt5682_set_verf, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), 1696 SND_SOC_DAPM_SUPPLY("Vref2", SND_SOC_NOPM, 0, 0, NULL, 0), 1697 SND_SOC_DAPM_SUPPLY("MICBIAS", SND_SOC_NOPM, 0, 0, NULL, 0), 1698 1699 /* ASRC */ 1700 SND_SOC_DAPM_SUPPLY_S("DAC STO1 ASRC", 1, RT5682_PLL_TRACK_1, 1701 RT5682_DAC_STO1_ASRC_SFT, 0, NULL, 0), 1702 SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5682_PLL_TRACK_1, 1703 RT5682_ADC_STO1_ASRC_SFT, 0, NULL, 0), 1704 SND_SOC_DAPM_SUPPLY_S("AD ASRC", 1, RT5682_PLL_TRACK_1, 1705 RT5682_AD_ASRC_SFT, 0, NULL, 0), 1706 SND_SOC_DAPM_SUPPLY_S("DA ASRC", 1, RT5682_PLL_TRACK_1, 1707 RT5682_DA_ASRC_SFT, 0, NULL, 0), 1708 SND_SOC_DAPM_SUPPLY_S("DMIC ASRC", 1, RT5682_PLL_TRACK_1, 1709 RT5682_DMIC_ASRC_SFT, 0, NULL, 0), 1710 1711 /* Input Side */ 1712 SND_SOC_DAPM_SUPPLY("MICBIAS1", RT5682_PWR_ANLG_2, RT5682_PWR_MB1_BIT, 1713 0, NULL, 0), 1714 SND_SOC_DAPM_SUPPLY("MICBIAS2", RT5682_PWR_ANLG_2, RT5682_PWR_MB2_BIT, 1715 0, NULL, 0), 1716 1717 /* Input Lines */ 1718 SND_SOC_DAPM_INPUT("DMIC L1"), 1719 SND_SOC_DAPM_INPUT("DMIC R1"), 1720 1721 SND_SOC_DAPM_INPUT("IN1P"), 1722 1723 SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0, 1724 set_dmic_clk, SND_SOC_DAPM_PRE_PMU), 1725 SND_SOC_DAPM_SUPPLY("DMIC1 Power", RT5682_DMIC_CTRL_1, 1726 RT5682_DMIC_1_EN_SFT, 0, set_dmic_power, 1727 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 1728 1729 /* Boost */ 1730 SND_SOC_DAPM_PGA("BST1 CBJ", SND_SOC_NOPM, 1731 0, 0, NULL, 0), 1732 1733 /* REC Mixer */ 1734 SND_SOC_DAPM_MIXER("RECMIX1L", SND_SOC_NOPM, 0, 0, rt5682_rec1_l_mix, 1735 ARRAY_SIZE(rt5682_rec1_l_mix)), 1736 SND_SOC_DAPM_SUPPLY("RECMIX1L Power", RT5682_PWR_ANLG_2, 1737 RT5682_PWR_RM1_L_BIT, 0, NULL, 0), 1738 1739 /* ADCs */ 1740 SND_SOC_DAPM_ADC("ADC1 L", NULL, SND_SOC_NOPM, 0, 0), 1741 SND_SOC_DAPM_ADC("ADC1 R", NULL, SND_SOC_NOPM, 0, 0), 1742 1743 SND_SOC_DAPM_SUPPLY("ADC1 L Power", RT5682_PWR_DIG_1, 1744 RT5682_PWR_ADC_L1_BIT, 0, NULL, 0), 1745 SND_SOC_DAPM_SUPPLY("ADC1 R Power", RT5682_PWR_DIG_1, 1746 RT5682_PWR_ADC_R1_BIT, 0, NULL, 0), 1747 SND_SOC_DAPM_SUPPLY("ADC1 clock", RT5682_CHOP_ADC, 1748 RT5682_CKGEN_ADC1_SFT, 0, NULL, 0), 1749 1750 /* ADC Mux */ 1751 SND_SOC_DAPM_MUX("Stereo1 ADC L1 Mux", SND_SOC_NOPM, 0, 0, 1752 &rt5682_sto1_adc1l_mux), 1753 SND_SOC_DAPM_MUX("Stereo1 ADC R1 Mux", SND_SOC_NOPM, 0, 0, 1754 &rt5682_sto1_adc1r_mux), 1755 SND_SOC_DAPM_MUX("Stereo1 ADC L2 Mux", SND_SOC_NOPM, 0, 0, 1756 &rt5682_sto1_adc2l_mux), 1757 SND_SOC_DAPM_MUX("Stereo1 ADC R2 Mux", SND_SOC_NOPM, 0, 0, 1758 &rt5682_sto1_adc2r_mux), 1759 SND_SOC_DAPM_MUX("Stereo1 ADC L Mux", SND_SOC_NOPM, 0, 0, 1760 &rt5682_sto1_adcl_mux), 1761 SND_SOC_DAPM_MUX("Stereo1 ADC R Mux", SND_SOC_NOPM, 0, 0, 1762 &rt5682_sto1_adcr_mux), 1763 SND_SOC_DAPM_MUX("IF1_ADC Mux", SND_SOC_NOPM, 0, 0, 1764 &rt5682_if1_adc_slot_mux), 1765 1766 /* ADC Mixer */ 1767 SND_SOC_DAPM_SUPPLY("ADC Stereo1 Filter", RT5682_PWR_DIG_2, 1768 RT5682_PWR_ADC_S1F_BIT, 0, set_filter_clk, 1769 SND_SOC_DAPM_PRE_PMU), 1770 SND_SOC_DAPM_MIXER("Stereo1 ADC MIXL", RT5682_STO1_ADC_DIG_VOL, 1771 RT5682_L_MUTE_SFT, 1, rt5682_sto1_adc_l_mix, 1772 ARRAY_SIZE(rt5682_sto1_adc_l_mix)), 1773 SND_SOC_DAPM_MIXER("Stereo1 ADC MIXR", RT5682_STO1_ADC_DIG_VOL, 1774 RT5682_R_MUTE_SFT, 1, rt5682_sto1_adc_r_mix, 1775 ARRAY_SIZE(rt5682_sto1_adc_r_mix)), 1776 1777 /* ADC PGA */ 1778 SND_SOC_DAPM_PGA("Stereo1 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 1779 1780 /* Digital Interface */ 1781 SND_SOC_DAPM_SUPPLY("I2S1", RT5682_PWR_DIG_1, RT5682_PWR_I2S1_BIT, 1782 0, NULL, 0), 1783 SND_SOC_DAPM_SUPPLY("I2S2", RT5682_PWR_DIG_1, RT5682_PWR_I2S2_BIT, 1784 0, NULL, 0), 1785 SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0), 1786 SND_SOC_DAPM_PGA("IF1 DAC1 L", SND_SOC_NOPM, 0, 0, NULL, 0), 1787 SND_SOC_DAPM_PGA("IF1 DAC1 R", SND_SOC_NOPM, 0, 0, NULL, 0), 1788 SND_SOC_DAPM_PGA("SOUND DAC L", SND_SOC_NOPM, 0, 0, NULL, 0), 1789 SND_SOC_DAPM_PGA("SOUND DAC R", SND_SOC_NOPM, 0, 0, NULL, 0), 1790 1791 /* Digital Interface Select */ 1792 SND_SOC_DAPM_MUX("IF1 01 ADC Swap Mux", SND_SOC_NOPM, 0, 0, 1793 &rt5682_if1_01_adc_swap_mux), 1794 SND_SOC_DAPM_MUX("IF1 23 ADC Swap Mux", SND_SOC_NOPM, 0, 0, 1795 &rt5682_if1_23_adc_swap_mux), 1796 SND_SOC_DAPM_MUX("IF1 45 ADC Swap Mux", SND_SOC_NOPM, 0, 0, 1797 &rt5682_if1_45_adc_swap_mux), 1798 SND_SOC_DAPM_MUX("IF1 67 ADC Swap Mux", SND_SOC_NOPM, 0, 0, 1799 &rt5682_if1_67_adc_swap_mux), 1800 SND_SOC_DAPM_MUX("IF2 ADC Swap Mux", SND_SOC_NOPM, 0, 0, 1801 &rt5682_if2_adc_swap_mux), 1802 1803 SND_SOC_DAPM_MUX("ADCDAT Mux", SND_SOC_NOPM, 0, 0, 1804 &rt5682_adcdat_pin_ctrl), 1805 1806 SND_SOC_DAPM_MUX("DAC L Mux", SND_SOC_NOPM, 0, 0, 1807 &rt5682_dac_l_mux), 1808 SND_SOC_DAPM_MUX("DAC R Mux", SND_SOC_NOPM, 0, 0, 1809 &rt5682_dac_r_mux), 1810 1811 /* Audio Interface */ 1812 SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, 1813 RT5682_I2S1_SDP, RT5682_SEL_ADCDAT_SFT, 1), 1814 SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, 1815 RT5682_I2S2_SDP, RT5682_I2S2_PIN_CFG_SFT, 1), 1816 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0), 1817 SND_SOC_DAPM_AIF_IN("SDWRX", "SDW Playback", 0, SND_SOC_NOPM, 0, 0), 1818 SND_SOC_DAPM_AIF_OUT("SDWTX", "SDW Capture", 0, SND_SOC_NOPM, 0, 0), 1819 1820 /* Output Side */ 1821 /* DAC mixer before sound effect */ 1822 SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0, 1823 rt5682_dac_l_mix, ARRAY_SIZE(rt5682_dac_l_mix)), 1824 SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0, 1825 rt5682_dac_r_mix, ARRAY_SIZE(rt5682_dac_r_mix)), 1826 1827 /* DAC channel Mux */ 1828 SND_SOC_DAPM_MUX("DAC L1 Source", SND_SOC_NOPM, 0, 0, 1829 &rt5682_alg_dac_l1_mux), 1830 SND_SOC_DAPM_MUX("DAC R1 Source", SND_SOC_NOPM, 0, 0, 1831 &rt5682_alg_dac_r1_mux), 1832 1833 /* DAC Mixer */ 1834 SND_SOC_DAPM_SUPPLY("DAC Stereo1 Filter", RT5682_PWR_DIG_2, 1835 RT5682_PWR_DAC_S1F_BIT, 0, set_filter_clk, 1836 SND_SOC_DAPM_PRE_PMU), 1837 SND_SOC_DAPM_MIXER("Stereo1 DAC MIXL", SND_SOC_NOPM, 0, 0, 1838 rt5682_sto1_dac_l_mix, ARRAY_SIZE(rt5682_sto1_dac_l_mix)), 1839 SND_SOC_DAPM_MIXER("Stereo1 DAC MIXR", SND_SOC_NOPM, 0, 0, 1840 rt5682_sto1_dac_r_mix, ARRAY_SIZE(rt5682_sto1_dac_r_mix)), 1841 1842 /* DACs */ 1843 SND_SOC_DAPM_DAC("DAC L1", NULL, RT5682_PWR_DIG_1, 1844 RT5682_PWR_DAC_L1_BIT, 0), 1845 SND_SOC_DAPM_DAC("DAC R1", NULL, RT5682_PWR_DIG_1, 1846 RT5682_PWR_DAC_R1_BIT, 0), 1847 SND_SOC_DAPM_SUPPLY_S("DAC 1 Clock", 3, RT5682_CHOP_DAC, 1848 RT5682_CKGEN_DAC1_SFT, 0, NULL, 0), 1849 1850 /* HPO */ 1851 SND_SOC_DAPM_PGA_S("HP Amp", 1, SND_SOC_NOPM, 0, 0, rt5682_hp_event, 1852 SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_PRE_PMU), 1853 1854 SND_SOC_DAPM_SUPPLY("HP Amp L", RT5682_PWR_ANLG_1, 1855 RT5682_PWR_HA_L_BIT, 0, NULL, 0), 1856 SND_SOC_DAPM_SUPPLY("HP Amp R", RT5682_PWR_ANLG_1, 1857 RT5682_PWR_HA_R_BIT, 0, NULL, 0), 1858 SND_SOC_DAPM_SUPPLY_S("Charge Pump", 1, RT5682_DEPOP_1, 1859 RT5682_PUMP_EN_SFT, 0, NULL, 0), 1860 SND_SOC_DAPM_SUPPLY_S("Capless", 2, RT5682_DEPOP_1, 1861 RT5682_CAPLESS_EN_SFT, 0, NULL, 0), 1862 1863 SND_SOC_DAPM_SWITCH("HPOL Playback", SND_SOC_NOPM, 0, 0, 1864 &hpol_switch), 1865 SND_SOC_DAPM_SWITCH("HPOR Playback", SND_SOC_NOPM, 0, 0, 1866 &hpor_switch), 1867 1868 SND_SOC_DAPM_OUT_DRV("HPO Legacy", SND_SOC_NOPM, 0, 0, NULL, 0), 1869 SND_SOC_DAPM_OUT_DRV("HPO OneBit", SND_SOC_NOPM, 0, 0, NULL, 0), 1870 SND_SOC_DAPM_DEMUX("HPO Signal Demux", SND_SOC_NOPM, 0, 0, &rt5682_hpo_sig_demux), 1871 1872 /* CLK DET */ 1873 SND_SOC_DAPM_SUPPLY("CLKDET SYS", RT5682_CLK_DET, 1874 RT5682_SYS_CLK_DET_SFT, 0, NULL, 0), 1875 SND_SOC_DAPM_SUPPLY("CLKDET PLL1", RT5682_CLK_DET, 1876 RT5682_PLL1_CLK_DET_SFT, 0, NULL, 0), 1877 SND_SOC_DAPM_SUPPLY("CLKDET PLL2", RT5682_CLK_DET, 1878 RT5682_PLL2_CLK_DET_SFT, 0, NULL, 0), 1879 SND_SOC_DAPM_SUPPLY("CLKDET", RT5682_CLK_DET, 1880 RT5682_POW_CLK_DET_SFT, 0, NULL, 0), 1881 1882 /* Output Lines */ 1883 SND_SOC_DAPM_OUTPUT("HPOL"), 1884 SND_SOC_DAPM_OUTPUT("HPOR"), 1885 }; 1886 1887 static const struct snd_soc_dapm_route rt5682_dapm_routes[] = { 1888 /*PLL*/ 1889 {"ADC Stereo1 Filter", NULL, "PLL1", is_sys_clk_from_pll1}, 1890 {"ADC Stereo1 Filter", NULL, "PLL2B", is_sys_clk_from_pll2}, 1891 {"ADC Stereo1 Filter", NULL, "PLL2F", is_sys_clk_from_pll2}, 1892 {"DAC Stereo1 Filter", NULL, "PLL1", is_sys_clk_from_pll1}, 1893 {"DAC Stereo1 Filter", NULL, "PLL2B", is_sys_clk_from_pll2}, 1894 {"DAC Stereo1 Filter", NULL, "PLL2F", is_sys_clk_from_pll2}, 1895 1896 /*ASRC*/ 1897 {"ADC Stereo1 Filter", NULL, "ADC STO1 ASRC", is_using_asrc}, 1898 {"DAC Stereo1 Filter", NULL, "DAC STO1 ASRC", is_using_asrc}, 1899 {"ADC STO1 ASRC", NULL, "AD ASRC"}, 1900 {"ADC STO1 ASRC", NULL, "DA ASRC"}, 1901 {"ADC STO1 ASRC", NULL, "CLKDET"}, 1902 {"DAC STO1 ASRC", NULL, "AD ASRC"}, 1903 {"DAC STO1 ASRC", NULL, "DA ASRC"}, 1904 {"DAC STO1 ASRC", NULL, "CLKDET"}, 1905 1906 /*Vref*/ 1907 {"MICBIAS1", NULL, "Vref1"}, 1908 {"MICBIAS2", NULL, "Vref1"}, 1909 1910 {"CLKDET SYS", NULL, "CLKDET"}, 1911 1912 {"BST1 CBJ", NULL, "IN1P"}, 1913 1914 {"RECMIX1L", "CBJ Switch", "BST1 CBJ"}, 1915 {"RECMIX1L", NULL, "RECMIX1L Power"}, 1916 1917 {"ADC1 L", NULL, "RECMIX1L"}, 1918 {"ADC1 L", NULL, "ADC1 L Power"}, 1919 {"ADC1 L", NULL, "ADC1 clock"}, 1920 1921 {"DMIC L1", NULL, "DMIC CLK"}, 1922 {"DMIC L1", NULL, "DMIC1 Power"}, 1923 {"DMIC R1", NULL, "DMIC CLK"}, 1924 {"DMIC R1", NULL, "DMIC1 Power"}, 1925 {"DMIC CLK", NULL, "DMIC ASRC"}, 1926 1927 {"Stereo1 ADC L Mux", "ADC1 L", "ADC1 L"}, 1928 {"Stereo1 ADC L Mux", "ADC1 R", "ADC1 R"}, 1929 {"Stereo1 ADC R Mux", "ADC1 L", "ADC1 L"}, 1930 {"Stereo1 ADC R Mux", "ADC1 R", "ADC1 R"}, 1931 1932 {"Stereo1 ADC L1 Mux", "ADC", "Stereo1 ADC L Mux"}, 1933 {"Stereo1 ADC L1 Mux", "DAC MIX", "Stereo1 DAC MIXL"}, 1934 {"Stereo1 ADC L2 Mux", "DMIC", "DMIC L1"}, 1935 {"Stereo1 ADC L2 Mux", "DAC MIX", "Stereo1 DAC MIXL"}, 1936 1937 {"Stereo1 ADC R1 Mux", "ADC", "Stereo1 ADC R Mux"}, 1938 {"Stereo1 ADC R1 Mux", "DAC MIX", "Stereo1 DAC MIXR"}, 1939 {"Stereo1 ADC R2 Mux", "DMIC", "DMIC R1"}, 1940 {"Stereo1 ADC R2 Mux", "DAC MIX", "Stereo1 DAC MIXR"}, 1941 1942 {"Stereo1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC L1 Mux"}, 1943 {"Stereo1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC L2 Mux"}, 1944 {"Stereo1 ADC MIXL", NULL, "ADC Stereo1 Filter"}, 1945 1946 {"Stereo1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC R1 Mux"}, 1947 {"Stereo1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC R2 Mux"}, 1948 {"Stereo1 ADC MIXR", NULL, "ADC Stereo1 Filter"}, 1949 1950 {"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXL"}, 1951 {"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXR"}, 1952 1953 {"IF1 01 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"}, 1954 {"IF1 01 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"}, 1955 {"IF1 01 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"}, 1956 {"IF1 01 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"}, 1957 {"IF1 23 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"}, 1958 {"IF1 23 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"}, 1959 {"IF1 23 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"}, 1960 {"IF1 23 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"}, 1961 {"IF1 45 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"}, 1962 {"IF1 45 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"}, 1963 {"IF1 45 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"}, 1964 {"IF1 45 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"}, 1965 {"IF1 67 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"}, 1966 {"IF1 67 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"}, 1967 {"IF1 67 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"}, 1968 {"IF1 67 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"}, 1969 1970 {"IF1_ADC Mux", "Slot 0", "IF1 01 ADC Swap Mux"}, 1971 {"IF1_ADC Mux", "Slot 2", "IF1 23 ADC Swap Mux"}, 1972 {"IF1_ADC Mux", "Slot 4", "IF1 45 ADC Swap Mux"}, 1973 {"IF1_ADC Mux", "Slot 6", "IF1 67 ADC Swap Mux"}, 1974 {"ADCDAT Mux", "ADCDAT1", "IF1_ADC Mux"}, 1975 {"AIF1TX", NULL, "I2S1"}, 1976 {"AIF1TX", NULL, "ADCDAT Mux"}, 1977 {"IF2 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"}, 1978 {"IF2 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"}, 1979 {"IF2 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"}, 1980 {"IF2 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"}, 1981 {"ADCDAT Mux", "ADCDAT2", "IF2 ADC Swap Mux"}, 1982 {"AIF2TX", NULL, "ADCDAT Mux"}, 1983 1984 {"SDWTX", NULL, "PLL2B"}, 1985 {"SDWTX", NULL, "PLL2F"}, 1986 {"SDWTX", NULL, "ADCDAT Mux"}, 1987 1988 {"IF1 DAC1 L", NULL, "AIF1RX"}, 1989 {"IF1 DAC1 L", NULL, "I2S1"}, 1990 {"IF1 DAC1 L", NULL, "DAC Stereo1 Filter"}, 1991 {"IF1 DAC1 R", NULL, "AIF1RX"}, 1992 {"IF1 DAC1 R", NULL, "I2S1"}, 1993 {"IF1 DAC1 R", NULL, "DAC Stereo1 Filter"}, 1994 1995 {"SOUND DAC L", NULL, "SDWRX"}, 1996 {"SOUND DAC L", NULL, "DAC Stereo1 Filter"}, 1997 {"SOUND DAC L", NULL, "PLL2B"}, 1998 {"SOUND DAC L", NULL, "PLL2F"}, 1999 {"SOUND DAC R", NULL, "SDWRX"}, 2000 {"SOUND DAC R", NULL, "DAC Stereo1 Filter"}, 2001 {"SOUND DAC R", NULL, "PLL2B"}, 2002 {"SOUND DAC R", NULL, "PLL2F"}, 2003 2004 {"DAC L Mux", "IF1", "IF1 DAC1 L"}, 2005 {"DAC L Mux", "SOUND", "SOUND DAC L"}, 2006 {"DAC R Mux", "IF1", "IF1 DAC1 R"}, 2007 {"DAC R Mux", "SOUND", "SOUND DAC R"}, 2008 2009 {"DAC1 MIXL", "Stereo ADC Switch", "Stereo1 ADC MIXL"}, 2010 {"DAC1 MIXL", "DAC1 Switch", "DAC L Mux"}, 2011 {"DAC1 MIXR", "Stereo ADC Switch", "Stereo1 ADC MIXR"}, 2012 {"DAC1 MIXR", "DAC1 Switch", "DAC R Mux"}, 2013 2014 {"Stereo1 DAC MIXL", "DAC L1 Switch", "DAC1 MIXL"}, 2015 {"Stereo1 DAC MIXL", "DAC R1 Switch", "DAC1 MIXR"}, 2016 2017 {"Stereo1 DAC MIXR", "DAC R1 Switch", "DAC1 MIXR"}, 2018 {"Stereo1 DAC MIXR", "DAC L1 Switch", "DAC1 MIXL"}, 2019 2020 {"DAC L1 Source", "DAC1", "DAC1 MIXL"}, 2021 {"DAC L1 Source", "Stereo1 DAC Mixer", "Stereo1 DAC MIXL"}, 2022 {"DAC R1 Source", "DAC1", "DAC1 MIXR"}, 2023 {"DAC R1 Source", "Stereo1 DAC Mixer", "Stereo1 DAC MIXR"}, 2024 2025 {"DAC L1", NULL, "DAC L1 Source"}, 2026 {"DAC R1", NULL, "DAC R1 Source"}, 2027 2028 {"DAC L1", NULL, "DAC 1 Clock"}, 2029 {"DAC R1", NULL, "DAC 1 Clock"}, 2030 2031 {"HP Amp", NULL, "DAC L1"}, 2032 {"HP Amp", NULL, "DAC R1"}, 2033 {"HP Amp", NULL, "HP Amp L"}, 2034 {"HP Amp", NULL, "HP Amp R"}, 2035 {"HP Amp", NULL, "Capless"}, 2036 {"HP Amp", NULL, "Charge Pump"}, 2037 {"HP Amp", NULL, "CLKDET SYS"}, 2038 {"HP Amp", NULL, "Vref1"}, 2039 2040 {"HPO Signal Demux", NULL, "HP Amp"}, 2041 2042 {"HPO Legacy", "Legacy", "HPO Signal Demux"}, 2043 {"HPO OneBit", "OneBit", "HPO Signal Demux"}, 2044 2045 {"HPOL Playback", "Switch", "HPO Legacy"}, 2046 {"HPOR Playback", "Switch", "HPO Legacy"}, 2047 2048 {"HPOL", NULL, "HPOL Playback"}, 2049 {"HPOR", NULL, "HPOR Playback"}, 2050 {"HPOL", NULL, "HPO OneBit"}, 2051 {"HPOR", NULL, "HPO OneBit"}, 2052 }; 2053 2054 static int rt5682_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask, 2055 unsigned int rx_mask, int slots, int slot_width) 2056 { 2057 struct snd_soc_component *component = dai->component; 2058 unsigned int cl, val = 0; 2059 2060 if (tx_mask || rx_mask) 2061 snd_soc_component_update_bits(component, RT5682_TDM_ADDA_CTRL_2, 2062 RT5682_TDM_EN, RT5682_TDM_EN); 2063 else 2064 snd_soc_component_update_bits(component, RT5682_TDM_ADDA_CTRL_2, 2065 RT5682_TDM_EN, 0); 2066 2067 switch (slots) { 2068 case 4: 2069 val |= RT5682_TDM_TX_CH_4; 2070 val |= RT5682_TDM_RX_CH_4; 2071 break; 2072 case 6: 2073 val |= RT5682_TDM_TX_CH_6; 2074 val |= RT5682_TDM_RX_CH_6; 2075 break; 2076 case 8: 2077 val |= RT5682_TDM_TX_CH_8; 2078 val |= RT5682_TDM_RX_CH_8; 2079 break; 2080 case 2: 2081 break; 2082 default: 2083 return -EINVAL; 2084 } 2085 2086 snd_soc_component_update_bits(component, RT5682_TDM_CTRL, 2087 RT5682_TDM_TX_CH_MASK | RT5682_TDM_RX_CH_MASK, val); 2088 2089 switch (slot_width) { 2090 case 8: 2091 if (tx_mask || rx_mask) 2092 return -EINVAL; 2093 cl = RT5682_I2S1_TX_CHL_8 | RT5682_I2S1_RX_CHL_8; 2094 break; 2095 case 16: 2096 val = RT5682_TDM_CL_16; 2097 cl = RT5682_I2S1_TX_CHL_16 | RT5682_I2S1_RX_CHL_16; 2098 break; 2099 case 20: 2100 val = RT5682_TDM_CL_20; 2101 cl = RT5682_I2S1_TX_CHL_20 | RT5682_I2S1_RX_CHL_20; 2102 break; 2103 case 24: 2104 val = RT5682_TDM_CL_24; 2105 cl = RT5682_I2S1_TX_CHL_24 | RT5682_I2S1_RX_CHL_24; 2106 break; 2107 case 32: 2108 val = RT5682_TDM_CL_32; 2109 cl = RT5682_I2S1_TX_CHL_32 | RT5682_I2S1_RX_CHL_32; 2110 break; 2111 default: 2112 return -EINVAL; 2113 } 2114 2115 snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL, 2116 RT5682_TDM_CL_MASK, val); 2117 snd_soc_component_update_bits(component, RT5682_I2S1_SDP, 2118 RT5682_I2S1_TX_CHL_MASK | RT5682_I2S1_RX_CHL_MASK, cl); 2119 2120 return 0; 2121 } 2122 2123 static int rt5682_hw_params(struct snd_pcm_substream *substream, 2124 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) 2125 { 2126 struct snd_soc_component *component = dai->component; 2127 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 2128 unsigned int len_1 = 0, len_2 = 0; 2129 int pre_div, frame_size; 2130 2131 rt5682->lrck[dai->id] = params_rate(params); 2132 pre_div = rl6231_get_clk_info(rt5682->sysclk, rt5682->lrck[dai->id]); 2133 2134 frame_size = snd_soc_params_to_frame_size(params); 2135 if (frame_size < 0) { 2136 dev_err(component->dev, "Unsupported frame size: %d\n", 2137 frame_size); 2138 return -EINVAL; 2139 } 2140 2141 dev_dbg(dai->dev, "lrck is %dHz and pre_div is %d for iis %d\n", 2142 rt5682->lrck[dai->id], pre_div, dai->id); 2143 2144 switch (params_width(params)) { 2145 case 16: 2146 break; 2147 case 20: 2148 len_1 |= RT5682_I2S1_DL_20; 2149 len_2 |= RT5682_I2S2_DL_20; 2150 break; 2151 case 24: 2152 len_1 |= RT5682_I2S1_DL_24; 2153 len_2 |= RT5682_I2S2_DL_24; 2154 break; 2155 case 32: 2156 len_1 |= RT5682_I2S1_DL_32; 2157 len_2 |= RT5682_I2S2_DL_24; 2158 break; 2159 case 8: 2160 len_1 |= RT5682_I2S2_DL_8; 2161 len_2 |= RT5682_I2S2_DL_8; 2162 break; 2163 default: 2164 return -EINVAL; 2165 } 2166 2167 switch (dai->id) { 2168 case RT5682_AIF1: 2169 snd_soc_component_update_bits(component, RT5682_I2S1_SDP, 2170 RT5682_I2S1_DL_MASK, len_1); 2171 if (rt5682->master[RT5682_AIF1]) { 2172 snd_soc_component_update_bits(component, 2173 RT5682_ADDA_CLK_1, RT5682_I2S_M_DIV_MASK | 2174 RT5682_I2S_CLK_SRC_MASK, 2175 pre_div << RT5682_I2S_M_DIV_SFT | 2176 (rt5682->sysclk_src) << RT5682_I2S_CLK_SRC_SFT); 2177 } 2178 if (params_channels(params) == 1) /* mono mode */ 2179 snd_soc_component_update_bits(component, 2180 RT5682_I2S1_SDP, RT5682_I2S1_MONO_MASK, 2181 RT5682_I2S1_MONO_EN); 2182 else 2183 snd_soc_component_update_bits(component, 2184 RT5682_I2S1_SDP, RT5682_I2S1_MONO_MASK, 2185 RT5682_I2S1_MONO_DIS); 2186 break; 2187 case RT5682_AIF2: 2188 snd_soc_component_update_bits(component, RT5682_I2S2_SDP, 2189 RT5682_I2S2_DL_MASK, len_2); 2190 if (rt5682->master[RT5682_AIF2]) { 2191 snd_soc_component_update_bits(component, 2192 RT5682_I2S_M_CLK_CTRL_1, RT5682_I2S2_M_PD_MASK, 2193 pre_div << RT5682_I2S2_M_PD_SFT); 2194 } 2195 if (params_channels(params) == 1) /* mono mode */ 2196 snd_soc_component_update_bits(component, 2197 RT5682_I2S2_SDP, RT5682_I2S2_MONO_MASK, 2198 RT5682_I2S2_MONO_EN); 2199 else 2200 snd_soc_component_update_bits(component, 2201 RT5682_I2S2_SDP, RT5682_I2S2_MONO_MASK, 2202 RT5682_I2S2_MONO_DIS); 2203 break; 2204 default: 2205 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id); 2206 return -EINVAL; 2207 } 2208 2209 return 0; 2210 } 2211 2212 static int rt5682_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) 2213 { 2214 struct snd_soc_component *component = dai->component; 2215 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 2216 unsigned int reg_val = 0, tdm_ctrl = 0; 2217 2218 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 2219 case SND_SOC_DAIFMT_CBM_CFM: 2220 rt5682->master[dai->id] = 1; 2221 break; 2222 case SND_SOC_DAIFMT_CBS_CFS: 2223 rt5682->master[dai->id] = 0; 2224 break; 2225 default: 2226 return -EINVAL; 2227 } 2228 2229 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 2230 case SND_SOC_DAIFMT_NB_NF: 2231 break; 2232 case SND_SOC_DAIFMT_IB_NF: 2233 reg_val |= RT5682_I2S_BP_INV; 2234 tdm_ctrl |= RT5682_TDM_S_BP_INV; 2235 break; 2236 case SND_SOC_DAIFMT_NB_IF: 2237 if (dai->id == RT5682_AIF1) 2238 tdm_ctrl |= RT5682_TDM_S_LP_INV | RT5682_TDM_M_BP_INV; 2239 else 2240 return -EINVAL; 2241 break; 2242 case SND_SOC_DAIFMT_IB_IF: 2243 if (dai->id == RT5682_AIF1) 2244 tdm_ctrl |= RT5682_TDM_S_BP_INV | RT5682_TDM_S_LP_INV | 2245 RT5682_TDM_M_BP_INV | RT5682_TDM_M_LP_INV; 2246 else 2247 return -EINVAL; 2248 break; 2249 default: 2250 return -EINVAL; 2251 } 2252 2253 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 2254 case SND_SOC_DAIFMT_I2S: 2255 break; 2256 case SND_SOC_DAIFMT_LEFT_J: 2257 reg_val |= RT5682_I2S_DF_LEFT; 2258 tdm_ctrl |= RT5682_TDM_DF_LEFT; 2259 break; 2260 case SND_SOC_DAIFMT_DSP_A: 2261 reg_val |= RT5682_I2S_DF_PCM_A; 2262 tdm_ctrl |= RT5682_TDM_DF_PCM_A; 2263 break; 2264 case SND_SOC_DAIFMT_DSP_B: 2265 reg_val |= RT5682_I2S_DF_PCM_B; 2266 tdm_ctrl |= RT5682_TDM_DF_PCM_B; 2267 break; 2268 default: 2269 return -EINVAL; 2270 } 2271 2272 switch (dai->id) { 2273 case RT5682_AIF1: 2274 snd_soc_component_update_bits(component, RT5682_I2S1_SDP, 2275 RT5682_I2S_DF_MASK, reg_val); 2276 snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL, 2277 RT5682_TDM_MS_MASK | RT5682_TDM_S_BP_MASK | 2278 RT5682_TDM_DF_MASK | RT5682_TDM_M_BP_MASK | 2279 RT5682_TDM_M_LP_MASK | RT5682_TDM_S_LP_MASK, 2280 tdm_ctrl | rt5682->master[dai->id]); 2281 break; 2282 case RT5682_AIF2: 2283 if (rt5682->master[dai->id] == 0) 2284 reg_val |= RT5682_I2S2_MS_S; 2285 snd_soc_component_update_bits(component, RT5682_I2S2_SDP, 2286 RT5682_I2S2_MS_MASK | RT5682_I2S_BP_MASK | 2287 RT5682_I2S_DF_MASK, reg_val); 2288 break; 2289 default: 2290 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id); 2291 return -EINVAL; 2292 } 2293 return 0; 2294 } 2295 2296 static int rt5682_set_component_sysclk(struct snd_soc_component *component, 2297 int clk_id, int source, unsigned int freq, int dir) 2298 { 2299 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 2300 unsigned int reg_val = 0, src = 0; 2301 2302 if (freq == rt5682->sysclk && clk_id == rt5682->sysclk_src) 2303 return 0; 2304 2305 switch (clk_id) { 2306 case RT5682_SCLK_S_MCLK: 2307 reg_val |= RT5682_SCLK_SRC_MCLK; 2308 src = RT5682_CLK_SRC_MCLK; 2309 break; 2310 case RT5682_SCLK_S_PLL1: 2311 reg_val |= RT5682_SCLK_SRC_PLL1; 2312 src = RT5682_CLK_SRC_PLL1; 2313 break; 2314 case RT5682_SCLK_S_PLL2: 2315 reg_val |= RT5682_SCLK_SRC_PLL2; 2316 src = RT5682_CLK_SRC_PLL2; 2317 break; 2318 case RT5682_SCLK_S_RCCLK: 2319 reg_val |= RT5682_SCLK_SRC_RCCLK; 2320 src = RT5682_CLK_SRC_RCCLK; 2321 break; 2322 default: 2323 dev_err(component->dev, "Invalid clock id (%d)\n", clk_id); 2324 return -EINVAL; 2325 } 2326 snd_soc_component_update_bits(component, RT5682_GLB_CLK, 2327 RT5682_SCLK_SRC_MASK, reg_val); 2328 2329 if (rt5682->master[RT5682_AIF2]) { 2330 snd_soc_component_update_bits(component, 2331 RT5682_I2S_M_CLK_CTRL_1, RT5682_I2S2_SRC_MASK, 2332 src << RT5682_I2S2_SRC_SFT); 2333 } 2334 2335 rt5682->sysclk = freq; 2336 rt5682->sysclk_src = clk_id; 2337 2338 dev_dbg(component->dev, "Sysclk is %dHz and clock id is %d\n", 2339 freq, clk_id); 2340 2341 return 0; 2342 } 2343 2344 static int rt5682_set_component_pll(struct snd_soc_component *component, 2345 int pll_id, int source, unsigned int freq_in, 2346 unsigned int freq_out) 2347 { 2348 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 2349 struct rl6231_pll_code pll_code, pll2f_code, pll2b_code; 2350 unsigned int pll2_fout1, pll2_ps_val; 2351 int ret; 2352 2353 if (source == rt5682->pll_src[pll_id] && 2354 freq_in == rt5682->pll_in[pll_id] && 2355 freq_out == rt5682->pll_out[pll_id]) 2356 return 0; 2357 2358 if (!freq_in || !freq_out) { 2359 dev_dbg(component->dev, "PLL disabled\n"); 2360 2361 rt5682->pll_in[pll_id] = 0; 2362 rt5682->pll_out[pll_id] = 0; 2363 snd_soc_component_update_bits(component, RT5682_GLB_CLK, 2364 RT5682_SCLK_SRC_MASK, RT5682_SCLK_SRC_MCLK); 2365 return 0; 2366 } 2367 2368 if (pll_id == RT5682_PLL2) { 2369 switch (source) { 2370 case RT5682_PLL2_S_MCLK: 2371 snd_soc_component_update_bits(component, 2372 RT5682_GLB_CLK, RT5682_PLL2_SRC_MASK, 2373 RT5682_PLL2_SRC_MCLK); 2374 break; 2375 default: 2376 dev_err(component->dev, "Unknown PLL2 Source %d\n", 2377 source); 2378 return -EINVAL; 2379 } 2380 2381 /** 2382 * PLL2 concatenates 2 PLL units. 2383 * We suggest the Fout of the front PLL is 3.84MHz. 2384 */ 2385 pll2_fout1 = 3840000; 2386 ret = rl6231_pll_calc(freq_in, pll2_fout1, &pll2f_code); 2387 if (ret < 0) { 2388 dev_err(component->dev, "Unsupported input clock %d\n", 2389 freq_in); 2390 return ret; 2391 } 2392 dev_dbg(component->dev, "PLL2F: fin=%d fout=%d bypass=%d m=%d n=%d k=%d\n", 2393 freq_in, pll2_fout1, 2394 pll2f_code.m_bp, 2395 (pll2f_code.m_bp ? 0 : pll2f_code.m_code), 2396 pll2f_code.n_code, pll2f_code.k_code); 2397 2398 ret = rl6231_pll_calc(pll2_fout1, freq_out, &pll2b_code); 2399 if (ret < 0) { 2400 dev_err(component->dev, "Unsupported input clock %d\n", 2401 pll2_fout1); 2402 return ret; 2403 } 2404 dev_dbg(component->dev, "PLL2B: fin=%d fout=%d bypass=%d m=%d n=%d k=%d\n", 2405 pll2_fout1, freq_out, 2406 pll2b_code.m_bp, 2407 (pll2b_code.m_bp ? 0 : pll2b_code.m_code), 2408 pll2b_code.n_code, pll2b_code.k_code); 2409 2410 snd_soc_component_write(component, RT5682_PLL2_CTRL_1, 2411 pll2f_code.k_code << RT5682_PLL2F_K_SFT | 2412 pll2b_code.k_code << RT5682_PLL2B_K_SFT | 2413 pll2b_code.m_code); 2414 snd_soc_component_write(component, RT5682_PLL2_CTRL_2, 2415 pll2f_code.m_code << RT5682_PLL2F_M_SFT | 2416 pll2b_code.n_code); 2417 snd_soc_component_write(component, RT5682_PLL2_CTRL_3, 2418 pll2f_code.n_code << RT5682_PLL2F_N_SFT); 2419 2420 if (freq_out == 22579200) 2421 pll2_ps_val = 1 << RT5682_PLL2B_SEL_PS_SFT; 2422 else 2423 pll2_ps_val = 1 << RT5682_PLL2B_PS_BYP_SFT; 2424 snd_soc_component_update_bits(component, RT5682_PLL2_CTRL_4, 2425 RT5682_PLL2B_SEL_PS_MASK | RT5682_PLL2B_PS_BYP_MASK | 2426 RT5682_PLL2B_M_BP_MASK | RT5682_PLL2F_M_BP_MASK | 0xf, 2427 pll2_ps_val | 2428 (pll2b_code.m_bp ? 1 : 0) << RT5682_PLL2B_M_BP_SFT | 2429 (pll2f_code.m_bp ? 1 : 0) << RT5682_PLL2F_M_BP_SFT | 2430 0xf); 2431 } else { 2432 switch (source) { 2433 case RT5682_PLL1_S_MCLK: 2434 snd_soc_component_update_bits(component, 2435 RT5682_GLB_CLK, RT5682_PLL1_SRC_MASK, 2436 RT5682_PLL1_SRC_MCLK); 2437 break; 2438 case RT5682_PLL1_S_BCLK1: 2439 snd_soc_component_update_bits(component, 2440 RT5682_GLB_CLK, RT5682_PLL1_SRC_MASK, 2441 RT5682_PLL1_SRC_BCLK1); 2442 break; 2443 default: 2444 dev_err(component->dev, "Unknown PLL1 Source %d\n", 2445 source); 2446 return -EINVAL; 2447 } 2448 2449 ret = rl6231_pll_calc(freq_in, freq_out, &pll_code); 2450 if (ret < 0) { 2451 dev_err(component->dev, "Unsupported input clock %d\n", 2452 freq_in); 2453 return ret; 2454 } 2455 2456 dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n", 2457 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code), 2458 pll_code.n_code, pll_code.k_code); 2459 2460 snd_soc_component_write(component, RT5682_PLL_CTRL_1, 2461 (pll_code.n_code << RT5682_PLL_N_SFT) | pll_code.k_code); 2462 snd_soc_component_write(component, RT5682_PLL_CTRL_2, 2463 ((pll_code.m_bp ? 0 : pll_code.m_code) << RT5682_PLL_M_SFT) | 2464 ((pll_code.m_bp << RT5682_PLL_M_BP_SFT) | RT5682_PLL_RST)); 2465 } 2466 2467 rt5682->pll_in[pll_id] = freq_in; 2468 rt5682->pll_out[pll_id] = freq_out; 2469 rt5682->pll_src[pll_id] = source; 2470 2471 return 0; 2472 } 2473 2474 static int rt5682_set_bclk1_ratio(struct snd_soc_dai *dai, unsigned int ratio) 2475 { 2476 struct snd_soc_component *component = dai->component; 2477 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 2478 2479 rt5682->bclk[dai->id] = ratio; 2480 2481 switch (ratio) { 2482 case 256: 2483 snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL, 2484 RT5682_TDM_BCLK_MS1_MASK, RT5682_TDM_BCLK_MS1_256); 2485 break; 2486 case 128: 2487 snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL, 2488 RT5682_TDM_BCLK_MS1_MASK, RT5682_TDM_BCLK_MS1_128); 2489 break; 2490 case 64: 2491 snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL, 2492 RT5682_TDM_BCLK_MS1_MASK, RT5682_TDM_BCLK_MS1_64); 2493 break; 2494 case 32: 2495 snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL, 2496 RT5682_TDM_BCLK_MS1_MASK, RT5682_TDM_BCLK_MS1_32); 2497 break; 2498 default: 2499 dev_err(dai->dev, "Invalid bclk1 ratio %d\n", ratio); 2500 return -EINVAL; 2501 } 2502 2503 return 0; 2504 } 2505 2506 static int rt5682_set_bclk2_ratio(struct snd_soc_dai *dai, unsigned int ratio) 2507 { 2508 struct snd_soc_component *component = dai->component; 2509 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 2510 2511 rt5682->bclk[dai->id] = ratio; 2512 2513 switch (ratio) { 2514 case 64: 2515 snd_soc_component_update_bits(component, RT5682_ADDA_CLK_2, 2516 RT5682_I2S2_BCLK_MS2_MASK, 2517 RT5682_I2S2_BCLK_MS2_64); 2518 break; 2519 case 32: 2520 snd_soc_component_update_bits(component, RT5682_ADDA_CLK_2, 2521 RT5682_I2S2_BCLK_MS2_MASK, 2522 RT5682_I2S2_BCLK_MS2_32); 2523 break; 2524 default: 2525 dev_err(dai->dev, "Invalid bclk2 ratio %d\n", ratio); 2526 return -EINVAL; 2527 } 2528 2529 return 0; 2530 } 2531 2532 static int rt5682_set_bias_level(struct snd_soc_component *component, 2533 enum snd_soc_bias_level level) 2534 { 2535 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 2536 2537 switch (level) { 2538 case SND_SOC_BIAS_PREPARE: 2539 regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_1, 2540 RT5682_PWR_BG, RT5682_PWR_BG); 2541 regmap_update_bits(rt5682->regmap, RT5682_PWR_DIG_1, 2542 RT5682_DIG_GATE_CTRL | RT5682_PWR_LDO, 2543 RT5682_DIG_GATE_CTRL | RT5682_PWR_LDO); 2544 break; 2545 2546 case SND_SOC_BIAS_STANDBY: 2547 regmap_update_bits(rt5682->regmap, RT5682_PWR_DIG_1, 2548 RT5682_DIG_GATE_CTRL, RT5682_DIG_GATE_CTRL); 2549 break; 2550 case SND_SOC_BIAS_OFF: 2551 regmap_update_bits(rt5682->regmap, RT5682_PWR_DIG_1, 2552 RT5682_DIG_GATE_CTRL | RT5682_PWR_LDO, 0); 2553 regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_1, 2554 RT5682_PWR_BG, 0); 2555 break; 2556 case SND_SOC_BIAS_ON: 2557 break; 2558 } 2559 2560 return 0; 2561 } 2562 2563 #ifdef CONFIG_COMMON_CLK 2564 #define CLK_PLL2_FIN 48000000 2565 #define CLK_48 48000 2566 #define CLK_44 44100 2567 2568 static bool rt5682_clk_check(struct rt5682_priv *rt5682) 2569 { 2570 if (!rt5682->master[RT5682_AIF1]) { 2571 dev_dbg(rt5682->i2c_dev, "sysclk/dai not set correctly\n"); 2572 return false; 2573 } 2574 return true; 2575 } 2576 2577 static int rt5682_wclk_prepare(struct clk_hw *hw) 2578 { 2579 struct rt5682_priv *rt5682 = 2580 container_of(hw, struct rt5682_priv, 2581 dai_clks_hw[RT5682_DAI_WCLK_IDX]); 2582 struct snd_soc_component *component; 2583 struct snd_soc_dapm_context *dapm; 2584 2585 if (!rt5682_clk_check(rt5682)) 2586 return -EINVAL; 2587 2588 component = rt5682->component; 2589 dapm = snd_soc_component_get_dapm(component); 2590 2591 snd_soc_dapm_mutex_lock(dapm); 2592 2593 snd_soc_dapm_force_enable_pin_unlocked(dapm, "MICBIAS"); 2594 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_1, 2595 RT5682_PWR_MB, RT5682_PWR_MB); 2596 2597 snd_soc_dapm_force_enable_pin_unlocked(dapm, "Vref2"); 2598 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_1, 2599 RT5682_PWR_VREF2 | RT5682_PWR_FV2, 2600 RT5682_PWR_VREF2); 2601 usleep_range(55000, 60000); 2602 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_1, 2603 RT5682_PWR_FV2, RT5682_PWR_FV2); 2604 2605 snd_soc_dapm_force_enable_pin_unlocked(dapm, "I2S1"); 2606 snd_soc_dapm_force_enable_pin_unlocked(dapm, "PLL2F"); 2607 snd_soc_dapm_force_enable_pin_unlocked(dapm, "PLL2B"); 2608 snd_soc_dapm_sync_unlocked(dapm); 2609 2610 snd_soc_dapm_mutex_unlock(dapm); 2611 2612 return 0; 2613 } 2614 2615 static void rt5682_wclk_unprepare(struct clk_hw *hw) 2616 { 2617 struct rt5682_priv *rt5682 = 2618 container_of(hw, struct rt5682_priv, 2619 dai_clks_hw[RT5682_DAI_WCLK_IDX]); 2620 struct snd_soc_component *component; 2621 struct snd_soc_dapm_context *dapm; 2622 2623 if (!rt5682_clk_check(rt5682)) 2624 return; 2625 2626 component = rt5682->component; 2627 dapm = snd_soc_component_get_dapm(component); 2628 2629 snd_soc_dapm_mutex_lock(dapm); 2630 2631 snd_soc_dapm_disable_pin_unlocked(dapm, "MICBIAS"); 2632 snd_soc_dapm_disable_pin_unlocked(dapm, "Vref2"); 2633 if (!rt5682->jack_type) 2634 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_1, 2635 RT5682_PWR_VREF2 | RT5682_PWR_FV2 | 2636 RT5682_PWR_MB, 0); 2637 2638 snd_soc_dapm_disable_pin_unlocked(dapm, "I2S1"); 2639 snd_soc_dapm_disable_pin_unlocked(dapm, "PLL2F"); 2640 snd_soc_dapm_disable_pin_unlocked(dapm, "PLL2B"); 2641 snd_soc_dapm_sync_unlocked(dapm); 2642 2643 snd_soc_dapm_mutex_unlock(dapm); 2644 } 2645 2646 static unsigned long rt5682_wclk_recalc_rate(struct clk_hw *hw, 2647 unsigned long parent_rate) 2648 { 2649 struct rt5682_priv *rt5682 = 2650 container_of(hw, struct rt5682_priv, 2651 dai_clks_hw[RT5682_DAI_WCLK_IDX]); 2652 const char * const clk_name = clk_hw_get_name(hw); 2653 2654 if (!rt5682_clk_check(rt5682)) 2655 return 0; 2656 /* 2657 * Only accept to set wclk rate to 44.1k or 48kHz. 2658 */ 2659 if (rt5682->lrck[RT5682_AIF1] != CLK_48 && 2660 rt5682->lrck[RT5682_AIF1] != CLK_44) { 2661 dev_warn(rt5682->i2c_dev, "%s: clk %s only support %d or %d Hz output\n", 2662 __func__, clk_name, CLK_44, CLK_48); 2663 return 0; 2664 } 2665 2666 return rt5682->lrck[RT5682_AIF1]; 2667 } 2668 2669 static long rt5682_wclk_round_rate(struct clk_hw *hw, unsigned long rate, 2670 unsigned long *parent_rate) 2671 { 2672 struct rt5682_priv *rt5682 = 2673 container_of(hw, struct rt5682_priv, 2674 dai_clks_hw[RT5682_DAI_WCLK_IDX]); 2675 const char * const clk_name = clk_hw_get_name(hw); 2676 2677 if (!rt5682_clk_check(rt5682)) 2678 return -EINVAL; 2679 /* 2680 * Only accept to set wclk rate to 44.1k or 48kHz. 2681 * It will force to 48kHz if not both. 2682 */ 2683 if (rate != CLK_48 && rate != CLK_44) { 2684 dev_warn(rt5682->i2c_dev, "%s: clk %s only support %d or %d Hz output\n", 2685 __func__, clk_name, CLK_44, CLK_48); 2686 rate = CLK_48; 2687 } 2688 2689 return rate; 2690 } 2691 2692 static int rt5682_wclk_set_rate(struct clk_hw *hw, unsigned long rate, 2693 unsigned long parent_rate) 2694 { 2695 struct rt5682_priv *rt5682 = 2696 container_of(hw, struct rt5682_priv, 2697 dai_clks_hw[RT5682_DAI_WCLK_IDX]); 2698 struct snd_soc_component *component; 2699 struct clk_hw *parent_hw; 2700 const char * const clk_name = clk_hw_get_name(hw); 2701 int pre_div; 2702 unsigned int clk_pll2_out; 2703 2704 if (!rt5682_clk_check(rt5682)) 2705 return -EINVAL; 2706 2707 component = rt5682->component; 2708 2709 /* 2710 * Whether the wclk's parent clk (mclk) exists or not, please ensure 2711 * it is fixed or set to 48MHz before setting wclk rate. It's a 2712 * temporary limitation. Only accept 48MHz clk as the clk provider. 2713 * 2714 * It will set the codec anyway by assuming mclk is 48MHz. 2715 */ 2716 parent_hw = clk_hw_get_parent(hw); 2717 if (!parent_hw) 2718 dev_warn(rt5682->i2c_dev, 2719 "Parent mclk of wclk not acquired in driver. Please ensure mclk was provided as %d Hz.\n", 2720 CLK_PLL2_FIN); 2721 2722 if (parent_rate != CLK_PLL2_FIN) 2723 dev_warn(rt5682->i2c_dev, "clk %s only support %d Hz input\n", 2724 clk_name, CLK_PLL2_FIN); 2725 2726 /* 2727 * To achieve the rate conversion from 48MHz to 44.1k or 48kHz, 2728 * PLL2 is needed. 2729 */ 2730 clk_pll2_out = rate * 512; 2731 rt5682_set_component_pll(component, RT5682_PLL2, RT5682_PLL2_S_MCLK, 2732 CLK_PLL2_FIN, clk_pll2_out); 2733 2734 rt5682_set_component_sysclk(component, RT5682_SCLK_S_PLL2, 0, 2735 clk_pll2_out, SND_SOC_CLOCK_IN); 2736 2737 rt5682->lrck[RT5682_AIF1] = rate; 2738 2739 pre_div = rl6231_get_clk_info(rt5682->sysclk, rate); 2740 2741 snd_soc_component_update_bits(component, RT5682_ADDA_CLK_1, 2742 RT5682_I2S_M_DIV_MASK | RT5682_I2S_CLK_SRC_MASK, 2743 pre_div << RT5682_I2S_M_DIV_SFT | 2744 (rt5682->sysclk_src) << RT5682_I2S_CLK_SRC_SFT); 2745 2746 return 0; 2747 } 2748 2749 static unsigned long rt5682_bclk_recalc_rate(struct clk_hw *hw, 2750 unsigned long parent_rate) 2751 { 2752 struct rt5682_priv *rt5682 = 2753 container_of(hw, struct rt5682_priv, 2754 dai_clks_hw[RT5682_DAI_BCLK_IDX]); 2755 unsigned int bclks_per_wclk; 2756 2757 regmap_read(rt5682->regmap, RT5682_TDM_TCON_CTRL, &bclks_per_wclk); 2758 2759 switch (bclks_per_wclk & RT5682_TDM_BCLK_MS1_MASK) { 2760 case RT5682_TDM_BCLK_MS1_256: 2761 return parent_rate * 256; 2762 case RT5682_TDM_BCLK_MS1_128: 2763 return parent_rate * 128; 2764 case RT5682_TDM_BCLK_MS1_64: 2765 return parent_rate * 64; 2766 case RT5682_TDM_BCLK_MS1_32: 2767 return parent_rate * 32; 2768 default: 2769 return 0; 2770 } 2771 } 2772 2773 static unsigned long rt5682_bclk_get_factor(unsigned long rate, 2774 unsigned long parent_rate) 2775 { 2776 unsigned long factor; 2777 2778 factor = rate / parent_rate; 2779 if (factor < 64) 2780 return 32; 2781 else if (factor < 128) 2782 return 64; 2783 else if (factor < 256) 2784 return 128; 2785 else 2786 return 256; 2787 } 2788 2789 static long rt5682_bclk_round_rate(struct clk_hw *hw, unsigned long rate, 2790 unsigned long *parent_rate) 2791 { 2792 struct rt5682_priv *rt5682 = 2793 container_of(hw, struct rt5682_priv, 2794 dai_clks_hw[RT5682_DAI_BCLK_IDX]); 2795 unsigned long factor; 2796 2797 if (!*parent_rate || !rt5682_clk_check(rt5682)) 2798 return -EINVAL; 2799 2800 /* 2801 * BCLK rates are set as a multiplier of WCLK in HW. 2802 * We don't allow changing the parent WCLK. We just do 2803 * some rounding down based on the parent WCLK rate 2804 * and find the appropriate multiplier of BCLK to 2805 * get the rounded down BCLK value. 2806 */ 2807 factor = rt5682_bclk_get_factor(rate, *parent_rate); 2808 2809 return *parent_rate * factor; 2810 } 2811 2812 static int rt5682_bclk_set_rate(struct clk_hw *hw, unsigned long rate, 2813 unsigned long parent_rate) 2814 { 2815 struct rt5682_priv *rt5682 = 2816 container_of(hw, struct rt5682_priv, 2817 dai_clks_hw[RT5682_DAI_BCLK_IDX]); 2818 struct snd_soc_component *component; 2819 struct snd_soc_dai *dai; 2820 unsigned long factor; 2821 2822 if (!rt5682_clk_check(rt5682)) 2823 return -EINVAL; 2824 2825 component = rt5682->component; 2826 2827 factor = rt5682_bclk_get_factor(rate, parent_rate); 2828 2829 for_each_component_dais(component, dai) 2830 if (dai->id == RT5682_AIF1) 2831 break; 2832 if (!dai) { 2833 dev_err(rt5682->i2c_dev, "dai %d not found in component\n", 2834 RT5682_AIF1); 2835 return -ENODEV; 2836 } 2837 2838 return rt5682_set_bclk1_ratio(dai, factor); 2839 } 2840 2841 static const struct clk_ops rt5682_dai_clk_ops[RT5682_DAI_NUM_CLKS] = { 2842 [RT5682_DAI_WCLK_IDX] = { 2843 .prepare = rt5682_wclk_prepare, 2844 .unprepare = rt5682_wclk_unprepare, 2845 .recalc_rate = rt5682_wclk_recalc_rate, 2846 .round_rate = rt5682_wclk_round_rate, 2847 .set_rate = rt5682_wclk_set_rate, 2848 }, 2849 [RT5682_DAI_BCLK_IDX] = { 2850 .recalc_rate = rt5682_bclk_recalc_rate, 2851 .round_rate = rt5682_bclk_round_rate, 2852 .set_rate = rt5682_bclk_set_rate, 2853 }, 2854 }; 2855 2856 int rt5682_register_dai_clks(struct rt5682_priv *rt5682) 2857 { 2858 struct device *dev = rt5682->i2c_dev; 2859 struct rt5682_platform_data *pdata = &rt5682->pdata; 2860 struct clk_hw *dai_clk_hw; 2861 int i, ret; 2862 2863 for (i = 0; i < RT5682_DAI_NUM_CLKS; ++i) { 2864 struct clk_init_data init = { }; 2865 const struct clk_hw *parent; 2866 2867 dai_clk_hw = &rt5682->dai_clks_hw[i]; 2868 2869 switch (i) { 2870 case RT5682_DAI_WCLK_IDX: 2871 /* Make MCLK the parent of WCLK */ 2872 if (rt5682->mclk) { 2873 parent = __clk_get_hw(rt5682->mclk); 2874 init.parent_hws = &parent; 2875 init.num_parents = 1; 2876 } 2877 break; 2878 case RT5682_DAI_BCLK_IDX: 2879 /* Make WCLK the parent of BCLK */ 2880 parent = &rt5682->dai_clks_hw[RT5682_DAI_WCLK_IDX]; 2881 init.parent_hws = &parent; 2882 init.num_parents = 1; 2883 break; 2884 default: 2885 dev_err(dev, "Invalid clock index\n"); 2886 return -EINVAL; 2887 } 2888 2889 init.name = pdata->dai_clk_names[i]; 2890 init.ops = &rt5682_dai_clk_ops[i]; 2891 init.flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_GATE; 2892 dai_clk_hw->init = &init; 2893 2894 ret = devm_clk_hw_register(dev, dai_clk_hw); 2895 if (ret) { 2896 dev_warn(dev, "Failed to register %s: %d\n", 2897 init.name, ret); 2898 return ret; 2899 } 2900 2901 if (dev->of_node) { 2902 devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, 2903 dai_clk_hw); 2904 } else { 2905 ret = devm_clk_hw_register_clkdev(dev, dai_clk_hw, 2906 init.name, 2907 dev_name(dev)); 2908 if (ret) 2909 return ret; 2910 } 2911 } 2912 2913 return 0; 2914 } 2915 EXPORT_SYMBOL_GPL(rt5682_register_dai_clks); 2916 #endif /* CONFIG_COMMON_CLK */ 2917 2918 static int rt5682_probe(struct snd_soc_component *component) 2919 { 2920 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 2921 struct sdw_slave *slave; 2922 unsigned long time; 2923 struct snd_soc_dapm_context *dapm = &component->dapm; 2924 2925 rt5682->component = component; 2926 2927 if (rt5682->is_sdw) { 2928 slave = rt5682->slave; 2929 time = wait_for_completion_timeout( 2930 &slave->initialization_complete, 2931 msecs_to_jiffies(RT5682_PROBE_TIMEOUT)); 2932 if (!time) { 2933 dev_err(&slave->dev, "Initialization not complete, timed out\n"); 2934 return -ETIMEDOUT; 2935 } 2936 } 2937 2938 snd_soc_dapm_disable_pin(dapm, "MICBIAS"); 2939 snd_soc_dapm_disable_pin(dapm, "Vref2"); 2940 snd_soc_dapm_sync(dapm); 2941 return 0; 2942 } 2943 2944 static void rt5682_remove(struct snd_soc_component *component) 2945 { 2946 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 2947 2948 rt5682_reset(rt5682); 2949 } 2950 2951 #ifdef CONFIG_PM 2952 static int rt5682_suspend(struct snd_soc_component *component) 2953 { 2954 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 2955 unsigned int val; 2956 2957 if (rt5682->is_sdw) 2958 return 0; 2959 2960 cancel_delayed_work_sync(&rt5682->jack_detect_work); 2961 cancel_delayed_work_sync(&rt5682->jd_check_work); 2962 if (rt5682->hs_jack && (rt5682->jack_type & SND_JACK_HEADSET) == SND_JACK_HEADSET) { 2963 val = snd_soc_component_read(component, 2964 RT5682_CBJ_CTRL_2) & RT5682_JACK_TYPE_MASK; 2965 2966 switch (val) { 2967 case 0x1: 2968 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1, 2969 RT5682_SAR_SEL_MB1_MASK | RT5682_SAR_SEL_MB2_MASK, 2970 RT5682_SAR_SEL_MB1_NOSEL | RT5682_SAR_SEL_MB2_SEL); 2971 break; 2972 case 0x2: 2973 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1, 2974 RT5682_SAR_SEL_MB1_MASK | RT5682_SAR_SEL_MB2_MASK, 2975 RT5682_SAR_SEL_MB1_SEL | RT5682_SAR_SEL_MB2_NOSEL); 2976 break; 2977 default: 2978 break; 2979 } 2980 2981 /* enter SAR ADC power saving mode */ 2982 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1, 2983 RT5682_SAR_BUTT_DET_MASK | RT5682_SAR_BUTDET_MODE_MASK | 2984 RT5682_SAR_SEL_MB1_MB2_MASK, 0); 2985 usleep_range(5000, 6000); 2986 snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1, 2987 RT5682_MB1_PATH_MASK | RT5682_MB2_PATH_MASK, 2988 RT5682_CTRL_MB1_REG | RT5682_CTRL_MB2_REG); 2989 usleep_range(10000, 12000); 2990 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1, 2991 RT5682_SAR_BUTT_DET_MASK | RT5682_SAR_BUTDET_MODE_MASK, 2992 RT5682_SAR_BUTT_DET_EN | RT5682_SAR_BUTDET_POW_SAV); 2993 snd_soc_component_update_bits(component, RT5682_HP_CHARGE_PUMP_1, 2994 RT5682_OSW_L_MASK | RT5682_OSW_R_MASK, 0); 2995 } 2996 2997 regcache_cache_only(rt5682->regmap, true); 2998 regcache_mark_dirty(rt5682->regmap); 2999 return 0; 3000 } 3001 3002 static int rt5682_resume(struct snd_soc_component *component) 3003 { 3004 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 3005 3006 if (rt5682->is_sdw) 3007 return 0; 3008 3009 regcache_cache_only(rt5682->regmap, false); 3010 regcache_sync(rt5682->regmap); 3011 3012 if (rt5682->hs_jack && (rt5682->jack_type & SND_JACK_HEADSET) == SND_JACK_HEADSET) { 3013 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1, 3014 RT5682_SAR_BUTDET_MODE_MASK | RT5682_SAR_SEL_MB1_MB2_MASK, 3015 RT5682_SAR_BUTDET_POW_NORM | RT5682_SAR_SEL_MB1_MB2_AUTO); 3016 usleep_range(5000, 6000); 3017 snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1, 3018 RT5682_MB1_PATH_MASK | RT5682_MB2_PATH_MASK, 3019 RT5682_CTRL_MB1_FSM | RT5682_CTRL_MB2_FSM); 3020 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_3, 3021 RT5682_PWR_CBJ, RT5682_PWR_CBJ); 3022 } 3023 3024 rt5682->jack_type = 0; 3025 mod_delayed_work(system_power_efficient_wq, 3026 &rt5682->jack_detect_work, msecs_to_jiffies(0)); 3027 3028 return 0; 3029 } 3030 #else 3031 #define rt5682_suspend NULL 3032 #define rt5682_resume NULL 3033 #endif 3034 3035 const struct snd_soc_dai_ops rt5682_aif1_dai_ops = { 3036 .hw_params = rt5682_hw_params, 3037 .set_fmt = rt5682_set_dai_fmt, 3038 .set_tdm_slot = rt5682_set_tdm_slot, 3039 .set_bclk_ratio = rt5682_set_bclk1_ratio, 3040 }; 3041 EXPORT_SYMBOL_GPL(rt5682_aif1_dai_ops); 3042 3043 const struct snd_soc_dai_ops rt5682_aif2_dai_ops = { 3044 .hw_params = rt5682_hw_params, 3045 .set_fmt = rt5682_set_dai_fmt, 3046 .set_bclk_ratio = rt5682_set_bclk2_ratio, 3047 }; 3048 EXPORT_SYMBOL_GPL(rt5682_aif2_dai_ops); 3049 3050 const struct snd_soc_component_driver rt5682_soc_component_dev = { 3051 .probe = rt5682_probe, 3052 .remove = rt5682_remove, 3053 .suspend = rt5682_suspend, 3054 .resume = rt5682_resume, 3055 .set_bias_level = rt5682_set_bias_level, 3056 .controls = rt5682_snd_controls, 3057 .num_controls = ARRAY_SIZE(rt5682_snd_controls), 3058 .dapm_widgets = rt5682_dapm_widgets, 3059 .num_dapm_widgets = ARRAY_SIZE(rt5682_dapm_widgets), 3060 .dapm_routes = rt5682_dapm_routes, 3061 .num_dapm_routes = ARRAY_SIZE(rt5682_dapm_routes), 3062 .set_sysclk = rt5682_set_component_sysclk, 3063 .set_pll = rt5682_set_component_pll, 3064 .set_jack = rt5682_set_jack_detect, 3065 .use_pmdown_time = 1, 3066 .endianness = 1, 3067 .non_legacy_dai_naming = 1, 3068 }; 3069 EXPORT_SYMBOL_GPL(rt5682_soc_component_dev); 3070 3071 int rt5682_parse_dt(struct rt5682_priv *rt5682, struct device *dev) 3072 { 3073 3074 device_property_read_u32(dev, "realtek,dmic1-data-pin", 3075 &rt5682->pdata.dmic1_data_pin); 3076 device_property_read_u32(dev, "realtek,dmic1-clk-pin", 3077 &rt5682->pdata.dmic1_clk_pin); 3078 device_property_read_u32(dev, "realtek,jd-src", 3079 &rt5682->pdata.jd_src); 3080 device_property_read_u32(dev, "realtek,btndet-delay", 3081 &rt5682->pdata.btndet_delay); 3082 device_property_read_u32(dev, "realtek,dmic-clk-rate-hz", 3083 &rt5682->pdata.dmic_clk_rate); 3084 device_property_read_u32(dev, "realtek,dmic-delay-ms", 3085 &rt5682->pdata.dmic_delay); 3086 3087 rt5682->pdata.ldo1_en = of_get_named_gpio(dev->of_node, 3088 "realtek,ldo1-en-gpios", 0); 3089 3090 if (device_property_read_string_array(dev, "clock-output-names", 3091 rt5682->pdata.dai_clk_names, 3092 RT5682_DAI_NUM_CLKS) < 0) 3093 dev_warn(dev, "Using default DAI clk names: %s, %s\n", 3094 rt5682->pdata.dai_clk_names[RT5682_DAI_WCLK_IDX], 3095 rt5682->pdata.dai_clk_names[RT5682_DAI_BCLK_IDX]); 3096 3097 rt5682->pdata.dmic_clk_driving_high = device_property_read_bool(dev, 3098 "realtek,dmic-clk-driving-high"); 3099 3100 return 0; 3101 } 3102 EXPORT_SYMBOL_GPL(rt5682_parse_dt); 3103 3104 void rt5682_calibrate(struct rt5682_priv *rt5682) 3105 { 3106 int value, count; 3107 3108 mutex_lock(&rt5682->calibrate_mutex); 3109 3110 rt5682_reset(rt5682); 3111 regmap_write(rt5682->regmap, RT5682_I2C_CTRL, 0x000f); 3112 regmap_write(rt5682->regmap, RT5682_PWR_ANLG_1, 0xa2af); 3113 usleep_range(15000, 20000); 3114 regmap_write(rt5682->regmap, RT5682_PWR_ANLG_1, 0xf2af); 3115 regmap_write(rt5682->regmap, RT5682_MICBIAS_2, 0x0300); 3116 regmap_write(rt5682->regmap, RT5682_GLB_CLK, 0x8000); 3117 regmap_write(rt5682->regmap, RT5682_PWR_DIG_1, 0x0100); 3118 regmap_write(rt5682->regmap, RT5682_HP_IMP_SENS_CTRL_19, 0x3800); 3119 regmap_write(rt5682->regmap, RT5682_CHOP_DAC, 0x3000); 3120 regmap_write(rt5682->regmap, RT5682_CALIB_ADC_CTRL, 0x7005); 3121 regmap_write(rt5682->regmap, RT5682_STO1_ADC_MIXER, 0x686c); 3122 regmap_write(rt5682->regmap, RT5682_CAL_REC, 0x0d0d); 3123 regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_2, 0x0321); 3124 regmap_write(rt5682->regmap, RT5682_HP_LOGIC_CTRL_2, 0x0004); 3125 regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_1, 0x7c00); 3126 regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_3, 0x06a1); 3127 regmap_write(rt5682->regmap, RT5682_A_DAC1_MUX, 0x0311); 3128 regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_1, 0x7c00); 3129 3130 regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_1, 0xfc00); 3131 3132 for (count = 0; count < 60; count++) { 3133 regmap_read(rt5682->regmap, RT5682_HP_CALIB_STA_1, &value); 3134 if (!(value & 0x8000)) 3135 break; 3136 3137 usleep_range(10000, 10005); 3138 } 3139 3140 if (count >= 60) 3141 dev_err(rt5682->component->dev, "HP Calibration Failure\n"); 3142 3143 /* restore settings */ 3144 regmap_write(rt5682->regmap, RT5682_PWR_ANLG_1, 0x002f); 3145 regmap_write(rt5682->regmap, RT5682_MICBIAS_2, 0x0080); 3146 regmap_write(rt5682->regmap, RT5682_GLB_CLK, 0x0000); 3147 regmap_write(rt5682->regmap, RT5682_PWR_DIG_1, 0x0000); 3148 regmap_write(rt5682->regmap, RT5682_CHOP_DAC, 0x2000); 3149 regmap_write(rt5682->regmap, RT5682_CALIB_ADC_CTRL, 0x2005); 3150 regmap_write(rt5682->regmap, RT5682_STO1_ADC_MIXER, 0xc0c4); 3151 regmap_write(rt5682->regmap, RT5682_CAL_REC, 0x0c0c); 3152 3153 mutex_unlock(&rt5682->calibrate_mutex); 3154 } 3155 EXPORT_SYMBOL_GPL(rt5682_calibrate); 3156 3157 MODULE_DESCRIPTION("ASoC RT5682 driver"); 3158 MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>"); 3159 MODULE_LICENSE("GPL v2"); 3160