1 /* 2 * rt5682.c -- RT5682 ALSA SoC audio component driver 3 * 4 * Copyright 2018 Realtek Semiconductor Corp. 5 * Author: Bard Liao <bardliao@realtek.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11 12 #include <linux/module.h> 13 #include <linux/moduleparam.h> 14 #include <linux/init.h> 15 #include <linux/delay.h> 16 #include <linux/pm.h> 17 #include <linux/i2c.h> 18 #include <linux/platform_device.h> 19 #include <linux/spi/spi.h> 20 #include <linux/acpi.h> 21 #include <linux/gpio.h> 22 #include <linux/of_gpio.h> 23 #include <linux/regulator/consumer.h> 24 #include <linux/mutex.h> 25 #include <sound/core.h> 26 #include <sound/pcm.h> 27 #include <sound/pcm_params.h> 28 #include <sound/jack.h> 29 #include <sound/soc.h> 30 #include <sound/soc-dapm.h> 31 #include <sound/initval.h> 32 #include <sound/tlv.h> 33 #include <sound/rt5682.h> 34 35 #include "rl6231.h" 36 #include "rt5682.h" 37 38 #define RT5682_NUM_SUPPLIES 3 39 40 static const char *rt5682_supply_names[RT5682_NUM_SUPPLIES] = { 41 "AVDD", 42 "MICVDD", 43 "VBAT", 44 }; 45 46 static const struct rt5682_platform_data i2s_default_platform_data = { 47 .dmic1_data_pin = RT5682_DMIC1_DATA_GPIO2, 48 .dmic1_clk_pin = RT5682_DMIC1_CLK_GPIO3, 49 .jd_src = RT5682_JD1, 50 }; 51 52 struct rt5682_priv { 53 struct snd_soc_component *component; 54 struct rt5682_platform_data pdata; 55 struct regmap *regmap; 56 struct snd_soc_jack *hs_jack; 57 struct regulator_bulk_data supplies[RT5682_NUM_SUPPLIES]; 58 struct delayed_work jack_detect_work; 59 struct delayed_work jd_check_work; 60 struct mutex calibrate_mutex; 61 62 int sysclk; 63 int sysclk_src; 64 int lrck[RT5682_AIFS]; 65 int bclk[RT5682_AIFS]; 66 int master[RT5682_AIFS]; 67 68 int pll_src; 69 int pll_in; 70 int pll_out; 71 72 int jack_type; 73 }; 74 75 static const struct reg_sequence patch_list[] = { 76 {RT5682_HP_IMP_SENS_CTRL_19, 0x1000}, 77 {RT5682_DAC_ADC_DIG_VOL1, 0xa020}, 78 }; 79 80 static const struct reg_default rt5682_reg[] = { 81 {0x0002, 0x8080}, 82 {0x0003, 0x8000}, 83 {0x0005, 0x0000}, 84 {0x0006, 0x0000}, 85 {0x0008, 0x800f}, 86 {0x000b, 0x0000}, 87 {0x0010, 0x4040}, 88 {0x0011, 0x0000}, 89 {0x0012, 0x1404}, 90 {0x0013, 0x1000}, 91 {0x0014, 0xa00a}, 92 {0x0015, 0x0404}, 93 {0x0016, 0x0404}, 94 {0x0019, 0xafaf}, 95 {0x001c, 0x2f2f}, 96 {0x001f, 0x0000}, 97 {0x0022, 0x5757}, 98 {0x0023, 0x0039}, 99 {0x0024, 0x000b}, 100 {0x0026, 0xc0c4}, 101 {0x0029, 0x8080}, 102 {0x002a, 0xa0a0}, 103 {0x002b, 0x0300}, 104 {0x0030, 0x0000}, 105 {0x003c, 0x0080}, 106 {0x0044, 0x0c0c}, 107 {0x0049, 0x0000}, 108 {0x0061, 0x0000}, 109 {0x0062, 0x0000}, 110 {0x0063, 0x003f}, 111 {0x0064, 0x0000}, 112 {0x0065, 0x0000}, 113 {0x0066, 0x0030}, 114 {0x0067, 0x0000}, 115 {0x006b, 0x0000}, 116 {0x006c, 0x0000}, 117 {0x006d, 0x2200}, 118 {0x006e, 0x0a10}, 119 {0x0070, 0x8000}, 120 {0x0071, 0x8000}, 121 {0x0073, 0x0000}, 122 {0x0074, 0x0000}, 123 {0x0075, 0x0002}, 124 {0x0076, 0x0001}, 125 {0x0079, 0x0000}, 126 {0x007a, 0x0000}, 127 {0x007b, 0x0000}, 128 {0x007c, 0x0100}, 129 {0x007e, 0x0000}, 130 {0x0080, 0x0000}, 131 {0x0081, 0x0000}, 132 {0x0082, 0x0000}, 133 {0x0083, 0x0000}, 134 {0x0084, 0x0000}, 135 {0x0085, 0x0000}, 136 {0x0086, 0x0005}, 137 {0x0087, 0x0000}, 138 {0x0088, 0x0000}, 139 {0x008c, 0x0003}, 140 {0x008d, 0x0000}, 141 {0x008e, 0x0060}, 142 {0x008f, 0x1000}, 143 {0x0091, 0x0c26}, 144 {0x0092, 0x0073}, 145 {0x0093, 0x0000}, 146 {0x0094, 0x0080}, 147 {0x0098, 0x0000}, 148 {0x009a, 0x0000}, 149 {0x009b, 0x0000}, 150 {0x009c, 0x0000}, 151 {0x009d, 0x0000}, 152 {0x009e, 0x100c}, 153 {0x009f, 0x0000}, 154 {0x00a0, 0x0000}, 155 {0x00a3, 0x0002}, 156 {0x00a4, 0x0001}, 157 {0x00ae, 0x2040}, 158 {0x00af, 0x0000}, 159 {0x00b6, 0x0000}, 160 {0x00b7, 0x0000}, 161 {0x00b8, 0x0000}, 162 {0x00b9, 0x0002}, 163 {0x00be, 0x0000}, 164 {0x00c0, 0x0160}, 165 {0x00c1, 0x82a0}, 166 {0x00c2, 0x0000}, 167 {0x00d0, 0x0000}, 168 {0x00d1, 0x2244}, 169 {0x00d2, 0x3300}, 170 {0x00d3, 0x2200}, 171 {0x00d4, 0x0000}, 172 {0x00d9, 0x0009}, 173 {0x00da, 0x0000}, 174 {0x00db, 0x0000}, 175 {0x00dc, 0x00c0}, 176 {0x00dd, 0x2220}, 177 {0x00de, 0x3131}, 178 {0x00df, 0x3131}, 179 {0x00e0, 0x3131}, 180 {0x00e2, 0x0000}, 181 {0x00e3, 0x4000}, 182 {0x00e4, 0x0aa0}, 183 {0x00e5, 0x3131}, 184 {0x00e6, 0x3131}, 185 {0x00e7, 0x3131}, 186 {0x00e8, 0x3131}, 187 {0x00ea, 0xb320}, 188 {0x00eb, 0x0000}, 189 {0x00f0, 0x0000}, 190 {0x00f1, 0x00d0}, 191 {0x00f2, 0x00d0}, 192 {0x00f6, 0x0000}, 193 {0x00fa, 0x0000}, 194 {0x00fb, 0x0000}, 195 {0x00fc, 0x0000}, 196 {0x00fd, 0x0000}, 197 {0x00fe, 0x10ec}, 198 {0x00ff, 0x6530}, 199 {0x0100, 0xa0a0}, 200 {0x010b, 0x0000}, 201 {0x010c, 0xae00}, 202 {0x010d, 0xaaa0}, 203 {0x010e, 0x8aa2}, 204 {0x010f, 0x02a2}, 205 {0x0110, 0xc000}, 206 {0x0111, 0x04a2}, 207 {0x0112, 0x2800}, 208 {0x0113, 0x0000}, 209 {0x0117, 0x0100}, 210 {0x0125, 0x0410}, 211 {0x0132, 0x6026}, 212 {0x0136, 0x5555}, 213 {0x0138, 0x3700}, 214 {0x013a, 0x2000}, 215 {0x013b, 0x2000}, 216 {0x013c, 0x2005}, 217 {0x013f, 0x0000}, 218 {0x0142, 0x0000}, 219 {0x0145, 0x0002}, 220 {0x0146, 0x0000}, 221 {0x0147, 0x0000}, 222 {0x0148, 0x0000}, 223 {0x0149, 0x0000}, 224 {0x0150, 0x79a1}, 225 {0x0151, 0x0000}, 226 {0x0160, 0x4ec0}, 227 {0x0161, 0x0080}, 228 {0x0162, 0x0200}, 229 {0x0163, 0x0800}, 230 {0x0164, 0x0000}, 231 {0x0165, 0x0000}, 232 {0x0166, 0x0000}, 233 {0x0167, 0x000f}, 234 {0x0168, 0x000f}, 235 {0x0169, 0x0021}, 236 {0x0190, 0x413d}, 237 {0x0194, 0x0000}, 238 {0x0195, 0x0000}, 239 {0x0197, 0x0022}, 240 {0x0198, 0x0000}, 241 {0x0199, 0x0000}, 242 {0x01af, 0x0000}, 243 {0x01b0, 0x0400}, 244 {0x01b1, 0x0000}, 245 {0x01b2, 0x0000}, 246 {0x01b3, 0x0000}, 247 {0x01b4, 0x0000}, 248 {0x01b5, 0x0000}, 249 {0x01b6, 0x01c3}, 250 {0x01b7, 0x02a0}, 251 {0x01b8, 0x03e9}, 252 {0x01b9, 0x1389}, 253 {0x01ba, 0xc351}, 254 {0x01bb, 0x0009}, 255 {0x01bc, 0x0018}, 256 {0x01bd, 0x002a}, 257 {0x01be, 0x004c}, 258 {0x01bf, 0x0097}, 259 {0x01c0, 0x433d}, 260 {0x01c2, 0x0000}, 261 {0x01c3, 0x0000}, 262 {0x01c4, 0x0000}, 263 {0x01c5, 0x0000}, 264 {0x01c6, 0x0000}, 265 {0x01c7, 0x0000}, 266 {0x01c8, 0x40af}, 267 {0x01c9, 0x0702}, 268 {0x01ca, 0x0000}, 269 {0x01cb, 0x0000}, 270 {0x01cc, 0x5757}, 271 {0x01cd, 0x5757}, 272 {0x01ce, 0x5757}, 273 {0x01cf, 0x5757}, 274 {0x01d0, 0x5757}, 275 {0x01d1, 0x5757}, 276 {0x01d2, 0x5757}, 277 {0x01d3, 0x5757}, 278 {0x01d4, 0x5757}, 279 {0x01d5, 0x5757}, 280 {0x01d6, 0x0000}, 281 {0x01d7, 0x0008}, 282 {0x01d8, 0x0029}, 283 {0x01d9, 0x3333}, 284 {0x01da, 0x0000}, 285 {0x01db, 0x0004}, 286 {0x01dc, 0x0000}, 287 {0x01de, 0x7c00}, 288 {0x01df, 0x0320}, 289 {0x01e0, 0x06a1}, 290 {0x01e1, 0x0000}, 291 {0x01e2, 0x0000}, 292 {0x01e3, 0x0000}, 293 {0x01e4, 0x0000}, 294 {0x01e6, 0x0001}, 295 {0x01e7, 0x0000}, 296 {0x01e8, 0x0000}, 297 {0x01ea, 0x0000}, 298 {0x01eb, 0x0000}, 299 {0x01ec, 0x0000}, 300 {0x01ed, 0x0000}, 301 {0x01ee, 0x0000}, 302 {0x01ef, 0x0000}, 303 {0x01f0, 0x0000}, 304 {0x01f1, 0x0000}, 305 {0x01f2, 0x0000}, 306 {0x01f3, 0x0000}, 307 {0x01f4, 0x0000}, 308 {0x0210, 0x6297}, 309 {0x0211, 0xa005}, 310 {0x0212, 0x824c}, 311 {0x0213, 0xf7ff}, 312 {0x0214, 0xf24c}, 313 {0x0215, 0x0102}, 314 {0x0216, 0x00a3}, 315 {0x0217, 0x0048}, 316 {0x0218, 0xa2c0}, 317 {0x0219, 0x0400}, 318 {0x021a, 0x00c8}, 319 {0x021b, 0x00c0}, 320 {0x021c, 0x0000}, 321 {0x0250, 0x4500}, 322 {0x0251, 0x40b3}, 323 {0x0252, 0x0000}, 324 {0x0253, 0x0000}, 325 {0x0254, 0x0000}, 326 {0x0255, 0x0000}, 327 {0x0256, 0x0000}, 328 {0x0257, 0x0000}, 329 {0x0258, 0x0000}, 330 {0x0259, 0x0000}, 331 {0x025a, 0x0005}, 332 {0x0270, 0x0000}, 333 {0x02ff, 0x0110}, 334 {0x0300, 0x001f}, 335 {0x0301, 0x032c}, 336 {0x0302, 0x5f21}, 337 {0x0303, 0x4000}, 338 {0x0304, 0x4000}, 339 {0x0305, 0x06d5}, 340 {0x0306, 0x8000}, 341 {0x0307, 0x0700}, 342 {0x0310, 0x4560}, 343 {0x0311, 0xa4a8}, 344 {0x0312, 0x7418}, 345 {0x0313, 0x0000}, 346 {0x0314, 0x0006}, 347 {0x0315, 0xffff}, 348 {0x0316, 0xc400}, 349 {0x0317, 0x0000}, 350 {0x03c0, 0x7e00}, 351 {0x03c1, 0x8000}, 352 {0x03c2, 0x8000}, 353 {0x03c3, 0x8000}, 354 {0x03c4, 0x8000}, 355 {0x03c5, 0x8000}, 356 {0x03c6, 0x8000}, 357 {0x03c7, 0x8000}, 358 {0x03c8, 0x8000}, 359 {0x03c9, 0x8000}, 360 {0x03ca, 0x8000}, 361 {0x03cb, 0x8000}, 362 {0x03cc, 0x8000}, 363 {0x03d0, 0x0000}, 364 {0x03d1, 0x0000}, 365 {0x03d2, 0x0000}, 366 {0x03d3, 0x0000}, 367 {0x03d4, 0x2000}, 368 {0x03d5, 0x2000}, 369 {0x03d6, 0x0000}, 370 {0x03d7, 0x0000}, 371 {0x03d8, 0x2000}, 372 {0x03d9, 0x2000}, 373 {0x03da, 0x2000}, 374 {0x03db, 0x2000}, 375 {0x03dc, 0x0000}, 376 {0x03dd, 0x0000}, 377 {0x03de, 0x0000}, 378 {0x03df, 0x2000}, 379 {0x03e0, 0x0000}, 380 {0x03e1, 0x0000}, 381 {0x03e2, 0x0000}, 382 {0x03e3, 0x0000}, 383 {0x03e4, 0x0000}, 384 {0x03e5, 0x0000}, 385 {0x03e6, 0x0000}, 386 {0x03e7, 0x0000}, 387 {0x03e8, 0x0000}, 388 {0x03e9, 0x0000}, 389 {0x03ea, 0x0000}, 390 {0x03eb, 0x0000}, 391 {0x03ec, 0x0000}, 392 {0x03ed, 0x0000}, 393 {0x03ee, 0x0000}, 394 {0x03ef, 0x0000}, 395 {0x03f0, 0x0800}, 396 {0x03f1, 0x0800}, 397 {0x03f2, 0x0800}, 398 {0x03f3, 0x0800}, 399 }; 400 401 static bool rt5682_volatile_register(struct device *dev, unsigned int reg) 402 { 403 switch (reg) { 404 case RT5682_RESET: 405 case RT5682_CBJ_CTRL_2: 406 case RT5682_INT_ST_1: 407 case RT5682_4BTN_IL_CMD_1: 408 case RT5682_AJD1_CTRL: 409 case RT5682_HP_CALIB_CTRL_1: 410 case RT5682_DEVICE_ID: 411 case RT5682_I2C_MODE: 412 case RT5682_HP_CALIB_CTRL_10: 413 case RT5682_EFUSE_CTRL_2: 414 case RT5682_JD_TOP_VC_VTRL: 415 case RT5682_HP_IMP_SENS_CTRL_19: 416 case RT5682_IL_CMD_1: 417 case RT5682_SAR_IL_CMD_2: 418 case RT5682_SAR_IL_CMD_4: 419 case RT5682_SAR_IL_CMD_10: 420 case RT5682_SAR_IL_CMD_11: 421 case RT5682_EFUSE_CTRL_6...RT5682_EFUSE_CTRL_11: 422 case RT5682_HP_CALIB_STA_1...RT5682_HP_CALIB_STA_11: 423 return true; 424 default: 425 return false; 426 } 427 } 428 429 static bool rt5682_readable_register(struct device *dev, unsigned int reg) 430 { 431 switch (reg) { 432 case RT5682_RESET: 433 case RT5682_VERSION_ID: 434 case RT5682_VENDOR_ID: 435 case RT5682_DEVICE_ID: 436 case RT5682_HP_CTRL_1: 437 case RT5682_HP_CTRL_2: 438 case RT5682_HPL_GAIN: 439 case RT5682_HPR_GAIN: 440 case RT5682_I2C_CTRL: 441 case RT5682_CBJ_BST_CTRL: 442 case RT5682_CBJ_CTRL_1: 443 case RT5682_CBJ_CTRL_2: 444 case RT5682_CBJ_CTRL_3: 445 case RT5682_CBJ_CTRL_4: 446 case RT5682_CBJ_CTRL_5: 447 case RT5682_CBJ_CTRL_6: 448 case RT5682_CBJ_CTRL_7: 449 case RT5682_DAC1_DIG_VOL: 450 case RT5682_STO1_ADC_DIG_VOL: 451 case RT5682_STO1_ADC_BOOST: 452 case RT5682_HP_IMP_GAIN_1: 453 case RT5682_HP_IMP_GAIN_2: 454 case RT5682_SIDETONE_CTRL: 455 case RT5682_STO1_ADC_MIXER: 456 case RT5682_AD_DA_MIXER: 457 case RT5682_STO1_DAC_MIXER: 458 case RT5682_A_DAC1_MUX: 459 case RT5682_DIG_INF2_DATA: 460 case RT5682_REC_MIXER: 461 case RT5682_CAL_REC: 462 case RT5682_ALC_BACK_GAIN: 463 case RT5682_PWR_DIG_1: 464 case RT5682_PWR_DIG_2: 465 case RT5682_PWR_ANLG_1: 466 case RT5682_PWR_ANLG_2: 467 case RT5682_PWR_ANLG_3: 468 case RT5682_PWR_MIXER: 469 case RT5682_PWR_VOL: 470 case RT5682_CLK_DET: 471 case RT5682_RESET_LPF_CTRL: 472 case RT5682_RESET_HPF_CTRL: 473 case RT5682_DMIC_CTRL_1: 474 case RT5682_I2S1_SDP: 475 case RT5682_I2S2_SDP: 476 case RT5682_ADDA_CLK_1: 477 case RT5682_ADDA_CLK_2: 478 case RT5682_I2S1_F_DIV_CTRL_1: 479 case RT5682_I2S1_F_DIV_CTRL_2: 480 case RT5682_TDM_CTRL: 481 case RT5682_TDM_ADDA_CTRL_1: 482 case RT5682_TDM_ADDA_CTRL_2: 483 case RT5682_DATA_SEL_CTRL_1: 484 case RT5682_TDM_TCON_CTRL: 485 case RT5682_GLB_CLK: 486 case RT5682_PLL_CTRL_1: 487 case RT5682_PLL_CTRL_2: 488 case RT5682_PLL_TRACK_1: 489 case RT5682_PLL_TRACK_2: 490 case RT5682_PLL_TRACK_3: 491 case RT5682_PLL_TRACK_4: 492 case RT5682_PLL_TRACK_5: 493 case RT5682_PLL_TRACK_6: 494 case RT5682_PLL_TRACK_11: 495 case RT5682_SDW_REF_CLK: 496 case RT5682_DEPOP_1: 497 case RT5682_DEPOP_2: 498 case RT5682_HP_CHARGE_PUMP_1: 499 case RT5682_HP_CHARGE_PUMP_2: 500 case RT5682_MICBIAS_1: 501 case RT5682_MICBIAS_2: 502 case RT5682_PLL_TRACK_12: 503 case RT5682_PLL_TRACK_14: 504 case RT5682_PLL2_CTRL_1: 505 case RT5682_PLL2_CTRL_2: 506 case RT5682_PLL2_CTRL_3: 507 case RT5682_PLL2_CTRL_4: 508 case RT5682_RC_CLK_CTRL: 509 case RT5682_I2S_M_CLK_CTRL_1: 510 case RT5682_I2S2_F_DIV_CTRL_1: 511 case RT5682_I2S2_F_DIV_CTRL_2: 512 case RT5682_EQ_CTRL_1: 513 case RT5682_EQ_CTRL_2: 514 case RT5682_IRQ_CTRL_1: 515 case RT5682_IRQ_CTRL_2: 516 case RT5682_IRQ_CTRL_3: 517 case RT5682_IRQ_CTRL_4: 518 case RT5682_INT_ST_1: 519 case RT5682_GPIO_CTRL_1: 520 case RT5682_GPIO_CTRL_2: 521 case RT5682_GPIO_CTRL_3: 522 case RT5682_HP_AMP_DET_CTRL_1: 523 case RT5682_HP_AMP_DET_CTRL_2: 524 case RT5682_MID_HP_AMP_DET: 525 case RT5682_LOW_HP_AMP_DET: 526 case RT5682_DELAY_BUF_CTRL: 527 case RT5682_SV_ZCD_1: 528 case RT5682_SV_ZCD_2: 529 case RT5682_IL_CMD_1: 530 case RT5682_IL_CMD_2: 531 case RT5682_IL_CMD_3: 532 case RT5682_IL_CMD_4: 533 case RT5682_IL_CMD_5: 534 case RT5682_IL_CMD_6: 535 case RT5682_4BTN_IL_CMD_1: 536 case RT5682_4BTN_IL_CMD_2: 537 case RT5682_4BTN_IL_CMD_3: 538 case RT5682_4BTN_IL_CMD_4: 539 case RT5682_4BTN_IL_CMD_5: 540 case RT5682_4BTN_IL_CMD_6: 541 case RT5682_4BTN_IL_CMD_7: 542 case RT5682_ADC_STO1_HP_CTRL_1: 543 case RT5682_ADC_STO1_HP_CTRL_2: 544 case RT5682_AJD1_CTRL: 545 case RT5682_JD1_THD: 546 case RT5682_JD2_THD: 547 case RT5682_JD_CTRL_1: 548 case RT5682_DUMMY_1: 549 case RT5682_DUMMY_2: 550 case RT5682_DUMMY_3: 551 case RT5682_DAC_ADC_DIG_VOL1: 552 case RT5682_BIAS_CUR_CTRL_2: 553 case RT5682_BIAS_CUR_CTRL_3: 554 case RT5682_BIAS_CUR_CTRL_4: 555 case RT5682_BIAS_CUR_CTRL_5: 556 case RT5682_BIAS_CUR_CTRL_6: 557 case RT5682_BIAS_CUR_CTRL_7: 558 case RT5682_BIAS_CUR_CTRL_8: 559 case RT5682_BIAS_CUR_CTRL_9: 560 case RT5682_BIAS_CUR_CTRL_10: 561 case RT5682_VREF_REC_OP_FB_CAP_CTRL: 562 case RT5682_CHARGE_PUMP_1: 563 case RT5682_DIG_IN_CTRL_1: 564 case RT5682_PAD_DRIVING_CTRL: 565 case RT5682_SOFT_RAMP_DEPOP: 566 case RT5682_CHOP_DAC: 567 case RT5682_CHOP_ADC: 568 case RT5682_CALIB_ADC_CTRL: 569 case RT5682_VOL_TEST: 570 case RT5682_SPKVDD_DET_STA: 571 case RT5682_TEST_MODE_CTRL_1: 572 case RT5682_TEST_MODE_CTRL_2: 573 case RT5682_TEST_MODE_CTRL_3: 574 case RT5682_TEST_MODE_CTRL_4: 575 case RT5682_TEST_MODE_CTRL_5: 576 case RT5682_PLL1_INTERNAL: 577 case RT5682_PLL2_INTERNAL: 578 case RT5682_STO_NG2_CTRL_1: 579 case RT5682_STO_NG2_CTRL_2: 580 case RT5682_STO_NG2_CTRL_3: 581 case RT5682_STO_NG2_CTRL_4: 582 case RT5682_STO_NG2_CTRL_5: 583 case RT5682_STO_NG2_CTRL_6: 584 case RT5682_STO_NG2_CTRL_7: 585 case RT5682_STO_NG2_CTRL_8: 586 case RT5682_STO_NG2_CTRL_9: 587 case RT5682_STO_NG2_CTRL_10: 588 case RT5682_STO1_DAC_SIL_DET: 589 case RT5682_SIL_PSV_CTRL1: 590 case RT5682_SIL_PSV_CTRL2: 591 case RT5682_SIL_PSV_CTRL3: 592 case RT5682_SIL_PSV_CTRL4: 593 case RT5682_SIL_PSV_CTRL5: 594 case RT5682_HP_IMP_SENS_CTRL_01: 595 case RT5682_HP_IMP_SENS_CTRL_02: 596 case RT5682_HP_IMP_SENS_CTRL_03: 597 case RT5682_HP_IMP_SENS_CTRL_04: 598 case RT5682_HP_IMP_SENS_CTRL_05: 599 case RT5682_HP_IMP_SENS_CTRL_06: 600 case RT5682_HP_IMP_SENS_CTRL_07: 601 case RT5682_HP_IMP_SENS_CTRL_08: 602 case RT5682_HP_IMP_SENS_CTRL_09: 603 case RT5682_HP_IMP_SENS_CTRL_10: 604 case RT5682_HP_IMP_SENS_CTRL_11: 605 case RT5682_HP_IMP_SENS_CTRL_12: 606 case RT5682_HP_IMP_SENS_CTRL_13: 607 case RT5682_HP_IMP_SENS_CTRL_14: 608 case RT5682_HP_IMP_SENS_CTRL_15: 609 case RT5682_HP_IMP_SENS_CTRL_16: 610 case RT5682_HP_IMP_SENS_CTRL_17: 611 case RT5682_HP_IMP_SENS_CTRL_18: 612 case RT5682_HP_IMP_SENS_CTRL_19: 613 case RT5682_HP_IMP_SENS_CTRL_20: 614 case RT5682_HP_IMP_SENS_CTRL_21: 615 case RT5682_HP_IMP_SENS_CTRL_22: 616 case RT5682_HP_IMP_SENS_CTRL_23: 617 case RT5682_HP_IMP_SENS_CTRL_24: 618 case RT5682_HP_IMP_SENS_CTRL_25: 619 case RT5682_HP_IMP_SENS_CTRL_26: 620 case RT5682_HP_IMP_SENS_CTRL_27: 621 case RT5682_HP_IMP_SENS_CTRL_28: 622 case RT5682_HP_IMP_SENS_CTRL_29: 623 case RT5682_HP_IMP_SENS_CTRL_30: 624 case RT5682_HP_IMP_SENS_CTRL_31: 625 case RT5682_HP_IMP_SENS_CTRL_32: 626 case RT5682_HP_IMP_SENS_CTRL_33: 627 case RT5682_HP_IMP_SENS_CTRL_34: 628 case RT5682_HP_IMP_SENS_CTRL_35: 629 case RT5682_HP_IMP_SENS_CTRL_36: 630 case RT5682_HP_IMP_SENS_CTRL_37: 631 case RT5682_HP_IMP_SENS_CTRL_38: 632 case RT5682_HP_IMP_SENS_CTRL_39: 633 case RT5682_HP_IMP_SENS_CTRL_40: 634 case RT5682_HP_IMP_SENS_CTRL_41: 635 case RT5682_HP_IMP_SENS_CTRL_42: 636 case RT5682_HP_IMP_SENS_CTRL_43: 637 case RT5682_HP_LOGIC_CTRL_1: 638 case RT5682_HP_LOGIC_CTRL_2: 639 case RT5682_HP_LOGIC_CTRL_3: 640 case RT5682_HP_CALIB_CTRL_1: 641 case RT5682_HP_CALIB_CTRL_2: 642 case RT5682_HP_CALIB_CTRL_3: 643 case RT5682_HP_CALIB_CTRL_4: 644 case RT5682_HP_CALIB_CTRL_5: 645 case RT5682_HP_CALIB_CTRL_6: 646 case RT5682_HP_CALIB_CTRL_7: 647 case RT5682_HP_CALIB_CTRL_9: 648 case RT5682_HP_CALIB_CTRL_10: 649 case RT5682_HP_CALIB_CTRL_11: 650 case RT5682_HP_CALIB_STA_1: 651 case RT5682_HP_CALIB_STA_2: 652 case RT5682_HP_CALIB_STA_3: 653 case RT5682_HP_CALIB_STA_4: 654 case RT5682_HP_CALIB_STA_5: 655 case RT5682_HP_CALIB_STA_6: 656 case RT5682_HP_CALIB_STA_7: 657 case RT5682_HP_CALIB_STA_8: 658 case RT5682_HP_CALIB_STA_9: 659 case RT5682_HP_CALIB_STA_10: 660 case RT5682_HP_CALIB_STA_11: 661 case RT5682_SAR_IL_CMD_1: 662 case RT5682_SAR_IL_CMD_2: 663 case RT5682_SAR_IL_CMD_3: 664 case RT5682_SAR_IL_CMD_4: 665 case RT5682_SAR_IL_CMD_5: 666 case RT5682_SAR_IL_CMD_6: 667 case RT5682_SAR_IL_CMD_7: 668 case RT5682_SAR_IL_CMD_8: 669 case RT5682_SAR_IL_CMD_9: 670 case RT5682_SAR_IL_CMD_10: 671 case RT5682_SAR_IL_CMD_11: 672 case RT5682_SAR_IL_CMD_12: 673 case RT5682_SAR_IL_CMD_13: 674 case RT5682_EFUSE_CTRL_1: 675 case RT5682_EFUSE_CTRL_2: 676 case RT5682_EFUSE_CTRL_3: 677 case RT5682_EFUSE_CTRL_4: 678 case RT5682_EFUSE_CTRL_5: 679 case RT5682_EFUSE_CTRL_6: 680 case RT5682_EFUSE_CTRL_7: 681 case RT5682_EFUSE_CTRL_8: 682 case RT5682_EFUSE_CTRL_9: 683 case RT5682_EFUSE_CTRL_10: 684 case RT5682_EFUSE_CTRL_11: 685 case RT5682_JD_TOP_VC_VTRL: 686 case RT5682_DRC1_CTRL_0: 687 case RT5682_DRC1_CTRL_1: 688 case RT5682_DRC1_CTRL_2: 689 case RT5682_DRC1_CTRL_3: 690 case RT5682_DRC1_CTRL_4: 691 case RT5682_DRC1_CTRL_5: 692 case RT5682_DRC1_CTRL_6: 693 case RT5682_DRC1_HARD_LMT_CTRL_1: 694 case RT5682_DRC1_HARD_LMT_CTRL_2: 695 case RT5682_DRC1_PRIV_1: 696 case RT5682_DRC1_PRIV_2: 697 case RT5682_DRC1_PRIV_3: 698 case RT5682_DRC1_PRIV_4: 699 case RT5682_DRC1_PRIV_5: 700 case RT5682_DRC1_PRIV_6: 701 case RT5682_DRC1_PRIV_7: 702 case RT5682_DRC1_PRIV_8: 703 case RT5682_EQ_AUTO_RCV_CTRL1: 704 case RT5682_EQ_AUTO_RCV_CTRL2: 705 case RT5682_EQ_AUTO_RCV_CTRL3: 706 case RT5682_EQ_AUTO_RCV_CTRL4: 707 case RT5682_EQ_AUTO_RCV_CTRL5: 708 case RT5682_EQ_AUTO_RCV_CTRL6: 709 case RT5682_EQ_AUTO_RCV_CTRL7: 710 case RT5682_EQ_AUTO_RCV_CTRL8: 711 case RT5682_EQ_AUTO_RCV_CTRL9: 712 case RT5682_EQ_AUTO_RCV_CTRL10: 713 case RT5682_EQ_AUTO_RCV_CTRL11: 714 case RT5682_EQ_AUTO_RCV_CTRL12: 715 case RT5682_EQ_AUTO_RCV_CTRL13: 716 case RT5682_ADC_L_EQ_LPF1_A1: 717 case RT5682_R_EQ_LPF1_A1: 718 case RT5682_L_EQ_LPF1_H0: 719 case RT5682_R_EQ_LPF1_H0: 720 case RT5682_L_EQ_BPF1_A1: 721 case RT5682_R_EQ_BPF1_A1: 722 case RT5682_L_EQ_BPF1_A2: 723 case RT5682_R_EQ_BPF1_A2: 724 case RT5682_L_EQ_BPF1_H0: 725 case RT5682_R_EQ_BPF1_H0: 726 case RT5682_L_EQ_BPF2_A1: 727 case RT5682_R_EQ_BPF2_A1: 728 case RT5682_L_EQ_BPF2_A2: 729 case RT5682_R_EQ_BPF2_A2: 730 case RT5682_L_EQ_BPF2_H0: 731 case RT5682_R_EQ_BPF2_H0: 732 case RT5682_L_EQ_BPF3_A1: 733 case RT5682_R_EQ_BPF3_A1: 734 case RT5682_L_EQ_BPF3_A2: 735 case RT5682_R_EQ_BPF3_A2: 736 case RT5682_L_EQ_BPF3_H0: 737 case RT5682_R_EQ_BPF3_H0: 738 case RT5682_L_EQ_BPF4_A1: 739 case RT5682_R_EQ_BPF4_A1: 740 case RT5682_L_EQ_BPF4_A2: 741 case RT5682_R_EQ_BPF4_A2: 742 case RT5682_L_EQ_BPF4_H0: 743 case RT5682_R_EQ_BPF4_H0: 744 case RT5682_L_EQ_HPF1_A1: 745 case RT5682_R_EQ_HPF1_A1: 746 case RT5682_L_EQ_HPF1_H0: 747 case RT5682_R_EQ_HPF1_H0: 748 case RT5682_L_EQ_PRE_VOL: 749 case RT5682_R_EQ_PRE_VOL: 750 case RT5682_L_EQ_POST_VOL: 751 case RT5682_R_EQ_POST_VOL: 752 case RT5682_I2C_MODE: 753 return true; 754 default: 755 return false; 756 } 757 } 758 759 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6525, 75, 0); 760 static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0); 761 static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0); 762 763 /* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */ 764 static const DECLARE_TLV_DB_RANGE(bst_tlv, 765 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0), 766 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0), 767 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0), 768 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0), 769 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0), 770 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0), 771 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0) 772 ); 773 774 /* Interface data select */ 775 static const char * const rt5682_data_select[] = { 776 "L/R", "R/L", "L/L", "R/R" 777 }; 778 779 static SOC_ENUM_SINGLE_DECL(rt5682_if2_adc_enum, 780 RT5682_DIG_INF2_DATA, RT5682_IF2_ADC_SEL_SFT, rt5682_data_select); 781 782 static SOC_ENUM_SINGLE_DECL(rt5682_if1_01_adc_enum, 783 RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC1_SEL_SFT, rt5682_data_select); 784 785 static SOC_ENUM_SINGLE_DECL(rt5682_if1_23_adc_enum, 786 RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC2_SEL_SFT, rt5682_data_select); 787 788 static SOC_ENUM_SINGLE_DECL(rt5682_if1_45_adc_enum, 789 RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC3_SEL_SFT, rt5682_data_select); 790 791 static SOC_ENUM_SINGLE_DECL(rt5682_if1_67_adc_enum, 792 RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC4_SEL_SFT, rt5682_data_select); 793 794 static const struct snd_kcontrol_new rt5682_if2_adc_swap_mux = 795 SOC_DAPM_ENUM("IF2 ADC Swap Mux", rt5682_if2_adc_enum); 796 797 static const struct snd_kcontrol_new rt5682_if1_01_adc_swap_mux = 798 SOC_DAPM_ENUM("IF1 01 ADC Swap Mux", rt5682_if1_01_adc_enum); 799 800 static const struct snd_kcontrol_new rt5682_if1_23_adc_swap_mux = 801 SOC_DAPM_ENUM("IF1 23 ADC Swap Mux", rt5682_if1_23_adc_enum); 802 803 static const struct snd_kcontrol_new rt5682_if1_45_adc_swap_mux = 804 SOC_DAPM_ENUM("IF1 45 ADC Swap Mux", rt5682_if1_45_adc_enum); 805 806 static const struct snd_kcontrol_new rt5682_if1_67_adc_swap_mux = 807 SOC_DAPM_ENUM("IF1 67 ADC Swap Mux", rt5682_if1_67_adc_enum); 808 809 static void rt5682_reset(struct regmap *regmap) 810 { 811 regmap_write(regmap, RT5682_RESET, 0); 812 regmap_write(regmap, RT5682_I2C_MODE, 1); 813 } 814 /** 815 * rt5682_sel_asrc_clk_src - select ASRC clock source for a set of filters 816 * @component: SoC audio component device. 817 * @filter_mask: mask of filters. 818 * @clk_src: clock source 819 * 820 * The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5682 can 821 * only support standard 32fs or 64fs i2s format, ASRC should be enabled to 822 * support special i2s clock format such as Intel's 100fs(100 * sampling rate). 823 * ASRC function will track i2s clock and generate a corresponding system clock 824 * for codec. This function provides an API to select the clock source for a 825 * set of filters specified by the mask. And the component driver will turn on 826 * ASRC for these filters if ASRC is selected as their clock source. 827 */ 828 int rt5682_sel_asrc_clk_src(struct snd_soc_component *component, 829 unsigned int filter_mask, unsigned int clk_src) 830 { 831 832 switch (clk_src) { 833 case RT5682_CLK_SEL_SYS: 834 case RT5682_CLK_SEL_I2S1_ASRC: 835 case RT5682_CLK_SEL_I2S2_ASRC: 836 break; 837 838 default: 839 return -EINVAL; 840 } 841 842 if (filter_mask & RT5682_DA_STEREO1_FILTER) { 843 snd_soc_component_update_bits(component, RT5682_PLL_TRACK_2, 844 RT5682_FILTER_CLK_SEL_MASK, 845 clk_src << RT5682_FILTER_CLK_SEL_SFT); 846 } 847 848 if (filter_mask & RT5682_AD_STEREO1_FILTER) { 849 snd_soc_component_update_bits(component, RT5682_PLL_TRACK_3, 850 RT5682_FILTER_CLK_SEL_MASK, 851 clk_src << RT5682_FILTER_CLK_SEL_SFT); 852 } 853 854 return 0; 855 } 856 EXPORT_SYMBOL_GPL(rt5682_sel_asrc_clk_src); 857 858 static int rt5682_button_detect(struct snd_soc_component *component) 859 { 860 int btn_type, val; 861 862 val = snd_soc_component_read32(component, RT5682_4BTN_IL_CMD_1); 863 btn_type = val & 0xfff0; 864 snd_soc_component_write(component, RT5682_4BTN_IL_CMD_1, val); 865 pr_debug("%s btn_type=%x\n", __func__, btn_type); 866 snd_soc_component_update_bits(component, 867 RT5682_SAR_IL_CMD_2, 0x10, 0x10); 868 869 return btn_type; 870 } 871 872 static void rt5682_enable_push_button_irq(struct snd_soc_component *component, 873 bool enable) 874 { 875 if (enable) { 876 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1, 877 RT5682_SAR_BUTT_DET_MASK, RT5682_SAR_BUTT_DET_EN); 878 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_13, 879 RT5682_SAR_SOUR_MASK, RT5682_SAR_SOUR_BTN); 880 snd_soc_component_write(component, RT5682_IL_CMD_1, 0x0040); 881 snd_soc_component_update_bits(component, RT5682_4BTN_IL_CMD_2, 882 RT5682_4BTN_IL_MASK | RT5682_4BTN_IL_RST_MASK, 883 RT5682_4BTN_IL_EN | RT5682_4BTN_IL_NOR); 884 snd_soc_component_update_bits(component, RT5682_IRQ_CTRL_3, 885 RT5682_IL_IRQ_MASK, RT5682_IL_IRQ_EN); 886 } else { 887 snd_soc_component_update_bits(component, RT5682_IRQ_CTRL_3, 888 RT5682_IL_IRQ_MASK, RT5682_IL_IRQ_DIS); 889 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1, 890 RT5682_SAR_BUTT_DET_MASK, RT5682_SAR_BUTT_DET_DIS); 891 snd_soc_component_update_bits(component, RT5682_4BTN_IL_CMD_2, 892 RT5682_4BTN_IL_MASK, RT5682_4BTN_IL_DIS); 893 snd_soc_component_update_bits(component, RT5682_4BTN_IL_CMD_2, 894 RT5682_4BTN_IL_RST_MASK, RT5682_4BTN_IL_RST); 895 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_13, 896 RT5682_SAR_SOUR_MASK, RT5682_SAR_SOUR_TYPE); 897 } 898 } 899 900 /** 901 * rt5682_headset_detect - Detect headset. 902 * @component: SoC audio component device. 903 * @jack_insert: Jack insert or not. 904 * 905 * Detect whether is headset or not when jack inserted. 906 * 907 * Returns detect status. 908 */ 909 static int rt5682_headset_detect(struct snd_soc_component *component, 910 int jack_insert) 911 { 912 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 913 unsigned int val, count; 914 915 if (jack_insert) { 916 917 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_1, 918 RT5682_PWR_VREF2 | RT5682_PWR_MB, 919 RT5682_PWR_VREF2 | RT5682_PWR_MB); 920 snd_soc_component_update_bits(component, 921 RT5682_PWR_ANLG_1, RT5682_PWR_FV2, 0); 922 usleep_range(15000, 20000); 923 snd_soc_component_update_bits(component, 924 RT5682_PWR_ANLG_1, RT5682_PWR_FV2, RT5682_PWR_FV2); 925 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_3, 926 RT5682_PWR_CBJ, RT5682_PWR_CBJ); 927 928 snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1, 929 RT5682_TRIG_JD_MASK, RT5682_TRIG_JD_HIGH); 930 931 count = 0; 932 val = snd_soc_component_read32(component, RT5682_CBJ_CTRL_2) 933 & RT5682_JACK_TYPE_MASK; 934 while (val == 0 && count < 50) { 935 usleep_range(10000, 15000); 936 val = snd_soc_component_read32(component, 937 RT5682_CBJ_CTRL_2) & RT5682_JACK_TYPE_MASK; 938 count++; 939 } 940 941 switch (val) { 942 case 0x1: 943 case 0x2: 944 rt5682->jack_type = SND_JACK_HEADSET; 945 rt5682_enable_push_button_irq(component, true); 946 break; 947 default: 948 rt5682->jack_type = SND_JACK_HEADPHONE; 949 } 950 951 } else { 952 rt5682_enable_push_button_irq(component, false); 953 snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1, 954 RT5682_TRIG_JD_MASK, RT5682_TRIG_JD_LOW); 955 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_1, 956 RT5682_PWR_VREF2 | RT5682_PWR_MB, 0); 957 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_3, 958 RT5682_PWR_CBJ, 0); 959 960 rt5682->jack_type = 0; 961 } 962 963 dev_dbg(component->dev, "jack_type = %d\n", rt5682->jack_type); 964 return rt5682->jack_type; 965 } 966 967 static irqreturn_t rt5682_irq(int irq, void *data) 968 { 969 struct rt5682_priv *rt5682 = data; 970 971 mod_delayed_work(system_power_efficient_wq, 972 &rt5682->jack_detect_work, msecs_to_jiffies(250)); 973 974 return IRQ_HANDLED; 975 } 976 977 static void rt5682_jd_check_handler(struct work_struct *work) 978 { 979 struct rt5682_priv *rt5682 = container_of(work, struct rt5682_priv, 980 jd_check_work.work); 981 982 if (snd_soc_component_read32(rt5682->component, RT5682_AJD1_CTRL) 983 & RT5682_JDH_RS_MASK) { 984 /* jack out */ 985 rt5682->jack_type = rt5682_headset_detect(rt5682->component, 0); 986 987 snd_soc_jack_report(rt5682->hs_jack, rt5682->jack_type, 988 SND_JACK_HEADSET | 989 SND_JACK_BTN_0 | SND_JACK_BTN_1 | 990 SND_JACK_BTN_2 | SND_JACK_BTN_3); 991 } else { 992 schedule_delayed_work(&rt5682->jd_check_work, 500); 993 } 994 } 995 996 static int rt5682_set_jack_detect(struct snd_soc_component *component, 997 struct snd_soc_jack *hs_jack, void *data) 998 { 999 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 1000 1001 switch (rt5682->pdata.jd_src) { 1002 case RT5682_JD1: 1003 snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_2, 1004 RT5682_EXT_JD_SRC, RT5682_EXT_JD_SRC_MANUAL); 1005 snd_soc_component_write(component, RT5682_CBJ_CTRL_1, 0xd042); 1006 snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_3, 1007 RT5682_CBJ_IN_BUF_EN, RT5682_CBJ_IN_BUF_EN); 1008 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1, 1009 RT5682_SAR_POW_MASK, RT5682_SAR_POW_EN); 1010 regmap_update_bits(rt5682->regmap, RT5682_GPIO_CTRL_1, 1011 RT5682_GP1_PIN_MASK, RT5682_GP1_PIN_IRQ); 1012 regmap_update_bits(rt5682->regmap, RT5682_RC_CLK_CTRL, 1013 RT5682_POW_IRQ | RT5682_POW_JDH | 1014 RT5682_POW_ANA, RT5682_POW_IRQ | 1015 RT5682_POW_JDH | RT5682_POW_ANA); 1016 regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_2, 1017 RT5682_PWR_JDH | RT5682_PWR_JDL, 1018 RT5682_PWR_JDH | RT5682_PWR_JDL); 1019 regmap_update_bits(rt5682->regmap, RT5682_IRQ_CTRL_2, 1020 RT5682_JD1_EN_MASK | RT5682_JD1_POL_MASK, 1021 RT5682_JD1_EN | RT5682_JD1_POL_NOR); 1022 mod_delayed_work(system_power_efficient_wq, 1023 &rt5682->jack_detect_work, msecs_to_jiffies(250)); 1024 break; 1025 1026 case RT5682_JD_NULL: 1027 regmap_update_bits(rt5682->regmap, RT5682_IRQ_CTRL_2, 1028 RT5682_JD1_EN_MASK, RT5682_JD1_DIS); 1029 regmap_update_bits(rt5682->regmap, RT5682_RC_CLK_CTRL, 1030 RT5682_POW_JDH | RT5682_POW_JDL, 0); 1031 break; 1032 1033 default: 1034 dev_warn(component->dev, "Wrong JD source\n"); 1035 break; 1036 } 1037 1038 rt5682->hs_jack = hs_jack; 1039 1040 return 0; 1041 } 1042 1043 static void rt5682_jack_detect_handler(struct work_struct *work) 1044 { 1045 struct rt5682_priv *rt5682 = 1046 container_of(work, struct rt5682_priv, jack_detect_work.work); 1047 int val, btn_type; 1048 1049 while (!rt5682->component) 1050 usleep_range(10000, 15000); 1051 1052 while (!rt5682->component->card->instantiated) 1053 usleep_range(10000, 15000); 1054 1055 mutex_lock(&rt5682->calibrate_mutex); 1056 1057 val = snd_soc_component_read32(rt5682->component, RT5682_AJD1_CTRL) 1058 & RT5682_JDH_RS_MASK; 1059 if (!val) { 1060 /* jack in */ 1061 if (rt5682->jack_type == 0) { 1062 /* jack was out, report jack type */ 1063 rt5682->jack_type = 1064 rt5682_headset_detect(rt5682->component, 1); 1065 } else { 1066 /* jack is already in, report button event */ 1067 rt5682->jack_type = SND_JACK_HEADSET; 1068 btn_type = rt5682_button_detect(rt5682->component); 1069 /** 1070 * rt5682 can report three kinds of button behavior, 1071 * one click, double click and hold. However, 1072 * currently we will report button pressed/released 1073 * event. So all the three button behaviors are 1074 * treated as button pressed. 1075 */ 1076 switch (btn_type) { 1077 case 0x8000: 1078 case 0x4000: 1079 case 0x2000: 1080 rt5682->jack_type |= SND_JACK_BTN_0; 1081 break; 1082 case 0x1000: 1083 case 0x0800: 1084 case 0x0400: 1085 rt5682->jack_type |= SND_JACK_BTN_1; 1086 break; 1087 case 0x0200: 1088 case 0x0100: 1089 case 0x0080: 1090 rt5682->jack_type |= SND_JACK_BTN_2; 1091 break; 1092 case 0x0040: 1093 case 0x0020: 1094 case 0x0010: 1095 rt5682->jack_type |= SND_JACK_BTN_3; 1096 break; 1097 case 0x0000: /* unpressed */ 1098 break; 1099 default: 1100 btn_type = 0; 1101 dev_err(rt5682->component->dev, 1102 "Unexpected button code 0x%04x\n", 1103 btn_type); 1104 break; 1105 } 1106 } 1107 } else { 1108 /* jack out */ 1109 rt5682->jack_type = rt5682_headset_detect(rt5682->component, 0); 1110 } 1111 1112 snd_soc_jack_report(rt5682->hs_jack, rt5682->jack_type, 1113 SND_JACK_HEADSET | 1114 SND_JACK_BTN_0 | SND_JACK_BTN_1 | 1115 SND_JACK_BTN_2 | SND_JACK_BTN_3); 1116 1117 if (rt5682->jack_type & (SND_JACK_BTN_0 | SND_JACK_BTN_1 | 1118 SND_JACK_BTN_2 | SND_JACK_BTN_3)) 1119 schedule_delayed_work(&rt5682->jd_check_work, 0); 1120 else 1121 cancel_delayed_work_sync(&rt5682->jd_check_work); 1122 1123 mutex_unlock(&rt5682->calibrate_mutex); 1124 } 1125 1126 static const struct snd_kcontrol_new rt5682_snd_controls[] = { 1127 /* DAC Digital Volume */ 1128 SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5682_DAC1_DIG_VOL, 1129 RT5682_L_VOL_SFT + 1, RT5682_R_VOL_SFT + 1, 86, 0, dac_vol_tlv), 1130 1131 /* IN Boost Volume */ 1132 SOC_SINGLE_TLV("CBJ Boost Volume", RT5682_CBJ_BST_CTRL, 1133 RT5682_BST_CBJ_SFT, 8, 0, bst_tlv), 1134 1135 /* ADC Digital Volume Control */ 1136 SOC_DOUBLE("STO1 ADC Capture Switch", RT5682_STO1_ADC_DIG_VOL, 1137 RT5682_L_MUTE_SFT, RT5682_R_MUTE_SFT, 1, 1), 1138 SOC_DOUBLE_TLV("STO1 ADC Capture Volume", RT5682_STO1_ADC_DIG_VOL, 1139 RT5682_L_VOL_SFT + 1, RT5682_R_VOL_SFT + 1, 63, 0, adc_vol_tlv), 1140 1141 /* ADC Boost Volume Control */ 1142 SOC_DOUBLE_TLV("STO1 ADC Boost Gain Volume", RT5682_STO1_ADC_BOOST, 1143 RT5682_STO1_ADC_L_BST_SFT, RT5682_STO1_ADC_R_BST_SFT, 1144 3, 0, adc_bst_tlv), 1145 }; 1146 1147 1148 static int rt5682_div_sel(struct rt5682_priv *rt5682, 1149 int target, const int div[], int size) 1150 { 1151 int i; 1152 1153 if (rt5682->sysclk < target) { 1154 pr_err("sysclk rate %d is too low\n", 1155 rt5682->sysclk); 1156 return 0; 1157 } 1158 1159 for (i = 0; i < size - 1; i++) { 1160 pr_info("div[%d]=%d\n", i, div[i]); 1161 if (target * div[i] == rt5682->sysclk) 1162 return i; 1163 if (target * div[i + 1] > rt5682->sysclk) { 1164 pr_err("can't find div for sysclk %d\n", 1165 rt5682->sysclk); 1166 return i; 1167 } 1168 } 1169 1170 if (target * div[i] < rt5682->sysclk) 1171 pr_err("sysclk rate %d is too high\n", 1172 rt5682->sysclk); 1173 1174 return size - 1; 1175 1176 } 1177 1178 /** 1179 * set_dmic_clk - Set parameter of dmic. 1180 * 1181 * @w: DAPM widget. 1182 * @kcontrol: The kcontrol of this widget. 1183 * @event: Event id. 1184 * 1185 * Choose dmic clock between 1MHz and 3MHz. 1186 * It is better for clock to approximate 3MHz. 1187 */ 1188 static int set_dmic_clk(struct snd_soc_dapm_widget *w, 1189 struct snd_kcontrol *kcontrol, int event) 1190 { 1191 struct snd_soc_component *component = 1192 snd_soc_dapm_to_component(w->dapm); 1193 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 1194 int idx = -EINVAL; 1195 static const int div[] = {2, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, 128}; 1196 1197 idx = rt5682_div_sel(rt5682, 1500000, div, ARRAY_SIZE(div)); 1198 1199 snd_soc_component_update_bits(component, RT5682_DMIC_CTRL_1, 1200 RT5682_DMIC_CLK_MASK, idx << RT5682_DMIC_CLK_SFT); 1201 1202 return 0; 1203 } 1204 1205 static int set_filter_clk(struct snd_soc_dapm_widget *w, 1206 struct snd_kcontrol *kcontrol, int event) 1207 { 1208 struct snd_soc_component *component = 1209 snd_soc_dapm_to_component(w->dapm); 1210 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 1211 int ref, val, reg, idx = -EINVAL; 1212 static const int div_f[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32, 48}; 1213 static const int div_o[] = {1, 2, 4, 6, 8, 12, 16, 24, 32, 48}; 1214 1215 val = snd_soc_component_read32(component, RT5682_GPIO_CTRL_1) & 1216 RT5682_GP4_PIN_MASK; 1217 if (w->shift == RT5682_PWR_ADC_S1F_BIT && 1218 val == RT5682_GP4_PIN_ADCDAT2) 1219 ref = 256 * rt5682->lrck[RT5682_AIF2]; 1220 else 1221 ref = 256 * rt5682->lrck[RT5682_AIF1]; 1222 1223 idx = rt5682_div_sel(rt5682, ref, div_f, ARRAY_SIZE(div_f)); 1224 1225 if (w->shift == RT5682_PWR_ADC_S1F_BIT) 1226 reg = RT5682_PLL_TRACK_3; 1227 else 1228 reg = RT5682_PLL_TRACK_2; 1229 1230 snd_soc_component_update_bits(component, reg, 1231 RT5682_FILTER_CLK_DIV_MASK, idx << RT5682_FILTER_CLK_DIV_SFT); 1232 1233 /* select over sample rate */ 1234 for (idx = 0; idx < ARRAY_SIZE(div_o); idx++) { 1235 if (rt5682->sysclk <= 12288000 * div_o[idx]) 1236 break; 1237 } 1238 1239 snd_soc_component_update_bits(component, RT5682_ADDA_CLK_1, 1240 RT5682_ADC_OSR_MASK | RT5682_DAC_OSR_MASK, 1241 (idx << RT5682_ADC_OSR_SFT) | (idx << RT5682_DAC_OSR_SFT)); 1242 1243 return 0; 1244 } 1245 1246 static int is_sys_clk_from_pll1(struct snd_soc_dapm_widget *w, 1247 struct snd_soc_dapm_widget *sink) 1248 { 1249 unsigned int val; 1250 struct snd_soc_component *component = 1251 snd_soc_dapm_to_component(w->dapm); 1252 1253 val = snd_soc_component_read32(component, RT5682_GLB_CLK); 1254 val &= RT5682_SCLK_SRC_MASK; 1255 if (val == RT5682_SCLK_SRC_PLL1) 1256 return 1; 1257 else 1258 return 0; 1259 } 1260 1261 static int is_using_asrc(struct snd_soc_dapm_widget *w, 1262 struct snd_soc_dapm_widget *sink) 1263 { 1264 unsigned int reg, shift, val; 1265 struct snd_soc_component *component = 1266 snd_soc_dapm_to_component(w->dapm); 1267 1268 switch (w->shift) { 1269 case RT5682_ADC_STO1_ASRC_SFT: 1270 reg = RT5682_PLL_TRACK_3; 1271 shift = RT5682_FILTER_CLK_SEL_SFT; 1272 break; 1273 case RT5682_DAC_STO1_ASRC_SFT: 1274 reg = RT5682_PLL_TRACK_2; 1275 shift = RT5682_FILTER_CLK_SEL_SFT; 1276 break; 1277 default: 1278 return 0; 1279 } 1280 1281 val = (snd_soc_component_read32(component, reg) >> shift) & 0xf; 1282 switch (val) { 1283 case RT5682_CLK_SEL_I2S1_ASRC: 1284 case RT5682_CLK_SEL_I2S2_ASRC: 1285 return 1; 1286 default: 1287 return 0; 1288 } 1289 1290 } 1291 1292 /* Digital Mixer */ 1293 static const struct snd_kcontrol_new rt5682_sto1_adc_l_mix[] = { 1294 SOC_DAPM_SINGLE("ADC1 Switch", RT5682_STO1_ADC_MIXER, 1295 RT5682_M_STO1_ADC_L1_SFT, 1, 1), 1296 SOC_DAPM_SINGLE("ADC2 Switch", RT5682_STO1_ADC_MIXER, 1297 RT5682_M_STO1_ADC_L2_SFT, 1, 1), 1298 }; 1299 1300 static const struct snd_kcontrol_new rt5682_sto1_adc_r_mix[] = { 1301 SOC_DAPM_SINGLE("ADC1 Switch", RT5682_STO1_ADC_MIXER, 1302 RT5682_M_STO1_ADC_R1_SFT, 1, 1), 1303 SOC_DAPM_SINGLE("ADC2 Switch", RT5682_STO1_ADC_MIXER, 1304 RT5682_M_STO1_ADC_R2_SFT, 1, 1), 1305 }; 1306 1307 static const struct snd_kcontrol_new rt5682_dac_l_mix[] = { 1308 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5682_AD_DA_MIXER, 1309 RT5682_M_ADCMIX_L_SFT, 1, 1), 1310 SOC_DAPM_SINGLE("DAC1 Switch", RT5682_AD_DA_MIXER, 1311 RT5682_M_DAC1_L_SFT, 1, 1), 1312 }; 1313 1314 static const struct snd_kcontrol_new rt5682_dac_r_mix[] = { 1315 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5682_AD_DA_MIXER, 1316 RT5682_M_ADCMIX_R_SFT, 1, 1), 1317 SOC_DAPM_SINGLE("DAC1 Switch", RT5682_AD_DA_MIXER, 1318 RT5682_M_DAC1_R_SFT, 1, 1), 1319 }; 1320 1321 static const struct snd_kcontrol_new rt5682_sto1_dac_l_mix[] = { 1322 SOC_DAPM_SINGLE("DAC L1 Switch", RT5682_STO1_DAC_MIXER, 1323 RT5682_M_DAC_L1_STO_L_SFT, 1, 1), 1324 SOC_DAPM_SINGLE("DAC R1 Switch", RT5682_STO1_DAC_MIXER, 1325 RT5682_M_DAC_R1_STO_L_SFT, 1, 1), 1326 }; 1327 1328 static const struct snd_kcontrol_new rt5682_sto1_dac_r_mix[] = { 1329 SOC_DAPM_SINGLE("DAC L1 Switch", RT5682_STO1_DAC_MIXER, 1330 RT5682_M_DAC_L1_STO_R_SFT, 1, 1), 1331 SOC_DAPM_SINGLE("DAC R1 Switch", RT5682_STO1_DAC_MIXER, 1332 RT5682_M_DAC_R1_STO_R_SFT, 1, 1), 1333 }; 1334 1335 /* Analog Input Mixer */ 1336 static const struct snd_kcontrol_new rt5682_rec1_l_mix[] = { 1337 SOC_DAPM_SINGLE("CBJ Switch", RT5682_REC_MIXER, 1338 RT5682_M_CBJ_RM1_L_SFT, 1, 1), 1339 }; 1340 1341 /* STO1 ADC1 Source */ 1342 /* MX-26 [13] [5] */ 1343 static const char * const rt5682_sto1_adc1_src[] = { 1344 "DAC MIX", "ADC" 1345 }; 1346 1347 static SOC_ENUM_SINGLE_DECL( 1348 rt5682_sto1_adc1l_enum, RT5682_STO1_ADC_MIXER, 1349 RT5682_STO1_ADC1L_SRC_SFT, rt5682_sto1_adc1_src); 1350 1351 static const struct snd_kcontrol_new rt5682_sto1_adc1l_mux = 1352 SOC_DAPM_ENUM("Stereo1 ADC1L Source", rt5682_sto1_adc1l_enum); 1353 1354 static SOC_ENUM_SINGLE_DECL( 1355 rt5682_sto1_adc1r_enum, RT5682_STO1_ADC_MIXER, 1356 RT5682_STO1_ADC1R_SRC_SFT, rt5682_sto1_adc1_src); 1357 1358 static const struct snd_kcontrol_new rt5682_sto1_adc1r_mux = 1359 SOC_DAPM_ENUM("Stereo1 ADC1L Source", rt5682_sto1_adc1r_enum); 1360 1361 /* STO1 ADC Source */ 1362 /* MX-26 [11:10] [3:2] */ 1363 static const char * const rt5682_sto1_adc_src[] = { 1364 "ADC1 L", "ADC1 R" 1365 }; 1366 1367 static SOC_ENUM_SINGLE_DECL( 1368 rt5682_sto1_adcl_enum, RT5682_STO1_ADC_MIXER, 1369 RT5682_STO1_ADCL_SRC_SFT, rt5682_sto1_adc_src); 1370 1371 static const struct snd_kcontrol_new rt5682_sto1_adcl_mux = 1372 SOC_DAPM_ENUM("Stereo1 ADCL Source", rt5682_sto1_adcl_enum); 1373 1374 static SOC_ENUM_SINGLE_DECL( 1375 rt5682_sto1_adcr_enum, RT5682_STO1_ADC_MIXER, 1376 RT5682_STO1_ADCR_SRC_SFT, rt5682_sto1_adc_src); 1377 1378 static const struct snd_kcontrol_new rt5682_sto1_adcr_mux = 1379 SOC_DAPM_ENUM("Stereo1 ADCR Source", rt5682_sto1_adcr_enum); 1380 1381 /* STO1 ADC2 Source */ 1382 /* MX-26 [12] [4] */ 1383 static const char * const rt5682_sto1_adc2_src[] = { 1384 "DAC MIX", "DMIC" 1385 }; 1386 1387 static SOC_ENUM_SINGLE_DECL( 1388 rt5682_sto1_adc2l_enum, RT5682_STO1_ADC_MIXER, 1389 RT5682_STO1_ADC2L_SRC_SFT, rt5682_sto1_adc2_src); 1390 1391 static const struct snd_kcontrol_new rt5682_sto1_adc2l_mux = 1392 SOC_DAPM_ENUM("Stereo1 ADC2L Source", rt5682_sto1_adc2l_enum); 1393 1394 static SOC_ENUM_SINGLE_DECL( 1395 rt5682_sto1_adc2r_enum, RT5682_STO1_ADC_MIXER, 1396 RT5682_STO1_ADC2R_SRC_SFT, rt5682_sto1_adc2_src); 1397 1398 static const struct snd_kcontrol_new rt5682_sto1_adc2r_mux = 1399 SOC_DAPM_ENUM("Stereo1 ADC2R Source", rt5682_sto1_adc2r_enum); 1400 1401 /* MX-79 [6:4] I2S1 ADC data location */ 1402 static const unsigned int rt5682_if1_adc_slot_values[] = { 1403 0, 1404 2, 1405 4, 1406 6, 1407 }; 1408 1409 static const char * const rt5682_if1_adc_slot_src[] = { 1410 "Slot 0", "Slot 2", "Slot 4", "Slot 6" 1411 }; 1412 1413 static SOC_VALUE_ENUM_SINGLE_DECL(rt5682_if1_adc_slot_enum, 1414 RT5682_TDM_CTRL, RT5682_TDM_ADC_LCA_SFT, RT5682_TDM_ADC_LCA_MASK, 1415 rt5682_if1_adc_slot_src, rt5682_if1_adc_slot_values); 1416 1417 static const struct snd_kcontrol_new rt5682_if1_adc_slot_mux = 1418 SOC_DAPM_ENUM("IF1 ADC Slot location", rt5682_if1_adc_slot_enum); 1419 1420 /* Analog DAC L1 Source, Analog DAC R1 Source*/ 1421 /* MX-2B [4], MX-2B [0]*/ 1422 static const char * const rt5682_alg_dac1_src[] = { 1423 "Stereo1 DAC Mixer", "DAC1" 1424 }; 1425 1426 static SOC_ENUM_SINGLE_DECL( 1427 rt5682_alg_dac_l1_enum, RT5682_A_DAC1_MUX, 1428 RT5682_A_DACL1_SFT, rt5682_alg_dac1_src); 1429 1430 static const struct snd_kcontrol_new rt5682_alg_dac_l1_mux = 1431 SOC_DAPM_ENUM("Analog DAC L1 Source", rt5682_alg_dac_l1_enum); 1432 1433 static SOC_ENUM_SINGLE_DECL( 1434 rt5682_alg_dac_r1_enum, RT5682_A_DAC1_MUX, 1435 RT5682_A_DACR1_SFT, rt5682_alg_dac1_src); 1436 1437 static const struct snd_kcontrol_new rt5682_alg_dac_r1_mux = 1438 SOC_DAPM_ENUM("Analog DAC R1 Source", rt5682_alg_dac_r1_enum); 1439 1440 /* Out Switch */ 1441 static const struct snd_kcontrol_new hpol_switch = 1442 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5682_HP_CTRL_1, 1443 RT5682_L_MUTE_SFT, 1, 1); 1444 static const struct snd_kcontrol_new hpor_switch = 1445 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5682_HP_CTRL_1, 1446 RT5682_R_MUTE_SFT, 1, 1); 1447 1448 static int rt5682_charge_pump_event(struct snd_soc_dapm_widget *w, 1449 struct snd_kcontrol *kcontrol, int event) 1450 { 1451 struct snd_soc_component *component = 1452 snd_soc_dapm_to_component(w->dapm); 1453 1454 switch (event) { 1455 case SND_SOC_DAPM_PRE_PMU: 1456 snd_soc_component_update_bits(component, 1457 RT5682_HP_CHARGE_PUMP_1, RT5682_PM_HP_MASK, RT5682_PM_HP_HV); 1458 break; 1459 case SND_SOC_DAPM_POST_PMD: 1460 snd_soc_component_update_bits(component, 1461 RT5682_HP_CHARGE_PUMP_1, RT5682_PM_HP_MASK, RT5682_PM_HP_LV); 1462 break; 1463 default: 1464 return 0; 1465 } 1466 1467 return 0; 1468 } 1469 1470 static int rt5682_hp_event(struct snd_soc_dapm_widget *w, 1471 struct snd_kcontrol *kcontrol, int event) 1472 { 1473 struct snd_soc_component *component = 1474 snd_soc_dapm_to_component(w->dapm); 1475 1476 switch (event) { 1477 case SND_SOC_DAPM_PRE_PMU: 1478 snd_soc_component_write(component, 1479 RT5682_HP_LOGIC_CTRL_2, 0x0012); 1480 snd_soc_component_write(component, 1481 RT5682_HP_CTRL_2, 0x6000); 1482 snd_soc_component_update_bits(component, 1483 RT5682_DEPOP_1, 0x60, 0x60); 1484 snd_soc_component_update_bits(component, 1485 RT5682_DAC_ADC_DIG_VOL1, 0x00c0, 0x0080); 1486 break; 1487 1488 case SND_SOC_DAPM_POST_PMD: 1489 snd_soc_component_update_bits(component, 1490 RT5682_DEPOP_1, 0x60, 0x0); 1491 snd_soc_component_write(component, 1492 RT5682_HP_CTRL_2, 0x0000); 1493 snd_soc_component_update_bits(component, 1494 RT5682_DAC_ADC_DIG_VOL1, 0x00c0, 0x0000); 1495 break; 1496 1497 default: 1498 return 0; 1499 } 1500 1501 return 0; 1502 1503 } 1504 1505 static int set_dmic_power(struct snd_soc_dapm_widget *w, 1506 struct snd_kcontrol *kcontrol, int event) 1507 { 1508 switch (event) { 1509 case SND_SOC_DAPM_POST_PMU: 1510 /*Add delay to avoid pop noise*/ 1511 msleep(150); 1512 break; 1513 1514 default: 1515 return 0; 1516 } 1517 1518 return 0; 1519 } 1520 1521 static int rt5655_set_verf(struct snd_soc_dapm_widget *w, 1522 struct snd_kcontrol *kcontrol, int event) 1523 { 1524 struct snd_soc_component *component = 1525 snd_soc_dapm_to_component(w->dapm); 1526 1527 switch (event) { 1528 case SND_SOC_DAPM_PRE_PMU: 1529 switch (w->shift) { 1530 case RT5682_PWR_VREF1_BIT: 1531 snd_soc_component_update_bits(component, 1532 RT5682_PWR_ANLG_1, RT5682_PWR_FV1, 0); 1533 break; 1534 1535 case RT5682_PWR_VREF2_BIT: 1536 snd_soc_component_update_bits(component, 1537 RT5682_PWR_ANLG_1, RT5682_PWR_FV2, 0); 1538 break; 1539 1540 default: 1541 break; 1542 } 1543 break; 1544 1545 case SND_SOC_DAPM_POST_PMU: 1546 usleep_range(15000, 20000); 1547 switch (w->shift) { 1548 case RT5682_PWR_VREF1_BIT: 1549 snd_soc_component_update_bits(component, 1550 RT5682_PWR_ANLG_1, RT5682_PWR_FV1, 1551 RT5682_PWR_FV1); 1552 break; 1553 1554 case RT5682_PWR_VREF2_BIT: 1555 snd_soc_component_update_bits(component, 1556 RT5682_PWR_ANLG_1, RT5682_PWR_FV2, 1557 RT5682_PWR_FV2); 1558 break; 1559 1560 default: 1561 break; 1562 } 1563 break; 1564 1565 default: 1566 return 0; 1567 } 1568 1569 return 0; 1570 } 1571 1572 static const unsigned int rt5682_adcdat_pin_values[] = { 1573 1, 1574 3, 1575 }; 1576 1577 static const char * const rt5682_adcdat_pin_select[] = { 1578 "ADCDAT1", 1579 "ADCDAT2", 1580 }; 1581 1582 static SOC_VALUE_ENUM_SINGLE_DECL(rt5682_adcdat_pin_enum, 1583 RT5682_GPIO_CTRL_1, RT5682_GP4_PIN_SFT, RT5682_GP4_PIN_MASK, 1584 rt5682_adcdat_pin_select, rt5682_adcdat_pin_values); 1585 1586 static const struct snd_kcontrol_new rt5682_adcdat_pin_ctrl = 1587 SOC_DAPM_ENUM("ADCDAT", rt5682_adcdat_pin_enum); 1588 1589 static const struct snd_soc_dapm_widget rt5682_dapm_widgets[] = { 1590 SND_SOC_DAPM_SUPPLY("LDO2", RT5682_PWR_ANLG_3, RT5682_PWR_LDO2_BIT, 1591 0, NULL, 0), 1592 SND_SOC_DAPM_SUPPLY("PLL1", RT5682_PWR_ANLG_3, RT5682_PWR_PLL_BIT, 1593 0, NULL, 0), 1594 SND_SOC_DAPM_SUPPLY("PLL2B", RT5682_PWR_ANLG_3, RT5682_PWR_PLL2B_BIT, 1595 0, NULL, 0), 1596 SND_SOC_DAPM_SUPPLY("PLL2F", RT5682_PWR_ANLG_3, RT5682_PWR_PLL2F_BIT, 1597 0, NULL, 0), 1598 SND_SOC_DAPM_SUPPLY("Vref1", RT5682_PWR_ANLG_1, RT5682_PWR_VREF1_BIT, 0, 1599 rt5655_set_verf, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), 1600 1601 /* ASRC */ 1602 SND_SOC_DAPM_SUPPLY_S("DAC STO1 ASRC", 1, RT5682_PLL_TRACK_1, 1603 RT5682_DAC_STO1_ASRC_SFT, 0, NULL, 0), 1604 SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5682_PLL_TRACK_1, 1605 RT5682_ADC_STO1_ASRC_SFT, 0, NULL, 0), 1606 SND_SOC_DAPM_SUPPLY_S("AD ASRC", 1, RT5682_PLL_TRACK_1, 1607 RT5682_AD_ASRC_SFT, 0, NULL, 0), 1608 SND_SOC_DAPM_SUPPLY_S("DA ASRC", 1, RT5682_PLL_TRACK_1, 1609 RT5682_DA_ASRC_SFT, 0, NULL, 0), 1610 SND_SOC_DAPM_SUPPLY_S("DMIC ASRC", 1, RT5682_PLL_TRACK_1, 1611 RT5682_DMIC_ASRC_SFT, 0, NULL, 0), 1612 1613 /* Input Side */ 1614 SND_SOC_DAPM_SUPPLY("MICBIAS1", RT5682_PWR_ANLG_2, RT5682_PWR_MB1_BIT, 1615 0, NULL, 0), 1616 SND_SOC_DAPM_SUPPLY("MICBIAS2", RT5682_PWR_ANLG_2, RT5682_PWR_MB2_BIT, 1617 0, NULL, 0), 1618 1619 /* Input Lines */ 1620 SND_SOC_DAPM_INPUT("DMIC L1"), 1621 SND_SOC_DAPM_INPUT("DMIC R1"), 1622 1623 SND_SOC_DAPM_INPUT("IN1P"), 1624 1625 SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0, 1626 set_dmic_clk, SND_SOC_DAPM_PRE_PMU), 1627 SND_SOC_DAPM_SUPPLY("DMIC1 Power", RT5682_DMIC_CTRL_1, 1628 RT5682_DMIC_1_EN_SFT, 0, set_dmic_power, SND_SOC_DAPM_POST_PMU), 1629 1630 /* Boost */ 1631 SND_SOC_DAPM_PGA("BST1 CBJ", SND_SOC_NOPM, 1632 0, 0, NULL, 0), 1633 1634 /* REC Mixer */ 1635 SND_SOC_DAPM_MIXER("RECMIX1L", SND_SOC_NOPM, 0, 0, rt5682_rec1_l_mix, 1636 ARRAY_SIZE(rt5682_rec1_l_mix)), 1637 SND_SOC_DAPM_SUPPLY("RECMIX1L Power", RT5682_PWR_ANLG_2, 1638 RT5682_PWR_RM1_L_BIT, 0, NULL, 0), 1639 1640 /* ADCs */ 1641 SND_SOC_DAPM_ADC("ADC1 L", NULL, SND_SOC_NOPM, 0, 0), 1642 SND_SOC_DAPM_ADC("ADC1 R", NULL, SND_SOC_NOPM, 0, 0), 1643 1644 SND_SOC_DAPM_SUPPLY("ADC1 L Power", RT5682_PWR_DIG_1, 1645 RT5682_PWR_ADC_L1_BIT, 0, NULL, 0), 1646 SND_SOC_DAPM_SUPPLY("ADC1 R Power", RT5682_PWR_DIG_1, 1647 RT5682_PWR_ADC_R1_BIT, 0, NULL, 0), 1648 SND_SOC_DAPM_SUPPLY("ADC1 clock", RT5682_CHOP_ADC, 1649 RT5682_CKGEN_ADC1_SFT, 0, NULL, 0), 1650 1651 /* ADC Mux */ 1652 SND_SOC_DAPM_MUX("Stereo1 ADC L1 Mux", SND_SOC_NOPM, 0, 0, 1653 &rt5682_sto1_adc1l_mux), 1654 SND_SOC_DAPM_MUX("Stereo1 ADC R1 Mux", SND_SOC_NOPM, 0, 0, 1655 &rt5682_sto1_adc1r_mux), 1656 SND_SOC_DAPM_MUX("Stereo1 ADC L2 Mux", SND_SOC_NOPM, 0, 0, 1657 &rt5682_sto1_adc2l_mux), 1658 SND_SOC_DAPM_MUX("Stereo1 ADC R2 Mux", SND_SOC_NOPM, 0, 0, 1659 &rt5682_sto1_adc2r_mux), 1660 SND_SOC_DAPM_MUX("Stereo1 ADC L Mux", SND_SOC_NOPM, 0, 0, 1661 &rt5682_sto1_adcl_mux), 1662 SND_SOC_DAPM_MUX("Stereo1 ADC R Mux", SND_SOC_NOPM, 0, 0, 1663 &rt5682_sto1_adcr_mux), 1664 SND_SOC_DAPM_MUX("IF1_ADC Mux", SND_SOC_NOPM, 0, 0, 1665 &rt5682_if1_adc_slot_mux), 1666 1667 /* ADC Mixer */ 1668 SND_SOC_DAPM_SUPPLY("ADC Stereo1 Filter", RT5682_PWR_DIG_2, 1669 RT5682_PWR_ADC_S1F_BIT, 0, set_filter_clk, 1670 SND_SOC_DAPM_PRE_PMU), 1671 SND_SOC_DAPM_MIXER("Stereo1 ADC MIXL", RT5682_STO1_ADC_DIG_VOL, 1672 RT5682_L_MUTE_SFT, 1, rt5682_sto1_adc_l_mix, 1673 ARRAY_SIZE(rt5682_sto1_adc_l_mix)), 1674 SND_SOC_DAPM_MIXER("Stereo1 ADC MIXR", RT5682_STO1_ADC_DIG_VOL, 1675 RT5682_R_MUTE_SFT, 1, rt5682_sto1_adc_r_mix, 1676 ARRAY_SIZE(rt5682_sto1_adc_r_mix)), 1677 SND_SOC_DAPM_SUPPLY("BTN Detection Mode", RT5682_SAR_IL_CMD_1, 1678 14, 1, NULL, 0), 1679 1680 /* ADC PGA */ 1681 SND_SOC_DAPM_PGA("Stereo1 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 1682 1683 /* Digital Interface */ 1684 SND_SOC_DAPM_SUPPLY("I2S1", RT5682_PWR_DIG_1, RT5682_PWR_I2S1_BIT, 1685 0, NULL, 0), 1686 SND_SOC_DAPM_SUPPLY("I2S2", RT5682_PWR_DIG_1, RT5682_PWR_I2S2_BIT, 1687 0, NULL, 0), 1688 SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0), 1689 SND_SOC_DAPM_PGA("IF1 DAC1 L", SND_SOC_NOPM, 0, 0, NULL, 0), 1690 SND_SOC_DAPM_PGA("IF1 DAC1 R", SND_SOC_NOPM, 0, 0, NULL, 0), 1691 1692 /* Digital Interface Select */ 1693 SND_SOC_DAPM_MUX("IF1 01 ADC Swap Mux", SND_SOC_NOPM, 0, 0, 1694 &rt5682_if1_01_adc_swap_mux), 1695 SND_SOC_DAPM_MUX("IF1 23 ADC Swap Mux", SND_SOC_NOPM, 0, 0, 1696 &rt5682_if1_23_adc_swap_mux), 1697 SND_SOC_DAPM_MUX("IF1 45 ADC Swap Mux", SND_SOC_NOPM, 0, 0, 1698 &rt5682_if1_45_adc_swap_mux), 1699 SND_SOC_DAPM_MUX("IF1 67 ADC Swap Mux", SND_SOC_NOPM, 0, 0, 1700 &rt5682_if1_67_adc_swap_mux), 1701 SND_SOC_DAPM_MUX("IF2 ADC Swap Mux", SND_SOC_NOPM, 0, 0, 1702 &rt5682_if2_adc_swap_mux), 1703 1704 SND_SOC_DAPM_MUX("ADCDAT Mux", SND_SOC_NOPM, 0, 0, 1705 &rt5682_adcdat_pin_ctrl), 1706 1707 /* Audio Interface */ 1708 SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, 1709 RT5682_I2S1_SDP, RT5682_SEL_ADCDAT_SFT, 1), 1710 SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, 1711 RT5682_I2S2_SDP, RT5682_I2S2_PIN_CFG_SFT, 1), 1712 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0), 1713 1714 /* Output Side */ 1715 /* DAC mixer before sound effect */ 1716 SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0, 1717 rt5682_dac_l_mix, ARRAY_SIZE(rt5682_dac_l_mix)), 1718 SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0, 1719 rt5682_dac_r_mix, ARRAY_SIZE(rt5682_dac_r_mix)), 1720 1721 /* DAC channel Mux */ 1722 SND_SOC_DAPM_MUX("DAC L1 Source", SND_SOC_NOPM, 0, 0, 1723 &rt5682_alg_dac_l1_mux), 1724 SND_SOC_DAPM_MUX("DAC R1 Source", SND_SOC_NOPM, 0, 0, 1725 &rt5682_alg_dac_r1_mux), 1726 1727 /* DAC Mixer */ 1728 SND_SOC_DAPM_SUPPLY("DAC Stereo1 Filter", RT5682_PWR_DIG_2, 1729 RT5682_PWR_DAC_S1F_BIT, 0, set_filter_clk, 1730 SND_SOC_DAPM_PRE_PMU), 1731 SND_SOC_DAPM_MIXER("Stereo1 DAC MIXL", SND_SOC_NOPM, 0, 0, 1732 rt5682_sto1_dac_l_mix, ARRAY_SIZE(rt5682_sto1_dac_l_mix)), 1733 SND_SOC_DAPM_MIXER("Stereo1 DAC MIXR", SND_SOC_NOPM, 0, 0, 1734 rt5682_sto1_dac_r_mix, ARRAY_SIZE(rt5682_sto1_dac_r_mix)), 1735 1736 /* DACs */ 1737 SND_SOC_DAPM_DAC("DAC L1", NULL, RT5682_PWR_DIG_1, 1738 RT5682_PWR_DAC_L1_BIT, 0), 1739 SND_SOC_DAPM_DAC("DAC R1", NULL, RT5682_PWR_DIG_1, 1740 RT5682_PWR_DAC_R1_BIT, 0), 1741 SND_SOC_DAPM_SUPPLY_S("DAC 1 Clock", 3, RT5682_CHOP_DAC, 1742 RT5682_CKGEN_DAC1_SFT, 0, NULL, 0), 1743 1744 /* HPO */ 1745 SND_SOC_DAPM_PGA_S("HP Amp", 1, SND_SOC_NOPM, 0, 0, rt5682_hp_event, 1746 SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_PRE_PMU), 1747 1748 SND_SOC_DAPM_SUPPLY("HP Amp L", RT5682_PWR_ANLG_1, 1749 RT5682_PWR_HA_L_BIT, 0, NULL, 0), 1750 SND_SOC_DAPM_SUPPLY("HP Amp R", RT5682_PWR_ANLG_1, 1751 RT5682_PWR_HA_R_BIT, 0, NULL, 0), 1752 SND_SOC_DAPM_SUPPLY_S("Charge Pump", 1, RT5682_DEPOP_1, 1753 RT5682_PUMP_EN_SFT, 0, rt5682_charge_pump_event, 1754 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 1755 SND_SOC_DAPM_SUPPLY_S("Capless", 2, RT5682_DEPOP_1, 1756 RT5682_CAPLESS_EN_SFT, 0, NULL, 0), 1757 1758 SND_SOC_DAPM_SWITCH("HPOL Playback", SND_SOC_NOPM, 0, 0, 1759 &hpol_switch), 1760 SND_SOC_DAPM_SWITCH("HPOR Playback", SND_SOC_NOPM, 0, 0, 1761 &hpor_switch), 1762 1763 /* CLK DET */ 1764 SND_SOC_DAPM_SUPPLY("CLKDET SYS", RT5682_CLK_DET, 1765 RT5682_SYS_CLK_DET_SFT, 0, NULL, 0), 1766 SND_SOC_DAPM_SUPPLY("CLKDET PLL1", RT5682_CLK_DET, 1767 RT5682_PLL1_CLK_DET_SFT, 0, NULL, 0), 1768 SND_SOC_DAPM_SUPPLY("CLKDET PLL2", RT5682_CLK_DET, 1769 RT5682_PLL2_CLK_DET_SFT, 0, NULL, 0), 1770 SND_SOC_DAPM_SUPPLY("CLKDET", RT5682_CLK_DET, 1771 RT5682_POW_CLK_DET_SFT, 0, NULL, 0), 1772 1773 /* Output Lines */ 1774 SND_SOC_DAPM_OUTPUT("HPOL"), 1775 SND_SOC_DAPM_OUTPUT("HPOR"), 1776 1777 }; 1778 1779 static const struct snd_soc_dapm_route rt5682_dapm_routes[] = { 1780 /*PLL*/ 1781 {"ADC Stereo1 Filter", NULL, "PLL1", is_sys_clk_from_pll1}, 1782 {"DAC Stereo1 Filter", NULL, "PLL1", is_sys_clk_from_pll1}, 1783 1784 /*ASRC*/ 1785 {"ADC Stereo1 Filter", NULL, "ADC STO1 ASRC", is_using_asrc}, 1786 {"DAC Stereo1 Filter", NULL, "DAC STO1 ASRC", is_using_asrc}, 1787 {"ADC STO1 ASRC", NULL, "AD ASRC"}, 1788 {"ADC STO1 ASRC", NULL, "DA ASRC"}, 1789 {"ADC STO1 ASRC", NULL, "CLKDET"}, 1790 {"DAC STO1 ASRC", NULL, "AD ASRC"}, 1791 {"DAC STO1 ASRC", NULL, "DA ASRC"}, 1792 {"DAC STO1 ASRC", NULL, "CLKDET"}, 1793 1794 /*Vref*/ 1795 {"MICBIAS1", NULL, "Vref1"}, 1796 {"MICBIAS2", NULL, "Vref1"}, 1797 1798 {"CLKDET SYS", NULL, "CLKDET"}, 1799 1800 {"IN1P", NULL, "LDO2"}, 1801 1802 {"BST1 CBJ", NULL, "IN1P"}, 1803 1804 {"RECMIX1L", "CBJ Switch", "BST1 CBJ"}, 1805 {"RECMIX1L", NULL, "RECMIX1L Power"}, 1806 1807 {"ADC1 L", NULL, "RECMIX1L"}, 1808 {"ADC1 L", NULL, "ADC1 L Power"}, 1809 {"ADC1 L", NULL, "ADC1 clock"}, 1810 1811 {"DMIC L1", NULL, "DMIC CLK"}, 1812 {"DMIC L1", NULL, "DMIC1 Power"}, 1813 {"DMIC R1", NULL, "DMIC CLK"}, 1814 {"DMIC R1", NULL, "DMIC1 Power"}, 1815 {"DMIC CLK", NULL, "DMIC ASRC"}, 1816 1817 {"Stereo1 ADC L Mux", "ADC1 L", "ADC1 L"}, 1818 {"Stereo1 ADC L Mux", "ADC1 R", "ADC1 R"}, 1819 {"Stereo1 ADC R Mux", "ADC1 L", "ADC1 L"}, 1820 {"Stereo1 ADC R Mux", "ADC1 R", "ADC1 R"}, 1821 1822 {"Stereo1 ADC L1 Mux", "ADC", "Stereo1 ADC L Mux"}, 1823 {"Stereo1 ADC L1 Mux", "DAC MIX", "Stereo1 DAC MIXL"}, 1824 {"Stereo1 ADC L2 Mux", "DMIC", "DMIC L1"}, 1825 {"Stereo1 ADC L2 Mux", "DAC MIX", "Stereo1 DAC MIXL"}, 1826 1827 {"Stereo1 ADC R1 Mux", "ADC", "Stereo1 ADC R Mux"}, 1828 {"Stereo1 ADC R1 Mux", "DAC MIX", "Stereo1 DAC MIXR"}, 1829 {"Stereo1 ADC R2 Mux", "DMIC", "DMIC R1"}, 1830 {"Stereo1 ADC R2 Mux", "DAC MIX", "Stereo1 DAC MIXR"}, 1831 1832 {"Stereo1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC L1 Mux"}, 1833 {"Stereo1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC L2 Mux"}, 1834 {"Stereo1 ADC MIXL", NULL, "ADC Stereo1 Filter"}, 1835 1836 {"Stereo1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC R1 Mux"}, 1837 {"Stereo1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC R2 Mux"}, 1838 {"Stereo1 ADC MIXR", NULL, "ADC Stereo1 Filter"}, 1839 1840 {"ADC Stereo1 Filter", NULL, "BTN Detection Mode"}, 1841 1842 {"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXL"}, 1843 {"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXR"}, 1844 1845 {"IF1 01 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"}, 1846 {"IF1 01 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"}, 1847 {"IF1 01 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"}, 1848 {"IF1 01 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"}, 1849 {"IF1 23 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"}, 1850 {"IF1 23 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"}, 1851 {"IF1 23 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"}, 1852 {"IF1 23 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"}, 1853 {"IF1 45 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"}, 1854 {"IF1 45 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"}, 1855 {"IF1 45 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"}, 1856 {"IF1 45 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"}, 1857 {"IF1 67 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"}, 1858 {"IF1 67 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"}, 1859 {"IF1 67 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"}, 1860 {"IF1 67 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"}, 1861 1862 {"IF1_ADC Mux", "Slot 0", "IF1 01 ADC Swap Mux"}, 1863 {"IF1_ADC Mux", "Slot 2", "IF1 23 ADC Swap Mux"}, 1864 {"IF1_ADC Mux", "Slot 4", "IF1 45 ADC Swap Mux"}, 1865 {"IF1_ADC Mux", "Slot 6", "IF1 67 ADC Swap Mux"}, 1866 {"IF1_ADC Mux", NULL, "I2S1"}, 1867 {"ADCDAT Mux", "ADCDAT1", "IF1_ADC Mux"}, 1868 {"AIF1TX", NULL, "ADCDAT Mux"}, 1869 {"IF2 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"}, 1870 {"IF2 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"}, 1871 {"IF2 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"}, 1872 {"IF2 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"}, 1873 {"ADCDAT Mux", "ADCDAT2", "IF2 ADC Swap Mux"}, 1874 {"AIF2TX", NULL, "ADCDAT Mux"}, 1875 1876 {"IF1 DAC1 L", NULL, "AIF1RX"}, 1877 {"IF1 DAC1 L", NULL, "I2S1"}, 1878 {"IF1 DAC1 L", NULL, "DAC Stereo1 Filter"}, 1879 {"IF1 DAC1 R", NULL, "AIF1RX"}, 1880 {"IF1 DAC1 R", NULL, "I2S1"}, 1881 {"IF1 DAC1 R", NULL, "DAC Stereo1 Filter"}, 1882 1883 {"DAC1 MIXL", "Stereo ADC Switch", "Stereo1 ADC MIXL"}, 1884 {"DAC1 MIXL", "DAC1 Switch", "IF1 DAC1 L"}, 1885 {"DAC1 MIXR", "Stereo ADC Switch", "Stereo1 ADC MIXR"}, 1886 {"DAC1 MIXR", "DAC1 Switch", "IF1 DAC1 R"}, 1887 1888 {"Stereo1 DAC MIXL", "DAC L1 Switch", "DAC1 MIXL"}, 1889 {"Stereo1 DAC MIXL", "DAC R1 Switch", "DAC1 MIXR"}, 1890 1891 {"Stereo1 DAC MIXR", "DAC R1 Switch", "DAC1 MIXR"}, 1892 {"Stereo1 DAC MIXR", "DAC L1 Switch", "DAC1 MIXL"}, 1893 1894 {"DAC L1 Source", "DAC1", "DAC1 MIXL"}, 1895 {"DAC L1 Source", "Stereo1 DAC Mixer", "Stereo1 DAC MIXL"}, 1896 {"DAC R1 Source", "DAC1", "DAC1 MIXR"}, 1897 {"DAC R1 Source", "Stereo1 DAC Mixer", "Stereo1 DAC MIXR"}, 1898 1899 {"DAC L1", NULL, "DAC L1 Source"}, 1900 {"DAC R1", NULL, "DAC R1 Source"}, 1901 1902 {"DAC L1", NULL, "DAC 1 Clock"}, 1903 {"DAC R1", NULL, "DAC 1 Clock"}, 1904 1905 {"HP Amp", NULL, "DAC L1"}, 1906 {"HP Amp", NULL, "DAC R1"}, 1907 {"HP Amp", NULL, "HP Amp L"}, 1908 {"HP Amp", NULL, "HP Amp R"}, 1909 {"HP Amp", NULL, "Capless"}, 1910 {"HP Amp", NULL, "Charge Pump"}, 1911 {"HP Amp", NULL, "CLKDET SYS"}, 1912 {"HP Amp", NULL, "Vref1"}, 1913 {"HPOL Playback", "Switch", "HP Amp"}, 1914 {"HPOR Playback", "Switch", "HP Amp"}, 1915 {"HPOL", NULL, "HPOL Playback"}, 1916 {"HPOR", NULL, "HPOR Playback"}, 1917 }; 1918 1919 static int rt5682_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask, 1920 unsigned int rx_mask, int slots, int slot_width) 1921 { 1922 struct snd_soc_component *component = dai->component; 1923 unsigned int cl, val = 0; 1924 1925 if (tx_mask || rx_mask) 1926 snd_soc_component_update_bits(component, RT5682_TDM_ADDA_CTRL_2, 1927 RT5682_TDM_EN, RT5682_TDM_EN); 1928 else 1929 snd_soc_component_update_bits(component, RT5682_TDM_ADDA_CTRL_2, 1930 RT5682_TDM_EN, 0); 1931 1932 switch (slots) { 1933 case 4: 1934 val |= RT5682_TDM_TX_CH_4; 1935 val |= RT5682_TDM_RX_CH_4; 1936 break; 1937 case 6: 1938 val |= RT5682_TDM_TX_CH_6; 1939 val |= RT5682_TDM_RX_CH_6; 1940 break; 1941 case 8: 1942 val |= RT5682_TDM_TX_CH_8; 1943 val |= RT5682_TDM_RX_CH_8; 1944 break; 1945 case 2: 1946 break; 1947 default: 1948 return -EINVAL; 1949 } 1950 1951 snd_soc_component_update_bits(component, RT5682_TDM_CTRL, 1952 RT5682_TDM_TX_CH_MASK | RT5682_TDM_RX_CH_MASK, val); 1953 1954 switch (slot_width) { 1955 case 8: 1956 if (tx_mask || rx_mask) 1957 return -EINVAL; 1958 cl = RT5682_I2S1_TX_CHL_8 | RT5682_I2S1_RX_CHL_8; 1959 break; 1960 case 16: 1961 val = RT5682_TDM_CL_16; 1962 cl = RT5682_I2S1_TX_CHL_16 | RT5682_I2S1_RX_CHL_16; 1963 break; 1964 case 20: 1965 val = RT5682_TDM_CL_20; 1966 cl = RT5682_I2S1_TX_CHL_20 | RT5682_I2S1_RX_CHL_20; 1967 break; 1968 case 24: 1969 val = RT5682_TDM_CL_24; 1970 cl = RT5682_I2S1_TX_CHL_24 | RT5682_I2S1_RX_CHL_24; 1971 break; 1972 case 32: 1973 val = RT5682_TDM_CL_32; 1974 cl = RT5682_I2S1_TX_CHL_32 | RT5682_I2S1_RX_CHL_32; 1975 break; 1976 default: 1977 return -EINVAL; 1978 } 1979 1980 snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL, 1981 RT5682_TDM_CL_MASK, val); 1982 snd_soc_component_update_bits(component, RT5682_I2S1_SDP, 1983 RT5682_I2S1_TX_CHL_MASK | RT5682_I2S1_RX_CHL_MASK, cl); 1984 1985 return 0; 1986 } 1987 1988 1989 static int rt5682_hw_params(struct snd_pcm_substream *substream, 1990 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) 1991 { 1992 struct snd_soc_component *component = dai->component; 1993 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 1994 unsigned int len_1 = 0, len_2 = 0; 1995 int pre_div, frame_size; 1996 1997 rt5682->lrck[dai->id] = params_rate(params); 1998 pre_div = rl6231_get_clk_info(rt5682->sysclk, rt5682->lrck[dai->id]); 1999 2000 frame_size = snd_soc_params_to_frame_size(params); 2001 if (frame_size < 0) { 2002 dev_err(component->dev, "Unsupported frame size: %d\n", 2003 frame_size); 2004 return -EINVAL; 2005 } 2006 2007 dev_dbg(dai->dev, "lrck is %dHz and pre_div is %d for iis %d\n", 2008 rt5682->lrck[dai->id], pre_div, dai->id); 2009 2010 switch (params_width(params)) { 2011 case 16: 2012 break; 2013 case 20: 2014 len_1 |= RT5682_I2S1_DL_20; 2015 len_2 |= RT5682_I2S2_DL_20; 2016 break; 2017 case 24: 2018 len_1 |= RT5682_I2S1_DL_24; 2019 len_2 |= RT5682_I2S2_DL_24; 2020 break; 2021 case 32: 2022 len_1 |= RT5682_I2S1_DL_32; 2023 len_2 |= RT5682_I2S2_DL_24; 2024 break; 2025 case 8: 2026 len_1 |= RT5682_I2S2_DL_8; 2027 len_2 |= RT5682_I2S2_DL_8; 2028 break; 2029 default: 2030 return -EINVAL; 2031 } 2032 2033 switch (dai->id) { 2034 case RT5682_AIF1: 2035 snd_soc_component_update_bits(component, RT5682_I2S1_SDP, 2036 RT5682_I2S1_DL_MASK, len_1); 2037 if (rt5682->master[RT5682_AIF1]) { 2038 snd_soc_component_update_bits(component, 2039 RT5682_ADDA_CLK_1, RT5682_I2S_M_DIV_MASK, 2040 pre_div << RT5682_I2S_M_DIV_SFT); 2041 } 2042 if (params_channels(params) == 1) /* mono mode */ 2043 snd_soc_component_update_bits(component, 2044 RT5682_I2S1_SDP, RT5682_I2S1_MONO_MASK, 2045 RT5682_I2S1_MONO_EN); 2046 else 2047 snd_soc_component_update_bits(component, 2048 RT5682_I2S1_SDP, RT5682_I2S1_MONO_MASK, 2049 RT5682_I2S1_MONO_DIS); 2050 break; 2051 case RT5682_AIF2: 2052 snd_soc_component_update_bits(component, RT5682_I2S2_SDP, 2053 RT5682_I2S2_DL_MASK, len_2); 2054 if (rt5682->master[RT5682_AIF2]) { 2055 snd_soc_component_update_bits(component, 2056 RT5682_I2S_M_CLK_CTRL_1, RT5682_I2S2_M_PD_MASK, 2057 pre_div << RT5682_I2S2_M_PD_SFT); 2058 } 2059 if (params_channels(params) == 1) /* mono mode */ 2060 snd_soc_component_update_bits(component, 2061 RT5682_I2S2_SDP, RT5682_I2S2_MONO_MASK, 2062 RT5682_I2S2_MONO_EN); 2063 else 2064 snd_soc_component_update_bits(component, 2065 RT5682_I2S2_SDP, RT5682_I2S2_MONO_MASK, 2066 RT5682_I2S2_MONO_DIS); 2067 break; 2068 default: 2069 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id); 2070 return -EINVAL; 2071 } 2072 2073 return 0; 2074 } 2075 2076 static int rt5682_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) 2077 { 2078 struct snd_soc_component *component = dai->component; 2079 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 2080 unsigned int reg_val = 0, tdm_ctrl = 0; 2081 2082 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 2083 case SND_SOC_DAIFMT_CBM_CFM: 2084 rt5682->master[dai->id] = 1; 2085 break; 2086 case SND_SOC_DAIFMT_CBS_CFS: 2087 rt5682->master[dai->id] = 0; 2088 break; 2089 default: 2090 return -EINVAL; 2091 } 2092 2093 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 2094 case SND_SOC_DAIFMT_NB_NF: 2095 break; 2096 case SND_SOC_DAIFMT_IB_NF: 2097 reg_val |= RT5682_I2S_BP_INV; 2098 tdm_ctrl |= RT5682_TDM_S_BP_INV; 2099 break; 2100 case SND_SOC_DAIFMT_NB_IF: 2101 if (dai->id == RT5682_AIF1) 2102 tdm_ctrl |= RT5682_TDM_S_LP_INV | RT5682_TDM_M_BP_INV; 2103 else 2104 return -EINVAL; 2105 break; 2106 case SND_SOC_DAIFMT_IB_IF: 2107 if (dai->id == RT5682_AIF1) 2108 tdm_ctrl |= RT5682_TDM_S_BP_INV | RT5682_TDM_S_LP_INV | 2109 RT5682_TDM_M_BP_INV | RT5682_TDM_M_LP_INV; 2110 else 2111 return -EINVAL; 2112 break; 2113 default: 2114 return -EINVAL; 2115 } 2116 2117 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 2118 case SND_SOC_DAIFMT_I2S: 2119 break; 2120 case SND_SOC_DAIFMT_LEFT_J: 2121 reg_val |= RT5682_I2S_DF_LEFT; 2122 tdm_ctrl |= RT5682_TDM_DF_LEFT; 2123 break; 2124 case SND_SOC_DAIFMT_DSP_A: 2125 reg_val |= RT5682_I2S_DF_PCM_A; 2126 tdm_ctrl |= RT5682_TDM_DF_PCM_A; 2127 break; 2128 case SND_SOC_DAIFMT_DSP_B: 2129 reg_val |= RT5682_I2S_DF_PCM_B; 2130 tdm_ctrl |= RT5682_TDM_DF_PCM_B; 2131 break; 2132 default: 2133 return -EINVAL; 2134 } 2135 2136 switch (dai->id) { 2137 case RT5682_AIF1: 2138 snd_soc_component_update_bits(component, RT5682_I2S1_SDP, 2139 RT5682_I2S_DF_MASK, reg_val); 2140 snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL, 2141 RT5682_TDM_MS_MASK | RT5682_TDM_S_BP_MASK | 2142 RT5682_TDM_DF_MASK | RT5682_TDM_M_BP_MASK | 2143 RT5682_TDM_M_LP_MASK | RT5682_TDM_S_LP_MASK, 2144 tdm_ctrl | rt5682->master[dai->id]); 2145 break; 2146 case RT5682_AIF2: 2147 if (rt5682->master[dai->id] == 0) 2148 reg_val |= RT5682_I2S2_MS_S; 2149 snd_soc_component_update_bits(component, RT5682_I2S2_SDP, 2150 RT5682_I2S2_MS_MASK | RT5682_I2S_BP_MASK | 2151 RT5682_I2S_DF_MASK, reg_val); 2152 break; 2153 default: 2154 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id); 2155 return -EINVAL; 2156 } 2157 return 0; 2158 } 2159 2160 static int rt5682_set_component_sysclk(struct snd_soc_component *component, 2161 int clk_id, int source, unsigned int freq, int dir) 2162 { 2163 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 2164 unsigned int reg_val = 0, src = 0; 2165 2166 if (freq == rt5682->sysclk && clk_id == rt5682->sysclk_src) 2167 return 0; 2168 2169 switch (clk_id) { 2170 case RT5682_SCLK_S_MCLK: 2171 reg_val |= RT5682_SCLK_SRC_MCLK; 2172 src = RT5682_CLK_SRC_MCLK; 2173 break; 2174 case RT5682_SCLK_S_PLL1: 2175 reg_val |= RT5682_SCLK_SRC_PLL1; 2176 src = RT5682_CLK_SRC_PLL1; 2177 break; 2178 case RT5682_SCLK_S_PLL2: 2179 reg_val |= RT5682_SCLK_SRC_PLL2; 2180 src = RT5682_CLK_SRC_PLL2; 2181 break; 2182 case RT5682_SCLK_S_RCCLK: 2183 reg_val |= RT5682_SCLK_SRC_RCCLK; 2184 src = RT5682_CLK_SRC_RCCLK; 2185 break; 2186 default: 2187 dev_err(component->dev, "Invalid clock id (%d)\n", clk_id); 2188 return -EINVAL; 2189 } 2190 snd_soc_component_update_bits(component, RT5682_GLB_CLK, 2191 RT5682_SCLK_SRC_MASK, reg_val); 2192 2193 if (rt5682->master[RT5682_AIF2]) { 2194 snd_soc_component_update_bits(component, 2195 RT5682_I2S_M_CLK_CTRL_1, RT5682_I2S2_SRC_MASK, 2196 src << RT5682_I2S2_SRC_SFT); 2197 } 2198 2199 rt5682->sysclk = freq; 2200 rt5682->sysclk_src = clk_id; 2201 2202 dev_dbg(component->dev, "Sysclk is %dHz and clock id is %d\n", 2203 freq, clk_id); 2204 2205 return 0; 2206 } 2207 2208 static int rt5682_set_component_pll(struct snd_soc_component *component, 2209 int pll_id, int source, unsigned int freq_in, 2210 unsigned int freq_out) 2211 { 2212 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 2213 struct rl6231_pll_code pll_code; 2214 int ret; 2215 2216 if (source == rt5682->pll_src && freq_in == rt5682->pll_in && 2217 freq_out == rt5682->pll_out) 2218 return 0; 2219 2220 if (!freq_in || !freq_out) { 2221 dev_dbg(component->dev, "PLL disabled\n"); 2222 2223 rt5682->pll_in = 0; 2224 rt5682->pll_out = 0; 2225 snd_soc_component_update_bits(component, RT5682_GLB_CLK, 2226 RT5682_SCLK_SRC_MASK, RT5682_SCLK_SRC_MCLK); 2227 return 0; 2228 } 2229 2230 switch (source) { 2231 case RT5682_PLL1_S_MCLK: 2232 snd_soc_component_update_bits(component, RT5682_GLB_CLK, 2233 RT5682_PLL1_SRC_MASK, RT5682_PLL1_SRC_MCLK); 2234 break; 2235 case RT5682_PLL1_S_BCLK1: 2236 snd_soc_component_update_bits(component, RT5682_GLB_CLK, 2237 RT5682_PLL1_SRC_MASK, RT5682_PLL1_SRC_BCLK1); 2238 break; 2239 default: 2240 dev_err(component->dev, "Unknown PLL Source %d\n", source); 2241 return -EINVAL; 2242 } 2243 2244 ret = rl6231_pll_calc(freq_in, freq_out, &pll_code); 2245 if (ret < 0) { 2246 dev_err(component->dev, "Unsupport input clock %d\n", freq_in); 2247 return ret; 2248 } 2249 2250 dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n", 2251 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code), 2252 pll_code.n_code, pll_code.k_code); 2253 2254 snd_soc_component_write(component, RT5682_PLL_CTRL_1, 2255 pll_code.n_code << RT5682_PLL_N_SFT | pll_code.k_code); 2256 snd_soc_component_write(component, RT5682_PLL_CTRL_2, 2257 (pll_code.m_bp ? 0 : pll_code.m_code) << RT5682_PLL_M_SFT | 2258 pll_code.m_bp << RT5682_PLL_M_BP_SFT | RT5682_PLL_RST); 2259 2260 rt5682->pll_in = freq_in; 2261 rt5682->pll_out = freq_out; 2262 rt5682->pll_src = source; 2263 2264 return 0; 2265 } 2266 2267 static int rt5682_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio) 2268 { 2269 struct snd_soc_component *component = dai->component; 2270 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 2271 2272 rt5682->bclk[dai->id] = ratio; 2273 2274 switch (ratio) { 2275 case 64: 2276 snd_soc_component_update_bits(component, RT5682_ADDA_CLK_2, 2277 RT5682_I2S2_BCLK_MS2_MASK, 2278 RT5682_I2S2_BCLK_MS2_64); 2279 break; 2280 case 32: 2281 snd_soc_component_update_bits(component, RT5682_ADDA_CLK_2, 2282 RT5682_I2S2_BCLK_MS2_MASK, 2283 RT5682_I2S2_BCLK_MS2_32); 2284 break; 2285 default: 2286 dev_err(dai->dev, "Invalid bclk ratio %d\n", ratio); 2287 return -EINVAL; 2288 } 2289 2290 return 0; 2291 } 2292 2293 static int rt5682_set_bias_level(struct snd_soc_component *component, 2294 enum snd_soc_bias_level level) 2295 { 2296 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 2297 2298 switch (level) { 2299 case SND_SOC_BIAS_PREPARE: 2300 regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_1, 2301 RT5682_PWR_BG, RT5682_PWR_BG); 2302 regmap_update_bits(rt5682->regmap, RT5682_PWR_DIG_1, 2303 RT5682_DIG_GATE_CTRL | RT5682_PWR_LDO, 2304 RT5682_DIG_GATE_CTRL | RT5682_PWR_LDO); 2305 break; 2306 2307 case SND_SOC_BIAS_STANDBY: 2308 regmap_update_bits(rt5682->regmap, RT5682_PWR_DIG_1, 2309 RT5682_DIG_GATE_CTRL, RT5682_DIG_GATE_CTRL); 2310 break; 2311 case SND_SOC_BIAS_OFF: 2312 regmap_update_bits(rt5682->regmap, RT5682_PWR_DIG_1, 2313 RT5682_DIG_GATE_CTRL | RT5682_PWR_LDO, 0); 2314 regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_1, 2315 RT5682_PWR_BG, 0); 2316 break; 2317 2318 default: 2319 break; 2320 } 2321 2322 return 0; 2323 } 2324 2325 static int rt5682_probe(struct snd_soc_component *component) 2326 { 2327 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 2328 2329 rt5682->component = component; 2330 2331 return 0; 2332 } 2333 2334 static void rt5682_remove(struct snd_soc_component *component) 2335 { 2336 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 2337 2338 rt5682_reset(rt5682->regmap); 2339 } 2340 2341 #ifdef CONFIG_PM 2342 static int rt5682_suspend(struct snd_soc_component *component) 2343 { 2344 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 2345 2346 regcache_cache_only(rt5682->regmap, true); 2347 regcache_mark_dirty(rt5682->regmap); 2348 return 0; 2349 } 2350 2351 static int rt5682_resume(struct snd_soc_component *component) 2352 { 2353 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 2354 2355 regcache_cache_only(rt5682->regmap, false); 2356 regcache_sync(rt5682->regmap); 2357 2358 rt5682_irq(0, rt5682); 2359 2360 return 0; 2361 } 2362 #else 2363 #define rt5682_suspend NULL 2364 #define rt5682_resume NULL 2365 #endif 2366 2367 #define RT5682_STEREO_RATES SNDRV_PCM_RATE_8000_192000 2368 #define RT5682_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ 2369 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8) 2370 2371 static const struct snd_soc_dai_ops rt5682_aif1_dai_ops = { 2372 .hw_params = rt5682_hw_params, 2373 .set_fmt = rt5682_set_dai_fmt, 2374 .set_tdm_slot = rt5682_set_tdm_slot, 2375 }; 2376 2377 static const struct snd_soc_dai_ops rt5682_aif2_dai_ops = { 2378 .hw_params = rt5682_hw_params, 2379 .set_fmt = rt5682_set_dai_fmt, 2380 .set_bclk_ratio = rt5682_set_bclk_ratio, 2381 }; 2382 2383 static struct snd_soc_dai_driver rt5682_dai[] = { 2384 { 2385 .name = "rt5682-aif1", 2386 .id = RT5682_AIF1, 2387 .playback = { 2388 .stream_name = "AIF1 Playback", 2389 .channels_min = 1, 2390 .channels_max = 2, 2391 .rates = RT5682_STEREO_RATES, 2392 .formats = RT5682_FORMATS, 2393 }, 2394 .capture = { 2395 .stream_name = "AIF1 Capture", 2396 .channels_min = 1, 2397 .channels_max = 2, 2398 .rates = RT5682_STEREO_RATES, 2399 .formats = RT5682_FORMATS, 2400 }, 2401 .ops = &rt5682_aif1_dai_ops, 2402 }, 2403 { 2404 .name = "rt5682-aif2", 2405 .id = RT5682_AIF2, 2406 .capture = { 2407 .stream_name = "AIF2 Capture", 2408 .channels_min = 1, 2409 .channels_max = 2, 2410 .rates = RT5682_STEREO_RATES, 2411 .formats = RT5682_FORMATS, 2412 }, 2413 .ops = &rt5682_aif2_dai_ops, 2414 }, 2415 }; 2416 2417 static const struct snd_soc_component_driver soc_component_dev_rt5682 = { 2418 .probe = rt5682_probe, 2419 .remove = rt5682_remove, 2420 .suspend = rt5682_suspend, 2421 .resume = rt5682_resume, 2422 .set_bias_level = rt5682_set_bias_level, 2423 .controls = rt5682_snd_controls, 2424 .num_controls = ARRAY_SIZE(rt5682_snd_controls), 2425 .dapm_widgets = rt5682_dapm_widgets, 2426 .num_dapm_widgets = ARRAY_SIZE(rt5682_dapm_widgets), 2427 .dapm_routes = rt5682_dapm_routes, 2428 .num_dapm_routes = ARRAY_SIZE(rt5682_dapm_routes), 2429 .set_sysclk = rt5682_set_component_sysclk, 2430 .set_pll = rt5682_set_component_pll, 2431 .set_jack = rt5682_set_jack_detect, 2432 .use_pmdown_time = 1, 2433 .endianness = 1, 2434 .non_legacy_dai_naming = 1, 2435 }; 2436 2437 static const struct regmap_config rt5682_regmap = { 2438 .reg_bits = 16, 2439 .val_bits = 16, 2440 .max_register = RT5682_I2C_MODE, 2441 .volatile_reg = rt5682_volatile_register, 2442 .readable_reg = rt5682_readable_register, 2443 .cache_type = REGCACHE_RBTREE, 2444 .reg_defaults = rt5682_reg, 2445 .num_reg_defaults = ARRAY_SIZE(rt5682_reg), 2446 .use_single_read = true, 2447 .use_single_write = true, 2448 }; 2449 2450 static const struct i2c_device_id rt5682_i2c_id[] = { 2451 {"rt5682", 0}, 2452 {} 2453 }; 2454 MODULE_DEVICE_TABLE(i2c, rt5682_i2c_id); 2455 2456 static int rt5682_parse_dt(struct rt5682_priv *rt5682, struct device *dev) 2457 { 2458 2459 device_property_read_u32(dev, "realtek,dmic1-data-pin", 2460 &rt5682->pdata.dmic1_data_pin); 2461 device_property_read_u32(dev, "realtek,dmic1-clk-pin", 2462 &rt5682->pdata.dmic1_clk_pin); 2463 device_property_read_u32(dev, "realtek,jd-src", 2464 &rt5682->pdata.jd_src); 2465 2466 rt5682->pdata.ldo1_en = of_get_named_gpio(dev->of_node, 2467 "realtek,ldo1-en-gpios", 0); 2468 2469 return 0; 2470 } 2471 2472 static void rt5682_calibrate(struct rt5682_priv *rt5682) 2473 { 2474 int value, count; 2475 2476 mutex_lock(&rt5682->calibrate_mutex); 2477 2478 rt5682_reset(rt5682->regmap); 2479 regmap_write(rt5682->regmap, RT5682_PWR_ANLG_1, 0xa2af); 2480 usleep_range(15000, 20000); 2481 regmap_write(rt5682->regmap, RT5682_PWR_ANLG_1, 0xf2af); 2482 regmap_write(rt5682->regmap, RT5682_MICBIAS_2, 0x0300); 2483 regmap_write(rt5682->regmap, RT5682_GLB_CLK, 0x8000); 2484 regmap_write(rt5682->regmap, RT5682_PWR_DIG_1, 0x0100); 2485 regmap_write(rt5682->regmap, RT5682_HP_IMP_SENS_CTRL_19, 0x3800); 2486 regmap_write(rt5682->regmap, RT5682_CHOP_DAC, 0x3000); 2487 regmap_write(rt5682->regmap, RT5682_CALIB_ADC_CTRL, 0x7005); 2488 regmap_write(rt5682->regmap, RT5682_STO1_ADC_MIXER, 0x686c); 2489 regmap_write(rt5682->regmap, RT5682_CAL_REC, 0x0d0d); 2490 regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_2, 0x0321); 2491 regmap_write(rt5682->regmap, RT5682_HP_LOGIC_CTRL_2, 0x0004); 2492 regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_1, 0x7c00); 2493 regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_3, 0x06a1); 2494 regmap_write(rt5682->regmap, RT5682_A_DAC1_MUX, 0x0311); 2495 regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_1, 0x7c00); 2496 2497 regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_1, 0xfc00); 2498 2499 for (count = 0; count < 60; count++) { 2500 regmap_read(rt5682->regmap, RT5682_HP_CALIB_STA_1, &value); 2501 if (!(value & 0x8000)) 2502 break; 2503 2504 usleep_range(10000, 10005); 2505 } 2506 2507 if (count >= 60) 2508 pr_err("HP Calibration Failure\n"); 2509 2510 /* restore settings */ 2511 regmap_write(rt5682->regmap, RT5682_PWR_ANLG_1, 0x02af); 2512 regmap_write(rt5682->regmap, RT5682_MICBIAS_2, 0x0080); 2513 regmap_write(rt5682->regmap, RT5682_GLB_CLK, 0x0000); 2514 regmap_write(rt5682->regmap, RT5682_PWR_DIG_1, 0x0000); 2515 regmap_write(rt5682->regmap, RT5682_CHOP_DAC, 0x2000); 2516 regmap_write(rt5682->regmap, RT5682_CALIB_ADC_CTRL, 0x2005); 2517 regmap_write(rt5682->regmap, RT5682_STO1_ADC_MIXER, 0xc0c4); 2518 2519 mutex_unlock(&rt5682->calibrate_mutex); 2520 2521 } 2522 2523 static int rt5682_i2c_probe(struct i2c_client *i2c, 2524 const struct i2c_device_id *id) 2525 { 2526 struct rt5682_platform_data *pdata = dev_get_platdata(&i2c->dev); 2527 struct rt5682_priv *rt5682; 2528 int i, ret; 2529 unsigned int val; 2530 2531 rt5682 = devm_kzalloc(&i2c->dev, sizeof(struct rt5682_priv), 2532 GFP_KERNEL); 2533 2534 if (rt5682 == NULL) 2535 return -ENOMEM; 2536 2537 i2c_set_clientdata(i2c, rt5682); 2538 2539 rt5682->pdata = i2s_default_platform_data; 2540 2541 if (pdata) 2542 rt5682->pdata = *pdata; 2543 else 2544 rt5682_parse_dt(rt5682, &i2c->dev); 2545 2546 rt5682->regmap = devm_regmap_init_i2c(i2c, &rt5682_regmap); 2547 if (IS_ERR(rt5682->regmap)) { 2548 ret = PTR_ERR(rt5682->regmap); 2549 dev_err(&i2c->dev, "Failed to allocate register map: %d\n", 2550 ret); 2551 return ret; 2552 } 2553 2554 for (i = 0; i < ARRAY_SIZE(rt5682->supplies); i++) 2555 rt5682->supplies[i].supply = rt5682_supply_names[i]; 2556 2557 ret = devm_regulator_bulk_get(&i2c->dev, ARRAY_SIZE(rt5682->supplies), 2558 rt5682->supplies); 2559 if (ret != 0) { 2560 dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret); 2561 return ret; 2562 } 2563 2564 ret = regulator_bulk_enable(ARRAY_SIZE(rt5682->supplies), 2565 rt5682->supplies); 2566 if (ret != 0) { 2567 dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret); 2568 return ret; 2569 } 2570 2571 if (gpio_is_valid(rt5682->pdata.ldo1_en)) { 2572 if (devm_gpio_request_one(&i2c->dev, rt5682->pdata.ldo1_en, 2573 GPIOF_OUT_INIT_HIGH, "rt5682")) 2574 dev_err(&i2c->dev, "Fail gpio_request gpio_ldo\n"); 2575 } 2576 2577 /* Sleep for 300 ms miniumum */ 2578 usleep_range(300000, 350000); 2579 2580 regmap_write(rt5682->regmap, RT5682_I2C_MODE, 0x1); 2581 usleep_range(10000, 15000); 2582 2583 regmap_read(rt5682->regmap, RT5682_DEVICE_ID, &val); 2584 if (val != DEVICE_ID) { 2585 pr_err("Device with ID register %x is not rt5682\n", val); 2586 return -ENODEV; 2587 } 2588 2589 rt5682_reset(rt5682->regmap); 2590 2591 rt5682_calibrate(rt5682); 2592 2593 ret = regmap_multi_reg_write(rt5682->regmap, patch_list, 2594 ARRAY_SIZE(patch_list)); 2595 if (ret != 0) 2596 dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret); 2597 2598 regmap_write(rt5682->regmap, RT5682_DEPOP_1, 0x0000); 2599 2600 /* DMIC pin*/ 2601 if (rt5682->pdata.dmic1_data_pin != RT5682_DMIC1_NULL) { 2602 switch (rt5682->pdata.dmic1_data_pin) { 2603 case RT5682_DMIC1_DATA_GPIO2: /* share with LRCK2 */ 2604 regmap_update_bits(rt5682->regmap, RT5682_DMIC_CTRL_1, 2605 RT5682_DMIC_1_DP_MASK, RT5682_DMIC_1_DP_GPIO2); 2606 regmap_update_bits(rt5682->regmap, RT5682_GPIO_CTRL_1, 2607 RT5682_GP2_PIN_MASK, RT5682_GP2_PIN_DMIC_SDA); 2608 break; 2609 2610 case RT5682_DMIC1_DATA_GPIO5: /* share with DACDAT1 */ 2611 regmap_update_bits(rt5682->regmap, RT5682_DMIC_CTRL_1, 2612 RT5682_DMIC_1_DP_MASK, RT5682_DMIC_1_DP_GPIO5); 2613 regmap_update_bits(rt5682->regmap, RT5682_GPIO_CTRL_1, 2614 RT5682_GP5_PIN_MASK, RT5682_GP5_PIN_DMIC_SDA); 2615 break; 2616 2617 default: 2618 dev_warn(&i2c->dev, "invalid DMIC_DAT pin\n"); 2619 break; 2620 } 2621 2622 switch (rt5682->pdata.dmic1_clk_pin) { 2623 case RT5682_DMIC1_CLK_GPIO1: /* share with IRQ */ 2624 regmap_update_bits(rt5682->regmap, RT5682_GPIO_CTRL_1, 2625 RT5682_GP1_PIN_MASK, RT5682_GP1_PIN_DMIC_CLK); 2626 break; 2627 2628 case RT5682_DMIC1_CLK_GPIO3: /* share with BCLK2 */ 2629 regmap_update_bits(rt5682->regmap, RT5682_GPIO_CTRL_1, 2630 RT5682_GP3_PIN_MASK, RT5682_GP3_PIN_DMIC_CLK); 2631 break; 2632 2633 default: 2634 dev_warn(&i2c->dev, "invalid DMIC_CLK pin\n"); 2635 break; 2636 } 2637 } 2638 2639 regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_1, 2640 RT5682_LDO1_DVO_MASK | RT5682_HP_DRIVER_MASK, 2641 RT5682_LDO1_DVO_12 | RT5682_HP_DRIVER_5X); 2642 regmap_write(rt5682->regmap, RT5682_MICBIAS_2, 0x0380); 2643 regmap_update_bits(rt5682->regmap, RT5682_GPIO_CTRL_1, 2644 RT5682_GP4_PIN_MASK | RT5682_GP5_PIN_MASK, 2645 RT5682_GP4_PIN_ADCDAT1 | RT5682_GP5_PIN_DACDAT1); 2646 regmap_write(rt5682->regmap, RT5682_TEST_MODE_CTRL_1, 0x0000); 2647 regmap_update_bits(rt5682->regmap, RT5682_BIAS_CUR_CTRL_8, 2648 RT5682_HPA_CP_BIAS_CTRL_MASK, RT5682_HPA_CP_BIAS_3UA); 2649 regmap_update_bits(rt5682->regmap, RT5682_CHARGE_PUMP_1, 2650 RT5682_CP_CLK_HP_MASK, RT5682_CP_CLK_HP_300KHZ); 2651 2652 INIT_DELAYED_WORK(&rt5682->jack_detect_work, 2653 rt5682_jack_detect_handler); 2654 INIT_DELAYED_WORK(&rt5682->jd_check_work, 2655 rt5682_jd_check_handler); 2656 2657 mutex_init(&rt5682->calibrate_mutex); 2658 2659 if (i2c->irq) { 2660 ret = devm_request_threaded_irq(&i2c->dev, i2c->irq, NULL, 2661 rt5682_irq, IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING 2662 | IRQF_ONESHOT, "rt5682", rt5682); 2663 if (ret) 2664 dev_err(&i2c->dev, "Failed to reguest IRQ: %d\n", ret); 2665 2666 } 2667 2668 return snd_soc_register_component(&i2c->dev, &soc_component_dev_rt5682, 2669 rt5682_dai, ARRAY_SIZE(rt5682_dai)); 2670 } 2671 2672 static int rt5682_i2c_remove(struct i2c_client *i2c) 2673 { 2674 snd_soc_unregister_component(&i2c->dev); 2675 2676 return 0; 2677 } 2678 2679 static void rt5682_i2c_shutdown(struct i2c_client *client) 2680 { 2681 struct rt5682_priv *rt5682 = i2c_get_clientdata(client); 2682 2683 rt5682_reset(rt5682->regmap); 2684 } 2685 2686 #ifdef CONFIG_OF 2687 static const struct of_device_id rt5682_of_match[] = { 2688 {.compatible = "realtek,rt5682i"}, 2689 {}, 2690 }; 2691 MODULE_DEVICE_TABLE(of, rt5682_of_match); 2692 #endif 2693 2694 #ifdef CONFIG_ACPI 2695 static const struct acpi_device_id rt5682_acpi_match[] = { 2696 {"10EC5682", 0,}, 2697 {}, 2698 }; 2699 MODULE_DEVICE_TABLE(acpi, rt5682_acpi_match); 2700 #endif 2701 2702 static struct i2c_driver rt5682_i2c_driver = { 2703 .driver = { 2704 .name = "rt5682", 2705 .of_match_table = of_match_ptr(rt5682_of_match), 2706 .acpi_match_table = ACPI_PTR(rt5682_acpi_match), 2707 }, 2708 .probe = rt5682_i2c_probe, 2709 .remove = rt5682_i2c_remove, 2710 .shutdown = rt5682_i2c_shutdown, 2711 .id_table = rt5682_i2c_id, 2712 }; 2713 module_i2c_driver(rt5682_i2c_driver); 2714 2715 MODULE_DESCRIPTION("ASoC RT5682 driver"); 2716 MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>"); 2717 MODULE_LICENSE("GPL v2"); 2718