1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * rt5677.c -- RT5677 ALSA SoC audio codec driver 4 * 5 * Copyright 2013 Realtek Semiconductor Corp. 6 * Author: Oder Chiou <oder_chiou@realtek.com> 7 */ 8 9 #include <linux/acpi.h> 10 #include <linux/fs.h> 11 #include <linux/module.h> 12 #include <linux/moduleparam.h> 13 #include <linux/init.h> 14 #include <linux/delay.h> 15 #include <linux/pm.h> 16 #include <linux/regmap.h> 17 #include <linux/i2c.h> 18 #include <linux/platform_device.h> 19 #include <linux/spi/spi.h> 20 #include <linux/firmware.h> 21 #include <linux/of_device.h> 22 #include <linux/property.h> 23 #include <linux/irq.h> 24 #include <linux/interrupt.h> 25 #include <linux/irqdomain.h> 26 #include <linux/workqueue.h> 27 #include <sound/core.h> 28 #include <sound/pcm.h> 29 #include <sound/pcm_params.h> 30 #include <sound/soc.h> 31 #include <sound/soc-dapm.h> 32 #include <sound/initval.h> 33 #include <sound/tlv.h> 34 35 #include "rl6231.h" 36 #include "rt5677.h" 37 #include "rt5677-spi.h" 38 39 #define RT5677_DEVICE_ID 0x6327 40 41 #define RT5677_PR_RANGE_BASE (0xff + 1) 42 #define RT5677_PR_SPACING 0x100 43 44 #define RT5677_PR_BASE (RT5677_PR_RANGE_BASE + (0 * RT5677_PR_SPACING)) 45 46 static const struct regmap_range_cfg rt5677_ranges[] = { 47 { 48 .name = "PR", 49 .range_min = RT5677_PR_BASE, 50 .range_max = RT5677_PR_BASE + 0xfd, 51 .selector_reg = RT5677_PRIV_INDEX, 52 .selector_mask = 0xff, 53 .selector_shift = 0x0, 54 .window_start = RT5677_PRIV_DATA, 55 .window_len = 0x1, 56 }, 57 }; 58 59 static const struct reg_sequence init_list[] = { 60 {RT5677_ASRC_12, 0x0018}, 61 {RT5677_PR_BASE + 0x3d, 0x364d}, 62 {RT5677_PR_BASE + 0x17, 0x4fc0}, 63 {RT5677_PR_BASE + 0x13, 0x0312}, 64 {RT5677_PR_BASE + 0x1e, 0x0000}, 65 {RT5677_PR_BASE + 0x12, 0x0eaa}, 66 {RT5677_PR_BASE + 0x14, 0x018a}, 67 {RT5677_PR_BASE + 0x15, 0x0490}, 68 {RT5677_PR_BASE + 0x38, 0x0f71}, 69 {RT5677_PR_BASE + 0x39, 0x0f71}, 70 }; 71 #define RT5677_INIT_REG_LEN ARRAY_SIZE(init_list) 72 73 static const struct reg_default rt5677_reg[] = { 74 {RT5677_RESET , 0x0000}, 75 {RT5677_LOUT1 , 0xa800}, 76 {RT5677_IN1 , 0x0000}, 77 {RT5677_MICBIAS , 0x0000}, 78 {RT5677_SLIMBUS_PARAM , 0x0000}, 79 {RT5677_SLIMBUS_RX , 0x0000}, 80 {RT5677_SLIMBUS_CTRL , 0x0000}, 81 {RT5677_SIDETONE_CTRL , 0x000b}, 82 {RT5677_ANA_DAC1_2_3_SRC , 0x0000}, 83 {RT5677_IF_DSP_DAC3_4_MIXER , 0x1111}, 84 {RT5677_DAC4_DIG_VOL , 0xafaf}, 85 {RT5677_DAC3_DIG_VOL , 0xafaf}, 86 {RT5677_DAC1_DIG_VOL , 0xafaf}, 87 {RT5677_DAC2_DIG_VOL , 0xafaf}, 88 {RT5677_IF_DSP_DAC2_MIXER , 0x0011}, 89 {RT5677_STO1_ADC_DIG_VOL , 0x2f2f}, 90 {RT5677_MONO_ADC_DIG_VOL , 0x2f2f}, 91 {RT5677_STO1_2_ADC_BST , 0x0000}, 92 {RT5677_STO2_ADC_DIG_VOL , 0x2f2f}, 93 {RT5677_ADC_BST_CTRL2 , 0x0000}, 94 {RT5677_STO3_4_ADC_BST , 0x0000}, 95 {RT5677_STO3_ADC_DIG_VOL , 0x2f2f}, 96 {RT5677_STO4_ADC_DIG_VOL , 0x2f2f}, 97 {RT5677_STO4_ADC_MIXER , 0xd4c0}, 98 {RT5677_STO3_ADC_MIXER , 0xd4c0}, 99 {RT5677_STO2_ADC_MIXER , 0xd4c0}, 100 {RT5677_STO1_ADC_MIXER , 0xd4c0}, 101 {RT5677_MONO_ADC_MIXER , 0xd4d1}, 102 {RT5677_ADC_IF_DSP_DAC1_MIXER , 0x8080}, 103 {RT5677_STO1_DAC_MIXER , 0xaaaa}, 104 {RT5677_MONO_DAC_MIXER , 0xaaaa}, 105 {RT5677_DD1_MIXER , 0xaaaa}, 106 {RT5677_DD2_MIXER , 0xaaaa}, 107 {RT5677_IF3_DATA , 0x0000}, 108 {RT5677_IF4_DATA , 0x0000}, 109 {RT5677_PDM_OUT_CTRL , 0x8888}, 110 {RT5677_PDM_DATA_CTRL1 , 0x0000}, 111 {RT5677_PDM_DATA_CTRL2 , 0x0000}, 112 {RT5677_PDM1_DATA_CTRL2 , 0x0000}, 113 {RT5677_PDM1_DATA_CTRL3 , 0x0000}, 114 {RT5677_PDM1_DATA_CTRL4 , 0x0000}, 115 {RT5677_PDM2_DATA_CTRL2 , 0x0000}, 116 {RT5677_PDM2_DATA_CTRL3 , 0x0000}, 117 {RT5677_PDM2_DATA_CTRL4 , 0x0000}, 118 {RT5677_TDM1_CTRL1 , 0x0300}, 119 {RT5677_TDM1_CTRL2 , 0x0000}, 120 {RT5677_TDM1_CTRL3 , 0x4000}, 121 {RT5677_TDM1_CTRL4 , 0x0123}, 122 {RT5677_TDM1_CTRL5 , 0x4567}, 123 {RT5677_TDM2_CTRL1 , 0x0300}, 124 {RT5677_TDM2_CTRL2 , 0x0000}, 125 {RT5677_TDM2_CTRL3 , 0x4000}, 126 {RT5677_TDM2_CTRL4 , 0x0123}, 127 {RT5677_TDM2_CTRL5 , 0x4567}, 128 {RT5677_I2C_MASTER_CTRL1 , 0x0001}, 129 {RT5677_I2C_MASTER_CTRL2 , 0x0000}, 130 {RT5677_I2C_MASTER_CTRL3 , 0x0000}, 131 {RT5677_I2C_MASTER_CTRL4 , 0x0000}, 132 {RT5677_I2C_MASTER_CTRL5 , 0x0000}, 133 {RT5677_I2C_MASTER_CTRL6 , 0x0000}, 134 {RT5677_I2C_MASTER_CTRL7 , 0x0000}, 135 {RT5677_I2C_MASTER_CTRL8 , 0x0000}, 136 {RT5677_DMIC_CTRL1 , 0x1505}, 137 {RT5677_DMIC_CTRL2 , 0x0055}, 138 {RT5677_HAP_GENE_CTRL1 , 0x0111}, 139 {RT5677_HAP_GENE_CTRL2 , 0x0064}, 140 {RT5677_HAP_GENE_CTRL3 , 0xef0e}, 141 {RT5677_HAP_GENE_CTRL4 , 0xf0f0}, 142 {RT5677_HAP_GENE_CTRL5 , 0xef0e}, 143 {RT5677_HAP_GENE_CTRL6 , 0xf0f0}, 144 {RT5677_HAP_GENE_CTRL7 , 0xef0e}, 145 {RT5677_HAP_GENE_CTRL8 , 0xf0f0}, 146 {RT5677_HAP_GENE_CTRL9 , 0xf000}, 147 {RT5677_HAP_GENE_CTRL10 , 0x0000}, 148 {RT5677_PWR_DIG1 , 0x0000}, 149 {RT5677_PWR_DIG2 , 0x0000}, 150 {RT5677_PWR_ANLG1 , 0x0055}, 151 {RT5677_PWR_ANLG2 , 0x0000}, 152 {RT5677_PWR_DSP1 , 0x0001}, 153 {RT5677_PWR_DSP_ST , 0x0000}, 154 {RT5677_PWR_DSP2 , 0x0000}, 155 {RT5677_ADC_DAC_HPF_CTRL1 , 0x0e00}, 156 {RT5677_PRIV_INDEX , 0x0000}, 157 {RT5677_PRIV_DATA , 0x0000}, 158 {RT5677_I2S4_SDP , 0x8000}, 159 {RT5677_I2S1_SDP , 0x8000}, 160 {RT5677_I2S2_SDP , 0x8000}, 161 {RT5677_I2S3_SDP , 0x8000}, 162 {RT5677_CLK_TREE_CTRL1 , 0x1111}, 163 {RT5677_CLK_TREE_CTRL2 , 0x1111}, 164 {RT5677_CLK_TREE_CTRL3 , 0x0000}, 165 {RT5677_PLL1_CTRL1 , 0x0000}, 166 {RT5677_PLL1_CTRL2 , 0x0000}, 167 {RT5677_PLL2_CTRL1 , 0x0c60}, 168 {RT5677_PLL2_CTRL2 , 0x2000}, 169 {RT5677_GLB_CLK1 , 0x0000}, 170 {RT5677_GLB_CLK2 , 0x0000}, 171 {RT5677_ASRC_1 , 0x0000}, 172 {RT5677_ASRC_2 , 0x0000}, 173 {RT5677_ASRC_3 , 0x0000}, 174 {RT5677_ASRC_4 , 0x0000}, 175 {RT5677_ASRC_5 , 0x0000}, 176 {RT5677_ASRC_6 , 0x0000}, 177 {RT5677_ASRC_7 , 0x0000}, 178 {RT5677_ASRC_8 , 0x0000}, 179 {RT5677_ASRC_9 , 0x0000}, 180 {RT5677_ASRC_10 , 0x0000}, 181 {RT5677_ASRC_11 , 0x0000}, 182 {RT5677_ASRC_12 , 0x0018}, 183 {RT5677_ASRC_13 , 0x0000}, 184 {RT5677_ASRC_14 , 0x0000}, 185 {RT5677_ASRC_15 , 0x0000}, 186 {RT5677_ASRC_16 , 0x0000}, 187 {RT5677_ASRC_17 , 0x0000}, 188 {RT5677_ASRC_18 , 0x0000}, 189 {RT5677_ASRC_19 , 0x0000}, 190 {RT5677_ASRC_20 , 0x0000}, 191 {RT5677_ASRC_21 , 0x000c}, 192 {RT5677_ASRC_22 , 0x0000}, 193 {RT5677_ASRC_23 , 0x0000}, 194 {RT5677_VAD_CTRL1 , 0x2184}, 195 {RT5677_VAD_CTRL2 , 0x010a}, 196 {RT5677_VAD_CTRL3 , 0x0aea}, 197 {RT5677_VAD_CTRL4 , 0x000c}, 198 {RT5677_VAD_CTRL5 , 0x0000}, 199 {RT5677_DSP_INB_CTRL1 , 0x0000}, 200 {RT5677_DSP_INB_CTRL2 , 0x0000}, 201 {RT5677_DSP_IN_OUTB_CTRL , 0x0000}, 202 {RT5677_DSP_OUTB0_1_DIG_VOL , 0x2f2f}, 203 {RT5677_DSP_OUTB2_3_DIG_VOL , 0x2f2f}, 204 {RT5677_DSP_OUTB4_5_DIG_VOL , 0x2f2f}, 205 {RT5677_DSP_OUTB6_7_DIG_VOL , 0x2f2f}, 206 {RT5677_ADC_EQ_CTRL1 , 0x6000}, 207 {RT5677_ADC_EQ_CTRL2 , 0x0000}, 208 {RT5677_EQ_CTRL1 , 0xc000}, 209 {RT5677_EQ_CTRL2 , 0x0000}, 210 {RT5677_EQ_CTRL3 , 0x0000}, 211 {RT5677_SOFT_VOL_ZERO_CROSS1 , 0x0009}, 212 {RT5677_JD_CTRL1 , 0x0000}, 213 {RT5677_JD_CTRL2 , 0x0000}, 214 {RT5677_JD_CTRL3 , 0x0000}, 215 {RT5677_IRQ_CTRL1 , 0x0000}, 216 {RT5677_IRQ_CTRL2 , 0x0000}, 217 {RT5677_GPIO_ST , 0x0000}, 218 {RT5677_GPIO_CTRL1 , 0x0000}, 219 {RT5677_GPIO_CTRL2 , 0x0000}, 220 {RT5677_GPIO_CTRL3 , 0x0000}, 221 {RT5677_STO1_ADC_HI_FILTER1 , 0xb320}, 222 {RT5677_STO1_ADC_HI_FILTER2 , 0x0000}, 223 {RT5677_MONO_ADC_HI_FILTER1 , 0xb300}, 224 {RT5677_MONO_ADC_HI_FILTER2 , 0x0000}, 225 {RT5677_STO2_ADC_HI_FILTER1 , 0xb300}, 226 {RT5677_STO2_ADC_HI_FILTER2 , 0x0000}, 227 {RT5677_STO3_ADC_HI_FILTER1 , 0xb300}, 228 {RT5677_STO3_ADC_HI_FILTER2 , 0x0000}, 229 {RT5677_STO4_ADC_HI_FILTER1 , 0xb300}, 230 {RT5677_STO4_ADC_HI_FILTER2 , 0x0000}, 231 {RT5677_MB_DRC_CTRL1 , 0x0f20}, 232 {RT5677_DRC1_CTRL1 , 0x001f}, 233 {RT5677_DRC1_CTRL2 , 0x020c}, 234 {RT5677_DRC1_CTRL3 , 0x1f00}, 235 {RT5677_DRC1_CTRL4 , 0x0000}, 236 {RT5677_DRC1_CTRL5 , 0x0000}, 237 {RT5677_DRC1_CTRL6 , 0x0029}, 238 {RT5677_DRC2_CTRL1 , 0x001f}, 239 {RT5677_DRC2_CTRL2 , 0x020c}, 240 {RT5677_DRC2_CTRL3 , 0x1f00}, 241 {RT5677_DRC2_CTRL4 , 0x0000}, 242 {RT5677_DRC2_CTRL5 , 0x0000}, 243 {RT5677_DRC2_CTRL6 , 0x0029}, 244 {RT5677_DRC1_HL_CTRL1 , 0x8000}, 245 {RT5677_DRC1_HL_CTRL2 , 0x0200}, 246 {RT5677_DRC2_HL_CTRL1 , 0x8000}, 247 {RT5677_DRC2_HL_CTRL2 , 0x0200}, 248 {RT5677_DSP_INB1_SRC_CTRL1 , 0x5800}, 249 {RT5677_DSP_INB1_SRC_CTRL2 , 0x0000}, 250 {RT5677_DSP_INB1_SRC_CTRL3 , 0x0000}, 251 {RT5677_DSP_INB1_SRC_CTRL4 , 0x0800}, 252 {RT5677_DSP_INB2_SRC_CTRL1 , 0x5800}, 253 {RT5677_DSP_INB2_SRC_CTRL2 , 0x0000}, 254 {RT5677_DSP_INB2_SRC_CTRL3 , 0x0000}, 255 {RT5677_DSP_INB2_SRC_CTRL4 , 0x0800}, 256 {RT5677_DSP_INB3_SRC_CTRL1 , 0x5800}, 257 {RT5677_DSP_INB3_SRC_CTRL2 , 0x0000}, 258 {RT5677_DSP_INB3_SRC_CTRL3 , 0x0000}, 259 {RT5677_DSP_INB3_SRC_CTRL4 , 0x0800}, 260 {RT5677_DSP_OUTB1_SRC_CTRL1 , 0x5800}, 261 {RT5677_DSP_OUTB1_SRC_CTRL2 , 0x0000}, 262 {RT5677_DSP_OUTB1_SRC_CTRL3 , 0x0000}, 263 {RT5677_DSP_OUTB1_SRC_CTRL4 , 0x0800}, 264 {RT5677_DSP_OUTB2_SRC_CTRL1 , 0x5800}, 265 {RT5677_DSP_OUTB2_SRC_CTRL2 , 0x0000}, 266 {RT5677_DSP_OUTB2_SRC_CTRL3 , 0x0000}, 267 {RT5677_DSP_OUTB2_SRC_CTRL4 , 0x0800}, 268 {RT5677_DSP_OUTB_0123_MIXER_CTRL, 0xfefe}, 269 {RT5677_DSP_OUTB_45_MIXER_CTRL , 0xfefe}, 270 {RT5677_DSP_OUTB_67_MIXER_CTRL , 0xfefe}, 271 {RT5677_DIG_MISC , 0x0000}, 272 {RT5677_GEN_CTRL1 , 0x0000}, 273 {RT5677_GEN_CTRL2 , 0x0000}, 274 {RT5677_VENDOR_ID , 0x0000}, 275 {RT5677_VENDOR_ID1 , 0x10ec}, 276 {RT5677_VENDOR_ID2 , 0x6327}, 277 }; 278 279 static bool rt5677_volatile_register(struct device *dev, unsigned int reg) 280 { 281 int i; 282 283 for (i = 0; i < ARRAY_SIZE(rt5677_ranges); i++) { 284 if (reg >= rt5677_ranges[i].range_min && 285 reg <= rt5677_ranges[i].range_max) { 286 return true; 287 } 288 } 289 290 switch (reg) { 291 case RT5677_RESET: 292 case RT5677_SLIMBUS_PARAM: 293 case RT5677_PDM_DATA_CTRL1: 294 case RT5677_PDM_DATA_CTRL2: 295 case RT5677_PDM1_DATA_CTRL4: 296 case RT5677_PDM2_DATA_CTRL4: 297 case RT5677_I2C_MASTER_CTRL1: 298 case RT5677_I2C_MASTER_CTRL7: 299 case RT5677_I2C_MASTER_CTRL8: 300 case RT5677_HAP_GENE_CTRL2: 301 case RT5677_PWR_DSP_ST: 302 case RT5677_PRIV_DATA: 303 case RT5677_ASRC_22: 304 case RT5677_ASRC_23: 305 case RT5677_VAD_CTRL5: 306 case RT5677_ADC_EQ_CTRL1: 307 case RT5677_EQ_CTRL1: 308 case RT5677_IRQ_CTRL1: 309 case RT5677_IRQ_CTRL2: 310 case RT5677_GPIO_ST: 311 case RT5677_DSP_INB1_SRC_CTRL4: 312 case RT5677_DSP_INB2_SRC_CTRL4: 313 case RT5677_DSP_INB3_SRC_CTRL4: 314 case RT5677_DSP_OUTB1_SRC_CTRL4: 315 case RT5677_DSP_OUTB2_SRC_CTRL4: 316 case RT5677_VENDOR_ID: 317 case RT5677_VENDOR_ID1: 318 case RT5677_VENDOR_ID2: 319 return true; 320 default: 321 return false; 322 } 323 } 324 325 static bool rt5677_readable_register(struct device *dev, unsigned int reg) 326 { 327 int i; 328 329 for (i = 0; i < ARRAY_SIZE(rt5677_ranges); i++) { 330 if (reg >= rt5677_ranges[i].range_min && 331 reg <= rt5677_ranges[i].range_max) { 332 return true; 333 } 334 } 335 336 switch (reg) { 337 case RT5677_RESET: 338 case RT5677_LOUT1: 339 case RT5677_IN1: 340 case RT5677_MICBIAS: 341 case RT5677_SLIMBUS_PARAM: 342 case RT5677_SLIMBUS_RX: 343 case RT5677_SLIMBUS_CTRL: 344 case RT5677_SIDETONE_CTRL: 345 case RT5677_ANA_DAC1_2_3_SRC: 346 case RT5677_IF_DSP_DAC3_4_MIXER: 347 case RT5677_DAC4_DIG_VOL: 348 case RT5677_DAC3_DIG_VOL: 349 case RT5677_DAC1_DIG_VOL: 350 case RT5677_DAC2_DIG_VOL: 351 case RT5677_IF_DSP_DAC2_MIXER: 352 case RT5677_STO1_ADC_DIG_VOL: 353 case RT5677_MONO_ADC_DIG_VOL: 354 case RT5677_STO1_2_ADC_BST: 355 case RT5677_STO2_ADC_DIG_VOL: 356 case RT5677_ADC_BST_CTRL2: 357 case RT5677_STO3_4_ADC_BST: 358 case RT5677_STO3_ADC_DIG_VOL: 359 case RT5677_STO4_ADC_DIG_VOL: 360 case RT5677_STO4_ADC_MIXER: 361 case RT5677_STO3_ADC_MIXER: 362 case RT5677_STO2_ADC_MIXER: 363 case RT5677_STO1_ADC_MIXER: 364 case RT5677_MONO_ADC_MIXER: 365 case RT5677_ADC_IF_DSP_DAC1_MIXER: 366 case RT5677_STO1_DAC_MIXER: 367 case RT5677_MONO_DAC_MIXER: 368 case RT5677_DD1_MIXER: 369 case RT5677_DD2_MIXER: 370 case RT5677_IF3_DATA: 371 case RT5677_IF4_DATA: 372 case RT5677_PDM_OUT_CTRL: 373 case RT5677_PDM_DATA_CTRL1: 374 case RT5677_PDM_DATA_CTRL2: 375 case RT5677_PDM1_DATA_CTRL2: 376 case RT5677_PDM1_DATA_CTRL3: 377 case RT5677_PDM1_DATA_CTRL4: 378 case RT5677_PDM2_DATA_CTRL2: 379 case RT5677_PDM2_DATA_CTRL3: 380 case RT5677_PDM2_DATA_CTRL4: 381 case RT5677_TDM1_CTRL1: 382 case RT5677_TDM1_CTRL2: 383 case RT5677_TDM1_CTRL3: 384 case RT5677_TDM1_CTRL4: 385 case RT5677_TDM1_CTRL5: 386 case RT5677_TDM2_CTRL1: 387 case RT5677_TDM2_CTRL2: 388 case RT5677_TDM2_CTRL3: 389 case RT5677_TDM2_CTRL4: 390 case RT5677_TDM2_CTRL5: 391 case RT5677_I2C_MASTER_CTRL1: 392 case RT5677_I2C_MASTER_CTRL2: 393 case RT5677_I2C_MASTER_CTRL3: 394 case RT5677_I2C_MASTER_CTRL4: 395 case RT5677_I2C_MASTER_CTRL5: 396 case RT5677_I2C_MASTER_CTRL6: 397 case RT5677_I2C_MASTER_CTRL7: 398 case RT5677_I2C_MASTER_CTRL8: 399 case RT5677_DMIC_CTRL1: 400 case RT5677_DMIC_CTRL2: 401 case RT5677_HAP_GENE_CTRL1: 402 case RT5677_HAP_GENE_CTRL2: 403 case RT5677_HAP_GENE_CTRL3: 404 case RT5677_HAP_GENE_CTRL4: 405 case RT5677_HAP_GENE_CTRL5: 406 case RT5677_HAP_GENE_CTRL6: 407 case RT5677_HAP_GENE_CTRL7: 408 case RT5677_HAP_GENE_CTRL8: 409 case RT5677_HAP_GENE_CTRL9: 410 case RT5677_HAP_GENE_CTRL10: 411 case RT5677_PWR_DIG1: 412 case RT5677_PWR_DIG2: 413 case RT5677_PWR_ANLG1: 414 case RT5677_PWR_ANLG2: 415 case RT5677_PWR_DSP1: 416 case RT5677_PWR_DSP_ST: 417 case RT5677_PWR_DSP2: 418 case RT5677_ADC_DAC_HPF_CTRL1: 419 case RT5677_PRIV_INDEX: 420 case RT5677_PRIV_DATA: 421 case RT5677_I2S4_SDP: 422 case RT5677_I2S1_SDP: 423 case RT5677_I2S2_SDP: 424 case RT5677_I2S3_SDP: 425 case RT5677_CLK_TREE_CTRL1: 426 case RT5677_CLK_TREE_CTRL2: 427 case RT5677_CLK_TREE_CTRL3: 428 case RT5677_PLL1_CTRL1: 429 case RT5677_PLL1_CTRL2: 430 case RT5677_PLL2_CTRL1: 431 case RT5677_PLL2_CTRL2: 432 case RT5677_GLB_CLK1: 433 case RT5677_GLB_CLK2: 434 case RT5677_ASRC_1: 435 case RT5677_ASRC_2: 436 case RT5677_ASRC_3: 437 case RT5677_ASRC_4: 438 case RT5677_ASRC_5: 439 case RT5677_ASRC_6: 440 case RT5677_ASRC_7: 441 case RT5677_ASRC_8: 442 case RT5677_ASRC_9: 443 case RT5677_ASRC_10: 444 case RT5677_ASRC_11: 445 case RT5677_ASRC_12: 446 case RT5677_ASRC_13: 447 case RT5677_ASRC_14: 448 case RT5677_ASRC_15: 449 case RT5677_ASRC_16: 450 case RT5677_ASRC_17: 451 case RT5677_ASRC_18: 452 case RT5677_ASRC_19: 453 case RT5677_ASRC_20: 454 case RT5677_ASRC_21: 455 case RT5677_ASRC_22: 456 case RT5677_ASRC_23: 457 case RT5677_VAD_CTRL1: 458 case RT5677_VAD_CTRL2: 459 case RT5677_VAD_CTRL3: 460 case RT5677_VAD_CTRL4: 461 case RT5677_VAD_CTRL5: 462 case RT5677_DSP_INB_CTRL1: 463 case RT5677_DSP_INB_CTRL2: 464 case RT5677_DSP_IN_OUTB_CTRL: 465 case RT5677_DSP_OUTB0_1_DIG_VOL: 466 case RT5677_DSP_OUTB2_3_DIG_VOL: 467 case RT5677_DSP_OUTB4_5_DIG_VOL: 468 case RT5677_DSP_OUTB6_7_DIG_VOL: 469 case RT5677_ADC_EQ_CTRL1: 470 case RT5677_ADC_EQ_CTRL2: 471 case RT5677_EQ_CTRL1: 472 case RT5677_EQ_CTRL2: 473 case RT5677_EQ_CTRL3: 474 case RT5677_SOFT_VOL_ZERO_CROSS1: 475 case RT5677_JD_CTRL1: 476 case RT5677_JD_CTRL2: 477 case RT5677_JD_CTRL3: 478 case RT5677_IRQ_CTRL1: 479 case RT5677_IRQ_CTRL2: 480 case RT5677_GPIO_ST: 481 case RT5677_GPIO_CTRL1: 482 case RT5677_GPIO_CTRL2: 483 case RT5677_GPIO_CTRL3: 484 case RT5677_STO1_ADC_HI_FILTER1: 485 case RT5677_STO1_ADC_HI_FILTER2: 486 case RT5677_MONO_ADC_HI_FILTER1: 487 case RT5677_MONO_ADC_HI_FILTER2: 488 case RT5677_STO2_ADC_HI_FILTER1: 489 case RT5677_STO2_ADC_HI_FILTER2: 490 case RT5677_STO3_ADC_HI_FILTER1: 491 case RT5677_STO3_ADC_HI_FILTER2: 492 case RT5677_STO4_ADC_HI_FILTER1: 493 case RT5677_STO4_ADC_HI_FILTER2: 494 case RT5677_MB_DRC_CTRL1: 495 case RT5677_DRC1_CTRL1: 496 case RT5677_DRC1_CTRL2: 497 case RT5677_DRC1_CTRL3: 498 case RT5677_DRC1_CTRL4: 499 case RT5677_DRC1_CTRL5: 500 case RT5677_DRC1_CTRL6: 501 case RT5677_DRC2_CTRL1: 502 case RT5677_DRC2_CTRL2: 503 case RT5677_DRC2_CTRL3: 504 case RT5677_DRC2_CTRL4: 505 case RT5677_DRC2_CTRL5: 506 case RT5677_DRC2_CTRL6: 507 case RT5677_DRC1_HL_CTRL1: 508 case RT5677_DRC1_HL_CTRL2: 509 case RT5677_DRC2_HL_CTRL1: 510 case RT5677_DRC2_HL_CTRL2: 511 case RT5677_DSP_INB1_SRC_CTRL1: 512 case RT5677_DSP_INB1_SRC_CTRL2: 513 case RT5677_DSP_INB1_SRC_CTRL3: 514 case RT5677_DSP_INB1_SRC_CTRL4: 515 case RT5677_DSP_INB2_SRC_CTRL1: 516 case RT5677_DSP_INB2_SRC_CTRL2: 517 case RT5677_DSP_INB2_SRC_CTRL3: 518 case RT5677_DSP_INB2_SRC_CTRL4: 519 case RT5677_DSP_INB3_SRC_CTRL1: 520 case RT5677_DSP_INB3_SRC_CTRL2: 521 case RT5677_DSP_INB3_SRC_CTRL3: 522 case RT5677_DSP_INB3_SRC_CTRL4: 523 case RT5677_DSP_OUTB1_SRC_CTRL1: 524 case RT5677_DSP_OUTB1_SRC_CTRL2: 525 case RT5677_DSP_OUTB1_SRC_CTRL3: 526 case RT5677_DSP_OUTB1_SRC_CTRL4: 527 case RT5677_DSP_OUTB2_SRC_CTRL1: 528 case RT5677_DSP_OUTB2_SRC_CTRL2: 529 case RT5677_DSP_OUTB2_SRC_CTRL3: 530 case RT5677_DSP_OUTB2_SRC_CTRL4: 531 case RT5677_DSP_OUTB_0123_MIXER_CTRL: 532 case RT5677_DSP_OUTB_45_MIXER_CTRL: 533 case RT5677_DSP_OUTB_67_MIXER_CTRL: 534 case RT5677_DIG_MISC: 535 case RT5677_GEN_CTRL1: 536 case RT5677_GEN_CTRL2: 537 case RT5677_VENDOR_ID: 538 case RT5677_VENDOR_ID1: 539 case RT5677_VENDOR_ID2: 540 return true; 541 default: 542 return false; 543 } 544 } 545 546 /** 547 * rt5677_dsp_mode_i2c_write_addr - Write value to address on DSP mode. 548 * @rt5677: Private Data. 549 * @addr: Address index. 550 * @value: Address data. 551 * @opcode: opcode value 552 * 553 * Returns 0 for success or negative error code. 554 */ 555 static int rt5677_dsp_mode_i2c_write_addr(struct rt5677_priv *rt5677, 556 unsigned int addr, unsigned int value, unsigned int opcode) 557 { 558 struct snd_soc_component *component = rt5677->component; 559 int ret; 560 561 mutex_lock(&rt5677->dsp_cmd_lock); 562 563 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_MSB, 564 addr >> 16); 565 if (ret < 0) { 566 dev_err(component->dev, "Failed to set addr msb value: %d\n", ret); 567 goto err; 568 } 569 570 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_LSB, 571 addr & 0xffff); 572 if (ret < 0) { 573 dev_err(component->dev, "Failed to set addr lsb value: %d\n", ret); 574 goto err; 575 } 576 577 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_MSB, 578 value >> 16); 579 if (ret < 0) { 580 dev_err(component->dev, "Failed to set data msb value: %d\n", ret); 581 goto err; 582 } 583 584 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_LSB, 585 value & 0xffff); 586 if (ret < 0) { 587 dev_err(component->dev, "Failed to set data lsb value: %d\n", ret); 588 goto err; 589 } 590 591 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_OP_CODE, 592 opcode); 593 if (ret < 0) { 594 dev_err(component->dev, "Failed to set op code value: %d\n", ret); 595 goto err; 596 } 597 598 err: 599 mutex_unlock(&rt5677->dsp_cmd_lock); 600 601 return ret; 602 } 603 604 /** 605 * rt5677_dsp_mode_i2c_read_addr - Read value from address on DSP mode. 606 * @rt5677: Private Data. 607 * @addr: Address index. 608 * @value: Address data. 609 * 610 * 611 * Returns 0 for success or negative error code. 612 */ 613 static int rt5677_dsp_mode_i2c_read_addr( 614 struct rt5677_priv *rt5677, unsigned int addr, unsigned int *value) 615 { 616 struct snd_soc_component *component = rt5677->component; 617 int ret; 618 unsigned int msb, lsb; 619 620 mutex_lock(&rt5677->dsp_cmd_lock); 621 622 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_MSB, 623 addr >> 16); 624 if (ret < 0) { 625 dev_err(component->dev, "Failed to set addr msb value: %d\n", ret); 626 goto err; 627 } 628 629 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_LSB, 630 addr & 0xffff); 631 if (ret < 0) { 632 dev_err(component->dev, "Failed to set addr lsb value: %d\n", ret); 633 goto err; 634 } 635 636 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_OP_CODE, 637 0x0002); 638 if (ret < 0) { 639 dev_err(component->dev, "Failed to set op code value: %d\n", ret); 640 goto err; 641 } 642 643 regmap_read(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_MSB, &msb); 644 regmap_read(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_LSB, &lsb); 645 *value = (msb << 16) | lsb; 646 647 err: 648 mutex_unlock(&rt5677->dsp_cmd_lock); 649 650 return ret; 651 } 652 653 /** 654 * rt5677_dsp_mode_i2c_write - Write register on DSP mode. 655 * @rt5677: Private Data. 656 * @reg: Register index. 657 * @value: Register data. 658 * 659 * 660 * Returns 0 for success or negative error code. 661 */ 662 static int rt5677_dsp_mode_i2c_write(struct rt5677_priv *rt5677, 663 unsigned int reg, unsigned int value) 664 { 665 return rt5677_dsp_mode_i2c_write_addr(rt5677, 0x18020000 + reg * 2, 666 value, 0x0001); 667 } 668 669 /** 670 * rt5677_dsp_mode_i2c_read - Read register on DSP mode. 671 * @rt5677: Private Data 672 * @reg: Register index. 673 * @value: Register data. 674 * 675 * 676 * Returns 0 for success or negative error code. 677 */ 678 static int rt5677_dsp_mode_i2c_read( 679 struct rt5677_priv *rt5677, unsigned int reg, unsigned int *value) 680 { 681 int ret = rt5677_dsp_mode_i2c_read_addr(rt5677, 0x18020000 + reg * 2, 682 value); 683 684 *value &= 0xffff; 685 686 return ret; 687 } 688 689 static void rt5677_set_dsp_mode(struct snd_soc_component *component, bool on) 690 { 691 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component); 692 693 if (on) { 694 regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, 0x2, 0x2); 695 rt5677->is_dsp_mode = true; 696 } else { 697 regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, 0x2, 0x0); 698 rt5677->is_dsp_mode = false; 699 } 700 } 701 702 static int rt5677_set_dsp_vad(struct snd_soc_component *component, bool on) 703 { 704 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component); 705 static bool activity; 706 int ret; 707 708 if (!IS_ENABLED(CONFIG_SND_SOC_RT5677_SPI)) 709 return -ENXIO; 710 711 if (on && !activity) { 712 activity = true; 713 714 regcache_cache_only(rt5677->regmap, false); 715 regcache_cache_bypass(rt5677->regmap, true); 716 717 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x1, 0x1); 718 regmap_update_bits(rt5677->regmap, 719 RT5677_PR_BASE + RT5677_BIAS_CUR4, 0x0f00, 0x0f00); 720 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1, 721 RT5677_LDO1_SEL_MASK, 0x0); 722 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2, 723 RT5677_PWR_LDO1, RT5677_PWR_LDO1); 724 switch (rt5677->type) { 725 case RT5677: 726 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1, 727 RT5677_MCLK_SRC_MASK, RT5677_MCLK2_SRC); 728 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK2, 729 RT5677_PLL2_PR_SRC_MASK | 730 RT5677_DSP_CLK_SRC_MASK, 731 RT5677_PLL2_PR_SRC_MCLK2 | 732 RT5677_DSP_CLK_SRC_BYPASS); 733 break; 734 case RT5676: 735 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK2, 736 RT5677_DSP_CLK_SRC_MASK, 737 RT5677_DSP_CLK_SRC_BYPASS); 738 break; 739 default: 740 break; 741 } 742 regmap_write(rt5677->regmap, RT5677_PWR_DSP2, 0x07ff); 743 regmap_write(rt5677->regmap, RT5677_PWR_DSP1, 0x07fd); 744 rt5677_set_dsp_mode(component, true); 745 746 ret = request_firmware(&rt5677->fw1, RT5677_FIRMWARE1, 747 component->dev); 748 if (ret == 0) { 749 rt5677_spi_write_firmware(0x50000000, rt5677->fw1); 750 release_firmware(rt5677->fw1); 751 } 752 753 ret = request_firmware(&rt5677->fw2, RT5677_FIRMWARE2, 754 component->dev); 755 if (ret == 0) { 756 rt5677_spi_write_firmware(0x60000000, rt5677->fw2); 757 release_firmware(rt5677->fw2); 758 } 759 760 regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, 0x1, 0x0); 761 762 regcache_cache_bypass(rt5677->regmap, false); 763 regcache_cache_only(rt5677->regmap, true); 764 } else if (!on && activity) { 765 activity = false; 766 767 regcache_cache_only(rt5677->regmap, false); 768 regcache_cache_bypass(rt5677->regmap, true); 769 770 regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, 0x1, 0x1); 771 rt5677_set_dsp_mode(component, false); 772 regmap_write(rt5677->regmap, RT5677_PWR_DSP1, 0x0001); 773 774 regmap_write(rt5677->regmap, RT5677_RESET, 0x10ec); 775 776 regcache_cache_bypass(rt5677->regmap, false); 777 regcache_mark_dirty(rt5677->regmap); 778 regcache_sync(rt5677->regmap); 779 } 780 781 return 0; 782 } 783 784 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6525, 75, 0); 785 static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0); 786 static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0); 787 static const DECLARE_TLV_DB_SCALE(st_vol_tlv, -4650, 150, 0); 788 789 /* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */ 790 static const DECLARE_TLV_DB_RANGE(bst_tlv, 791 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0), 792 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0), 793 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0), 794 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0), 795 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0), 796 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0), 797 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0) 798 ); 799 800 static int rt5677_dsp_vad_get(struct snd_kcontrol *kcontrol, 801 struct snd_ctl_elem_value *ucontrol) 802 { 803 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 804 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component); 805 806 ucontrol->value.integer.value[0] = rt5677->dsp_vad_en; 807 808 return 0; 809 } 810 811 static int rt5677_dsp_vad_put(struct snd_kcontrol *kcontrol, 812 struct snd_ctl_elem_value *ucontrol) 813 { 814 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 815 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component); 816 817 rt5677->dsp_vad_en = !!ucontrol->value.integer.value[0]; 818 819 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) 820 rt5677_set_dsp_vad(component, rt5677->dsp_vad_en); 821 822 return 0; 823 } 824 825 static const struct snd_kcontrol_new rt5677_snd_controls[] = { 826 /* OUTPUT Control */ 827 SOC_SINGLE("OUT1 Playback Switch", RT5677_LOUT1, 828 RT5677_LOUT1_L_MUTE_SFT, 1, 1), 829 SOC_SINGLE("OUT2 Playback Switch", RT5677_LOUT1, 830 RT5677_LOUT2_L_MUTE_SFT, 1, 1), 831 SOC_SINGLE("OUT3 Playback Switch", RT5677_LOUT1, 832 RT5677_LOUT3_L_MUTE_SFT, 1, 1), 833 834 /* DAC Digital Volume */ 835 SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5677_DAC1_DIG_VOL, 836 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 127, 0, dac_vol_tlv), 837 SOC_DOUBLE_TLV("DAC2 Playback Volume", RT5677_DAC2_DIG_VOL, 838 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 127, 0, dac_vol_tlv), 839 SOC_DOUBLE_TLV("DAC3 Playback Volume", RT5677_DAC3_DIG_VOL, 840 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 127, 0, dac_vol_tlv), 841 SOC_DOUBLE_TLV("DAC4 Playback Volume", RT5677_DAC4_DIG_VOL, 842 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 127, 0, dac_vol_tlv), 843 844 /* IN1/IN2 Control */ 845 SOC_SINGLE_TLV("IN1 Boost", RT5677_IN1, RT5677_BST_SFT1, 8, 0, bst_tlv), 846 SOC_SINGLE_TLV("IN2 Boost", RT5677_IN1, RT5677_BST_SFT2, 8, 0, bst_tlv), 847 848 /* ADC Digital Volume Control */ 849 SOC_DOUBLE("ADC1 Capture Switch", RT5677_STO1_ADC_DIG_VOL, 850 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1), 851 SOC_DOUBLE("ADC2 Capture Switch", RT5677_STO2_ADC_DIG_VOL, 852 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1), 853 SOC_DOUBLE("ADC3 Capture Switch", RT5677_STO3_ADC_DIG_VOL, 854 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1), 855 SOC_DOUBLE("ADC4 Capture Switch", RT5677_STO4_ADC_DIG_VOL, 856 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1), 857 SOC_DOUBLE("Mono ADC Capture Switch", RT5677_MONO_ADC_DIG_VOL, 858 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1), 859 860 SOC_DOUBLE_TLV("ADC1 Capture Volume", RT5677_STO1_ADC_DIG_VOL, 861 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 63, 0, 862 adc_vol_tlv), 863 SOC_DOUBLE_TLV("ADC2 Capture Volume", RT5677_STO2_ADC_DIG_VOL, 864 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 63, 0, 865 adc_vol_tlv), 866 SOC_DOUBLE_TLV("ADC3 Capture Volume", RT5677_STO3_ADC_DIG_VOL, 867 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 63, 0, 868 adc_vol_tlv), 869 SOC_DOUBLE_TLV("ADC4 Capture Volume", RT5677_STO4_ADC_DIG_VOL, 870 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 63, 0, 871 adc_vol_tlv), 872 SOC_DOUBLE_TLV("Mono ADC Capture Volume", RT5677_MONO_ADC_DIG_VOL, 873 RT5677_MONO_ADC_L_VOL_SFT, RT5677_MONO_ADC_R_VOL_SFT, 63, 0, 874 adc_vol_tlv), 875 876 /* Sidetone Control */ 877 SOC_SINGLE_TLV("Sidetone Volume", RT5677_SIDETONE_CTRL, 878 RT5677_ST_VOL_SFT, 31, 0, st_vol_tlv), 879 880 /* ADC Boost Volume Control */ 881 SOC_DOUBLE_TLV("STO1 ADC Boost Volume", RT5677_STO1_2_ADC_BST, 882 RT5677_STO1_ADC_L_BST_SFT, RT5677_STO1_ADC_R_BST_SFT, 3, 0, 883 adc_bst_tlv), 884 SOC_DOUBLE_TLV("STO2 ADC Boost Volume", RT5677_STO1_2_ADC_BST, 885 RT5677_STO2_ADC_L_BST_SFT, RT5677_STO2_ADC_R_BST_SFT, 3, 0, 886 adc_bst_tlv), 887 SOC_DOUBLE_TLV("STO3 ADC Boost Volume", RT5677_STO3_4_ADC_BST, 888 RT5677_STO3_ADC_L_BST_SFT, RT5677_STO3_ADC_R_BST_SFT, 3, 0, 889 adc_bst_tlv), 890 SOC_DOUBLE_TLV("STO4 ADC Boost Volume", RT5677_STO3_4_ADC_BST, 891 RT5677_STO4_ADC_L_BST_SFT, RT5677_STO4_ADC_R_BST_SFT, 3, 0, 892 adc_bst_tlv), 893 SOC_DOUBLE_TLV("Mono ADC Boost Volume", RT5677_ADC_BST_CTRL2, 894 RT5677_MONO_ADC_L_BST_SFT, RT5677_MONO_ADC_R_BST_SFT, 3, 0, 895 adc_bst_tlv), 896 897 SOC_SINGLE_EXT("DSP VAD Switch", SND_SOC_NOPM, 0, 1, 0, 898 rt5677_dsp_vad_get, rt5677_dsp_vad_put), 899 }; 900 901 /** 902 * set_dmic_clk - Set parameter of dmic. 903 * 904 * @w: DAPM widget. 905 * @kcontrol: The kcontrol of this widget. 906 * @event: Event id. 907 * 908 * Choose dmic clock between 1MHz and 3MHz. 909 * It is better for clock to approximate 3MHz. 910 */ 911 static int set_dmic_clk(struct snd_soc_dapm_widget *w, 912 struct snd_kcontrol *kcontrol, int event) 913 { 914 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 915 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component); 916 int idx, rate; 917 918 rate = rt5677->sysclk / rl6231_get_pre_div(rt5677->regmap, 919 RT5677_CLK_TREE_CTRL1, RT5677_I2S_PD1_SFT); 920 idx = rl6231_calc_dmic_clk(rate); 921 if (idx < 0) 922 dev_err(component->dev, "Failed to set DMIC clock\n"); 923 else 924 regmap_update_bits(rt5677->regmap, RT5677_DMIC_CTRL1, 925 RT5677_DMIC_CLK_MASK, idx << RT5677_DMIC_CLK_SFT); 926 return idx; 927 } 928 929 static int is_sys_clk_from_pll(struct snd_soc_dapm_widget *source, 930 struct snd_soc_dapm_widget *sink) 931 { 932 struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm); 933 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component); 934 unsigned int val; 935 936 regmap_read(rt5677->regmap, RT5677_GLB_CLK1, &val); 937 val &= RT5677_SCLK_SRC_MASK; 938 if (val == RT5677_SCLK_SRC_PLL1) 939 return 1; 940 else 941 return 0; 942 } 943 944 static int is_using_asrc(struct snd_soc_dapm_widget *source, 945 struct snd_soc_dapm_widget *sink) 946 { 947 struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm); 948 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component); 949 unsigned int reg, shift, val; 950 951 if (source->reg == RT5677_ASRC_1) { 952 switch (source->shift) { 953 case 12: 954 reg = RT5677_ASRC_4; 955 shift = 0; 956 break; 957 case 13: 958 reg = RT5677_ASRC_4; 959 shift = 4; 960 break; 961 case 14: 962 reg = RT5677_ASRC_4; 963 shift = 8; 964 break; 965 case 15: 966 reg = RT5677_ASRC_4; 967 shift = 12; 968 break; 969 default: 970 return 0; 971 } 972 } else { 973 switch (source->shift) { 974 case 0: 975 reg = RT5677_ASRC_6; 976 shift = 8; 977 break; 978 case 1: 979 reg = RT5677_ASRC_6; 980 shift = 12; 981 break; 982 case 2: 983 reg = RT5677_ASRC_5; 984 shift = 0; 985 break; 986 case 3: 987 reg = RT5677_ASRC_5; 988 shift = 4; 989 break; 990 case 4: 991 reg = RT5677_ASRC_5; 992 shift = 8; 993 break; 994 case 5: 995 reg = RT5677_ASRC_5; 996 shift = 12; 997 break; 998 case 12: 999 reg = RT5677_ASRC_3; 1000 shift = 0; 1001 break; 1002 case 13: 1003 reg = RT5677_ASRC_3; 1004 shift = 4; 1005 break; 1006 case 14: 1007 reg = RT5677_ASRC_3; 1008 shift = 12; 1009 break; 1010 default: 1011 return 0; 1012 } 1013 } 1014 1015 regmap_read(rt5677->regmap, reg, &val); 1016 val = (val >> shift) & 0xf; 1017 1018 switch (val) { 1019 case 1 ... 6: 1020 return 1; 1021 default: 1022 return 0; 1023 } 1024 1025 } 1026 1027 static int can_use_asrc(struct snd_soc_dapm_widget *source, 1028 struct snd_soc_dapm_widget *sink) 1029 { 1030 struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm); 1031 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component); 1032 1033 if (rt5677->sysclk > rt5677->lrck[RT5677_AIF1] * 384) 1034 return 1; 1035 1036 return 0; 1037 } 1038 1039 /** 1040 * rt5677_sel_asrc_clk_src - select ASRC clock source for a set of filters 1041 * @component: SoC audio component device. 1042 * @filter_mask: mask of filters. 1043 * @clk_src: clock source 1044 * 1045 * The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5677 can 1046 * only support standard 32fs or 64fs i2s format, ASRC should be enabled to 1047 * support special i2s clock format such as Intel's 100fs(100 * sampling rate). 1048 * ASRC function will track i2s clock and generate a corresponding system clock 1049 * for codec. This function provides an API to select the clock source for a 1050 * set of filters specified by the mask. And the codec driver will turn on ASRC 1051 * for these filters if ASRC is selected as their clock source. 1052 */ 1053 int rt5677_sel_asrc_clk_src(struct snd_soc_component *component, 1054 unsigned int filter_mask, unsigned int clk_src) 1055 { 1056 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component); 1057 unsigned int asrc3_mask = 0, asrc3_value = 0; 1058 unsigned int asrc4_mask = 0, asrc4_value = 0; 1059 unsigned int asrc5_mask = 0, asrc5_value = 0; 1060 unsigned int asrc6_mask = 0, asrc6_value = 0; 1061 unsigned int asrc7_mask = 0, asrc7_value = 0; 1062 unsigned int asrc8_mask = 0, asrc8_value = 0; 1063 1064 switch (clk_src) { 1065 case RT5677_CLK_SEL_SYS: 1066 case RT5677_CLK_SEL_I2S1_ASRC: 1067 case RT5677_CLK_SEL_I2S2_ASRC: 1068 case RT5677_CLK_SEL_I2S3_ASRC: 1069 case RT5677_CLK_SEL_I2S4_ASRC: 1070 case RT5677_CLK_SEL_I2S5_ASRC: 1071 case RT5677_CLK_SEL_I2S6_ASRC: 1072 case RT5677_CLK_SEL_SYS2: 1073 case RT5677_CLK_SEL_SYS3: 1074 case RT5677_CLK_SEL_SYS4: 1075 case RT5677_CLK_SEL_SYS5: 1076 case RT5677_CLK_SEL_SYS6: 1077 case RT5677_CLK_SEL_SYS7: 1078 break; 1079 1080 default: 1081 return -EINVAL; 1082 } 1083 1084 /* ASRC 3 */ 1085 if (filter_mask & RT5677_DA_STEREO_FILTER) { 1086 asrc3_mask |= RT5677_DA_STO_CLK_SEL_MASK; 1087 asrc3_value = (asrc3_value & ~RT5677_DA_STO_CLK_SEL_MASK) 1088 | (clk_src << RT5677_DA_STO_CLK_SEL_SFT); 1089 } 1090 1091 if (filter_mask & RT5677_DA_MONO2_L_FILTER) { 1092 asrc3_mask |= RT5677_DA_MONO2L_CLK_SEL_MASK; 1093 asrc3_value = (asrc3_value & ~RT5677_DA_MONO2L_CLK_SEL_MASK) 1094 | (clk_src << RT5677_DA_MONO2L_CLK_SEL_SFT); 1095 } 1096 1097 if (filter_mask & RT5677_DA_MONO2_R_FILTER) { 1098 asrc3_mask |= RT5677_DA_MONO2R_CLK_SEL_MASK; 1099 asrc3_value = (asrc3_value & ~RT5677_DA_MONO2R_CLK_SEL_MASK) 1100 | (clk_src << RT5677_DA_MONO2R_CLK_SEL_SFT); 1101 } 1102 1103 if (asrc3_mask) 1104 regmap_update_bits(rt5677->regmap, RT5677_ASRC_3, asrc3_mask, 1105 asrc3_value); 1106 1107 /* ASRC 4 */ 1108 if (filter_mask & RT5677_DA_MONO3_L_FILTER) { 1109 asrc4_mask |= RT5677_DA_MONO3L_CLK_SEL_MASK; 1110 asrc4_value = (asrc4_value & ~RT5677_DA_MONO3L_CLK_SEL_MASK) 1111 | (clk_src << RT5677_DA_MONO3L_CLK_SEL_SFT); 1112 } 1113 1114 if (filter_mask & RT5677_DA_MONO3_R_FILTER) { 1115 asrc4_mask |= RT5677_DA_MONO3R_CLK_SEL_MASK; 1116 asrc4_value = (asrc4_value & ~RT5677_DA_MONO3R_CLK_SEL_MASK) 1117 | (clk_src << RT5677_DA_MONO3R_CLK_SEL_SFT); 1118 } 1119 1120 if (filter_mask & RT5677_DA_MONO4_L_FILTER) { 1121 asrc4_mask |= RT5677_DA_MONO4L_CLK_SEL_MASK; 1122 asrc4_value = (asrc4_value & ~RT5677_DA_MONO4L_CLK_SEL_MASK) 1123 | (clk_src << RT5677_DA_MONO4L_CLK_SEL_SFT); 1124 } 1125 1126 if (filter_mask & RT5677_DA_MONO4_R_FILTER) { 1127 asrc4_mask |= RT5677_DA_MONO4R_CLK_SEL_MASK; 1128 asrc4_value = (asrc4_value & ~RT5677_DA_MONO4R_CLK_SEL_MASK) 1129 | (clk_src << RT5677_DA_MONO4R_CLK_SEL_SFT); 1130 } 1131 1132 if (asrc4_mask) 1133 regmap_update_bits(rt5677->regmap, RT5677_ASRC_4, asrc4_mask, 1134 asrc4_value); 1135 1136 /* ASRC 5 */ 1137 if (filter_mask & RT5677_AD_STEREO1_FILTER) { 1138 asrc5_mask |= RT5677_AD_STO1_CLK_SEL_MASK; 1139 asrc5_value = (asrc5_value & ~RT5677_AD_STO1_CLK_SEL_MASK) 1140 | (clk_src << RT5677_AD_STO1_CLK_SEL_SFT); 1141 } 1142 1143 if (filter_mask & RT5677_AD_STEREO2_FILTER) { 1144 asrc5_mask |= RT5677_AD_STO2_CLK_SEL_MASK; 1145 asrc5_value = (asrc5_value & ~RT5677_AD_STO2_CLK_SEL_MASK) 1146 | (clk_src << RT5677_AD_STO2_CLK_SEL_SFT); 1147 } 1148 1149 if (filter_mask & RT5677_AD_STEREO3_FILTER) { 1150 asrc5_mask |= RT5677_AD_STO3_CLK_SEL_MASK; 1151 asrc5_value = (asrc5_value & ~RT5677_AD_STO3_CLK_SEL_MASK) 1152 | (clk_src << RT5677_AD_STO3_CLK_SEL_SFT); 1153 } 1154 1155 if (filter_mask & RT5677_AD_STEREO4_FILTER) { 1156 asrc5_mask |= RT5677_AD_STO4_CLK_SEL_MASK; 1157 asrc5_value = (asrc5_value & ~RT5677_AD_STO4_CLK_SEL_MASK) 1158 | (clk_src << RT5677_AD_STO4_CLK_SEL_SFT); 1159 } 1160 1161 if (asrc5_mask) 1162 regmap_update_bits(rt5677->regmap, RT5677_ASRC_5, asrc5_mask, 1163 asrc5_value); 1164 1165 /* ASRC 6 */ 1166 if (filter_mask & RT5677_AD_MONO_L_FILTER) { 1167 asrc6_mask |= RT5677_AD_MONOL_CLK_SEL_MASK; 1168 asrc6_value = (asrc6_value & ~RT5677_AD_MONOL_CLK_SEL_MASK) 1169 | (clk_src << RT5677_AD_MONOL_CLK_SEL_SFT); 1170 } 1171 1172 if (filter_mask & RT5677_AD_MONO_R_FILTER) { 1173 asrc6_mask |= RT5677_AD_MONOR_CLK_SEL_MASK; 1174 asrc6_value = (asrc6_value & ~RT5677_AD_MONOR_CLK_SEL_MASK) 1175 | (clk_src << RT5677_AD_MONOR_CLK_SEL_SFT); 1176 } 1177 1178 if (asrc6_mask) 1179 regmap_update_bits(rt5677->regmap, RT5677_ASRC_6, asrc6_mask, 1180 asrc6_value); 1181 1182 /* ASRC 7 */ 1183 if (filter_mask & RT5677_DSP_OB_0_3_FILTER) { 1184 asrc7_mask |= RT5677_DSP_OB_0_3_CLK_SEL_MASK; 1185 asrc7_value = (asrc7_value & ~RT5677_DSP_OB_0_3_CLK_SEL_MASK) 1186 | (clk_src << RT5677_DSP_OB_0_3_CLK_SEL_SFT); 1187 } 1188 1189 if (filter_mask & RT5677_DSP_OB_4_7_FILTER) { 1190 asrc7_mask |= RT5677_DSP_OB_4_7_CLK_SEL_MASK; 1191 asrc7_value = (asrc7_value & ~RT5677_DSP_OB_4_7_CLK_SEL_MASK) 1192 | (clk_src << RT5677_DSP_OB_4_7_CLK_SEL_SFT); 1193 } 1194 1195 if (asrc7_mask) 1196 regmap_update_bits(rt5677->regmap, RT5677_ASRC_7, asrc7_mask, 1197 asrc7_value); 1198 1199 /* ASRC 8 */ 1200 if (filter_mask & RT5677_I2S1_SOURCE) { 1201 asrc8_mask |= RT5677_I2S1_CLK_SEL_MASK; 1202 asrc8_value = (asrc8_value & ~RT5677_I2S1_CLK_SEL_MASK) 1203 | ((clk_src - 1) << RT5677_I2S1_CLK_SEL_SFT); 1204 } 1205 1206 if (filter_mask & RT5677_I2S2_SOURCE) { 1207 asrc8_mask |= RT5677_I2S2_CLK_SEL_MASK; 1208 asrc8_value = (asrc8_value & ~RT5677_I2S2_CLK_SEL_MASK) 1209 | ((clk_src - 1) << RT5677_I2S2_CLK_SEL_SFT); 1210 } 1211 1212 if (filter_mask & RT5677_I2S3_SOURCE) { 1213 asrc8_mask |= RT5677_I2S3_CLK_SEL_MASK; 1214 asrc8_value = (asrc8_value & ~RT5677_I2S3_CLK_SEL_MASK) 1215 | ((clk_src - 1) << RT5677_I2S3_CLK_SEL_SFT); 1216 } 1217 1218 if (filter_mask & RT5677_I2S4_SOURCE) { 1219 asrc8_mask |= RT5677_I2S4_CLK_SEL_MASK; 1220 asrc8_value = (asrc8_value & ~RT5677_I2S4_CLK_SEL_MASK) 1221 | ((clk_src - 1) << RT5677_I2S4_CLK_SEL_SFT); 1222 } 1223 1224 if (asrc8_mask) 1225 regmap_update_bits(rt5677->regmap, RT5677_ASRC_8, asrc8_mask, 1226 asrc8_value); 1227 1228 return 0; 1229 } 1230 EXPORT_SYMBOL_GPL(rt5677_sel_asrc_clk_src); 1231 1232 static int rt5677_dmic_use_asrc(struct snd_soc_dapm_widget *source, 1233 struct snd_soc_dapm_widget *sink) 1234 { 1235 struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm); 1236 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component); 1237 unsigned int asrc_setting; 1238 1239 switch (source->shift) { 1240 case 11: 1241 regmap_read(rt5677->regmap, RT5677_ASRC_5, &asrc_setting); 1242 asrc_setting = (asrc_setting & RT5677_AD_STO1_CLK_SEL_MASK) >> 1243 RT5677_AD_STO1_CLK_SEL_SFT; 1244 break; 1245 1246 case 10: 1247 regmap_read(rt5677->regmap, RT5677_ASRC_5, &asrc_setting); 1248 asrc_setting = (asrc_setting & RT5677_AD_STO2_CLK_SEL_MASK) >> 1249 RT5677_AD_STO2_CLK_SEL_SFT; 1250 break; 1251 1252 case 9: 1253 regmap_read(rt5677->regmap, RT5677_ASRC_5, &asrc_setting); 1254 asrc_setting = (asrc_setting & RT5677_AD_STO3_CLK_SEL_MASK) >> 1255 RT5677_AD_STO3_CLK_SEL_SFT; 1256 break; 1257 1258 case 8: 1259 regmap_read(rt5677->regmap, RT5677_ASRC_5, &asrc_setting); 1260 asrc_setting = (asrc_setting & RT5677_AD_STO4_CLK_SEL_MASK) >> 1261 RT5677_AD_STO4_CLK_SEL_SFT; 1262 break; 1263 1264 case 7: 1265 regmap_read(rt5677->regmap, RT5677_ASRC_6, &asrc_setting); 1266 asrc_setting = (asrc_setting & RT5677_AD_MONOL_CLK_SEL_MASK) >> 1267 RT5677_AD_MONOL_CLK_SEL_SFT; 1268 break; 1269 1270 case 6: 1271 regmap_read(rt5677->regmap, RT5677_ASRC_6, &asrc_setting); 1272 asrc_setting = (asrc_setting & RT5677_AD_MONOR_CLK_SEL_MASK) >> 1273 RT5677_AD_MONOR_CLK_SEL_SFT; 1274 break; 1275 1276 default: 1277 return 0; 1278 } 1279 1280 if (asrc_setting >= RT5677_CLK_SEL_I2S1_ASRC && 1281 asrc_setting <= RT5677_CLK_SEL_I2S6_ASRC) 1282 return 1; 1283 1284 return 0; 1285 } 1286 1287 /* Digital Mixer */ 1288 static const struct snd_kcontrol_new rt5677_sto1_adc_l_mix[] = { 1289 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO1_ADC_MIXER, 1290 RT5677_M_STO1_ADC_L1_SFT, 1, 1), 1291 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO1_ADC_MIXER, 1292 RT5677_M_STO1_ADC_L2_SFT, 1, 1), 1293 }; 1294 1295 static const struct snd_kcontrol_new rt5677_sto1_adc_r_mix[] = { 1296 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO1_ADC_MIXER, 1297 RT5677_M_STO1_ADC_R1_SFT, 1, 1), 1298 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO1_ADC_MIXER, 1299 RT5677_M_STO1_ADC_R2_SFT, 1, 1), 1300 }; 1301 1302 static const struct snd_kcontrol_new rt5677_sto2_adc_l_mix[] = { 1303 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO2_ADC_MIXER, 1304 RT5677_M_STO2_ADC_L1_SFT, 1, 1), 1305 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO2_ADC_MIXER, 1306 RT5677_M_STO2_ADC_L2_SFT, 1, 1), 1307 }; 1308 1309 static const struct snd_kcontrol_new rt5677_sto2_adc_r_mix[] = { 1310 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO2_ADC_MIXER, 1311 RT5677_M_STO2_ADC_R1_SFT, 1, 1), 1312 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO2_ADC_MIXER, 1313 RT5677_M_STO2_ADC_R2_SFT, 1, 1), 1314 }; 1315 1316 static const struct snd_kcontrol_new rt5677_sto3_adc_l_mix[] = { 1317 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO3_ADC_MIXER, 1318 RT5677_M_STO3_ADC_L1_SFT, 1, 1), 1319 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO3_ADC_MIXER, 1320 RT5677_M_STO3_ADC_L2_SFT, 1, 1), 1321 }; 1322 1323 static const struct snd_kcontrol_new rt5677_sto3_adc_r_mix[] = { 1324 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO3_ADC_MIXER, 1325 RT5677_M_STO3_ADC_R1_SFT, 1, 1), 1326 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO3_ADC_MIXER, 1327 RT5677_M_STO3_ADC_R2_SFT, 1, 1), 1328 }; 1329 1330 static const struct snd_kcontrol_new rt5677_sto4_adc_l_mix[] = { 1331 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO4_ADC_MIXER, 1332 RT5677_M_STO4_ADC_L1_SFT, 1, 1), 1333 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO4_ADC_MIXER, 1334 RT5677_M_STO4_ADC_L2_SFT, 1, 1), 1335 }; 1336 1337 static const struct snd_kcontrol_new rt5677_sto4_adc_r_mix[] = { 1338 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO4_ADC_MIXER, 1339 RT5677_M_STO4_ADC_R1_SFT, 1, 1), 1340 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO4_ADC_MIXER, 1341 RT5677_M_STO4_ADC_R2_SFT, 1, 1), 1342 }; 1343 1344 static const struct snd_kcontrol_new rt5677_mono_adc_l_mix[] = { 1345 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_MONO_ADC_MIXER, 1346 RT5677_M_MONO_ADC_L1_SFT, 1, 1), 1347 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_MONO_ADC_MIXER, 1348 RT5677_M_MONO_ADC_L2_SFT, 1, 1), 1349 }; 1350 1351 static const struct snd_kcontrol_new rt5677_mono_adc_r_mix[] = { 1352 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_MONO_ADC_MIXER, 1353 RT5677_M_MONO_ADC_R1_SFT, 1, 1), 1354 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_MONO_ADC_MIXER, 1355 RT5677_M_MONO_ADC_R2_SFT, 1, 1), 1356 }; 1357 1358 static const struct snd_kcontrol_new rt5677_dac_l_mix[] = { 1359 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5677_ADC_IF_DSP_DAC1_MIXER, 1360 RT5677_M_ADDA_MIXER1_L_SFT, 1, 1), 1361 SOC_DAPM_SINGLE("DAC1 Switch", RT5677_ADC_IF_DSP_DAC1_MIXER, 1362 RT5677_M_DAC1_L_SFT, 1, 1), 1363 }; 1364 1365 static const struct snd_kcontrol_new rt5677_dac_r_mix[] = { 1366 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5677_ADC_IF_DSP_DAC1_MIXER, 1367 RT5677_M_ADDA_MIXER1_R_SFT, 1, 1), 1368 SOC_DAPM_SINGLE("DAC1 Switch", RT5677_ADC_IF_DSP_DAC1_MIXER, 1369 RT5677_M_DAC1_R_SFT, 1, 1), 1370 }; 1371 1372 static const struct snd_kcontrol_new rt5677_sto1_dac_l_mix[] = { 1373 SOC_DAPM_SINGLE_AUTODISABLE("ST L Switch", RT5677_STO1_DAC_MIXER, 1374 RT5677_M_ST_DAC1_L_SFT, 1, 1), 1375 SOC_DAPM_SINGLE_AUTODISABLE("DAC1 L Switch", RT5677_STO1_DAC_MIXER, 1376 RT5677_M_DAC1_L_STO_L_SFT, 1, 1), 1377 SOC_DAPM_SINGLE_AUTODISABLE("DAC2 L Switch", RT5677_STO1_DAC_MIXER, 1378 RT5677_M_DAC2_L_STO_L_SFT, 1, 1), 1379 SOC_DAPM_SINGLE_AUTODISABLE("DAC1 R Switch", RT5677_STO1_DAC_MIXER, 1380 RT5677_M_DAC1_R_STO_L_SFT, 1, 1), 1381 }; 1382 1383 static const struct snd_kcontrol_new rt5677_sto1_dac_r_mix[] = { 1384 SOC_DAPM_SINGLE_AUTODISABLE("ST R Switch", RT5677_STO1_DAC_MIXER, 1385 RT5677_M_ST_DAC1_R_SFT, 1, 1), 1386 SOC_DAPM_SINGLE_AUTODISABLE("DAC1 R Switch", RT5677_STO1_DAC_MIXER, 1387 RT5677_M_DAC1_R_STO_R_SFT, 1, 1), 1388 SOC_DAPM_SINGLE_AUTODISABLE("DAC2 R Switch", RT5677_STO1_DAC_MIXER, 1389 RT5677_M_DAC2_R_STO_R_SFT, 1, 1), 1390 SOC_DAPM_SINGLE_AUTODISABLE("DAC1 L Switch", RT5677_STO1_DAC_MIXER, 1391 RT5677_M_DAC1_L_STO_R_SFT, 1, 1), 1392 }; 1393 1394 static const struct snd_kcontrol_new rt5677_mono_dac_l_mix[] = { 1395 SOC_DAPM_SINGLE_AUTODISABLE("ST L Switch", RT5677_MONO_DAC_MIXER, 1396 RT5677_M_ST_DAC2_L_SFT, 1, 1), 1397 SOC_DAPM_SINGLE_AUTODISABLE("DAC1 L Switch", RT5677_MONO_DAC_MIXER, 1398 RT5677_M_DAC1_L_MONO_L_SFT, 1, 1), 1399 SOC_DAPM_SINGLE_AUTODISABLE("DAC2 L Switch", RT5677_MONO_DAC_MIXER, 1400 RT5677_M_DAC2_L_MONO_L_SFT, 1, 1), 1401 SOC_DAPM_SINGLE_AUTODISABLE("DAC2 R Switch", RT5677_MONO_DAC_MIXER, 1402 RT5677_M_DAC2_R_MONO_L_SFT, 1, 1), 1403 }; 1404 1405 static const struct snd_kcontrol_new rt5677_mono_dac_r_mix[] = { 1406 SOC_DAPM_SINGLE_AUTODISABLE("ST R Switch", RT5677_MONO_DAC_MIXER, 1407 RT5677_M_ST_DAC2_R_SFT, 1, 1), 1408 SOC_DAPM_SINGLE_AUTODISABLE("DAC1 R Switch", RT5677_MONO_DAC_MIXER, 1409 RT5677_M_DAC1_R_MONO_R_SFT, 1, 1), 1410 SOC_DAPM_SINGLE_AUTODISABLE("DAC2 R Switch", RT5677_MONO_DAC_MIXER, 1411 RT5677_M_DAC2_R_MONO_R_SFT, 1, 1), 1412 SOC_DAPM_SINGLE_AUTODISABLE("DAC2 L Switch", RT5677_MONO_DAC_MIXER, 1413 RT5677_M_DAC2_L_MONO_R_SFT, 1, 1), 1414 }; 1415 1416 static const struct snd_kcontrol_new rt5677_dd1_l_mix[] = { 1417 SOC_DAPM_SINGLE_AUTODISABLE("Sto DAC Mix L Switch", RT5677_DD1_MIXER, 1418 RT5677_M_STO_L_DD1_L_SFT, 1, 1), 1419 SOC_DAPM_SINGLE_AUTODISABLE("Mono DAC Mix L Switch", RT5677_DD1_MIXER, 1420 RT5677_M_MONO_L_DD1_L_SFT, 1, 1), 1421 SOC_DAPM_SINGLE_AUTODISABLE("DAC3 L Switch", RT5677_DD1_MIXER, 1422 RT5677_M_DAC3_L_DD1_L_SFT, 1, 1), 1423 SOC_DAPM_SINGLE_AUTODISABLE("DAC3 R Switch", RT5677_DD1_MIXER, 1424 RT5677_M_DAC3_R_DD1_L_SFT, 1, 1), 1425 }; 1426 1427 static const struct snd_kcontrol_new rt5677_dd1_r_mix[] = { 1428 SOC_DAPM_SINGLE_AUTODISABLE("Sto DAC Mix R Switch", RT5677_DD1_MIXER, 1429 RT5677_M_STO_R_DD1_R_SFT, 1, 1), 1430 SOC_DAPM_SINGLE_AUTODISABLE("Mono DAC Mix R Switch", RT5677_DD1_MIXER, 1431 RT5677_M_MONO_R_DD1_R_SFT, 1, 1), 1432 SOC_DAPM_SINGLE_AUTODISABLE("DAC3 R Switch", RT5677_DD1_MIXER, 1433 RT5677_M_DAC3_R_DD1_R_SFT, 1, 1), 1434 SOC_DAPM_SINGLE_AUTODISABLE("DAC3 L Switch", RT5677_DD1_MIXER, 1435 RT5677_M_DAC3_L_DD1_R_SFT, 1, 1), 1436 }; 1437 1438 static const struct snd_kcontrol_new rt5677_dd2_l_mix[] = { 1439 SOC_DAPM_SINGLE_AUTODISABLE("Sto DAC Mix L Switch", RT5677_DD2_MIXER, 1440 RT5677_M_STO_L_DD2_L_SFT, 1, 1), 1441 SOC_DAPM_SINGLE_AUTODISABLE("Mono DAC Mix L Switch", RT5677_DD2_MIXER, 1442 RT5677_M_MONO_L_DD2_L_SFT, 1, 1), 1443 SOC_DAPM_SINGLE_AUTODISABLE("DAC4 L Switch", RT5677_DD2_MIXER, 1444 RT5677_M_DAC4_L_DD2_L_SFT, 1, 1), 1445 SOC_DAPM_SINGLE_AUTODISABLE("DAC4 R Switch", RT5677_DD2_MIXER, 1446 RT5677_M_DAC4_R_DD2_L_SFT, 1, 1), 1447 }; 1448 1449 static const struct snd_kcontrol_new rt5677_dd2_r_mix[] = { 1450 SOC_DAPM_SINGLE_AUTODISABLE("Sto DAC Mix R Switch", RT5677_DD2_MIXER, 1451 RT5677_M_STO_R_DD2_R_SFT, 1, 1), 1452 SOC_DAPM_SINGLE_AUTODISABLE("Mono DAC Mix R Switch", RT5677_DD2_MIXER, 1453 RT5677_M_MONO_R_DD2_R_SFT, 1, 1), 1454 SOC_DAPM_SINGLE_AUTODISABLE("DAC4 R Switch", RT5677_DD2_MIXER, 1455 RT5677_M_DAC4_R_DD2_R_SFT, 1, 1), 1456 SOC_DAPM_SINGLE_AUTODISABLE("DAC4 L Switch", RT5677_DD2_MIXER, 1457 RT5677_M_DAC4_L_DD2_R_SFT, 1, 1), 1458 }; 1459 1460 static const struct snd_kcontrol_new rt5677_ob_01_mix[] = { 1461 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL, 1462 RT5677_DSP_IB_01_H_SFT, 1, 1), 1463 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL, 1464 RT5677_DSP_IB_23_H_SFT, 1, 1), 1465 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL, 1466 RT5677_DSP_IB_45_H_SFT, 1, 1), 1467 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL, 1468 RT5677_DSP_IB_6_H_SFT, 1, 1), 1469 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL, 1470 RT5677_DSP_IB_7_H_SFT, 1, 1), 1471 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL, 1472 RT5677_DSP_IB_8_H_SFT, 1, 1), 1473 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL, 1474 RT5677_DSP_IB_9_H_SFT, 1, 1), 1475 }; 1476 1477 static const struct snd_kcontrol_new rt5677_ob_23_mix[] = { 1478 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL, 1479 RT5677_DSP_IB_01_L_SFT, 1, 1), 1480 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL, 1481 RT5677_DSP_IB_23_L_SFT, 1, 1), 1482 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL, 1483 RT5677_DSP_IB_45_L_SFT, 1, 1), 1484 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL, 1485 RT5677_DSP_IB_6_L_SFT, 1, 1), 1486 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL, 1487 RT5677_DSP_IB_7_L_SFT, 1, 1), 1488 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL, 1489 RT5677_DSP_IB_8_L_SFT, 1, 1), 1490 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL, 1491 RT5677_DSP_IB_9_L_SFT, 1, 1), 1492 }; 1493 1494 static const struct snd_kcontrol_new rt5677_ob_4_mix[] = { 1495 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL, 1496 RT5677_DSP_IB_01_H_SFT, 1, 1), 1497 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL, 1498 RT5677_DSP_IB_23_H_SFT, 1, 1), 1499 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL, 1500 RT5677_DSP_IB_45_H_SFT, 1, 1), 1501 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL, 1502 RT5677_DSP_IB_6_H_SFT, 1, 1), 1503 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL, 1504 RT5677_DSP_IB_7_H_SFT, 1, 1), 1505 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL, 1506 RT5677_DSP_IB_8_H_SFT, 1, 1), 1507 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL, 1508 RT5677_DSP_IB_9_H_SFT, 1, 1), 1509 }; 1510 1511 static const struct snd_kcontrol_new rt5677_ob_5_mix[] = { 1512 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL, 1513 RT5677_DSP_IB_01_L_SFT, 1, 1), 1514 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL, 1515 RT5677_DSP_IB_23_L_SFT, 1, 1), 1516 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL, 1517 RT5677_DSP_IB_45_L_SFT, 1, 1), 1518 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL, 1519 RT5677_DSP_IB_6_L_SFT, 1, 1), 1520 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL, 1521 RT5677_DSP_IB_7_L_SFT, 1, 1), 1522 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL, 1523 RT5677_DSP_IB_8_L_SFT, 1, 1), 1524 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL, 1525 RT5677_DSP_IB_9_L_SFT, 1, 1), 1526 }; 1527 1528 static const struct snd_kcontrol_new rt5677_ob_6_mix[] = { 1529 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL, 1530 RT5677_DSP_IB_01_H_SFT, 1, 1), 1531 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL, 1532 RT5677_DSP_IB_23_H_SFT, 1, 1), 1533 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL, 1534 RT5677_DSP_IB_45_H_SFT, 1, 1), 1535 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL, 1536 RT5677_DSP_IB_6_H_SFT, 1, 1), 1537 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL, 1538 RT5677_DSP_IB_7_H_SFT, 1, 1), 1539 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL, 1540 RT5677_DSP_IB_8_H_SFT, 1, 1), 1541 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL, 1542 RT5677_DSP_IB_9_H_SFT, 1, 1), 1543 }; 1544 1545 static const struct snd_kcontrol_new rt5677_ob_7_mix[] = { 1546 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL, 1547 RT5677_DSP_IB_01_L_SFT, 1, 1), 1548 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL, 1549 RT5677_DSP_IB_23_L_SFT, 1, 1), 1550 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL, 1551 RT5677_DSP_IB_45_L_SFT, 1, 1), 1552 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL, 1553 RT5677_DSP_IB_6_L_SFT, 1, 1), 1554 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL, 1555 RT5677_DSP_IB_7_L_SFT, 1, 1), 1556 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL, 1557 RT5677_DSP_IB_8_L_SFT, 1, 1), 1558 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL, 1559 RT5677_DSP_IB_9_L_SFT, 1, 1), 1560 }; 1561 1562 1563 /* Mux */ 1564 /* DAC1 L/R Source */ /* MX-29 [10:8] */ 1565 static const char * const rt5677_dac1_src[] = { 1566 "IF1 DAC 01", "IF2 DAC 01", "IF3 DAC LR", "IF4 DAC LR", "SLB DAC 01", 1567 "OB 01" 1568 }; 1569 1570 static SOC_ENUM_SINGLE_DECL( 1571 rt5677_dac1_enum, RT5677_ADC_IF_DSP_DAC1_MIXER, 1572 RT5677_DAC1_L_SEL_SFT, rt5677_dac1_src); 1573 1574 static const struct snd_kcontrol_new rt5677_dac1_mux = 1575 SOC_DAPM_ENUM("DAC1 Source", rt5677_dac1_enum); 1576 1577 /* ADDA1 L/R Source */ /* MX-29 [1:0] */ 1578 static const char * const rt5677_adda1_src[] = { 1579 "STO1 ADC MIX", "STO2 ADC MIX", "OB 67", 1580 }; 1581 1582 static SOC_ENUM_SINGLE_DECL( 1583 rt5677_adda1_enum, RT5677_ADC_IF_DSP_DAC1_MIXER, 1584 RT5677_ADDA1_SEL_SFT, rt5677_adda1_src); 1585 1586 static const struct snd_kcontrol_new rt5677_adda1_mux = 1587 SOC_DAPM_ENUM("ADDA1 Source", rt5677_adda1_enum); 1588 1589 1590 /*DAC2 L/R Source*/ /* MX-1B [6:4] [2:0] */ 1591 static const char * const rt5677_dac2l_src[] = { 1592 "IF1 DAC 2", "IF2 DAC 2", "IF3 DAC L", "IF4 DAC L", "SLB DAC 2", 1593 "OB 2", 1594 }; 1595 1596 static SOC_ENUM_SINGLE_DECL( 1597 rt5677_dac2l_enum, RT5677_IF_DSP_DAC2_MIXER, 1598 RT5677_SEL_DAC2_L_SRC_SFT, rt5677_dac2l_src); 1599 1600 static const struct snd_kcontrol_new rt5677_dac2_l_mux = 1601 SOC_DAPM_ENUM("DAC2 L Source", rt5677_dac2l_enum); 1602 1603 static const char * const rt5677_dac2r_src[] = { 1604 "IF1 DAC 3", "IF2 DAC 3", "IF3 DAC R", "IF4 DAC R", "SLB DAC 3", 1605 "OB 3", "Haptic Generator", "VAD ADC" 1606 }; 1607 1608 static SOC_ENUM_SINGLE_DECL( 1609 rt5677_dac2r_enum, RT5677_IF_DSP_DAC2_MIXER, 1610 RT5677_SEL_DAC2_R_SRC_SFT, rt5677_dac2r_src); 1611 1612 static const struct snd_kcontrol_new rt5677_dac2_r_mux = 1613 SOC_DAPM_ENUM("DAC2 R Source", rt5677_dac2r_enum); 1614 1615 /*DAC3 L/R Source*/ /* MX-16 [6:4] [2:0] */ 1616 static const char * const rt5677_dac3l_src[] = { 1617 "IF1 DAC 4", "IF2 DAC 4", "IF3 DAC L", "IF4 DAC L", 1618 "SLB DAC 4", "OB 4" 1619 }; 1620 1621 static SOC_ENUM_SINGLE_DECL( 1622 rt5677_dac3l_enum, RT5677_IF_DSP_DAC3_4_MIXER, 1623 RT5677_SEL_DAC3_L_SRC_SFT, rt5677_dac3l_src); 1624 1625 static const struct snd_kcontrol_new rt5677_dac3_l_mux = 1626 SOC_DAPM_ENUM("DAC3 L Source", rt5677_dac3l_enum); 1627 1628 static const char * const rt5677_dac3r_src[] = { 1629 "IF1 DAC 5", "IF2 DAC 5", "IF3 DAC R", "IF4 DAC R", 1630 "SLB DAC 5", "OB 5" 1631 }; 1632 1633 static SOC_ENUM_SINGLE_DECL( 1634 rt5677_dac3r_enum, RT5677_IF_DSP_DAC3_4_MIXER, 1635 RT5677_SEL_DAC3_R_SRC_SFT, rt5677_dac3r_src); 1636 1637 static const struct snd_kcontrol_new rt5677_dac3_r_mux = 1638 SOC_DAPM_ENUM("DAC3 R Source", rt5677_dac3r_enum); 1639 1640 /*DAC4 L/R Source*/ /* MX-16 [14:12] [10:8] */ 1641 static const char * const rt5677_dac4l_src[] = { 1642 "IF1 DAC 6", "IF2 DAC 6", "IF3 DAC L", "IF4 DAC L", 1643 "SLB DAC 6", "OB 6" 1644 }; 1645 1646 static SOC_ENUM_SINGLE_DECL( 1647 rt5677_dac4l_enum, RT5677_IF_DSP_DAC3_4_MIXER, 1648 RT5677_SEL_DAC4_L_SRC_SFT, rt5677_dac4l_src); 1649 1650 static const struct snd_kcontrol_new rt5677_dac4_l_mux = 1651 SOC_DAPM_ENUM("DAC4 L Source", rt5677_dac4l_enum); 1652 1653 static const char * const rt5677_dac4r_src[] = { 1654 "IF1 DAC 7", "IF2 DAC 7", "IF3 DAC R", "IF4 DAC R", 1655 "SLB DAC 7", "OB 7" 1656 }; 1657 1658 static SOC_ENUM_SINGLE_DECL( 1659 rt5677_dac4r_enum, RT5677_IF_DSP_DAC3_4_MIXER, 1660 RT5677_SEL_DAC4_R_SRC_SFT, rt5677_dac4r_src); 1661 1662 static const struct snd_kcontrol_new rt5677_dac4_r_mux = 1663 SOC_DAPM_ENUM("DAC4 R Source", rt5677_dac4r_enum); 1664 1665 /* In/OutBound Source Pass SRC */ /* MX-A5 [3] [4] [0] [1] [2] */ 1666 static const char * const rt5677_iob_bypass_src[] = { 1667 "Bypass", "Pass SRC" 1668 }; 1669 1670 static SOC_ENUM_SINGLE_DECL( 1671 rt5677_ob01_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL, 1672 RT5677_SEL_SRC_OB01_SFT, rt5677_iob_bypass_src); 1673 1674 static const struct snd_kcontrol_new rt5677_ob01_bypass_src_mux = 1675 SOC_DAPM_ENUM("OB01 Bypass Source", rt5677_ob01_bypass_src_enum); 1676 1677 static SOC_ENUM_SINGLE_DECL( 1678 rt5677_ob23_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL, 1679 RT5677_SEL_SRC_OB23_SFT, rt5677_iob_bypass_src); 1680 1681 static const struct snd_kcontrol_new rt5677_ob23_bypass_src_mux = 1682 SOC_DAPM_ENUM("OB23 Bypass Source", rt5677_ob23_bypass_src_enum); 1683 1684 static SOC_ENUM_SINGLE_DECL( 1685 rt5677_ib01_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL, 1686 RT5677_SEL_SRC_IB01_SFT, rt5677_iob_bypass_src); 1687 1688 static const struct snd_kcontrol_new rt5677_ib01_bypass_src_mux = 1689 SOC_DAPM_ENUM("IB01 Bypass Source", rt5677_ib01_bypass_src_enum); 1690 1691 static SOC_ENUM_SINGLE_DECL( 1692 rt5677_ib23_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL, 1693 RT5677_SEL_SRC_IB23_SFT, rt5677_iob_bypass_src); 1694 1695 static const struct snd_kcontrol_new rt5677_ib23_bypass_src_mux = 1696 SOC_DAPM_ENUM("IB23 Bypass Source", rt5677_ib23_bypass_src_enum); 1697 1698 static SOC_ENUM_SINGLE_DECL( 1699 rt5677_ib45_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL, 1700 RT5677_SEL_SRC_IB45_SFT, rt5677_iob_bypass_src); 1701 1702 static const struct snd_kcontrol_new rt5677_ib45_bypass_src_mux = 1703 SOC_DAPM_ENUM("IB45 Bypass Source", rt5677_ib45_bypass_src_enum); 1704 1705 /* Stereo ADC Source 2 */ /* MX-27 MX26 MX25 [11:10] */ 1706 static const char * const rt5677_stereo_adc2_src[] = { 1707 "DD MIX1", "DMIC", "Stereo DAC MIX" 1708 }; 1709 1710 static SOC_ENUM_SINGLE_DECL( 1711 rt5677_stereo1_adc2_enum, RT5677_STO1_ADC_MIXER, 1712 RT5677_SEL_STO1_ADC2_SFT, rt5677_stereo_adc2_src); 1713 1714 static const struct snd_kcontrol_new rt5677_sto1_adc2_mux = 1715 SOC_DAPM_ENUM("Stereo1 ADC2 Source", rt5677_stereo1_adc2_enum); 1716 1717 static SOC_ENUM_SINGLE_DECL( 1718 rt5677_stereo2_adc2_enum, RT5677_STO2_ADC_MIXER, 1719 RT5677_SEL_STO2_ADC2_SFT, rt5677_stereo_adc2_src); 1720 1721 static const struct snd_kcontrol_new rt5677_sto2_adc2_mux = 1722 SOC_DAPM_ENUM("Stereo2 ADC2 Source", rt5677_stereo2_adc2_enum); 1723 1724 static SOC_ENUM_SINGLE_DECL( 1725 rt5677_stereo3_adc2_enum, RT5677_STO3_ADC_MIXER, 1726 RT5677_SEL_STO3_ADC2_SFT, rt5677_stereo_adc2_src); 1727 1728 static const struct snd_kcontrol_new rt5677_sto3_adc2_mux = 1729 SOC_DAPM_ENUM("Stereo3 ADC2 Source", rt5677_stereo3_adc2_enum); 1730 1731 /* DMIC Source */ /* MX-28 [9:8][1:0] MX-27 MX-26 MX-25 MX-24 [9:8] */ 1732 static const char * const rt5677_dmic_src[] = { 1733 "DMIC1", "DMIC2", "DMIC3", "DMIC4" 1734 }; 1735 1736 static SOC_ENUM_SINGLE_DECL( 1737 rt5677_mono_dmic_l_enum, RT5677_MONO_ADC_MIXER, 1738 RT5677_SEL_MONO_DMIC_L_SFT, rt5677_dmic_src); 1739 1740 static const struct snd_kcontrol_new rt5677_mono_dmic_l_mux = 1741 SOC_DAPM_ENUM("Mono DMIC L Source", rt5677_mono_dmic_l_enum); 1742 1743 static SOC_ENUM_SINGLE_DECL( 1744 rt5677_mono_dmic_r_enum, RT5677_MONO_ADC_MIXER, 1745 RT5677_SEL_MONO_DMIC_R_SFT, rt5677_dmic_src); 1746 1747 static const struct snd_kcontrol_new rt5677_mono_dmic_r_mux = 1748 SOC_DAPM_ENUM("Mono DMIC R Source", rt5677_mono_dmic_r_enum); 1749 1750 static SOC_ENUM_SINGLE_DECL( 1751 rt5677_stereo1_dmic_enum, RT5677_STO1_ADC_MIXER, 1752 RT5677_SEL_STO1_DMIC_SFT, rt5677_dmic_src); 1753 1754 static const struct snd_kcontrol_new rt5677_sto1_dmic_mux = 1755 SOC_DAPM_ENUM("Stereo1 DMIC Source", rt5677_stereo1_dmic_enum); 1756 1757 static SOC_ENUM_SINGLE_DECL( 1758 rt5677_stereo2_dmic_enum, RT5677_STO2_ADC_MIXER, 1759 RT5677_SEL_STO2_DMIC_SFT, rt5677_dmic_src); 1760 1761 static const struct snd_kcontrol_new rt5677_sto2_dmic_mux = 1762 SOC_DAPM_ENUM("Stereo2 DMIC Source", rt5677_stereo2_dmic_enum); 1763 1764 static SOC_ENUM_SINGLE_DECL( 1765 rt5677_stereo3_dmic_enum, RT5677_STO3_ADC_MIXER, 1766 RT5677_SEL_STO3_DMIC_SFT, rt5677_dmic_src); 1767 1768 static const struct snd_kcontrol_new rt5677_sto3_dmic_mux = 1769 SOC_DAPM_ENUM("Stereo3 DMIC Source", rt5677_stereo3_dmic_enum); 1770 1771 static SOC_ENUM_SINGLE_DECL( 1772 rt5677_stereo4_dmic_enum, RT5677_STO4_ADC_MIXER, 1773 RT5677_SEL_STO4_DMIC_SFT, rt5677_dmic_src); 1774 1775 static const struct snd_kcontrol_new rt5677_sto4_dmic_mux = 1776 SOC_DAPM_ENUM("Stereo4 DMIC Source", rt5677_stereo4_dmic_enum); 1777 1778 /* Stereo2 ADC Source */ /* MX-26 [0] */ 1779 static const char * const rt5677_stereo2_adc_lr_src[] = { 1780 "L", "LR" 1781 }; 1782 1783 static SOC_ENUM_SINGLE_DECL( 1784 rt5677_stereo2_adc_lr_enum, RT5677_STO2_ADC_MIXER, 1785 RT5677_SEL_STO2_LR_MIX_SFT, rt5677_stereo2_adc_lr_src); 1786 1787 static const struct snd_kcontrol_new rt5677_sto2_adc_lr_mux = 1788 SOC_DAPM_ENUM("Stereo2 ADC LR Source", rt5677_stereo2_adc_lr_enum); 1789 1790 /* Stereo1 ADC Source 1 */ /* MX-27 MX26 MX25 [13:12] */ 1791 static const char * const rt5677_stereo_adc1_src[] = { 1792 "DD MIX1", "ADC1/2", "Stereo DAC MIX" 1793 }; 1794 1795 static SOC_ENUM_SINGLE_DECL( 1796 rt5677_stereo1_adc1_enum, RT5677_STO1_ADC_MIXER, 1797 RT5677_SEL_STO1_ADC1_SFT, rt5677_stereo_adc1_src); 1798 1799 static const struct snd_kcontrol_new rt5677_sto1_adc1_mux = 1800 SOC_DAPM_ENUM("Stereo1 ADC1 Source", rt5677_stereo1_adc1_enum); 1801 1802 static SOC_ENUM_SINGLE_DECL( 1803 rt5677_stereo2_adc1_enum, RT5677_STO2_ADC_MIXER, 1804 RT5677_SEL_STO2_ADC1_SFT, rt5677_stereo_adc1_src); 1805 1806 static const struct snd_kcontrol_new rt5677_sto2_adc1_mux = 1807 SOC_DAPM_ENUM("Stereo2 ADC1 Source", rt5677_stereo2_adc1_enum); 1808 1809 static SOC_ENUM_SINGLE_DECL( 1810 rt5677_stereo3_adc1_enum, RT5677_STO3_ADC_MIXER, 1811 RT5677_SEL_STO3_ADC1_SFT, rt5677_stereo_adc1_src); 1812 1813 static const struct snd_kcontrol_new rt5677_sto3_adc1_mux = 1814 SOC_DAPM_ENUM("Stereo3 ADC1 Source", rt5677_stereo3_adc1_enum); 1815 1816 /* Mono ADC Left Source 2 */ /* MX-28 [11:10] */ 1817 static const char * const rt5677_mono_adc2_l_src[] = { 1818 "DD MIX1L", "DMIC", "MONO DAC MIXL" 1819 }; 1820 1821 static SOC_ENUM_SINGLE_DECL( 1822 rt5677_mono_adc2_l_enum, RT5677_MONO_ADC_MIXER, 1823 RT5677_SEL_MONO_ADC_L2_SFT, rt5677_mono_adc2_l_src); 1824 1825 static const struct snd_kcontrol_new rt5677_mono_adc2_l_mux = 1826 SOC_DAPM_ENUM("Mono ADC2 L Source", rt5677_mono_adc2_l_enum); 1827 1828 /* Mono ADC Left Source 1 */ /* MX-28 [13:12] */ 1829 static const char * const rt5677_mono_adc1_l_src[] = { 1830 "DD MIX1L", "ADC1", "MONO DAC MIXL" 1831 }; 1832 1833 static SOC_ENUM_SINGLE_DECL( 1834 rt5677_mono_adc1_l_enum, RT5677_MONO_ADC_MIXER, 1835 RT5677_SEL_MONO_ADC_L1_SFT, rt5677_mono_adc1_l_src); 1836 1837 static const struct snd_kcontrol_new rt5677_mono_adc1_l_mux = 1838 SOC_DAPM_ENUM("Mono ADC1 L Source", rt5677_mono_adc1_l_enum); 1839 1840 /* Mono ADC Right Source 2 */ /* MX-28 [3:2] */ 1841 static const char * const rt5677_mono_adc2_r_src[] = { 1842 "DD MIX1R", "DMIC", "MONO DAC MIXR" 1843 }; 1844 1845 static SOC_ENUM_SINGLE_DECL( 1846 rt5677_mono_adc2_r_enum, RT5677_MONO_ADC_MIXER, 1847 RT5677_SEL_MONO_ADC_R2_SFT, rt5677_mono_adc2_r_src); 1848 1849 static const struct snd_kcontrol_new rt5677_mono_adc2_r_mux = 1850 SOC_DAPM_ENUM("Mono ADC2 R Source", rt5677_mono_adc2_r_enum); 1851 1852 /* Mono ADC Right Source 1 */ /* MX-28 [5:4] */ 1853 static const char * const rt5677_mono_adc1_r_src[] = { 1854 "DD MIX1R", "ADC2", "MONO DAC MIXR" 1855 }; 1856 1857 static SOC_ENUM_SINGLE_DECL( 1858 rt5677_mono_adc1_r_enum, RT5677_MONO_ADC_MIXER, 1859 RT5677_SEL_MONO_ADC_R1_SFT, rt5677_mono_adc1_r_src); 1860 1861 static const struct snd_kcontrol_new rt5677_mono_adc1_r_mux = 1862 SOC_DAPM_ENUM("Mono ADC1 R Source", rt5677_mono_adc1_r_enum); 1863 1864 /* Stereo4 ADC Source 2 */ /* MX-24 [11:10] */ 1865 static const char * const rt5677_stereo4_adc2_src[] = { 1866 "DD MIX1", "DMIC", "DD MIX2" 1867 }; 1868 1869 static SOC_ENUM_SINGLE_DECL( 1870 rt5677_stereo4_adc2_enum, RT5677_STO4_ADC_MIXER, 1871 RT5677_SEL_STO4_ADC2_SFT, rt5677_stereo4_adc2_src); 1872 1873 static const struct snd_kcontrol_new rt5677_sto4_adc2_mux = 1874 SOC_DAPM_ENUM("Stereo4 ADC2 Source", rt5677_stereo4_adc2_enum); 1875 1876 1877 /* Stereo4 ADC Source 1 */ /* MX-24 [13:12] */ 1878 static const char * const rt5677_stereo4_adc1_src[] = { 1879 "DD MIX1", "ADC1/2", "DD MIX2" 1880 }; 1881 1882 static SOC_ENUM_SINGLE_DECL( 1883 rt5677_stereo4_adc1_enum, RT5677_STO4_ADC_MIXER, 1884 RT5677_SEL_STO4_ADC1_SFT, rt5677_stereo4_adc1_src); 1885 1886 static const struct snd_kcontrol_new rt5677_sto4_adc1_mux = 1887 SOC_DAPM_ENUM("Stereo4 ADC1 Source", rt5677_stereo4_adc1_enum); 1888 1889 /* InBound0/1 Source */ /* MX-A3 [14:12] */ 1890 static const char * const rt5677_inbound01_src[] = { 1891 "IF1 DAC 01", "IF2 DAC 01", "SLB DAC 01", "STO1 ADC MIX", 1892 "VAD ADC/DAC1 FS" 1893 }; 1894 1895 static SOC_ENUM_SINGLE_DECL( 1896 rt5677_inbound01_enum, RT5677_DSP_INB_CTRL1, 1897 RT5677_IB01_SRC_SFT, rt5677_inbound01_src); 1898 1899 static const struct snd_kcontrol_new rt5677_ib01_src_mux = 1900 SOC_DAPM_ENUM("InBound0/1 Source", rt5677_inbound01_enum); 1901 1902 /* InBound2/3 Source */ /* MX-A3 [10:8] */ 1903 static const char * const rt5677_inbound23_src[] = { 1904 "IF1 DAC 23", "IF2 DAC 23", "SLB DAC 23", "STO2 ADC MIX", 1905 "DAC1 FS", "IF4 DAC" 1906 }; 1907 1908 static SOC_ENUM_SINGLE_DECL( 1909 rt5677_inbound23_enum, RT5677_DSP_INB_CTRL1, 1910 RT5677_IB23_SRC_SFT, rt5677_inbound23_src); 1911 1912 static const struct snd_kcontrol_new rt5677_ib23_src_mux = 1913 SOC_DAPM_ENUM("InBound2/3 Source", rt5677_inbound23_enum); 1914 1915 /* InBound4/5 Source */ /* MX-A3 [6:4] */ 1916 static const char * const rt5677_inbound45_src[] = { 1917 "IF1 DAC 45", "IF2 DAC 45", "SLB DAC 45", "STO3 ADC MIX", 1918 "IF3 DAC" 1919 }; 1920 1921 static SOC_ENUM_SINGLE_DECL( 1922 rt5677_inbound45_enum, RT5677_DSP_INB_CTRL1, 1923 RT5677_IB45_SRC_SFT, rt5677_inbound45_src); 1924 1925 static const struct snd_kcontrol_new rt5677_ib45_src_mux = 1926 SOC_DAPM_ENUM("InBound4/5 Source", rt5677_inbound45_enum); 1927 1928 /* InBound6 Source */ /* MX-A3 [2:0] */ 1929 static const char * const rt5677_inbound6_src[] = { 1930 "IF1 DAC 6", "IF2 DAC 6", "SLB DAC 6", "STO4 ADC MIX L", 1931 "IF4 DAC L", "STO1 ADC MIX L", "STO2 ADC MIX L", "STO3 ADC MIX L" 1932 }; 1933 1934 static SOC_ENUM_SINGLE_DECL( 1935 rt5677_inbound6_enum, RT5677_DSP_INB_CTRL1, 1936 RT5677_IB6_SRC_SFT, rt5677_inbound6_src); 1937 1938 static const struct snd_kcontrol_new rt5677_ib6_src_mux = 1939 SOC_DAPM_ENUM("InBound6 Source", rt5677_inbound6_enum); 1940 1941 /* InBound7 Source */ /* MX-A4 [14:12] */ 1942 static const char * const rt5677_inbound7_src[] = { 1943 "IF1 DAC 7", "IF2 DAC 7", "SLB DAC 7", "STO4 ADC MIX R", 1944 "IF4 DAC R", "STO1 ADC MIX R", "STO2 ADC MIX R", "STO3 ADC MIX R" 1945 }; 1946 1947 static SOC_ENUM_SINGLE_DECL( 1948 rt5677_inbound7_enum, RT5677_DSP_INB_CTRL2, 1949 RT5677_IB7_SRC_SFT, rt5677_inbound7_src); 1950 1951 static const struct snd_kcontrol_new rt5677_ib7_src_mux = 1952 SOC_DAPM_ENUM("InBound7 Source", rt5677_inbound7_enum); 1953 1954 /* InBound8 Source */ /* MX-A4 [10:8] */ 1955 static const char * const rt5677_inbound8_src[] = { 1956 "STO1 ADC MIX L", "STO2 ADC MIX L", "STO3 ADC MIX L", "STO4 ADC MIX L", 1957 "MONO ADC MIX L", "DACL1 FS" 1958 }; 1959 1960 static SOC_ENUM_SINGLE_DECL( 1961 rt5677_inbound8_enum, RT5677_DSP_INB_CTRL2, 1962 RT5677_IB8_SRC_SFT, rt5677_inbound8_src); 1963 1964 static const struct snd_kcontrol_new rt5677_ib8_src_mux = 1965 SOC_DAPM_ENUM("InBound8 Source", rt5677_inbound8_enum); 1966 1967 /* InBound9 Source */ /* MX-A4 [6:4] */ 1968 static const char * const rt5677_inbound9_src[] = { 1969 "STO1 ADC MIX R", "STO2 ADC MIX R", "STO3 ADC MIX R", "STO4 ADC MIX R", 1970 "MONO ADC MIX R", "DACR1 FS", "DAC1 FS" 1971 }; 1972 1973 static SOC_ENUM_SINGLE_DECL( 1974 rt5677_inbound9_enum, RT5677_DSP_INB_CTRL2, 1975 RT5677_IB9_SRC_SFT, rt5677_inbound9_src); 1976 1977 static const struct snd_kcontrol_new rt5677_ib9_src_mux = 1978 SOC_DAPM_ENUM("InBound9 Source", rt5677_inbound9_enum); 1979 1980 /* VAD Source */ /* MX-9F [6:4] */ 1981 static const char * const rt5677_vad_src[] = { 1982 "STO1 ADC MIX L", "MONO ADC MIX L", "MONO ADC MIX R", "STO2 ADC MIX L", 1983 "STO3 ADC MIX L" 1984 }; 1985 1986 static SOC_ENUM_SINGLE_DECL( 1987 rt5677_vad_enum, RT5677_VAD_CTRL4, 1988 RT5677_VAD_SRC_SFT, rt5677_vad_src); 1989 1990 static const struct snd_kcontrol_new rt5677_vad_src_mux = 1991 SOC_DAPM_ENUM("VAD Source", rt5677_vad_enum); 1992 1993 /* Sidetone Source */ /* MX-13 [11:9] */ 1994 static const char * const rt5677_sidetone_src[] = { 1995 "DMIC1 L", "DMIC2 L", "DMIC3 L", "DMIC4 L", "ADC1", "ADC2" 1996 }; 1997 1998 static SOC_ENUM_SINGLE_DECL( 1999 rt5677_sidetone_enum, RT5677_SIDETONE_CTRL, 2000 RT5677_ST_SEL_SFT, rt5677_sidetone_src); 2001 2002 static const struct snd_kcontrol_new rt5677_sidetone_mux = 2003 SOC_DAPM_ENUM("Sidetone Source", rt5677_sidetone_enum); 2004 2005 /* DAC1/2 Source */ /* MX-15 [1:0] */ 2006 static const char * const rt5677_dac12_src[] = { 2007 "STO1 DAC MIX", "MONO DAC MIX", "DD MIX1", "DD MIX2" 2008 }; 2009 2010 static SOC_ENUM_SINGLE_DECL( 2011 rt5677_dac12_enum, RT5677_ANA_DAC1_2_3_SRC, 2012 RT5677_ANA_DAC1_2_SRC_SEL_SFT, rt5677_dac12_src); 2013 2014 static const struct snd_kcontrol_new rt5677_dac12_mux = 2015 SOC_DAPM_ENUM("Analog DAC1/2 Source", rt5677_dac12_enum); 2016 2017 /* DAC3 Source */ /* MX-15 [5:4] */ 2018 static const char * const rt5677_dac3_src[] = { 2019 "MONO DAC MIXL", "MONO DAC MIXR", "DD MIX1L", "DD MIX2L" 2020 }; 2021 2022 static SOC_ENUM_SINGLE_DECL( 2023 rt5677_dac3_enum, RT5677_ANA_DAC1_2_3_SRC, 2024 RT5677_ANA_DAC3_SRC_SEL_SFT, rt5677_dac3_src); 2025 2026 static const struct snd_kcontrol_new rt5677_dac3_mux = 2027 SOC_DAPM_ENUM("Analog DAC3 Source", rt5677_dac3_enum); 2028 2029 /* PDM channel Source */ /* MX-31 [13:12][9:8][5:4][1:0] */ 2030 static const char * const rt5677_pdm_src[] = { 2031 "STO1 DAC MIX", "MONO DAC MIX", "DD MIX1", "DD MIX2" 2032 }; 2033 2034 static SOC_ENUM_SINGLE_DECL( 2035 rt5677_pdm1_l_enum, RT5677_PDM_OUT_CTRL, 2036 RT5677_SEL_PDM1_L_SFT, rt5677_pdm_src); 2037 2038 static const struct snd_kcontrol_new rt5677_pdm1_l_mux = 2039 SOC_DAPM_ENUM("PDM1 Source", rt5677_pdm1_l_enum); 2040 2041 static SOC_ENUM_SINGLE_DECL( 2042 rt5677_pdm2_l_enum, RT5677_PDM_OUT_CTRL, 2043 RT5677_SEL_PDM2_L_SFT, rt5677_pdm_src); 2044 2045 static const struct snd_kcontrol_new rt5677_pdm2_l_mux = 2046 SOC_DAPM_ENUM("PDM2 Source", rt5677_pdm2_l_enum); 2047 2048 static SOC_ENUM_SINGLE_DECL( 2049 rt5677_pdm1_r_enum, RT5677_PDM_OUT_CTRL, 2050 RT5677_SEL_PDM1_R_SFT, rt5677_pdm_src); 2051 2052 static const struct snd_kcontrol_new rt5677_pdm1_r_mux = 2053 SOC_DAPM_ENUM("PDM1 Source", rt5677_pdm1_r_enum); 2054 2055 static SOC_ENUM_SINGLE_DECL( 2056 rt5677_pdm2_r_enum, RT5677_PDM_OUT_CTRL, 2057 RT5677_SEL_PDM2_R_SFT, rt5677_pdm_src); 2058 2059 static const struct snd_kcontrol_new rt5677_pdm2_r_mux = 2060 SOC_DAPM_ENUM("PDM2 Source", rt5677_pdm2_r_enum); 2061 2062 /* TDM IF1/2 SLB ADC1 Data Selection */ /* MX-3C MX-41 [5:4] MX-08 [1:0] */ 2063 static const char * const rt5677_if12_adc1_src[] = { 2064 "STO1 ADC MIX", "OB01", "VAD ADC" 2065 }; 2066 2067 static SOC_ENUM_SINGLE_DECL( 2068 rt5677_if1_adc1_enum, RT5677_TDM1_CTRL2, 2069 RT5677_IF1_ADC1_SFT, rt5677_if12_adc1_src); 2070 2071 static const struct snd_kcontrol_new rt5677_if1_adc1_mux = 2072 SOC_DAPM_ENUM("IF1 ADC1 Source", rt5677_if1_adc1_enum); 2073 2074 static SOC_ENUM_SINGLE_DECL( 2075 rt5677_if2_adc1_enum, RT5677_TDM2_CTRL2, 2076 RT5677_IF2_ADC1_SFT, rt5677_if12_adc1_src); 2077 2078 static const struct snd_kcontrol_new rt5677_if2_adc1_mux = 2079 SOC_DAPM_ENUM("IF2 ADC1 Source", rt5677_if2_adc1_enum); 2080 2081 static SOC_ENUM_SINGLE_DECL( 2082 rt5677_slb_adc1_enum, RT5677_SLIMBUS_RX, 2083 RT5677_SLB_ADC1_SFT, rt5677_if12_adc1_src); 2084 2085 static const struct snd_kcontrol_new rt5677_slb_adc1_mux = 2086 SOC_DAPM_ENUM("SLB ADC1 Source", rt5677_slb_adc1_enum); 2087 2088 /* TDM IF1/2 SLB ADC2 Data Selection */ /* MX-3C MX-41 [7:6] MX-08 [3:2] */ 2089 static const char * const rt5677_if12_adc2_src[] = { 2090 "STO2 ADC MIX", "OB23" 2091 }; 2092 2093 static SOC_ENUM_SINGLE_DECL( 2094 rt5677_if1_adc2_enum, RT5677_TDM1_CTRL2, 2095 RT5677_IF1_ADC2_SFT, rt5677_if12_adc2_src); 2096 2097 static const struct snd_kcontrol_new rt5677_if1_adc2_mux = 2098 SOC_DAPM_ENUM("IF1 ADC2 Source", rt5677_if1_adc2_enum); 2099 2100 static SOC_ENUM_SINGLE_DECL( 2101 rt5677_if2_adc2_enum, RT5677_TDM2_CTRL2, 2102 RT5677_IF2_ADC2_SFT, rt5677_if12_adc2_src); 2103 2104 static const struct snd_kcontrol_new rt5677_if2_adc2_mux = 2105 SOC_DAPM_ENUM("IF2 ADC2 Source", rt5677_if2_adc2_enum); 2106 2107 static SOC_ENUM_SINGLE_DECL( 2108 rt5677_slb_adc2_enum, RT5677_SLIMBUS_RX, 2109 RT5677_SLB_ADC2_SFT, rt5677_if12_adc2_src); 2110 2111 static const struct snd_kcontrol_new rt5677_slb_adc2_mux = 2112 SOC_DAPM_ENUM("SLB ADC2 Source", rt5677_slb_adc2_enum); 2113 2114 /* TDM IF1/2 SLB ADC3 Data Selection */ /* MX-3C MX-41 [9:8] MX-08 [5:4] */ 2115 static const char * const rt5677_if12_adc3_src[] = { 2116 "STO3 ADC MIX", "MONO ADC MIX", "OB45" 2117 }; 2118 2119 static SOC_ENUM_SINGLE_DECL( 2120 rt5677_if1_adc3_enum, RT5677_TDM1_CTRL2, 2121 RT5677_IF1_ADC3_SFT, rt5677_if12_adc3_src); 2122 2123 static const struct snd_kcontrol_new rt5677_if1_adc3_mux = 2124 SOC_DAPM_ENUM("IF1 ADC3 Source", rt5677_if1_adc3_enum); 2125 2126 static SOC_ENUM_SINGLE_DECL( 2127 rt5677_if2_adc3_enum, RT5677_TDM2_CTRL2, 2128 RT5677_IF2_ADC3_SFT, rt5677_if12_adc3_src); 2129 2130 static const struct snd_kcontrol_new rt5677_if2_adc3_mux = 2131 SOC_DAPM_ENUM("IF2 ADC3 Source", rt5677_if2_adc3_enum); 2132 2133 static SOC_ENUM_SINGLE_DECL( 2134 rt5677_slb_adc3_enum, RT5677_SLIMBUS_RX, 2135 RT5677_SLB_ADC3_SFT, rt5677_if12_adc3_src); 2136 2137 static const struct snd_kcontrol_new rt5677_slb_adc3_mux = 2138 SOC_DAPM_ENUM("SLB ADC3 Source", rt5677_slb_adc3_enum); 2139 2140 /* TDM IF1/2 SLB ADC4 Data Selection */ /* MX-3C MX-41 [11:10] MX-08 [7:6] */ 2141 static const char * const rt5677_if12_adc4_src[] = { 2142 "STO4 ADC MIX", "OB67", "OB01" 2143 }; 2144 2145 static SOC_ENUM_SINGLE_DECL( 2146 rt5677_if1_adc4_enum, RT5677_TDM1_CTRL2, 2147 RT5677_IF1_ADC4_SFT, rt5677_if12_adc4_src); 2148 2149 static const struct snd_kcontrol_new rt5677_if1_adc4_mux = 2150 SOC_DAPM_ENUM("IF1 ADC4 Source", rt5677_if1_adc4_enum); 2151 2152 static SOC_ENUM_SINGLE_DECL( 2153 rt5677_if2_adc4_enum, RT5677_TDM2_CTRL2, 2154 RT5677_IF2_ADC4_SFT, rt5677_if12_adc4_src); 2155 2156 static const struct snd_kcontrol_new rt5677_if2_adc4_mux = 2157 SOC_DAPM_ENUM("IF2 ADC4 Source", rt5677_if2_adc4_enum); 2158 2159 static SOC_ENUM_SINGLE_DECL( 2160 rt5677_slb_adc4_enum, RT5677_SLIMBUS_RX, 2161 RT5677_SLB_ADC4_SFT, rt5677_if12_adc4_src); 2162 2163 static const struct snd_kcontrol_new rt5677_slb_adc4_mux = 2164 SOC_DAPM_ENUM("SLB ADC4 Source", rt5677_slb_adc4_enum); 2165 2166 /* Interface3/4 ADC Data Input */ /* MX-2F [3:0] MX-30 [7:4] */ 2167 static const char * const rt5677_if34_adc_src[] = { 2168 "STO1 ADC MIX", "STO2 ADC MIX", "STO3 ADC MIX", "STO4 ADC MIX", 2169 "MONO ADC MIX", "OB01", "OB23", "VAD ADC" 2170 }; 2171 2172 static SOC_ENUM_SINGLE_DECL( 2173 rt5677_if3_adc_enum, RT5677_IF3_DATA, 2174 RT5677_IF3_ADC_IN_SFT, rt5677_if34_adc_src); 2175 2176 static const struct snd_kcontrol_new rt5677_if3_adc_mux = 2177 SOC_DAPM_ENUM("IF3 ADC Source", rt5677_if3_adc_enum); 2178 2179 static SOC_ENUM_SINGLE_DECL( 2180 rt5677_if4_adc_enum, RT5677_IF4_DATA, 2181 RT5677_IF4_ADC_IN_SFT, rt5677_if34_adc_src); 2182 2183 static const struct snd_kcontrol_new rt5677_if4_adc_mux = 2184 SOC_DAPM_ENUM("IF4 ADC Source", rt5677_if4_adc_enum); 2185 2186 /* TDM IF1/2 ADC Data Selection */ /* MX-3B MX-40 [7:6][5:4][3:2][1:0] */ 2187 static const char * const rt5677_if12_adc_swap_src[] = { 2188 "L/R", "R/L", "L/L", "R/R" 2189 }; 2190 2191 static SOC_ENUM_SINGLE_DECL( 2192 rt5677_if1_adc1_swap_enum, RT5677_TDM1_CTRL1, 2193 RT5677_IF1_ADC1_SWAP_SFT, rt5677_if12_adc_swap_src); 2194 2195 static const struct snd_kcontrol_new rt5677_if1_adc1_swap_mux = 2196 SOC_DAPM_ENUM("IF1 ADC1 Swap Source", rt5677_if1_adc1_swap_enum); 2197 2198 static SOC_ENUM_SINGLE_DECL( 2199 rt5677_if1_adc2_swap_enum, RT5677_TDM1_CTRL1, 2200 RT5677_IF1_ADC2_SWAP_SFT, rt5677_if12_adc_swap_src); 2201 2202 static const struct snd_kcontrol_new rt5677_if1_adc2_swap_mux = 2203 SOC_DAPM_ENUM("IF1 ADC2 Swap Source", rt5677_if1_adc2_swap_enum); 2204 2205 static SOC_ENUM_SINGLE_DECL( 2206 rt5677_if1_adc3_swap_enum, RT5677_TDM1_CTRL1, 2207 RT5677_IF1_ADC3_SWAP_SFT, rt5677_if12_adc_swap_src); 2208 2209 static const struct snd_kcontrol_new rt5677_if1_adc3_swap_mux = 2210 SOC_DAPM_ENUM("IF1 ADC3 Swap Source", rt5677_if1_adc3_swap_enum); 2211 2212 static SOC_ENUM_SINGLE_DECL( 2213 rt5677_if1_adc4_swap_enum, RT5677_TDM1_CTRL1, 2214 RT5677_IF1_ADC4_SWAP_SFT, rt5677_if12_adc_swap_src); 2215 2216 static const struct snd_kcontrol_new rt5677_if1_adc4_swap_mux = 2217 SOC_DAPM_ENUM("IF1 ADC4 Swap Source", rt5677_if1_adc4_swap_enum); 2218 2219 static SOC_ENUM_SINGLE_DECL( 2220 rt5677_if2_adc1_swap_enum, RT5677_TDM2_CTRL1, 2221 RT5677_IF1_ADC2_SWAP_SFT, rt5677_if12_adc_swap_src); 2222 2223 static const struct snd_kcontrol_new rt5677_if2_adc1_swap_mux = 2224 SOC_DAPM_ENUM("IF1 ADC2 Swap Source", rt5677_if2_adc1_swap_enum); 2225 2226 static SOC_ENUM_SINGLE_DECL( 2227 rt5677_if2_adc2_swap_enum, RT5677_TDM2_CTRL1, 2228 RT5677_IF2_ADC2_SWAP_SFT, rt5677_if12_adc_swap_src); 2229 2230 static const struct snd_kcontrol_new rt5677_if2_adc2_swap_mux = 2231 SOC_DAPM_ENUM("IF2 ADC2 Swap Source", rt5677_if2_adc2_swap_enum); 2232 2233 static SOC_ENUM_SINGLE_DECL( 2234 rt5677_if2_adc3_swap_enum, RT5677_TDM2_CTRL1, 2235 RT5677_IF2_ADC3_SWAP_SFT, rt5677_if12_adc_swap_src); 2236 2237 static const struct snd_kcontrol_new rt5677_if2_adc3_swap_mux = 2238 SOC_DAPM_ENUM("IF2 ADC3 Swap Source", rt5677_if2_adc3_swap_enum); 2239 2240 static SOC_ENUM_SINGLE_DECL( 2241 rt5677_if2_adc4_swap_enum, RT5677_TDM2_CTRL1, 2242 RT5677_IF2_ADC4_SWAP_SFT, rt5677_if12_adc_swap_src); 2243 2244 static const struct snd_kcontrol_new rt5677_if2_adc4_swap_mux = 2245 SOC_DAPM_ENUM("IF2 ADC4 Swap Source", rt5677_if2_adc4_swap_enum); 2246 2247 /* TDM IF1 ADC Data Selection */ /* MX-3C [2:0] */ 2248 static const char * const rt5677_if1_adc_tdm_swap_src[] = { 2249 "1/2/3/4", "2/1/3/4", "2/3/1/4", "4/1/2/3", "1/3/2/4", "1/4/2/3", 2250 "3/1/2/4", "3/4/1/2" 2251 }; 2252 2253 static SOC_ENUM_SINGLE_DECL( 2254 rt5677_if1_adc_tdm_swap_enum, RT5677_TDM1_CTRL2, 2255 RT5677_IF1_ADC_CTRL_SFT, rt5677_if1_adc_tdm_swap_src); 2256 2257 static const struct snd_kcontrol_new rt5677_if1_adc_tdm_swap_mux = 2258 SOC_DAPM_ENUM("IF1 ADC TDM Swap Source", rt5677_if1_adc_tdm_swap_enum); 2259 2260 /* TDM IF2 ADC Data Selection */ /* MX-41[2:0] */ 2261 static const char * const rt5677_if2_adc_tdm_swap_src[] = { 2262 "1/2/3/4", "2/1/3/4", "3/1/2/4", "4/1/2/3", "1/3/2/4", "1/4/2/3", 2263 "2/3/1/4", "3/4/1/2" 2264 }; 2265 2266 static SOC_ENUM_SINGLE_DECL( 2267 rt5677_if2_adc_tdm_swap_enum, RT5677_TDM2_CTRL2, 2268 RT5677_IF2_ADC_CTRL_SFT, rt5677_if2_adc_tdm_swap_src); 2269 2270 static const struct snd_kcontrol_new rt5677_if2_adc_tdm_swap_mux = 2271 SOC_DAPM_ENUM("IF2 ADC TDM Swap Source", rt5677_if2_adc_tdm_swap_enum); 2272 2273 /* TDM IF1/2 DAC Data Selection */ /* MX-3E[14:12][10:8][6:4][2:0] 2274 MX-3F[14:12][10:8][6:4][2:0] 2275 MX-43[14:12][10:8][6:4][2:0] 2276 MX-44[14:12][10:8][6:4][2:0] */ 2277 static const char * const rt5677_if12_dac_tdm_sel_src[] = { 2278 "Slot0", "Slot1", "Slot2", "Slot3", "Slot4", "Slot5", "Slot6", "Slot7" 2279 }; 2280 2281 static SOC_ENUM_SINGLE_DECL( 2282 rt5677_if1_dac0_tdm_sel_enum, RT5677_TDM1_CTRL4, 2283 RT5677_IF1_DAC0_SFT, rt5677_if12_dac_tdm_sel_src); 2284 2285 static const struct snd_kcontrol_new rt5677_if1_dac0_tdm_sel_mux = 2286 SOC_DAPM_ENUM("IF1 DAC0 TDM Source", rt5677_if1_dac0_tdm_sel_enum); 2287 2288 static SOC_ENUM_SINGLE_DECL( 2289 rt5677_if1_dac1_tdm_sel_enum, RT5677_TDM1_CTRL4, 2290 RT5677_IF1_DAC1_SFT, rt5677_if12_dac_tdm_sel_src); 2291 2292 static const struct snd_kcontrol_new rt5677_if1_dac1_tdm_sel_mux = 2293 SOC_DAPM_ENUM("IF1 DAC1 TDM Source", rt5677_if1_dac1_tdm_sel_enum); 2294 2295 static SOC_ENUM_SINGLE_DECL( 2296 rt5677_if1_dac2_tdm_sel_enum, RT5677_TDM1_CTRL4, 2297 RT5677_IF1_DAC2_SFT, rt5677_if12_dac_tdm_sel_src); 2298 2299 static const struct snd_kcontrol_new rt5677_if1_dac2_tdm_sel_mux = 2300 SOC_DAPM_ENUM("IF1 DAC2 TDM Source", rt5677_if1_dac2_tdm_sel_enum); 2301 2302 static SOC_ENUM_SINGLE_DECL( 2303 rt5677_if1_dac3_tdm_sel_enum, RT5677_TDM1_CTRL4, 2304 RT5677_IF1_DAC3_SFT, rt5677_if12_dac_tdm_sel_src); 2305 2306 static const struct snd_kcontrol_new rt5677_if1_dac3_tdm_sel_mux = 2307 SOC_DAPM_ENUM("IF1 DAC3 TDM Source", rt5677_if1_dac3_tdm_sel_enum); 2308 2309 static SOC_ENUM_SINGLE_DECL( 2310 rt5677_if1_dac4_tdm_sel_enum, RT5677_TDM1_CTRL5, 2311 RT5677_IF1_DAC4_SFT, rt5677_if12_dac_tdm_sel_src); 2312 2313 static const struct snd_kcontrol_new rt5677_if1_dac4_tdm_sel_mux = 2314 SOC_DAPM_ENUM("IF1 DAC4 TDM Source", rt5677_if1_dac4_tdm_sel_enum); 2315 2316 static SOC_ENUM_SINGLE_DECL( 2317 rt5677_if1_dac5_tdm_sel_enum, RT5677_TDM1_CTRL5, 2318 RT5677_IF1_DAC5_SFT, rt5677_if12_dac_tdm_sel_src); 2319 2320 static const struct snd_kcontrol_new rt5677_if1_dac5_tdm_sel_mux = 2321 SOC_DAPM_ENUM("IF1 DAC5 TDM Source", rt5677_if1_dac5_tdm_sel_enum); 2322 2323 static SOC_ENUM_SINGLE_DECL( 2324 rt5677_if1_dac6_tdm_sel_enum, RT5677_TDM1_CTRL5, 2325 RT5677_IF1_DAC6_SFT, rt5677_if12_dac_tdm_sel_src); 2326 2327 static const struct snd_kcontrol_new rt5677_if1_dac6_tdm_sel_mux = 2328 SOC_DAPM_ENUM("IF1 DAC6 TDM Source", rt5677_if1_dac6_tdm_sel_enum); 2329 2330 static SOC_ENUM_SINGLE_DECL( 2331 rt5677_if1_dac7_tdm_sel_enum, RT5677_TDM1_CTRL5, 2332 RT5677_IF1_DAC7_SFT, rt5677_if12_dac_tdm_sel_src); 2333 2334 static const struct snd_kcontrol_new rt5677_if1_dac7_tdm_sel_mux = 2335 SOC_DAPM_ENUM("IF1 DAC7 TDM Source", rt5677_if1_dac7_tdm_sel_enum); 2336 2337 static SOC_ENUM_SINGLE_DECL( 2338 rt5677_if2_dac0_tdm_sel_enum, RT5677_TDM2_CTRL4, 2339 RT5677_IF2_DAC0_SFT, rt5677_if12_dac_tdm_sel_src); 2340 2341 static const struct snd_kcontrol_new rt5677_if2_dac0_tdm_sel_mux = 2342 SOC_DAPM_ENUM("IF2 DAC0 TDM Source", rt5677_if2_dac0_tdm_sel_enum); 2343 2344 static SOC_ENUM_SINGLE_DECL( 2345 rt5677_if2_dac1_tdm_sel_enum, RT5677_TDM2_CTRL4, 2346 RT5677_IF2_DAC1_SFT, rt5677_if12_dac_tdm_sel_src); 2347 2348 static const struct snd_kcontrol_new rt5677_if2_dac1_tdm_sel_mux = 2349 SOC_DAPM_ENUM("IF2 DAC1 TDM Source", rt5677_if2_dac1_tdm_sel_enum); 2350 2351 static SOC_ENUM_SINGLE_DECL( 2352 rt5677_if2_dac2_tdm_sel_enum, RT5677_TDM2_CTRL4, 2353 RT5677_IF2_DAC2_SFT, rt5677_if12_dac_tdm_sel_src); 2354 2355 static const struct snd_kcontrol_new rt5677_if2_dac2_tdm_sel_mux = 2356 SOC_DAPM_ENUM("IF2 DAC2 TDM Source", rt5677_if2_dac2_tdm_sel_enum); 2357 2358 static SOC_ENUM_SINGLE_DECL( 2359 rt5677_if2_dac3_tdm_sel_enum, RT5677_TDM2_CTRL4, 2360 RT5677_IF2_DAC3_SFT, rt5677_if12_dac_tdm_sel_src); 2361 2362 static const struct snd_kcontrol_new rt5677_if2_dac3_tdm_sel_mux = 2363 SOC_DAPM_ENUM("IF2 DAC3 TDM Source", rt5677_if2_dac3_tdm_sel_enum); 2364 2365 static SOC_ENUM_SINGLE_DECL( 2366 rt5677_if2_dac4_tdm_sel_enum, RT5677_TDM2_CTRL5, 2367 RT5677_IF2_DAC4_SFT, rt5677_if12_dac_tdm_sel_src); 2368 2369 static const struct snd_kcontrol_new rt5677_if2_dac4_tdm_sel_mux = 2370 SOC_DAPM_ENUM("IF2 DAC4 TDM Source", rt5677_if2_dac4_tdm_sel_enum); 2371 2372 static SOC_ENUM_SINGLE_DECL( 2373 rt5677_if2_dac5_tdm_sel_enum, RT5677_TDM2_CTRL5, 2374 RT5677_IF2_DAC5_SFT, rt5677_if12_dac_tdm_sel_src); 2375 2376 static const struct snd_kcontrol_new rt5677_if2_dac5_tdm_sel_mux = 2377 SOC_DAPM_ENUM("IF2 DAC5 TDM Source", rt5677_if2_dac5_tdm_sel_enum); 2378 2379 static SOC_ENUM_SINGLE_DECL( 2380 rt5677_if2_dac6_tdm_sel_enum, RT5677_TDM2_CTRL5, 2381 RT5677_IF2_DAC6_SFT, rt5677_if12_dac_tdm_sel_src); 2382 2383 static const struct snd_kcontrol_new rt5677_if2_dac6_tdm_sel_mux = 2384 SOC_DAPM_ENUM("IF2 DAC6 TDM Source", rt5677_if2_dac6_tdm_sel_enum); 2385 2386 static SOC_ENUM_SINGLE_DECL( 2387 rt5677_if2_dac7_tdm_sel_enum, RT5677_TDM2_CTRL5, 2388 RT5677_IF2_DAC7_SFT, rt5677_if12_dac_tdm_sel_src); 2389 2390 static const struct snd_kcontrol_new rt5677_if2_dac7_tdm_sel_mux = 2391 SOC_DAPM_ENUM("IF2 DAC7 TDM Source", rt5677_if2_dac7_tdm_sel_enum); 2392 2393 static int rt5677_bst1_event(struct snd_soc_dapm_widget *w, 2394 struct snd_kcontrol *kcontrol, int event) 2395 { 2396 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 2397 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component); 2398 2399 switch (event) { 2400 case SND_SOC_DAPM_POST_PMU: 2401 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2, 2402 RT5677_PWR_BST1_P, RT5677_PWR_BST1_P); 2403 break; 2404 2405 case SND_SOC_DAPM_PRE_PMD: 2406 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2, 2407 RT5677_PWR_BST1_P, 0); 2408 break; 2409 2410 default: 2411 return 0; 2412 } 2413 2414 return 0; 2415 } 2416 2417 static int rt5677_bst2_event(struct snd_soc_dapm_widget *w, 2418 struct snd_kcontrol *kcontrol, int event) 2419 { 2420 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 2421 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component); 2422 2423 switch (event) { 2424 case SND_SOC_DAPM_POST_PMU: 2425 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2, 2426 RT5677_PWR_BST2_P, RT5677_PWR_BST2_P); 2427 break; 2428 2429 case SND_SOC_DAPM_PRE_PMD: 2430 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2, 2431 RT5677_PWR_BST2_P, 0); 2432 break; 2433 2434 default: 2435 return 0; 2436 } 2437 2438 return 0; 2439 } 2440 2441 static int rt5677_set_pll1_event(struct snd_soc_dapm_widget *w, 2442 struct snd_kcontrol *kcontrol, int event) 2443 { 2444 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 2445 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component); 2446 2447 switch (event) { 2448 case SND_SOC_DAPM_PRE_PMU: 2449 regmap_update_bits(rt5677->regmap, RT5677_PLL1_CTRL2, 0x2, 0x2); 2450 break; 2451 2452 case SND_SOC_DAPM_POST_PMU: 2453 regmap_update_bits(rt5677->regmap, RT5677_PLL1_CTRL2, 0x2, 0x0); 2454 break; 2455 2456 default: 2457 return 0; 2458 } 2459 2460 return 0; 2461 } 2462 2463 static int rt5677_set_pll2_event(struct snd_soc_dapm_widget *w, 2464 struct snd_kcontrol *kcontrol, int event) 2465 { 2466 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 2467 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component); 2468 2469 switch (event) { 2470 case SND_SOC_DAPM_PRE_PMU: 2471 regmap_update_bits(rt5677->regmap, RT5677_PLL2_CTRL2, 0x2, 0x2); 2472 break; 2473 2474 case SND_SOC_DAPM_POST_PMU: 2475 regmap_update_bits(rt5677->regmap, RT5677_PLL2_CTRL2, 0x2, 0x0); 2476 break; 2477 2478 default: 2479 return 0; 2480 } 2481 2482 return 0; 2483 } 2484 2485 static int rt5677_set_micbias1_event(struct snd_soc_dapm_widget *w, 2486 struct snd_kcontrol *kcontrol, int event) 2487 { 2488 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 2489 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component); 2490 2491 switch (event) { 2492 case SND_SOC_DAPM_POST_PMU: 2493 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2, 2494 RT5677_PWR_CLK_MB1 | RT5677_PWR_PP_MB1 | 2495 RT5677_PWR_CLK_MB, RT5677_PWR_CLK_MB1 | 2496 RT5677_PWR_PP_MB1 | RT5677_PWR_CLK_MB); 2497 break; 2498 2499 case SND_SOC_DAPM_PRE_PMD: 2500 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2, 2501 RT5677_PWR_CLK_MB1 | RT5677_PWR_PP_MB1 | 2502 RT5677_PWR_CLK_MB, 0); 2503 break; 2504 2505 default: 2506 return 0; 2507 } 2508 2509 return 0; 2510 } 2511 2512 static int rt5677_if1_adc_tdm_event(struct snd_soc_dapm_widget *w, 2513 struct snd_kcontrol *kcontrol, int event) 2514 { 2515 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 2516 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component); 2517 unsigned int value; 2518 2519 switch (event) { 2520 case SND_SOC_DAPM_PRE_PMU: 2521 regmap_read(rt5677->regmap, RT5677_TDM1_CTRL2, &value); 2522 if (value & RT5677_IF1_ADC_CTRL_MASK) 2523 regmap_update_bits(rt5677->regmap, RT5677_TDM1_CTRL1, 2524 RT5677_IF1_ADC_MODE_MASK, 2525 RT5677_IF1_ADC_MODE_TDM); 2526 break; 2527 2528 default: 2529 return 0; 2530 } 2531 2532 return 0; 2533 } 2534 2535 static int rt5677_if2_adc_tdm_event(struct snd_soc_dapm_widget *w, 2536 struct snd_kcontrol *kcontrol, int event) 2537 { 2538 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 2539 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component); 2540 unsigned int value; 2541 2542 switch (event) { 2543 case SND_SOC_DAPM_PRE_PMU: 2544 regmap_read(rt5677->regmap, RT5677_TDM2_CTRL2, &value); 2545 if (value & RT5677_IF2_ADC_CTRL_MASK) 2546 regmap_update_bits(rt5677->regmap, RT5677_TDM2_CTRL1, 2547 RT5677_IF2_ADC_MODE_MASK, 2548 RT5677_IF2_ADC_MODE_TDM); 2549 break; 2550 2551 default: 2552 return 0; 2553 } 2554 2555 return 0; 2556 } 2557 2558 static int rt5677_vref_event(struct snd_soc_dapm_widget *w, 2559 struct snd_kcontrol *kcontrol, int event) 2560 { 2561 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 2562 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component); 2563 2564 switch (event) { 2565 case SND_SOC_DAPM_POST_PMU: 2566 if (snd_soc_component_get_bias_level(component) != SND_SOC_BIAS_ON && 2567 !rt5677->is_vref_slow) { 2568 mdelay(20); 2569 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1, 2570 RT5677_PWR_FV1 | RT5677_PWR_FV2, 2571 RT5677_PWR_FV1 | RT5677_PWR_FV2); 2572 rt5677->is_vref_slow = true; 2573 } 2574 break; 2575 2576 default: 2577 return 0; 2578 } 2579 2580 return 0; 2581 } 2582 2583 static int rt5677_filter_power_event(struct snd_soc_dapm_widget *w, 2584 struct snd_kcontrol *kcontrol, int event) 2585 { 2586 switch (event) { 2587 case SND_SOC_DAPM_POST_PMU: 2588 msleep(50); 2589 break; 2590 2591 default: 2592 return 0; 2593 } 2594 2595 return 0; 2596 } 2597 2598 static const struct snd_soc_dapm_widget rt5677_dapm_widgets[] = { 2599 SND_SOC_DAPM_SUPPLY("PLL1", RT5677_PWR_ANLG2, RT5677_PWR_PLL1_BIT, 2600 0, rt5677_set_pll1_event, SND_SOC_DAPM_PRE_PMU | 2601 SND_SOC_DAPM_POST_PMU), 2602 SND_SOC_DAPM_SUPPLY("PLL2", RT5677_PWR_ANLG2, RT5677_PWR_PLL2_BIT, 2603 0, rt5677_set_pll2_event, SND_SOC_DAPM_PRE_PMU | 2604 SND_SOC_DAPM_POST_PMU), 2605 2606 /* ASRC */ 2607 SND_SOC_DAPM_SUPPLY_S("I2S1 ASRC", 1, RT5677_ASRC_1, 0, 0, NULL, 0), 2608 SND_SOC_DAPM_SUPPLY_S("I2S2 ASRC", 1, RT5677_ASRC_1, 1, 0, NULL, 0), 2609 SND_SOC_DAPM_SUPPLY_S("I2S3 ASRC", 1, RT5677_ASRC_1, 2, 0, NULL, 0), 2610 SND_SOC_DAPM_SUPPLY_S("I2S4 ASRC", 1, RT5677_ASRC_1, 3, 0, NULL, 0), 2611 SND_SOC_DAPM_SUPPLY_S("DAC STO ASRC", 1, RT5677_ASRC_2, 14, 0, 2612 rt5677_filter_power_event, SND_SOC_DAPM_POST_PMU), 2613 SND_SOC_DAPM_SUPPLY_S("DAC MONO2 L ASRC", 1, RT5677_ASRC_2, 13, 0, NULL, 2614 0), 2615 SND_SOC_DAPM_SUPPLY_S("DAC MONO2 R ASRC", 1, RT5677_ASRC_2, 12, 0, NULL, 2616 0), 2617 SND_SOC_DAPM_SUPPLY_S("DAC MONO3 L ASRC", 1, RT5677_ASRC_1, 15, 0, NULL, 2618 0), 2619 SND_SOC_DAPM_SUPPLY_S("DAC MONO3 R ASRC", 1, RT5677_ASRC_1, 14, 0, NULL, 2620 0), 2621 SND_SOC_DAPM_SUPPLY_S("DAC MONO4 L ASRC", 1, RT5677_ASRC_1, 13, 0, NULL, 2622 0), 2623 SND_SOC_DAPM_SUPPLY_S("DAC MONO4 R ASRC", 1, RT5677_ASRC_1, 12, 0, NULL, 2624 0), 2625 SND_SOC_DAPM_SUPPLY_S("DMIC STO1 ASRC", 1, RT5677_ASRC_2, 11, 0, NULL, 2626 0), 2627 SND_SOC_DAPM_SUPPLY_S("DMIC STO2 ASRC", 1, RT5677_ASRC_2, 10, 0, NULL, 2628 0), 2629 SND_SOC_DAPM_SUPPLY_S("DMIC STO3 ASRC", 1, RT5677_ASRC_2, 9, 0, NULL, 2630 0), 2631 SND_SOC_DAPM_SUPPLY_S("DMIC STO4 ASRC", 1, RT5677_ASRC_2, 8, 0, NULL, 2632 0), 2633 SND_SOC_DAPM_SUPPLY_S("DMIC MONO L ASRC", 1, RT5677_ASRC_2, 7, 0, NULL, 2634 0), 2635 SND_SOC_DAPM_SUPPLY_S("DMIC MONO R ASRC", 1, RT5677_ASRC_2, 6, 0, NULL, 2636 0), 2637 SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5677_ASRC_2, 5, 0, NULL, 0), 2638 SND_SOC_DAPM_SUPPLY_S("ADC STO2 ASRC", 1, RT5677_ASRC_2, 4, 0, NULL, 0), 2639 SND_SOC_DAPM_SUPPLY_S("ADC STO3 ASRC", 1, RT5677_ASRC_2, 3, 0, NULL, 0), 2640 SND_SOC_DAPM_SUPPLY_S("ADC STO4 ASRC", 1, RT5677_ASRC_2, 2, 0, NULL, 0), 2641 SND_SOC_DAPM_SUPPLY_S("ADC MONO L ASRC", 1, RT5677_ASRC_2, 1, 0, NULL, 2642 0), 2643 SND_SOC_DAPM_SUPPLY_S("ADC MONO R ASRC", 1, RT5677_ASRC_2, 0, 0, NULL, 2644 0), 2645 2646 /* Input Side */ 2647 /* micbias */ 2648 SND_SOC_DAPM_SUPPLY("MICBIAS1", RT5677_PWR_ANLG2, RT5677_PWR_MB1_BIT, 2649 0, rt5677_set_micbias1_event, SND_SOC_DAPM_PRE_PMD | 2650 SND_SOC_DAPM_POST_PMU), 2651 2652 /* Input Lines */ 2653 SND_SOC_DAPM_INPUT("DMIC L1"), 2654 SND_SOC_DAPM_INPUT("DMIC R1"), 2655 SND_SOC_DAPM_INPUT("DMIC L2"), 2656 SND_SOC_DAPM_INPUT("DMIC R2"), 2657 SND_SOC_DAPM_INPUT("DMIC L3"), 2658 SND_SOC_DAPM_INPUT("DMIC R3"), 2659 SND_SOC_DAPM_INPUT("DMIC L4"), 2660 SND_SOC_DAPM_INPUT("DMIC R4"), 2661 2662 SND_SOC_DAPM_INPUT("IN1P"), 2663 SND_SOC_DAPM_INPUT("IN1N"), 2664 SND_SOC_DAPM_INPUT("IN2P"), 2665 SND_SOC_DAPM_INPUT("IN2N"), 2666 2667 SND_SOC_DAPM_INPUT("Haptic Generator"), 2668 2669 SND_SOC_DAPM_PGA("DMIC1", SND_SOC_NOPM, 0, 0, NULL, 0), 2670 SND_SOC_DAPM_PGA("DMIC2", SND_SOC_NOPM, 0, 0, NULL, 0), 2671 SND_SOC_DAPM_PGA("DMIC3", SND_SOC_NOPM, 0, 0, NULL, 0), 2672 SND_SOC_DAPM_PGA("DMIC4", SND_SOC_NOPM, 0, 0, NULL, 0), 2673 2674 SND_SOC_DAPM_SUPPLY("DMIC1 power", RT5677_DMIC_CTRL1, 2675 RT5677_DMIC_1_EN_SFT, 0, NULL, 0), 2676 SND_SOC_DAPM_SUPPLY("DMIC2 power", RT5677_DMIC_CTRL1, 2677 RT5677_DMIC_2_EN_SFT, 0, NULL, 0), 2678 SND_SOC_DAPM_SUPPLY("DMIC3 power", RT5677_DMIC_CTRL1, 2679 RT5677_DMIC_3_EN_SFT, 0, NULL, 0), 2680 SND_SOC_DAPM_SUPPLY("DMIC4 power", RT5677_DMIC_CTRL2, 2681 RT5677_DMIC_4_EN_SFT, 0, NULL, 0), 2682 2683 SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0, 2684 set_dmic_clk, SND_SOC_DAPM_PRE_PMU), 2685 2686 /* Boost */ 2687 SND_SOC_DAPM_PGA_E("BST1", RT5677_PWR_ANLG2, 2688 RT5677_PWR_BST1_BIT, 0, NULL, 0, rt5677_bst1_event, 2689 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU), 2690 SND_SOC_DAPM_PGA_E("BST2", RT5677_PWR_ANLG2, 2691 RT5677_PWR_BST2_BIT, 0, NULL, 0, rt5677_bst2_event, 2692 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU), 2693 2694 /* ADCs */ 2695 SND_SOC_DAPM_ADC("ADC 1", NULL, SND_SOC_NOPM, 2696 0, 0), 2697 SND_SOC_DAPM_ADC("ADC 2", NULL, SND_SOC_NOPM, 2698 0, 0), 2699 SND_SOC_DAPM_PGA("ADC 1_2", SND_SOC_NOPM, 0, 0, NULL, 0), 2700 2701 SND_SOC_DAPM_SUPPLY("ADC 1 power", RT5677_PWR_DIG1, 2702 RT5677_PWR_ADC_L_BIT, 0, NULL, 0), 2703 SND_SOC_DAPM_SUPPLY("ADC 2 power", RT5677_PWR_DIG1, 2704 RT5677_PWR_ADC_R_BIT, 0, NULL, 0), 2705 SND_SOC_DAPM_SUPPLY("ADC1 clock", RT5677_PWR_DIG1, 2706 RT5677_PWR_ADCFED1_BIT, 0, NULL, 0), 2707 SND_SOC_DAPM_SUPPLY("ADC2 clock", RT5677_PWR_DIG1, 2708 RT5677_PWR_ADCFED2_BIT, 0, NULL, 0), 2709 2710 /* ADC Mux */ 2711 SND_SOC_DAPM_MUX("Stereo1 DMIC Mux", SND_SOC_NOPM, 0, 0, 2712 &rt5677_sto1_dmic_mux), 2713 SND_SOC_DAPM_MUX("Stereo1 ADC1 Mux", SND_SOC_NOPM, 0, 0, 2714 &rt5677_sto1_adc1_mux), 2715 SND_SOC_DAPM_MUX("Stereo1 ADC2 Mux", SND_SOC_NOPM, 0, 0, 2716 &rt5677_sto1_adc2_mux), 2717 SND_SOC_DAPM_MUX("Stereo2 DMIC Mux", SND_SOC_NOPM, 0, 0, 2718 &rt5677_sto2_dmic_mux), 2719 SND_SOC_DAPM_MUX("Stereo2 ADC1 Mux", SND_SOC_NOPM, 0, 0, 2720 &rt5677_sto2_adc1_mux), 2721 SND_SOC_DAPM_MUX("Stereo2 ADC2 Mux", SND_SOC_NOPM, 0, 0, 2722 &rt5677_sto2_adc2_mux), 2723 SND_SOC_DAPM_MUX("Stereo2 ADC LR Mux", SND_SOC_NOPM, 0, 0, 2724 &rt5677_sto2_adc_lr_mux), 2725 SND_SOC_DAPM_MUX("Stereo3 DMIC Mux", SND_SOC_NOPM, 0, 0, 2726 &rt5677_sto3_dmic_mux), 2727 SND_SOC_DAPM_MUX("Stereo3 ADC1 Mux", SND_SOC_NOPM, 0, 0, 2728 &rt5677_sto3_adc1_mux), 2729 SND_SOC_DAPM_MUX("Stereo3 ADC2 Mux", SND_SOC_NOPM, 0, 0, 2730 &rt5677_sto3_adc2_mux), 2731 SND_SOC_DAPM_MUX("Stereo4 DMIC Mux", SND_SOC_NOPM, 0, 0, 2732 &rt5677_sto4_dmic_mux), 2733 SND_SOC_DAPM_MUX("Stereo4 ADC1 Mux", SND_SOC_NOPM, 0, 0, 2734 &rt5677_sto4_adc1_mux), 2735 SND_SOC_DAPM_MUX("Stereo4 ADC2 Mux", SND_SOC_NOPM, 0, 0, 2736 &rt5677_sto4_adc2_mux), 2737 SND_SOC_DAPM_MUX("Mono DMIC L Mux", SND_SOC_NOPM, 0, 0, 2738 &rt5677_mono_dmic_l_mux), 2739 SND_SOC_DAPM_MUX("Mono DMIC R Mux", SND_SOC_NOPM, 0, 0, 2740 &rt5677_mono_dmic_r_mux), 2741 SND_SOC_DAPM_MUX("Mono ADC2 L Mux", SND_SOC_NOPM, 0, 0, 2742 &rt5677_mono_adc2_l_mux), 2743 SND_SOC_DAPM_MUX("Mono ADC1 L Mux", SND_SOC_NOPM, 0, 0, 2744 &rt5677_mono_adc1_l_mux), 2745 SND_SOC_DAPM_MUX("Mono ADC1 R Mux", SND_SOC_NOPM, 0, 0, 2746 &rt5677_mono_adc1_r_mux), 2747 SND_SOC_DAPM_MUX("Mono ADC2 R Mux", SND_SOC_NOPM, 0, 0, 2748 &rt5677_mono_adc2_r_mux), 2749 2750 /* ADC Mixer */ 2751 SND_SOC_DAPM_SUPPLY("adc stereo1 filter", RT5677_PWR_DIG2, 2752 RT5677_PWR_ADC_S1F_BIT, 0, NULL, 0), 2753 SND_SOC_DAPM_SUPPLY("adc stereo2 filter", RT5677_PWR_DIG2, 2754 RT5677_PWR_ADC_S2F_BIT, 0, NULL, 0), 2755 SND_SOC_DAPM_SUPPLY("adc stereo3 filter", RT5677_PWR_DIG2, 2756 RT5677_PWR_ADC_S3F_BIT, 0, NULL, 0), 2757 SND_SOC_DAPM_SUPPLY("adc stereo4 filter", RT5677_PWR_DIG2, 2758 RT5677_PWR_ADC_S4F_BIT, 0, NULL, 0), 2759 SND_SOC_DAPM_MIXER("Sto1 ADC MIXL", SND_SOC_NOPM, 0, 0, 2760 rt5677_sto1_adc_l_mix, ARRAY_SIZE(rt5677_sto1_adc_l_mix)), 2761 SND_SOC_DAPM_MIXER("Sto1 ADC MIXR", SND_SOC_NOPM, 0, 0, 2762 rt5677_sto1_adc_r_mix, ARRAY_SIZE(rt5677_sto1_adc_r_mix)), 2763 SND_SOC_DAPM_MIXER("Sto2 ADC MIXL", SND_SOC_NOPM, 0, 0, 2764 rt5677_sto2_adc_l_mix, ARRAY_SIZE(rt5677_sto2_adc_l_mix)), 2765 SND_SOC_DAPM_MIXER("Sto2 ADC MIXR", SND_SOC_NOPM, 0, 0, 2766 rt5677_sto2_adc_r_mix, ARRAY_SIZE(rt5677_sto2_adc_r_mix)), 2767 SND_SOC_DAPM_MIXER("Sto3 ADC MIXL", SND_SOC_NOPM, 0, 0, 2768 rt5677_sto3_adc_l_mix, ARRAY_SIZE(rt5677_sto3_adc_l_mix)), 2769 SND_SOC_DAPM_MIXER("Sto3 ADC MIXR", SND_SOC_NOPM, 0, 0, 2770 rt5677_sto3_adc_r_mix, ARRAY_SIZE(rt5677_sto3_adc_r_mix)), 2771 SND_SOC_DAPM_MIXER("Sto4 ADC MIXL", SND_SOC_NOPM, 0, 0, 2772 rt5677_sto4_adc_l_mix, ARRAY_SIZE(rt5677_sto4_adc_l_mix)), 2773 SND_SOC_DAPM_MIXER("Sto4 ADC MIXR", SND_SOC_NOPM, 0, 0, 2774 rt5677_sto4_adc_r_mix, ARRAY_SIZE(rt5677_sto4_adc_r_mix)), 2775 SND_SOC_DAPM_SUPPLY("adc mono left filter", RT5677_PWR_DIG2, 2776 RT5677_PWR_ADC_MF_L_BIT, 0, NULL, 0), 2777 SND_SOC_DAPM_MIXER("Mono ADC MIXL", SND_SOC_NOPM, 0, 0, 2778 rt5677_mono_adc_l_mix, ARRAY_SIZE(rt5677_mono_adc_l_mix)), 2779 SND_SOC_DAPM_SUPPLY("adc mono right filter", RT5677_PWR_DIG2, 2780 RT5677_PWR_ADC_MF_R_BIT, 0, NULL, 0), 2781 SND_SOC_DAPM_MIXER("Mono ADC MIXR", SND_SOC_NOPM, 0, 0, 2782 rt5677_mono_adc_r_mix, ARRAY_SIZE(rt5677_mono_adc_r_mix)), 2783 2784 /* ADC PGA */ 2785 SND_SOC_DAPM_PGA("Stereo1 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0), 2786 SND_SOC_DAPM_PGA("Stereo1 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0), 2787 SND_SOC_DAPM_PGA("Stereo1 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 2788 SND_SOC_DAPM_PGA("Stereo2 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0), 2789 SND_SOC_DAPM_PGA("Stereo2 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0), 2790 SND_SOC_DAPM_PGA("Stereo2 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 2791 SND_SOC_DAPM_PGA("Stereo3 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0), 2792 SND_SOC_DAPM_PGA("Stereo3 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0), 2793 SND_SOC_DAPM_PGA("Stereo3 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 2794 SND_SOC_DAPM_PGA("Stereo4 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0), 2795 SND_SOC_DAPM_PGA("Stereo4 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0), 2796 SND_SOC_DAPM_PGA("Stereo4 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 2797 SND_SOC_DAPM_PGA("Sto2 ADC LR MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 2798 SND_SOC_DAPM_PGA("Mono ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 2799 SND_SOC_DAPM_PGA("IF1 ADC", SND_SOC_NOPM, 0, 0, NULL, 0), 2800 SND_SOC_DAPM_PGA("IF2 ADC", SND_SOC_NOPM, 0, 0, NULL, 0), 2801 2802 /* DSP */ 2803 SND_SOC_DAPM_MUX("IB9 Mux", SND_SOC_NOPM, 0, 0, 2804 &rt5677_ib9_src_mux), 2805 SND_SOC_DAPM_MUX("IB8 Mux", SND_SOC_NOPM, 0, 0, 2806 &rt5677_ib8_src_mux), 2807 SND_SOC_DAPM_MUX("IB7 Mux", SND_SOC_NOPM, 0, 0, 2808 &rt5677_ib7_src_mux), 2809 SND_SOC_DAPM_MUX("IB6 Mux", SND_SOC_NOPM, 0, 0, 2810 &rt5677_ib6_src_mux), 2811 SND_SOC_DAPM_MUX("IB45 Mux", SND_SOC_NOPM, 0, 0, 2812 &rt5677_ib45_src_mux), 2813 SND_SOC_DAPM_MUX("IB23 Mux", SND_SOC_NOPM, 0, 0, 2814 &rt5677_ib23_src_mux), 2815 SND_SOC_DAPM_MUX("IB01 Mux", SND_SOC_NOPM, 0, 0, 2816 &rt5677_ib01_src_mux), 2817 SND_SOC_DAPM_MUX("IB45 Bypass Mux", SND_SOC_NOPM, 0, 0, 2818 &rt5677_ib45_bypass_src_mux), 2819 SND_SOC_DAPM_MUX("IB23 Bypass Mux", SND_SOC_NOPM, 0, 0, 2820 &rt5677_ib23_bypass_src_mux), 2821 SND_SOC_DAPM_MUX("IB01 Bypass Mux", SND_SOC_NOPM, 0, 0, 2822 &rt5677_ib01_bypass_src_mux), 2823 SND_SOC_DAPM_MUX("OB23 Bypass Mux", SND_SOC_NOPM, 0, 0, 2824 &rt5677_ob23_bypass_src_mux), 2825 SND_SOC_DAPM_MUX("OB01 Bypass Mux", SND_SOC_NOPM, 0, 0, 2826 &rt5677_ob01_bypass_src_mux), 2827 2828 SND_SOC_DAPM_PGA("OB45", SND_SOC_NOPM, 0, 0, NULL, 0), 2829 SND_SOC_DAPM_PGA("OB67", SND_SOC_NOPM, 0, 0, NULL, 0), 2830 2831 SND_SOC_DAPM_PGA("OutBound2", SND_SOC_NOPM, 0, 0, NULL, 0), 2832 SND_SOC_DAPM_PGA("OutBound3", SND_SOC_NOPM, 0, 0, NULL, 0), 2833 SND_SOC_DAPM_PGA("OutBound4", SND_SOC_NOPM, 0, 0, NULL, 0), 2834 SND_SOC_DAPM_PGA("OutBound5", SND_SOC_NOPM, 0, 0, NULL, 0), 2835 SND_SOC_DAPM_PGA("OutBound6", SND_SOC_NOPM, 0, 0, NULL, 0), 2836 SND_SOC_DAPM_PGA("OutBound7", SND_SOC_NOPM, 0, 0, NULL, 0), 2837 2838 /* Digital Interface */ 2839 SND_SOC_DAPM_SUPPLY("I2S1", RT5677_PWR_DIG1, 2840 RT5677_PWR_I2S1_BIT, 0, NULL, 0), 2841 SND_SOC_DAPM_PGA("IF1 DAC0", SND_SOC_NOPM, 0, 0, NULL, 0), 2842 SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0), 2843 SND_SOC_DAPM_PGA("IF1 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0), 2844 SND_SOC_DAPM_PGA("IF1 DAC3", SND_SOC_NOPM, 0, 0, NULL, 0), 2845 SND_SOC_DAPM_PGA("IF1 DAC4", SND_SOC_NOPM, 0, 0, NULL, 0), 2846 SND_SOC_DAPM_PGA("IF1 DAC5", SND_SOC_NOPM, 0, 0, NULL, 0), 2847 SND_SOC_DAPM_PGA("IF1 DAC6", SND_SOC_NOPM, 0, 0, NULL, 0), 2848 SND_SOC_DAPM_PGA("IF1 DAC7", SND_SOC_NOPM, 0, 0, NULL, 0), 2849 SND_SOC_DAPM_PGA("IF1 DAC01", SND_SOC_NOPM, 0, 0, NULL, 0), 2850 SND_SOC_DAPM_PGA("IF1 DAC23", SND_SOC_NOPM, 0, 0, NULL, 0), 2851 SND_SOC_DAPM_PGA("IF1 DAC45", SND_SOC_NOPM, 0, 0, NULL, 0), 2852 SND_SOC_DAPM_PGA("IF1 DAC67", SND_SOC_NOPM, 0, 0, NULL, 0), 2853 SND_SOC_DAPM_PGA("IF1 ADC1", SND_SOC_NOPM, 0, 0, NULL, 0), 2854 SND_SOC_DAPM_PGA("IF1 ADC2", SND_SOC_NOPM, 0, 0, NULL, 0), 2855 SND_SOC_DAPM_PGA("IF1 ADC3", SND_SOC_NOPM, 0, 0, NULL, 0), 2856 SND_SOC_DAPM_PGA("IF1 ADC4", SND_SOC_NOPM, 0, 0, NULL, 0), 2857 2858 SND_SOC_DAPM_SUPPLY("I2S2", RT5677_PWR_DIG1, 2859 RT5677_PWR_I2S2_BIT, 0, NULL, 0), 2860 SND_SOC_DAPM_PGA("IF2 DAC0", SND_SOC_NOPM, 0, 0, NULL, 0), 2861 SND_SOC_DAPM_PGA("IF2 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0), 2862 SND_SOC_DAPM_PGA("IF2 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0), 2863 SND_SOC_DAPM_PGA("IF2 DAC3", SND_SOC_NOPM, 0, 0, NULL, 0), 2864 SND_SOC_DAPM_PGA("IF2 DAC4", SND_SOC_NOPM, 0, 0, NULL, 0), 2865 SND_SOC_DAPM_PGA("IF2 DAC5", SND_SOC_NOPM, 0, 0, NULL, 0), 2866 SND_SOC_DAPM_PGA("IF2 DAC6", SND_SOC_NOPM, 0, 0, NULL, 0), 2867 SND_SOC_DAPM_PGA("IF2 DAC7", SND_SOC_NOPM, 0, 0, NULL, 0), 2868 SND_SOC_DAPM_PGA("IF2 DAC01", SND_SOC_NOPM, 0, 0, NULL, 0), 2869 SND_SOC_DAPM_PGA("IF2 DAC23", SND_SOC_NOPM, 0, 0, NULL, 0), 2870 SND_SOC_DAPM_PGA("IF2 DAC45", SND_SOC_NOPM, 0, 0, NULL, 0), 2871 SND_SOC_DAPM_PGA("IF2 DAC67", SND_SOC_NOPM, 0, 0, NULL, 0), 2872 SND_SOC_DAPM_PGA("IF2 ADC1", SND_SOC_NOPM, 0, 0, NULL, 0), 2873 SND_SOC_DAPM_PGA("IF2 ADC2", SND_SOC_NOPM, 0, 0, NULL, 0), 2874 SND_SOC_DAPM_PGA("IF2 ADC3", SND_SOC_NOPM, 0, 0, NULL, 0), 2875 SND_SOC_DAPM_PGA("IF2 ADC4", SND_SOC_NOPM, 0, 0, NULL, 0), 2876 2877 SND_SOC_DAPM_SUPPLY("I2S3", RT5677_PWR_DIG1, 2878 RT5677_PWR_I2S3_BIT, 0, NULL, 0), 2879 SND_SOC_DAPM_PGA("IF3 DAC", SND_SOC_NOPM, 0, 0, NULL, 0), 2880 SND_SOC_DAPM_PGA("IF3 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0), 2881 SND_SOC_DAPM_PGA("IF3 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0), 2882 SND_SOC_DAPM_PGA("IF3 ADC", SND_SOC_NOPM, 0, 0, NULL, 0), 2883 SND_SOC_DAPM_PGA("IF3 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0), 2884 SND_SOC_DAPM_PGA("IF3 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0), 2885 2886 SND_SOC_DAPM_SUPPLY("I2S4", RT5677_PWR_DIG1, 2887 RT5677_PWR_I2S4_BIT, 0, NULL, 0), 2888 SND_SOC_DAPM_PGA("IF4 DAC", SND_SOC_NOPM, 0, 0, NULL, 0), 2889 SND_SOC_DAPM_PGA("IF4 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0), 2890 SND_SOC_DAPM_PGA("IF4 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0), 2891 SND_SOC_DAPM_PGA("IF4 ADC", SND_SOC_NOPM, 0, 0, NULL, 0), 2892 SND_SOC_DAPM_PGA("IF4 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0), 2893 SND_SOC_DAPM_PGA("IF4 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0), 2894 2895 SND_SOC_DAPM_SUPPLY("SLB", RT5677_PWR_DIG1, 2896 RT5677_PWR_SLB_BIT, 0, NULL, 0), 2897 SND_SOC_DAPM_PGA("SLB DAC0", SND_SOC_NOPM, 0, 0, NULL, 0), 2898 SND_SOC_DAPM_PGA("SLB DAC1", SND_SOC_NOPM, 0, 0, NULL, 0), 2899 SND_SOC_DAPM_PGA("SLB DAC2", SND_SOC_NOPM, 0, 0, NULL, 0), 2900 SND_SOC_DAPM_PGA("SLB DAC3", SND_SOC_NOPM, 0, 0, NULL, 0), 2901 SND_SOC_DAPM_PGA("SLB DAC4", SND_SOC_NOPM, 0, 0, NULL, 0), 2902 SND_SOC_DAPM_PGA("SLB DAC5", SND_SOC_NOPM, 0, 0, NULL, 0), 2903 SND_SOC_DAPM_PGA("SLB DAC6", SND_SOC_NOPM, 0, 0, NULL, 0), 2904 SND_SOC_DAPM_PGA("SLB DAC7", SND_SOC_NOPM, 0, 0, NULL, 0), 2905 SND_SOC_DAPM_PGA("SLB DAC01", SND_SOC_NOPM, 0, 0, NULL, 0), 2906 SND_SOC_DAPM_PGA("SLB DAC23", SND_SOC_NOPM, 0, 0, NULL, 0), 2907 SND_SOC_DAPM_PGA("SLB DAC45", SND_SOC_NOPM, 0, 0, NULL, 0), 2908 SND_SOC_DAPM_PGA("SLB DAC67", SND_SOC_NOPM, 0, 0, NULL, 0), 2909 SND_SOC_DAPM_PGA("SLB ADC1", SND_SOC_NOPM, 0, 0, NULL, 0), 2910 SND_SOC_DAPM_PGA("SLB ADC2", SND_SOC_NOPM, 0, 0, NULL, 0), 2911 SND_SOC_DAPM_PGA("SLB ADC3", SND_SOC_NOPM, 0, 0, NULL, 0), 2912 SND_SOC_DAPM_PGA("SLB ADC4", SND_SOC_NOPM, 0, 0, NULL, 0), 2913 2914 /* Digital Interface Select */ 2915 SND_SOC_DAPM_MUX("IF1 ADC1 Mux", SND_SOC_NOPM, 0, 0, 2916 &rt5677_if1_adc1_mux), 2917 SND_SOC_DAPM_MUX("IF1 ADC2 Mux", SND_SOC_NOPM, 0, 0, 2918 &rt5677_if1_adc2_mux), 2919 SND_SOC_DAPM_MUX("IF1 ADC3 Mux", SND_SOC_NOPM, 0, 0, 2920 &rt5677_if1_adc3_mux), 2921 SND_SOC_DAPM_MUX("IF1 ADC4 Mux", SND_SOC_NOPM, 0, 0, 2922 &rt5677_if1_adc4_mux), 2923 SND_SOC_DAPM_MUX("IF1 ADC1 Swap Mux", SND_SOC_NOPM, 0, 0, 2924 &rt5677_if1_adc1_swap_mux), 2925 SND_SOC_DAPM_MUX("IF1 ADC2 Swap Mux", SND_SOC_NOPM, 0, 0, 2926 &rt5677_if1_adc2_swap_mux), 2927 SND_SOC_DAPM_MUX("IF1 ADC3 Swap Mux", SND_SOC_NOPM, 0, 0, 2928 &rt5677_if1_adc3_swap_mux), 2929 SND_SOC_DAPM_MUX("IF1 ADC4 Swap Mux", SND_SOC_NOPM, 0, 0, 2930 &rt5677_if1_adc4_swap_mux), 2931 SND_SOC_DAPM_MUX_E("IF1 ADC TDM Swap Mux", SND_SOC_NOPM, 0, 0, 2932 &rt5677_if1_adc_tdm_swap_mux, rt5677_if1_adc_tdm_event, 2933 SND_SOC_DAPM_PRE_PMU), 2934 SND_SOC_DAPM_MUX("IF2 ADC1 Mux", SND_SOC_NOPM, 0, 0, 2935 &rt5677_if2_adc1_mux), 2936 SND_SOC_DAPM_MUX("IF2 ADC2 Mux", SND_SOC_NOPM, 0, 0, 2937 &rt5677_if2_adc2_mux), 2938 SND_SOC_DAPM_MUX("IF2 ADC3 Mux", SND_SOC_NOPM, 0, 0, 2939 &rt5677_if2_adc3_mux), 2940 SND_SOC_DAPM_MUX("IF2 ADC4 Mux", SND_SOC_NOPM, 0, 0, 2941 &rt5677_if2_adc4_mux), 2942 SND_SOC_DAPM_MUX("IF2 ADC1 Swap Mux", SND_SOC_NOPM, 0, 0, 2943 &rt5677_if2_adc1_swap_mux), 2944 SND_SOC_DAPM_MUX("IF2 ADC2 Swap Mux", SND_SOC_NOPM, 0, 0, 2945 &rt5677_if2_adc2_swap_mux), 2946 SND_SOC_DAPM_MUX("IF2 ADC3 Swap Mux", SND_SOC_NOPM, 0, 0, 2947 &rt5677_if2_adc3_swap_mux), 2948 SND_SOC_DAPM_MUX("IF2 ADC4 Swap Mux", SND_SOC_NOPM, 0, 0, 2949 &rt5677_if2_adc4_swap_mux), 2950 SND_SOC_DAPM_MUX_E("IF2 ADC TDM Swap Mux", SND_SOC_NOPM, 0, 0, 2951 &rt5677_if2_adc_tdm_swap_mux, rt5677_if2_adc_tdm_event, 2952 SND_SOC_DAPM_PRE_PMU), 2953 SND_SOC_DAPM_MUX("IF3 ADC Mux", SND_SOC_NOPM, 0, 0, 2954 &rt5677_if3_adc_mux), 2955 SND_SOC_DAPM_MUX("IF4 ADC Mux", SND_SOC_NOPM, 0, 0, 2956 &rt5677_if4_adc_mux), 2957 SND_SOC_DAPM_MUX("SLB ADC1 Mux", SND_SOC_NOPM, 0, 0, 2958 &rt5677_slb_adc1_mux), 2959 SND_SOC_DAPM_MUX("SLB ADC2 Mux", SND_SOC_NOPM, 0, 0, 2960 &rt5677_slb_adc2_mux), 2961 SND_SOC_DAPM_MUX("SLB ADC3 Mux", SND_SOC_NOPM, 0, 0, 2962 &rt5677_slb_adc3_mux), 2963 SND_SOC_DAPM_MUX("SLB ADC4 Mux", SND_SOC_NOPM, 0, 0, 2964 &rt5677_slb_adc4_mux), 2965 2966 SND_SOC_DAPM_MUX("IF1 DAC0 Mux", SND_SOC_NOPM, 0, 0, 2967 &rt5677_if1_dac0_tdm_sel_mux), 2968 SND_SOC_DAPM_MUX("IF1 DAC1 Mux", SND_SOC_NOPM, 0, 0, 2969 &rt5677_if1_dac1_tdm_sel_mux), 2970 SND_SOC_DAPM_MUX("IF1 DAC2 Mux", SND_SOC_NOPM, 0, 0, 2971 &rt5677_if1_dac2_tdm_sel_mux), 2972 SND_SOC_DAPM_MUX("IF1 DAC3 Mux", SND_SOC_NOPM, 0, 0, 2973 &rt5677_if1_dac3_tdm_sel_mux), 2974 SND_SOC_DAPM_MUX("IF1 DAC4 Mux", SND_SOC_NOPM, 0, 0, 2975 &rt5677_if1_dac4_tdm_sel_mux), 2976 SND_SOC_DAPM_MUX("IF1 DAC5 Mux", SND_SOC_NOPM, 0, 0, 2977 &rt5677_if1_dac5_tdm_sel_mux), 2978 SND_SOC_DAPM_MUX("IF1 DAC6 Mux", SND_SOC_NOPM, 0, 0, 2979 &rt5677_if1_dac6_tdm_sel_mux), 2980 SND_SOC_DAPM_MUX("IF1 DAC7 Mux", SND_SOC_NOPM, 0, 0, 2981 &rt5677_if1_dac7_tdm_sel_mux), 2982 2983 SND_SOC_DAPM_MUX("IF2 DAC0 Mux", SND_SOC_NOPM, 0, 0, 2984 &rt5677_if2_dac0_tdm_sel_mux), 2985 SND_SOC_DAPM_MUX("IF2 DAC1 Mux", SND_SOC_NOPM, 0, 0, 2986 &rt5677_if2_dac1_tdm_sel_mux), 2987 SND_SOC_DAPM_MUX("IF2 DAC2 Mux", SND_SOC_NOPM, 0, 0, 2988 &rt5677_if2_dac2_tdm_sel_mux), 2989 SND_SOC_DAPM_MUX("IF2 DAC3 Mux", SND_SOC_NOPM, 0, 0, 2990 &rt5677_if2_dac3_tdm_sel_mux), 2991 SND_SOC_DAPM_MUX("IF2 DAC4 Mux", SND_SOC_NOPM, 0, 0, 2992 &rt5677_if2_dac4_tdm_sel_mux), 2993 SND_SOC_DAPM_MUX("IF2 DAC5 Mux", SND_SOC_NOPM, 0, 0, 2994 &rt5677_if2_dac5_tdm_sel_mux), 2995 SND_SOC_DAPM_MUX("IF2 DAC6 Mux", SND_SOC_NOPM, 0, 0, 2996 &rt5677_if2_dac6_tdm_sel_mux), 2997 SND_SOC_DAPM_MUX("IF2 DAC7 Mux", SND_SOC_NOPM, 0, 0, 2998 &rt5677_if2_dac7_tdm_sel_mux), 2999 3000 /* Audio Interface */ 3001 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0), 3002 SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0), 3003 SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0), 3004 SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0), 3005 SND_SOC_DAPM_AIF_IN("AIF3RX", "AIF3 Playback", 0, SND_SOC_NOPM, 0, 0), 3006 SND_SOC_DAPM_AIF_OUT("AIF3TX", "AIF3 Capture", 0, SND_SOC_NOPM, 0, 0), 3007 SND_SOC_DAPM_AIF_IN("AIF4RX", "AIF4 Playback", 0, SND_SOC_NOPM, 0, 0), 3008 SND_SOC_DAPM_AIF_OUT("AIF4TX", "AIF4 Capture", 0, SND_SOC_NOPM, 0, 0), 3009 SND_SOC_DAPM_AIF_IN("SLBRX", "SLIMBus Playback", 0, SND_SOC_NOPM, 0, 0), 3010 SND_SOC_DAPM_AIF_OUT("SLBTX", "SLIMBus Capture", 0, SND_SOC_NOPM, 0, 0), 3011 3012 /* Sidetone Mux */ 3013 SND_SOC_DAPM_MUX("Sidetone Mux", SND_SOC_NOPM, 0, 0, 3014 &rt5677_sidetone_mux), 3015 SND_SOC_DAPM_SUPPLY("Sidetone Power", RT5677_SIDETONE_CTRL, 3016 RT5677_ST_EN_SFT, 0, NULL, 0), 3017 3018 /* VAD Mux*/ 3019 SND_SOC_DAPM_MUX("VAD ADC Mux", SND_SOC_NOPM, 0, 0, 3020 &rt5677_vad_src_mux), 3021 3022 /* Tensilica DSP */ 3023 SND_SOC_DAPM_PGA("Tensilica DSP", SND_SOC_NOPM, 0, 0, NULL, 0), 3024 SND_SOC_DAPM_MIXER("OB01 MIX", SND_SOC_NOPM, 0, 0, 3025 rt5677_ob_01_mix, ARRAY_SIZE(rt5677_ob_01_mix)), 3026 SND_SOC_DAPM_MIXER("OB23 MIX", SND_SOC_NOPM, 0, 0, 3027 rt5677_ob_23_mix, ARRAY_SIZE(rt5677_ob_23_mix)), 3028 SND_SOC_DAPM_MIXER("OB4 MIX", SND_SOC_NOPM, 0, 0, 3029 rt5677_ob_4_mix, ARRAY_SIZE(rt5677_ob_4_mix)), 3030 SND_SOC_DAPM_MIXER("OB5 MIX", SND_SOC_NOPM, 0, 0, 3031 rt5677_ob_5_mix, ARRAY_SIZE(rt5677_ob_5_mix)), 3032 SND_SOC_DAPM_MIXER("OB6 MIX", SND_SOC_NOPM, 0, 0, 3033 rt5677_ob_6_mix, ARRAY_SIZE(rt5677_ob_6_mix)), 3034 SND_SOC_DAPM_MIXER("OB7 MIX", SND_SOC_NOPM, 0, 0, 3035 rt5677_ob_7_mix, ARRAY_SIZE(rt5677_ob_7_mix)), 3036 3037 /* Output Side */ 3038 /* DAC mixer before sound effect */ 3039 SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0, 3040 rt5677_dac_l_mix, ARRAY_SIZE(rt5677_dac_l_mix)), 3041 SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0, 3042 rt5677_dac_r_mix, ARRAY_SIZE(rt5677_dac_r_mix)), 3043 SND_SOC_DAPM_PGA("DAC1 FS", SND_SOC_NOPM, 0, 0, NULL, 0), 3044 3045 /* DAC Mux */ 3046 SND_SOC_DAPM_MUX("DAC1 Mux", SND_SOC_NOPM, 0, 0, 3047 &rt5677_dac1_mux), 3048 SND_SOC_DAPM_MUX("ADDA1 Mux", SND_SOC_NOPM, 0, 0, 3049 &rt5677_adda1_mux), 3050 SND_SOC_DAPM_MUX("DAC12 SRC Mux", SND_SOC_NOPM, 0, 0, 3051 &rt5677_dac12_mux), 3052 SND_SOC_DAPM_MUX("DAC3 SRC Mux", SND_SOC_NOPM, 0, 0, 3053 &rt5677_dac3_mux), 3054 3055 /* DAC2 channel Mux */ 3056 SND_SOC_DAPM_MUX("DAC2 L Mux", SND_SOC_NOPM, 0, 0, 3057 &rt5677_dac2_l_mux), 3058 SND_SOC_DAPM_MUX("DAC2 R Mux", SND_SOC_NOPM, 0, 0, 3059 &rt5677_dac2_r_mux), 3060 3061 /* DAC3 channel Mux */ 3062 SND_SOC_DAPM_MUX("DAC3 L Mux", SND_SOC_NOPM, 0, 0, 3063 &rt5677_dac3_l_mux), 3064 SND_SOC_DAPM_MUX("DAC3 R Mux", SND_SOC_NOPM, 0, 0, 3065 &rt5677_dac3_r_mux), 3066 3067 /* DAC4 channel Mux */ 3068 SND_SOC_DAPM_MUX("DAC4 L Mux", SND_SOC_NOPM, 0, 0, 3069 &rt5677_dac4_l_mux), 3070 SND_SOC_DAPM_MUX("DAC4 R Mux", SND_SOC_NOPM, 0, 0, 3071 &rt5677_dac4_r_mux), 3072 3073 /* DAC Mixer */ 3074 SND_SOC_DAPM_SUPPLY("dac stereo1 filter", RT5677_PWR_DIG2, 3075 RT5677_PWR_DAC_S1F_BIT, 0, rt5677_filter_power_event, 3076 SND_SOC_DAPM_POST_PMU), 3077 SND_SOC_DAPM_SUPPLY("dac mono2 left filter", RT5677_PWR_DIG2, 3078 RT5677_PWR_DAC_M2F_L_BIT, 0, rt5677_filter_power_event, 3079 SND_SOC_DAPM_POST_PMU), 3080 SND_SOC_DAPM_SUPPLY("dac mono2 right filter", RT5677_PWR_DIG2, 3081 RT5677_PWR_DAC_M2F_R_BIT, 0, rt5677_filter_power_event, 3082 SND_SOC_DAPM_POST_PMU), 3083 SND_SOC_DAPM_SUPPLY("dac mono3 left filter", RT5677_PWR_DIG2, 3084 RT5677_PWR_DAC_M3F_L_BIT, 0, rt5677_filter_power_event, 3085 SND_SOC_DAPM_POST_PMU), 3086 SND_SOC_DAPM_SUPPLY("dac mono3 right filter", RT5677_PWR_DIG2, 3087 RT5677_PWR_DAC_M3F_R_BIT, 0, rt5677_filter_power_event, 3088 SND_SOC_DAPM_POST_PMU), 3089 SND_SOC_DAPM_SUPPLY("dac mono4 left filter", RT5677_PWR_DIG2, 3090 RT5677_PWR_DAC_M4F_L_BIT, 0, rt5677_filter_power_event, 3091 SND_SOC_DAPM_POST_PMU), 3092 SND_SOC_DAPM_SUPPLY("dac mono4 right filter", RT5677_PWR_DIG2, 3093 RT5677_PWR_DAC_M4F_R_BIT, 0, rt5677_filter_power_event, 3094 SND_SOC_DAPM_POST_PMU), 3095 3096 SND_SOC_DAPM_MIXER("Stereo DAC MIXL", SND_SOC_NOPM, 0, 0, 3097 rt5677_sto1_dac_l_mix, ARRAY_SIZE(rt5677_sto1_dac_l_mix)), 3098 SND_SOC_DAPM_MIXER("Stereo DAC MIXR", SND_SOC_NOPM, 0, 0, 3099 rt5677_sto1_dac_r_mix, ARRAY_SIZE(rt5677_sto1_dac_r_mix)), 3100 SND_SOC_DAPM_MIXER("Mono DAC MIXL", SND_SOC_NOPM, 0, 0, 3101 rt5677_mono_dac_l_mix, ARRAY_SIZE(rt5677_mono_dac_l_mix)), 3102 SND_SOC_DAPM_MIXER("Mono DAC MIXR", SND_SOC_NOPM, 0, 0, 3103 rt5677_mono_dac_r_mix, ARRAY_SIZE(rt5677_mono_dac_r_mix)), 3104 SND_SOC_DAPM_MIXER("DD1 MIXL", SND_SOC_NOPM, 0, 0, 3105 rt5677_dd1_l_mix, ARRAY_SIZE(rt5677_dd1_l_mix)), 3106 SND_SOC_DAPM_MIXER("DD1 MIXR", SND_SOC_NOPM, 0, 0, 3107 rt5677_dd1_r_mix, ARRAY_SIZE(rt5677_dd1_r_mix)), 3108 SND_SOC_DAPM_MIXER("DD2 MIXL", SND_SOC_NOPM, 0, 0, 3109 rt5677_dd2_l_mix, ARRAY_SIZE(rt5677_dd2_l_mix)), 3110 SND_SOC_DAPM_MIXER("DD2 MIXR", SND_SOC_NOPM, 0, 0, 3111 rt5677_dd2_r_mix, ARRAY_SIZE(rt5677_dd2_r_mix)), 3112 SND_SOC_DAPM_PGA("Stereo DAC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 3113 SND_SOC_DAPM_PGA("Mono DAC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 3114 SND_SOC_DAPM_PGA("DD1 MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 3115 SND_SOC_DAPM_PGA("DD2 MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 3116 3117 /* DACs */ 3118 SND_SOC_DAPM_DAC("DAC 1", NULL, RT5677_PWR_DIG1, 3119 RT5677_PWR_DAC1_BIT, 0), 3120 SND_SOC_DAPM_DAC("DAC 2", NULL, RT5677_PWR_DIG1, 3121 RT5677_PWR_DAC2_BIT, 0), 3122 SND_SOC_DAPM_DAC("DAC 3", NULL, RT5677_PWR_DIG1, 3123 RT5677_PWR_DAC3_BIT, 0), 3124 3125 /* PDM */ 3126 SND_SOC_DAPM_SUPPLY("PDM1 Power", RT5677_PWR_DIG2, 3127 RT5677_PWR_PDM1_BIT, 0, NULL, 0), 3128 SND_SOC_DAPM_SUPPLY("PDM2 Power", RT5677_PWR_DIG2, 3129 RT5677_PWR_PDM2_BIT, 0, NULL, 0), 3130 3131 SND_SOC_DAPM_MUX("PDM1 L Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM1_L_SFT, 3132 1, &rt5677_pdm1_l_mux), 3133 SND_SOC_DAPM_MUX("PDM1 R Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM1_R_SFT, 3134 1, &rt5677_pdm1_r_mux), 3135 SND_SOC_DAPM_MUX("PDM2 L Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM2_L_SFT, 3136 1, &rt5677_pdm2_l_mux), 3137 SND_SOC_DAPM_MUX("PDM2 R Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM2_R_SFT, 3138 1, &rt5677_pdm2_r_mux), 3139 3140 SND_SOC_DAPM_PGA_S("LOUT1 amp", 0, RT5677_PWR_ANLG1, RT5677_PWR_LO1_BIT, 3141 0, NULL, 0), 3142 SND_SOC_DAPM_PGA_S("LOUT2 amp", 0, RT5677_PWR_ANLG1, RT5677_PWR_LO2_BIT, 3143 0, NULL, 0), 3144 SND_SOC_DAPM_PGA_S("LOUT3 amp", 0, RT5677_PWR_ANLG1, RT5677_PWR_LO3_BIT, 3145 0, NULL, 0), 3146 3147 SND_SOC_DAPM_PGA_S("LOUT1 vref", 1, SND_SOC_NOPM, 0, 0, 3148 rt5677_vref_event, SND_SOC_DAPM_POST_PMU), 3149 SND_SOC_DAPM_PGA_S("LOUT2 vref", 1, SND_SOC_NOPM, 0, 0, 3150 rt5677_vref_event, SND_SOC_DAPM_POST_PMU), 3151 SND_SOC_DAPM_PGA_S("LOUT3 vref", 1, SND_SOC_NOPM, 0, 0, 3152 rt5677_vref_event, SND_SOC_DAPM_POST_PMU), 3153 3154 /* Output Lines */ 3155 SND_SOC_DAPM_OUTPUT("LOUT1"), 3156 SND_SOC_DAPM_OUTPUT("LOUT2"), 3157 SND_SOC_DAPM_OUTPUT("LOUT3"), 3158 SND_SOC_DAPM_OUTPUT("PDM1L"), 3159 SND_SOC_DAPM_OUTPUT("PDM1R"), 3160 SND_SOC_DAPM_OUTPUT("PDM2L"), 3161 SND_SOC_DAPM_OUTPUT("PDM2R"), 3162 3163 SND_SOC_DAPM_POST("vref", rt5677_vref_event), 3164 }; 3165 3166 static const struct snd_soc_dapm_route rt5677_dapm_routes[] = { 3167 { "Stereo1 DMIC Mux", NULL, "DMIC STO1 ASRC", rt5677_dmic_use_asrc }, 3168 { "Stereo2 DMIC Mux", NULL, "DMIC STO2 ASRC", rt5677_dmic_use_asrc }, 3169 { "Stereo3 DMIC Mux", NULL, "DMIC STO3 ASRC", rt5677_dmic_use_asrc }, 3170 { "Stereo4 DMIC Mux", NULL, "DMIC STO4 ASRC", rt5677_dmic_use_asrc }, 3171 { "Mono DMIC L Mux", NULL, "DMIC MONO L ASRC", rt5677_dmic_use_asrc }, 3172 { "Mono DMIC R Mux", NULL, "DMIC MONO R ASRC", rt5677_dmic_use_asrc }, 3173 { "I2S1", NULL, "I2S1 ASRC", can_use_asrc}, 3174 { "I2S2", NULL, "I2S2 ASRC", can_use_asrc}, 3175 { "I2S3", NULL, "I2S3 ASRC", can_use_asrc}, 3176 { "I2S4", NULL, "I2S4 ASRC", can_use_asrc}, 3177 3178 { "dac stereo1 filter", NULL, "DAC STO ASRC", is_using_asrc }, 3179 { "dac mono2 left filter", NULL, "DAC MONO2 L ASRC", is_using_asrc }, 3180 { "dac mono2 right filter", NULL, "DAC MONO2 R ASRC", is_using_asrc }, 3181 { "dac mono3 left filter", NULL, "DAC MONO3 L ASRC", is_using_asrc }, 3182 { "dac mono3 right filter", NULL, "DAC MONO3 R ASRC", is_using_asrc }, 3183 { "dac mono4 left filter", NULL, "DAC MONO4 L ASRC", is_using_asrc }, 3184 { "dac mono4 right filter", NULL, "DAC MONO4 R ASRC", is_using_asrc }, 3185 { "adc stereo1 filter", NULL, "ADC STO1 ASRC", is_using_asrc }, 3186 { "adc stereo2 filter", NULL, "ADC STO2 ASRC", is_using_asrc }, 3187 { "adc stereo3 filter", NULL, "ADC STO3 ASRC", is_using_asrc }, 3188 { "adc stereo4 filter", NULL, "ADC STO4 ASRC", is_using_asrc }, 3189 { "adc mono left filter", NULL, "ADC MONO L ASRC", is_using_asrc }, 3190 { "adc mono right filter", NULL, "ADC MONO R ASRC", is_using_asrc }, 3191 3192 { "DMIC1", NULL, "DMIC L1" }, 3193 { "DMIC1", NULL, "DMIC R1" }, 3194 { "DMIC2", NULL, "DMIC L2" }, 3195 { "DMIC2", NULL, "DMIC R2" }, 3196 { "DMIC3", NULL, "DMIC L3" }, 3197 { "DMIC3", NULL, "DMIC R3" }, 3198 { "DMIC4", NULL, "DMIC L4" }, 3199 { "DMIC4", NULL, "DMIC R4" }, 3200 3201 { "DMIC L1", NULL, "DMIC CLK" }, 3202 { "DMIC R1", NULL, "DMIC CLK" }, 3203 { "DMIC L2", NULL, "DMIC CLK" }, 3204 { "DMIC R2", NULL, "DMIC CLK" }, 3205 { "DMIC L3", NULL, "DMIC CLK" }, 3206 { "DMIC R3", NULL, "DMIC CLK" }, 3207 { "DMIC L4", NULL, "DMIC CLK" }, 3208 { "DMIC R4", NULL, "DMIC CLK" }, 3209 3210 { "DMIC L1", NULL, "DMIC1 power" }, 3211 { "DMIC R1", NULL, "DMIC1 power" }, 3212 { "DMIC L3", NULL, "DMIC3 power" }, 3213 { "DMIC R3", NULL, "DMIC3 power" }, 3214 { "DMIC L4", NULL, "DMIC4 power" }, 3215 { "DMIC R4", NULL, "DMIC4 power" }, 3216 3217 { "BST1", NULL, "IN1P" }, 3218 { "BST1", NULL, "IN1N" }, 3219 { "BST2", NULL, "IN2P" }, 3220 { "BST2", NULL, "IN2N" }, 3221 3222 { "IN1P", NULL, "MICBIAS1" }, 3223 { "IN1N", NULL, "MICBIAS1" }, 3224 { "IN2P", NULL, "MICBIAS1" }, 3225 { "IN2N", NULL, "MICBIAS1" }, 3226 3227 { "ADC 1", NULL, "BST1" }, 3228 { "ADC 1", NULL, "ADC 1 power" }, 3229 { "ADC 1", NULL, "ADC1 clock" }, 3230 { "ADC 2", NULL, "BST2" }, 3231 { "ADC 2", NULL, "ADC 2 power" }, 3232 { "ADC 2", NULL, "ADC2 clock" }, 3233 3234 { "Stereo1 DMIC Mux", "DMIC1", "DMIC1" }, 3235 { "Stereo1 DMIC Mux", "DMIC2", "DMIC2" }, 3236 { "Stereo1 DMIC Mux", "DMIC3", "DMIC3" }, 3237 { "Stereo1 DMIC Mux", "DMIC4", "DMIC4" }, 3238 3239 { "Stereo2 DMIC Mux", "DMIC1", "DMIC1" }, 3240 { "Stereo2 DMIC Mux", "DMIC2", "DMIC2" }, 3241 { "Stereo2 DMIC Mux", "DMIC3", "DMIC3" }, 3242 { "Stereo2 DMIC Mux", "DMIC4", "DMIC4" }, 3243 3244 { "Stereo3 DMIC Mux", "DMIC1", "DMIC1" }, 3245 { "Stereo3 DMIC Mux", "DMIC2", "DMIC2" }, 3246 { "Stereo3 DMIC Mux", "DMIC3", "DMIC3" }, 3247 { "Stereo3 DMIC Mux", "DMIC4", "DMIC4" }, 3248 3249 { "Stereo4 DMIC Mux", "DMIC1", "DMIC1" }, 3250 { "Stereo4 DMIC Mux", "DMIC2", "DMIC2" }, 3251 { "Stereo4 DMIC Mux", "DMIC3", "DMIC3" }, 3252 { "Stereo4 DMIC Mux", "DMIC4", "DMIC4" }, 3253 3254 { "Mono DMIC L Mux", "DMIC1", "DMIC1" }, 3255 { "Mono DMIC L Mux", "DMIC2", "DMIC2" }, 3256 { "Mono DMIC L Mux", "DMIC3", "DMIC3" }, 3257 { "Mono DMIC L Mux", "DMIC4", "DMIC4" }, 3258 3259 { "Mono DMIC R Mux", "DMIC1", "DMIC1" }, 3260 { "Mono DMIC R Mux", "DMIC2", "DMIC2" }, 3261 { "Mono DMIC R Mux", "DMIC3", "DMIC3" }, 3262 { "Mono DMIC R Mux", "DMIC4", "DMIC4" }, 3263 3264 { "ADC 1_2", NULL, "ADC 1" }, 3265 { "ADC 1_2", NULL, "ADC 2" }, 3266 3267 { "Stereo1 ADC1 Mux", "DD MIX1", "DD1 MIX" }, 3268 { "Stereo1 ADC1 Mux", "ADC1/2", "ADC 1_2" }, 3269 { "Stereo1 ADC1 Mux", "Stereo DAC MIX", "Stereo DAC MIX" }, 3270 3271 { "Stereo1 ADC2 Mux", "DD MIX1", "DD1 MIX" }, 3272 { "Stereo1 ADC2 Mux", "DMIC", "Stereo1 DMIC Mux" }, 3273 { "Stereo1 ADC2 Mux", "Stereo DAC MIX", "Stereo DAC MIX" }, 3274 3275 { "Stereo2 ADC1 Mux", "DD MIX1", "DD1 MIX" }, 3276 { "Stereo2 ADC1 Mux", "ADC1/2", "ADC 1_2" }, 3277 { "Stereo2 ADC1 Mux", "Stereo DAC MIX", "Stereo DAC MIX" }, 3278 3279 { "Stereo2 ADC2 Mux", "DD MIX1", "DD1 MIX" }, 3280 { "Stereo2 ADC2 Mux", "DMIC", "Stereo2 DMIC Mux" }, 3281 { "Stereo2 ADC2 Mux", "Stereo DAC MIX", "Stereo DAC MIX" }, 3282 3283 { "Stereo3 ADC1 Mux", "DD MIX1", "DD1 MIX" }, 3284 { "Stereo3 ADC1 Mux", "ADC1/2", "ADC 1_2" }, 3285 { "Stereo3 ADC1 Mux", "Stereo DAC MIX", "Stereo DAC MIX" }, 3286 3287 { "Stereo3 ADC2 Mux", "DD MIX1", "DD1 MIX" }, 3288 { "Stereo3 ADC2 Mux", "DMIC", "Stereo3 DMIC Mux" }, 3289 { "Stereo3 ADC2 Mux", "Stereo DAC MIX", "Stereo DAC MIX" }, 3290 3291 { "Stereo4 ADC1 Mux", "DD MIX1", "DD1 MIX" }, 3292 { "Stereo4 ADC1 Mux", "ADC1/2", "ADC 1_2" }, 3293 { "Stereo4 ADC1 Mux", "DD MIX2", "DD2 MIX" }, 3294 3295 { "Stereo4 ADC2 Mux", "DD MIX1", "DD1 MIX" }, 3296 { "Stereo4 ADC2 Mux", "DMIC", "Stereo3 DMIC Mux" }, 3297 { "Stereo4 ADC2 Mux", "DD MIX2", "DD2 MIX" }, 3298 3299 { "Mono ADC2 L Mux", "DD MIX1L", "DD1 MIXL" }, 3300 { "Mono ADC2 L Mux", "DMIC", "Mono DMIC L Mux" }, 3301 { "Mono ADC2 L Mux", "MONO DAC MIXL", "Mono DAC MIXL" }, 3302 3303 { "Mono ADC1 L Mux", "DD MIX1L", "DD1 MIXL" }, 3304 { "Mono ADC1 L Mux", "ADC1", "ADC 1" }, 3305 { "Mono ADC1 L Mux", "MONO DAC MIXL", "Mono DAC MIXL" }, 3306 3307 { "Mono ADC1 R Mux", "DD MIX1R", "DD1 MIXR" }, 3308 { "Mono ADC1 R Mux", "ADC2", "ADC 2" }, 3309 { "Mono ADC1 R Mux", "MONO DAC MIXR", "Mono DAC MIXR" }, 3310 3311 { "Mono ADC2 R Mux", "DD MIX1R", "DD1 MIXR" }, 3312 { "Mono ADC2 R Mux", "DMIC", "Mono DMIC R Mux" }, 3313 { "Mono ADC2 R Mux", "MONO DAC MIXR", "Mono DAC MIXR" }, 3314 3315 { "Sto1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC1 Mux" }, 3316 { "Sto1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC2 Mux" }, 3317 { "Sto1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC1 Mux" }, 3318 { "Sto1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC2 Mux" }, 3319 3320 { "Stereo1 ADC MIXL", NULL, "Sto1 ADC MIXL" }, 3321 { "Stereo1 ADC MIXL", NULL, "adc stereo1 filter" }, 3322 { "Stereo1 ADC MIXR", NULL, "Sto1 ADC MIXR" }, 3323 { "Stereo1 ADC MIXR", NULL, "adc stereo1 filter" }, 3324 { "adc stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll }, 3325 3326 { "Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXL" }, 3327 { "Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXR" }, 3328 3329 { "Sto2 ADC MIXL", "ADC1 Switch", "Stereo2 ADC1 Mux" }, 3330 { "Sto2 ADC MIXL", "ADC2 Switch", "Stereo2 ADC2 Mux" }, 3331 { "Sto2 ADC MIXR", "ADC1 Switch", "Stereo2 ADC1 Mux" }, 3332 { "Sto2 ADC MIXR", "ADC2 Switch", "Stereo2 ADC2 Mux" }, 3333 3334 { "Sto2 ADC LR MIX", NULL, "Sto2 ADC MIXL" }, 3335 { "Sto2 ADC LR MIX", NULL, "Sto2 ADC MIXR" }, 3336 3337 { "Stereo2 ADC LR Mux", "L", "Sto2 ADC MIXL" }, 3338 { "Stereo2 ADC LR Mux", "LR", "Sto2 ADC LR MIX" }, 3339 3340 { "Stereo2 ADC MIXL", NULL, "Stereo2 ADC LR Mux" }, 3341 { "Stereo2 ADC MIXL", NULL, "adc stereo2 filter" }, 3342 { "Stereo2 ADC MIXR", NULL, "Sto2 ADC MIXR" }, 3343 { "Stereo2 ADC MIXR", NULL, "adc stereo2 filter" }, 3344 { "adc stereo2 filter", NULL, "PLL1", is_sys_clk_from_pll }, 3345 3346 { "Stereo2 ADC MIX", NULL, "Stereo2 ADC MIXL" }, 3347 { "Stereo2 ADC MIX", NULL, "Stereo2 ADC MIXR" }, 3348 3349 { "Sto3 ADC MIXL", "ADC1 Switch", "Stereo3 ADC1 Mux" }, 3350 { "Sto3 ADC MIXL", "ADC2 Switch", "Stereo3 ADC2 Mux" }, 3351 { "Sto3 ADC MIXR", "ADC1 Switch", "Stereo3 ADC1 Mux" }, 3352 { "Sto3 ADC MIXR", "ADC2 Switch", "Stereo3 ADC2 Mux" }, 3353 3354 { "Stereo3 ADC MIXL", NULL, "Sto3 ADC MIXL" }, 3355 { "Stereo3 ADC MIXL", NULL, "adc stereo3 filter" }, 3356 { "Stereo3 ADC MIXR", NULL, "Sto3 ADC MIXR" }, 3357 { "Stereo3 ADC MIXR", NULL, "adc stereo3 filter" }, 3358 { "adc stereo3 filter", NULL, "PLL1", is_sys_clk_from_pll }, 3359 3360 { "Stereo3 ADC MIX", NULL, "Stereo3 ADC MIXL" }, 3361 { "Stereo3 ADC MIX", NULL, "Stereo3 ADC MIXR" }, 3362 3363 { "Sto4 ADC MIXL", "ADC1 Switch", "Stereo4 ADC1 Mux" }, 3364 { "Sto4 ADC MIXL", "ADC2 Switch", "Stereo4 ADC2 Mux" }, 3365 { "Sto4 ADC MIXR", "ADC1 Switch", "Stereo4 ADC1 Mux" }, 3366 { "Sto4 ADC MIXR", "ADC2 Switch", "Stereo4 ADC2 Mux" }, 3367 3368 { "Stereo4 ADC MIXL", NULL, "Sto4 ADC MIXL" }, 3369 { "Stereo4 ADC MIXL", NULL, "adc stereo4 filter" }, 3370 { "Stereo4 ADC MIXR", NULL, "Sto4 ADC MIXR" }, 3371 { "Stereo4 ADC MIXR", NULL, "adc stereo4 filter" }, 3372 { "adc stereo4 filter", NULL, "PLL1", is_sys_clk_from_pll }, 3373 3374 { "Stereo4 ADC MIX", NULL, "Stereo4 ADC MIXL" }, 3375 { "Stereo4 ADC MIX", NULL, "Stereo4 ADC MIXR" }, 3376 3377 { "Mono ADC MIXL", "ADC1 Switch", "Mono ADC1 L Mux" }, 3378 { "Mono ADC MIXL", "ADC2 Switch", "Mono ADC2 L Mux" }, 3379 { "Mono ADC MIXL", NULL, "adc mono left filter" }, 3380 { "adc mono left filter", NULL, "PLL1", is_sys_clk_from_pll }, 3381 3382 { "Mono ADC MIXR", "ADC1 Switch", "Mono ADC1 R Mux" }, 3383 { "Mono ADC MIXR", "ADC2 Switch", "Mono ADC2 R Mux" }, 3384 { "Mono ADC MIXR", NULL, "adc mono right filter" }, 3385 { "adc mono right filter", NULL, "PLL1", is_sys_clk_from_pll }, 3386 3387 { "Mono ADC MIX", NULL, "Mono ADC MIXL" }, 3388 { "Mono ADC MIX", NULL, "Mono ADC MIXR" }, 3389 3390 { "VAD ADC Mux", "STO1 ADC MIX L", "Stereo1 ADC MIXL" }, 3391 { "VAD ADC Mux", "MONO ADC MIX L", "Mono ADC MIXL" }, 3392 { "VAD ADC Mux", "MONO ADC MIX R", "Mono ADC MIXR" }, 3393 { "VAD ADC Mux", "STO2 ADC MIX L", "Stereo2 ADC MIXL" }, 3394 { "VAD ADC Mux", "STO3 ADC MIX L", "Stereo3 ADC MIXL" }, 3395 3396 { "IF1 ADC1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" }, 3397 { "IF1 ADC1 Mux", "OB01", "OB01 Bypass Mux" }, 3398 { "IF1 ADC1 Mux", "VAD ADC", "VAD ADC Mux" }, 3399 3400 { "IF1 ADC2 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" }, 3401 { "IF1 ADC2 Mux", "OB23", "OB23 Bypass Mux" }, 3402 3403 { "IF1 ADC3 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" }, 3404 { "IF1 ADC3 Mux", "MONO ADC MIX", "Mono ADC MIX" }, 3405 { "IF1 ADC3 Mux", "OB45", "OB45" }, 3406 3407 { "IF1 ADC4 Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" }, 3408 { "IF1 ADC4 Mux", "OB67", "OB67" }, 3409 { "IF1 ADC4 Mux", "OB01", "OB01 Bypass Mux" }, 3410 3411 { "IF1 ADC1 Swap Mux", "L/R", "IF1 ADC1 Mux" }, 3412 { "IF1 ADC1 Swap Mux", "R/L", "IF1 ADC1 Mux" }, 3413 { "IF1 ADC1 Swap Mux", "L/L", "IF1 ADC1 Mux" }, 3414 { "IF1 ADC1 Swap Mux", "R/R", "IF1 ADC1 Mux" }, 3415 3416 { "IF1 ADC2 Swap Mux", "L/R", "IF1 ADC2 Mux" }, 3417 { "IF1 ADC2 Swap Mux", "R/L", "IF1 ADC2 Mux" }, 3418 { "IF1 ADC2 Swap Mux", "L/L", "IF1 ADC2 Mux" }, 3419 { "IF1 ADC2 Swap Mux", "R/R", "IF1 ADC2 Mux" }, 3420 3421 { "IF1 ADC3 Swap Mux", "L/R", "IF1 ADC3 Mux" }, 3422 { "IF1 ADC3 Swap Mux", "R/L", "IF1 ADC3 Mux" }, 3423 { "IF1 ADC3 Swap Mux", "L/L", "IF1 ADC3 Mux" }, 3424 { "IF1 ADC3 Swap Mux", "R/R", "IF1 ADC3 Mux" }, 3425 3426 { "IF1 ADC4 Swap Mux", "L/R", "IF1 ADC4 Mux" }, 3427 { "IF1 ADC4 Swap Mux", "R/L", "IF1 ADC4 Mux" }, 3428 { "IF1 ADC4 Swap Mux", "L/L", "IF1 ADC4 Mux" }, 3429 { "IF1 ADC4 Swap Mux", "R/R", "IF1 ADC4 Mux" }, 3430 3431 { "IF1 ADC", NULL, "IF1 ADC1 Swap Mux" }, 3432 { "IF1 ADC", NULL, "IF1 ADC2 Swap Mux" }, 3433 { "IF1 ADC", NULL, "IF1 ADC3 Swap Mux" }, 3434 { "IF1 ADC", NULL, "IF1 ADC4 Swap Mux" }, 3435 3436 { "IF1 ADC TDM Swap Mux", "1/2/3/4", "IF1 ADC" }, 3437 { "IF1 ADC TDM Swap Mux", "2/1/3/4", "IF1 ADC" }, 3438 { "IF1 ADC TDM Swap Mux", "2/3/1/4", "IF1 ADC" }, 3439 { "IF1 ADC TDM Swap Mux", "4/1/2/3", "IF1 ADC" }, 3440 { "IF1 ADC TDM Swap Mux", "1/3/2/4", "IF1 ADC" }, 3441 { "IF1 ADC TDM Swap Mux", "1/4/2/3", "IF1 ADC" }, 3442 { "IF1 ADC TDM Swap Mux", "3/1/2/4", "IF1 ADC" }, 3443 { "IF1 ADC TDM Swap Mux", "3/4/1/2", "IF1 ADC" }, 3444 3445 { "AIF1TX", NULL, "I2S1" }, 3446 { "AIF1TX", NULL, "IF1 ADC TDM Swap Mux" }, 3447 3448 { "IF2 ADC1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" }, 3449 { "IF2 ADC1 Mux", "OB01", "OB01 Bypass Mux" }, 3450 { "IF2 ADC1 Mux", "VAD ADC", "VAD ADC Mux" }, 3451 3452 { "IF2 ADC2 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" }, 3453 { "IF2 ADC2 Mux", "OB23", "OB23 Bypass Mux" }, 3454 3455 { "IF2 ADC3 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" }, 3456 { "IF2 ADC3 Mux", "MONO ADC MIX", "Mono ADC MIX" }, 3457 { "IF2 ADC3 Mux", "OB45", "OB45" }, 3458 3459 { "IF2 ADC4 Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" }, 3460 { "IF2 ADC4 Mux", "OB67", "OB67" }, 3461 { "IF2 ADC4 Mux", "OB01", "OB01 Bypass Mux" }, 3462 3463 { "IF2 ADC1 Swap Mux", "L/R", "IF2 ADC1 Mux" }, 3464 { "IF2 ADC1 Swap Mux", "R/L", "IF2 ADC1 Mux" }, 3465 { "IF2 ADC1 Swap Mux", "L/L", "IF2 ADC1 Mux" }, 3466 { "IF2 ADC1 Swap Mux", "R/R", "IF2 ADC1 Mux" }, 3467 3468 { "IF2 ADC2 Swap Mux", "L/R", "IF2 ADC2 Mux" }, 3469 { "IF2 ADC2 Swap Mux", "R/L", "IF2 ADC2 Mux" }, 3470 { "IF2 ADC2 Swap Mux", "L/L", "IF2 ADC2 Mux" }, 3471 { "IF2 ADC2 Swap Mux", "R/R", "IF2 ADC2 Mux" }, 3472 3473 { "IF2 ADC3 Swap Mux", "L/R", "IF2 ADC3 Mux" }, 3474 { "IF2 ADC3 Swap Mux", "R/L", "IF2 ADC3 Mux" }, 3475 { "IF2 ADC3 Swap Mux", "L/L", "IF2 ADC3 Mux" }, 3476 { "IF2 ADC3 Swap Mux", "R/R", "IF2 ADC3 Mux" }, 3477 3478 { "IF2 ADC4 Swap Mux", "L/R", "IF2 ADC4 Mux" }, 3479 { "IF2 ADC4 Swap Mux", "R/L", "IF2 ADC4 Mux" }, 3480 { "IF2 ADC4 Swap Mux", "L/L", "IF2 ADC4 Mux" }, 3481 { "IF2 ADC4 Swap Mux", "R/R", "IF2 ADC4 Mux" }, 3482 3483 { "IF2 ADC", NULL, "IF2 ADC1 Swap Mux" }, 3484 { "IF2 ADC", NULL, "IF2 ADC2 Swap Mux" }, 3485 { "IF2 ADC", NULL, "IF2 ADC3 Swap Mux" }, 3486 { "IF2 ADC", NULL, "IF2 ADC4 Swap Mux" }, 3487 3488 { "IF2 ADC TDM Swap Mux", "1/2/3/4", "IF2 ADC" }, 3489 { "IF2 ADC TDM Swap Mux", "2/1/3/4", "IF2 ADC" }, 3490 { "IF2 ADC TDM Swap Mux", "3/1/2/4", "IF2 ADC" }, 3491 { "IF2 ADC TDM Swap Mux", "4/1/2/3", "IF2 ADC" }, 3492 { "IF2 ADC TDM Swap Mux", "1/3/2/4", "IF2 ADC" }, 3493 { "IF2 ADC TDM Swap Mux", "1/4/2/3", "IF2 ADC" }, 3494 { "IF2 ADC TDM Swap Mux", "2/3/1/4", "IF2 ADC" }, 3495 { "IF2 ADC TDM Swap Mux", "3/4/1/2", "IF2 ADC" }, 3496 3497 { "AIF2TX", NULL, "I2S2" }, 3498 { "AIF2TX", NULL, "IF2 ADC TDM Swap Mux" }, 3499 3500 { "IF3 ADC Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" }, 3501 { "IF3 ADC Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" }, 3502 { "IF3 ADC Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" }, 3503 { "IF3 ADC Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" }, 3504 { "IF3 ADC Mux", "MONO ADC MIX", "Mono ADC MIX" }, 3505 { "IF3 ADC Mux", "OB01", "OB01 Bypass Mux" }, 3506 { "IF3 ADC Mux", "OB23", "OB23 Bypass Mux" }, 3507 { "IF3 ADC Mux", "VAD ADC", "VAD ADC Mux" }, 3508 3509 { "AIF3TX", NULL, "I2S3" }, 3510 { "AIF3TX", NULL, "IF3 ADC Mux" }, 3511 3512 { "IF4 ADC Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" }, 3513 { "IF4 ADC Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" }, 3514 { "IF4 ADC Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" }, 3515 { "IF4 ADC Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" }, 3516 { "IF4 ADC Mux", "MONO ADC MIX", "Mono ADC MIX" }, 3517 { "IF4 ADC Mux", "OB01", "OB01 Bypass Mux" }, 3518 { "IF4 ADC Mux", "OB23", "OB23 Bypass Mux" }, 3519 { "IF4 ADC Mux", "VAD ADC", "VAD ADC Mux" }, 3520 3521 { "AIF4TX", NULL, "I2S4" }, 3522 { "AIF4TX", NULL, "IF4 ADC Mux" }, 3523 3524 { "SLB ADC1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" }, 3525 { "SLB ADC1 Mux", "OB01", "OB01 Bypass Mux" }, 3526 { "SLB ADC1 Mux", "VAD ADC", "VAD ADC Mux" }, 3527 3528 { "SLB ADC2 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" }, 3529 { "SLB ADC2 Mux", "OB23", "OB23 Bypass Mux" }, 3530 3531 { "SLB ADC3 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" }, 3532 { "SLB ADC3 Mux", "MONO ADC MIX", "Mono ADC MIX" }, 3533 { "SLB ADC3 Mux", "OB45", "OB45" }, 3534 3535 { "SLB ADC4 Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" }, 3536 { "SLB ADC4 Mux", "OB67", "OB67" }, 3537 { "SLB ADC4 Mux", "OB01", "OB01 Bypass Mux" }, 3538 3539 { "SLBTX", NULL, "SLB" }, 3540 { "SLBTX", NULL, "SLB ADC1 Mux" }, 3541 { "SLBTX", NULL, "SLB ADC2 Mux" }, 3542 { "SLBTX", NULL, "SLB ADC3 Mux" }, 3543 { "SLBTX", NULL, "SLB ADC4 Mux" }, 3544 3545 { "IB01 Mux", "IF1 DAC 01", "IF1 DAC01" }, 3546 { "IB01 Mux", "IF2 DAC 01", "IF2 DAC01" }, 3547 { "IB01 Mux", "SLB DAC 01", "SLB DAC01" }, 3548 { "IB01 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" }, 3549 { "IB01 Mux", "VAD ADC/DAC1 FS", "DAC1 FS" }, 3550 3551 { "IB01 Bypass Mux", "Bypass", "IB01 Mux" }, 3552 { "IB01 Bypass Mux", "Pass SRC", "IB01 Mux" }, 3553 3554 { "IB23 Mux", "IF1 DAC 23", "IF1 DAC23" }, 3555 { "IB23 Mux", "IF2 DAC 23", "IF2 DAC23" }, 3556 { "IB23 Mux", "SLB DAC 23", "SLB DAC23" }, 3557 { "IB23 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" }, 3558 { "IB23 Mux", "DAC1 FS", "DAC1 FS" }, 3559 { "IB23 Mux", "IF4 DAC", "IF4 DAC" }, 3560 3561 { "IB23 Bypass Mux", "Bypass", "IB23 Mux" }, 3562 { "IB23 Bypass Mux", "Pass SRC", "IB23 Mux" }, 3563 3564 { "IB45 Mux", "IF1 DAC 45", "IF1 DAC45" }, 3565 { "IB45 Mux", "IF2 DAC 45", "IF2 DAC45" }, 3566 { "IB45 Mux", "SLB DAC 45", "SLB DAC45" }, 3567 { "IB45 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" }, 3568 { "IB45 Mux", "IF3 DAC", "IF3 DAC" }, 3569 3570 { "IB45 Bypass Mux", "Bypass", "IB45 Mux" }, 3571 { "IB45 Bypass Mux", "Pass SRC", "IB45 Mux" }, 3572 3573 { "IB6 Mux", "IF1 DAC 6", "IF1 DAC6 Mux" }, 3574 { "IB6 Mux", "IF2 DAC 6", "IF2 DAC6 Mux" }, 3575 { "IB6 Mux", "SLB DAC 6", "SLB DAC6" }, 3576 { "IB6 Mux", "STO4 ADC MIX L", "Stereo4 ADC MIXL" }, 3577 { "IB6 Mux", "IF4 DAC L", "IF4 DAC L" }, 3578 { "IB6 Mux", "STO1 ADC MIX L", "Stereo1 ADC MIXL" }, 3579 { "IB6 Mux", "STO2 ADC MIX L", "Stereo2 ADC MIXL" }, 3580 { "IB6 Mux", "STO3 ADC MIX L", "Stereo3 ADC MIXL" }, 3581 3582 { "IB7 Mux", "IF1 DAC 7", "IF1 DAC7 Mux" }, 3583 { "IB7 Mux", "IF2 DAC 7", "IF2 DAC7 Mux" }, 3584 { "IB7 Mux", "SLB DAC 7", "SLB DAC7" }, 3585 { "IB7 Mux", "STO4 ADC MIX R", "Stereo4 ADC MIXR" }, 3586 { "IB7 Mux", "IF4 DAC R", "IF4 DAC R" }, 3587 { "IB7 Mux", "STO1 ADC MIX R", "Stereo1 ADC MIXR" }, 3588 { "IB7 Mux", "STO2 ADC MIX R", "Stereo2 ADC MIXR" }, 3589 { "IB7 Mux", "STO3 ADC MIX R", "Stereo3 ADC MIXR" }, 3590 3591 { "IB8 Mux", "STO1 ADC MIX L", "Stereo1 ADC MIXL" }, 3592 { "IB8 Mux", "STO2 ADC MIX L", "Stereo2 ADC MIXL" }, 3593 { "IB8 Mux", "STO3 ADC MIX L", "Stereo3 ADC MIXL" }, 3594 { "IB8 Mux", "STO4 ADC MIX L", "Stereo4 ADC MIXL" }, 3595 { "IB8 Mux", "MONO ADC MIX L", "Mono ADC MIXL" }, 3596 { "IB8 Mux", "DACL1 FS", "DAC1 MIXL" }, 3597 3598 { "IB9 Mux", "STO1 ADC MIX R", "Stereo1 ADC MIXR" }, 3599 { "IB9 Mux", "STO2 ADC MIX R", "Stereo2 ADC MIXR" }, 3600 { "IB9 Mux", "STO3 ADC MIX R", "Stereo3 ADC MIXR" }, 3601 { "IB9 Mux", "STO4 ADC MIX R", "Stereo4 ADC MIXR" }, 3602 { "IB9 Mux", "MONO ADC MIX R", "Mono ADC MIXR" }, 3603 { "IB9 Mux", "DACR1 FS", "DAC1 MIXR" }, 3604 { "IB9 Mux", "DAC1 FS", "DAC1 FS" }, 3605 3606 { "OB01 MIX", "IB01 Switch", "IB01 Bypass Mux" }, 3607 { "OB01 MIX", "IB23 Switch", "IB23 Bypass Mux" }, 3608 { "OB01 MIX", "IB45 Switch", "IB45 Bypass Mux" }, 3609 { "OB01 MIX", "IB6 Switch", "IB6 Mux" }, 3610 { "OB01 MIX", "IB7 Switch", "IB7 Mux" }, 3611 { "OB01 MIX", "IB8 Switch", "IB8 Mux" }, 3612 { "OB01 MIX", "IB9 Switch", "IB9 Mux" }, 3613 3614 { "OB23 MIX", "IB01 Switch", "IB01 Bypass Mux" }, 3615 { "OB23 MIX", "IB23 Switch", "IB23 Bypass Mux" }, 3616 { "OB23 MIX", "IB45 Switch", "IB45 Bypass Mux" }, 3617 { "OB23 MIX", "IB6 Switch", "IB6 Mux" }, 3618 { "OB23 MIX", "IB7 Switch", "IB7 Mux" }, 3619 { "OB23 MIX", "IB8 Switch", "IB8 Mux" }, 3620 { "OB23 MIX", "IB9 Switch", "IB9 Mux" }, 3621 3622 { "OB4 MIX", "IB01 Switch", "IB01 Bypass Mux" }, 3623 { "OB4 MIX", "IB23 Switch", "IB23 Bypass Mux" }, 3624 { "OB4 MIX", "IB45 Switch", "IB45 Bypass Mux" }, 3625 { "OB4 MIX", "IB6 Switch", "IB6 Mux" }, 3626 { "OB4 MIX", "IB7 Switch", "IB7 Mux" }, 3627 { "OB4 MIX", "IB8 Switch", "IB8 Mux" }, 3628 { "OB4 MIX", "IB9 Switch", "IB9 Mux" }, 3629 3630 { "OB5 MIX", "IB01 Switch", "IB01 Bypass Mux" }, 3631 { "OB5 MIX", "IB23 Switch", "IB23 Bypass Mux" }, 3632 { "OB5 MIX", "IB45 Switch", "IB45 Bypass Mux" }, 3633 { "OB5 MIX", "IB6 Switch", "IB6 Mux" }, 3634 { "OB5 MIX", "IB7 Switch", "IB7 Mux" }, 3635 { "OB5 MIX", "IB8 Switch", "IB8 Mux" }, 3636 { "OB5 MIX", "IB9 Switch", "IB9 Mux" }, 3637 3638 { "OB6 MIX", "IB01 Switch", "IB01 Bypass Mux" }, 3639 { "OB6 MIX", "IB23 Switch", "IB23 Bypass Mux" }, 3640 { "OB6 MIX", "IB45 Switch", "IB45 Bypass Mux" }, 3641 { "OB6 MIX", "IB6 Switch", "IB6 Mux" }, 3642 { "OB6 MIX", "IB7 Switch", "IB7 Mux" }, 3643 { "OB6 MIX", "IB8 Switch", "IB8 Mux" }, 3644 { "OB6 MIX", "IB9 Switch", "IB9 Mux" }, 3645 3646 { "OB7 MIX", "IB01 Switch", "IB01 Bypass Mux" }, 3647 { "OB7 MIX", "IB23 Switch", "IB23 Bypass Mux" }, 3648 { "OB7 MIX", "IB45 Switch", "IB45 Bypass Mux" }, 3649 { "OB7 MIX", "IB6 Switch", "IB6 Mux" }, 3650 { "OB7 MIX", "IB7 Switch", "IB7 Mux" }, 3651 { "OB7 MIX", "IB8 Switch", "IB8 Mux" }, 3652 { "OB7 MIX", "IB9 Switch", "IB9 Mux" }, 3653 3654 { "OB01 Bypass Mux", "Bypass", "OB01 MIX" }, 3655 { "OB01 Bypass Mux", "Pass SRC", "OB01 MIX" }, 3656 { "OB23 Bypass Mux", "Bypass", "OB23 MIX" }, 3657 { "OB23 Bypass Mux", "Pass SRC", "OB23 MIX" }, 3658 3659 { "OutBound2", NULL, "OB23 Bypass Mux" }, 3660 { "OutBound3", NULL, "OB23 Bypass Mux" }, 3661 { "OutBound4", NULL, "OB4 MIX" }, 3662 { "OutBound5", NULL, "OB5 MIX" }, 3663 { "OutBound6", NULL, "OB6 MIX" }, 3664 { "OutBound7", NULL, "OB7 MIX" }, 3665 3666 { "OB45", NULL, "OutBound4" }, 3667 { "OB45", NULL, "OutBound5" }, 3668 { "OB67", NULL, "OutBound6" }, 3669 { "OB67", NULL, "OutBound7" }, 3670 3671 { "IF1 DAC0", NULL, "AIF1RX" }, 3672 { "IF1 DAC1", NULL, "AIF1RX" }, 3673 { "IF1 DAC2", NULL, "AIF1RX" }, 3674 { "IF1 DAC3", NULL, "AIF1RX" }, 3675 { "IF1 DAC4", NULL, "AIF1RX" }, 3676 { "IF1 DAC5", NULL, "AIF1RX" }, 3677 { "IF1 DAC6", NULL, "AIF1RX" }, 3678 { "IF1 DAC7", NULL, "AIF1RX" }, 3679 { "IF1 DAC0", NULL, "I2S1" }, 3680 { "IF1 DAC1", NULL, "I2S1" }, 3681 { "IF1 DAC2", NULL, "I2S1" }, 3682 { "IF1 DAC3", NULL, "I2S1" }, 3683 { "IF1 DAC4", NULL, "I2S1" }, 3684 { "IF1 DAC5", NULL, "I2S1" }, 3685 { "IF1 DAC6", NULL, "I2S1" }, 3686 { "IF1 DAC7", NULL, "I2S1" }, 3687 3688 { "IF1 DAC0 Mux", "Slot0", "IF1 DAC0" }, 3689 { "IF1 DAC0 Mux", "Slot1", "IF1 DAC1" }, 3690 { "IF1 DAC0 Mux", "Slot2", "IF1 DAC2" }, 3691 { "IF1 DAC0 Mux", "Slot3", "IF1 DAC3" }, 3692 { "IF1 DAC0 Mux", "Slot4", "IF1 DAC4" }, 3693 { "IF1 DAC0 Mux", "Slot5", "IF1 DAC5" }, 3694 { "IF1 DAC0 Mux", "Slot6", "IF1 DAC6" }, 3695 { "IF1 DAC0 Mux", "Slot7", "IF1 DAC7" }, 3696 3697 { "IF1 DAC1 Mux", "Slot0", "IF1 DAC0" }, 3698 { "IF1 DAC1 Mux", "Slot1", "IF1 DAC1" }, 3699 { "IF1 DAC1 Mux", "Slot2", "IF1 DAC2" }, 3700 { "IF1 DAC1 Mux", "Slot3", "IF1 DAC3" }, 3701 { "IF1 DAC1 Mux", "Slot4", "IF1 DAC4" }, 3702 { "IF1 DAC1 Mux", "Slot5", "IF1 DAC5" }, 3703 { "IF1 DAC1 Mux", "Slot6", "IF1 DAC6" }, 3704 { "IF1 DAC1 Mux", "Slot7", "IF1 DAC7" }, 3705 3706 { "IF1 DAC2 Mux", "Slot0", "IF1 DAC0" }, 3707 { "IF1 DAC2 Mux", "Slot1", "IF1 DAC1" }, 3708 { "IF1 DAC2 Mux", "Slot2", "IF1 DAC2" }, 3709 { "IF1 DAC2 Mux", "Slot3", "IF1 DAC3" }, 3710 { "IF1 DAC2 Mux", "Slot4", "IF1 DAC4" }, 3711 { "IF1 DAC2 Mux", "Slot5", "IF1 DAC5" }, 3712 { "IF1 DAC2 Mux", "Slot6", "IF1 DAC6" }, 3713 { "IF1 DAC2 Mux", "Slot7", "IF1 DAC7" }, 3714 3715 { "IF1 DAC3 Mux", "Slot0", "IF1 DAC0" }, 3716 { "IF1 DAC3 Mux", "Slot1", "IF1 DAC1" }, 3717 { "IF1 DAC3 Mux", "Slot2", "IF1 DAC2" }, 3718 { "IF1 DAC3 Mux", "Slot3", "IF1 DAC3" }, 3719 { "IF1 DAC3 Mux", "Slot4", "IF1 DAC4" }, 3720 { "IF1 DAC3 Mux", "Slot5", "IF1 DAC5" }, 3721 { "IF1 DAC3 Mux", "Slot6", "IF1 DAC6" }, 3722 { "IF1 DAC3 Mux", "Slot7", "IF1 DAC7" }, 3723 3724 { "IF1 DAC4 Mux", "Slot0", "IF1 DAC0" }, 3725 { "IF1 DAC4 Mux", "Slot1", "IF1 DAC1" }, 3726 { "IF1 DAC4 Mux", "Slot2", "IF1 DAC2" }, 3727 { "IF1 DAC4 Mux", "Slot3", "IF1 DAC3" }, 3728 { "IF1 DAC4 Mux", "Slot4", "IF1 DAC4" }, 3729 { "IF1 DAC4 Mux", "Slot5", "IF1 DAC5" }, 3730 { "IF1 DAC4 Mux", "Slot6", "IF1 DAC6" }, 3731 { "IF1 DAC4 Mux", "Slot7", "IF1 DAC7" }, 3732 3733 { "IF1 DAC5 Mux", "Slot0", "IF1 DAC0" }, 3734 { "IF1 DAC5 Mux", "Slot1", "IF1 DAC1" }, 3735 { "IF1 DAC5 Mux", "Slot2", "IF1 DAC2" }, 3736 { "IF1 DAC5 Mux", "Slot3", "IF1 DAC3" }, 3737 { "IF1 DAC5 Mux", "Slot4", "IF1 DAC4" }, 3738 { "IF1 DAC5 Mux", "Slot5", "IF1 DAC5" }, 3739 { "IF1 DAC5 Mux", "Slot6", "IF1 DAC6" }, 3740 { "IF1 DAC5 Mux", "Slot7", "IF1 DAC7" }, 3741 3742 { "IF1 DAC6 Mux", "Slot0", "IF1 DAC0" }, 3743 { "IF1 DAC6 Mux", "Slot1", "IF1 DAC1" }, 3744 { "IF1 DAC6 Mux", "Slot2", "IF1 DAC2" }, 3745 { "IF1 DAC6 Mux", "Slot3", "IF1 DAC3" }, 3746 { "IF1 DAC6 Mux", "Slot4", "IF1 DAC4" }, 3747 { "IF1 DAC6 Mux", "Slot5", "IF1 DAC5" }, 3748 { "IF1 DAC6 Mux", "Slot6", "IF1 DAC6" }, 3749 { "IF1 DAC6 Mux", "Slot7", "IF1 DAC7" }, 3750 3751 { "IF1 DAC7 Mux", "Slot0", "IF1 DAC0" }, 3752 { "IF1 DAC7 Mux", "Slot1", "IF1 DAC1" }, 3753 { "IF1 DAC7 Mux", "Slot2", "IF1 DAC2" }, 3754 { "IF1 DAC7 Mux", "Slot3", "IF1 DAC3" }, 3755 { "IF1 DAC7 Mux", "Slot4", "IF1 DAC4" }, 3756 { "IF1 DAC7 Mux", "Slot5", "IF1 DAC5" }, 3757 { "IF1 DAC7 Mux", "Slot6", "IF1 DAC6" }, 3758 { "IF1 DAC7 Mux", "Slot7", "IF1 DAC7" }, 3759 3760 { "IF1 DAC01", NULL, "IF1 DAC0 Mux" }, 3761 { "IF1 DAC01", NULL, "IF1 DAC1 Mux" }, 3762 { "IF1 DAC23", NULL, "IF1 DAC2 Mux" }, 3763 { "IF1 DAC23", NULL, "IF1 DAC3 Mux" }, 3764 { "IF1 DAC45", NULL, "IF1 DAC4 Mux" }, 3765 { "IF1 DAC45", NULL, "IF1 DAC5 Mux" }, 3766 { "IF1 DAC67", NULL, "IF1 DAC6 Mux" }, 3767 { "IF1 DAC67", NULL, "IF1 DAC7 Mux" }, 3768 3769 { "IF2 DAC0", NULL, "AIF2RX" }, 3770 { "IF2 DAC1", NULL, "AIF2RX" }, 3771 { "IF2 DAC2", NULL, "AIF2RX" }, 3772 { "IF2 DAC3", NULL, "AIF2RX" }, 3773 { "IF2 DAC4", NULL, "AIF2RX" }, 3774 { "IF2 DAC5", NULL, "AIF2RX" }, 3775 { "IF2 DAC6", NULL, "AIF2RX" }, 3776 { "IF2 DAC7", NULL, "AIF2RX" }, 3777 { "IF2 DAC0", NULL, "I2S2" }, 3778 { "IF2 DAC1", NULL, "I2S2" }, 3779 { "IF2 DAC2", NULL, "I2S2" }, 3780 { "IF2 DAC3", NULL, "I2S2" }, 3781 { "IF2 DAC4", NULL, "I2S2" }, 3782 { "IF2 DAC5", NULL, "I2S2" }, 3783 { "IF2 DAC6", NULL, "I2S2" }, 3784 { "IF2 DAC7", NULL, "I2S2" }, 3785 3786 { "IF2 DAC0 Mux", "Slot0", "IF2 DAC0" }, 3787 { "IF2 DAC0 Mux", "Slot1", "IF2 DAC1" }, 3788 { "IF2 DAC0 Mux", "Slot2", "IF2 DAC2" }, 3789 { "IF2 DAC0 Mux", "Slot3", "IF2 DAC3" }, 3790 { "IF2 DAC0 Mux", "Slot4", "IF2 DAC4" }, 3791 { "IF2 DAC0 Mux", "Slot5", "IF2 DAC5" }, 3792 { "IF2 DAC0 Mux", "Slot6", "IF2 DAC6" }, 3793 { "IF2 DAC0 Mux", "Slot7", "IF2 DAC7" }, 3794 3795 { "IF2 DAC1 Mux", "Slot0", "IF2 DAC0" }, 3796 { "IF2 DAC1 Mux", "Slot1", "IF2 DAC1" }, 3797 { "IF2 DAC1 Mux", "Slot2", "IF2 DAC2" }, 3798 { "IF2 DAC1 Mux", "Slot3", "IF2 DAC3" }, 3799 { "IF2 DAC1 Mux", "Slot4", "IF2 DAC4" }, 3800 { "IF2 DAC1 Mux", "Slot5", "IF2 DAC5" }, 3801 { "IF2 DAC1 Mux", "Slot6", "IF2 DAC6" }, 3802 { "IF2 DAC1 Mux", "Slot7", "IF2 DAC7" }, 3803 3804 { "IF2 DAC2 Mux", "Slot0", "IF2 DAC0" }, 3805 { "IF2 DAC2 Mux", "Slot1", "IF2 DAC1" }, 3806 { "IF2 DAC2 Mux", "Slot2", "IF2 DAC2" }, 3807 { "IF2 DAC2 Mux", "Slot3", "IF2 DAC3" }, 3808 { "IF2 DAC2 Mux", "Slot4", "IF2 DAC4" }, 3809 { "IF2 DAC2 Mux", "Slot5", "IF2 DAC5" }, 3810 { "IF2 DAC2 Mux", "Slot6", "IF2 DAC6" }, 3811 { "IF2 DAC2 Mux", "Slot7", "IF2 DAC7" }, 3812 3813 { "IF2 DAC3 Mux", "Slot0", "IF2 DAC0" }, 3814 { "IF2 DAC3 Mux", "Slot1", "IF2 DAC1" }, 3815 { "IF2 DAC3 Mux", "Slot2", "IF2 DAC2" }, 3816 { "IF2 DAC3 Mux", "Slot3", "IF2 DAC3" }, 3817 { "IF2 DAC3 Mux", "Slot4", "IF2 DAC4" }, 3818 { "IF2 DAC3 Mux", "Slot5", "IF2 DAC5" }, 3819 { "IF2 DAC3 Mux", "Slot6", "IF2 DAC6" }, 3820 { "IF2 DAC3 Mux", "Slot7", "IF2 DAC7" }, 3821 3822 { "IF2 DAC4 Mux", "Slot0", "IF2 DAC0" }, 3823 { "IF2 DAC4 Mux", "Slot1", "IF2 DAC1" }, 3824 { "IF2 DAC4 Mux", "Slot2", "IF2 DAC2" }, 3825 { "IF2 DAC4 Mux", "Slot3", "IF2 DAC3" }, 3826 { "IF2 DAC4 Mux", "Slot4", "IF2 DAC4" }, 3827 { "IF2 DAC4 Mux", "Slot5", "IF2 DAC5" }, 3828 { "IF2 DAC4 Mux", "Slot6", "IF2 DAC6" }, 3829 { "IF2 DAC4 Mux", "Slot7", "IF2 DAC7" }, 3830 3831 { "IF2 DAC5 Mux", "Slot0", "IF2 DAC0" }, 3832 { "IF2 DAC5 Mux", "Slot1", "IF2 DAC1" }, 3833 { "IF2 DAC5 Mux", "Slot2", "IF2 DAC2" }, 3834 { "IF2 DAC5 Mux", "Slot3", "IF2 DAC3" }, 3835 { "IF2 DAC5 Mux", "Slot4", "IF2 DAC4" }, 3836 { "IF2 DAC5 Mux", "Slot5", "IF2 DAC5" }, 3837 { "IF2 DAC5 Mux", "Slot6", "IF2 DAC6" }, 3838 { "IF2 DAC5 Mux", "Slot7", "IF2 DAC7" }, 3839 3840 { "IF2 DAC6 Mux", "Slot0", "IF2 DAC0" }, 3841 { "IF2 DAC6 Mux", "Slot1", "IF2 DAC1" }, 3842 { "IF2 DAC6 Mux", "Slot2", "IF2 DAC2" }, 3843 { "IF2 DAC6 Mux", "Slot3", "IF2 DAC3" }, 3844 { "IF2 DAC6 Mux", "Slot4", "IF2 DAC4" }, 3845 { "IF2 DAC6 Mux", "Slot5", "IF2 DAC5" }, 3846 { "IF2 DAC6 Mux", "Slot6", "IF2 DAC6" }, 3847 { "IF2 DAC6 Mux", "Slot7", "IF2 DAC7" }, 3848 3849 { "IF2 DAC7 Mux", "Slot0", "IF2 DAC0" }, 3850 { "IF2 DAC7 Mux", "Slot1", "IF2 DAC1" }, 3851 { "IF2 DAC7 Mux", "Slot2", "IF2 DAC2" }, 3852 { "IF2 DAC7 Mux", "Slot3", "IF2 DAC3" }, 3853 { "IF2 DAC7 Mux", "Slot4", "IF2 DAC4" }, 3854 { "IF2 DAC7 Mux", "Slot5", "IF2 DAC5" }, 3855 { "IF2 DAC7 Mux", "Slot6", "IF2 DAC6" }, 3856 { "IF2 DAC7 Mux", "Slot7", "IF2 DAC7" }, 3857 3858 { "IF2 DAC01", NULL, "IF2 DAC0 Mux" }, 3859 { "IF2 DAC01", NULL, "IF2 DAC1 Mux" }, 3860 { "IF2 DAC23", NULL, "IF2 DAC2 Mux" }, 3861 { "IF2 DAC23", NULL, "IF2 DAC3 Mux" }, 3862 { "IF2 DAC45", NULL, "IF2 DAC4 Mux" }, 3863 { "IF2 DAC45", NULL, "IF2 DAC5 Mux" }, 3864 { "IF2 DAC67", NULL, "IF2 DAC6 Mux" }, 3865 { "IF2 DAC67", NULL, "IF2 DAC7 Mux" }, 3866 3867 { "IF3 DAC", NULL, "AIF3RX" }, 3868 { "IF3 DAC", NULL, "I2S3" }, 3869 3870 { "IF4 DAC", NULL, "AIF4RX" }, 3871 { "IF4 DAC", NULL, "I2S4" }, 3872 3873 { "IF3 DAC L", NULL, "IF3 DAC" }, 3874 { "IF3 DAC R", NULL, "IF3 DAC" }, 3875 3876 { "IF4 DAC L", NULL, "IF4 DAC" }, 3877 { "IF4 DAC R", NULL, "IF4 DAC" }, 3878 3879 { "SLB DAC0", NULL, "SLBRX" }, 3880 { "SLB DAC1", NULL, "SLBRX" }, 3881 { "SLB DAC2", NULL, "SLBRX" }, 3882 { "SLB DAC3", NULL, "SLBRX" }, 3883 { "SLB DAC4", NULL, "SLBRX" }, 3884 { "SLB DAC5", NULL, "SLBRX" }, 3885 { "SLB DAC6", NULL, "SLBRX" }, 3886 { "SLB DAC7", NULL, "SLBRX" }, 3887 { "SLB DAC0", NULL, "SLB" }, 3888 { "SLB DAC1", NULL, "SLB" }, 3889 { "SLB DAC2", NULL, "SLB" }, 3890 { "SLB DAC3", NULL, "SLB" }, 3891 { "SLB DAC4", NULL, "SLB" }, 3892 { "SLB DAC5", NULL, "SLB" }, 3893 { "SLB DAC6", NULL, "SLB" }, 3894 { "SLB DAC7", NULL, "SLB" }, 3895 3896 { "SLB DAC01", NULL, "SLB DAC0" }, 3897 { "SLB DAC01", NULL, "SLB DAC1" }, 3898 { "SLB DAC23", NULL, "SLB DAC2" }, 3899 { "SLB DAC23", NULL, "SLB DAC3" }, 3900 { "SLB DAC45", NULL, "SLB DAC4" }, 3901 { "SLB DAC45", NULL, "SLB DAC5" }, 3902 { "SLB DAC67", NULL, "SLB DAC6" }, 3903 { "SLB DAC67", NULL, "SLB DAC7" }, 3904 3905 { "ADDA1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" }, 3906 { "ADDA1 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" }, 3907 { "ADDA1 Mux", "OB 67", "OB67" }, 3908 3909 { "DAC1 Mux", "IF1 DAC 01", "IF1 DAC01" }, 3910 { "DAC1 Mux", "IF2 DAC 01", "IF2 DAC01" }, 3911 { "DAC1 Mux", "IF3 DAC LR", "IF3 DAC" }, 3912 { "DAC1 Mux", "IF4 DAC LR", "IF4 DAC" }, 3913 { "DAC1 Mux", "SLB DAC 01", "SLB DAC01" }, 3914 { "DAC1 Mux", "OB 01", "OB01 Bypass Mux" }, 3915 3916 { "DAC1 MIXL", "Stereo ADC Switch", "ADDA1 Mux" }, 3917 { "DAC1 MIXL", "DAC1 Switch", "DAC1 Mux" }, 3918 { "DAC1 MIXR", "Stereo ADC Switch", "ADDA1 Mux" }, 3919 { "DAC1 MIXR", "DAC1 Switch", "DAC1 Mux" }, 3920 3921 { "DAC1 FS", NULL, "DAC1 MIXL" }, 3922 { "DAC1 FS", NULL, "DAC1 MIXR" }, 3923 3924 { "DAC2 L Mux", "IF1 DAC 2", "IF1 DAC2 Mux" }, 3925 { "DAC2 L Mux", "IF2 DAC 2", "IF2 DAC2 Mux" }, 3926 { "DAC2 L Mux", "IF3 DAC L", "IF3 DAC L" }, 3927 { "DAC2 L Mux", "IF4 DAC L", "IF4 DAC L" }, 3928 { "DAC2 L Mux", "SLB DAC 2", "SLB DAC2" }, 3929 { "DAC2 L Mux", "OB 2", "OutBound2" }, 3930 3931 { "DAC2 R Mux", "IF1 DAC 3", "IF1 DAC3 Mux" }, 3932 { "DAC2 R Mux", "IF2 DAC 3", "IF2 DAC3 Mux" }, 3933 { "DAC2 R Mux", "IF3 DAC R", "IF3 DAC R" }, 3934 { "DAC2 R Mux", "IF4 DAC R", "IF4 DAC R" }, 3935 { "DAC2 R Mux", "SLB DAC 3", "SLB DAC3" }, 3936 { "DAC2 R Mux", "OB 3", "OutBound3" }, 3937 { "DAC2 R Mux", "Haptic Generator", "Haptic Generator" }, 3938 { "DAC2 R Mux", "VAD ADC", "VAD ADC Mux" }, 3939 3940 { "DAC3 L Mux", "IF1 DAC 4", "IF1 DAC4 Mux" }, 3941 { "DAC3 L Mux", "IF2 DAC 4", "IF2 DAC4 Mux" }, 3942 { "DAC3 L Mux", "IF3 DAC L", "IF3 DAC L" }, 3943 { "DAC3 L Mux", "IF4 DAC L", "IF4 DAC L" }, 3944 { "DAC3 L Mux", "SLB DAC 4", "SLB DAC4" }, 3945 { "DAC3 L Mux", "OB 4", "OutBound4" }, 3946 3947 { "DAC3 R Mux", "IF1 DAC 5", "IF1 DAC5 Mux" }, 3948 { "DAC3 R Mux", "IF2 DAC 5", "IF2 DAC5 Mux" }, 3949 { "DAC3 R Mux", "IF3 DAC R", "IF3 DAC R" }, 3950 { "DAC3 R Mux", "IF4 DAC R", "IF4 DAC R" }, 3951 { "DAC3 R Mux", "SLB DAC 5", "SLB DAC5" }, 3952 { "DAC3 R Mux", "OB 5", "OutBound5" }, 3953 3954 { "DAC4 L Mux", "IF1 DAC 6", "IF1 DAC6 Mux" }, 3955 { "DAC4 L Mux", "IF2 DAC 6", "IF2 DAC6 Mux" }, 3956 { "DAC4 L Mux", "IF3 DAC L", "IF3 DAC L" }, 3957 { "DAC4 L Mux", "IF4 DAC L", "IF4 DAC L" }, 3958 { "DAC4 L Mux", "SLB DAC 6", "SLB DAC6" }, 3959 { "DAC4 L Mux", "OB 6", "OutBound6" }, 3960 3961 { "DAC4 R Mux", "IF1 DAC 7", "IF1 DAC7 Mux" }, 3962 { "DAC4 R Mux", "IF2 DAC 7", "IF2 DAC7 Mux" }, 3963 { "DAC4 R Mux", "IF3 DAC R", "IF3 DAC R" }, 3964 { "DAC4 R Mux", "IF4 DAC R", "IF4 DAC R" }, 3965 { "DAC4 R Mux", "SLB DAC 7", "SLB DAC7" }, 3966 { "DAC4 R Mux", "OB 7", "OutBound7" }, 3967 3968 { "Sidetone Mux", "DMIC1 L", "DMIC L1" }, 3969 { "Sidetone Mux", "DMIC2 L", "DMIC L2" }, 3970 { "Sidetone Mux", "DMIC3 L", "DMIC L3" }, 3971 { "Sidetone Mux", "DMIC4 L", "DMIC L4" }, 3972 { "Sidetone Mux", "ADC1", "ADC 1" }, 3973 { "Sidetone Mux", "ADC2", "ADC 2" }, 3974 { "Sidetone Mux", NULL, "Sidetone Power" }, 3975 3976 { "Stereo DAC MIXL", "ST L Switch", "Sidetone Mux" }, 3977 { "Stereo DAC MIXL", "DAC1 L Switch", "DAC1 MIXL" }, 3978 { "Stereo DAC MIXL", "DAC2 L Switch", "DAC2 L Mux" }, 3979 { "Stereo DAC MIXL", "DAC1 R Switch", "DAC1 MIXR" }, 3980 { "Stereo DAC MIXL", NULL, "dac stereo1 filter" }, 3981 { "Stereo DAC MIXR", "ST R Switch", "Sidetone Mux" }, 3982 { "Stereo DAC MIXR", "DAC1 R Switch", "DAC1 MIXR" }, 3983 { "Stereo DAC MIXR", "DAC2 R Switch", "DAC2 R Mux" }, 3984 { "Stereo DAC MIXR", "DAC1 L Switch", "DAC1 MIXL" }, 3985 { "Stereo DAC MIXR", NULL, "dac stereo1 filter" }, 3986 { "dac stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll }, 3987 3988 { "Mono DAC MIXL", "ST L Switch", "Sidetone Mux" }, 3989 { "Mono DAC MIXL", "DAC1 L Switch", "DAC1 MIXL" }, 3990 { "Mono DAC MIXL", "DAC2 L Switch", "DAC2 L Mux" }, 3991 { "Mono DAC MIXL", "DAC2 R Switch", "DAC2 R Mux" }, 3992 { "Mono DAC MIXL", NULL, "dac mono2 left filter" }, 3993 { "dac mono2 left filter", NULL, "PLL1", is_sys_clk_from_pll }, 3994 { "Mono DAC MIXR", "ST R Switch", "Sidetone Mux" }, 3995 { "Mono DAC MIXR", "DAC1 R Switch", "DAC1 MIXR" }, 3996 { "Mono DAC MIXR", "DAC2 R Switch", "DAC2 R Mux" }, 3997 { "Mono DAC MIXR", "DAC2 L Switch", "DAC2 L Mux" }, 3998 { "Mono DAC MIXR", NULL, "dac mono2 right filter" }, 3999 { "dac mono2 right filter", NULL, "PLL1", is_sys_clk_from_pll }, 4000 4001 { "DD1 MIXL", "Sto DAC Mix L Switch", "Stereo DAC MIXL" }, 4002 { "DD1 MIXL", "Mono DAC Mix L Switch", "Mono DAC MIXL" }, 4003 { "DD1 MIXL", "DAC3 L Switch", "DAC3 L Mux" }, 4004 { "DD1 MIXL", "DAC3 R Switch", "DAC3 R Mux" }, 4005 { "DD1 MIXL", NULL, "dac mono3 left filter" }, 4006 { "dac mono3 left filter", NULL, "PLL1", is_sys_clk_from_pll }, 4007 { "DD1 MIXR", "Sto DAC Mix R Switch", "Stereo DAC MIXR" }, 4008 { "DD1 MIXR", "Mono DAC Mix R Switch", "Mono DAC MIXR" }, 4009 { "DD1 MIXR", "DAC3 L Switch", "DAC3 L Mux" }, 4010 { "DD1 MIXR", "DAC3 R Switch", "DAC3 R Mux" }, 4011 { "DD1 MIXR", NULL, "dac mono3 right filter" }, 4012 { "dac mono3 right filter", NULL, "PLL1", is_sys_clk_from_pll }, 4013 4014 { "DD2 MIXL", "Sto DAC Mix L Switch", "Stereo DAC MIXL" }, 4015 { "DD2 MIXL", "Mono DAC Mix L Switch", "Mono DAC MIXL" }, 4016 { "DD2 MIXL", "DAC4 L Switch", "DAC4 L Mux" }, 4017 { "DD2 MIXL", "DAC4 R Switch", "DAC4 R Mux" }, 4018 { "DD2 MIXL", NULL, "dac mono4 left filter" }, 4019 { "dac mono4 left filter", NULL, "PLL1", is_sys_clk_from_pll }, 4020 { "DD2 MIXR", "Sto DAC Mix R Switch", "Stereo DAC MIXR" }, 4021 { "DD2 MIXR", "Mono DAC Mix R Switch", "Mono DAC MIXR" }, 4022 { "DD2 MIXR", "DAC4 L Switch", "DAC4 L Mux" }, 4023 { "DD2 MIXR", "DAC4 R Switch", "DAC4 R Mux" }, 4024 { "DD2 MIXR", NULL, "dac mono4 right filter" }, 4025 { "dac mono4 right filter", NULL, "PLL1", is_sys_clk_from_pll }, 4026 4027 { "Stereo DAC MIX", NULL, "Stereo DAC MIXL" }, 4028 { "Stereo DAC MIX", NULL, "Stereo DAC MIXR" }, 4029 { "Mono DAC MIX", NULL, "Mono DAC MIXL" }, 4030 { "Mono DAC MIX", NULL, "Mono DAC MIXR" }, 4031 { "DD1 MIX", NULL, "DD1 MIXL" }, 4032 { "DD1 MIX", NULL, "DD1 MIXR" }, 4033 { "DD2 MIX", NULL, "DD2 MIXL" }, 4034 { "DD2 MIX", NULL, "DD2 MIXR" }, 4035 4036 { "DAC12 SRC Mux", "STO1 DAC MIX", "Stereo DAC MIX" }, 4037 { "DAC12 SRC Mux", "MONO DAC MIX", "Mono DAC MIX" }, 4038 { "DAC12 SRC Mux", "DD MIX1", "DD1 MIX" }, 4039 { "DAC12 SRC Mux", "DD MIX2", "DD2 MIX" }, 4040 4041 { "DAC3 SRC Mux", "MONO DAC MIXL", "Mono DAC MIXL" }, 4042 { "DAC3 SRC Mux", "MONO DAC MIXR", "Mono DAC MIXR" }, 4043 { "DAC3 SRC Mux", "DD MIX1L", "DD1 MIXL" }, 4044 { "DAC3 SRC Mux", "DD MIX2L", "DD2 MIXL" }, 4045 4046 { "DAC 1", NULL, "DAC12 SRC Mux" }, 4047 { "DAC 2", NULL, "DAC12 SRC Mux" }, 4048 { "DAC 3", NULL, "DAC3 SRC Mux" }, 4049 4050 { "PDM1 L Mux", "STO1 DAC MIX", "Stereo DAC MIXL" }, 4051 { "PDM1 L Mux", "MONO DAC MIX", "Mono DAC MIXL" }, 4052 { "PDM1 L Mux", "DD MIX1", "DD1 MIXL" }, 4053 { "PDM1 L Mux", "DD MIX2", "DD2 MIXL" }, 4054 { "PDM1 L Mux", NULL, "PDM1 Power" }, 4055 { "PDM1 R Mux", "STO1 DAC MIX", "Stereo DAC MIXR" }, 4056 { "PDM1 R Mux", "MONO DAC MIX", "Mono DAC MIXR" }, 4057 { "PDM1 R Mux", "DD MIX1", "DD1 MIXR" }, 4058 { "PDM1 R Mux", "DD MIX2", "DD2 MIXR" }, 4059 { "PDM1 R Mux", NULL, "PDM1 Power" }, 4060 { "PDM2 L Mux", "STO1 DAC MIX", "Stereo DAC MIXL" }, 4061 { "PDM2 L Mux", "MONO DAC MIX", "Mono DAC MIXL" }, 4062 { "PDM2 L Mux", "DD MIX1", "DD1 MIXL" }, 4063 { "PDM2 L Mux", "DD MIX2", "DD2 MIXL" }, 4064 { "PDM2 L Mux", NULL, "PDM2 Power" }, 4065 { "PDM2 R Mux", "STO1 DAC MIX", "Stereo DAC MIXR" }, 4066 { "PDM2 R Mux", "MONO DAC MIX", "Mono DAC MIXR" }, 4067 { "PDM2 R Mux", "DD MIX1", "DD1 MIXR" }, 4068 { "PDM2 R Mux", "DD MIX1", "DD2 MIXR" }, 4069 { "PDM2 R Mux", NULL, "PDM2 Power" }, 4070 4071 { "LOUT1 amp", NULL, "DAC 1" }, 4072 { "LOUT2 amp", NULL, "DAC 2" }, 4073 { "LOUT3 amp", NULL, "DAC 3" }, 4074 4075 { "LOUT1 vref", NULL, "LOUT1 amp" }, 4076 { "LOUT2 vref", NULL, "LOUT2 amp" }, 4077 { "LOUT3 vref", NULL, "LOUT3 amp" }, 4078 4079 { "LOUT1", NULL, "LOUT1 vref" }, 4080 { "LOUT2", NULL, "LOUT2 vref" }, 4081 { "LOUT3", NULL, "LOUT3 vref" }, 4082 4083 { "PDM1L", NULL, "PDM1 L Mux" }, 4084 { "PDM1R", NULL, "PDM1 R Mux" }, 4085 { "PDM2L", NULL, "PDM2 L Mux" }, 4086 { "PDM2R", NULL, "PDM2 R Mux" }, 4087 }; 4088 4089 static const struct snd_soc_dapm_route rt5677_dmic2_clk_1[] = { 4090 { "DMIC L2", NULL, "DMIC1 power" }, 4091 { "DMIC R2", NULL, "DMIC1 power" }, 4092 }; 4093 4094 static const struct snd_soc_dapm_route rt5677_dmic2_clk_2[] = { 4095 { "DMIC L2", NULL, "DMIC2 power" }, 4096 { "DMIC R2", NULL, "DMIC2 power" }, 4097 }; 4098 4099 static int rt5677_hw_params(struct snd_pcm_substream *substream, 4100 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) 4101 { 4102 struct snd_soc_component *component = dai->component; 4103 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component); 4104 unsigned int val_len = 0, val_clk, mask_clk; 4105 int pre_div, bclk_ms, frame_size; 4106 4107 rt5677->lrck[dai->id] = params_rate(params); 4108 pre_div = rl6231_get_clk_info(rt5677->sysclk, rt5677->lrck[dai->id]); 4109 if (pre_div < 0) { 4110 dev_err(component->dev, "Unsupported clock setting: sysclk=%dHz lrck=%dHz\n", 4111 rt5677->sysclk, rt5677->lrck[dai->id]); 4112 return -EINVAL; 4113 } 4114 frame_size = snd_soc_params_to_frame_size(params); 4115 if (frame_size < 0) { 4116 dev_err(component->dev, "Unsupported frame size: %d\n", frame_size); 4117 return -EINVAL; 4118 } 4119 bclk_ms = frame_size > 32; 4120 rt5677->bclk[dai->id] = rt5677->lrck[dai->id] * (32 << bclk_ms); 4121 4122 dev_dbg(dai->dev, "bclk is %dHz and lrck is %dHz\n", 4123 rt5677->bclk[dai->id], rt5677->lrck[dai->id]); 4124 dev_dbg(dai->dev, "bclk_ms is %d and pre_div is %d for iis %d\n", 4125 bclk_ms, pre_div, dai->id); 4126 4127 switch (params_width(params)) { 4128 case 16: 4129 break; 4130 case 20: 4131 val_len |= RT5677_I2S_DL_20; 4132 break; 4133 case 24: 4134 val_len |= RT5677_I2S_DL_24; 4135 break; 4136 case 8: 4137 val_len |= RT5677_I2S_DL_8; 4138 break; 4139 default: 4140 return -EINVAL; 4141 } 4142 4143 switch (dai->id) { 4144 case RT5677_AIF1: 4145 mask_clk = RT5677_I2S_PD1_MASK; 4146 val_clk = pre_div << RT5677_I2S_PD1_SFT; 4147 regmap_update_bits(rt5677->regmap, RT5677_I2S1_SDP, 4148 RT5677_I2S_DL_MASK, val_len); 4149 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1, 4150 mask_clk, val_clk); 4151 break; 4152 case RT5677_AIF2: 4153 mask_clk = RT5677_I2S_PD2_MASK; 4154 val_clk = pre_div << RT5677_I2S_PD2_SFT; 4155 regmap_update_bits(rt5677->regmap, RT5677_I2S2_SDP, 4156 RT5677_I2S_DL_MASK, val_len); 4157 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1, 4158 mask_clk, val_clk); 4159 break; 4160 case RT5677_AIF3: 4161 mask_clk = RT5677_I2S_BCLK_MS3_MASK | RT5677_I2S_PD3_MASK; 4162 val_clk = bclk_ms << RT5677_I2S_BCLK_MS3_SFT | 4163 pre_div << RT5677_I2S_PD3_SFT; 4164 regmap_update_bits(rt5677->regmap, RT5677_I2S3_SDP, 4165 RT5677_I2S_DL_MASK, val_len); 4166 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1, 4167 mask_clk, val_clk); 4168 break; 4169 case RT5677_AIF4: 4170 mask_clk = RT5677_I2S_BCLK_MS4_MASK | RT5677_I2S_PD4_MASK; 4171 val_clk = bclk_ms << RT5677_I2S_BCLK_MS4_SFT | 4172 pre_div << RT5677_I2S_PD4_SFT; 4173 regmap_update_bits(rt5677->regmap, RT5677_I2S4_SDP, 4174 RT5677_I2S_DL_MASK, val_len); 4175 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1, 4176 mask_clk, val_clk); 4177 break; 4178 default: 4179 break; 4180 } 4181 4182 return 0; 4183 } 4184 4185 static int rt5677_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) 4186 { 4187 struct snd_soc_component *component = dai->component; 4188 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component); 4189 unsigned int reg_val = 0; 4190 4191 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 4192 case SND_SOC_DAIFMT_CBM_CFM: 4193 rt5677->master[dai->id] = 1; 4194 break; 4195 case SND_SOC_DAIFMT_CBS_CFS: 4196 reg_val |= RT5677_I2S_MS_S; 4197 rt5677->master[dai->id] = 0; 4198 break; 4199 default: 4200 return -EINVAL; 4201 } 4202 4203 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 4204 case SND_SOC_DAIFMT_NB_NF: 4205 break; 4206 case SND_SOC_DAIFMT_IB_NF: 4207 reg_val |= RT5677_I2S_BP_INV; 4208 break; 4209 default: 4210 return -EINVAL; 4211 } 4212 4213 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 4214 case SND_SOC_DAIFMT_I2S: 4215 break; 4216 case SND_SOC_DAIFMT_LEFT_J: 4217 reg_val |= RT5677_I2S_DF_LEFT; 4218 break; 4219 case SND_SOC_DAIFMT_DSP_A: 4220 reg_val |= RT5677_I2S_DF_PCM_A; 4221 break; 4222 case SND_SOC_DAIFMT_DSP_B: 4223 reg_val |= RT5677_I2S_DF_PCM_B; 4224 break; 4225 default: 4226 return -EINVAL; 4227 } 4228 4229 switch (dai->id) { 4230 case RT5677_AIF1: 4231 regmap_update_bits(rt5677->regmap, RT5677_I2S1_SDP, 4232 RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK | 4233 RT5677_I2S_DF_MASK, reg_val); 4234 break; 4235 case RT5677_AIF2: 4236 regmap_update_bits(rt5677->regmap, RT5677_I2S2_SDP, 4237 RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK | 4238 RT5677_I2S_DF_MASK, reg_val); 4239 break; 4240 case RT5677_AIF3: 4241 regmap_update_bits(rt5677->regmap, RT5677_I2S3_SDP, 4242 RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK | 4243 RT5677_I2S_DF_MASK, reg_val); 4244 break; 4245 case RT5677_AIF4: 4246 regmap_update_bits(rt5677->regmap, RT5677_I2S4_SDP, 4247 RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK | 4248 RT5677_I2S_DF_MASK, reg_val); 4249 break; 4250 default: 4251 break; 4252 } 4253 4254 4255 return 0; 4256 } 4257 4258 static int rt5677_set_dai_sysclk(struct snd_soc_dai *dai, 4259 int clk_id, unsigned int freq, int dir) 4260 { 4261 struct snd_soc_component *component = dai->component; 4262 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component); 4263 unsigned int reg_val = 0; 4264 4265 if (freq == rt5677->sysclk && clk_id == rt5677->sysclk_src) 4266 return 0; 4267 4268 switch (clk_id) { 4269 case RT5677_SCLK_S_MCLK: 4270 reg_val |= RT5677_SCLK_SRC_MCLK; 4271 break; 4272 case RT5677_SCLK_S_PLL1: 4273 reg_val |= RT5677_SCLK_SRC_PLL1; 4274 break; 4275 case RT5677_SCLK_S_RCCLK: 4276 reg_val |= RT5677_SCLK_SRC_RCCLK; 4277 break; 4278 default: 4279 dev_err(component->dev, "Invalid clock id (%d)\n", clk_id); 4280 return -EINVAL; 4281 } 4282 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1, 4283 RT5677_SCLK_SRC_MASK, reg_val); 4284 rt5677->sysclk = freq; 4285 rt5677->sysclk_src = clk_id; 4286 4287 dev_dbg(dai->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id); 4288 4289 return 0; 4290 } 4291 4292 /** 4293 * rt5677_pll_calc - Calcualte PLL M/N/K code. 4294 * @freq_in: external clock provided to codec. 4295 * @freq_out: target clock which codec works on. 4296 * @pll_code: Pointer to structure with M, N, K, bypass K and bypass M flag. 4297 * 4298 * Calcualte M/N/K code and bypass K/M flag to configure PLL for codec. 4299 * 4300 * Returns 0 for success or negative error code. 4301 */ 4302 static int rt5677_pll_calc(const unsigned int freq_in, 4303 const unsigned int freq_out, struct rl6231_pll_code *pll_code) 4304 { 4305 if (RT5677_PLL_INP_MIN > freq_in) 4306 return -EINVAL; 4307 4308 return rl6231_pll_calc(freq_in, freq_out, pll_code); 4309 } 4310 4311 static int rt5677_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source, 4312 unsigned int freq_in, unsigned int freq_out) 4313 { 4314 struct snd_soc_component *component = dai->component; 4315 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component); 4316 struct rl6231_pll_code pll_code; 4317 int ret; 4318 4319 if (source == rt5677->pll_src && freq_in == rt5677->pll_in && 4320 freq_out == rt5677->pll_out) 4321 return 0; 4322 4323 if (!freq_in || !freq_out) { 4324 dev_dbg(component->dev, "PLL disabled\n"); 4325 4326 rt5677->pll_in = 0; 4327 rt5677->pll_out = 0; 4328 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1, 4329 RT5677_SCLK_SRC_MASK, RT5677_SCLK_SRC_MCLK); 4330 return 0; 4331 } 4332 4333 switch (source) { 4334 case RT5677_PLL1_S_MCLK: 4335 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1, 4336 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_MCLK); 4337 break; 4338 case RT5677_PLL1_S_BCLK1: 4339 case RT5677_PLL1_S_BCLK2: 4340 case RT5677_PLL1_S_BCLK3: 4341 case RT5677_PLL1_S_BCLK4: 4342 switch (dai->id) { 4343 case RT5677_AIF1: 4344 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1, 4345 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK1); 4346 break; 4347 case RT5677_AIF2: 4348 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1, 4349 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK2); 4350 break; 4351 case RT5677_AIF3: 4352 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1, 4353 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK3); 4354 break; 4355 case RT5677_AIF4: 4356 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1, 4357 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK4); 4358 break; 4359 default: 4360 break; 4361 } 4362 break; 4363 default: 4364 dev_err(component->dev, "Unknown PLL source %d\n", source); 4365 return -EINVAL; 4366 } 4367 4368 ret = rt5677_pll_calc(freq_in, freq_out, &pll_code); 4369 if (ret < 0) { 4370 dev_err(component->dev, "Unsupport input clock %d\n", freq_in); 4371 return ret; 4372 } 4373 4374 dev_dbg(component->dev, "m_bypass=%d m=%d n=%d k=%d\n", 4375 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code), 4376 pll_code.n_code, pll_code.k_code); 4377 4378 regmap_write(rt5677->regmap, RT5677_PLL1_CTRL1, 4379 pll_code.n_code << RT5677_PLL_N_SFT | pll_code.k_code); 4380 regmap_write(rt5677->regmap, RT5677_PLL1_CTRL2, 4381 (pll_code.m_bp ? 0 : pll_code.m_code) << RT5677_PLL_M_SFT | 4382 pll_code.m_bp << RT5677_PLL_M_BP_SFT); 4383 4384 rt5677->pll_in = freq_in; 4385 rt5677->pll_out = freq_out; 4386 rt5677->pll_src = source; 4387 4388 return 0; 4389 } 4390 4391 static int rt5677_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask, 4392 unsigned int rx_mask, int slots, int slot_width) 4393 { 4394 struct snd_soc_component *component = dai->component; 4395 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component); 4396 unsigned int val = 0, slot_width_25 = 0; 4397 4398 if (rx_mask || tx_mask) 4399 val |= (1 << 12); 4400 4401 switch (slots) { 4402 case 4: 4403 val |= (1 << 10); 4404 break; 4405 case 6: 4406 val |= (2 << 10); 4407 break; 4408 case 8: 4409 val |= (3 << 10); 4410 break; 4411 case 2: 4412 default: 4413 break; 4414 } 4415 4416 switch (slot_width) { 4417 case 20: 4418 val |= (1 << 8); 4419 break; 4420 case 25: 4421 slot_width_25 = 0x8080; 4422 /* fall through */ 4423 case 24: 4424 val |= (2 << 8); 4425 break; 4426 case 32: 4427 val |= (3 << 8); 4428 break; 4429 case 16: 4430 default: 4431 break; 4432 } 4433 4434 switch (dai->id) { 4435 case RT5677_AIF1: 4436 regmap_update_bits(rt5677->regmap, RT5677_TDM1_CTRL1, 0x1f00, 4437 val); 4438 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x8000, 4439 slot_width_25); 4440 break; 4441 case RT5677_AIF2: 4442 regmap_update_bits(rt5677->regmap, RT5677_TDM2_CTRL1, 0x1f00, 4443 val); 4444 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x80, 4445 slot_width_25); 4446 break; 4447 default: 4448 break; 4449 } 4450 4451 return 0; 4452 } 4453 4454 static int rt5677_set_bias_level(struct snd_soc_component *component, 4455 enum snd_soc_bias_level level) 4456 { 4457 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component); 4458 4459 switch (level) { 4460 case SND_SOC_BIAS_ON: 4461 break; 4462 4463 case SND_SOC_BIAS_PREPARE: 4464 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_STANDBY) { 4465 rt5677_set_dsp_vad(component, false); 4466 4467 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1, 4468 RT5677_LDO1_SEL_MASK | RT5677_LDO2_SEL_MASK, 4469 0x0055); 4470 regmap_update_bits(rt5677->regmap, 4471 RT5677_PR_BASE + RT5677_BIAS_CUR4, 4472 0x0f00, 0x0f00); 4473 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1, 4474 RT5677_PWR_FV1 | RT5677_PWR_FV2 | 4475 RT5677_PWR_VREF1 | RT5677_PWR_MB | 4476 RT5677_PWR_BG | RT5677_PWR_VREF2, 4477 RT5677_PWR_VREF1 | RT5677_PWR_MB | 4478 RT5677_PWR_BG | RT5677_PWR_VREF2); 4479 rt5677->is_vref_slow = false; 4480 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2, 4481 RT5677_PWR_CORE, RT5677_PWR_CORE); 4482 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 4483 0x1, 0x1); 4484 } 4485 break; 4486 4487 case SND_SOC_BIAS_STANDBY: 4488 break; 4489 4490 case SND_SOC_BIAS_OFF: 4491 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x1, 0x0); 4492 regmap_write(rt5677->regmap, RT5677_PWR_DIG1, 0x0000); 4493 regmap_write(rt5677->regmap, RT5677_PWR_DIG2, 0x0000); 4494 regmap_write(rt5677->regmap, RT5677_PWR_ANLG1, 0x0022); 4495 regmap_write(rt5677->regmap, RT5677_PWR_ANLG2, 0x0000); 4496 regmap_update_bits(rt5677->regmap, 4497 RT5677_PR_BASE + RT5677_BIAS_CUR4, 0x0f00, 0x0000); 4498 4499 if (rt5677->dsp_vad_en) 4500 rt5677_set_dsp_vad(component, true); 4501 break; 4502 4503 default: 4504 break; 4505 } 4506 4507 return 0; 4508 } 4509 4510 #ifdef CONFIG_GPIOLIB 4511 static void rt5677_gpio_set(struct gpio_chip *chip, unsigned offset, int value) 4512 { 4513 struct rt5677_priv *rt5677 = gpiochip_get_data(chip); 4514 4515 switch (offset) { 4516 case RT5677_GPIO1 ... RT5677_GPIO5: 4517 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2, 4518 0x1 << (offset * 3 + 1), !!value << (offset * 3 + 1)); 4519 break; 4520 4521 case RT5677_GPIO6: 4522 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL3, 4523 RT5677_GPIO6_OUT_MASK, !!value << RT5677_GPIO6_OUT_SFT); 4524 break; 4525 4526 default: 4527 break; 4528 } 4529 } 4530 4531 static int rt5677_gpio_direction_out(struct gpio_chip *chip, 4532 unsigned offset, int value) 4533 { 4534 struct rt5677_priv *rt5677 = gpiochip_get_data(chip); 4535 4536 switch (offset) { 4537 case RT5677_GPIO1 ... RT5677_GPIO5: 4538 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2, 4539 0x3 << (offset * 3 + 1), 4540 (0x2 | !!value) << (offset * 3 + 1)); 4541 break; 4542 4543 case RT5677_GPIO6: 4544 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL3, 4545 RT5677_GPIO6_DIR_MASK | RT5677_GPIO6_OUT_MASK, 4546 RT5677_GPIO6_DIR_OUT | !!value << RT5677_GPIO6_OUT_SFT); 4547 break; 4548 4549 default: 4550 break; 4551 } 4552 4553 return 0; 4554 } 4555 4556 static int rt5677_gpio_get(struct gpio_chip *chip, unsigned offset) 4557 { 4558 struct rt5677_priv *rt5677 = gpiochip_get_data(chip); 4559 int value, ret; 4560 4561 ret = regmap_read(rt5677->regmap, RT5677_GPIO_ST, &value); 4562 if (ret < 0) 4563 return ret; 4564 4565 return (value & (0x1 << offset)) >> offset; 4566 } 4567 4568 static int rt5677_gpio_direction_in(struct gpio_chip *chip, unsigned offset) 4569 { 4570 struct rt5677_priv *rt5677 = gpiochip_get_data(chip); 4571 4572 switch (offset) { 4573 case RT5677_GPIO1 ... RT5677_GPIO5: 4574 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2, 4575 0x1 << (offset * 3 + 2), 0x0); 4576 break; 4577 4578 case RT5677_GPIO6: 4579 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL3, 4580 RT5677_GPIO6_DIR_MASK, RT5677_GPIO6_DIR_IN); 4581 break; 4582 4583 default: 4584 break; 4585 } 4586 4587 return 0; 4588 } 4589 4590 /** Configures the gpio as 4591 * 0 - floating 4592 * 1 - pull down 4593 * 2 - pull up 4594 */ 4595 static void rt5677_gpio_config(struct rt5677_priv *rt5677, unsigned offset, 4596 int value) 4597 { 4598 int shift; 4599 4600 switch (offset) { 4601 case RT5677_GPIO1 ... RT5677_GPIO2: 4602 shift = 2 * (1 - offset); 4603 regmap_update_bits(rt5677->regmap, 4604 RT5677_PR_BASE + RT5677_DIG_IN_PIN_ST_CTRL2, 4605 0x3 << shift, 4606 (value & 0x3) << shift); 4607 break; 4608 4609 case RT5677_GPIO3 ... RT5677_GPIO6: 4610 shift = 2 * (9 - offset); 4611 regmap_update_bits(rt5677->regmap, 4612 RT5677_PR_BASE + RT5677_DIG_IN_PIN_ST_CTRL3, 4613 0x3 << shift, 4614 (value & 0x3) << shift); 4615 break; 4616 4617 default: 4618 break; 4619 } 4620 } 4621 4622 static int rt5677_to_irq(struct gpio_chip *chip, unsigned offset) 4623 { 4624 struct rt5677_priv *rt5677 = gpiochip_get_data(chip); 4625 int irq; 4626 4627 if ((rt5677->pdata.jd1_gpio == 1 && offset == RT5677_GPIO1) || 4628 (rt5677->pdata.jd1_gpio == 2 && 4629 offset == RT5677_GPIO2) || 4630 (rt5677->pdata.jd1_gpio == 3 && 4631 offset == RT5677_GPIO3)) { 4632 irq = RT5677_IRQ_JD1; 4633 } else if ((rt5677->pdata.jd2_gpio == 1 && offset == RT5677_GPIO4) || 4634 (rt5677->pdata.jd2_gpio == 2 && 4635 offset == RT5677_GPIO5) || 4636 (rt5677->pdata.jd2_gpio == 3 && 4637 offset == RT5677_GPIO6)) { 4638 irq = RT5677_IRQ_JD2; 4639 } else if ((rt5677->pdata.jd3_gpio == 1 && 4640 offset == RT5677_GPIO4) || 4641 (rt5677->pdata.jd3_gpio == 2 && 4642 offset == RT5677_GPIO5) || 4643 (rt5677->pdata.jd3_gpio == 3 && 4644 offset == RT5677_GPIO6)) { 4645 irq = RT5677_IRQ_JD3; 4646 } else { 4647 return -ENXIO; 4648 } 4649 4650 return irq_create_mapping(rt5677->domain, irq); 4651 } 4652 4653 static const struct gpio_chip rt5677_template_chip = { 4654 .label = RT5677_DRV_NAME, 4655 .owner = THIS_MODULE, 4656 .direction_output = rt5677_gpio_direction_out, 4657 .set = rt5677_gpio_set, 4658 .direction_input = rt5677_gpio_direction_in, 4659 .get = rt5677_gpio_get, 4660 .to_irq = rt5677_to_irq, 4661 .can_sleep = 1, 4662 }; 4663 4664 static void rt5677_init_gpio(struct i2c_client *i2c) 4665 { 4666 struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c); 4667 int ret; 4668 4669 rt5677->gpio_chip = rt5677_template_chip; 4670 rt5677->gpio_chip.ngpio = RT5677_GPIO_NUM; 4671 rt5677->gpio_chip.parent = &i2c->dev; 4672 rt5677->gpio_chip.base = -1; 4673 4674 ret = gpiochip_add_data(&rt5677->gpio_chip, rt5677); 4675 if (ret != 0) 4676 dev_err(&i2c->dev, "Failed to add GPIOs: %d\n", ret); 4677 } 4678 4679 static void rt5677_free_gpio(struct i2c_client *i2c) 4680 { 4681 struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c); 4682 4683 gpiochip_remove(&rt5677->gpio_chip); 4684 } 4685 #else 4686 static void rt5677_gpio_config(struct rt5677_priv *rt5677, unsigned offset, 4687 int value) 4688 { 4689 } 4690 4691 static void rt5677_init_gpio(struct i2c_client *i2c) 4692 { 4693 } 4694 4695 static void rt5677_free_gpio(struct i2c_client *i2c) 4696 { 4697 } 4698 #endif 4699 4700 static int rt5677_probe(struct snd_soc_component *component) 4701 { 4702 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); 4703 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component); 4704 int i; 4705 4706 rt5677->component = component; 4707 4708 if (rt5677->pdata.dmic2_clk_pin == RT5677_DMIC_CLK2) { 4709 snd_soc_dapm_add_routes(dapm, 4710 rt5677_dmic2_clk_2, 4711 ARRAY_SIZE(rt5677_dmic2_clk_2)); 4712 } else { /*use dmic1 clock by default*/ 4713 snd_soc_dapm_add_routes(dapm, 4714 rt5677_dmic2_clk_1, 4715 ARRAY_SIZE(rt5677_dmic2_clk_1)); 4716 } 4717 4718 snd_soc_component_force_bias_level(component, SND_SOC_BIAS_OFF); 4719 4720 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 4721 ~RT5677_IRQ_DEBOUNCE_SEL_MASK, 0x0020); 4722 regmap_write(rt5677->regmap, RT5677_PWR_DSP2, 0x0c00); 4723 4724 for (i = 0; i < RT5677_GPIO_NUM; i++) 4725 rt5677_gpio_config(rt5677, i, rt5677->pdata.gpio_config[i]); 4726 4727 mutex_init(&rt5677->dsp_cmd_lock); 4728 mutex_init(&rt5677->dsp_pri_lock); 4729 4730 return 0; 4731 } 4732 4733 static void rt5677_remove(struct snd_soc_component *component) 4734 { 4735 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component); 4736 4737 regmap_write(rt5677->regmap, RT5677_RESET, 0x10ec); 4738 gpiod_set_value_cansleep(rt5677->pow_ldo2, 0); 4739 gpiod_set_value_cansleep(rt5677->reset_pin, 1); 4740 } 4741 4742 #ifdef CONFIG_PM 4743 static int rt5677_suspend(struct snd_soc_component *component) 4744 { 4745 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component); 4746 4747 if (!rt5677->dsp_vad_en) { 4748 regcache_cache_only(rt5677->regmap, true); 4749 regcache_mark_dirty(rt5677->regmap); 4750 4751 gpiod_set_value_cansleep(rt5677->pow_ldo2, 0); 4752 gpiod_set_value_cansleep(rt5677->reset_pin, 1); 4753 } 4754 4755 return 0; 4756 } 4757 4758 static int rt5677_resume(struct snd_soc_component *component) 4759 { 4760 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component); 4761 4762 if (!rt5677->dsp_vad_en) { 4763 rt5677->pll_src = 0; 4764 rt5677->pll_in = 0; 4765 rt5677->pll_out = 0; 4766 gpiod_set_value_cansleep(rt5677->pow_ldo2, 1); 4767 gpiod_set_value_cansleep(rt5677->reset_pin, 0); 4768 if (rt5677->pow_ldo2 || rt5677->reset_pin) 4769 msleep(10); 4770 4771 regcache_cache_only(rt5677->regmap, false); 4772 regcache_sync(rt5677->regmap); 4773 } 4774 4775 return 0; 4776 } 4777 #else 4778 #define rt5677_suspend NULL 4779 #define rt5677_resume NULL 4780 #endif 4781 4782 static int rt5677_read(void *context, unsigned int reg, unsigned int *val) 4783 { 4784 struct i2c_client *client = context; 4785 struct rt5677_priv *rt5677 = i2c_get_clientdata(client); 4786 4787 if (rt5677->is_dsp_mode) { 4788 if (reg > 0xff) { 4789 mutex_lock(&rt5677->dsp_pri_lock); 4790 rt5677_dsp_mode_i2c_write(rt5677, RT5677_PRIV_INDEX, 4791 reg & 0xff); 4792 rt5677_dsp_mode_i2c_read(rt5677, RT5677_PRIV_DATA, val); 4793 mutex_unlock(&rt5677->dsp_pri_lock); 4794 } else { 4795 rt5677_dsp_mode_i2c_read(rt5677, reg, val); 4796 } 4797 } else { 4798 regmap_read(rt5677->regmap_physical, reg, val); 4799 } 4800 4801 return 0; 4802 } 4803 4804 static int rt5677_write(void *context, unsigned int reg, unsigned int val) 4805 { 4806 struct i2c_client *client = context; 4807 struct rt5677_priv *rt5677 = i2c_get_clientdata(client); 4808 4809 if (rt5677->is_dsp_mode) { 4810 if (reg > 0xff) { 4811 mutex_lock(&rt5677->dsp_pri_lock); 4812 rt5677_dsp_mode_i2c_write(rt5677, RT5677_PRIV_INDEX, 4813 reg & 0xff); 4814 rt5677_dsp_mode_i2c_write(rt5677, RT5677_PRIV_DATA, 4815 val); 4816 mutex_unlock(&rt5677->dsp_pri_lock); 4817 } else { 4818 rt5677_dsp_mode_i2c_write(rt5677, reg, val); 4819 } 4820 } else { 4821 regmap_write(rt5677->regmap_physical, reg, val); 4822 } 4823 4824 return 0; 4825 } 4826 4827 #define RT5677_STEREO_RATES SNDRV_PCM_RATE_8000_96000 4828 #define RT5677_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ 4829 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8) 4830 4831 static const struct snd_soc_dai_ops rt5677_aif_dai_ops = { 4832 .hw_params = rt5677_hw_params, 4833 .set_fmt = rt5677_set_dai_fmt, 4834 .set_sysclk = rt5677_set_dai_sysclk, 4835 .set_pll = rt5677_set_dai_pll, 4836 .set_tdm_slot = rt5677_set_tdm_slot, 4837 }; 4838 4839 static struct snd_soc_dai_driver rt5677_dai[] = { 4840 { 4841 .name = "rt5677-aif1", 4842 .id = RT5677_AIF1, 4843 .playback = { 4844 .stream_name = "AIF1 Playback", 4845 .channels_min = 1, 4846 .channels_max = 2, 4847 .rates = RT5677_STEREO_RATES, 4848 .formats = RT5677_FORMATS, 4849 }, 4850 .capture = { 4851 .stream_name = "AIF1 Capture", 4852 .channels_min = 1, 4853 .channels_max = 2, 4854 .rates = RT5677_STEREO_RATES, 4855 .formats = RT5677_FORMATS, 4856 }, 4857 .ops = &rt5677_aif_dai_ops, 4858 }, 4859 { 4860 .name = "rt5677-aif2", 4861 .id = RT5677_AIF2, 4862 .playback = { 4863 .stream_name = "AIF2 Playback", 4864 .channels_min = 1, 4865 .channels_max = 2, 4866 .rates = RT5677_STEREO_RATES, 4867 .formats = RT5677_FORMATS, 4868 }, 4869 .capture = { 4870 .stream_name = "AIF2 Capture", 4871 .channels_min = 1, 4872 .channels_max = 2, 4873 .rates = RT5677_STEREO_RATES, 4874 .formats = RT5677_FORMATS, 4875 }, 4876 .ops = &rt5677_aif_dai_ops, 4877 }, 4878 { 4879 .name = "rt5677-aif3", 4880 .id = RT5677_AIF3, 4881 .playback = { 4882 .stream_name = "AIF3 Playback", 4883 .channels_min = 1, 4884 .channels_max = 2, 4885 .rates = RT5677_STEREO_RATES, 4886 .formats = RT5677_FORMATS, 4887 }, 4888 .capture = { 4889 .stream_name = "AIF3 Capture", 4890 .channels_min = 1, 4891 .channels_max = 2, 4892 .rates = RT5677_STEREO_RATES, 4893 .formats = RT5677_FORMATS, 4894 }, 4895 .ops = &rt5677_aif_dai_ops, 4896 }, 4897 { 4898 .name = "rt5677-aif4", 4899 .id = RT5677_AIF4, 4900 .playback = { 4901 .stream_name = "AIF4 Playback", 4902 .channels_min = 1, 4903 .channels_max = 2, 4904 .rates = RT5677_STEREO_RATES, 4905 .formats = RT5677_FORMATS, 4906 }, 4907 .capture = { 4908 .stream_name = "AIF4 Capture", 4909 .channels_min = 1, 4910 .channels_max = 2, 4911 .rates = RT5677_STEREO_RATES, 4912 .formats = RT5677_FORMATS, 4913 }, 4914 .ops = &rt5677_aif_dai_ops, 4915 }, 4916 { 4917 .name = "rt5677-slimbus", 4918 .id = RT5677_AIF5, 4919 .playback = { 4920 .stream_name = "SLIMBus Playback", 4921 .channels_min = 1, 4922 .channels_max = 2, 4923 .rates = RT5677_STEREO_RATES, 4924 .formats = RT5677_FORMATS, 4925 }, 4926 .capture = { 4927 .stream_name = "SLIMBus Capture", 4928 .channels_min = 1, 4929 .channels_max = 2, 4930 .rates = RT5677_STEREO_RATES, 4931 .formats = RT5677_FORMATS, 4932 }, 4933 .ops = &rt5677_aif_dai_ops, 4934 }, 4935 }; 4936 4937 static const struct snd_soc_component_driver soc_component_dev_rt5677 = { 4938 .name = RT5677_DRV_NAME, 4939 .probe = rt5677_probe, 4940 .remove = rt5677_remove, 4941 .suspend = rt5677_suspend, 4942 .resume = rt5677_resume, 4943 .set_bias_level = rt5677_set_bias_level, 4944 .controls = rt5677_snd_controls, 4945 .num_controls = ARRAY_SIZE(rt5677_snd_controls), 4946 .dapm_widgets = rt5677_dapm_widgets, 4947 .num_dapm_widgets = ARRAY_SIZE(rt5677_dapm_widgets), 4948 .dapm_routes = rt5677_dapm_routes, 4949 .num_dapm_routes = ARRAY_SIZE(rt5677_dapm_routes), 4950 .use_pmdown_time = 1, 4951 .endianness = 1, 4952 .non_legacy_dai_naming = 1, 4953 }; 4954 4955 static const struct regmap_config rt5677_regmap_physical = { 4956 .name = "physical", 4957 .reg_bits = 8, 4958 .val_bits = 16, 4959 4960 .max_register = RT5677_VENDOR_ID2 + 1 + (ARRAY_SIZE(rt5677_ranges) * 4961 RT5677_PR_SPACING), 4962 .readable_reg = rt5677_readable_register, 4963 4964 .cache_type = REGCACHE_NONE, 4965 .ranges = rt5677_ranges, 4966 .num_ranges = ARRAY_SIZE(rt5677_ranges), 4967 }; 4968 4969 static const struct regmap_config rt5677_regmap = { 4970 .reg_bits = 8, 4971 .val_bits = 16, 4972 4973 .max_register = RT5677_VENDOR_ID2 + 1 + (ARRAY_SIZE(rt5677_ranges) * 4974 RT5677_PR_SPACING), 4975 4976 .volatile_reg = rt5677_volatile_register, 4977 .readable_reg = rt5677_readable_register, 4978 .reg_read = rt5677_read, 4979 .reg_write = rt5677_write, 4980 4981 .cache_type = REGCACHE_RBTREE, 4982 .reg_defaults = rt5677_reg, 4983 .num_reg_defaults = ARRAY_SIZE(rt5677_reg), 4984 .ranges = rt5677_ranges, 4985 .num_ranges = ARRAY_SIZE(rt5677_ranges), 4986 }; 4987 4988 static const struct of_device_id rt5677_of_match[] = { 4989 { .compatible = "realtek,rt5677", .data = (const void *)RT5677 }, 4990 { } 4991 }; 4992 MODULE_DEVICE_TABLE(of, rt5677_of_match); 4993 4994 static const struct acpi_device_id rt5677_acpi_match[] = { 4995 { "RT5677CE", RT5677 }, 4996 { } 4997 }; 4998 MODULE_DEVICE_TABLE(acpi, rt5677_acpi_match); 4999 5000 static void rt5677_read_device_properties(struct rt5677_priv *rt5677, 5001 struct device *dev) 5002 { 5003 u32 val; 5004 5005 rt5677->pdata.in1_diff = 5006 device_property_read_bool(dev, "IN1") || 5007 device_property_read_bool(dev, "realtek,in1-differential"); 5008 5009 rt5677->pdata.in2_diff = 5010 device_property_read_bool(dev, "IN2") || 5011 device_property_read_bool(dev, "realtek,in2-differential"); 5012 5013 rt5677->pdata.lout1_diff = 5014 device_property_read_bool(dev, "OUT1") || 5015 device_property_read_bool(dev, "realtek,lout1-differential"); 5016 5017 rt5677->pdata.lout2_diff = 5018 device_property_read_bool(dev, "OUT2") || 5019 device_property_read_bool(dev, "realtek,lout2-differential"); 5020 5021 rt5677->pdata.lout3_diff = 5022 device_property_read_bool(dev, "OUT3") || 5023 device_property_read_bool(dev, "realtek,lout3-differential"); 5024 5025 device_property_read_u8_array(dev, "realtek,gpio-config", 5026 rt5677->pdata.gpio_config, 5027 RT5677_GPIO_NUM); 5028 5029 if (!device_property_read_u32(dev, "DCLK", &val) || 5030 !device_property_read_u32(dev, "realtek,dmic2_clk_pin", &val)) 5031 rt5677->pdata.dmic2_clk_pin = val; 5032 5033 if (!device_property_read_u32(dev, "JD1", &val) || 5034 !device_property_read_u32(dev, "realtek,jd1-gpio", &val)) 5035 rt5677->pdata.jd1_gpio = val; 5036 5037 if (!device_property_read_u32(dev, "JD2", &val) || 5038 !device_property_read_u32(dev, "realtek,jd2-gpio", &val)) 5039 rt5677->pdata.jd2_gpio = val; 5040 5041 if (!device_property_read_u32(dev, "JD3", &val) || 5042 !device_property_read_u32(dev, "realtek,jd3-gpio", &val)) 5043 rt5677->pdata.jd3_gpio = val; 5044 } 5045 5046 struct rt5677_irq_desc { 5047 unsigned int enable_mask; 5048 unsigned int status_mask; 5049 unsigned int polarity_mask; 5050 }; 5051 5052 static const struct rt5677_irq_desc rt5677_irq_descs[] = { 5053 [RT5677_IRQ_JD1] = { 5054 .enable_mask = RT5677_EN_IRQ_GPIO_JD1, 5055 .status_mask = RT5677_STA_GPIO_JD1, 5056 .polarity_mask = RT5677_INV_GPIO_JD1, 5057 }, 5058 [RT5677_IRQ_JD2] = { 5059 .enable_mask = RT5677_EN_IRQ_GPIO_JD2, 5060 .status_mask = RT5677_STA_GPIO_JD2, 5061 .polarity_mask = RT5677_INV_GPIO_JD2, 5062 }, 5063 [RT5677_IRQ_JD3] = { 5064 .enable_mask = RT5677_EN_IRQ_GPIO_JD3, 5065 .status_mask = RT5677_STA_GPIO_JD3, 5066 .polarity_mask = RT5677_INV_GPIO_JD3, 5067 }, 5068 }; 5069 5070 static irqreturn_t rt5677_irq(int unused, void *data) 5071 { 5072 struct rt5677_priv *rt5677 = data; 5073 int ret = 0, loop, i, reg_irq, virq; 5074 bool irq_fired = false; 5075 5076 mutex_lock(&rt5677->irq_lock); 5077 5078 /* 5079 * Loop to handle interrupts until the last i2c read shows no pending 5080 * irqs. The interrupt line is shared by multiple interrupt sources. 5081 * After the regmap_read() below, a new interrupt source line may 5082 * become high before the regmap_write() finishes, so there isn't a 5083 * rising edge on the shared interrupt line for the new interrupt. Thus, 5084 * the loop is needed to avoid missing irqs. 5085 * 5086 * A safeguard of 20 loops is used to avoid hanging in the irq handler 5087 * if there is something wrong with the interrupt status update. The 5088 * interrupt sources here are audio jack plug/unplug events which 5089 * shouldn't happen at a high frequency for a long period of time. 5090 * Empirically, more than 3 loops have never been seen. 5091 */ 5092 for (loop = 0; loop < 20; loop++) { 5093 /* Read interrupt status */ 5094 ret = regmap_read(rt5677->regmap, RT5677_IRQ_CTRL1, ®_irq); 5095 if (ret) { 5096 dev_err(rt5677->dev, "failed reading IRQ status: %d\n", 5097 ret); 5098 goto exit; 5099 } 5100 5101 irq_fired = false; 5102 for (i = 0; i < RT5677_IRQ_NUM; i++) { 5103 if (reg_irq & rt5677_irq_descs[i].status_mask) { 5104 irq_fired = true; 5105 virq = irq_find_mapping(rt5677->domain, i); 5106 if (virq) 5107 handle_nested_irq(virq); 5108 5109 /* Clear the interrupt by flipping the polarity 5110 * of the interrupt source line that fired 5111 */ 5112 reg_irq ^= rt5677_irq_descs[i].polarity_mask; 5113 } 5114 } 5115 if (!irq_fired) 5116 goto exit; 5117 5118 ret = regmap_write(rt5677->regmap, RT5677_IRQ_CTRL1, reg_irq); 5119 if (ret) { 5120 dev_err(rt5677->dev, "failed updating IRQ status: %d\n", 5121 ret); 5122 goto exit; 5123 } 5124 } 5125 exit: 5126 mutex_unlock(&rt5677->irq_lock); 5127 if (irq_fired) 5128 return IRQ_HANDLED; 5129 else 5130 return IRQ_NONE; 5131 } 5132 5133 static void rt5677_irq_bus_lock(struct irq_data *data) 5134 { 5135 struct rt5677_priv *rt5677 = irq_data_get_irq_chip_data(data); 5136 5137 mutex_lock(&rt5677->irq_lock); 5138 } 5139 5140 static void rt5677_irq_bus_sync_unlock(struct irq_data *data) 5141 { 5142 struct rt5677_priv *rt5677 = irq_data_get_irq_chip_data(data); 5143 5144 // Set the enable/disable bits for the jack detect IRQs. 5145 regmap_update_bits(rt5677->regmap, RT5677_IRQ_CTRL1, 5146 RT5677_EN_IRQ_GPIO_JD1 | RT5677_EN_IRQ_GPIO_JD2 | 5147 RT5677_EN_IRQ_GPIO_JD3, rt5677->irq_en); 5148 mutex_unlock(&rt5677->irq_lock); 5149 } 5150 5151 static void rt5677_irq_enable(struct irq_data *data) 5152 { 5153 struct rt5677_priv *rt5677 = irq_data_get_irq_chip_data(data); 5154 5155 rt5677->irq_en |= rt5677_irq_descs[data->hwirq].enable_mask; 5156 } 5157 5158 static void rt5677_irq_disable(struct irq_data *data) 5159 { 5160 struct rt5677_priv *rt5677 = irq_data_get_irq_chip_data(data); 5161 5162 rt5677->irq_en &= ~rt5677_irq_descs[data->hwirq].enable_mask; 5163 } 5164 5165 static struct irq_chip rt5677_irq_chip = { 5166 .name = "rt5677_irq_chip", 5167 .irq_bus_lock = rt5677_irq_bus_lock, 5168 .irq_bus_sync_unlock = rt5677_irq_bus_sync_unlock, 5169 .irq_disable = rt5677_irq_disable, 5170 .irq_enable = rt5677_irq_enable, 5171 }; 5172 5173 static int rt5677_irq_map(struct irq_domain *h, unsigned int virq, 5174 irq_hw_number_t hw) 5175 { 5176 struct rt5677_priv *rt5677 = h->host_data; 5177 5178 irq_set_chip_data(virq, rt5677); 5179 irq_set_chip(virq, &rt5677_irq_chip); 5180 irq_set_nested_thread(virq, 1); 5181 irq_set_noprobe(virq); 5182 return 0; 5183 } 5184 5185 5186 static const struct irq_domain_ops rt5677_domain_ops = { 5187 .map = rt5677_irq_map, 5188 .xlate = irq_domain_xlate_twocell, 5189 }; 5190 5191 static int rt5677_init_irq(struct i2c_client *i2c) 5192 { 5193 int ret; 5194 struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c); 5195 unsigned int jd_mask = 0, jd_val = 0; 5196 5197 if (!rt5677->pdata.jd1_gpio && 5198 !rt5677->pdata.jd2_gpio && 5199 !rt5677->pdata.jd3_gpio) 5200 return 0; 5201 5202 if (!i2c->irq) { 5203 dev_err(&i2c->dev, "No interrupt specified\n"); 5204 return -EINVAL; 5205 } 5206 5207 mutex_init(&rt5677->irq_lock); 5208 5209 /* 5210 * Select RC as the debounce clock so that GPIO works even when 5211 * MCLK is gated which happens when there is no audio stream 5212 * (SND_SOC_BIAS_OFF). 5213 */ 5214 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 5215 RT5677_IRQ_DEBOUNCE_SEL_MASK, 5216 RT5677_IRQ_DEBOUNCE_SEL_RC); 5217 /* Enable auto power on RC when GPIO states are changed */ 5218 regmap_update_bits(rt5677->regmap, RT5677_GEN_CTRL1, 0xff, 0xff); 5219 5220 /* Select and enable jack detection sources per platform data */ 5221 if (rt5677->pdata.jd1_gpio) { 5222 jd_mask |= RT5677_SEL_GPIO_JD1_MASK; 5223 jd_val |= rt5677->pdata.jd1_gpio << RT5677_SEL_GPIO_JD1_SFT; 5224 } 5225 if (rt5677->pdata.jd2_gpio) { 5226 jd_mask |= RT5677_SEL_GPIO_JD2_MASK; 5227 jd_val |= rt5677->pdata.jd2_gpio << RT5677_SEL_GPIO_JD2_SFT; 5228 } 5229 if (rt5677->pdata.jd3_gpio) { 5230 jd_mask |= RT5677_SEL_GPIO_JD3_MASK; 5231 jd_val |= rt5677->pdata.jd3_gpio << RT5677_SEL_GPIO_JD3_SFT; 5232 } 5233 regmap_update_bits(rt5677->regmap, RT5677_JD_CTRL1, jd_mask, jd_val); 5234 5235 /* Set GPIO1 pin to be IRQ output */ 5236 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL1, 5237 RT5677_GPIO1_PIN_MASK, RT5677_GPIO1_PIN_IRQ); 5238 5239 /* Ready to listen for interrupts */ 5240 rt5677->domain = irq_domain_add_linear(i2c->dev.of_node, 5241 RT5677_IRQ_NUM, &rt5677_domain_ops, rt5677); 5242 if (!rt5677->domain) { 5243 dev_err(&i2c->dev, "Failed to create IRQ domain\n"); 5244 return -ENOMEM; 5245 } 5246 5247 ret = devm_request_threaded_irq(&i2c->dev, i2c->irq, NULL, rt5677_irq, 5248 IRQF_TRIGGER_RISING | IRQF_ONESHOT, 5249 "rt5677", rt5677); 5250 if (ret) 5251 dev_err(&i2c->dev, "Failed to request IRQ: %d\n", ret); 5252 5253 return ret; 5254 } 5255 5256 static int rt5677_i2c_probe(struct i2c_client *i2c) 5257 { 5258 struct rt5677_priv *rt5677; 5259 int ret; 5260 unsigned int val; 5261 5262 rt5677 = devm_kzalloc(&i2c->dev, sizeof(struct rt5677_priv), 5263 GFP_KERNEL); 5264 if (rt5677 == NULL) 5265 return -ENOMEM; 5266 5267 rt5677->dev = &i2c->dev; 5268 i2c_set_clientdata(i2c, rt5677); 5269 5270 if (i2c->dev.of_node) { 5271 const struct of_device_id *match_id; 5272 5273 match_id = of_match_device(rt5677_of_match, &i2c->dev); 5274 if (match_id) 5275 rt5677->type = (enum rt5677_type)match_id->data; 5276 } else if (ACPI_HANDLE(&i2c->dev)) { 5277 const struct acpi_device_id *acpi_id; 5278 5279 acpi_id = acpi_match_device(rt5677_acpi_match, &i2c->dev); 5280 if (acpi_id) 5281 rt5677->type = (enum rt5677_type)acpi_id->driver_data; 5282 } else { 5283 return -EINVAL; 5284 } 5285 5286 rt5677_read_device_properties(rt5677, &i2c->dev); 5287 5288 /* pow-ldo2 and reset are optional. The codec pins may be statically 5289 * connected on the board without gpios. If the gpio device property 5290 * isn't specified, devm_gpiod_get_optional returns NULL. 5291 */ 5292 rt5677->pow_ldo2 = devm_gpiod_get_optional(&i2c->dev, 5293 "realtek,pow-ldo2", GPIOD_OUT_HIGH); 5294 if (IS_ERR(rt5677->pow_ldo2)) { 5295 ret = PTR_ERR(rt5677->pow_ldo2); 5296 dev_err(&i2c->dev, "Failed to request POW_LDO2: %d\n", ret); 5297 return ret; 5298 } 5299 rt5677->reset_pin = devm_gpiod_get_optional(&i2c->dev, 5300 "realtek,reset", GPIOD_OUT_LOW); 5301 if (IS_ERR(rt5677->reset_pin)) { 5302 ret = PTR_ERR(rt5677->reset_pin); 5303 dev_err(&i2c->dev, "Failed to request RESET: %d\n", ret); 5304 return ret; 5305 } 5306 5307 if (rt5677->pow_ldo2 || rt5677->reset_pin) { 5308 /* Wait a while until I2C bus becomes available. The datasheet 5309 * does not specify the exact we should wait but startup 5310 * sequence mentiones at least a few milliseconds. 5311 */ 5312 msleep(10); 5313 } 5314 5315 rt5677->regmap_physical = devm_regmap_init_i2c(i2c, 5316 &rt5677_regmap_physical); 5317 if (IS_ERR(rt5677->regmap_physical)) { 5318 ret = PTR_ERR(rt5677->regmap_physical); 5319 dev_err(&i2c->dev, "Failed to allocate register map: %d\n", 5320 ret); 5321 return ret; 5322 } 5323 5324 rt5677->regmap = devm_regmap_init(&i2c->dev, NULL, i2c, &rt5677_regmap); 5325 if (IS_ERR(rt5677->regmap)) { 5326 ret = PTR_ERR(rt5677->regmap); 5327 dev_err(&i2c->dev, "Failed to allocate register map: %d\n", 5328 ret); 5329 return ret; 5330 } 5331 5332 regmap_read(rt5677->regmap, RT5677_VENDOR_ID2, &val); 5333 if (val != RT5677_DEVICE_ID) { 5334 dev_err(&i2c->dev, 5335 "Device with ID register %#x is not rt5677\n", val); 5336 return -ENODEV; 5337 } 5338 5339 regmap_write(rt5677->regmap, RT5677_RESET, 0x10ec); 5340 5341 ret = regmap_register_patch(rt5677->regmap, init_list, 5342 ARRAY_SIZE(init_list)); 5343 if (ret != 0) 5344 dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret); 5345 5346 if (rt5677->pdata.in1_diff) 5347 regmap_update_bits(rt5677->regmap, RT5677_IN1, 5348 RT5677_IN_DF1, RT5677_IN_DF1); 5349 5350 if (rt5677->pdata.in2_diff) 5351 regmap_update_bits(rt5677->regmap, RT5677_IN1, 5352 RT5677_IN_DF2, RT5677_IN_DF2); 5353 5354 if (rt5677->pdata.lout1_diff) 5355 regmap_update_bits(rt5677->regmap, RT5677_LOUT1, 5356 RT5677_LOUT1_L_DF, RT5677_LOUT1_L_DF); 5357 5358 if (rt5677->pdata.lout2_diff) 5359 regmap_update_bits(rt5677->regmap, RT5677_LOUT1, 5360 RT5677_LOUT2_L_DF, RT5677_LOUT2_L_DF); 5361 5362 if (rt5677->pdata.lout3_diff) 5363 regmap_update_bits(rt5677->regmap, RT5677_LOUT1, 5364 RT5677_LOUT3_L_DF, RT5677_LOUT3_L_DF); 5365 5366 if (rt5677->pdata.dmic2_clk_pin == RT5677_DMIC_CLK2) { 5367 regmap_update_bits(rt5677->regmap, RT5677_GEN_CTRL2, 5368 RT5677_GPIO5_FUNC_MASK, 5369 RT5677_GPIO5_FUNC_DMIC); 5370 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2, 5371 RT5677_GPIO5_DIR_MASK, 5372 RT5677_GPIO5_DIR_OUT); 5373 } 5374 5375 if (rt5677->pdata.micbias1_vdd_3v3) 5376 regmap_update_bits(rt5677->regmap, RT5677_MICBIAS, 5377 RT5677_MICBIAS1_CTRL_VDD_MASK, 5378 RT5677_MICBIAS1_CTRL_VDD_3_3V); 5379 5380 rt5677_init_gpio(i2c); 5381 ret = rt5677_init_irq(i2c); 5382 if (ret) 5383 dev_err(&i2c->dev, "Failed to initialize irq: %d\n", ret); 5384 5385 return devm_snd_soc_register_component(&i2c->dev, 5386 &soc_component_dev_rt5677, 5387 rt5677_dai, ARRAY_SIZE(rt5677_dai)); 5388 } 5389 5390 static int rt5677_i2c_remove(struct i2c_client *i2c) 5391 { 5392 rt5677_free_gpio(i2c); 5393 5394 return 0; 5395 } 5396 5397 static struct i2c_driver rt5677_i2c_driver = { 5398 .driver = { 5399 .name = RT5677_DRV_NAME, 5400 .of_match_table = rt5677_of_match, 5401 .acpi_match_table = ACPI_PTR(rt5677_acpi_match), 5402 }, 5403 .probe_new = rt5677_i2c_probe, 5404 .remove = rt5677_i2c_remove, 5405 }; 5406 module_i2c_driver(rt5677_i2c_driver); 5407 5408 MODULE_DESCRIPTION("ASoC RT5677 driver"); 5409 MODULE_AUTHOR("Oder Chiou <oder_chiou@realtek.com>"); 5410 MODULE_LICENSE("GPL v2"); 5411