1 /* 2 * rt5677.c -- RT5677 ALSA SoC audio codec driver 3 * 4 * Copyright 2013 Realtek Semiconductor Corp. 5 * Author: Oder Chiou <oder_chiou@realtek.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11 12 #include <linux/fs.h> 13 #include <linux/module.h> 14 #include <linux/moduleparam.h> 15 #include <linux/init.h> 16 #include <linux/delay.h> 17 #include <linux/pm.h> 18 #include <linux/of_gpio.h> 19 #include <linux/regmap.h> 20 #include <linux/i2c.h> 21 #include <linux/platform_device.h> 22 #include <linux/spi/spi.h> 23 #include <linux/firmware.h> 24 #include <linux/gpio.h> 25 #include <sound/core.h> 26 #include <sound/pcm.h> 27 #include <sound/pcm_params.h> 28 #include <sound/soc.h> 29 #include <sound/soc-dapm.h> 30 #include <sound/initval.h> 31 #include <sound/tlv.h> 32 33 #include "rl6231.h" 34 #include "rt5677.h" 35 #include "rt5677-spi.h" 36 37 #define RT5677_DEVICE_ID 0x6327 38 39 #define RT5677_PR_RANGE_BASE (0xff + 1) 40 #define RT5677_PR_SPACING 0x100 41 42 #define RT5677_PR_BASE (RT5677_PR_RANGE_BASE + (0 * RT5677_PR_SPACING)) 43 44 static const struct regmap_range_cfg rt5677_ranges[] = { 45 { 46 .name = "PR", 47 .range_min = RT5677_PR_BASE, 48 .range_max = RT5677_PR_BASE + 0xfd, 49 .selector_reg = RT5677_PRIV_INDEX, 50 .selector_mask = 0xff, 51 .selector_shift = 0x0, 52 .window_start = RT5677_PRIV_DATA, 53 .window_len = 0x1, 54 }, 55 }; 56 57 static const struct reg_default init_list[] = { 58 {RT5677_ASRC_12, 0x0018}, 59 {RT5677_PR_BASE + 0x3d, 0x364d}, 60 {RT5677_PR_BASE + 0x17, 0x4fc0}, 61 {RT5677_PR_BASE + 0x13, 0x0312}, 62 {RT5677_PR_BASE + 0x1e, 0x0000}, 63 {RT5677_PR_BASE + 0x12, 0x0eaa}, 64 {RT5677_PR_BASE + 0x14, 0x018a}, 65 }; 66 #define RT5677_INIT_REG_LEN ARRAY_SIZE(init_list) 67 68 static const struct reg_default rt5677_reg[] = { 69 {RT5677_RESET , 0x0000}, 70 {RT5677_LOUT1 , 0xa800}, 71 {RT5677_IN1 , 0x0000}, 72 {RT5677_MICBIAS , 0x0000}, 73 {RT5677_SLIMBUS_PARAM , 0x0000}, 74 {RT5677_SLIMBUS_RX , 0x0000}, 75 {RT5677_SLIMBUS_CTRL , 0x0000}, 76 {RT5677_SIDETONE_CTRL , 0x000b}, 77 {RT5677_ANA_DAC1_2_3_SRC , 0x0000}, 78 {RT5677_IF_DSP_DAC3_4_MIXER , 0x1111}, 79 {RT5677_DAC4_DIG_VOL , 0xafaf}, 80 {RT5677_DAC3_DIG_VOL , 0xafaf}, 81 {RT5677_DAC1_DIG_VOL , 0xafaf}, 82 {RT5677_DAC2_DIG_VOL , 0xafaf}, 83 {RT5677_IF_DSP_DAC2_MIXER , 0x0011}, 84 {RT5677_STO1_ADC_DIG_VOL , 0x2f2f}, 85 {RT5677_MONO_ADC_DIG_VOL , 0x2f2f}, 86 {RT5677_STO1_2_ADC_BST , 0x0000}, 87 {RT5677_STO2_ADC_DIG_VOL , 0x2f2f}, 88 {RT5677_ADC_BST_CTRL2 , 0x0000}, 89 {RT5677_STO3_4_ADC_BST , 0x0000}, 90 {RT5677_STO3_ADC_DIG_VOL , 0x2f2f}, 91 {RT5677_STO4_ADC_DIG_VOL , 0x2f2f}, 92 {RT5677_STO4_ADC_MIXER , 0xd4c0}, 93 {RT5677_STO3_ADC_MIXER , 0xd4c0}, 94 {RT5677_STO2_ADC_MIXER , 0xd4c0}, 95 {RT5677_STO1_ADC_MIXER , 0xd4c0}, 96 {RT5677_MONO_ADC_MIXER , 0xd4d1}, 97 {RT5677_ADC_IF_DSP_DAC1_MIXER , 0x8080}, 98 {RT5677_STO1_DAC_MIXER , 0xaaaa}, 99 {RT5677_MONO_DAC_MIXER , 0xaaaa}, 100 {RT5677_DD1_MIXER , 0xaaaa}, 101 {RT5677_DD2_MIXER , 0xaaaa}, 102 {RT5677_IF3_DATA , 0x0000}, 103 {RT5677_IF4_DATA , 0x0000}, 104 {RT5677_PDM_OUT_CTRL , 0x8888}, 105 {RT5677_PDM_DATA_CTRL1 , 0x0000}, 106 {RT5677_PDM_DATA_CTRL2 , 0x0000}, 107 {RT5677_PDM1_DATA_CTRL2 , 0x0000}, 108 {RT5677_PDM1_DATA_CTRL3 , 0x0000}, 109 {RT5677_PDM1_DATA_CTRL4 , 0x0000}, 110 {RT5677_PDM2_DATA_CTRL2 , 0x0000}, 111 {RT5677_PDM2_DATA_CTRL3 , 0x0000}, 112 {RT5677_PDM2_DATA_CTRL4 , 0x0000}, 113 {RT5677_TDM1_CTRL1 , 0x0300}, 114 {RT5677_TDM1_CTRL2 , 0x0000}, 115 {RT5677_TDM1_CTRL3 , 0x4000}, 116 {RT5677_TDM1_CTRL4 , 0x0123}, 117 {RT5677_TDM1_CTRL5 , 0x4567}, 118 {RT5677_TDM2_CTRL1 , 0x0300}, 119 {RT5677_TDM2_CTRL2 , 0x0000}, 120 {RT5677_TDM2_CTRL3 , 0x4000}, 121 {RT5677_TDM2_CTRL4 , 0x0123}, 122 {RT5677_TDM2_CTRL5 , 0x4567}, 123 {RT5677_I2C_MASTER_CTRL1 , 0x0001}, 124 {RT5677_I2C_MASTER_CTRL2 , 0x0000}, 125 {RT5677_I2C_MASTER_CTRL3 , 0x0000}, 126 {RT5677_I2C_MASTER_CTRL4 , 0x0000}, 127 {RT5677_I2C_MASTER_CTRL5 , 0x0000}, 128 {RT5677_I2C_MASTER_CTRL6 , 0x0000}, 129 {RT5677_I2C_MASTER_CTRL7 , 0x0000}, 130 {RT5677_I2C_MASTER_CTRL8 , 0x0000}, 131 {RT5677_DMIC_CTRL1 , 0x1505}, 132 {RT5677_DMIC_CTRL2 , 0x0055}, 133 {RT5677_HAP_GENE_CTRL1 , 0x0111}, 134 {RT5677_HAP_GENE_CTRL2 , 0x0064}, 135 {RT5677_HAP_GENE_CTRL3 , 0xef0e}, 136 {RT5677_HAP_GENE_CTRL4 , 0xf0f0}, 137 {RT5677_HAP_GENE_CTRL5 , 0xef0e}, 138 {RT5677_HAP_GENE_CTRL6 , 0xf0f0}, 139 {RT5677_HAP_GENE_CTRL7 , 0xef0e}, 140 {RT5677_HAP_GENE_CTRL8 , 0xf0f0}, 141 {RT5677_HAP_GENE_CTRL9 , 0xf000}, 142 {RT5677_HAP_GENE_CTRL10 , 0x0000}, 143 {RT5677_PWR_DIG1 , 0x0000}, 144 {RT5677_PWR_DIG2 , 0x0000}, 145 {RT5677_PWR_ANLG1 , 0x0055}, 146 {RT5677_PWR_ANLG2 , 0x0000}, 147 {RT5677_PWR_DSP1 , 0x0001}, 148 {RT5677_PWR_DSP_ST , 0x0000}, 149 {RT5677_PWR_DSP2 , 0x0000}, 150 {RT5677_ADC_DAC_HPF_CTRL1 , 0x0e00}, 151 {RT5677_PRIV_INDEX , 0x0000}, 152 {RT5677_PRIV_DATA , 0x0000}, 153 {RT5677_I2S4_SDP , 0x8000}, 154 {RT5677_I2S1_SDP , 0x8000}, 155 {RT5677_I2S2_SDP , 0x8000}, 156 {RT5677_I2S3_SDP , 0x8000}, 157 {RT5677_CLK_TREE_CTRL1 , 0x1111}, 158 {RT5677_CLK_TREE_CTRL2 , 0x1111}, 159 {RT5677_CLK_TREE_CTRL3 , 0x0000}, 160 {RT5677_PLL1_CTRL1 , 0x0000}, 161 {RT5677_PLL1_CTRL2 , 0x0000}, 162 {RT5677_PLL2_CTRL1 , 0x0c60}, 163 {RT5677_PLL2_CTRL2 , 0x2000}, 164 {RT5677_GLB_CLK1 , 0x0000}, 165 {RT5677_GLB_CLK2 , 0x0000}, 166 {RT5677_ASRC_1 , 0x0000}, 167 {RT5677_ASRC_2 , 0x0000}, 168 {RT5677_ASRC_3 , 0x0000}, 169 {RT5677_ASRC_4 , 0x0000}, 170 {RT5677_ASRC_5 , 0x0000}, 171 {RT5677_ASRC_6 , 0x0000}, 172 {RT5677_ASRC_7 , 0x0000}, 173 {RT5677_ASRC_8 , 0x0000}, 174 {RT5677_ASRC_9 , 0x0000}, 175 {RT5677_ASRC_10 , 0x0000}, 176 {RT5677_ASRC_11 , 0x0000}, 177 {RT5677_ASRC_12 , 0x0018}, 178 {RT5677_ASRC_13 , 0x0000}, 179 {RT5677_ASRC_14 , 0x0000}, 180 {RT5677_ASRC_15 , 0x0000}, 181 {RT5677_ASRC_16 , 0x0000}, 182 {RT5677_ASRC_17 , 0x0000}, 183 {RT5677_ASRC_18 , 0x0000}, 184 {RT5677_ASRC_19 , 0x0000}, 185 {RT5677_ASRC_20 , 0x0000}, 186 {RT5677_ASRC_21 , 0x000c}, 187 {RT5677_ASRC_22 , 0x0000}, 188 {RT5677_ASRC_23 , 0x0000}, 189 {RT5677_VAD_CTRL1 , 0x2184}, 190 {RT5677_VAD_CTRL2 , 0x010a}, 191 {RT5677_VAD_CTRL3 , 0x0aea}, 192 {RT5677_VAD_CTRL4 , 0x000c}, 193 {RT5677_VAD_CTRL5 , 0x0000}, 194 {RT5677_DSP_INB_CTRL1 , 0x0000}, 195 {RT5677_DSP_INB_CTRL2 , 0x0000}, 196 {RT5677_DSP_IN_OUTB_CTRL , 0x0000}, 197 {RT5677_DSP_OUTB0_1_DIG_VOL , 0x2f2f}, 198 {RT5677_DSP_OUTB2_3_DIG_VOL , 0x2f2f}, 199 {RT5677_DSP_OUTB4_5_DIG_VOL , 0x2f2f}, 200 {RT5677_DSP_OUTB6_7_DIG_VOL , 0x2f2f}, 201 {RT5677_ADC_EQ_CTRL1 , 0x6000}, 202 {RT5677_ADC_EQ_CTRL2 , 0x0000}, 203 {RT5677_EQ_CTRL1 , 0xc000}, 204 {RT5677_EQ_CTRL2 , 0x0000}, 205 {RT5677_EQ_CTRL3 , 0x0000}, 206 {RT5677_SOFT_VOL_ZERO_CROSS1 , 0x0009}, 207 {RT5677_JD_CTRL1 , 0x0000}, 208 {RT5677_JD_CTRL2 , 0x0000}, 209 {RT5677_JD_CTRL3 , 0x0000}, 210 {RT5677_IRQ_CTRL1 , 0x0000}, 211 {RT5677_IRQ_CTRL2 , 0x0000}, 212 {RT5677_GPIO_ST , 0x0000}, 213 {RT5677_GPIO_CTRL1 , 0x0000}, 214 {RT5677_GPIO_CTRL2 , 0x0000}, 215 {RT5677_GPIO_CTRL3 , 0x0000}, 216 {RT5677_STO1_ADC_HI_FILTER1 , 0xb320}, 217 {RT5677_STO1_ADC_HI_FILTER2 , 0x0000}, 218 {RT5677_MONO_ADC_HI_FILTER1 , 0xb300}, 219 {RT5677_MONO_ADC_HI_FILTER2 , 0x0000}, 220 {RT5677_STO2_ADC_HI_FILTER1 , 0xb300}, 221 {RT5677_STO2_ADC_HI_FILTER2 , 0x0000}, 222 {RT5677_STO3_ADC_HI_FILTER1 , 0xb300}, 223 {RT5677_STO3_ADC_HI_FILTER2 , 0x0000}, 224 {RT5677_STO4_ADC_HI_FILTER1 , 0xb300}, 225 {RT5677_STO4_ADC_HI_FILTER2 , 0x0000}, 226 {RT5677_MB_DRC_CTRL1 , 0x0f20}, 227 {RT5677_DRC1_CTRL1 , 0x001f}, 228 {RT5677_DRC1_CTRL2 , 0x020c}, 229 {RT5677_DRC1_CTRL3 , 0x1f00}, 230 {RT5677_DRC1_CTRL4 , 0x0000}, 231 {RT5677_DRC1_CTRL5 , 0x0000}, 232 {RT5677_DRC1_CTRL6 , 0x0029}, 233 {RT5677_DRC2_CTRL1 , 0x001f}, 234 {RT5677_DRC2_CTRL2 , 0x020c}, 235 {RT5677_DRC2_CTRL3 , 0x1f00}, 236 {RT5677_DRC2_CTRL4 , 0x0000}, 237 {RT5677_DRC2_CTRL5 , 0x0000}, 238 {RT5677_DRC2_CTRL6 , 0x0029}, 239 {RT5677_DRC1_HL_CTRL1 , 0x8000}, 240 {RT5677_DRC1_HL_CTRL2 , 0x0200}, 241 {RT5677_DRC2_HL_CTRL1 , 0x8000}, 242 {RT5677_DRC2_HL_CTRL2 , 0x0200}, 243 {RT5677_DSP_INB1_SRC_CTRL1 , 0x5800}, 244 {RT5677_DSP_INB1_SRC_CTRL2 , 0x0000}, 245 {RT5677_DSP_INB1_SRC_CTRL3 , 0x0000}, 246 {RT5677_DSP_INB1_SRC_CTRL4 , 0x0800}, 247 {RT5677_DSP_INB2_SRC_CTRL1 , 0x5800}, 248 {RT5677_DSP_INB2_SRC_CTRL2 , 0x0000}, 249 {RT5677_DSP_INB2_SRC_CTRL3 , 0x0000}, 250 {RT5677_DSP_INB2_SRC_CTRL4 , 0x0800}, 251 {RT5677_DSP_INB3_SRC_CTRL1 , 0x5800}, 252 {RT5677_DSP_INB3_SRC_CTRL2 , 0x0000}, 253 {RT5677_DSP_INB3_SRC_CTRL3 , 0x0000}, 254 {RT5677_DSP_INB3_SRC_CTRL4 , 0x0800}, 255 {RT5677_DSP_OUTB1_SRC_CTRL1 , 0x5800}, 256 {RT5677_DSP_OUTB1_SRC_CTRL2 , 0x0000}, 257 {RT5677_DSP_OUTB1_SRC_CTRL3 , 0x0000}, 258 {RT5677_DSP_OUTB1_SRC_CTRL4 , 0x0800}, 259 {RT5677_DSP_OUTB2_SRC_CTRL1 , 0x5800}, 260 {RT5677_DSP_OUTB2_SRC_CTRL2 , 0x0000}, 261 {RT5677_DSP_OUTB2_SRC_CTRL3 , 0x0000}, 262 {RT5677_DSP_OUTB2_SRC_CTRL4 , 0x0800}, 263 {RT5677_DSP_OUTB_0123_MIXER_CTRL, 0xfefe}, 264 {RT5677_DSP_OUTB_45_MIXER_CTRL , 0xfefe}, 265 {RT5677_DSP_OUTB_67_MIXER_CTRL , 0xfefe}, 266 {RT5677_DIG_MISC , 0x0000}, 267 {RT5677_GEN_CTRL1 , 0x0000}, 268 {RT5677_GEN_CTRL2 , 0x0000}, 269 {RT5677_VENDOR_ID , 0x0000}, 270 {RT5677_VENDOR_ID1 , 0x10ec}, 271 {RT5677_VENDOR_ID2 , 0x6327}, 272 }; 273 274 static bool rt5677_volatile_register(struct device *dev, unsigned int reg) 275 { 276 int i; 277 278 for (i = 0; i < ARRAY_SIZE(rt5677_ranges); i++) { 279 if (reg >= rt5677_ranges[i].range_min && 280 reg <= rt5677_ranges[i].range_max) { 281 return true; 282 } 283 } 284 285 switch (reg) { 286 case RT5677_RESET: 287 case RT5677_SLIMBUS_PARAM: 288 case RT5677_PDM_DATA_CTRL1: 289 case RT5677_PDM_DATA_CTRL2: 290 case RT5677_PDM1_DATA_CTRL4: 291 case RT5677_PDM2_DATA_CTRL4: 292 case RT5677_I2C_MASTER_CTRL1: 293 case RT5677_I2C_MASTER_CTRL7: 294 case RT5677_I2C_MASTER_CTRL8: 295 case RT5677_HAP_GENE_CTRL2: 296 case RT5677_PWR_DSP_ST: 297 case RT5677_PRIV_DATA: 298 case RT5677_PLL1_CTRL2: 299 case RT5677_PLL2_CTRL2: 300 case RT5677_ASRC_22: 301 case RT5677_ASRC_23: 302 case RT5677_VAD_CTRL5: 303 case RT5677_ADC_EQ_CTRL1: 304 case RT5677_EQ_CTRL1: 305 case RT5677_IRQ_CTRL1: 306 case RT5677_IRQ_CTRL2: 307 case RT5677_GPIO_ST: 308 case RT5677_DSP_INB1_SRC_CTRL4: 309 case RT5677_DSP_INB2_SRC_CTRL4: 310 case RT5677_DSP_INB3_SRC_CTRL4: 311 case RT5677_DSP_OUTB1_SRC_CTRL4: 312 case RT5677_DSP_OUTB2_SRC_CTRL4: 313 case RT5677_VENDOR_ID: 314 case RT5677_VENDOR_ID1: 315 case RT5677_VENDOR_ID2: 316 return true; 317 default: 318 return false; 319 } 320 } 321 322 static bool rt5677_readable_register(struct device *dev, unsigned int reg) 323 { 324 int i; 325 326 for (i = 0; i < ARRAY_SIZE(rt5677_ranges); i++) { 327 if (reg >= rt5677_ranges[i].range_min && 328 reg <= rt5677_ranges[i].range_max) { 329 return true; 330 } 331 } 332 333 switch (reg) { 334 case RT5677_RESET: 335 case RT5677_LOUT1: 336 case RT5677_IN1: 337 case RT5677_MICBIAS: 338 case RT5677_SLIMBUS_PARAM: 339 case RT5677_SLIMBUS_RX: 340 case RT5677_SLIMBUS_CTRL: 341 case RT5677_SIDETONE_CTRL: 342 case RT5677_ANA_DAC1_2_3_SRC: 343 case RT5677_IF_DSP_DAC3_4_MIXER: 344 case RT5677_DAC4_DIG_VOL: 345 case RT5677_DAC3_DIG_VOL: 346 case RT5677_DAC1_DIG_VOL: 347 case RT5677_DAC2_DIG_VOL: 348 case RT5677_IF_DSP_DAC2_MIXER: 349 case RT5677_STO1_ADC_DIG_VOL: 350 case RT5677_MONO_ADC_DIG_VOL: 351 case RT5677_STO1_2_ADC_BST: 352 case RT5677_STO2_ADC_DIG_VOL: 353 case RT5677_ADC_BST_CTRL2: 354 case RT5677_STO3_4_ADC_BST: 355 case RT5677_STO3_ADC_DIG_VOL: 356 case RT5677_STO4_ADC_DIG_VOL: 357 case RT5677_STO4_ADC_MIXER: 358 case RT5677_STO3_ADC_MIXER: 359 case RT5677_STO2_ADC_MIXER: 360 case RT5677_STO1_ADC_MIXER: 361 case RT5677_MONO_ADC_MIXER: 362 case RT5677_ADC_IF_DSP_DAC1_MIXER: 363 case RT5677_STO1_DAC_MIXER: 364 case RT5677_MONO_DAC_MIXER: 365 case RT5677_DD1_MIXER: 366 case RT5677_DD2_MIXER: 367 case RT5677_IF3_DATA: 368 case RT5677_IF4_DATA: 369 case RT5677_PDM_OUT_CTRL: 370 case RT5677_PDM_DATA_CTRL1: 371 case RT5677_PDM_DATA_CTRL2: 372 case RT5677_PDM1_DATA_CTRL2: 373 case RT5677_PDM1_DATA_CTRL3: 374 case RT5677_PDM1_DATA_CTRL4: 375 case RT5677_PDM2_DATA_CTRL2: 376 case RT5677_PDM2_DATA_CTRL3: 377 case RT5677_PDM2_DATA_CTRL4: 378 case RT5677_TDM1_CTRL1: 379 case RT5677_TDM1_CTRL2: 380 case RT5677_TDM1_CTRL3: 381 case RT5677_TDM1_CTRL4: 382 case RT5677_TDM1_CTRL5: 383 case RT5677_TDM2_CTRL1: 384 case RT5677_TDM2_CTRL2: 385 case RT5677_TDM2_CTRL3: 386 case RT5677_TDM2_CTRL4: 387 case RT5677_TDM2_CTRL5: 388 case RT5677_I2C_MASTER_CTRL1: 389 case RT5677_I2C_MASTER_CTRL2: 390 case RT5677_I2C_MASTER_CTRL3: 391 case RT5677_I2C_MASTER_CTRL4: 392 case RT5677_I2C_MASTER_CTRL5: 393 case RT5677_I2C_MASTER_CTRL6: 394 case RT5677_I2C_MASTER_CTRL7: 395 case RT5677_I2C_MASTER_CTRL8: 396 case RT5677_DMIC_CTRL1: 397 case RT5677_DMIC_CTRL2: 398 case RT5677_HAP_GENE_CTRL1: 399 case RT5677_HAP_GENE_CTRL2: 400 case RT5677_HAP_GENE_CTRL3: 401 case RT5677_HAP_GENE_CTRL4: 402 case RT5677_HAP_GENE_CTRL5: 403 case RT5677_HAP_GENE_CTRL6: 404 case RT5677_HAP_GENE_CTRL7: 405 case RT5677_HAP_GENE_CTRL8: 406 case RT5677_HAP_GENE_CTRL9: 407 case RT5677_HAP_GENE_CTRL10: 408 case RT5677_PWR_DIG1: 409 case RT5677_PWR_DIG2: 410 case RT5677_PWR_ANLG1: 411 case RT5677_PWR_ANLG2: 412 case RT5677_PWR_DSP1: 413 case RT5677_PWR_DSP_ST: 414 case RT5677_PWR_DSP2: 415 case RT5677_ADC_DAC_HPF_CTRL1: 416 case RT5677_PRIV_INDEX: 417 case RT5677_PRIV_DATA: 418 case RT5677_I2S4_SDP: 419 case RT5677_I2S1_SDP: 420 case RT5677_I2S2_SDP: 421 case RT5677_I2S3_SDP: 422 case RT5677_CLK_TREE_CTRL1: 423 case RT5677_CLK_TREE_CTRL2: 424 case RT5677_CLK_TREE_CTRL3: 425 case RT5677_PLL1_CTRL1: 426 case RT5677_PLL1_CTRL2: 427 case RT5677_PLL2_CTRL1: 428 case RT5677_PLL2_CTRL2: 429 case RT5677_GLB_CLK1: 430 case RT5677_GLB_CLK2: 431 case RT5677_ASRC_1: 432 case RT5677_ASRC_2: 433 case RT5677_ASRC_3: 434 case RT5677_ASRC_4: 435 case RT5677_ASRC_5: 436 case RT5677_ASRC_6: 437 case RT5677_ASRC_7: 438 case RT5677_ASRC_8: 439 case RT5677_ASRC_9: 440 case RT5677_ASRC_10: 441 case RT5677_ASRC_11: 442 case RT5677_ASRC_12: 443 case RT5677_ASRC_13: 444 case RT5677_ASRC_14: 445 case RT5677_ASRC_15: 446 case RT5677_ASRC_16: 447 case RT5677_ASRC_17: 448 case RT5677_ASRC_18: 449 case RT5677_ASRC_19: 450 case RT5677_ASRC_20: 451 case RT5677_ASRC_21: 452 case RT5677_ASRC_22: 453 case RT5677_ASRC_23: 454 case RT5677_VAD_CTRL1: 455 case RT5677_VAD_CTRL2: 456 case RT5677_VAD_CTRL3: 457 case RT5677_VAD_CTRL4: 458 case RT5677_VAD_CTRL5: 459 case RT5677_DSP_INB_CTRL1: 460 case RT5677_DSP_INB_CTRL2: 461 case RT5677_DSP_IN_OUTB_CTRL: 462 case RT5677_DSP_OUTB0_1_DIG_VOL: 463 case RT5677_DSP_OUTB2_3_DIG_VOL: 464 case RT5677_DSP_OUTB4_5_DIG_VOL: 465 case RT5677_DSP_OUTB6_7_DIG_VOL: 466 case RT5677_ADC_EQ_CTRL1: 467 case RT5677_ADC_EQ_CTRL2: 468 case RT5677_EQ_CTRL1: 469 case RT5677_EQ_CTRL2: 470 case RT5677_EQ_CTRL3: 471 case RT5677_SOFT_VOL_ZERO_CROSS1: 472 case RT5677_JD_CTRL1: 473 case RT5677_JD_CTRL2: 474 case RT5677_JD_CTRL3: 475 case RT5677_IRQ_CTRL1: 476 case RT5677_IRQ_CTRL2: 477 case RT5677_GPIO_ST: 478 case RT5677_GPIO_CTRL1: 479 case RT5677_GPIO_CTRL2: 480 case RT5677_GPIO_CTRL3: 481 case RT5677_STO1_ADC_HI_FILTER1: 482 case RT5677_STO1_ADC_HI_FILTER2: 483 case RT5677_MONO_ADC_HI_FILTER1: 484 case RT5677_MONO_ADC_HI_FILTER2: 485 case RT5677_STO2_ADC_HI_FILTER1: 486 case RT5677_STO2_ADC_HI_FILTER2: 487 case RT5677_STO3_ADC_HI_FILTER1: 488 case RT5677_STO3_ADC_HI_FILTER2: 489 case RT5677_STO4_ADC_HI_FILTER1: 490 case RT5677_STO4_ADC_HI_FILTER2: 491 case RT5677_MB_DRC_CTRL1: 492 case RT5677_DRC1_CTRL1: 493 case RT5677_DRC1_CTRL2: 494 case RT5677_DRC1_CTRL3: 495 case RT5677_DRC1_CTRL4: 496 case RT5677_DRC1_CTRL5: 497 case RT5677_DRC1_CTRL6: 498 case RT5677_DRC2_CTRL1: 499 case RT5677_DRC2_CTRL2: 500 case RT5677_DRC2_CTRL3: 501 case RT5677_DRC2_CTRL4: 502 case RT5677_DRC2_CTRL5: 503 case RT5677_DRC2_CTRL6: 504 case RT5677_DRC1_HL_CTRL1: 505 case RT5677_DRC1_HL_CTRL2: 506 case RT5677_DRC2_HL_CTRL1: 507 case RT5677_DRC2_HL_CTRL2: 508 case RT5677_DSP_INB1_SRC_CTRL1: 509 case RT5677_DSP_INB1_SRC_CTRL2: 510 case RT5677_DSP_INB1_SRC_CTRL3: 511 case RT5677_DSP_INB1_SRC_CTRL4: 512 case RT5677_DSP_INB2_SRC_CTRL1: 513 case RT5677_DSP_INB2_SRC_CTRL2: 514 case RT5677_DSP_INB2_SRC_CTRL3: 515 case RT5677_DSP_INB2_SRC_CTRL4: 516 case RT5677_DSP_INB3_SRC_CTRL1: 517 case RT5677_DSP_INB3_SRC_CTRL2: 518 case RT5677_DSP_INB3_SRC_CTRL3: 519 case RT5677_DSP_INB3_SRC_CTRL4: 520 case RT5677_DSP_OUTB1_SRC_CTRL1: 521 case RT5677_DSP_OUTB1_SRC_CTRL2: 522 case RT5677_DSP_OUTB1_SRC_CTRL3: 523 case RT5677_DSP_OUTB1_SRC_CTRL4: 524 case RT5677_DSP_OUTB2_SRC_CTRL1: 525 case RT5677_DSP_OUTB2_SRC_CTRL2: 526 case RT5677_DSP_OUTB2_SRC_CTRL3: 527 case RT5677_DSP_OUTB2_SRC_CTRL4: 528 case RT5677_DSP_OUTB_0123_MIXER_CTRL: 529 case RT5677_DSP_OUTB_45_MIXER_CTRL: 530 case RT5677_DSP_OUTB_67_MIXER_CTRL: 531 case RT5677_DIG_MISC: 532 case RT5677_GEN_CTRL1: 533 case RT5677_GEN_CTRL2: 534 case RT5677_VENDOR_ID: 535 case RT5677_VENDOR_ID1: 536 case RT5677_VENDOR_ID2: 537 return true; 538 default: 539 return false; 540 } 541 } 542 543 /** 544 * rt5677_dsp_mode_i2c_write_addr - Write value to address on DSP mode. 545 * @rt5677: Private Data. 546 * @addr: Address index. 547 * @value: Address data. 548 * 549 * 550 * Returns 0 for success or negative error code. 551 */ 552 static int rt5677_dsp_mode_i2c_write_addr(struct rt5677_priv *rt5677, 553 unsigned int addr, unsigned int value, unsigned int opcode) 554 { 555 struct snd_soc_codec *codec = rt5677->codec; 556 int ret; 557 558 mutex_lock(&rt5677->dsp_cmd_lock); 559 560 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_MSB, 561 addr >> 16); 562 if (ret < 0) { 563 dev_err(codec->dev, "Failed to set addr msb value: %d\n", ret); 564 goto err; 565 } 566 567 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_LSB, 568 addr & 0xffff); 569 if (ret < 0) { 570 dev_err(codec->dev, "Failed to set addr lsb value: %d\n", ret); 571 goto err; 572 } 573 574 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_MSB, 575 value >> 16); 576 if (ret < 0) { 577 dev_err(codec->dev, "Failed to set data msb value: %d\n", ret); 578 goto err; 579 } 580 581 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_LSB, 582 value & 0xffff); 583 if (ret < 0) { 584 dev_err(codec->dev, "Failed to set data lsb value: %d\n", ret); 585 goto err; 586 } 587 588 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_OP_CODE, 589 opcode); 590 if (ret < 0) { 591 dev_err(codec->dev, "Failed to set op code value: %d\n", ret); 592 goto err; 593 } 594 595 err: 596 mutex_unlock(&rt5677->dsp_cmd_lock); 597 598 return ret; 599 } 600 601 /** 602 * rt5677_dsp_mode_i2c_read_addr - Read value from address on DSP mode. 603 * rt5677: Private Data. 604 * @addr: Address index. 605 * @value: Address data. 606 * 607 * 608 * Returns 0 for success or negative error code. 609 */ 610 static int rt5677_dsp_mode_i2c_read_addr( 611 struct rt5677_priv *rt5677, unsigned int addr, unsigned int *value) 612 { 613 struct snd_soc_codec *codec = rt5677->codec; 614 int ret; 615 unsigned int msb, lsb; 616 617 mutex_lock(&rt5677->dsp_cmd_lock); 618 619 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_MSB, 620 addr >> 16); 621 if (ret < 0) { 622 dev_err(codec->dev, "Failed to set addr msb value: %d\n", ret); 623 goto err; 624 } 625 626 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_LSB, 627 addr & 0xffff); 628 if (ret < 0) { 629 dev_err(codec->dev, "Failed to set addr lsb value: %d\n", ret); 630 goto err; 631 } 632 633 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_OP_CODE, 634 0x0002); 635 if (ret < 0) { 636 dev_err(codec->dev, "Failed to set op code value: %d\n", ret); 637 goto err; 638 } 639 640 regmap_read(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_MSB, &msb); 641 regmap_read(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_LSB, &lsb); 642 *value = (msb << 16) | lsb; 643 644 err: 645 mutex_unlock(&rt5677->dsp_cmd_lock); 646 647 return ret; 648 } 649 650 /** 651 * rt5677_dsp_mode_i2c_write - Write register on DSP mode. 652 * rt5677: Private Data. 653 * @reg: Register index. 654 * @value: Register data. 655 * 656 * 657 * Returns 0 for success or negative error code. 658 */ 659 static int rt5677_dsp_mode_i2c_write(struct rt5677_priv *rt5677, 660 unsigned int reg, unsigned int value) 661 { 662 return rt5677_dsp_mode_i2c_write_addr(rt5677, 0x18020000 + reg * 2, 663 value, 0x0001); 664 } 665 666 /** 667 * rt5677_dsp_mode_i2c_read - Read register on DSP mode. 668 * @codec: SoC audio codec device. 669 * @reg: Register index. 670 * @value: Register data. 671 * 672 * 673 * Returns 0 for success or negative error code. 674 */ 675 static int rt5677_dsp_mode_i2c_read( 676 struct rt5677_priv *rt5677, unsigned int reg, unsigned int *value) 677 { 678 int ret = rt5677_dsp_mode_i2c_read_addr(rt5677, 0x18020000 + reg * 2, 679 value); 680 681 *value &= 0xffff; 682 683 return ret; 684 } 685 686 static void rt5677_set_dsp_mode(struct snd_soc_codec *codec, bool on) 687 { 688 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec); 689 690 if (on) { 691 regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, 0x2, 0x2); 692 rt5677->is_dsp_mode = true; 693 } else { 694 regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, 0x2, 0x0); 695 rt5677->is_dsp_mode = false; 696 } 697 } 698 699 static int rt5677_set_dsp_vad(struct snd_soc_codec *codec, bool on) 700 { 701 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec); 702 static bool activity; 703 int ret; 704 705 if (on && !activity) { 706 activity = true; 707 708 regcache_cache_only(rt5677->regmap, false); 709 regcache_cache_bypass(rt5677->regmap, true); 710 711 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x1, 0x1); 712 regmap_update_bits(rt5677->regmap, 713 RT5677_PR_BASE + RT5677_BIAS_CUR4, 0x0f00, 0x0f00); 714 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1, 715 RT5677_LDO1_SEL_MASK, 0x0); 716 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2, 717 RT5677_PWR_LDO1, RT5677_PWR_LDO1); 718 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1, 719 RT5677_MCLK_SRC_MASK, RT5677_MCLK2_SRC); 720 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK2, 721 RT5677_PLL2_PR_SRC_MASK | RT5677_DSP_CLK_SRC_MASK, 722 RT5677_PLL2_PR_SRC_MCLK2 | RT5677_DSP_CLK_SRC_BYPASS); 723 regmap_write(rt5677->regmap, RT5677_PWR_DSP2, 0x07ff); 724 regmap_write(rt5677->regmap, RT5677_PWR_DSP1, 0x07fd); 725 rt5677_set_dsp_mode(codec, true); 726 727 ret = request_firmware(&rt5677->fw1, RT5677_FIRMWARE1, 728 codec->dev); 729 if (ret == 0) { 730 rt5677_spi_burst_write(0x50000000, rt5677->fw1); 731 release_firmware(rt5677->fw1); 732 } 733 734 ret = request_firmware(&rt5677->fw2, RT5677_FIRMWARE2, 735 codec->dev); 736 if (ret == 0) { 737 rt5677_spi_burst_write(0x60000000, rt5677->fw2); 738 release_firmware(rt5677->fw2); 739 } 740 741 regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, 0x1, 0x0); 742 743 regcache_cache_bypass(rt5677->regmap, false); 744 regcache_cache_only(rt5677->regmap, true); 745 } else if (!on && activity) { 746 activity = false; 747 748 regcache_cache_only(rt5677->regmap, false); 749 regcache_cache_bypass(rt5677->regmap, true); 750 751 regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, 0x1, 0x1); 752 rt5677_set_dsp_mode(codec, false); 753 regmap_write(rt5677->regmap, RT5677_PWR_DSP1, 0x0001); 754 755 regmap_write(rt5677->regmap, RT5677_RESET, 0x10ec); 756 757 regcache_cache_bypass(rt5677->regmap, false); 758 regcache_mark_dirty(rt5677->regmap); 759 regcache_sync(rt5677->regmap); 760 } 761 762 return 0; 763 } 764 765 static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -4650, 150, 0); 766 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6525, 75, 0); 767 static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -3450, 150, 0); 768 static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0); 769 static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0); 770 static const DECLARE_TLV_DB_SCALE(st_vol_tlv, -4650, 150, 0); 771 772 /* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */ 773 static unsigned int bst_tlv[] = { 774 TLV_DB_RANGE_HEAD(7), 775 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0), 776 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0), 777 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0), 778 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0), 779 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0), 780 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0), 781 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0), 782 }; 783 784 static int rt5677_dsp_vad_get(struct snd_kcontrol *kcontrol, 785 struct snd_ctl_elem_value *ucontrol) 786 { 787 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 788 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component); 789 790 ucontrol->value.integer.value[0] = rt5677->dsp_vad_en; 791 792 return 0; 793 } 794 795 static int rt5677_dsp_vad_put(struct snd_kcontrol *kcontrol, 796 struct snd_ctl_elem_value *ucontrol) 797 { 798 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 799 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component); 800 struct snd_soc_codec *codec = snd_soc_component_to_codec(component); 801 802 rt5677->dsp_vad_en = !!ucontrol->value.integer.value[0]; 803 804 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) 805 rt5677_set_dsp_vad(codec, rt5677->dsp_vad_en); 806 807 return 0; 808 } 809 810 static const struct snd_kcontrol_new rt5677_snd_controls[] = { 811 /* OUTPUT Control */ 812 SOC_SINGLE("OUT1 Playback Switch", RT5677_LOUT1, 813 RT5677_LOUT1_L_MUTE_SFT, 1, 1), 814 SOC_SINGLE("OUT2 Playback Switch", RT5677_LOUT1, 815 RT5677_LOUT2_L_MUTE_SFT, 1, 1), 816 SOC_SINGLE("OUT3 Playback Switch", RT5677_LOUT1, 817 RT5677_LOUT3_L_MUTE_SFT, 1, 1), 818 819 /* DAC Digital Volume */ 820 SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5677_DAC1_DIG_VOL, 821 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 87, 0, dac_vol_tlv), 822 SOC_DOUBLE_TLV("DAC2 Playback Volume", RT5677_DAC2_DIG_VOL, 823 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 87, 0, dac_vol_tlv), 824 SOC_DOUBLE_TLV("DAC3 Playback Volume", RT5677_DAC3_DIG_VOL, 825 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 87, 0, dac_vol_tlv), 826 SOC_DOUBLE_TLV("DAC4 Playback Volume", RT5677_DAC4_DIG_VOL, 827 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 87, 0, dac_vol_tlv), 828 829 /* IN1/IN2 Control */ 830 SOC_SINGLE_TLV("IN1 Boost", RT5677_IN1, RT5677_BST_SFT1, 8, 0, bst_tlv), 831 SOC_SINGLE_TLV("IN2 Boost", RT5677_IN1, RT5677_BST_SFT2, 8, 0, bst_tlv), 832 833 /* ADC Digital Volume Control */ 834 SOC_DOUBLE("ADC1 Capture Switch", RT5677_STO1_ADC_DIG_VOL, 835 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1), 836 SOC_DOUBLE("ADC2 Capture Switch", RT5677_STO2_ADC_DIG_VOL, 837 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1), 838 SOC_DOUBLE("ADC3 Capture Switch", RT5677_STO3_ADC_DIG_VOL, 839 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1), 840 SOC_DOUBLE("ADC4 Capture Switch", RT5677_STO4_ADC_DIG_VOL, 841 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1), 842 SOC_DOUBLE("Mono ADC Capture Switch", RT5677_MONO_ADC_DIG_VOL, 843 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1), 844 845 SOC_DOUBLE_TLV("ADC1 Capture Volume", RT5677_STO1_ADC_DIG_VOL, 846 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 63, 0, 847 adc_vol_tlv), 848 SOC_DOUBLE_TLV("ADC2 Capture Volume", RT5677_STO2_ADC_DIG_VOL, 849 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 63, 0, 850 adc_vol_tlv), 851 SOC_DOUBLE_TLV("ADC3 Capture Volume", RT5677_STO3_ADC_DIG_VOL, 852 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 63, 0, 853 adc_vol_tlv), 854 SOC_DOUBLE_TLV("ADC4 Capture Volume", RT5677_STO4_ADC_DIG_VOL, 855 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 63, 0, 856 adc_vol_tlv), 857 SOC_DOUBLE_TLV("Mono ADC Capture Volume", RT5677_MONO_ADC_DIG_VOL, 858 RT5677_MONO_ADC_L_VOL_SFT, RT5677_MONO_ADC_R_VOL_SFT, 63, 0, 859 adc_vol_tlv), 860 861 /* Sidetone Control */ 862 SOC_SINGLE_TLV("Sidetone Volume", RT5677_SIDETONE_CTRL, 863 RT5677_ST_VOL_SFT, 31, 0, st_vol_tlv), 864 865 /* ADC Boost Volume Control */ 866 SOC_DOUBLE_TLV("STO1 ADC Boost Volume", RT5677_STO1_2_ADC_BST, 867 RT5677_STO1_ADC_L_BST_SFT, RT5677_STO1_ADC_R_BST_SFT, 3, 0, 868 adc_bst_tlv), 869 SOC_DOUBLE_TLV("STO2 ADC Boost Volume", RT5677_STO1_2_ADC_BST, 870 RT5677_STO2_ADC_L_BST_SFT, RT5677_STO2_ADC_R_BST_SFT, 3, 0, 871 adc_bst_tlv), 872 SOC_DOUBLE_TLV("STO3 ADC Boost Volume", RT5677_STO3_4_ADC_BST, 873 RT5677_STO3_ADC_L_BST_SFT, RT5677_STO3_ADC_R_BST_SFT, 3, 0, 874 adc_bst_tlv), 875 SOC_DOUBLE_TLV("STO4 ADC Boost Volume", RT5677_STO3_4_ADC_BST, 876 RT5677_STO4_ADC_L_BST_SFT, RT5677_STO4_ADC_R_BST_SFT, 3, 0, 877 adc_bst_tlv), 878 SOC_DOUBLE_TLV("Mono ADC Boost Volume", RT5677_ADC_BST_CTRL2, 879 RT5677_MONO_ADC_L_BST_SFT, RT5677_MONO_ADC_R_BST_SFT, 3, 0, 880 adc_bst_tlv), 881 882 SOC_SINGLE_EXT("DSP VAD Switch", SND_SOC_NOPM, 0, 1, 0, 883 rt5677_dsp_vad_get, rt5677_dsp_vad_put), 884 }; 885 886 /** 887 * set_dmic_clk - Set parameter of dmic. 888 * 889 * @w: DAPM widget. 890 * @kcontrol: The kcontrol of this widget. 891 * @event: Event id. 892 * 893 * Choose dmic clock between 1MHz and 3MHz. 894 * It is better for clock to approximate 3MHz. 895 */ 896 static int set_dmic_clk(struct snd_soc_dapm_widget *w, 897 struct snd_kcontrol *kcontrol, int event) 898 { 899 struct snd_soc_codec *codec = w->codec; 900 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec); 901 int idx = rl6231_calc_dmic_clk(rt5677->sysclk); 902 903 if (idx < 0) 904 dev_err(codec->dev, "Failed to set DMIC clock\n"); 905 else 906 regmap_update_bits(rt5677->regmap, RT5677_DMIC_CTRL1, 907 RT5677_DMIC_CLK_MASK, idx << RT5677_DMIC_CLK_SFT); 908 return idx; 909 } 910 911 static int is_sys_clk_from_pll(struct snd_soc_dapm_widget *source, 912 struct snd_soc_dapm_widget *sink) 913 { 914 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(source->codec); 915 unsigned int val; 916 917 regmap_read(rt5677->regmap, RT5677_GLB_CLK1, &val); 918 val &= RT5677_SCLK_SRC_MASK; 919 if (val == RT5677_SCLK_SRC_PLL1) 920 return 1; 921 else 922 return 0; 923 } 924 925 static int is_using_asrc(struct snd_soc_dapm_widget *source, 926 struct snd_soc_dapm_widget *sink) 927 { 928 unsigned int reg, shift, val; 929 930 if (source->reg == RT5677_ASRC_1) { 931 switch (source->shift) { 932 case 12: 933 reg = RT5677_ASRC_4; 934 shift = 0; 935 break; 936 case 13: 937 reg = RT5677_ASRC_4; 938 shift = 4; 939 break; 940 case 14: 941 reg = RT5677_ASRC_4; 942 shift = 8; 943 break; 944 case 15: 945 reg = RT5677_ASRC_4; 946 shift = 12; 947 break; 948 default: 949 return 0; 950 } 951 } else { 952 switch (source->shift) { 953 case 0: 954 reg = RT5677_ASRC_6; 955 shift = 8; 956 break; 957 case 1: 958 reg = RT5677_ASRC_6; 959 shift = 12; 960 break; 961 case 2: 962 reg = RT5677_ASRC_5; 963 shift = 0; 964 break; 965 case 3: 966 reg = RT5677_ASRC_5; 967 shift = 4; 968 break; 969 case 4: 970 reg = RT5677_ASRC_5; 971 shift = 8; 972 break; 973 case 5: 974 reg = RT5677_ASRC_5; 975 shift = 12; 976 break; 977 case 12: 978 reg = RT5677_ASRC_3; 979 shift = 0; 980 break; 981 case 13: 982 reg = RT5677_ASRC_3; 983 shift = 4; 984 break; 985 case 14: 986 reg = RT5677_ASRC_3; 987 shift = 12; 988 break; 989 default: 990 return 0; 991 } 992 } 993 994 val = (snd_soc_read(source->codec, reg) >> shift) & 0xf; 995 switch (val) { 996 case 1 ... 6: 997 return 1; 998 default: 999 return 0; 1000 } 1001 1002 } 1003 1004 static int can_use_asrc(struct snd_soc_dapm_widget *source, 1005 struct snd_soc_dapm_widget *sink) 1006 { 1007 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(source->dapm); 1008 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec); 1009 1010 if (rt5677->sysclk > rt5677->lrck[RT5677_AIF1] * 384) 1011 return 1; 1012 1013 return 0; 1014 } 1015 1016 /* Digital Mixer */ 1017 static const struct snd_kcontrol_new rt5677_sto1_adc_l_mix[] = { 1018 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO1_ADC_MIXER, 1019 RT5677_M_STO1_ADC_L1_SFT, 1, 1), 1020 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO1_ADC_MIXER, 1021 RT5677_M_STO1_ADC_L2_SFT, 1, 1), 1022 }; 1023 1024 static const struct snd_kcontrol_new rt5677_sto1_adc_r_mix[] = { 1025 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO1_ADC_MIXER, 1026 RT5677_M_STO1_ADC_R1_SFT, 1, 1), 1027 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO1_ADC_MIXER, 1028 RT5677_M_STO1_ADC_R2_SFT, 1, 1), 1029 }; 1030 1031 static const struct snd_kcontrol_new rt5677_sto2_adc_l_mix[] = { 1032 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO2_ADC_MIXER, 1033 RT5677_M_STO2_ADC_L1_SFT, 1, 1), 1034 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO2_ADC_MIXER, 1035 RT5677_M_STO2_ADC_L2_SFT, 1, 1), 1036 }; 1037 1038 static const struct snd_kcontrol_new rt5677_sto2_adc_r_mix[] = { 1039 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO2_ADC_MIXER, 1040 RT5677_M_STO2_ADC_R1_SFT, 1, 1), 1041 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO2_ADC_MIXER, 1042 RT5677_M_STO2_ADC_R2_SFT, 1, 1), 1043 }; 1044 1045 static const struct snd_kcontrol_new rt5677_sto3_adc_l_mix[] = { 1046 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO3_ADC_MIXER, 1047 RT5677_M_STO3_ADC_L1_SFT, 1, 1), 1048 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO3_ADC_MIXER, 1049 RT5677_M_STO3_ADC_L2_SFT, 1, 1), 1050 }; 1051 1052 static const struct snd_kcontrol_new rt5677_sto3_adc_r_mix[] = { 1053 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO3_ADC_MIXER, 1054 RT5677_M_STO3_ADC_R1_SFT, 1, 1), 1055 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO3_ADC_MIXER, 1056 RT5677_M_STO3_ADC_R2_SFT, 1, 1), 1057 }; 1058 1059 static const struct snd_kcontrol_new rt5677_sto4_adc_l_mix[] = { 1060 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO4_ADC_MIXER, 1061 RT5677_M_STO4_ADC_L1_SFT, 1, 1), 1062 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO4_ADC_MIXER, 1063 RT5677_M_STO4_ADC_L2_SFT, 1, 1), 1064 }; 1065 1066 static const struct snd_kcontrol_new rt5677_sto4_adc_r_mix[] = { 1067 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO4_ADC_MIXER, 1068 RT5677_M_STO4_ADC_R1_SFT, 1, 1), 1069 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO4_ADC_MIXER, 1070 RT5677_M_STO4_ADC_R2_SFT, 1, 1), 1071 }; 1072 1073 static const struct snd_kcontrol_new rt5677_mono_adc_l_mix[] = { 1074 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_MONO_ADC_MIXER, 1075 RT5677_M_MONO_ADC_L1_SFT, 1, 1), 1076 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_MONO_ADC_MIXER, 1077 RT5677_M_MONO_ADC_L2_SFT, 1, 1), 1078 }; 1079 1080 static const struct snd_kcontrol_new rt5677_mono_adc_r_mix[] = { 1081 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_MONO_ADC_MIXER, 1082 RT5677_M_MONO_ADC_R1_SFT, 1, 1), 1083 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_MONO_ADC_MIXER, 1084 RT5677_M_MONO_ADC_R2_SFT, 1, 1), 1085 }; 1086 1087 static const struct snd_kcontrol_new rt5677_dac_l_mix[] = { 1088 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5677_ADC_IF_DSP_DAC1_MIXER, 1089 RT5677_M_ADDA_MIXER1_L_SFT, 1, 1), 1090 SOC_DAPM_SINGLE("DAC1 Switch", RT5677_ADC_IF_DSP_DAC1_MIXER, 1091 RT5677_M_DAC1_L_SFT, 1, 1), 1092 }; 1093 1094 static const struct snd_kcontrol_new rt5677_dac_r_mix[] = { 1095 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5677_ADC_IF_DSP_DAC1_MIXER, 1096 RT5677_M_ADDA_MIXER1_R_SFT, 1, 1), 1097 SOC_DAPM_SINGLE("DAC1 Switch", RT5677_ADC_IF_DSP_DAC1_MIXER, 1098 RT5677_M_DAC1_R_SFT, 1, 1), 1099 }; 1100 1101 static const struct snd_kcontrol_new rt5677_sto1_dac_l_mix[] = { 1102 SOC_DAPM_SINGLE("ST L Switch", RT5677_STO1_DAC_MIXER, 1103 RT5677_M_ST_DAC1_L_SFT, 1, 1), 1104 SOC_DAPM_SINGLE("DAC1 L Switch", RT5677_STO1_DAC_MIXER, 1105 RT5677_M_DAC1_L_STO_L_SFT, 1, 1), 1106 SOC_DAPM_SINGLE("DAC2 L Switch", RT5677_STO1_DAC_MIXER, 1107 RT5677_M_DAC2_L_STO_L_SFT, 1, 1), 1108 SOC_DAPM_SINGLE("DAC1 R Switch", RT5677_STO1_DAC_MIXER, 1109 RT5677_M_DAC1_R_STO_L_SFT, 1, 1), 1110 }; 1111 1112 static const struct snd_kcontrol_new rt5677_sto1_dac_r_mix[] = { 1113 SOC_DAPM_SINGLE("ST R Switch", RT5677_STO1_DAC_MIXER, 1114 RT5677_M_ST_DAC1_R_SFT, 1, 1), 1115 SOC_DAPM_SINGLE("DAC1 R Switch", RT5677_STO1_DAC_MIXER, 1116 RT5677_M_DAC1_R_STO_R_SFT, 1, 1), 1117 SOC_DAPM_SINGLE("DAC2 R Switch", RT5677_STO1_DAC_MIXER, 1118 RT5677_M_DAC2_R_STO_R_SFT, 1, 1), 1119 SOC_DAPM_SINGLE("DAC1 L Switch", RT5677_STO1_DAC_MIXER, 1120 RT5677_M_DAC1_L_STO_R_SFT, 1, 1), 1121 }; 1122 1123 static const struct snd_kcontrol_new rt5677_mono_dac_l_mix[] = { 1124 SOC_DAPM_SINGLE("ST L Switch", RT5677_MONO_DAC_MIXER, 1125 RT5677_M_ST_DAC2_L_SFT, 1, 1), 1126 SOC_DAPM_SINGLE("DAC1 L Switch", RT5677_MONO_DAC_MIXER, 1127 RT5677_M_DAC1_L_MONO_L_SFT, 1, 1), 1128 SOC_DAPM_SINGLE("DAC2 L Switch", RT5677_MONO_DAC_MIXER, 1129 RT5677_M_DAC2_L_MONO_L_SFT, 1, 1), 1130 SOC_DAPM_SINGLE("DAC2 R Switch", RT5677_MONO_DAC_MIXER, 1131 RT5677_M_DAC2_R_MONO_L_SFT, 1, 1), 1132 }; 1133 1134 static const struct snd_kcontrol_new rt5677_mono_dac_r_mix[] = { 1135 SOC_DAPM_SINGLE("ST R Switch", RT5677_MONO_DAC_MIXER, 1136 RT5677_M_ST_DAC2_R_SFT, 1, 1), 1137 SOC_DAPM_SINGLE("DAC1 R Switch", RT5677_MONO_DAC_MIXER, 1138 RT5677_M_DAC1_R_MONO_R_SFT, 1, 1), 1139 SOC_DAPM_SINGLE("DAC2 R Switch", RT5677_MONO_DAC_MIXER, 1140 RT5677_M_DAC2_R_MONO_R_SFT, 1, 1), 1141 SOC_DAPM_SINGLE("DAC2 L Switch", RT5677_MONO_DAC_MIXER, 1142 RT5677_M_DAC2_L_MONO_R_SFT, 1, 1), 1143 }; 1144 1145 static const struct snd_kcontrol_new rt5677_dd1_l_mix[] = { 1146 SOC_DAPM_SINGLE("Sto DAC Mix L Switch", RT5677_DD1_MIXER, 1147 RT5677_M_STO_L_DD1_L_SFT, 1, 1), 1148 SOC_DAPM_SINGLE("Mono DAC Mix L Switch", RT5677_DD1_MIXER, 1149 RT5677_M_MONO_L_DD1_L_SFT, 1, 1), 1150 SOC_DAPM_SINGLE("DAC3 L Switch", RT5677_DD1_MIXER, 1151 RT5677_M_DAC3_L_DD1_L_SFT, 1, 1), 1152 SOC_DAPM_SINGLE("DAC3 R Switch", RT5677_DD1_MIXER, 1153 RT5677_M_DAC3_R_DD1_L_SFT, 1, 1), 1154 }; 1155 1156 static const struct snd_kcontrol_new rt5677_dd1_r_mix[] = { 1157 SOC_DAPM_SINGLE("Sto DAC Mix R Switch", RT5677_DD1_MIXER, 1158 RT5677_M_STO_R_DD1_R_SFT, 1, 1), 1159 SOC_DAPM_SINGLE("Mono DAC Mix R Switch", RT5677_DD1_MIXER, 1160 RT5677_M_MONO_R_DD1_R_SFT, 1, 1), 1161 SOC_DAPM_SINGLE("DAC3 R Switch", RT5677_DD1_MIXER, 1162 RT5677_M_DAC3_R_DD1_R_SFT, 1, 1), 1163 SOC_DAPM_SINGLE("DAC3 L Switch", RT5677_DD1_MIXER, 1164 RT5677_M_DAC3_L_DD1_R_SFT, 1, 1), 1165 }; 1166 1167 static const struct snd_kcontrol_new rt5677_dd2_l_mix[] = { 1168 SOC_DAPM_SINGLE("Sto DAC Mix L Switch", RT5677_DD2_MIXER, 1169 RT5677_M_STO_L_DD2_L_SFT, 1, 1), 1170 SOC_DAPM_SINGLE("Mono DAC Mix L Switch", RT5677_DD2_MIXER, 1171 RT5677_M_MONO_L_DD2_L_SFT, 1, 1), 1172 SOC_DAPM_SINGLE("DAC4 L Switch", RT5677_DD2_MIXER, 1173 RT5677_M_DAC4_L_DD2_L_SFT, 1, 1), 1174 SOC_DAPM_SINGLE("DAC4 R Switch", RT5677_DD2_MIXER, 1175 RT5677_M_DAC4_R_DD2_L_SFT, 1, 1), 1176 }; 1177 1178 static const struct snd_kcontrol_new rt5677_dd2_r_mix[] = { 1179 SOC_DAPM_SINGLE("Sto DAC Mix R Switch", RT5677_DD2_MIXER, 1180 RT5677_M_STO_R_DD2_R_SFT, 1, 1), 1181 SOC_DAPM_SINGLE("Mono DAC Mix R Switch", RT5677_DD2_MIXER, 1182 RT5677_M_MONO_R_DD2_R_SFT, 1, 1), 1183 SOC_DAPM_SINGLE("DAC4 R Switch", RT5677_DD2_MIXER, 1184 RT5677_M_DAC4_R_DD2_R_SFT, 1, 1), 1185 SOC_DAPM_SINGLE("DAC4 L Switch", RT5677_DD2_MIXER, 1186 RT5677_M_DAC4_L_DD2_R_SFT, 1, 1), 1187 }; 1188 1189 static const struct snd_kcontrol_new rt5677_ob_01_mix[] = { 1190 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL, 1191 RT5677_DSP_IB_01_H_SFT, 1, 1), 1192 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL, 1193 RT5677_DSP_IB_23_H_SFT, 1, 1), 1194 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL, 1195 RT5677_DSP_IB_45_H_SFT, 1, 1), 1196 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL, 1197 RT5677_DSP_IB_6_H_SFT, 1, 1), 1198 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL, 1199 RT5677_DSP_IB_7_H_SFT, 1, 1), 1200 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL, 1201 RT5677_DSP_IB_8_H_SFT, 1, 1), 1202 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL, 1203 RT5677_DSP_IB_9_H_SFT, 1, 1), 1204 }; 1205 1206 static const struct snd_kcontrol_new rt5677_ob_23_mix[] = { 1207 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL, 1208 RT5677_DSP_IB_01_L_SFT, 1, 1), 1209 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL, 1210 RT5677_DSP_IB_23_L_SFT, 1, 1), 1211 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL, 1212 RT5677_DSP_IB_45_L_SFT, 1, 1), 1213 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL, 1214 RT5677_DSP_IB_6_L_SFT, 1, 1), 1215 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL, 1216 RT5677_DSP_IB_7_L_SFT, 1, 1), 1217 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL, 1218 RT5677_DSP_IB_8_L_SFT, 1, 1), 1219 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL, 1220 RT5677_DSP_IB_9_L_SFT, 1, 1), 1221 }; 1222 1223 static const struct snd_kcontrol_new rt5677_ob_4_mix[] = { 1224 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL, 1225 RT5677_DSP_IB_01_H_SFT, 1, 1), 1226 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL, 1227 RT5677_DSP_IB_23_H_SFT, 1, 1), 1228 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL, 1229 RT5677_DSP_IB_45_H_SFT, 1, 1), 1230 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL, 1231 RT5677_DSP_IB_6_H_SFT, 1, 1), 1232 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL, 1233 RT5677_DSP_IB_7_H_SFT, 1, 1), 1234 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL, 1235 RT5677_DSP_IB_8_H_SFT, 1, 1), 1236 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL, 1237 RT5677_DSP_IB_9_H_SFT, 1, 1), 1238 }; 1239 1240 static const struct snd_kcontrol_new rt5677_ob_5_mix[] = { 1241 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL, 1242 RT5677_DSP_IB_01_L_SFT, 1, 1), 1243 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL, 1244 RT5677_DSP_IB_23_L_SFT, 1, 1), 1245 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL, 1246 RT5677_DSP_IB_45_L_SFT, 1, 1), 1247 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL, 1248 RT5677_DSP_IB_6_L_SFT, 1, 1), 1249 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL, 1250 RT5677_DSP_IB_7_L_SFT, 1, 1), 1251 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL, 1252 RT5677_DSP_IB_8_L_SFT, 1, 1), 1253 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL, 1254 RT5677_DSP_IB_9_L_SFT, 1, 1), 1255 }; 1256 1257 static const struct snd_kcontrol_new rt5677_ob_6_mix[] = { 1258 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL, 1259 RT5677_DSP_IB_01_H_SFT, 1, 1), 1260 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL, 1261 RT5677_DSP_IB_23_H_SFT, 1, 1), 1262 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL, 1263 RT5677_DSP_IB_45_H_SFT, 1, 1), 1264 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL, 1265 RT5677_DSP_IB_6_H_SFT, 1, 1), 1266 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL, 1267 RT5677_DSP_IB_7_H_SFT, 1, 1), 1268 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL, 1269 RT5677_DSP_IB_8_H_SFT, 1, 1), 1270 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL, 1271 RT5677_DSP_IB_9_H_SFT, 1, 1), 1272 }; 1273 1274 static const struct snd_kcontrol_new rt5677_ob_7_mix[] = { 1275 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL, 1276 RT5677_DSP_IB_01_L_SFT, 1, 1), 1277 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL, 1278 RT5677_DSP_IB_23_L_SFT, 1, 1), 1279 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL, 1280 RT5677_DSP_IB_45_L_SFT, 1, 1), 1281 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL, 1282 RT5677_DSP_IB_6_L_SFT, 1, 1), 1283 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL, 1284 RT5677_DSP_IB_7_L_SFT, 1, 1), 1285 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL, 1286 RT5677_DSP_IB_8_L_SFT, 1, 1), 1287 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL, 1288 RT5677_DSP_IB_9_L_SFT, 1, 1), 1289 }; 1290 1291 1292 /* Mux */ 1293 /* DAC1 L/R Source */ /* MX-29 [10:8] */ 1294 static const char * const rt5677_dac1_src[] = { 1295 "IF1 DAC 01", "IF2 DAC 01", "IF3 DAC LR", "IF4 DAC LR", "SLB DAC 01", 1296 "OB 01" 1297 }; 1298 1299 static SOC_ENUM_SINGLE_DECL( 1300 rt5677_dac1_enum, RT5677_ADC_IF_DSP_DAC1_MIXER, 1301 RT5677_DAC1_L_SEL_SFT, rt5677_dac1_src); 1302 1303 static const struct snd_kcontrol_new rt5677_dac1_mux = 1304 SOC_DAPM_ENUM("DAC1 Source", rt5677_dac1_enum); 1305 1306 /* ADDA1 L/R Source */ /* MX-29 [1:0] */ 1307 static const char * const rt5677_adda1_src[] = { 1308 "STO1 ADC MIX", "STO2 ADC MIX", "OB 67", 1309 }; 1310 1311 static SOC_ENUM_SINGLE_DECL( 1312 rt5677_adda1_enum, RT5677_ADC_IF_DSP_DAC1_MIXER, 1313 RT5677_ADDA1_SEL_SFT, rt5677_adda1_src); 1314 1315 static const struct snd_kcontrol_new rt5677_adda1_mux = 1316 SOC_DAPM_ENUM("ADDA1 Source", rt5677_adda1_enum); 1317 1318 1319 /*DAC2 L/R Source*/ /* MX-1B [6:4] [2:0] */ 1320 static const char * const rt5677_dac2l_src[] = { 1321 "IF1 DAC 2", "IF2 DAC 2", "IF3 DAC L", "IF4 DAC L", "SLB DAC 2", 1322 "OB 2", 1323 }; 1324 1325 static SOC_ENUM_SINGLE_DECL( 1326 rt5677_dac2l_enum, RT5677_IF_DSP_DAC2_MIXER, 1327 RT5677_SEL_DAC2_L_SRC_SFT, rt5677_dac2l_src); 1328 1329 static const struct snd_kcontrol_new rt5677_dac2_l_mux = 1330 SOC_DAPM_ENUM("DAC2 L Source", rt5677_dac2l_enum); 1331 1332 static const char * const rt5677_dac2r_src[] = { 1333 "IF1 DAC 3", "IF2 DAC 3", "IF3 DAC R", "IF4 DAC R", "SLB DAC 3", 1334 "OB 3", "Haptic Generator", "VAD ADC" 1335 }; 1336 1337 static SOC_ENUM_SINGLE_DECL( 1338 rt5677_dac2r_enum, RT5677_IF_DSP_DAC2_MIXER, 1339 RT5677_SEL_DAC2_R_SRC_SFT, rt5677_dac2r_src); 1340 1341 static const struct snd_kcontrol_new rt5677_dac2_r_mux = 1342 SOC_DAPM_ENUM("DAC2 R Source", rt5677_dac2r_enum); 1343 1344 /*DAC3 L/R Source*/ /* MX-16 [6:4] [2:0] */ 1345 static const char * const rt5677_dac3l_src[] = { 1346 "IF1 DAC 4", "IF2 DAC 4", "IF3 DAC L", "IF4 DAC L", 1347 "SLB DAC 4", "OB 4" 1348 }; 1349 1350 static SOC_ENUM_SINGLE_DECL( 1351 rt5677_dac3l_enum, RT5677_IF_DSP_DAC3_4_MIXER, 1352 RT5677_SEL_DAC3_L_SRC_SFT, rt5677_dac3l_src); 1353 1354 static const struct snd_kcontrol_new rt5677_dac3_l_mux = 1355 SOC_DAPM_ENUM("DAC3 L Source", rt5677_dac3l_enum); 1356 1357 static const char * const rt5677_dac3r_src[] = { 1358 "IF1 DAC 5", "IF2 DAC 5", "IF3 DAC R", "IF4 DAC R", 1359 "SLB DAC 5", "OB 5" 1360 }; 1361 1362 static SOC_ENUM_SINGLE_DECL( 1363 rt5677_dac3r_enum, RT5677_IF_DSP_DAC3_4_MIXER, 1364 RT5677_SEL_DAC3_R_SRC_SFT, rt5677_dac3r_src); 1365 1366 static const struct snd_kcontrol_new rt5677_dac3_r_mux = 1367 SOC_DAPM_ENUM("DAC3 R Source", rt5677_dac3r_enum); 1368 1369 /*DAC4 L/R Source*/ /* MX-16 [14:12] [10:8] */ 1370 static const char * const rt5677_dac4l_src[] = { 1371 "IF1 DAC 6", "IF2 DAC 6", "IF3 DAC L", "IF4 DAC L", 1372 "SLB DAC 6", "OB 6" 1373 }; 1374 1375 static SOC_ENUM_SINGLE_DECL( 1376 rt5677_dac4l_enum, RT5677_IF_DSP_DAC3_4_MIXER, 1377 RT5677_SEL_DAC4_L_SRC_SFT, rt5677_dac4l_src); 1378 1379 static const struct snd_kcontrol_new rt5677_dac4_l_mux = 1380 SOC_DAPM_ENUM("DAC4 L Source", rt5677_dac4l_enum); 1381 1382 static const char * const rt5677_dac4r_src[] = { 1383 "IF1 DAC 7", "IF2 DAC 7", "IF3 DAC R", "IF4 DAC R", 1384 "SLB DAC 7", "OB 7" 1385 }; 1386 1387 static SOC_ENUM_SINGLE_DECL( 1388 rt5677_dac4r_enum, RT5677_IF_DSP_DAC3_4_MIXER, 1389 RT5677_SEL_DAC4_R_SRC_SFT, rt5677_dac4r_src); 1390 1391 static const struct snd_kcontrol_new rt5677_dac4_r_mux = 1392 SOC_DAPM_ENUM("DAC4 R Source", rt5677_dac4r_enum); 1393 1394 /* In/OutBound Source Pass SRC */ /* MX-A5 [3] [4] [0] [1] [2] */ 1395 static const char * const rt5677_iob_bypass_src[] = { 1396 "Bypass", "Pass SRC" 1397 }; 1398 1399 static SOC_ENUM_SINGLE_DECL( 1400 rt5677_ob01_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL, 1401 RT5677_SEL_SRC_OB01_SFT, rt5677_iob_bypass_src); 1402 1403 static const struct snd_kcontrol_new rt5677_ob01_bypass_src_mux = 1404 SOC_DAPM_ENUM("OB01 Bypass Source", rt5677_ob01_bypass_src_enum); 1405 1406 static SOC_ENUM_SINGLE_DECL( 1407 rt5677_ob23_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL, 1408 RT5677_SEL_SRC_OB23_SFT, rt5677_iob_bypass_src); 1409 1410 static const struct snd_kcontrol_new rt5677_ob23_bypass_src_mux = 1411 SOC_DAPM_ENUM("OB23 Bypass Source", rt5677_ob23_bypass_src_enum); 1412 1413 static SOC_ENUM_SINGLE_DECL( 1414 rt5677_ib01_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL, 1415 RT5677_SEL_SRC_IB01_SFT, rt5677_iob_bypass_src); 1416 1417 static const struct snd_kcontrol_new rt5677_ib01_bypass_src_mux = 1418 SOC_DAPM_ENUM("IB01 Bypass Source", rt5677_ib01_bypass_src_enum); 1419 1420 static SOC_ENUM_SINGLE_DECL( 1421 rt5677_ib23_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL, 1422 RT5677_SEL_SRC_IB23_SFT, rt5677_iob_bypass_src); 1423 1424 static const struct snd_kcontrol_new rt5677_ib23_bypass_src_mux = 1425 SOC_DAPM_ENUM("IB23 Bypass Source", rt5677_ib23_bypass_src_enum); 1426 1427 static SOC_ENUM_SINGLE_DECL( 1428 rt5677_ib45_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL, 1429 RT5677_SEL_SRC_IB45_SFT, rt5677_iob_bypass_src); 1430 1431 static const struct snd_kcontrol_new rt5677_ib45_bypass_src_mux = 1432 SOC_DAPM_ENUM("IB45 Bypass Source", rt5677_ib45_bypass_src_enum); 1433 1434 /* Stereo ADC Source 2 */ /* MX-27 MX26 MX25 [11:10] */ 1435 static const char * const rt5677_stereo_adc2_src[] = { 1436 "DD MIX1", "DMIC", "Stereo DAC MIX" 1437 }; 1438 1439 static SOC_ENUM_SINGLE_DECL( 1440 rt5677_stereo1_adc2_enum, RT5677_STO1_ADC_MIXER, 1441 RT5677_SEL_STO1_ADC2_SFT, rt5677_stereo_adc2_src); 1442 1443 static const struct snd_kcontrol_new rt5677_sto1_adc2_mux = 1444 SOC_DAPM_ENUM("Stereo1 ADC2 Source", rt5677_stereo1_adc2_enum); 1445 1446 static SOC_ENUM_SINGLE_DECL( 1447 rt5677_stereo2_adc2_enum, RT5677_STO2_ADC_MIXER, 1448 RT5677_SEL_STO2_ADC2_SFT, rt5677_stereo_adc2_src); 1449 1450 static const struct snd_kcontrol_new rt5677_sto2_adc2_mux = 1451 SOC_DAPM_ENUM("Stereo2 ADC2 Source", rt5677_stereo2_adc2_enum); 1452 1453 static SOC_ENUM_SINGLE_DECL( 1454 rt5677_stereo3_adc2_enum, RT5677_STO3_ADC_MIXER, 1455 RT5677_SEL_STO3_ADC2_SFT, rt5677_stereo_adc2_src); 1456 1457 static const struct snd_kcontrol_new rt5677_sto3_adc2_mux = 1458 SOC_DAPM_ENUM("Stereo3 ADC2 Source", rt5677_stereo3_adc2_enum); 1459 1460 /* DMIC Source */ /* MX-28 [9:8][1:0] MX-27 MX-26 MX-25 MX-24 [9:8] */ 1461 static const char * const rt5677_dmic_src[] = { 1462 "DMIC1", "DMIC2", "DMIC3", "DMIC4" 1463 }; 1464 1465 static SOC_ENUM_SINGLE_DECL( 1466 rt5677_mono_dmic_l_enum, RT5677_MONO_ADC_MIXER, 1467 RT5677_SEL_MONO_DMIC_L_SFT, rt5677_dmic_src); 1468 1469 static const struct snd_kcontrol_new rt5677_mono_dmic_l_mux = 1470 SOC_DAPM_ENUM("Mono DMIC L Source", rt5677_mono_dmic_l_enum); 1471 1472 static SOC_ENUM_SINGLE_DECL( 1473 rt5677_mono_dmic_r_enum, RT5677_MONO_ADC_MIXER, 1474 RT5677_SEL_MONO_DMIC_R_SFT, rt5677_dmic_src); 1475 1476 static const struct snd_kcontrol_new rt5677_mono_dmic_r_mux = 1477 SOC_DAPM_ENUM("Mono DMIC R Source", rt5677_mono_dmic_r_enum); 1478 1479 static SOC_ENUM_SINGLE_DECL( 1480 rt5677_stereo1_dmic_enum, RT5677_STO1_ADC_MIXER, 1481 RT5677_SEL_STO1_DMIC_SFT, rt5677_dmic_src); 1482 1483 static const struct snd_kcontrol_new rt5677_sto1_dmic_mux = 1484 SOC_DAPM_ENUM("Stereo1 DMIC Source", rt5677_stereo1_dmic_enum); 1485 1486 static SOC_ENUM_SINGLE_DECL( 1487 rt5677_stereo2_dmic_enum, RT5677_STO2_ADC_MIXER, 1488 RT5677_SEL_STO2_DMIC_SFT, rt5677_dmic_src); 1489 1490 static const struct snd_kcontrol_new rt5677_sto2_dmic_mux = 1491 SOC_DAPM_ENUM("Stereo2 DMIC Source", rt5677_stereo2_dmic_enum); 1492 1493 static SOC_ENUM_SINGLE_DECL( 1494 rt5677_stereo3_dmic_enum, RT5677_STO3_ADC_MIXER, 1495 RT5677_SEL_STO3_DMIC_SFT, rt5677_dmic_src); 1496 1497 static const struct snd_kcontrol_new rt5677_sto3_dmic_mux = 1498 SOC_DAPM_ENUM("Stereo3 DMIC Source", rt5677_stereo3_dmic_enum); 1499 1500 static SOC_ENUM_SINGLE_DECL( 1501 rt5677_stereo4_dmic_enum, RT5677_STO4_ADC_MIXER, 1502 RT5677_SEL_STO4_DMIC_SFT, rt5677_dmic_src); 1503 1504 static const struct snd_kcontrol_new rt5677_sto4_dmic_mux = 1505 SOC_DAPM_ENUM("Stereo4 DMIC Source", rt5677_stereo4_dmic_enum); 1506 1507 /* Stereo2 ADC Source */ /* MX-26 [0] */ 1508 static const char * const rt5677_stereo2_adc_lr_src[] = { 1509 "L", "LR" 1510 }; 1511 1512 static SOC_ENUM_SINGLE_DECL( 1513 rt5677_stereo2_adc_lr_enum, RT5677_STO2_ADC_MIXER, 1514 RT5677_SEL_STO2_LR_MIX_SFT, rt5677_stereo2_adc_lr_src); 1515 1516 static const struct snd_kcontrol_new rt5677_sto2_adc_lr_mux = 1517 SOC_DAPM_ENUM("Stereo2 ADC LR Source", rt5677_stereo2_adc_lr_enum); 1518 1519 /* Stereo1 ADC Source 1 */ /* MX-27 MX26 MX25 [13:12] */ 1520 static const char * const rt5677_stereo_adc1_src[] = { 1521 "DD MIX1", "ADC1/2", "Stereo DAC MIX" 1522 }; 1523 1524 static SOC_ENUM_SINGLE_DECL( 1525 rt5677_stereo1_adc1_enum, RT5677_STO1_ADC_MIXER, 1526 RT5677_SEL_STO1_ADC1_SFT, rt5677_stereo_adc1_src); 1527 1528 static const struct snd_kcontrol_new rt5677_sto1_adc1_mux = 1529 SOC_DAPM_ENUM("Stereo1 ADC1 Source", rt5677_stereo1_adc1_enum); 1530 1531 static SOC_ENUM_SINGLE_DECL( 1532 rt5677_stereo2_adc1_enum, RT5677_STO2_ADC_MIXER, 1533 RT5677_SEL_STO2_ADC1_SFT, rt5677_stereo_adc1_src); 1534 1535 static const struct snd_kcontrol_new rt5677_sto2_adc1_mux = 1536 SOC_DAPM_ENUM("Stereo2 ADC1 Source", rt5677_stereo2_adc1_enum); 1537 1538 static SOC_ENUM_SINGLE_DECL( 1539 rt5677_stereo3_adc1_enum, RT5677_STO3_ADC_MIXER, 1540 RT5677_SEL_STO3_ADC1_SFT, rt5677_stereo_adc1_src); 1541 1542 static const struct snd_kcontrol_new rt5677_sto3_adc1_mux = 1543 SOC_DAPM_ENUM("Stereo3 ADC1 Source", rt5677_stereo3_adc1_enum); 1544 1545 /* Mono ADC Left Source 2 */ /* MX-28 [11:10] */ 1546 static const char * const rt5677_mono_adc2_l_src[] = { 1547 "DD MIX1L", "DMIC", "MONO DAC MIXL" 1548 }; 1549 1550 static SOC_ENUM_SINGLE_DECL( 1551 rt5677_mono_adc2_l_enum, RT5677_MONO_ADC_MIXER, 1552 RT5677_SEL_MONO_ADC_L2_SFT, rt5677_mono_adc2_l_src); 1553 1554 static const struct snd_kcontrol_new rt5677_mono_adc2_l_mux = 1555 SOC_DAPM_ENUM("Mono ADC2 L Source", rt5677_mono_adc2_l_enum); 1556 1557 /* Mono ADC Left Source 1 */ /* MX-28 [13:12] */ 1558 static const char * const rt5677_mono_adc1_l_src[] = { 1559 "DD MIX1L", "ADC1", "MONO DAC MIXL" 1560 }; 1561 1562 static SOC_ENUM_SINGLE_DECL( 1563 rt5677_mono_adc1_l_enum, RT5677_MONO_ADC_MIXER, 1564 RT5677_SEL_MONO_ADC_L1_SFT, rt5677_mono_adc1_l_src); 1565 1566 static const struct snd_kcontrol_new rt5677_mono_adc1_l_mux = 1567 SOC_DAPM_ENUM("Mono ADC1 L Source", rt5677_mono_adc1_l_enum); 1568 1569 /* Mono ADC Right Source 2 */ /* MX-28 [3:2] */ 1570 static const char * const rt5677_mono_adc2_r_src[] = { 1571 "DD MIX1R", "DMIC", "MONO DAC MIXR" 1572 }; 1573 1574 static SOC_ENUM_SINGLE_DECL( 1575 rt5677_mono_adc2_r_enum, RT5677_MONO_ADC_MIXER, 1576 RT5677_SEL_MONO_ADC_R2_SFT, rt5677_mono_adc2_r_src); 1577 1578 static const struct snd_kcontrol_new rt5677_mono_adc2_r_mux = 1579 SOC_DAPM_ENUM("Mono ADC2 R Source", rt5677_mono_adc2_r_enum); 1580 1581 /* Mono ADC Right Source 1 */ /* MX-28 [5:4] */ 1582 static const char * const rt5677_mono_adc1_r_src[] = { 1583 "DD MIX1R", "ADC2", "MONO DAC MIXR" 1584 }; 1585 1586 static SOC_ENUM_SINGLE_DECL( 1587 rt5677_mono_adc1_r_enum, RT5677_MONO_ADC_MIXER, 1588 RT5677_SEL_MONO_ADC_R1_SFT, rt5677_mono_adc1_r_src); 1589 1590 static const struct snd_kcontrol_new rt5677_mono_adc1_r_mux = 1591 SOC_DAPM_ENUM("Mono ADC1 R Source", rt5677_mono_adc1_r_enum); 1592 1593 /* Stereo4 ADC Source 2 */ /* MX-24 [11:10] */ 1594 static const char * const rt5677_stereo4_adc2_src[] = { 1595 "DD MIX1", "DMIC", "DD MIX2" 1596 }; 1597 1598 static SOC_ENUM_SINGLE_DECL( 1599 rt5677_stereo4_adc2_enum, RT5677_STO4_ADC_MIXER, 1600 RT5677_SEL_STO4_ADC2_SFT, rt5677_stereo4_adc2_src); 1601 1602 static const struct snd_kcontrol_new rt5677_sto4_adc2_mux = 1603 SOC_DAPM_ENUM("Stereo4 ADC2 Source", rt5677_stereo4_adc2_enum); 1604 1605 1606 /* Stereo4 ADC Source 1 */ /* MX-24 [13:12] */ 1607 static const char * const rt5677_stereo4_adc1_src[] = { 1608 "DD MIX1", "ADC1/2", "DD MIX2" 1609 }; 1610 1611 static SOC_ENUM_SINGLE_DECL( 1612 rt5677_stereo4_adc1_enum, RT5677_STO4_ADC_MIXER, 1613 RT5677_SEL_STO4_ADC1_SFT, rt5677_stereo4_adc1_src); 1614 1615 static const struct snd_kcontrol_new rt5677_sto4_adc1_mux = 1616 SOC_DAPM_ENUM("Stereo4 ADC1 Source", rt5677_stereo4_adc1_enum); 1617 1618 /* InBound0/1 Source */ /* MX-A3 [14:12] */ 1619 static const char * const rt5677_inbound01_src[] = { 1620 "IF1 DAC 01", "IF2 DAC 01", "SLB DAC 01", "STO1 ADC MIX", 1621 "VAD ADC/DAC1 FS" 1622 }; 1623 1624 static SOC_ENUM_SINGLE_DECL( 1625 rt5677_inbound01_enum, RT5677_DSP_INB_CTRL1, 1626 RT5677_IB01_SRC_SFT, rt5677_inbound01_src); 1627 1628 static const struct snd_kcontrol_new rt5677_ib01_src_mux = 1629 SOC_DAPM_ENUM("InBound0/1 Source", rt5677_inbound01_enum); 1630 1631 /* InBound2/3 Source */ /* MX-A3 [10:8] */ 1632 static const char * const rt5677_inbound23_src[] = { 1633 "IF1 DAC 23", "IF2 DAC 23", "SLB DAC 23", "STO2 ADC MIX", 1634 "DAC1 FS", "IF4 DAC" 1635 }; 1636 1637 static SOC_ENUM_SINGLE_DECL( 1638 rt5677_inbound23_enum, RT5677_DSP_INB_CTRL1, 1639 RT5677_IB23_SRC_SFT, rt5677_inbound23_src); 1640 1641 static const struct snd_kcontrol_new rt5677_ib23_src_mux = 1642 SOC_DAPM_ENUM("InBound2/3 Source", rt5677_inbound23_enum); 1643 1644 /* InBound4/5 Source */ /* MX-A3 [6:4] */ 1645 static const char * const rt5677_inbound45_src[] = { 1646 "IF1 DAC 45", "IF2 DAC 45", "SLB DAC 45", "STO3 ADC MIX", 1647 "IF3 DAC" 1648 }; 1649 1650 static SOC_ENUM_SINGLE_DECL( 1651 rt5677_inbound45_enum, RT5677_DSP_INB_CTRL1, 1652 RT5677_IB45_SRC_SFT, rt5677_inbound45_src); 1653 1654 static const struct snd_kcontrol_new rt5677_ib45_src_mux = 1655 SOC_DAPM_ENUM("InBound4/5 Source", rt5677_inbound45_enum); 1656 1657 /* InBound6 Source */ /* MX-A3 [2:0] */ 1658 static const char * const rt5677_inbound6_src[] = { 1659 "IF1 DAC 6", "IF2 DAC 6", "SLB DAC 6", "STO4 ADC MIX L", 1660 "IF4 DAC L", "STO1 ADC MIX L", "STO2 ADC MIX L", "STO3 ADC MIX L" 1661 }; 1662 1663 static SOC_ENUM_SINGLE_DECL( 1664 rt5677_inbound6_enum, RT5677_DSP_INB_CTRL1, 1665 RT5677_IB6_SRC_SFT, rt5677_inbound6_src); 1666 1667 static const struct snd_kcontrol_new rt5677_ib6_src_mux = 1668 SOC_DAPM_ENUM("InBound6 Source", rt5677_inbound6_enum); 1669 1670 /* InBound7 Source */ /* MX-A4 [14:12] */ 1671 static const char * const rt5677_inbound7_src[] = { 1672 "IF1 DAC 7", "IF2 DAC 7", "SLB DAC 7", "STO4 ADC MIX R", 1673 "IF4 DAC R", "STO1 ADC MIX R", "STO2 ADC MIX R", "STO3 ADC MIX R" 1674 }; 1675 1676 static SOC_ENUM_SINGLE_DECL( 1677 rt5677_inbound7_enum, RT5677_DSP_INB_CTRL2, 1678 RT5677_IB7_SRC_SFT, rt5677_inbound7_src); 1679 1680 static const struct snd_kcontrol_new rt5677_ib7_src_mux = 1681 SOC_DAPM_ENUM("InBound7 Source", rt5677_inbound7_enum); 1682 1683 /* InBound8 Source */ /* MX-A4 [10:8] */ 1684 static const char * const rt5677_inbound8_src[] = { 1685 "STO1 ADC MIX L", "STO2 ADC MIX L", "STO3 ADC MIX L", "STO4 ADC MIX L", 1686 "MONO ADC MIX L", "DACL1 FS" 1687 }; 1688 1689 static SOC_ENUM_SINGLE_DECL( 1690 rt5677_inbound8_enum, RT5677_DSP_INB_CTRL2, 1691 RT5677_IB8_SRC_SFT, rt5677_inbound8_src); 1692 1693 static const struct snd_kcontrol_new rt5677_ib8_src_mux = 1694 SOC_DAPM_ENUM("InBound8 Source", rt5677_inbound8_enum); 1695 1696 /* InBound9 Source */ /* MX-A4 [6:4] */ 1697 static const char * const rt5677_inbound9_src[] = { 1698 "STO1 ADC MIX R", "STO2 ADC MIX R", "STO3 ADC MIX R", "STO4 ADC MIX R", 1699 "MONO ADC MIX R", "DACR1 FS", "DAC1 FS" 1700 }; 1701 1702 static SOC_ENUM_SINGLE_DECL( 1703 rt5677_inbound9_enum, RT5677_DSP_INB_CTRL2, 1704 RT5677_IB9_SRC_SFT, rt5677_inbound9_src); 1705 1706 static const struct snd_kcontrol_new rt5677_ib9_src_mux = 1707 SOC_DAPM_ENUM("InBound9 Source", rt5677_inbound9_enum); 1708 1709 /* VAD Source */ /* MX-9F [6:4] */ 1710 static const char * const rt5677_vad_src[] = { 1711 "STO1 ADC MIX L", "MONO ADC MIX L", "MONO ADC MIX R", "STO2 ADC MIX L", 1712 "STO3 ADC MIX L" 1713 }; 1714 1715 static SOC_ENUM_SINGLE_DECL( 1716 rt5677_vad_enum, RT5677_VAD_CTRL4, 1717 RT5677_VAD_SRC_SFT, rt5677_vad_src); 1718 1719 static const struct snd_kcontrol_new rt5677_vad_src_mux = 1720 SOC_DAPM_ENUM("VAD Source", rt5677_vad_enum); 1721 1722 /* Sidetone Source */ /* MX-13 [11:9] */ 1723 static const char * const rt5677_sidetone_src[] = { 1724 "DMIC1 L", "DMIC2 L", "DMIC3 L", "DMIC4 L", "ADC1", "ADC2" 1725 }; 1726 1727 static SOC_ENUM_SINGLE_DECL( 1728 rt5677_sidetone_enum, RT5677_SIDETONE_CTRL, 1729 RT5677_ST_SEL_SFT, rt5677_sidetone_src); 1730 1731 static const struct snd_kcontrol_new rt5677_sidetone_mux = 1732 SOC_DAPM_ENUM("Sidetone Source", rt5677_sidetone_enum); 1733 1734 /* DAC1/2 Source */ /* MX-15 [1:0] */ 1735 static const char * const rt5677_dac12_src[] = { 1736 "STO1 DAC MIX", "MONO DAC MIX", "DD MIX1", "DD MIX2" 1737 }; 1738 1739 static SOC_ENUM_SINGLE_DECL( 1740 rt5677_dac12_enum, RT5677_ANA_DAC1_2_3_SRC, 1741 RT5677_ANA_DAC1_2_SRC_SEL_SFT, rt5677_dac12_src); 1742 1743 static const struct snd_kcontrol_new rt5677_dac12_mux = 1744 SOC_DAPM_ENUM("Analog DAC1/2 Source", rt5677_dac12_enum); 1745 1746 /* DAC3 Source */ /* MX-15 [5:4] */ 1747 static const char * const rt5677_dac3_src[] = { 1748 "MONO DAC MIXL", "MONO DAC MIXR", "DD MIX1L", "DD MIX2L" 1749 }; 1750 1751 static SOC_ENUM_SINGLE_DECL( 1752 rt5677_dac3_enum, RT5677_ANA_DAC1_2_3_SRC, 1753 RT5677_ANA_DAC3_SRC_SEL_SFT, rt5677_dac3_src); 1754 1755 static const struct snd_kcontrol_new rt5677_dac3_mux = 1756 SOC_DAPM_ENUM("Analog DAC3 Source", rt5677_dac3_enum); 1757 1758 /* PDM channel Source */ /* MX-31 [13:12][9:8][5:4][1:0] */ 1759 static const char * const rt5677_pdm_src[] = { 1760 "STO1 DAC MIX", "MONO DAC MIX", "DD MIX1", "DD MIX2" 1761 }; 1762 1763 static SOC_ENUM_SINGLE_DECL( 1764 rt5677_pdm1_l_enum, RT5677_PDM_OUT_CTRL, 1765 RT5677_SEL_PDM1_L_SFT, rt5677_pdm_src); 1766 1767 static const struct snd_kcontrol_new rt5677_pdm1_l_mux = 1768 SOC_DAPM_ENUM("PDM1 Source", rt5677_pdm1_l_enum); 1769 1770 static SOC_ENUM_SINGLE_DECL( 1771 rt5677_pdm2_l_enum, RT5677_PDM_OUT_CTRL, 1772 RT5677_SEL_PDM2_L_SFT, rt5677_pdm_src); 1773 1774 static const struct snd_kcontrol_new rt5677_pdm2_l_mux = 1775 SOC_DAPM_ENUM("PDM2 Source", rt5677_pdm2_l_enum); 1776 1777 static SOC_ENUM_SINGLE_DECL( 1778 rt5677_pdm1_r_enum, RT5677_PDM_OUT_CTRL, 1779 RT5677_SEL_PDM1_R_SFT, rt5677_pdm_src); 1780 1781 static const struct snd_kcontrol_new rt5677_pdm1_r_mux = 1782 SOC_DAPM_ENUM("PDM1 Source", rt5677_pdm1_r_enum); 1783 1784 static SOC_ENUM_SINGLE_DECL( 1785 rt5677_pdm2_r_enum, RT5677_PDM_OUT_CTRL, 1786 RT5677_SEL_PDM2_R_SFT, rt5677_pdm_src); 1787 1788 static const struct snd_kcontrol_new rt5677_pdm2_r_mux = 1789 SOC_DAPM_ENUM("PDM2 Source", rt5677_pdm2_r_enum); 1790 1791 /* TDM IF1/2 SLB ADC1 Data Selection */ /* MX-3C MX-41 [5:4] MX-08 [1:0] */ 1792 static const char * const rt5677_if12_adc1_src[] = { 1793 "STO1 ADC MIX", "OB01", "VAD ADC" 1794 }; 1795 1796 static SOC_ENUM_SINGLE_DECL( 1797 rt5677_if1_adc1_enum, RT5677_TDM1_CTRL2, 1798 RT5677_IF1_ADC1_SFT, rt5677_if12_adc1_src); 1799 1800 static const struct snd_kcontrol_new rt5677_if1_adc1_mux = 1801 SOC_DAPM_ENUM("IF1 ADC1 Source", rt5677_if1_adc1_enum); 1802 1803 static SOC_ENUM_SINGLE_DECL( 1804 rt5677_if2_adc1_enum, RT5677_TDM2_CTRL2, 1805 RT5677_IF2_ADC1_SFT, rt5677_if12_adc1_src); 1806 1807 static const struct snd_kcontrol_new rt5677_if2_adc1_mux = 1808 SOC_DAPM_ENUM("IF2 ADC1 Source", rt5677_if2_adc1_enum); 1809 1810 static SOC_ENUM_SINGLE_DECL( 1811 rt5677_slb_adc1_enum, RT5677_SLIMBUS_RX, 1812 RT5677_SLB_ADC1_SFT, rt5677_if12_adc1_src); 1813 1814 static const struct snd_kcontrol_new rt5677_slb_adc1_mux = 1815 SOC_DAPM_ENUM("SLB ADC1 Source", rt5677_slb_adc1_enum); 1816 1817 /* TDM IF1/2 SLB ADC2 Data Selection */ /* MX-3C MX-41 [7:6] MX-08 [3:2] */ 1818 static const char * const rt5677_if12_adc2_src[] = { 1819 "STO2 ADC MIX", "OB23" 1820 }; 1821 1822 static SOC_ENUM_SINGLE_DECL( 1823 rt5677_if1_adc2_enum, RT5677_TDM1_CTRL2, 1824 RT5677_IF1_ADC2_SFT, rt5677_if12_adc2_src); 1825 1826 static const struct snd_kcontrol_new rt5677_if1_adc2_mux = 1827 SOC_DAPM_ENUM("IF1 ADC2 Source", rt5677_if1_adc2_enum); 1828 1829 static SOC_ENUM_SINGLE_DECL( 1830 rt5677_if2_adc2_enum, RT5677_TDM2_CTRL2, 1831 RT5677_IF2_ADC2_SFT, rt5677_if12_adc2_src); 1832 1833 static const struct snd_kcontrol_new rt5677_if2_adc2_mux = 1834 SOC_DAPM_ENUM("IF2 ADC2 Source", rt5677_if2_adc2_enum); 1835 1836 static SOC_ENUM_SINGLE_DECL( 1837 rt5677_slb_adc2_enum, RT5677_SLIMBUS_RX, 1838 RT5677_SLB_ADC2_SFT, rt5677_if12_adc2_src); 1839 1840 static const struct snd_kcontrol_new rt5677_slb_adc2_mux = 1841 SOC_DAPM_ENUM("SLB ADC2 Source", rt5677_slb_adc2_enum); 1842 1843 /* TDM IF1/2 SLB ADC3 Data Selection */ /* MX-3C MX-41 [9:8] MX-08 [5:4] */ 1844 static const char * const rt5677_if12_adc3_src[] = { 1845 "STO3 ADC MIX", "MONO ADC MIX", "OB45" 1846 }; 1847 1848 static SOC_ENUM_SINGLE_DECL( 1849 rt5677_if1_adc3_enum, RT5677_TDM1_CTRL2, 1850 RT5677_IF1_ADC3_SFT, rt5677_if12_adc3_src); 1851 1852 static const struct snd_kcontrol_new rt5677_if1_adc3_mux = 1853 SOC_DAPM_ENUM("IF1 ADC3 Source", rt5677_if1_adc3_enum); 1854 1855 static SOC_ENUM_SINGLE_DECL( 1856 rt5677_if2_adc3_enum, RT5677_TDM2_CTRL2, 1857 RT5677_IF2_ADC3_SFT, rt5677_if12_adc3_src); 1858 1859 static const struct snd_kcontrol_new rt5677_if2_adc3_mux = 1860 SOC_DAPM_ENUM("IF2 ADC3 Source", rt5677_if2_adc3_enum); 1861 1862 static SOC_ENUM_SINGLE_DECL( 1863 rt5677_slb_adc3_enum, RT5677_SLIMBUS_RX, 1864 RT5677_SLB_ADC3_SFT, rt5677_if12_adc3_src); 1865 1866 static const struct snd_kcontrol_new rt5677_slb_adc3_mux = 1867 SOC_DAPM_ENUM("SLB ADC3 Source", rt5677_slb_adc3_enum); 1868 1869 /* TDM IF1/2 SLB ADC4 Data Selection */ /* MX-3C MX-41 [11:10] MX-08 [7:6] */ 1870 static const char * const rt5677_if12_adc4_src[] = { 1871 "STO4 ADC MIX", "OB67", "OB01" 1872 }; 1873 1874 static SOC_ENUM_SINGLE_DECL( 1875 rt5677_if1_adc4_enum, RT5677_TDM1_CTRL2, 1876 RT5677_IF1_ADC4_SFT, rt5677_if12_adc4_src); 1877 1878 static const struct snd_kcontrol_new rt5677_if1_adc4_mux = 1879 SOC_DAPM_ENUM("IF1 ADC4 Source", rt5677_if1_adc4_enum); 1880 1881 static SOC_ENUM_SINGLE_DECL( 1882 rt5677_if2_adc4_enum, RT5677_TDM2_CTRL2, 1883 RT5677_IF2_ADC4_SFT, rt5677_if12_adc4_src); 1884 1885 static const struct snd_kcontrol_new rt5677_if2_adc4_mux = 1886 SOC_DAPM_ENUM("IF2 ADC4 Source", rt5677_if2_adc4_enum); 1887 1888 static SOC_ENUM_SINGLE_DECL( 1889 rt5677_slb_adc4_enum, RT5677_SLIMBUS_RX, 1890 RT5677_SLB_ADC4_SFT, rt5677_if12_adc4_src); 1891 1892 static const struct snd_kcontrol_new rt5677_slb_adc4_mux = 1893 SOC_DAPM_ENUM("SLB ADC4 Source", rt5677_slb_adc4_enum); 1894 1895 /* Interface3/4 ADC Data Input */ /* MX-2F [3:0] MX-30 [7:4] */ 1896 static const char * const rt5677_if34_adc_src[] = { 1897 "STO1 ADC MIX", "STO2 ADC MIX", "STO3 ADC MIX", "STO4 ADC MIX", 1898 "MONO ADC MIX", "OB01", "OB23", "VAD ADC" 1899 }; 1900 1901 static SOC_ENUM_SINGLE_DECL( 1902 rt5677_if3_adc_enum, RT5677_IF3_DATA, 1903 RT5677_IF3_ADC_IN_SFT, rt5677_if34_adc_src); 1904 1905 static const struct snd_kcontrol_new rt5677_if3_adc_mux = 1906 SOC_DAPM_ENUM("IF3 ADC Source", rt5677_if3_adc_enum); 1907 1908 static SOC_ENUM_SINGLE_DECL( 1909 rt5677_if4_adc_enum, RT5677_IF4_DATA, 1910 RT5677_IF4_ADC_IN_SFT, rt5677_if34_adc_src); 1911 1912 static const struct snd_kcontrol_new rt5677_if4_adc_mux = 1913 SOC_DAPM_ENUM("IF4 ADC Source", rt5677_if4_adc_enum); 1914 1915 /* TDM IF1/2 ADC Data Selection */ /* MX-3B MX-40 [7:6][5:4][3:2][1:0] */ 1916 static const char * const rt5677_if12_adc_swap_src[] = { 1917 "L/R", "R/L", "L/L", "R/R" 1918 }; 1919 1920 static SOC_ENUM_SINGLE_DECL( 1921 rt5677_if1_adc1_swap_enum, RT5677_TDM1_CTRL1, 1922 RT5677_IF1_ADC1_SWAP_SFT, rt5677_if12_adc_swap_src); 1923 1924 static const struct snd_kcontrol_new rt5677_if1_adc1_swap_mux = 1925 SOC_DAPM_ENUM("IF1 ADC1 Swap Source", rt5677_if1_adc1_swap_enum); 1926 1927 static SOC_ENUM_SINGLE_DECL( 1928 rt5677_if1_adc2_swap_enum, RT5677_TDM1_CTRL1, 1929 RT5677_IF1_ADC2_SWAP_SFT, rt5677_if12_adc_swap_src); 1930 1931 static const struct snd_kcontrol_new rt5677_if1_adc2_swap_mux = 1932 SOC_DAPM_ENUM("IF1 ADC2 Swap Source", rt5677_if1_adc2_swap_enum); 1933 1934 static SOC_ENUM_SINGLE_DECL( 1935 rt5677_if1_adc3_swap_enum, RT5677_TDM1_CTRL1, 1936 RT5677_IF1_ADC3_SWAP_SFT, rt5677_if12_adc_swap_src); 1937 1938 static const struct snd_kcontrol_new rt5677_if1_adc3_swap_mux = 1939 SOC_DAPM_ENUM("IF1 ADC3 Swap Source", rt5677_if1_adc3_swap_enum); 1940 1941 static SOC_ENUM_SINGLE_DECL( 1942 rt5677_if1_adc4_swap_enum, RT5677_TDM1_CTRL1, 1943 RT5677_IF1_ADC4_SWAP_SFT, rt5677_if12_adc_swap_src); 1944 1945 static const struct snd_kcontrol_new rt5677_if1_adc4_swap_mux = 1946 SOC_DAPM_ENUM("IF1 ADC4 Swap Source", rt5677_if1_adc4_swap_enum); 1947 1948 static SOC_ENUM_SINGLE_DECL( 1949 rt5677_if2_adc1_swap_enum, RT5677_TDM2_CTRL1, 1950 RT5677_IF1_ADC2_SWAP_SFT, rt5677_if12_adc_swap_src); 1951 1952 static const struct snd_kcontrol_new rt5677_if2_adc1_swap_mux = 1953 SOC_DAPM_ENUM("IF1 ADC2 Swap Source", rt5677_if2_adc1_swap_enum); 1954 1955 static SOC_ENUM_SINGLE_DECL( 1956 rt5677_if2_adc2_swap_enum, RT5677_TDM2_CTRL1, 1957 RT5677_IF2_ADC2_SWAP_SFT, rt5677_if12_adc_swap_src); 1958 1959 static const struct snd_kcontrol_new rt5677_if2_adc2_swap_mux = 1960 SOC_DAPM_ENUM("IF2 ADC2 Swap Source", rt5677_if2_adc2_swap_enum); 1961 1962 static SOC_ENUM_SINGLE_DECL( 1963 rt5677_if2_adc3_swap_enum, RT5677_TDM2_CTRL1, 1964 RT5677_IF2_ADC3_SWAP_SFT, rt5677_if12_adc_swap_src); 1965 1966 static const struct snd_kcontrol_new rt5677_if2_adc3_swap_mux = 1967 SOC_DAPM_ENUM("IF2 ADC3 Swap Source", rt5677_if2_adc3_swap_enum); 1968 1969 static SOC_ENUM_SINGLE_DECL( 1970 rt5677_if2_adc4_swap_enum, RT5677_TDM2_CTRL1, 1971 RT5677_IF2_ADC4_SWAP_SFT, rt5677_if12_adc_swap_src); 1972 1973 static const struct snd_kcontrol_new rt5677_if2_adc4_swap_mux = 1974 SOC_DAPM_ENUM("IF2 ADC4 Swap Source", rt5677_if2_adc4_swap_enum); 1975 1976 /* TDM IF1 ADC Data Selection */ /* MX-3C [2:0] */ 1977 static const char * const rt5677_if1_adc_tdm_swap_src[] = { 1978 "1/2/3/4", "2/1/3/4", "2/3/1/4", "4/1/2/3", "1/3/2/4", "1/4/2/3", 1979 "3/1/2/4", "3/4/1/2" 1980 }; 1981 1982 static SOC_ENUM_SINGLE_DECL( 1983 rt5677_if1_adc_tdm_swap_enum, RT5677_TDM1_CTRL2, 1984 RT5677_IF1_ADC_CTRL_SFT, rt5677_if1_adc_tdm_swap_src); 1985 1986 static const struct snd_kcontrol_new rt5677_if1_adc_tdm_swap_mux = 1987 SOC_DAPM_ENUM("IF1 ADC TDM Swap Source", rt5677_if1_adc_tdm_swap_enum); 1988 1989 /* TDM IF2 ADC Data Selection */ /* MX-41[2:0] */ 1990 static const char * const rt5677_if2_adc_tdm_swap_src[] = { 1991 "1/2/3/4", "2/1/3/4", "3/1/2/4", "4/1/2/3", "1/3/2/4", "1/4/2/3", 1992 "2/3/1/4", "3/4/1/2" 1993 }; 1994 1995 static SOC_ENUM_SINGLE_DECL( 1996 rt5677_if2_adc_tdm_swap_enum, RT5677_TDM2_CTRL2, 1997 RT5677_IF2_ADC_CTRL_SFT, rt5677_if2_adc_tdm_swap_src); 1998 1999 static const struct snd_kcontrol_new rt5677_if2_adc_tdm_swap_mux = 2000 SOC_DAPM_ENUM("IF2 ADC TDM Swap Source", rt5677_if2_adc_tdm_swap_enum); 2001 2002 /* TDM IF1/2 DAC Data Selection */ /* MX-3E[14:12][10:8][6:4][2:0] 2003 MX-3F[14:12][10:8][6:4][2:0] 2004 MX-43[14:12][10:8][6:4][2:0] 2005 MX-44[14:12][10:8][6:4][2:0] */ 2006 static const char * const rt5677_if12_dac_tdm_sel_src[] = { 2007 "Slot0", "Slot1", "Slot2", "Slot3", "Slot4", "Slot5", "Slot6", "Slot7" 2008 }; 2009 2010 static SOC_ENUM_SINGLE_DECL( 2011 rt5677_if1_dac0_tdm_sel_enum, RT5677_TDM1_CTRL4, 2012 RT5677_IF1_DAC0_SFT, rt5677_if12_dac_tdm_sel_src); 2013 2014 static const struct snd_kcontrol_new rt5677_if1_dac0_tdm_sel_mux = 2015 SOC_DAPM_ENUM("IF1 DAC0 TDM Source", rt5677_if1_dac0_tdm_sel_enum); 2016 2017 static SOC_ENUM_SINGLE_DECL( 2018 rt5677_if1_dac1_tdm_sel_enum, RT5677_TDM1_CTRL4, 2019 RT5677_IF1_DAC1_SFT, rt5677_if12_dac_tdm_sel_src); 2020 2021 static const struct snd_kcontrol_new rt5677_if1_dac1_tdm_sel_mux = 2022 SOC_DAPM_ENUM("IF1 DAC1 TDM Source", rt5677_if1_dac1_tdm_sel_enum); 2023 2024 static SOC_ENUM_SINGLE_DECL( 2025 rt5677_if1_dac2_tdm_sel_enum, RT5677_TDM1_CTRL4, 2026 RT5677_IF1_DAC2_SFT, rt5677_if12_dac_tdm_sel_src); 2027 2028 static const struct snd_kcontrol_new rt5677_if1_dac2_tdm_sel_mux = 2029 SOC_DAPM_ENUM("IF1 DAC2 TDM Source", rt5677_if1_dac2_tdm_sel_enum); 2030 2031 static SOC_ENUM_SINGLE_DECL( 2032 rt5677_if1_dac3_tdm_sel_enum, RT5677_TDM1_CTRL4, 2033 RT5677_IF1_DAC3_SFT, rt5677_if12_dac_tdm_sel_src); 2034 2035 static const struct snd_kcontrol_new rt5677_if1_dac3_tdm_sel_mux = 2036 SOC_DAPM_ENUM("IF1 DAC3 TDM Source", rt5677_if1_dac3_tdm_sel_enum); 2037 2038 static SOC_ENUM_SINGLE_DECL( 2039 rt5677_if1_dac4_tdm_sel_enum, RT5677_TDM1_CTRL5, 2040 RT5677_IF1_DAC4_SFT, rt5677_if12_dac_tdm_sel_src); 2041 2042 static const struct snd_kcontrol_new rt5677_if1_dac4_tdm_sel_mux = 2043 SOC_DAPM_ENUM("IF1 DAC4 TDM Source", rt5677_if1_dac4_tdm_sel_enum); 2044 2045 static SOC_ENUM_SINGLE_DECL( 2046 rt5677_if1_dac5_tdm_sel_enum, RT5677_TDM1_CTRL5, 2047 RT5677_IF1_DAC5_SFT, rt5677_if12_dac_tdm_sel_src); 2048 2049 static const struct snd_kcontrol_new rt5677_if1_dac5_tdm_sel_mux = 2050 SOC_DAPM_ENUM("IF1 DAC5 TDM Source", rt5677_if1_dac5_tdm_sel_enum); 2051 2052 static SOC_ENUM_SINGLE_DECL( 2053 rt5677_if1_dac6_tdm_sel_enum, RT5677_TDM1_CTRL5, 2054 RT5677_IF1_DAC6_SFT, rt5677_if12_dac_tdm_sel_src); 2055 2056 static const struct snd_kcontrol_new rt5677_if1_dac6_tdm_sel_mux = 2057 SOC_DAPM_ENUM("IF1 DAC6 TDM Source", rt5677_if1_dac6_tdm_sel_enum); 2058 2059 static SOC_ENUM_SINGLE_DECL( 2060 rt5677_if1_dac7_tdm_sel_enum, RT5677_TDM1_CTRL5, 2061 RT5677_IF1_DAC7_SFT, rt5677_if12_dac_tdm_sel_src); 2062 2063 static const struct snd_kcontrol_new rt5677_if1_dac7_tdm_sel_mux = 2064 SOC_DAPM_ENUM("IF1 DAC7 TDM Source", rt5677_if1_dac7_tdm_sel_enum); 2065 2066 static SOC_ENUM_SINGLE_DECL( 2067 rt5677_if2_dac0_tdm_sel_enum, RT5677_TDM2_CTRL4, 2068 RT5677_IF2_DAC0_SFT, rt5677_if12_dac_tdm_sel_src); 2069 2070 static const struct snd_kcontrol_new rt5677_if2_dac0_tdm_sel_mux = 2071 SOC_DAPM_ENUM("IF2 DAC0 TDM Source", rt5677_if2_dac0_tdm_sel_enum); 2072 2073 static SOC_ENUM_SINGLE_DECL( 2074 rt5677_if2_dac1_tdm_sel_enum, RT5677_TDM2_CTRL4, 2075 RT5677_IF2_DAC1_SFT, rt5677_if12_dac_tdm_sel_src); 2076 2077 static const struct snd_kcontrol_new rt5677_if2_dac1_tdm_sel_mux = 2078 SOC_DAPM_ENUM("IF2 DAC1 TDM Source", rt5677_if2_dac1_tdm_sel_enum); 2079 2080 static SOC_ENUM_SINGLE_DECL( 2081 rt5677_if2_dac2_tdm_sel_enum, RT5677_TDM2_CTRL4, 2082 RT5677_IF2_DAC2_SFT, rt5677_if12_dac_tdm_sel_src); 2083 2084 static const struct snd_kcontrol_new rt5677_if2_dac2_tdm_sel_mux = 2085 SOC_DAPM_ENUM("IF2 DAC2 TDM Source", rt5677_if2_dac2_tdm_sel_enum); 2086 2087 static SOC_ENUM_SINGLE_DECL( 2088 rt5677_if2_dac3_tdm_sel_enum, RT5677_TDM2_CTRL4, 2089 RT5677_IF2_DAC3_SFT, rt5677_if12_dac_tdm_sel_src); 2090 2091 static const struct snd_kcontrol_new rt5677_if2_dac3_tdm_sel_mux = 2092 SOC_DAPM_ENUM("IF2 DAC3 TDM Source", rt5677_if2_dac3_tdm_sel_enum); 2093 2094 static SOC_ENUM_SINGLE_DECL( 2095 rt5677_if2_dac4_tdm_sel_enum, RT5677_TDM2_CTRL5, 2096 RT5677_IF2_DAC4_SFT, rt5677_if12_dac_tdm_sel_src); 2097 2098 static const struct snd_kcontrol_new rt5677_if2_dac4_tdm_sel_mux = 2099 SOC_DAPM_ENUM("IF2 DAC4 TDM Source", rt5677_if2_dac4_tdm_sel_enum); 2100 2101 static SOC_ENUM_SINGLE_DECL( 2102 rt5677_if2_dac5_tdm_sel_enum, RT5677_TDM2_CTRL5, 2103 RT5677_IF2_DAC5_SFT, rt5677_if12_dac_tdm_sel_src); 2104 2105 static const struct snd_kcontrol_new rt5677_if2_dac5_tdm_sel_mux = 2106 SOC_DAPM_ENUM("IF2 DAC5 TDM Source", rt5677_if2_dac5_tdm_sel_enum); 2107 2108 static SOC_ENUM_SINGLE_DECL( 2109 rt5677_if2_dac6_tdm_sel_enum, RT5677_TDM2_CTRL5, 2110 RT5677_IF2_DAC6_SFT, rt5677_if12_dac_tdm_sel_src); 2111 2112 static const struct snd_kcontrol_new rt5677_if2_dac6_tdm_sel_mux = 2113 SOC_DAPM_ENUM("IF2 DAC6 TDM Source", rt5677_if2_dac6_tdm_sel_enum); 2114 2115 static SOC_ENUM_SINGLE_DECL( 2116 rt5677_if2_dac7_tdm_sel_enum, RT5677_TDM2_CTRL5, 2117 RT5677_IF2_DAC7_SFT, rt5677_if12_dac_tdm_sel_src); 2118 2119 static const struct snd_kcontrol_new rt5677_if2_dac7_tdm_sel_mux = 2120 SOC_DAPM_ENUM("IF2 DAC7 TDM Source", rt5677_if2_dac7_tdm_sel_enum); 2121 2122 static int rt5677_bst1_event(struct snd_soc_dapm_widget *w, 2123 struct snd_kcontrol *kcontrol, int event) 2124 { 2125 struct snd_soc_codec *codec = w->codec; 2126 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec); 2127 2128 switch (event) { 2129 case SND_SOC_DAPM_POST_PMU: 2130 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2, 2131 RT5677_PWR_BST1_P, RT5677_PWR_BST1_P); 2132 break; 2133 2134 case SND_SOC_DAPM_PRE_PMD: 2135 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2, 2136 RT5677_PWR_BST1_P, 0); 2137 break; 2138 2139 default: 2140 return 0; 2141 } 2142 2143 return 0; 2144 } 2145 2146 static int rt5677_bst2_event(struct snd_soc_dapm_widget *w, 2147 struct snd_kcontrol *kcontrol, int event) 2148 { 2149 struct snd_soc_codec *codec = w->codec; 2150 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec); 2151 2152 switch (event) { 2153 case SND_SOC_DAPM_POST_PMU: 2154 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2, 2155 RT5677_PWR_BST2_P, RT5677_PWR_BST2_P); 2156 break; 2157 2158 case SND_SOC_DAPM_PRE_PMD: 2159 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2, 2160 RT5677_PWR_BST2_P, 0); 2161 break; 2162 2163 default: 2164 return 0; 2165 } 2166 2167 return 0; 2168 } 2169 2170 static int rt5677_set_pll1_event(struct snd_soc_dapm_widget *w, 2171 struct snd_kcontrol *kcontrol, int event) 2172 { 2173 struct snd_soc_codec *codec = w->codec; 2174 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec); 2175 2176 switch (event) { 2177 case SND_SOC_DAPM_PRE_PMU: 2178 regmap_update_bits(rt5677->regmap, RT5677_PLL1_CTRL2, 0x2, 0x2); 2179 break; 2180 2181 case SND_SOC_DAPM_POST_PMU: 2182 regmap_update_bits(rt5677->regmap, RT5677_PLL1_CTRL2, 0x2, 0x0); 2183 break; 2184 2185 default: 2186 return 0; 2187 } 2188 2189 return 0; 2190 } 2191 2192 static int rt5677_set_pll2_event(struct snd_soc_dapm_widget *w, 2193 struct snd_kcontrol *kcontrol, int event) 2194 { 2195 struct snd_soc_codec *codec = w->codec; 2196 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec); 2197 2198 switch (event) { 2199 case SND_SOC_DAPM_PRE_PMU: 2200 regmap_update_bits(rt5677->regmap, RT5677_PLL2_CTRL2, 0x2, 0x2); 2201 break; 2202 2203 case SND_SOC_DAPM_POST_PMU: 2204 regmap_update_bits(rt5677->regmap, RT5677_PLL2_CTRL2, 0x2, 0x0); 2205 break; 2206 2207 default: 2208 return 0; 2209 } 2210 2211 return 0; 2212 } 2213 2214 static int rt5677_set_micbias1_event(struct snd_soc_dapm_widget *w, 2215 struct snd_kcontrol *kcontrol, int event) 2216 { 2217 struct snd_soc_codec *codec = w->codec; 2218 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec); 2219 2220 switch (event) { 2221 case SND_SOC_DAPM_POST_PMU: 2222 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2, 2223 RT5677_PWR_CLK_MB1 | RT5677_PWR_PP_MB1 | 2224 RT5677_PWR_CLK_MB, RT5677_PWR_CLK_MB1 | 2225 RT5677_PWR_PP_MB1 | RT5677_PWR_CLK_MB); 2226 break; 2227 2228 case SND_SOC_DAPM_PRE_PMD: 2229 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2, 2230 RT5677_PWR_CLK_MB1 | RT5677_PWR_PP_MB1 | 2231 RT5677_PWR_CLK_MB, 0); 2232 break; 2233 2234 default: 2235 return 0; 2236 } 2237 2238 return 0; 2239 } 2240 2241 static int rt5677_if1_adc_tdm_event(struct snd_soc_dapm_widget *w, 2242 struct snd_kcontrol *kcontrol, int event) 2243 { 2244 struct snd_soc_codec *codec = w->codec; 2245 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec); 2246 unsigned int value; 2247 2248 switch (event) { 2249 case SND_SOC_DAPM_PRE_PMU: 2250 regmap_read(rt5677->regmap, RT5677_TDM1_CTRL2, &value); 2251 if (value & RT5677_IF1_ADC_CTRL_MASK) 2252 regmap_update_bits(rt5677->regmap, RT5677_TDM1_CTRL1, 2253 RT5677_IF1_ADC_MODE_MASK, 2254 RT5677_IF1_ADC_MODE_TDM); 2255 break; 2256 2257 default: 2258 return 0; 2259 } 2260 2261 return 0; 2262 } 2263 2264 static int rt5677_if2_adc_tdm_event(struct snd_soc_dapm_widget *w, 2265 struct snd_kcontrol *kcontrol, int event) 2266 { 2267 struct snd_soc_codec *codec = w->codec; 2268 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec); 2269 unsigned int value; 2270 2271 switch (event) { 2272 case SND_SOC_DAPM_PRE_PMU: 2273 regmap_read(rt5677->regmap, RT5677_TDM2_CTRL2, &value); 2274 if (value & RT5677_IF2_ADC_CTRL_MASK) 2275 regmap_update_bits(rt5677->regmap, RT5677_TDM2_CTRL1, 2276 RT5677_IF2_ADC_MODE_MASK, 2277 RT5677_IF2_ADC_MODE_TDM); 2278 break; 2279 2280 default: 2281 return 0; 2282 } 2283 2284 return 0; 2285 } 2286 2287 static int rt5677_vref_event(struct snd_soc_dapm_widget *w, 2288 struct snd_kcontrol *kcontrol, int event) 2289 { 2290 struct snd_soc_codec *codec = w->codec; 2291 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec); 2292 2293 switch (event) { 2294 case SND_SOC_DAPM_POST_PMU: 2295 if (codec->dapm.bias_level != SND_SOC_BIAS_ON && 2296 !rt5677->is_vref_slow) { 2297 mdelay(20); 2298 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1, 2299 RT5677_PWR_FV1 | RT5677_PWR_FV2, 2300 RT5677_PWR_FV1 | RT5677_PWR_FV2); 2301 rt5677->is_vref_slow = true; 2302 } 2303 break; 2304 2305 default: 2306 return 0; 2307 } 2308 2309 return 0; 2310 } 2311 2312 static const struct snd_soc_dapm_widget rt5677_dapm_widgets[] = { 2313 SND_SOC_DAPM_SUPPLY("PLL1", RT5677_PWR_ANLG2, RT5677_PWR_PLL1_BIT, 2314 0, rt5677_set_pll1_event, SND_SOC_DAPM_PRE_PMU | 2315 SND_SOC_DAPM_POST_PMU), 2316 SND_SOC_DAPM_SUPPLY("PLL2", RT5677_PWR_ANLG2, RT5677_PWR_PLL2_BIT, 2317 0, rt5677_set_pll2_event, SND_SOC_DAPM_PRE_PMU | 2318 SND_SOC_DAPM_POST_PMU), 2319 2320 /* ASRC */ 2321 SND_SOC_DAPM_SUPPLY_S("I2S1 ASRC", 1, RT5677_ASRC_1, 0, 0, NULL, 0), 2322 SND_SOC_DAPM_SUPPLY_S("I2S2 ASRC", 1, RT5677_ASRC_1, 1, 0, NULL, 0), 2323 SND_SOC_DAPM_SUPPLY_S("I2S3 ASRC", 1, RT5677_ASRC_1, 2, 0, NULL, 0), 2324 SND_SOC_DAPM_SUPPLY_S("I2S4 ASRC", 1, RT5677_ASRC_1, 3, 0, NULL, 0), 2325 SND_SOC_DAPM_SUPPLY_S("DAC STO ASRC", 1, RT5677_ASRC_2, 14, 0, NULL, 0), 2326 SND_SOC_DAPM_SUPPLY_S("DAC MONO2 L ASRC", 1, RT5677_ASRC_2, 13, 0, NULL, 2327 0), 2328 SND_SOC_DAPM_SUPPLY_S("DAC MONO2 R ASRC", 1, RT5677_ASRC_2, 12, 0, NULL, 2329 0), 2330 SND_SOC_DAPM_SUPPLY_S("DAC MONO3 L ASRC", 1, RT5677_ASRC_1, 15, 0, NULL, 2331 0), 2332 SND_SOC_DAPM_SUPPLY_S("DAC MONO3 R ASRC", 1, RT5677_ASRC_1, 14, 0, NULL, 2333 0), 2334 SND_SOC_DAPM_SUPPLY_S("DAC MONO4 L ASRC", 1, RT5677_ASRC_1, 13, 0, NULL, 2335 0), 2336 SND_SOC_DAPM_SUPPLY_S("DAC MONO4 R ASRC", 1, RT5677_ASRC_1, 12, 0, NULL, 2337 0), 2338 SND_SOC_DAPM_SUPPLY_S("DMIC STO1 ASRC", 1, RT5677_ASRC_2, 11, 0, NULL, 2339 0), 2340 SND_SOC_DAPM_SUPPLY_S("DMIC STO2 ASRC", 1, RT5677_ASRC_2, 10, 0, NULL, 2341 0), 2342 SND_SOC_DAPM_SUPPLY_S("DMIC STO3 ASRC", 1, RT5677_ASRC_2, 9, 0, NULL, 2343 0), 2344 SND_SOC_DAPM_SUPPLY_S("DMIC STO4 ASRC", 1, RT5677_ASRC_2, 8, 0, NULL, 2345 0), 2346 SND_SOC_DAPM_SUPPLY_S("DMIC MONO L ASRC", 1, RT5677_ASRC_2, 7, 0, NULL, 2347 0), 2348 SND_SOC_DAPM_SUPPLY_S("DMIC MONO R ASRC", 1, RT5677_ASRC_2, 6, 0, NULL, 2349 0), 2350 SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5677_ASRC_2, 5, 0, NULL, 0), 2351 SND_SOC_DAPM_SUPPLY_S("ADC STO2 ASRC", 1, RT5677_ASRC_2, 4, 0, NULL, 0), 2352 SND_SOC_DAPM_SUPPLY_S("ADC STO3 ASRC", 1, RT5677_ASRC_2, 3, 0, NULL, 0), 2353 SND_SOC_DAPM_SUPPLY_S("ADC STO4 ASRC", 1, RT5677_ASRC_2, 2, 0, NULL, 0), 2354 SND_SOC_DAPM_SUPPLY_S("ADC MONO L ASRC", 1, RT5677_ASRC_2, 1, 0, NULL, 2355 0), 2356 SND_SOC_DAPM_SUPPLY_S("ADC MONO R ASRC", 1, RT5677_ASRC_2, 0, 0, NULL, 2357 0), 2358 2359 /* Input Side */ 2360 /* micbias */ 2361 SND_SOC_DAPM_SUPPLY("MICBIAS1", RT5677_PWR_ANLG2, RT5677_PWR_MB1_BIT, 2362 0, rt5677_set_micbias1_event, SND_SOC_DAPM_PRE_PMD | 2363 SND_SOC_DAPM_POST_PMU), 2364 2365 /* Input Lines */ 2366 SND_SOC_DAPM_INPUT("DMIC L1"), 2367 SND_SOC_DAPM_INPUT("DMIC R1"), 2368 SND_SOC_DAPM_INPUT("DMIC L2"), 2369 SND_SOC_DAPM_INPUT("DMIC R2"), 2370 SND_SOC_DAPM_INPUT("DMIC L3"), 2371 SND_SOC_DAPM_INPUT("DMIC R3"), 2372 SND_SOC_DAPM_INPUT("DMIC L4"), 2373 SND_SOC_DAPM_INPUT("DMIC R4"), 2374 2375 SND_SOC_DAPM_INPUT("IN1P"), 2376 SND_SOC_DAPM_INPUT("IN1N"), 2377 SND_SOC_DAPM_INPUT("IN2P"), 2378 SND_SOC_DAPM_INPUT("IN2N"), 2379 2380 SND_SOC_DAPM_INPUT("Haptic Generator"), 2381 2382 SND_SOC_DAPM_PGA("DMIC1", SND_SOC_NOPM, 0, 0, NULL, 0), 2383 SND_SOC_DAPM_PGA("DMIC2", SND_SOC_NOPM, 0, 0, NULL, 0), 2384 SND_SOC_DAPM_PGA("DMIC3", SND_SOC_NOPM, 0, 0, NULL, 0), 2385 SND_SOC_DAPM_PGA("DMIC4", SND_SOC_NOPM, 0, 0, NULL, 0), 2386 2387 SND_SOC_DAPM_SUPPLY("DMIC1 power", RT5677_DMIC_CTRL1, 2388 RT5677_DMIC_1_EN_SFT, 0, NULL, 0), 2389 SND_SOC_DAPM_SUPPLY("DMIC2 power", RT5677_DMIC_CTRL1, 2390 RT5677_DMIC_2_EN_SFT, 0, NULL, 0), 2391 SND_SOC_DAPM_SUPPLY("DMIC3 power", RT5677_DMIC_CTRL1, 2392 RT5677_DMIC_3_EN_SFT, 0, NULL, 0), 2393 SND_SOC_DAPM_SUPPLY("DMIC4 power", RT5677_DMIC_CTRL2, 2394 RT5677_DMIC_4_EN_SFT, 0, NULL, 0), 2395 2396 SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0, 2397 set_dmic_clk, SND_SOC_DAPM_PRE_PMU), 2398 2399 /* Boost */ 2400 SND_SOC_DAPM_PGA_E("BST1", RT5677_PWR_ANLG2, 2401 RT5677_PWR_BST1_BIT, 0, NULL, 0, rt5677_bst1_event, 2402 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU), 2403 SND_SOC_DAPM_PGA_E("BST2", RT5677_PWR_ANLG2, 2404 RT5677_PWR_BST2_BIT, 0, NULL, 0, rt5677_bst2_event, 2405 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU), 2406 2407 /* ADCs */ 2408 SND_SOC_DAPM_ADC("ADC 1", NULL, SND_SOC_NOPM, 2409 0, 0), 2410 SND_SOC_DAPM_ADC("ADC 2", NULL, SND_SOC_NOPM, 2411 0, 0), 2412 SND_SOC_DAPM_PGA("ADC 1_2", SND_SOC_NOPM, 0, 0, NULL, 0), 2413 2414 SND_SOC_DAPM_SUPPLY("ADC 1 power", RT5677_PWR_DIG1, 2415 RT5677_PWR_ADC_L_BIT, 0, NULL, 0), 2416 SND_SOC_DAPM_SUPPLY("ADC 2 power", RT5677_PWR_DIG1, 2417 RT5677_PWR_ADC_R_BIT, 0, NULL, 0), 2418 SND_SOC_DAPM_SUPPLY("ADC1 clock", RT5677_PWR_DIG1, 2419 RT5677_PWR_ADCFED1_BIT, 0, NULL, 0), 2420 SND_SOC_DAPM_SUPPLY("ADC2 clock", RT5677_PWR_DIG1, 2421 RT5677_PWR_ADCFED2_BIT, 0, NULL, 0), 2422 2423 /* ADC Mux */ 2424 SND_SOC_DAPM_MUX("Stereo1 DMIC Mux", SND_SOC_NOPM, 0, 0, 2425 &rt5677_sto1_dmic_mux), 2426 SND_SOC_DAPM_MUX("Stereo1 ADC1 Mux", SND_SOC_NOPM, 0, 0, 2427 &rt5677_sto1_adc1_mux), 2428 SND_SOC_DAPM_MUX("Stereo1 ADC2 Mux", SND_SOC_NOPM, 0, 0, 2429 &rt5677_sto1_adc2_mux), 2430 SND_SOC_DAPM_MUX("Stereo2 DMIC Mux", SND_SOC_NOPM, 0, 0, 2431 &rt5677_sto2_dmic_mux), 2432 SND_SOC_DAPM_MUX("Stereo2 ADC1 Mux", SND_SOC_NOPM, 0, 0, 2433 &rt5677_sto2_adc1_mux), 2434 SND_SOC_DAPM_MUX("Stereo2 ADC2 Mux", SND_SOC_NOPM, 0, 0, 2435 &rt5677_sto2_adc2_mux), 2436 SND_SOC_DAPM_MUX("Stereo2 ADC LR Mux", SND_SOC_NOPM, 0, 0, 2437 &rt5677_sto2_adc_lr_mux), 2438 SND_SOC_DAPM_MUX("Stereo3 DMIC Mux", SND_SOC_NOPM, 0, 0, 2439 &rt5677_sto3_dmic_mux), 2440 SND_SOC_DAPM_MUX("Stereo3 ADC1 Mux", SND_SOC_NOPM, 0, 0, 2441 &rt5677_sto3_adc1_mux), 2442 SND_SOC_DAPM_MUX("Stereo3 ADC2 Mux", SND_SOC_NOPM, 0, 0, 2443 &rt5677_sto3_adc2_mux), 2444 SND_SOC_DAPM_MUX("Stereo4 DMIC Mux", SND_SOC_NOPM, 0, 0, 2445 &rt5677_sto4_dmic_mux), 2446 SND_SOC_DAPM_MUX("Stereo4 ADC1 Mux", SND_SOC_NOPM, 0, 0, 2447 &rt5677_sto4_adc1_mux), 2448 SND_SOC_DAPM_MUX("Stereo4 ADC2 Mux", SND_SOC_NOPM, 0, 0, 2449 &rt5677_sto4_adc2_mux), 2450 SND_SOC_DAPM_MUX("Mono DMIC L Mux", SND_SOC_NOPM, 0, 0, 2451 &rt5677_mono_dmic_l_mux), 2452 SND_SOC_DAPM_MUX("Mono DMIC R Mux", SND_SOC_NOPM, 0, 0, 2453 &rt5677_mono_dmic_r_mux), 2454 SND_SOC_DAPM_MUX("Mono ADC2 L Mux", SND_SOC_NOPM, 0, 0, 2455 &rt5677_mono_adc2_l_mux), 2456 SND_SOC_DAPM_MUX("Mono ADC1 L Mux", SND_SOC_NOPM, 0, 0, 2457 &rt5677_mono_adc1_l_mux), 2458 SND_SOC_DAPM_MUX("Mono ADC1 R Mux", SND_SOC_NOPM, 0, 0, 2459 &rt5677_mono_adc1_r_mux), 2460 SND_SOC_DAPM_MUX("Mono ADC2 R Mux", SND_SOC_NOPM, 0, 0, 2461 &rt5677_mono_adc2_r_mux), 2462 2463 /* ADC Mixer */ 2464 SND_SOC_DAPM_SUPPLY("adc stereo1 filter", RT5677_PWR_DIG2, 2465 RT5677_PWR_ADC_S1F_BIT, 0, NULL, 0), 2466 SND_SOC_DAPM_SUPPLY("adc stereo2 filter", RT5677_PWR_DIG2, 2467 RT5677_PWR_ADC_S2F_BIT, 0, NULL, 0), 2468 SND_SOC_DAPM_SUPPLY("adc stereo3 filter", RT5677_PWR_DIG2, 2469 RT5677_PWR_ADC_S3F_BIT, 0, NULL, 0), 2470 SND_SOC_DAPM_SUPPLY("adc stereo4 filter", RT5677_PWR_DIG2, 2471 RT5677_PWR_ADC_S4F_BIT, 0, NULL, 0), 2472 SND_SOC_DAPM_MIXER("Sto1 ADC MIXL", SND_SOC_NOPM, 0, 0, 2473 rt5677_sto1_adc_l_mix, ARRAY_SIZE(rt5677_sto1_adc_l_mix)), 2474 SND_SOC_DAPM_MIXER("Sto1 ADC MIXR", SND_SOC_NOPM, 0, 0, 2475 rt5677_sto1_adc_r_mix, ARRAY_SIZE(rt5677_sto1_adc_r_mix)), 2476 SND_SOC_DAPM_MIXER("Sto2 ADC MIXL", SND_SOC_NOPM, 0, 0, 2477 rt5677_sto2_adc_l_mix, ARRAY_SIZE(rt5677_sto2_adc_l_mix)), 2478 SND_SOC_DAPM_MIXER("Sto2 ADC MIXR", SND_SOC_NOPM, 0, 0, 2479 rt5677_sto2_adc_r_mix, ARRAY_SIZE(rt5677_sto2_adc_r_mix)), 2480 SND_SOC_DAPM_MIXER("Sto3 ADC MIXL", SND_SOC_NOPM, 0, 0, 2481 rt5677_sto3_adc_l_mix, ARRAY_SIZE(rt5677_sto3_adc_l_mix)), 2482 SND_SOC_DAPM_MIXER("Sto3 ADC MIXR", SND_SOC_NOPM, 0, 0, 2483 rt5677_sto3_adc_r_mix, ARRAY_SIZE(rt5677_sto3_adc_r_mix)), 2484 SND_SOC_DAPM_MIXER("Sto4 ADC MIXL", SND_SOC_NOPM, 0, 0, 2485 rt5677_sto4_adc_l_mix, ARRAY_SIZE(rt5677_sto4_adc_l_mix)), 2486 SND_SOC_DAPM_MIXER("Sto4 ADC MIXR", SND_SOC_NOPM, 0, 0, 2487 rt5677_sto4_adc_r_mix, ARRAY_SIZE(rt5677_sto4_adc_r_mix)), 2488 SND_SOC_DAPM_SUPPLY("adc mono left filter", RT5677_PWR_DIG2, 2489 RT5677_PWR_ADC_MF_L_BIT, 0, NULL, 0), 2490 SND_SOC_DAPM_MIXER("Mono ADC MIXL", SND_SOC_NOPM, 0, 0, 2491 rt5677_mono_adc_l_mix, ARRAY_SIZE(rt5677_mono_adc_l_mix)), 2492 SND_SOC_DAPM_SUPPLY("adc mono right filter", RT5677_PWR_DIG2, 2493 RT5677_PWR_ADC_MF_R_BIT, 0, NULL, 0), 2494 SND_SOC_DAPM_MIXER("Mono ADC MIXR", SND_SOC_NOPM, 0, 0, 2495 rt5677_mono_adc_r_mix, ARRAY_SIZE(rt5677_mono_adc_r_mix)), 2496 2497 /* ADC PGA */ 2498 SND_SOC_DAPM_PGA("Stereo1 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0), 2499 SND_SOC_DAPM_PGA("Stereo1 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0), 2500 SND_SOC_DAPM_PGA("Stereo1 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 2501 SND_SOC_DAPM_PGA("Stereo2 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0), 2502 SND_SOC_DAPM_PGA("Stereo2 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0), 2503 SND_SOC_DAPM_PGA("Stereo2 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 2504 SND_SOC_DAPM_PGA("Stereo3 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0), 2505 SND_SOC_DAPM_PGA("Stereo3 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0), 2506 SND_SOC_DAPM_PGA("Stereo3 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 2507 SND_SOC_DAPM_PGA("Stereo4 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0), 2508 SND_SOC_DAPM_PGA("Stereo4 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0), 2509 SND_SOC_DAPM_PGA("Stereo4 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 2510 SND_SOC_DAPM_PGA("Sto2 ADC LR MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 2511 SND_SOC_DAPM_PGA("Mono ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 2512 SND_SOC_DAPM_PGA("IF1 ADC", SND_SOC_NOPM, 0, 0, NULL, 0), 2513 SND_SOC_DAPM_PGA("IF2 ADC", SND_SOC_NOPM, 0, 0, NULL, 0), 2514 2515 /* DSP */ 2516 SND_SOC_DAPM_MUX("IB9 Mux", SND_SOC_NOPM, 0, 0, 2517 &rt5677_ib9_src_mux), 2518 SND_SOC_DAPM_MUX("IB8 Mux", SND_SOC_NOPM, 0, 0, 2519 &rt5677_ib8_src_mux), 2520 SND_SOC_DAPM_MUX("IB7 Mux", SND_SOC_NOPM, 0, 0, 2521 &rt5677_ib7_src_mux), 2522 SND_SOC_DAPM_MUX("IB6 Mux", SND_SOC_NOPM, 0, 0, 2523 &rt5677_ib6_src_mux), 2524 SND_SOC_DAPM_MUX("IB45 Mux", SND_SOC_NOPM, 0, 0, 2525 &rt5677_ib45_src_mux), 2526 SND_SOC_DAPM_MUX("IB23 Mux", SND_SOC_NOPM, 0, 0, 2527 &rt5677_ib23_src_mux), 2528 SND_SOC_DAPM_MUX("IB01 Mux", SND_SOC_NOPM, 0, 0, 2529 &rt5677_ib01_src_mux), 2530 SND_SOC_DAPM_MUX("IB45 Bypass Mux", SND_SOC_NOPM, 0, 0, 2531 &rt5677_ib45_bypass_src_mux), 2532 SND_SOC_DAPM_MUX("IB23 Bypass Mux", SND_SOC_NOPM, 0, 0, 2533 &rt5677_ib23_bypass_src_mux), 2534 SND_SOC_DAPM_MUX("IB01 Bypass Mux", SND_SOC_NOPM, 0, 0, 2535 &rt5677_ib01_bypass_src_mux), 2536 SND_SOC_DAPM_MUX("OB23 Bypass Mux", SND_SOC_NOPM, 0, 0, 2537 &rt5677_ob23_bypass_src_mux), 2538 SND_SOC_DAPM_MUX("OB01 Bypass Mux", SND_SOC_NOPM, 0, 0, 2539 &rt5677_ob01_bypass_src_mux), 2540 2541 SND_SOC_DAPM_PGA("OB45", SND_SOC_NOPM, 0, 0, NULL, 0), 2542 SND_SOC_DAPM_PGA("OB67", SND_SOC_NOPM, 0, 0, NULL, 0), 2543 2544 SND_SOC_DAPM_PGA("OutBound2", SND_SOC_NOPM, 0, 0, NULL, 0), 2545 SND_SOC_DAPM_PGA("OutBound3", SND_SOC_NOPM, 0, 0, NULL, 0), 2546 SND_SOC_DAPM_PGA("OutBound4", SND_SOC_NOPM, 0, 0, NULL, 0), 2547 SND_SOC_DAPM_PGA("OutBound5", SND_SOC_NOPM, 0, 0, NULL, 0), 2548 SND_SOC_DAPM_PGA("OutBound6", SND_SOC_NOPM, 0, 0, NULL, 0), 2549 SND_SOC_DAPM_PGA("OutBound7", SND_SOC_NOPM, 0, 0, NULL, 0), 2550 2551 /* Digital Interface */ 2552 SND_SOC_DAPM_SUPPLY("I2S1", RT5677_PWR_DIG1, 2553 RT5677_PWR_I2S1_BIT, 0, NULL, 0), 2554 SND_SOC_DAPM_PGA("IF1 DAC0", SND_SOC_NOPM, 0, 0, NULL, 0), 2555 SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0), 2556 SND_SOC_DAPM_PGA("IF1 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0), 2557 SND_SOC_DAPM_PGA("IF1 DAC3", SND_SOC_NOPM, 0, 0, NULL, 0), 2558 SND_SOC_DAPM_PGA("IF1 DAC4", SND_SOC_NOPM, 0, 0, NULL, 0), 2559 SND_SOC_DAPM_PGA("IF1 DAC5", SND_SOC_NOPM, 0, 0, NULL, 0), 2560 SND_SOC_DAPM_PGA("IF1 DAC6", SND_SOC_NOPM, 0, 0, NULL, 0), 2561 SND_SOC_DAPM_PGA("IF1 DAC7", SND_SOC_NOPM, 0, 0, NULL, 0), 2562 SND_SOC_DAPM_PGA("IF1 DAC01", SND_SOC_NOPM, 0, 0, NULL, 0), 2563 SND_SOC_DAPM_PGA("IF1 DAC23", SND_SOC_NOPM, 0, 0, NULL, 0), 2564 SND_SOC_DAPM_PGA("IF1 DAC45", SND_SOC_NOPM, 0, 0, NULL, 0), 2565 SND_SOC_DAPM_PGA("IF1 DAC67", SND_SOC_NOPM, 0, 0, NULL, 0), 2566 SND_SOC_DAPM_PGA("IF1 ADC1", SND_SOC_NOPM, 0, 0, NULL, 0), 2567 SND_SOC_DAPM_PGA("IF1 ADC2", SND_SOC_NOPM, 0, 0, NULL, 0), 2568 SND_SOC_DAPM_PGA("IF1 ADC3", SND_SOC_NOPM, 0, 0, NULL, 0), 2569 SND_SOC_DAPM_PGA("IF1 ADC4", SND_SOC_NOPM, 0, 0, NULL, 0), 2570 2571 SND_SOC_DAPM_SUPPLY("I2S2", RT5677_PWR_DIG1, 2572 RT5677_PWR_I2S2_BIT, 0, NULL, 0), 2573 SND_SOC_DAPM_PGA("IF2 DAC0", SND_SOC_NOPM, 0, 0, NULL, 0), 2574 SND_SOC_DAPM_PGA("IF2 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0), 2575 SND_SOC_DAPM_PGA("IF2 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0), 2576 SND_SOC_DAPM_PGA("IF2 DAC3", SND_SOC_NOPM, 0, 0, NULL, 0), 2577 SND_SOC_DAPM_PGA("IF2 DAC4", SND_SOC_NOPM, 0, 0, NULL, 0), 2578 SND_SOC_DAPM_PGA("IF2 DAC5", SND_SOC_NOPM, 0, 0, NULL, 0), 2579 SND_SOC_DAPM_PGA("IF2 DAC6", SND_SOC_NOPM, 0, 0, NULL, 0), 2580 SND_SOC_DAPM_PGA("IF2 DAC7", SND_SOC_NOPM, 0, 0, NULL, 0), 2581 SND_SOC_DAPM_PGA("IF2 DAC01", SND_SOC_NOPM, 0, 0, NULL, 0), 2582 SND_SOC_DAPM_PGA("IF2 DAC23", SND_SOC_NOPM, 0, 0, NULL, 0), 2583 SND_SOC_DAPM_PGA("IF2 DAC45", SND_SOC_NOPM, 0, 0, NULL, 0), 2584 SND_SOC_DAPM_PGA("IF2 DAC67", SND_SOC_NOPM, 0, 0, NULL, 0), 2585 SND_SOC_DAPM_PGA("IF2 ADC1", SND_SOC_NOPM, 0, 0, NULL, 0), 2586 SND_SOC_DAPM_PGA("IF2 ADC2", SND_SOC_NOPM, 0, 0, NULL, 0), 2587 SND_SOC_DAPM_PGA("IF2 ADC3", SND_SOC_NOPM, 0, 0, NULL, 0), 2588 SND_SOC_DAPM_PGA("IF2 ADC4", SND_SOC_NOPM, 0, 0, NULL, 0), 2589 2590 SND_SOC_DAPM_SUPPLY("I2S3", RT5677_PWR_DIG1, 2591 RT5677_PWR_I2S3_BIT, 0, NULL, 0), 2592 SND_SOC_DAPM_PGA("IF3 DAC", SND_SOC_NOPM, 0, 0, NULL, 0), 2593 SND_SOC_DAPM_PGA("IF3 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0), 2594 SND_SOC_DAPM_PGA("IF3 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0), 2595 SND_SOC_DAPM_PGA("IF3 ADC", SND_SOC_NOPM, 0, 0, NULL, 0), 2596 SND_SOC_DAPM_PGA("IF3 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0), 2597 SND_SOC_DAPM_PGA("IF3 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0), 2598 2599 SND_SOC_DAPM_SUPPLY("I2S4", RT5677_PWR_DIG1, 2600 RT5677_PWR_I2S4_BIT, 0, NULL, 0), 2601 SND_SOC_DAPM_PGA("IF4 DAC", SND_SOC_NOPM, 0, 0, NULL, 0), 2602 SND_SOC_DAPM_PGA("IF4 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0), 2603 SND_SOC_DAPM_PGA("IF4 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0), 2604 SND_SOC_DAPM_PGA("IF4 ADC", SND_SOC_NOPM, 0, 0, NULL, 0), 2605 SND_SOC_DAPM_PGA("IF4 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0), 2606 SND_SOC_DAPM_PGA("IF4 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0), 2607 2608 SND_SOC_DAPM_SUPPLY("SLB", RT5677_PWR_DIG1, 2609 RT5677_PWR_SLB_BIT, 0, NULL, 0), 2610 SND_SOC_DAPM_PGA("SLB DAC0", SND_SOC_NOPM, 0, 0, NULL, 0), 2611 SND_SOC_DAPM_PGA("SLB DAC1", SND_SOC_NOPM, 0, 0, NULL, 0), 2612 SND_SOC_DAPM_PGA("SLB DAC2", SND_SOC_NOPM, 0, 0, NULL, 0), 2613 SND_SOC_DAPM_PGA("SLB DAC3", SND_SOC_NOPM, 0, 0, NULL, 0), 2614 SND_SOC_DAPM_PGA("SLB DAC4", SND_SOC_NOPM, 0, 0, NULL, 0), 2615 SND_SOC_DAPM_PGA("SLB DAC5", SND_SOC_NOPM, 0, 0, NULL, 0), 2616 SND_SOC_DAPM_PGA("SLB DAC6", SND_SOC_NOPM, 0, 0, NULL, 0), 2617 SND_SOC_DAPM_PGA("SLB DAC7", SND_SOC_NOPM, 0, 0, NULL, 0), 2618 SND_SOC_DAPM_PGA("SLB DAC01", SND_SOC_NOPM, 0, 0, NULL, 0), 2619 SND_SOC_DAPM_PGA("SLB DAC23", SND_SOC_NOPM, 0, 0, NULL, 0), 2620 SND_SOC_DAPM_PGA("SLB DAC45", SND_SOC_NOPM, 0, 0, NULL, 0), 2621 SND_SOC_DAPM_PGA("SLB DAC67", SND_SOC_NOPM, 0, 0, NULL, 0), 2622 SND_SOC_DAPM_PGA("SLB ADC1", SND_SOC_NOPM, 0, 0, NULL, 0), 2623 SND_SOC_DAPM_PGA("SLB ADC2", SND_SOC_NOPM, 0, 0, NULL, 0), 2624 SND_SOC_DAPM_PGA("SLB ADC3", SND_SOC_NOPM, 0, 0, NULL, 0), 2625 SND_SOC_DAPM_PGA("SLB ADC4", SND_SOC_NOPM, 0, 0, NULL, 0), 2626 2627 /* Digital Interface Select */ 2628 SND_SOC_DAPM_MUX("IF1 ADC1 Mux", SND_SOC_NOPM, 0, 0, 2629 &rt5677_if1_adc1_mux), 2630 SND_SOC_DAPM_MUX("IF1 ADC2 Mux", SND_SOC_NOPM, 0, 0, 2631 &rt5677_if1_adc2_mux), 2632 SND_SOC_DAPM_MUX("IF1 ADC3 Mux", SND_SOC_NOPM, 0, 0, 2633 &rt5677_if1_adc3_mux), 2634 SND_SOC_DAPM_MUX("IF1 ADC4 Mux", SND_SOC_NOPM, 0, 0, 2635 &rt5677_if1_adc4_mux), 2636 SND_SOC_DAPM_MUX("IF1 ADC1 Swap Mux", SND_SOC_NOPM, 0, 0, 2637 &rt5677_if1_adc1_swap_mux), 2638 SND_SOC_DAPM_MUX("IF1 ADC2 Swap Mux", SND_SOC_NOPM, 0, 0, 2639 &rt5677_if1_adc2_swap_mux), 2640 SND_SOC_DAPM_MUX("IF1 ADC3 Swap Mux", SND_SOC_NOPM, 0, 0, 2641 &rt5677_if1_adc3_swap_mux), 2642 SND_SOC_DAPM_MUX("IF1 ADC4 Swap Mux", SND_SOC_NOPM, 0, 0, 2643 &rt5677_if1_adc4_swap_mux), 2644 SND_SOC_DAPM_MUX_E("IF1 ADC TDM Swap Mux", SND_SOC_NOPM, 0, 0, 2645 &rt5677_if1_adc_tdm_swap_mux, rt5677_if1_adc_tdm_event, 2646 SND_SOC_DAPM_PRE_PMU), 2647 SND_SOC_DAPM_MUX("IF2 ADC1 Mux", SND_SOC_NOPM, 0, 0, 2648 &rt5677_if2_adc1_mux), 2649 SND_SOC_DAPM_MUX("IF2 ADC2 Mux", SND_SOC_NOPM, 0, 0, 2650 &rt5677_if2_adc2_mux), 2651 SND_SOC_DAPM_MUX("IF2 ADC3 Mux", SND_SOC_NOPM, 0, 0, 2652 &rt5677_if2_adc3_mux), 2653 SND_SOC_DAPM_MUX("IF2 ADC4 Mux", SND_SOC_NOPM, 0, 0, 2654 &rt5677_if2_adc4_mux), 2655 SND_SOC_DAPM_MUX("IF2 ADC1 Swap Mux", SND_SOC_NOPM, 0, 0, 2656 &rt5677_if2_adc1_swap_mux), 2657 SND_SOC_DAPM_MUX("IF2 ADC2 Swap Mux", SND_SOC_NOPM, 0, 0, 2658 &rt5677_if2_adc2_swap_mux), 2659 SND_SOC_DAPM_MUX("IF2 ADC3 Swap Mux", SND_SOC_NOPM, 0, 0, 2660 &rt5677_if2_adc3_swap_mux), 2661 SND_SOC_DAPM_MUX("IF2 ADC4 Swap Mux", SND_SOC_NOPM, 0, 0, 2662 &rt5677_if2_adc4_swap_mux), 2663 SND_SOC_DAPM_MUX_E("IF2 ADC TDM Swap Mux", SND_SOC_NOPM, 0, 0, 2664 &rt5677_if2_adc_tdm_swap_mux, rt5677_if2_adc_tdm_event, 2665 SND_SOC_DAPM_PRE_PMU), 2666 SND_SOC_DAPM_MUX("IF3 ADC Mux", SND_SOC_NOPM, 0, 0, 2667 &rt5677_if3_adc_mux), 2668 SND_SOC_DAPM_MUX("IF4 ADC Mux", SND_SOC_NOPM, 0, 0, 2669 &rt5677_if4_adc_mux), 2670 SND_SOC_DAPM_MUX("SLB ADC1 Mux", SND_SOC_NOPM, 0, 0, 2671 &rt5677_slb_adc1_mux), 2672 SND_SOC_DAPM_MUX("SLB ADC2 Mux", SND_SOC_NOPM, 0, 0, 2673 &rt5677_slb_adc2_mux), 2674 SND_SOC_DAPM_MUX("SLB ADC3 Mux", SND_SOC_NOPM, 0, 0, 2675 &rt5677_slb_adc3_mux), 2676 SND_SOC_DAPM_MUX("SLB ADC4 Mux", SND_SOC_NOPM, 0, 0, 2677 &rt5677_slb_adc4_mux), 2678 2679 SND_SOC_DAPM_MUX("IF1 DAC0 Mux", SND_SOC_NOPM, 0, 0, 2680 &rt5677_if1_dac0_tdm_sel_mux), 2681 SND_SOC_DAPM_MUX("IF1 DAC1 Mux", SND_SOC_NOPM, 0, 0, 2682 &rt5677_if1_dac1_tdm_sel_mux), 2683 SND_SOC_DAPM_MUX("IF1 DAC2 Mux", SND_SOC_NOPM, 0, 0, 2684 &rt5677_if1_dac2_tdm_sel_mux), 2685 SND_SOC_DAPM_MUX("IF1 DAC3 Mux", SND_SOC_NOPM, 0, 0, 2686 &rt5677_if1_dac3_tdm_sel_mux), 2687 SND_SOC_DAPM_MUX("IF1 DAC4 Mux", SND_SOC_NOPM, 0, 0, 2688 &rt5677_if1_dac4_tdm_sel_mux), 2689 SND_SOC_DAPM_MUX("IF1 DAC5 Mux", SND_SOC_NOPM, 0, 0, 2690 &rt5677_if1_dac5_tdm_sel_mux), 2691 SND_SOC_DAPM_MUX("IF1 DAC6 Mux", SND_SOC_NOPM, 0, 0, 2692 &rt5677_if1_dac6_tdm_sel_mux), 2693 SND_SOC_DAPM_MUX("IF1 DAC7 Mux", SND_SOC_NOPM, 0, 0, 2694 &rt5677_if1_dac7_tdm_sel_mux), 2695 2696 SND_SOC_DAPM_MUX("IF2 DAC0 Mux", SND_SOC_NOPM, 0, 0, 2697 &rt5677_if2_dac0_tdm_sel_mux), 2698 SND_SOC_DAPM_MUX("IF2 DAC1 Mux", SND_SOC_NOPM, 0, 0, 2699 &rt5677_if2_dac1_tdm_sel_mux), 2700 SND_SOC_DAPM_MUX("IF2 DAC2 Mux", SND_SOC_NOPM, 0, 0, 2701 &rt5677_if2_dac2_tdm_sel_mux), 2702 SND_SOC_DAPM_MUX("IF2 DAC3 Mux", SND_SOC_NOPM, 0, 0, 2703 &rt5677_if2_dac3_tdm_sel_mux), 2704 SND_SOC_DAPM_MUX("IF2 DAC4 Mux", SND_SOC_NOPM, 0, 0, 2705 &rt5677_if2_dac4_tdm_sel_mux), 2706 SND_SOC_DAPM_MUX("IF2 DAC5 Mux", SND_SOC_NOPM, 0, 0, 2707 &rt5677_if2_dac5_tdm_sel_mux), 2708 SND_SOC_DAPM_MUX("IF2 DAC6 Mux", SND_SOC_NOPM, 0, 0, 2709 &rt5677_if2_dac6_tdm_sel_mux), 2710 SND_SOC_DAPM_MUX("IF2 DAC7 Mux", SND_SOC_NOPM, 0, 0, 2711 &rt5677_if2_dac7_tdm_sel_mux), 2712 2713 /* Audio Interface */ 2714 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0), 2715 SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0), 2716 SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0), 2717 SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0), 2718 SND_SOC_DAPM_AIF_IN("AIF3RX", "AIF3 Playback", 0, SND_SOC_NOPM, 0, 0), 2719 SND_SOC_DAPM_AIF_OUT("AIF3TX", "AIF3 Capture", 0, SND_SOC_NOPM, 0, 0), 2720 SND_SOC_DAPM_AIF_IN("AIF4RX", "AIF4 Playback", 0, SND_SOC_NOPM, 0, 0), 2721 SND_SOC_DAPM_AIF_OUT("AIF4TX", "AIF4 Capture", 0, SND_SOC_NOPM, 0, 0), 2722 SND_SOC_DAPM_AIF_IN("SLBRX", "SLIMBus Playback", 0, SND_SOC_NOPM, 0, 0), 2723 SND_SOC_DAPM_AIF_OUT("SLBTX", "SLIMBus Capture", 0, SND_SOC_NOPM, 0, 0), 2724 2725 /* Sidetone Mux */ 2726 SND_SOC_DAPM_MUX("Sidetone Mux", SND_SOC_NOPM, 0, 0, 2727 &rt5677_sidetone_mux), 2728 SND_SOC_DAPM_SUPPLY("Sidetone Power", RT5677_SIDETONE_CTRL, 2729 RT5677_ST_EN_SFT, 0, NULL, 0), 2730 2731 /* VAD Mux*/ 2732 SND_SOC_DAPM_MUX("VAD ADC Mux", SND_SOC_NOPM, 0, 0, 2733 &rt5677_vad_src_mux), 2734 2735 /* Tensilica DSP */ 2736 SND_SOC_DAPM_PGA("Tensilica DSP", SND_SOC_NOPM, 0, 0, NULL, 0), 2737 SND_SOC_DAPM_MIXER("OB01 MIX", SND_SOC_NOPM, 0, 0, 2738 rt5677_ob_01_mix, ARRAY_SIZE(rt5677_ob_01_mix)), 2739 SND_SOC_DAPM_MIXER("OB23 MIX", SND_SOC_NOPM, 0, 0, 2740 rt5677_ob_23_mix, ARRAY_SIZE(rt5677_ob_23_mix)), 2741 SND_SOC_DAPM_MIXER("OB4 MIX", SND_SOC_NOPM, 0, 0, 2742 rt5677_ob_4_mix, ARRAY_SIZE(rt5677_ob_4_mix)), 2743 SND_SOC_DAPM_MIXER("OB5 MIX", SND_SOC_NOPM, 0, 0, 2744 rt5677_ob_5_mix, ARRAY_SIZE(rt5677_ob_5_mix)), 2745 SND_SOC_DAPM_MIXER("OB6 MIX", SND_SOC_NOPM, 0, 0, 2746 rt5677_ob_6_mix, ARRAY_SIZE(rt5677_ob_6_mix)), 2747 SND_SOC_DAPM_MIXER("OB7 MIX", SND_SOC_NOPM, 0, 0, 2748 rt5677_ob_7_mix, ARRAY_SIZE(rt5677_ob_7_mix)), 2749 2750 /* Output Side */ 2751 /* DAC mixer before sound effect */ 2752 SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0, 2753 rt5677_dac_l_mix, ARRAY_SIZE(rt5677_dac_l_mix)), 2754 SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0, 2755 rt5677_dac_r_mix, ARRAY_SIZE(rt5677_dac_r_mix)), 2756 SND_SOC_DAPM_PGA("DAC1 FS", SND_SOC_NOPM, 0, 0, NULL, 0), 2757 2758 /* DAC Mux */ 2759 SND_SOC_DAPM_MUX("DAC1 Mux", SND_SOC_NOPM, 0, 0, 2760 &rt5677_dac1_mux), 2761 SND_SOC_DAPM_MUX("ADDA1 Mux", SND_SOC_NOPM, 0, 0, 2762 &rt5677_adda1_mux), 2763 SND_SOC_DAPM_MUX("DAC12 SRC Mux", SND_SOC_NOPM, 0, 0, 2764 &rt5677_dac12_mux), 2765 SND_SOC_DAPM_MUX("DAC3 SRC Mux", SND_SOC_NOPM, 0, 0, 2766 &rt5677_dac3_mux), 2767 2768 /* DAC2 channel Mux */ 2769 SND_SOC_DAPM_MUX("DAC2 L Mux", SND_SOC_NOPM, 0, 0, 2770 &rt5677_dac2_l_mux), 2771 SND_SOC_DAPM_MUX("DAC2 R Mux", SND_SOC_NOPM, 0, 0, 2772 &rt5677_dac2_r_mux), 2773 2774 /* DAC3 channel Mux */ 2775 SND_SOC_DAPM_MUX("DAC3 L Mux", SND_SOC_NOPM, 0, 0, 2776 &rt5677_dac3_l_mux), 2777 SND_SOC_DAPM_MUX("DAC3 R Mux", SND_SOC_NOPM, 0, 0, 2778 &rt5677_dac3_r_mux), 2779 2780 /* DAC4 channel Mux */ 2781 SND_SOC_DAPM_MUX("DAC4 L Mux", SND_SOC_NOPM, 0, 0, 2782 &rt5677_dac4_l_mux), 2783 SND_SOC_DAPM_MUX("DAC4 R Mux", SND_SOC_NOPM, 0, 0, 2784 &rt5677_dac4_r_mux), 2785 2786 /* DAC Mixer */ 2787 SND_SOC_DAPM_SUPPLY("dac stereo1 filter", RT5677_PWR_DIG2, 2788 RT5677_PWR_DAC_S1F_BIT, 0, NULL, 0), 2789 SND_SOC_DAPM_SUPPLY("dac mono2 left filter", RT5677_PWR_DIG2, 2790 RT5677_PWR_DAC_M2F_L_BIT, 0, NULL, 0), 2791 SND_SOC_DAPM_SUPPLY("dac mono2 right filter", RT5677_PWR_DIG2, 2792 RT5677_PWR_DAC_M2F_R_BIT, 0, NULL, 0), 2793 SND_SOC_DAPM_SUPPLY("dac mono3 left filter", RT5677_PWR_DIG2, 2794 RT5677_PWR_DAC_M3F_L_BIT, 0, NULL, 0), 2795 SND_SOC_DAPM_SUPPLY("dac mono3 right filter", RT5677_PWR_DIG2, 2796 RT5677_PWR_DAC_M3F_R_BIT, 0, NULL, 0), 2797 SND_SOC_DAPM_SUPPLY("dac mono4 left filter", RT5677_PWR_DIG2, 2798 RT5677_PWR_DAC_M4F_L_BIT, 0, NULL, 0), 2799 SND_SOC_DAPM_SUPPLY("dac mono4 right filter", RT5677_PWR_DIG2, 2800 RT5677_PWR_DAC_M4F_R_BIT, 0, NULL, 0), 2801 2802 SND_SOC_DAPM_MIXER("Stereo DAC MIXL", SND_SOC_NOPM, 0, 0, 2803 rt5677_sto1_dac_l_mix, ARRAY_SIZE(rt5677_sto1_dac_l_mix)), 2804 SND_SOC_DAPM_MIXER("Stereo DAC MIXR", SND_SOC_NOPM, 0, 0, 2805 rt5677_sto1_dac_r_mix, ARRAY_SIZE(rt5677_sto1_dac_r_mix)), 2806 SND_SOC_DAPM_MIXER("Mono DAC MIXL", SND_SOC_NOPM, 0, 0, 2807 rt5677_mono_dac_l_mix, ARRAY_SIZE(rt5677_mono_dac_l_mix)), 2808 SND_SOC_DAPM_MIXER("Mono DAC MIXR", SND_SOC_NOPM, 0, 0, 2809 rt5677_mono_dac_r_mix, ARRAY_SIZE(rt5677_mono_dac_r_mix)), 2810 SND_SOC_DAPM_MIXER("DD1 MIXL", SND_SOC_NOPM, 0, 0, 2811 rt5677_dd1_l_mix, ARRAY_SIZE(rt5677_dd1_l_mix)), 2812 SND_SOC_DAPM_MIXER("DD1 MIXR", SND_SOC_NOPM, 0, 0, 2813 rt5677_dd1_r_mix, ARRAY_SIZE(rt5677_dd1_r_mix)), 2814 SND_SOC_DAPM_MIXER("DD2 MIXL", SND_SOC_NOPM, 0, 0, 2815 rt5677_dd2_l_mix, ARRAY_SIZE(rt5677_dd2_l_mix)), 2816 SND_SOC_DAPM_MIXER("DD2 MIXR", SND_SOC_NOPM, 0, 0, 2817 rt5677_dd2_r_mix, ARRAY_SIZE(rt5677_dd2_r_mix)), 2818 SND_SOC_DAPM_PGA("Stereo DAC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 2819 SND_SOC_DAPM_PGA("Mono DAC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 2820 SND_SOC_DAPM_PGA("DD1 MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 2821 SND_SOC_DAPM_PGA("DD2 MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 2822 2823 /* DACs */ 2824 SND_SOC_DAPM_DAC("DAC 1", NULL, RT5677_PWR_DIG1, 2825 RT5677_PWR_DAC1_BIT, 0), 2826 SND_SOC_DAPM_DAC("DAC 2", NULL, RT5677_PWR_DIG1, 2827 RT5677_PWR_DAC2_BIT, 0), 2828 SND_SOC_DAPM_DAC("DAC 3", NULL, RT5677_PWR_DIG1, 2829 RT5677_PWR_DAC3_BIT, 0), 2830 2831 /* PDM */ 2832 SND_SOC_DAPM_SUPPLY("PDM1 Power", RT5677_PWR_DIG2, 2833 RT5677_PWR_PDM1_BIT, 0, NULL, 0), 2834 SND_SOC_DAPM_SUPPLY("PDM2 Power", RT5677_PWR_DIG2, 2835 RT5677_PWR_PDM2_BIT, 0, NULL, 0), 2836 2837 SND_SOC_DAPM_MUX("PDM1 L Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM1_L_SFT, 2838 1, &rt5677_pdm1_l_mux), 2839 SND_SOC_DAPM_MUX("PDM1 R Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM1_R_SFT, 2840 1, &rt5677_pdm1_r_mux), 2841 SND_SOC_DAPM_MUX("PDM2 L Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM2_L_SFT, 2842 1, &rt5677_pdm2_l_mux), 2843 SND_SOC_DAPM_MUX("PDM2 R Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM2_R_SFT, 2844 1, &rt5677_pdm2_r_mux), 2845 2846 SND_SOC_DAPM_PGA_S("LOUT1 amp", 0, RT5677_PWR_ANLG1, RT5677_PWR_LO1_BIT, 2847 0, NULL, 0), 2848 SND_SOC_DAPM_PGA_S("LOUT2 amp", 0, RT5677_PWR_ANLG1, RT5677_PWR_LO2_BIT, 2849 0, NULL, 0), 2850 SND_SOC_DAPM_PGA_S("LOUT3 amp", 0, RT5677_PWR_ANLG1, RT5677_PWR_LO3_BIT, 2851 0, NULL, 0), 2852 2853 SND_SOC_DAPM_PGA_S("LOUT1 vref", 1, SND_SOC_NOPM, 0, 0, 2854 rt5677_vref_event, SND_SOC_DAPM_POST_PMU), 2855 SND_SOC_DAPM_PGA_S("LOUT2 vref", 1, SND_SOC_NOPM, 0, 0, 2856 rt5677_vref_event, SND_SOC_DAPM_POST_PMU), 2857 SND_SOC_DAPM_PGA_S("LOUT3 vref", 1, SND_SOC_NOPM, 0, 0, 2858 rt5677_vref_event, SND_SOC_DAPM_POST_PMU), 2859 2860 /* Output Lines */ 2861 SND_SOC_DAPM_OUTPUT("LOUT1"), 2862 SND_SOC_DAPM_OUTPUT("LOUT2"), 2863 SND_SOC_DAPM_OUTPUT("LOUT3"), 2864 SND_SOC_DAPM_OUTPUT("PDM1L"), 2865 SND_SOC_DAPM_OUTPUT("PDM1R"), 2866 SND_SOC_DAPM_OUTPUT("PDM2L"), 2867 SND_SOC_DAPM_OUTPUT("PDM2R"), 2868 2869 SND_SOC_DAPM_POST("vref", rt5677_vref_event), 2870 }; 2871 2872 static const struct snd_soc_dapm_route rt5677_dapm_routes[] = { 2873 { "Stereo1 DMIC Mux", NULL, "DMIC STO1 ASRC", can_use_asrc }, 2874 { "Stereo2 DMIC Mux", NULL, "DMIC STO2 ASRC", can_use_asrc }, 2875 { "Stereo3 DMIC Mux", NULL, "DMIC STO3 ASRC", can_use_asrc }, 2876 { "Stereo4 DMIC Mux", NULL, "DMIC STO4 ASRC", can_use_asrc }, 2877 { "Mono DMIC L Mux", NULL, "DMIC MONO L ASRC", can_use_asrc }, 2878 { "Mono DMIC R Mux", NULL, "DMIC MONO R ASRC", can_use_asrc }, 2879 { "I2S1", NULL, "I2S1 ASRC", can_use_asrc}, 2880 { "I2S2", NULL, "I2S2 ASRC", can_use_asrc}, 2881 { "I2S3", NULL, "I2S3 ASRC", can_use_asrc}, 2882 { "I2S4", NULL, "I2S4 ASRC", can_use_asrc}, 2883 2884 { "dac stereo1 filter", NULL, "DAC STO ASRC", is_using_asrc }, 2885 { "dac mono2 left filter", NULL, "DAC MONO2 L ASRC", is_using_asrc }, 2886 { "dac mono2 right filter", NULL, "DAC MONO2 R ASRC", is_using_asrc }, 2887 { "dac mono3 left filter", NULL, "DAC MONO3 L ASRC", is_using_asrc }, 2888 { "dac mono3 right filter", NULL, "DAC MONO3 R ASRC", is_using_asrc }, 2889 { "dac mono4 left filter", NULL, "DAC MONO4 L ASRC", is_using_asrc }, 2890 { "dac mono4 right filter", NULL, "DAC MONO4 R ASRC", is_using_asrc }, 2891 { "adc stereo1 filter", NULL, "ADC STO1 ASRC", is_using_asrc }, 2892 { "adc stereo2 filter", NULL, "ADC STO2 ASRC", is_using_asrc }, 2893 { "adc stereo3 filter", NULL, "ADC STO3 ASRC", is_using_asrc }, 2894 { "adc stereo4 filter", NULL, "ADC STO4 ASRC", is_using_asrc }, 2895 { "adc mono left filter", NULL, "ADC MONO L ASRC", is_using_asrc }, 2896 { "adc mono right filter", NULL, "ADC MONO R ASRC", is_using_asrc }, 2897 2898 { "DMIC1", NULL, "DMIC L1" }, 2899 { "DMIC1", NULL, "DMIC R1" }, 2900 { "DMIC2", NULL, "DMIC L2" }, 2901 { "DMIC2", NULL, "DMIC R2" }, 2902 { "DMIC3", NULL, "DMIC L3" }, 2903 { "DMIC3", NULL, "DMIC R3" }, 2904 { "DMIC4", NULL, "DMIC L4" }, 2905 { "DMIC4", NULL, "DMIC R4" }, 2906 2907 { "DMIC L1", NULL, "DMIC CLK" }, 2908 { "DMIC R1", NULL, "DMIC CLK" }, 2909 { "DMIC L2", NULL, "DMIC CLK" }, 2910 { "DMIC R2", NULL, "DMIC CLK" }, 2911 { "DMIC L3", NULL, "DMIC CLK" }, 2912 { "DMIC R3", NULL, "DMIC CLK" }, 2913 { "DMIC L4", NULL, "DMIC CLK" }, 2914 { "DMIC R4", NULL, "DMIC CLK" }, 2915 2916 { "DMIC L1", NULL, "DMIC1 power" }, 2917 { "DMIC R1", NULL, "DMIC1 power" }, 2918 { "DMIC L3", NULL, "DMIC3 power" }, 2919 { "DMIC R3", NULL, "DMIC3 power" }, 2920 { "DMIC L4", NULL, "DMIC4 power" }, 2921 { "DMIC R4", NULL, "DMIC4 power" }, 2922 2923 { "BST1", NULL, "IN1P" }, 2924 { "BST1", NULL, "IN1N" }, 2925 { "BST2", NULL, "IN2P" }, 2926 { "BST2", NULL, "IN2N" }, 2927 2928 { "IN1P", NULL, "MICBIAS1" }, 2929 { "IN1N", NULL, "MICBIAS1" }, 2930 { "IN2P", NULL, "MICBIAS1" }, 2931 { "IN2N", NULL, "MICBIAS1" }, 2932 2933 { "ADC 1", NULL, "BST1" }, 2934 { "ADC 1", NULL, "ADC 1 power" }, 2935 { "ADC 1", NULL, "ADC1 clock" }, 2936 { "ADC 2", NULL, "BST2" }, 2937 { "ADC 2", NULL, "ADC 2 power" }, 2938 { "ADC 2", NULL, "ADC2 clock" }, 2939 2940 { "Stereo1 DMIC Mux", "DMIC1", "DMIC1" }, 2941 { "Stereo1 DMIC Mux", "DMIC2", "DMIC2" }, 2942 { "Stereo1 DMIC Mux", "DMIC3", "DMIC3" }, 2943 { "Stereo1 DMIC Mux", "DMIC4", "DMIC4" }, 2944 2945 { "Stereo2 DMIC Mux", "DMIC1", "DMIC1" }, 2946 { "Stereo2 DMIC Mux", "DMIC2", "DMIC2" }, 2947 { "Stereo2 DMIC Mux", "DMIC3", "DMIC3" }, 2948 { "Stereo2 DMIC Mux", "DMIC4", "DMIC4" }, 2949 2950 { "Stereo3 DMIC Mux", "DMIC1", "DMIC1" }, 2951 { "Stereo3 DMIC Mux", "DMIC2", "DMIC2" }, 2952 { "Stereo3 DMIC Mux", "DMIC3", "DMIC3" }, 2953 { "Stereo3 DMIC Mux", "DMIC4", "DMIC4" }, 2954 2955 { "Stereo4 DMIC Mux", "DMIC1", "DMIC1" }, 2956 { "Stereo4 DMIC Mux", "DMIC2", "DMIC2" }, 2957 { "Stereo4 DMIC Mux", "DMIC3", "DMIC3" }, 2958 { "Stereo4 DMIC Mux", "DMIC4", "DMIC4" }, 2959 2960 { "Mono DMIC L Mux", "DMIC1", "DMIC1" }, 2961 { "Mono DMIC L Mux", "DMIC2", "DMIC2" }, 2962 { "Mono DMIC L Mux", "DMIC3", "DMIC3" }, 2963 { "Mono DMIC L Mux", "DMIC4", "DMIC4" }, 2964 2965 { "Mono DMIC R Mux", "DMIC1", "DMIC1" }, 2966 { "Mono DMIC R Mux", "DMIC2", "DMIC2" }, 2967 { "Mono DMIC R Mux", "DMIC3", "DMIC3" }, 2968 { "Mono DMIC R Mux", "DMIC4", "DMIC4" }, 2969 2970 { "ADC 1_2", NULL, "ADC 1" }, 2971 { "ADC 1_2", NULL, "ADC 2" }, 2972 2973 { "Stereo1 ADC1 Mux", "DD MIX1", "DD1 MIX" }, 2974 { "Stereo1 ADC1 Mux", "ADC1/2", "ADC 1_2" }, 2975 { "Stereo1 ADC1 Mux", "Stereo DAC MIX", "Stereo DAC MIX" }, 2976 2977 { "Stereo1 ADC2 Mux", "DD MIX1", "DD1 MIX" }, 2978 { "Stereo1 ADC2 Mux", "DMIC", "Stereo1 DMIC Mux" }, 2979 { "Stereo1 ADC2 Mux", "Stereo DAC MIX", "Stereo DAC MIX" }, 2980 2981 { "Stereo2 ADC1 Mux", "DD MIX1", "DD1 MIX" }, 2982 { "Stereo2 ADC1 Mux", "ADC1/2", "ADC 1_2" }, 2983 { "Stereo2 ADC1 Mux", "Stereo DAC MIX", "Stereo DAC MIX" }, 2984 2985 { "Stereo2 ADC2 Mux", "DD MIX1", "DD1 MIX" }, 2986 { "Stereo2 ADC2 Mux", "DMIC", "Stereo2 DMIC Mux" }, 2987 { "Stereo2 ADC2 Mux", "Stereo DAC MIX", "Stereo DAC MIX" }, 2988 2989 { "Stereo3 ADC1 Mux", "DD MIX1", "DD1 MIX" }, 2990 { "Stereo3 ADC1 Mux", "ADC1/2", "ADC 1_2" }, 2991 { "Stereo3 ADC1 Mux", "Stereo DAC MIX", "Stereo DAC MIX" }, 2992 2993 { "Stereo3 ADC2 Mux", "DD MIX1", "DD1 MIX" }, 2994 { "Stereo3 ADC2 Mux", "DMIC", "Stereo3 DMIC Mux" }, 2995 { "Stereo3 ADC2 Mux", "Stereo DAC MIX", "Stereo DAC MIX" }, 2996 2997 { "Stereo4 ADC1 Mux", "DD MIX1", "DD1 MIX" }, 2998 { "Stereo4 ADC1 Mux", "ADC1/2", "ADC 1_2" }, 2999 { "Stereo4 ADC1 Mux", "DD MIX2", "DD2 MIX" }, 3000 3001 { "Stereo4 ADC2 Mux", "DD MIX1", "DD1 MIX" }, 3002 { "Stereo4 ADC2 Mux", "DMIC", "Stereo3 DMIC Mux" }, 3003 { "Stereo4 ADC2 Mux", "DD MIX2", "DD2 MIX" }, 3004 3005 { "Mono ADC2 L Mux", "DD MIX1L", "DD1 MIXL" }, 3006 { "Mono ADC2 L Mux", "DMIC", "Mono DMIC L Mux" }, 3007 { "Mono ADC2 L Mux", "MONO DAC MIXL", "Mono DAC MIXL" }, 3008 3009 { "Mono ADC1 L Mux", "DD MIX1L", "DD1 MIXL" }, 3010 { "Mono ADC1 L Mux", "ADC1", "ADC 1" }, 3011 { "Mono ADC1 L Mux", "MONO DAC MIXL", "Mono DAC MIXL" }, 3012 3013 { "Mono ADC1 R Mux", "DD MIX1R", "DD1 MIXR" }, 3014 { "Mono ADC1 R Mux", "ADC2", "ADC 2" }, 3015 { "Mono ADC1 R Mux", "MONO DAC MIXR", "Mono DAC MIXR" }, 3016 3017 { "Mono ADC2 R Mux", "DD MIX1R", "DD1 MIXR" }, 3018 { "Mono ADC2 R Mux", "DMIC", "Mono DMIC R Mux" }, 3019 { "Mono ADC2 R Mux", "MONO DAC MIXR", "Mono DAC MIXR" }, 3020 3021 { "Sto1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC1 Mux" }, 3022 { "Sto1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC2 Mux" }, 3023 { "Sto1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC1 Mux" }, 3024 { "Sto1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC2 Mux" }, 3025 3026 { "Stereo1 ADC MIXL", NULL, "Sto1 ADC MIXL" }, 3027 { "Stereo1 ADC MIXL", NULL, "adc stereo1 filter" }, 3028 { "Stereo1 ADC MIXR", NULL, "Sto1 ADC MIXR" }, 3029 { "Stereo1 ADC MIXR", NULL, "adc stereo1 filter" }, 3030 { "adc stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll }, 3031 3032 { "Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXL" }, 3033 { "Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXR" }, 3034 3035 { "Sto2 ADC MIXL", "ADC1 Switch", "Stereo2 ADC1 Mux" }, 3036 { "Sto2 ADC MIXL", "ADC2 Switch", "Stereo2 ADC2 Mux" }, 3037 { "Sto2 ADC MIXR", "ADC1 Switch", "Stereo2 ADC1 Mux" }, 3038 { "Sto2 ADC MIXR", "ADC2 Switch", "Stereo2 ADC2 Mux" }, 3039 3040 { "Sto2 ADC LR MIX", NULL, "Sto2 ADC MIXL" }, 3041 { "Sto2 ADC LR MIX", NULL, "Sto2 ADC MIXR" }, 3042 3043 { "Stereo2 ADC LR Mux", "L", "Sto2 ADC MIXL" }, 3044 { "Stereo2 ADC LR Mux", "LR", "Sto2 ADC LR MIX" }, 3045 3046 { "Stereo2 ADC MIXL", NULL, "Stereo2 ADC LR Mux" }, 3047 { "Stereo2 ADC MIXL", NULL, "adc stereo2 filter" }, 3048 { "Stereo2 ADC MIXR", NULL, "Sto2 ADC MIXR" }, 3049 { "Stereo2 ADC MIXR", NULL, "adc stereo2 filter" }, 3050 { "adc stereo2 filter", NULL, "PLL1", is_sys_clk_from_pll }, 3051 3052 { "Stereo2 ADC MIX", NULL, "Stereo2 ADC MIXL" }, 3053 { "Stereo2 ADC MIX", NULL, "Stereo2 ADC MIXR" }, 3054 3055 { "Sto3 ADC MIXL", "ADC1 Switch", "Stereo3 ADC1 Mux" }, 3056 { "Sto3 ADC MIXL", "ADC2 Switch", "Stereo3 ADC2 Mux" }, 3057 { "Sto3 ADC MIXR", "ADC1 Switch", "Stereo3 ADC1 Mux" }, 3058 { "Sto3 ADC MIXR", "ADC2 Switch", "Stereo3 ADC2 Mux" }, 3059 3060 { "Stereo3 ADC MIXL", NULL, "Sto3 ADC MIXL" }, 3061 { "Stereo3 ADC MIXL", NULL, "adc stereo3 filter" }, 3062 { "Stereo3 ADC MIXR", NULL, "Sto3 ADC MIXR" }, 3063 { "Stereo3 ADC MIXR", NULL, "adc stereo3 filter" }, 3064 { "adc stereo3 filter", NULL, "PLL1", is_sys_clk_from_pll }, 3065 3066 { "Stereo3 ADC MIX", NULL, "Stereo3 ADC MIXL" }, 3067 { "Stereo3 ADC MIX", NULL, "Stereo3 ADC MIXR" }, 3068 3069 { "Sto4 ADC MIXL", "ADC1 Switch", "Stereo4 ADC1 Mux" }, 3070 { "Sto4 ADC MIXL", "ADC2 Switch", "Stereo4 ADC2 Mux" }, 3071 { "Sto4 ADC MIXR", "ADC1 Switch", "Stereo4 ADC1 Mux" }, 3072 { "Sto4 ADC MIXR", "ADC2 Switch", "Stereo4 ADC2 Mux" }, 3073 3074 { "Stereo4 ADC MIXL", NULL, "Sto4 ADC MIXL" }, 3075 { "Stereo4 ADC MIXL", NULL, "adc stereo4 filter" }, 3076 { "Stereo4 ADC MIXR", NULL, "Sto4 ADC MIXR" }, 3077 { "Stereo4 ADC MIXR", NULL, "adc stereo4 filter" }, 3078 { "adc stereo4 filter", NULL, "PLL1", is_sys_clk_from_pll }, 3079 3080 { "Stereo4 ADC MIX", NULL, "Stereo4 ADC MIXL" }, 3081 { "Stereo4 ADC MIX", NULL, "Stereo4 ADC MIXR" }, 3082 3083 { "Mono ADC MIXL", "ADC1 Switch", "Mono ADC1 L Mux" }, 3084 { "Mono ADC MIXL", "ADC2 Switch", "Mono ADC2 L Mux" }, 3085 { "Mono ADC MIXL", NULL, "adc mono left filter" }, 3086 { "adc mono left filter", NULL, "PLL1", is_sys_clk_from_pll }, 3087 3088 { "Mono ADC MIXR", "ADC1 Switch", "Mono ADC1 R Mux" }, 3089 { "Mono ADC MIXR", "ADC2 Switch", "Mono ADC2 R Mux" }, 3090 { "Mono ADC MIXR", NULL, "adc mono right filter" }, 3091 { "adc mono right filter", NULL, "PLL1", is_sys_clk_from_pll }, 3092 3093 { "Mono ADC MIX", NULL, "Mono ADC MIXL" }, 3094 { "Mono ADC MIX", NULL, "Mono ADC MIXR" }, 3095 3096 { "VAD ADC Mux", "STO1 ADC MIX L", "Stereo1 ADC MIXL" }, 3097 { "VAD ADC Mux", "MONO ADC MIX L", "Mono ADC MIXL" }, 3098 { "VAD ADC Mux", "MONO ADC MIX R", "Mono ADC MIXR" }, 3099 { "VAD ADC Mux", "STO2 ADC MIX L", "Stereo2 ADC MIXL" }, 3100 { "VAD ADC Mux", "STO3 ADC MIX L", "Stereo3 ADC MIXL" }, 3101 3102 { "IF1 ADC1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" }, 3103 { "IF1 ADC1 Mux", "OB01", "OB01 Bypass Mux" }, 3104 { "IF1 ADC1 Mux", "VAD ADC", "VAD ADC Mux" }, 3105 3106 { "IF1 ADC2 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" }, 3107 { "IF1 ADC2 Mux", "OB23", "OB23 Bypass Mux" }, 3108 3109 { "IF1 ADC3 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" }, 3110 { "IF1 ADC3 Mux", "MONO ADC MIX", "Mono ADC MIX" }, 3111 { "IF1 ADC3 Mux", "OB45", "OB45" }, 3112 3113 { "IF1 ADC4 Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" }, 3114 { "IF1 ADC4 Mux", "OB67", "OB67" }, 3115 { "IF1 ADC4 Mux", "OB01", "OB01 Bypass Mux" }, 3116 3117 { "IF1 ADC1 Swap Mux", "L/R", "IF1 ADC1 Mux" }, 3118 { "IF1 ADC1 Swap Mux", "R/L", "IF1 ADC1 Mux" }, 3119 { "IF1 ADC1 Swap Mux", "L/L", "IF1 ADC1 Mux" }, 3120 { "IF1 ADC1 Swap Mux", "R/R", "IF1 ADC1 Mux" }, 3121 3122 { "IF1 ADC2 Swap Mux", "L/R", "IF1 ADC2 Mux" }, 3123 { "IF1 ADC2 Swap Mux", "R/L", "IF1 ADC2 Mux" }, 3124 { "IF1 ADC2 Swap Mux", "L/L", "IF1 ADC2 Mux" }, 3125 { "IF1 ADC2 Swap Mux", "R/R", "IF1 ADC2 Mux" }, 3126 3127 { "IF1 ADC3 Swap Mux", "L/R", "IF1 ADC3 Mux" }, 3128 { "IF1 ADC3 Swap Mux", "R/L", "IF1 ADC3 Mux" }, 3129 { "IF1 ADC3 Swap Mux", "L/L", "IF1 ADC3 Mux" }, 3130 { "IF1 ADC3 Swap Mux", "R/R", "IF1 ADC3 Mux" }, 3131 3132 { "IF1 ADC4 Swap Mux", "L/R", "IF1 ADC4 Mux" }, 3133 { "IF1 ADC4 Swap Mux", "R/L", "IF1 ADC4 Mux" }, 3134 { "IF1 ADC4 Swap Mux", "L/L", "IF1 ADC4 Mux" }, 3135 { "IF1 ADC4 Swap Mux", "R/R", "IF1 ADC4 Mux" }, 3136 3137 { "IF1 ADC", NULL, "IF1 ADC1 Swap Mux" }, 3138 { "IF1 ADC", NULL, "IF1 ADC2 Swap Mux" }, 3139 { "IF1 ADC", NULL, "IF1 ADC3 Swap Mux" }, 3140 { "IF1 ADC", NULL, "IF1 ADC4 Swap Mux" }, 3141 3142 { "IF1 ADC TDM Swap Mux", "1/2/3/4", "IF1 ADC" }, 3143 { "IF1 ADC TDM Swap Mux", "2/1/3/4", "IF1 ADC" }, 3144 { "IF1 ADC TDM Swap Mux", "2/3/1/4", "IF1 ADC" }, 3145 { "IF1 ADC TDM Swap Mux", "4/1/2/3", "IF1 ADC" }, 3146 { "IF1 ADC TDM Swap Mux", "1/3/2/4", "IF1 ADC" }, 3147 { "IF1 ADC TDM Swap Mux", "1/4/2/3", "IF1 ADC" }, 3148 { "IF1 ADC TDM Swap Mux", "3/1/2/4", "IF1 ADC" }, 3149 { "IF1 ADC TDM Swap Mux", "3/4/1/2", "IF1 ADC" }, 3150 3151 { "AIF1TX", NULL, "I2S1" }, 3152 { "AIF1TX", NULL, "IF1 ADC TDM Swap Mux" }, 3153 3154 { "IF2 ADC1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" }, 3155 { "IF2 ADC1 Mux", "OB01", "OB01 Bypass Mux" }, 3156 { "IF2 ADC1 Mux", "VAD ADC", "VAD ADC Mux" }, 3157 3158 { "IF2 ADC2 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" }, 3159 { "IF2 ADC2 Mux", "OB23", "OB23 Bypass Mux" }, 3160 3161 { "IF2 ADC3 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" }, 3162 { "IF2 ADC3 Mux", "MONO ADC MIX", "Mono ADC MIX" }, 3163 { "IF2 ADC3 Mux", "OB45", "OB45" }, 3164 3165 { "IF2 ADC4 Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" }, 3166 { "IF2 ADC4 Mux", "OB67", "OB67" }, 3167 { "IF2 ADC4 Mux", "OB01", "OB01 Bypass Mux" }, 3168 3169 { "IF2 ADC1 Swap Mux", "L/R", "IF2 ADC1 Mux" }, 3170 { "IF2 ADC1 Swap Mux", "R/L", "IF2 ADC1 Mux" }, 3171 { "IF2 ADC1 Swap Mux", "L/L", "IF2 ADC1 Mux" }, 3172 { "IF2 ADC1 Swap Mux", "R/R", "IF2 ADC1 Mux" }, 3173 3174 { "IF2 ADC2 Swap Mux", "L/R", "IF2 ADC2 Mux" }, 3175 { "IF2 ADC2 Swap Mux", "R/L", "IF2 ADC2 Mux" }, 3176 { "IF2 ADC2 Swap Mux", "L/L", "IF2 ADC2 Mux" }, 3177 { "IF2 ADC2 Swap Mux", "R/R", "IF2 ADC2 Mux" }, 3178 3179 { "IF2 ADC3 Swap Mux", "L/R", "IF2 ADC3 Mux" }, 3180 { "IF2 ADC3 Swap Mux", "R/L", "IF2 ADC3 Mux" }, 3181 { "IF2 ADC3 Swap Mux", "L/L", "IF2 ADC3 Mux" }, 3182 { "IF2 ADC3 Swap Mux", "R/R", "IF2 ADC3 Mux" }, 3183 3184 { "IF2 ADC4 Swap Mux", "L/R", "IF2 ADC4 Mux" }, 3185 { "IF2 ADC4 Swap Mux", "R/L", "IF2 ADC4 Mux" }, 3186 { "IF2 ADC4 Swap Mux", "L/L", "IF2 ADC4 Mux" }, 3187 { "IF2 ADC4 Swap Mux", "R/R", "IF2 ADC4 Mux" }, 3188 3189 { "IF2 ADC", NULL, "IF2 ADC1 Swap Mux" }, 3190 { "IF2 ADC", NULL, "IF2 ADC2 Swap Mux" }, 3191 { "IF2 ADC", NULL, "IF2 ADC3 Swap Mux" }, 3192 { "IF2 ADC", NULL, "IF2 ADC4 Swap Mux" }, 3193 3194 { "IF2 ADC TDM Swap Mux", "1/2/3/4", "IF2 ADC" }, 3195 { "IF2 ADC TDM Swap Mux", "2/1/3/4", "IF2 ADC" }, 3196 { "IF2 ADC TDM Swap Mux", "3/1/2/4", "IF2 ADC" }, 3197 { "IF2 ADC TDM Swap Mux", "4/1/2/3", "IF2 ADC" }, 3198 { "IF2 ADC TDM Swap Mux", "1/3/2/4", "IF2 ADC" }, 3199 { "IF2 ADC TDM Swap Mux", "1/4/2/3", "IF2 ADC" }, 3200 { "IF2 ADC TDM Swap Mux", "2/3/1/4", "IF2 ADC" }, 3201 { "IF2 ADC TDM Swap Mux", "3/4/1/2", "IF2 ADC" }, 3202 3203 { "AIF2TX", NULL, "I2S2" }, 3204 { "AIF2TX", NULL, "IF2 ADC TDM Swap Mux" }, 3205 3206 { "IF3 ADC Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" }, 3207 { "IF3 ADC Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" }, 3208 { "IF3 ADC Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" }, 3209 { "IF3 ADC Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" }, 3210 { "IF3 ADC Mux", "MONO ADC MIX", "Mono ADC MIX" }, 3211 { "IF3 ADC Mux", "OB01", "OB01 Bypass Mux" }, 3212 { "IF3 ADC Mux", "OB23", "OB23 Bypass Mux" }, 3213 { "IF3 ADC Mux", "VAD ADC", "VAD ADC Mux" }, 3214 3215 { "AIF3TX", NULL, "I2S3" }, 3216 { "AIF3TX", NULL, "IF3 ADC Mux" }, 3217 3218 { "IF4 ADC Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" }, 3219 { "IF4 ADC Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" }, 3220 { "IF4 ADC Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" }, 3221 { "IF4 ADC Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" }, 3222 { "IF4 ADC Mux", "MONO ADC MIX", "Mono ADC MIX" }, 3223 { "IF4 ADC Mux", "OB01", "OB01 Bypass Mux" }, 3224 { "IF4 ADC Mux", "OB23", "OB23 Bypass Mux" }, 3225 { "IF4 ADC Mux", "VAD ADC", "VAD ADC Mux" }, 3226 3227 { "AIF4TX", NULL, "I2S4" }, 3228 { "AIF4TX", NULL, "IF4 ADC Mux" }, 3229 3230 { "SLB ADC1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" }, 3231 { "SLB ADC1 Mux", "OB01", "OB01 Bypass Mux" }, 3232 { "SLB ADC1 Mux", "VAD ADC", "VAD ADC Mux" }, 3233 3234 { "SLB ADC2 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" }, 3235 { "SLB ADC2 Mux", "OB23", "OB23 Bypass Mux" }, 3236 3237 { "SLB ADC3 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" }, 3238 { "SLB ADC3 Mux", "MONO ADC MIX", "Mono ADC MIX" }, 3239 { "SLB ADC3 Mux", "OB45", "OB45" }, 3240 3241 { "SLB ADC4 Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" }, 3242 { "SLB ADC4 Mux", "OB67", "OB67" }, 3243 { "SLB ADC4 Mux", "OB01", "OB01 Bypass Mux" }, 3244 3245 { "SLBTX", NULL, "SLB" }, 3246 { "SLBTX", NULL, "SLB ADC1 Mux" }, 3247 { "SLBTX", NULL, "SLB ADC2 Mux" }, 3248 { "SLBTX", NULL, "SLB ADC3 Mux" }, 3249 { "SLBTX", NULL, "SLB ADC4 Mux" }, 3250 3251 { "IB01 Mux", "IF1 DAC 01", "IF1 DAC01" }, 3252 { "IB01 Mux", "IF2 DAC 01", "IF2 DAC01" }, 3253 { "IB01 Mux", "SLB DAC 01", "SLB DAC01" }, 3254 { "IB01 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" }, 3255 { "IB01 Mux", "VAD ADC/DAC1 FS", "DAC1 FS" }, 3256 3257 { "IB01 Bypass Mux", "Bypass", "IB01 Mux" }, 3258 { "IB01 Bypass Mux", "Pass SRC", "IB01 Mux" }, 3259 3260 { "IB23 Mux", "IF1 DAC 23", "IF1 DAC23" }, 3261 { "IB23 Mux", "IF2 DAC 23", "IF2 DAC23" }, 3262 { "IB23 Mux", "SLB DAC 23", "SLB DAC23" }, 3263 { "IB23 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" }, 3264 { "IB23 Mux", "DAC1 FS", "DAC1 FS" }, 3265 { "IB23 Mux", "IF4 DAC", "IF4 DAC" }, 3266 3267 { "IB23 Bypass Mux", "Bypass", "IB23 Mux" }, 3268 { "IB23 Bypass Mux", "Pass SRC", "IB23 Mux" }, 3269 3270 { "IB45 Mux", "IF1 DAC 45", "IF1 DAC45" }, 3271 { "IB45 Mux", "IF2 DAC 45", "IF2 DAC45" }, 3272 { "IB45 Mux", "SLB DAC 45", "SLB DAC45" }, 3273 { "IB45 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" }, 3274 { "IB45 Mux", "IF3 DAC", "IF3 DAC" }, 3275 3276 { "IB45 Bypass Mux", "Bypass", "IB45 Mux" }, 3277 { "IB45 Bypass Mux", "Pass SRC", "IB45 Mux" }, 3278 3279 { "IB6 Mux", "IF1 DAC 6", "IF1 DAC6" }, 3280 { "IB6 Mux", "IF2 DAC 6", "IF2 DAC6" }, 3281 { "IB6 Mux", "SLB DAC 6", "SLB DAC6" }, 3282 { "IB6 Mux", "STO4 ADC MIX L", "Stereo4 ADC MIXL" }, 3283 { "IB6 Mux", "IF4 DAC L", "IF4 DAC L" }, 3284 { "IB6 Mux", "STO1 ADC MIX L", "Stereo1 ADC MIXL" }, 3285 { "IB6 Mux", "STO2 ADC MIX L", "Stereo2 ADC MIXL" }, 3286 { "IB6 Mux", "STO3 ADC MIX L", "Stereo3 ADC MIXL" }, 3287 3288 { "IB7 Mux", "IF1 DAC 7", "IF1 DAC7" }, 3289 { "IB7 Mux", "IF2 DAC 7", "IF2 DAC7" }, 3290 { "IB7 Mux", "SLB DAC 7", "SLB DAC7" }, 3291 { "IB7 Mux", "STO4 ADC MIX R", "Stereo4 ADC MIXR" }, 3292 { "IB7 Mux", "IF4 DAC R", "IF4 DAC R" }, 3293 { "IB7 Mux", "STO1 ADC MIX R", "Stereo1 ADC MIXR" }, 3294 { "IB7 Mux", "STO2 ADC MIX R", "Stereo2 ADC MIXR" }, 3295 { "IB7 Mux", "STO3 ADC MIX R", "Stereo3 ADC MIXR" }, 3296 3297 { "IB8 Mux", "STO1 ADC MIX L", "Stereo1 ADC MIXL" }, 3298 { "IB8 Mux", "STO2 ADC MIX L", "Stereo2 ADC MIXL" }, 3299 { "IB8 Mux", "STO3 ADC MIX L", "Stereo3 ADC MIXL" }, 3300 { "IB8 Mux", "STO4 ADC MIX L", "Stereo4 ADC MIXL" }, 3301 { "IB8 Mux", "MONO ADC MIX L", "Mono ADC MIXL" }, 3302 { "IB8 Mux", "DACL1 FS", "DAC1 MIXL" }, 3303 3304 { "IB9 Mux", "STO1 ADC MIX R", "Stereo1 ADC MIXR" }, 3305 { "IB9 Mux", "STO2 ADC MIX R", "Stereo2 ADC MIXR" }, 3306 { "IB9 Mux", "STO3 ADC MIX R", "Stereo3 ADC MIXR" }, 3307 { "IB9 Mux", "STO4 ADC MIX R", "Stereo4 ADC MIXR" }, 3308 { "IB9 Mux", "MONO ADC MIX R", "Mono ADC MIXR" }, 3309 { "IB9 Mux", "DACR1 FS", "DAC1 MIXR" }, 3310 { "IB9 Mux", "DAC1 FS", "DAC1 FS" }, 3311 3312 { "OB01 MIX", "IB01 Switch", "IB01 Bypass Mux" }, 3313 { "OB01 MIX", "IB23 Switch", "IB23 Bypass Mux" }, 3314 { "OB01 MIX", "IB45 Switch", "IB45 Bypass Mux" }, 3315 { "OB01 MIX", "IB6 Switch", "IB6 Mux" }, 3316 { "OB01 MIX", "IB7 Switch", "IB7 Mux" }, 3317 { "OB01 MIX", "IB8 Switch", "IB8 Mux" }, 3318 { "OB01 MIX", "IB9 Switch", "IB9 Mux" }, 3319 3320 { "OB23 MIX", "IB01 Switch", "IB01 Bypass Mux" }, 3321 { "OB23 MIX", "IB23 Switch", "IB23 Bypass Mux" }, 3322 { "OB23 MIX", "IB45 Switch", "IB45 Bypass Mux" }, 3323 { "OB23 MIX", "IB6 Switch", "IB6 Mux" }, 3324 { "OB23 MIX", "IB7 Switch", "IB7 Mux" }, 3325 { "OB23 MIX", "IB8 Switch", "IB8 Mux" }, 3326 { "OB23 MIX", "IB9 Switch", "IB9 Mux" }, 3327 3328 { "OB4 MIX", "IB01 Switch", "IB01 Bypass Mux" }, 3329 { "OB4 MIX", "IB23 Switch", "IB23 Bypass Mux" }, 3330 { "OB4 MIX", "IB45 Switch", "IB45 Bypass Mux" }, 3331 { "OB4 MIX", "IB6 Switch", "IB6 Mux" }, 3332 { "OB4 MIX", "IB7 Switch", "IB7 Mux" }, 3333 { "OB4 MIX", "IB8 Switch", "IB8 Mux" }, 3334 { "OB4 MIX", "IB9 Switch", "IB9 Mux" }, 3335 3336 { "OB5 MIX", "IB01 Switch", "IB01 Bypass Mux" }, 3337 { "OB5 MIX", "IB23 Switch", "IB23 Bypass Mux" }, 3338 { "OB5 MIX", "IB45 Switch", "IB45 Bypass Mux" }, 3339 { "OB5 MIX", "IB6 Switch", "IB6 Mux" }, 3340 { "OB5 MIX", "IB7 Switch", "IB7 Mux" }, 3341 { "OB5 MIX", "IB8 Switch", "IB8 Mux" }, 3342 { "OB5 MIX", "IB9 Switch", "IB9 Mux" }, 3343 3344 { "OB6 MIX", "IB01 Switch", "IB01 Bypass Mux" }, 3345 { "OB6 MIX", "IB23 Switch", "IB23 Bypass Mux" }, 3346 { "OB6 MIX", "IB45 Switch", "IB45 Bypass Mux" }, 3347 { "OB6 MIX", "IB6 Switch", "IB6 Mux" }, 3348 { "OB6 MIX", "IB7 Switch", "IB7 Mux" }, 3349 { "OB6 MIX", "IB8 Switch", "IB8 Mux" }, 3350 { "OB6 MIX", "IB9 Switch", "IB9 Mux" }, 3351 3352 { "OB7 MIX", "IB01 Switch", "IB01 Bypass Mux" }, 3353 { "OB7 MIX", "IB23 Switch", "IB23 Bypass Mux" }, 3354 { "OB7 MIX", "IB45 Switch", "IB45 Bypass Mux" }, 3355 { "OB7 MIX", "IB6 Switch", "IB6 Mux" }, 3356 { "OB7 MIX", "IB7 Switch", "IB7 Mux" }, 3357 { "OB7 MIX", "IB8 Switch", "IB8 Mux" }, 3358 { "OB7 MIX", "IB9 Switch", "IB9 Mux" }, 3359 3360 { "OB01 Bypass Mux", "Bypass", "OB01 MIX" }, 3361 { "OB01 Bypass Mux", "Pass SRC", "OB01 MIX" }, 3362 { "OB23 Bypass Mux", "Bypass", "OB23 MIX" }, 3363 { "OB23 Bypass Mux", "Pass SRC", "OB23 MIX" }, 3364 3365 { "OutBound2", NULL, "OB23 Bypass Mux" }, 3366 { "OutBound3", NULL, "OB23 Bypass Mux" }, 3367 { "OutBound4", NULL, "OB4 MIX" }, 3368 { "OutBound5", NULL, "OB5 MIX" }, 3369 { "OutBound6", NULL, "OB6 MIX" }, 3370 { "OutBound7", NULL, "OB7 MIX" }, 3371 3372 { "OB45", NULL, "OutBound4" }, 3373 { "OB45", NULL, "OutBound5" }, 3374 { "OB67", NULL, "OutBound6" }, 3375 { "OB67", NULL, "OutBound7" }, 3376 3377 { "IF1 DAC0", NULL, "AIF1RX" }, 3378 { "IF1 DAC1", NULL, "AIF1RX" }, 3379 { "IF1 DAC2", NULL, "AIF1RX" }, 3380 { "IF1 DAC3", NULL, "AIF1RX" }, 3381 { "IF1 DAC4", NULL, "AIF1RX" }, 3382 { "IF1 DAC5", NULL, "AIF1RX" }, 3383 { "IF1 DAC6", NULL, "AIF1RX" }, 3384 { "IF1 DAC7", NULL, "AIF1RX" }, 3385 { "IF1 DAC0", NULL, "I2S1" }, 3386 { "IF1 DAC1", NULL, "I2S1" }, 3387 { "IF1 DAC2", NULL, "I2S1" }, 3388 { "IF1 DAC3", NULL, "I2S1" }, 3389 { "IF1 DAC4", NULL, "I2S1" }, 3390 { "IF1 DAC5", NULL, "I2S1" }, 3391 { "IF1 DAC6", NULL, "I2S1" }, 3392 { "IF1 DAC7", NULL, "I2S1" }, 3393 3394 { "IF1 DAC0 Mux", "Slot0", "IF1 DAC0" }, 3395 { "IF1 DAC0 Mux", "Slot1", "IF1 DAC1" }, 3396 { "IF1 DAC0 Mux", "Slot2", "IF1 DAC2" }, 3397 { "IF1 DAC0 Mux", "Slot3", "IF1 DAC3" }, 3398 { "IF1 DAC0 Mux", "Slot4", "IF1 DAC4" }, 3399 { "IF1 DAC0 Mux", "Slot5", "IF1 DAC5" }, 3400 { "IF1 DAC0 Mux", "Slot6", "IF1 DAC6" }, 3401 { "IF1 DAC0 Mux", "Slot7", "IF1 DAC7" }, 3402 3403 { "IF1 DAC1 Mux", "Slot0", "IF1 DAC0" }, 3404 { "IF1 DAC1 Mux", "Slot1", "IF1 DAC1" }, 3405 { "IF1 DAC1 Mux", "Slot2", "IF1 DAC2" }, 3406 { "IF1 DAC1 Mux", "Slot3", "IF1 DAC3" }, 3407 { "IF1 DAC1 Mux", "Slot4", "IF1 DAC4" }, 3408 { "IF1 DAC1 Mux", "Slot5", "IF1 DAC5" }, 3409 { "IF1 DAC1 Mux", "Slot6", "IF1 DAC6" }, 3410 { "IF1 DAC1 Mux", "Slot7", "IF1 DAC7" }, 3411 3412 { "IF1 DAC2 Mux", "Slot0", "IF1 DAC0" }, 3413 { "IF1 DAC2 Mux", "Slot1", "IF1 DAC1" }, 3414 { "IF1 DAC2 Mux", "Slot2", "IF1 DAC2" }, 3415 { "IF1 DAC2 Mux", "Slot3", "IF1 DAC3" }, 3416 { "IF1 DAC2 Mux", "Slot4", "IF1 DAC4" }, 3417 { "IF1 DAC2 Mux", "Slot5", "IF1 DAC5" }, 3418 { "IF1 DAC2 Mux", "Slot6", "IF1 DAC6" }, 3419 { "IF1 DAC2 Mux", "Slot7", "IF1 DAC7" }, 3420 3421 { "IF1 DAC3 Mux", "Slot0", "IF1 DAC0" }, 3422 { "IF1 DAC3 Mux", "Slot1", "IF1 DAC1" }, 3423 { "IF1 DAC3 Mux", "Slot2", "IF1 DAC2" }, 3424 { "IF1 DAC3 Mux", "Slot3", "IF1 DAC3" }, 3425 { "IF1 DAC3 Mux", "Slot4", "IF1 DAC4" }, 3426 { "IF1 DAC3 Mux", "Slot5", "IF1 DAC5" }, 3427 { "IF1 DAC3 Mux", "Slot6", "IF1 DAC6" }, 3428 { "IF1 DAC3 Mux", "Slot7", "IF1 DAC7" }, 3429 3430 { "IF1 DAC4 Mux", "Slot0", "IF1 DAC0" }, 3431 { "IF1 DAC4 Mux", "Slot1", "IF1 DAC1" }, 3432 { "IF1 DAC4 Mux", "Slot2", "IF1 DAC2" }, 3433 { "IF1 DAC4 Mux", "Slot3", "IF1 DAC3" }, 3434 { "IF1 DAC4 Mux", "Slot4", "IF1 DAC4" }, 3435 { "IF1 DAC4 Mux", "Slot5", "IF1 DAC5" }, 3436 { "IF1 DAC4 Mux", "Slot6", "IF1 DAC6" }, 3437 { "IF1 DAC4 Mux", "Slot7", "IF1 DAC7" }, 3438 3439 { "IF1 DAC5 Mux", "Slot0", "IF1 DAC0" }, 3440 { "IF1 DAC5 Mux", "Slot1", "IF1 DAC1" }, 3441 { "IF1 DAC5 Mux", "Slot2", "IF1 DAC2" }, 3442 { "IF1 DAC5 Mux", "Slot3", "IF1 DAC3" }, 3443 { "IF1 DAC5 Mux", "Slot4", "IF1 DAC4" }, 3444 { "IF1 DAC5 Mux", "Slot5", "IF1 DAC5" }, 3445 { "IF1 DAC5 Mux", "Slot6", "IF1 DAC6" }, 3446 { "IF1 DAC5 Mux", "Slot7", "IF1 DAC7" }, 3447 3448 { "IF1 DAC6 Mux", "Slot0", "IF1 DAC0" }, 3449 { "IF1 DAC6 Mux", "Slot1", "IF1 DAC1" }, 3450 { "IF1 DAC6 Mux", "Slot2", "IF1 DAC2" }, 3451 { "IF1 DAC6 Mux", "Slot3", "IF1 DAC3" }, 3452 { "IF1 DAC6 Mux", "Slot4", "IF1 DAC4" }, 3453 { "IF1 DAC6 Mux", "Slot5", "IF1 DAC5" }, 3454 { "IF1 DAC6 Mux", "Slot6", "IF1 DAC6" }, 3455 { "IF1 DAC6 Mux", "Slot7", "IF1 DAC7" }, 3456 3457 { "IF1 DAC7 Mux", "Slot0", "IF1 DAC0" }, 3458 { "IF1 DAC7 Mux", "Slot1", "IF1 DAC1" }, 3459 { "IF1 DAC7 Mux", "Slot2", "IF1 DAC2" }, 3460 { "IF1 DAC7 Mux", "Slot3", "IF1 DAC3" }, 3461 { "IF1 DAC7 Mux", "Slot4", "IF1 DAC4" }, 3462 { "IF1 DAC7 Mux", "Slot5", "IF1 DAC5" }, 3463 { "IF1 DAC7 Mux", "Slot6", "IF1 DAC6" }, 3464 { "IF1 DAC7 Mux", "Slot7", "IF1 DAC7" }, 3465 3466 { "IF1 DAC01", NULL, "IF1 DAC0 Mux" }, 3467 { "IF1 DAC01", NULL, "IF1 DAC1 Mux" }, 3468 { "IF1 DAC23", NULL, "IF1 DAC2 Mux" }, 3469 { "IF1 DAC23", NULL, "IF1 DAC3 Mux" }, 3470 { "IF1 DAC45", NULL, "IF1 DAC4 Mux" }, 3471 { "IF1 DAC45", NULL, "IF1 DAC5 Mux" }, 3472 { "IF1 DAC67", NULL, "IF1 DAC6 Mux" }, 3473 { "IF1 DAC67", NULL, "IF1 DAC7 Mux" }, 3474 3475 { "IF2 DAC0", NULL, "AIF2RX" }, 3476 { "IF2 DAC1", NULL, "AIF2RX" }, 3477 { "IF2 DAC2", NULL, "AIF2RX" }, 3478 { "IF2 DAC3", NULL, "AIF2RX" }, 3479 { "IF2 DAC4", NULL, "AIF2RX" }, 3480 { "IF2 DAC5", NULL, "AIF2RX" }, 3481 { "IF2 DAC6", NULL, "AIF2RX" }, 3482 { "IF2 DAC7", NULL, "AIF2RX" }, 3483 { "IF2 DAC0", NULL, "I2S2" }, 3484 { "IF2 DAC1", NULL, "I2S2" }, 3485 { "IF2 DAC2", NULL, "I2S2" }, 3486 { "IF2 DAC3", NULL, "I2S2" }, 3487 { "IF2 DAC4", NULL, "I2S2" }, 3488 { "IF2 DAC5", NULL, "I2S2" }, 3489 { "IF2 DAC6", NULL, "I2S2" }, 3490 { "IF2 DAC7", NULL, "I2S2" }, 3491 3492 { "IF2 DAC0 Mux", "Slot0", "IF2 DAC0" }, 3493 { "IF2 DAC0 Mux", "Slot1", "IF2 DAC1" }, 3494 { "IF2 DAC0 Mux", "Slot2", "IF2 DAC2" }, 3495 { "IF2 DAC0 Mux", "Slot3", "IF2 DAC3" }, 3496 { "IF2 DAC0 Mux", "Slot4", "IF2 DAC4" }, 3497 { "IF2 DAC0 Mux", "Slot5", "IF2 DAC5" }, 3498 { "IF2 DAC0 Mux", "Slot6", "IF2 DAC6" }, 3499 { "IF2 DAC0 Mux", "Slot7", "IF2 DAC7" }, 3500 3501 { "IF2 DAC1 Mux", "Slot0", "IF2 DAC0" }, 3502 { "IF2 DAC1 Mux", "Slot1", "IF2 DAC1" }, 3503 { "IF2 DAC1 Mux", "Slot2", "IF2 DAC2" }, 3504 { "IF2 DAC1 Mux", "Slot3", "IF2 DAC3" }, 3505 { "IF2 DAC1 Mux", "Slot4", "IF2 DAC4" }, 3506 { "IF2 DAC1 Mux", "Slot5", "IF2 DAC5" }, 3507 { "IF2 DAC1 Mux", "Slot6", "IF2 DAC6" }, 3508 { "IF2 DAC1 Mux", "Slot7", "IF2 DAC7" }, 3509 3510 { "IF2 DAC2 Mux", "Slot0", "IF2 DAC0" }, 3511 { "IF2 DAC2 Mux", "Slot1", "IF2 DAC1" }, 3512 { "IF2 DAC2 Mux", "Slot2", "IF2 DAC2" }, 3513 { "IF2 DAC2 Mux", "Slot3", "IF2 DAC3" }, 3514 { "IF2 DAC2 Mux", "Slot4", "IF2 DAC4" }, 3515 { "IF2 DAC2 Mux", "Slot5", "IF2 DAC5" }, 3516 { "IF2 DAC2 Mux", "Slot6", "IF2 DAC6" }, 3517 { "IF2 DAC2 Mux", "Slot7", "IF2 DAC7" }, 3518 3519 { "IF2 DAC3 Mux", "Slot0", "IF2 DAC0" }, 3520 { "IF2 DAC3 Mux", "Slot1", "IF2 DAC1" }, 3521 { "IF2 DAC3 Mux", "Slot2", "IF2 DAC2" }, 3522 { "IF2 DAC3 Mux", "Slot3", "IF2 DAC3" }, 3523 { "IF2 DAC3 Mux", "Slot4", "IF2 DAC4" }, 3524 { "IF2 DAC3 Mux", "Slot5", "IF2 DAC5" }, 3525 { "IF2 DAC3 Mux", "Slot6", "IF2 DAC6" }, 3526 { "IF2 DAC3 Mux", "Slot7", "IF2 DAC7" }, 3527 3528 { "IF2 DAC4 Mux", "Slot0", "IF2 DAC0" }, 3529 { "IF2 DAC4 Mux", "Slot1", "IF2 DAC1" }, 3530 { "IF2 DAC4 Mux", "Slot2", "IF2 DAC2" }, 3531 { "IF2 DAC4 Mux", "Slot3", "IF2 DAC3" }, 3532 { "IF2 DAC4 Mux", "Slot4", "IF2 DAC4" }, 3533 { "IF2 DAC4 Mux", "Slot5", "IF2 DAC5" }, 3534 { "IF2 DAC4 Mux", "Slot6", "IF2 DAC6" }, 3535 { "IF2 DAC4 Mux", "Slot7", "IF2 DAC7" }, 3536 3537 { "IF2 DAC5 Mux", "Slot0", "IF2 DAC0" }, 3538 { "IF2 DAC5 Mux", "Slot1", "IF2 DAC1" }, 3539 { "IF2 DAC5 Mux", "Slot2", "IF2 DAC2" }, 3540 { "IF2 DAC5 Mux", "Slot3", "IF2 DAC3" }, 3541 { "IF2 DAC5 Mux", "Slot4", "IF2 DAC4" }, 3542 { "IF2 DAC5 Mux", "Slot5", "IF2 DAC5" }, 3543 { "IF2 DAC5 Mux", "Slot6", "IF2 DAC6" }, 3544 { "IF2 DAC5 Mux", "Slot7", "IF2 DAC7" }, 3545 3546 { "IF2 DAC6 Mux", "Slot0", "IF2 DAC0" }, 3547 { "IF2 DAC6 Mux", "Slot1", "IF2 DAC1" }, 3548 { "IF2 DAC6 Mux", "Slot2", "IF2 DAC2" }, 3549 { "IF2 DAC6 Mux", "Slot3", "IF2 DAC3" }, 3550 { "IF2 DAC6 Mux", "Slot4", "IF2 DAC4" }, 3551 { "IF2 DAC6 Mux", "Slot5", "IF2 DAC5" }, 3552 { "IF2 DAC6 Mux", "Slot6", "IF2 DAC6" }, 3553 { "IF2 DAC6 Mux", "Slot7", "IF2 DAC7" }, 3554 3555 { "IF2 DAC7 Mux", "Slot0", "IF2 DAC0" }, 3556 { "IF2 DAC7 Mux", "Slot1", "IF2 DAC1" }, 3557 { "IF2 DAC7 Mux", "Slot2", "IF2 DAC2" }, 3558 { "IF2 DAC7 Mux", "Slot3", "IF2 DAC3" }, 3559 { "IF2 DAC7 Mux", "Slot4", "IF2 DAC4" }, 3560 { "IF2 DAC7 Mux", "Slot5", "IF2 DAC5" }, 3561 { "IF2 DAC7 Mux", "Slot6", "IF2 DAC6" }, 3562 { "IF2 DAC7 Mux", "Slot7", "IF2 DAC7" }, 3563 3564 { "IF2 DAC01", NULL, "IF2 DAC0 Mux" }, 3565 { "IF2 DAC01", NULL, "IF2 DAC1 Mux" }, 3566 { "IF2 DAC23", NULL, "IF2 DAC2 Mux" }, 3567 { "IF2 DAC23", NULL, "IF2 DAC3 Mux" }, 3568 { "IF2 DAC45", NULL, "IF2 DAC4 Mux" }, 3569 { "IF2 DAC45", NULL, "IF2 DAC5 Mux" }, 3570 { "IF2 DAC67", NULL, "IF2 DAC6 Mux" }, 3571 { "IF2 DAC67", NULL, "IF2 DAC7 Mux" }, 3572 3573 { "IF3 DAC", NULL, "AIF3RX" }, 3574 { "IF3 DAC", NULL, "I2S3" }, 3575 3576 { "IF4 DAC", NULL, "AIF4RX" }, 3577 { "IF4 DAC", NULL, "I2S4" }, 3578 3579 { "IF3 DAC L", NULL, "IF3 DAC" }, 3580 { "IF3 DAC R", NULL, "IF3 DAC" }, 3581 3582 { "IF4 DAC L", NULL, "IF4 DAC" }, 3583 { "IF4 DAC R", NULL, "IF4 DAC" }, 3584 3585 { "SLB DAC0", NULL, "SLBRX" }, 3586 { "SLB DAC1", NULL, "SLBRX" }, 3587 { "SLB DAC2", NULL, "SLBRX" }, 3588 { "SLB DAC3", NULL, "SLBRX" }, 3589 { "SLB DAC4", NULL, "SLBRX" }, 3590 { "SLB DAC5", NULL, "SLBRX" }, 3591 { "SLB DAC6", NULL, "SLBRX" }, 3592 { "SLB DAC7", NULL, "SLBRX" }, 3593 { "SLB DAC0", NULL, "SLB" }, 3594 { "SLB DAC1", NULL, "SLB" }, 3595 { "SLB DAC2", NULL, "SLB" }, 3596 { "SLB DAC3", NULL, "SLB" }, 3597 { "SLB DAC4", NULL, "SLB" }, 3598 { "SLB DAC5", NULL, "SLB" }, 3599 { "SLB DAC6", NULL, "SLB" }, 3600 { "SLB DAC7", NULL, "SLB" }, 3601 3602 { "SLB DAC01", NULL, "SLB DAC0" }, 3603 { "SLB DAC01", NULL, "SLB DAC1" }, 3604 { "SLB DAC23", NULL, "SLB DAC2" }, 3605 { "SLB DAC23", NULL, "SLB DAC3" }, 3606 { "SLB DAC45", NULL, "SLB DAC4" }, 3607 { "SLB DAC45", NULL, "SLB DAC5" }, 3608 { "SLB DAC67", NULL, "SLB DAC6" }, 3609 { "SLB DAC67", NULL, "SLB DAC7" }, 3610 3611 { "ADDA1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" }, 3612 { "ADDA1 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" }, 3613 { "ADDA1 Mux", "OB 67", "OB67" }, 3614 3615 { "DAC1 Mux", "IF1 DAC 01", "IF1 DAC01" }, 3616 { "DAC1 Mux", "IF2 DAC 01", "IF2 DAC01" }, 3617 { "DAC1 Mux", "IF3 DAC LR", "IF3 DAC" }, 3618 { "DAC1 Mux", "IF4 DAC LR", "IF4 DAC" }, 3619 { "DAC1 Mux", "SLB DAC 01", "SLB DAC01" }, 3620 { "DAC1 Mux", "OB 01", "OB01 Bypass Mux" }, 3621 3622 { "DAC1 MIXL", "Stereo ADC Switch", "ADDA1 Mux" }, 3623 { "DAC1 MIXL", "DAC1 Switch", "DAC1 Mux" }, 3624 { "DAC1 MIXR", "Stereo ADC Switch", "ADDA1 Mux" }, 3625 { "DAC1 MIXR", "DAC1 Switch", "DAC1 Mux" }, 3626 3627 { "DAC1 FS", NULL, "DAC1 MIXL" }, 3628 { "DAC1 FS", NULL, "DAC1 MIXR" }, 3629 3630 { "DAC2 L Mux", "IF1 DAC 2", "IF1 DAC2" }, 3631 { "DAC2 L Mux", "IF2 DAC 2", "IF2 DAC2" }, 3632 { "DAC2 L Mux", "IF3 DAC L", "IF3 DAC L" }, 3633 { "DAC2 L Mux", "IF4 DAC L", "IF4 DAC L" }, 3634 { "DAC2 L Mux", "SLB DAC 2", "SLB DAC2" }, 3635 { "DAC2 L Mux", "OB 2", "OutBound2" }, 3636 3637 { "DAC2 R Mux", "IF1 DAC 3", "IF1 DAC3" }, 3638 { "DAC2 R Mux", "IF2 DAC 3", "IF2 DAC3" }, 3639 { "DAC2 R Mux", "IF3 DAC R", "IF3 DAC R" }, 3640 { "DAC2 R Mux", "IF4 DAC R", "IF4 DAC R" }, 3641 { "DAC2 R Mux", "SLB DAC 3", "SLB DAC3" }, 3642 { "DAC2 R Mux", "OB 3", "OutBound3" }, 3643 { "DAC2 R Mux", "Haptic Generator", "Haptic Generator" }, 3644 { "DAC2 R Mux", "VAD ADC", "VAD ADC Mux" }, 3645 3646 { "DAC3 L Mux", "IF1 DAC 4", "IF1 DAC4" }, 3647 { "DAC3 L Mux", "IF2 DAC 4", "IF2 DAC4" }, 3648 { "DAC3 L Mux", "IF3 DAC L", "IF3 DAC L" }, 3649 { "DAC3 L Mux", "IF4 DAC L", "IF4 DAC L" }, 3650 { "DAC3 L Mux", "SLB DAC 4", "SLB DAC4" }, 3651 { "DAC3 L Mux", "OB 4", "OutBound4" }, 3652 3653 { "DAC3 R Mux", "IF1 DAC 5", "IF1 DAC4" }, 3654 { "DAC3 R Mux", "IF2 DAC 5", "IF2 DAC4" }, 3655 { "DAC3 R Mux", "IF3 DAC R", "IF3 DAC R" }, 3656 { "DAC3 R Mux", "IF4 DAC R", "IF4 DAC R" }, 3657 { "DAC3 R Mux", "SLB DAC 5", "SLB DAC5" }, 3658 { "DAC3 R Mux", "OB 5", "OutBound5" }, 3659 3660 { "DAC4 L Mux", "IF1 DAC 6", "IF1 DAC6" }, 3661 { "DAC4 L Mux", "IF2 DAC 6", "IF2 DAC6" }, 3662 { "DAC4 L Mux", "IF3 DAC L", "IF3 DAC L" }, 3663 { "DAC4 L Mux", "IF4 DAC L", "IF4 DAC L" }, 3664 { "DAC4 L Mux", "SLB DAC 6", "SLB DAC6" }, 3665 { "DAC4 L Mux", "OB 6", "OutBound6" }, 3666 3667 { "DAC4 R Mux", "IF1 DAC 7", "IF1 DAC7" }, 3668 { "DAC4 R Mux", "IF2 DAC 7", "IF2 DAC7" }, 3669 { "DAC4 R Mux", "IF3 DAC R", "IF3 DAC R" }, 3670 { "DAC4 R Mux", "IF4 DAC R", "IF4 DAC R" }, 3671 { "DAC4 R Mux", "SLB DAC 7", "SLB DAC7" }, 3672 { "DAC4 R Mux", "OB 7", "OutBound7" }, 3673 3674 { "Sidetone Mux", "DMIC1 L", "DMIC L1" }, 3675 { "Sidetone Mux", "DMIC2 L", "DMIC L2" }, 3676 { "Sidetone Mux", "DMIC3 L", "DMIC L3" }, 3677 { "Sidetone Mux", "DMIC4 L", "DMIC L4" }, 3678 { "Sidetone Mux", "ADC1", "ADC 1" }, 3679 { "Sidetone Mux", "ADC2", "ADC 2" }, 3680 { "Sidetone Mux", NULL, "Sidetone Power" }, 3681 3682 { "Stereo DAC MIXL", "ST L Switch", "Sidetone Mux" }, 3683 { "Stereo DAC MIXL", "DAC1 L Switch", "DAC1 MIXL" }, 3684 { "Stereo DAC MIXL", "DAC2 L Switch", "DAC2 L Mux" }, 3685 { "Stereo DAC MIXL", "DAC1 R Switch", "DAC1 MIXR" }, 3686 { "Stereo DAC MIXL", NULL, "dac stereo1 filter" }, 3687 { "Stereo DAC MIXR", "ST R Switch", "Sidetone Mux" }, 3688 { "Stereo DAC MIXR", "DAC1 R Switch", "DAC1 MIXR" }, 3689 { "Stereo DAC MIXR", "DAC2 R Switch", "DAC2 R Mux" }, 3690 { "Stereo DAC MIXR", "DAC1 L Switch", "DAC1 MIXL" }, 3691 { "Stereo DAC MIXR", NULL, "dac stereo1 filter" }, 3692 { "dac stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll }, 3693 3694 { "Mono DAC MIXL", "ST L Switch", "Sidetone Mux" }, 3695 { "Mono DAC MIXL", "DAC1 L Switch", "DAC1 MIXL" }, 3696 { "Mono DAC MIXL", "DAC2 L Switch", "DAC2 L Mux" }, 3697 { "Mono DAC MIXL", "DAC2 R Switch", "DAC2 R Mux" }, 3698 { "Mono DAC MIXL", NULL, "dac mono2 left filter" }, 3699 { "dac mono2 left filter", NULL, "PLL1", is_sys_clk_from_pll }, 3700 { "Mono DAC MIXR", "ST R Switch", "Sidetone Mux" }, 3701 { "Mono DAC MIXR", "DAC1 R Switch", "DAC1 MIXR" }, 3702 { "Mono DAC MIXR", "DAC2 R Switch", "DAC2 R Mux" }, 3703 { "Mono DAC MIXR", "DAC2 L Switch", "DAC2 L Mux" }, 3704 { "Mono DAC MIXR", NULL, "dac mono2 right filter" }, 3705 { "dac mono2 right filter", NULL, "PLL1", is_sys_clk_from_pll }, 3706 3707 { "DD1 MIXL", "Sto DAC Mix L Switch", "Stereo DAC MIXL" }, 3708 { "DD1 MIXL", "Mono DAC Mix L Switch", "Mono DAC MIXL" }, 3709 { "DD1 MIXL", "DAC3 L Switch", "DAC3 L Mux" }, 3710 { "DD1 MIXL", "DAC3 R Switch", "DAC3 R Mux" }, 3711 { "DD1 MIXL", NULL, "dac mono3 left filter" }, 3712 { "dac mono3 left filter", NULL, "PLL1", is_sys_clk_from_pll }, 3713 { "DD1 MIXR", "Sto DAC Mix R Switch", "Stereo DAC MIXR" }, 3714 { "DD1 MIXR", "Mono DAC Mix R Switch", "Mono DAC MIXR" }, 3715 { "DD1 MIXR", "DAC3 L Switch", "DAC3 L Mux" }, 3716 { "DD1 MIXR", "DAC3 R Switch", "DAC3 R Mux" }, 3717 { "DD1 MIXR", NULL, "dac mono3 right filter" }, 3718 { "dac mono3 right filter", NULL, "PLL1", is_sys_clk_from_pll }, 3719 3720 { "DD2 MIXL", "Sto DAC Mix L Switch", "Stereo DAC MIXL" }, 3721 { "DD2 MIXL", "Mono DAC Mix L Switch", "Mono DAC MIXL" }, 3722 { "DD2 MIXL", "DAC4 L Switch", "DAC4 L Mux" }, 3723 { "DD2 MIXL", "DAC4 R Switch", "DAC4 R Mux" }, 3724 { "DD2 MIXL", NULL, "dac mono4 left filter" }, 3725 { "dac mono4 left filter", NULL, "PLL1", is_sys_clk_from_pll }, 3726 { "DD2 MIXR", "Sto DAC Mix R Switch", "Stereo DAC MIXR" }, 3727 { "DD2 MIXR", "Mono DAC Mix R Switch", "Mono DAC MIXR" }, 3728 { "DD2 MIXR", "DAC4 L Switch", "DAC4 L Mux" }, 3729 { "DD2 MIXR", "DAC4 R Switch", "DAC4 R Mux" }, 3730 { "DD2 MIXR", NULL, "dac mono4 right filter" }, 3731 { "dac mono4 right filter", NULL, "PLL1", is_sys_clk_from_pll }, 3732 3733 { "Stereo DAC MIX", NULL, "Stereo DAC MIXL" }, 3734 { "Stereo DAC MIX", NULL, "Stereo DAC MIXR" }, 3735 { "Mono DAC MIX", NULL, "Mono DAC MIXL" }, 3736 { "Mono DAC MIX", NULL, "Mono DAC MIXR" }, 3737 { "DD1 MIX", NULL, "DD1 MIXL" }, 3738 { "DD1 MIX", NULL, "DD1 MIXR" }, 3739 { "DD2 MIX", NULL, "DD2 MIXL" }, 3740 { "DD2 MIX", NULL, "DD2 MIXR" }, 3741 3742 { "DAC12 SRC Mux", "STO1 DAC MIX", "Stereo DAC MIX" }, 3743 { "DAC12 SRC Mux", "MONO DAC MIX", "Mono DAC MIX" }, 3744 { "DAC12 SRC Mux", "DD MIX1", "DD1 MIX" }, 3745 { "DAC12 SRC Mux", "DD MIX2", "DD2 MIX" }, 3746 3747 { "DAC3 SRC Mux", "MONO DAC MIXL", "Mono DAC MIXL" }, 3748 { "DAC3 SRC Mux", "MONO DAC MIXR", "Mono DAC MIXR" }, 3749 { "DAC3 SRC Mux", "DD MIX1L", "DD1 MIXL" }, 3750 { "DAC3 SRC Mux", "DD MIX2L", "DD2 MIXL" }, 3751 3752 { "DAC 1", NULL, "DAC12 SRC Mux" }, 3753 { "DAC 2", NULL, "DAC12 SRC Mux" }, 3754 { "DAC 3", NULL, "DAC3 SRC Mux" }, 3755 3756 { "PDM1 L Mux", "STO1 DAC MIX", "Stereo DAC MIXL" }, 3757 { "PDM1 L Mux", "MONO DAC MIX", "Mono DAC MIXL" }, 3758 { "PDM1 L Mux", "DD MIX1", "DD1 MIXL" }, 3759 { "PDM1 L Mux", "DD MIX2", "DD2 MIXL" }, 3760 { "PDM1 L Mux", NULL, "PDM1 Power" }, 3761 { "PDM1 R Mux", "STO1 DAC MIX", "Stereo DAC MIXR" }, 3762 { "PDM1 R Mux", "MONO DAC MIX", "Mono DAC MIXR" }, 3763 { "PDM1 R Mux", "DD MIX1", "DD1 MIXR" }, 3764 { "PDM1 R Mux", "DD MIX2", "DD2 MIXR" }, 3765 { "PDM1 R Mux", NULL, "PDM1 Power" }, 3766 { "PDM2 L Mux", "STO1 DAC MIX", "Stereo DAC MIXL" }, 3767 { "PDM2 L Mux", "MONO DAC MIX", "Mono DAC MIXL" }, 3768 { "PDM2 L Mux", "DD MIX1", "DD1 MIXL" }, 3769 { "PDM2 L Mux", "DD MIX2", "DD2 MIXL" }, 3770 { "PDM2 L Mux", NULL, "PDM2 Power" }, 3771 { "PDM2 R Mux", "STO1 DAC MIX", "Stereo DAC MIXR" }, 3772 { "PDM2 R Mux", "MONO DAC MIX", "Mono DAC MIXR" }, 3773 { "PDM2 R Mux", "DD MIX1", "DD1 MIXR" }, 3774 { "PDM2 R Mux", "DD MIX1", "DD2 MIXR" }, 3775 { "PDM2 R Mux", NULL, "PDM2 Power" }, 3776 3777 { "LOUT1 amp", NULL, "DAC 1" }, 3778 { "LOUT2 amp", NULL, "DAC 2" }, 3779 { "LOUT3 amp", NULL, "DAC 3" }, 3780 3781 { "LOUT1 vref", NULL, "LOUT1 amp" }, 3782 { "LOUT2 vref", NULL, "LOUT2 amp" }, 3783 { "LOUT3 vref", NULL, "LOUT3 amp" }, 3784 3785 { "LOUT1", NULL, "LOUT1 vref" }, 3786 { "LOUT2", NULL, "LOUT2 vref" }, 3787 { "LOUT3", NULL, "LOUT3 vref" }, 3788 3789 { "PDM1L", NULL, "PDM1 L Mux" }, 3790 { "PDM1R", NULL, "PDM1 R Mux" }, 3791 { "PDM2L", NULL, "PDM2 L Mux" }, 3792 { "PDM2R", NULL, "PDM2 R Mux" }, 3793 }; 3794 3795 static const struct snd_soc_dapm_route rt5677_dmic2_clk_1[] = { 3796 { "DMIC L2", NULL, "DMIC1 power" }, 3797 { "DMIC R2", NULL, "DMIC1 power" }, 3798 }; 3799 3800 static const struct snd_soc_dapm_route rt5677_dmic2_clk_2[] = { 3801 { "DMIC L2", NULL, "DMIC2 power" }, 3802 { "DMIC R2", NULL, "DMIC2 power" }, 3803 }; 3804 3805 static int rt5677_hw_params(struct snd_pcm_substream *substream, 3806 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) 3807 { 3808 struct snd_soc_codec *codec = dai->codec; 3809 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec); 3810 unsigned int val_len = 0, val_clk, mask_clk; 3811 int pre_div, bclk_ms, frame_size; 3812 3813 rt5677->lrck[dai->id] = params_rate(params); 3814 pre_div = rl6231_get_clk_info(rt5677->sysclk, rt5677->lrck[dai->id]); 3815 if (pre_div < 0) { 3816 dev_err(codec->dev, "Unsupported clock setting: sysclk=%dHz lrck=%dHz\n", 3817 rt5677->sysclk, rt5677->lrck[dai->id]); 3818 return -EINVAL; 3819 } 3820 frame_size = snd_soc_params_to_frame_size(params); 3821 if (frame_size < 0) { 3822 dev_err(codec->dev, "Unsupported frame size: %d\n", frame_size); 3823 return -EINVAL; 3824 } 3825 bclk_ms = frame_size > 32; 3826 rt5677->bclk[dai->id] = rt5677->lrck[dai->id] * (32 << bclk_ms); 3827 3828 dev_dbg(dai->dev, "bclk is %dHz and lrck is %dHz\n", 3829 rt5677->bclk[dai->id], rt5677->lrck[dai->id]); 3830 dev_dbg(dai->dev, "bclk_ms is %d and pre_div is %d for iis %d\n", 3831 bclk_ms, pre_div, dai->id); 3832 3833 switch (params_width(params)) { 3834 case 16: 3835 break; 3836 case 20: 3837 val_len |= RT5677_I2S_DL_20; 3838 break; 3839 case 24: 3840 val_len |= RT5677_I2S_DL_24; 3841 break; 3842 case 8: 3843 val_len |= RT5677_I2S_DL_8; 3844 break; 3845 default: 3846 return -EINVAL; 3847 } 3848 3849 switch (dai->id) { 3850 case RT5677_AIF1: 3851 mask_clk = RT5677_I2S_PD1_MASK; 3852 val_clk = pre_div << RT5677_I2S_PD1_SFT; 3853 regmap_update_bits(rt5677->regmap, RT5677_I2S1_SDP, 3854 RT5677_I2S_DL_MASK, val_len); 3855 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1, 3856 mask_clk, val_clk); 3857 break; 3858 case RT5677_AIF2: 3859 mask_clk = RT5677_I2S_PD2_MASK; 3860 val_clk = pre_div << RT5677_I2S_PD2_SFT; 3861 regmap_update_bits(rt5677->regmap, RT5677_I2S2_SDP, 3862 RT5677_I2S_DL_MASK, val_len); 3863 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1, 3864 mask_clk, val_clk); 3865 break; 3866 case RT5677_AIF3: 3867 mask_clk = RT5677_I2S_BCLK_MS3_MASK | RT5677_I2S_PD3_MASK; 3868 val_clk = bclk_ms << RT5677_I2S_BCLK_MS3_SFT | 3869 pre_div << RT5677_I2S_PD3_SFT; 3870 regmap_update_bits(rt5677->regmap, RT5677_I2S3_SDP, 3871 RT5677_I2S_DL_MASK, val_len); 3872 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1, 3873 mask_clk, val_clk); 3874 break; 3875 case RT5677_AIF4: 3876 mask_clk = RT5677_I2S_BCLK_MS4_MASK | RT5677_I2S_PD4_MASK; 3877 val_clk = bclk_ms << RT5677_I2S_BCLK_MS4_SFT | 3878 pre_div << RT5677_I2S_PD4_SFT; 3879 regmap_update_bits(rt5677->regmap, RT5677_I2S4_SDP, 3880 RT5677_I2S_DL_MASK, val_len); 3881 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1, 3882 mask_clk, val_clk); 3883 break; 3884 default: 3885 break; 3886 } 3887 3888 return 0; 3889 } 3890 3891 static int rt5677_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) 3892 { 3893 struct snd_soc_codec *codec = dai->codec; 3894 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec); 3895 unsigned int reg_val = 0; 3896 3897 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 3898 case SND_SOC_DAIFMT_CBM_CFM: 3899 rt5677->master[dai->id] = 1; 3900 break; 3901 case SND_SOC_DAIFMT_CBS_CFS: 3902 reg_val |= RT5677_I2S_MS_S; 3903 rt5677->master[dai->id] = 0; 3904 break; 3905 default: 3906 return -EINVAL; 3907 } 3908 3909 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 3910 case SND_SOC_DAIFMT_NB_NF: 3911 break; 3912 case SND_SOC_DAIFMT_IB_NF: 3913 reg_val |= RT5677_I2S_BP_INV; 3914 break; 3915 default: 3916 return -EINVAL; 3917 } 3918 3919 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 3920 case SND_SOC_DAIFMT_I2S: 3921 break; 3922 case SND_SOC_DAIFMT_LEFT_J: 3923 reg_val |= RT5677_I2S_DF_LEFT; 3924 break; 3925 case SND_SOC_DAIFMT_DSP_A: 3926 reg_val |= RT5677_I2S_DF_PCM_A; 3927 break; 3928 case SND_SOC_DAIFMT_DSP_B: 3929 reg_val |= RT5677_I2S_DF_PCM_B; 3930 break; 3931 default: 3932 return -EINVAL; 3933 } 3934 3935 switch (dai->id) { 3936 case RT5677_AIF1: 3937 regmap_update_bits(rt5677->regmap, RT5677_I2S1_SDP, 3938 RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK | 3939 RT5677_I2S_DF_MASK, reg_val); 3940 break; 3941 case RT5677_AIF2: 3942 regmap_update_bits(rt5677->regmap, RT5677_I2S2_SDP, 3943 RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK | 3944 RT5677_I2S_DF_MASK, reg_val); 3945 break; 3946 case RT5677_AIF3: 3947 regmap_update_bits(rt5677->regmap, RT5677_I2S3_SDP, 3948 RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK | 3949 RT5677_I2S_DF_MASK, reg_val); 3950 break; 3951 case RT5677_AIF4: 3952 regmap_update_bits(rt5677->regmap, RT5677_I2S4_SDP, 3953 RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK | 3954 RT5677_I2S_DF_MASK, reg_val); 3955 break; 3956 default: 3957 break; 3958 } 3959 3960 3961 return 0; 3962 } 3963 3964 static int rt5677_set_dai_sysclk(struct snd_soc_dai *dai, 3965 int clk_id, unsigned int freq, int dir) 3966 { 3967 struct snd_soc_codec *codec = dai->codec; 3968 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec); 3969 unsigned int reg_val = 0; 3970 3971 if (freq == rt5677->sysclk && clk_id == rt5677->sysclk_src) 3972 return 0; 3973 3974 switch (clk_id) { 3975 case RT5677_SCLK_S_MCLK: 3976 reg_val |= RT5677_SCLK_SRC_MCLK; 3977 break; 3978 case RT5677_SCLK_S_PLL1: 3979 reg_val |= RT5677_SCLK_SRC_PLL1; 3980 break; 3981 case RT5677_SCLK_S_RCCLK: 3982 reg_val |= RT5677_SCLK_SRC_RCCLK; 3983 break; 3984 default: 3985 dev_err(codec->dev, "Invalid clock id (%d)\n", clk_id); 3986 return -EINVAL; 3987 } 3988 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1, 3989 RT5677_SCLK_SRC_MASK, reg_val); 3990 rt5677->sysclk = freq; 3991 rt5677->sysclk_src = clk_id; 3992 3993 dev_dbg(dai->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id); 3994 3995 return 0; 3996 } 3997 3998 /** 3999 * rt5677_pll_calc - Calcualte PLL M/N/K code. 4000 * @freq_in: external clock provided to codec. 4001 * @freq_out: target clock which codec works on. 4002 * @pll_code: Pointer to structure with M, N, K, bypass K and bypass M flag. 4003 * 4004 * Calcualte M/N/K code and bypass K/M flag to configure PLL for codec. 4005 * 4006 * Returns 0 for success or negative error code. 4007 */ 4008 static int rt5677_pll_calc(const unsigned int freq_in, 4009 const unsigned int freq_out, struct rl6231_pll_code *pll_code) 4010 { 4011 if (RT5677_PLL_INP_MIN > freq_in) 4012 return -EINVAL; 4013 4014 return rl6231_pll_calc(freq_in, freq_out, pll_code); 4015 } 4016 4017 static int rt5677_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source, 4018 unsigned int freq_in, unsigned int freq_out) 4019 { 4020 struct snd_soc_codec *codec = dai->codec; 4021 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec); 4022 struct rl6231_pll_code pll_code; 4023 int ret; 4024 4025 if (source == rt5677->pll_src && freq_in == rt5677->pll_in && 4026 freq_out == rt5677->pll_out) 4027 return 0; 4028 4029 if (!freq_in || !freq_out) { 4030 dev_dbg(codec->dev, "PLL disabled\n"); 4031 4032 rt5677->pll_in = 0; 4033 rt5677->pll_out = 0; 4034 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1, 4035 RT5677_SCLK_SRC_MASK, RT5677_SCLK_SRC_MCLK); 4036 return 0; 4037 } 4038 4039 switch (source) { 4040 case RT5677_PLL1_S_MCLK: 4041 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1, 4042 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_MCLK); 4043 break; 4044 case RT5677_PLL1_S_BCLK1: 4045 case RT5677_PLL1_S_BCLK2: 4046 case RT5677_PLL1_S_BCLK3: 4047 case RT5677_PLL1_S_BCLK4: 4048 switch (dai->id) { 4049 case RT5677_AIF1: 4050 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1, 4051 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK1); 4052 break; 4053 case RT5677_AIF2: 4054 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1, 4055 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK2); 4056 break; 4057 case RT5677_AIF3: 4058 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1, 4059 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK3); 4060 break; 4061 case RT5677_AIF4: 4062 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1, 4063 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK4); 4064 break; 4065 default: 4066 break; 4067 } 4068 break; 4069 default: 4070 dev_err(codec->dev, "Unknown PLL source %d\n", source); 4071 return -EINVAL; 4072 } 4073 4074 ret = rt5677_pll_calc(freq_in, freq_out, &pll_code); 4075 if (ret < 0) { 4076 dev_err(codec->dev, "Unsupport input clock %d\n", freq_in); 4077 return ret; 4078 } 4079 4080 dev_dbg(codec->dev, "m_bypass=%d m=%d n=%d k=%d\n", 4081 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code), 4082 pll_code.n_code, pll_code.k_code); 4083 4084 regmap_write(rt5677->regmap, RT5677_PLL1_CTRL1, 4085 pll_code.n_code << RT5677_PLL_N_SFT | pll_code.k_code); 4086 regmap_write(rt5677->regmap, RT5677_PLL1_CTRL2, 4087 (pll_code.m_bp ? 0 : pll_code.m_code) << RT5677_PLL_M_SFT | 4088 pll_code.m_bp << RT5677_PLL_M_BP_SFT); 4089 4090 rt5677->pll_in = freq_in; 4091 rt5677->pll_out = freq_out; 4092 rt5677->pll_src = source; 4093 4094 return 0; 4095 } 4096 4097 static int rt5677_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask, 4098 unsigned int rx_mask, int slots, int slot_width) 4099 { 4100 struct snd_soc_codec *codec = dai->codec; 4101 unsigned int val = 0; 4102 4103 if (rx_mask || tx_mask) 4104 val |= (1 << 12); 4105 4106 switch (slots) { 4107 case 4: 4108 val |= (1 << 10); 4109 break; 4110 case 6: 4111 val |= (2 << 10); 4112 break; 4113 case 8: 4114 val |= (3 << 10); 4115 break; 4116 case 2: 4117 default: 4118 break; 4119 } 4120 4121 switch (slot_width) { 4122 case 20: 4123 val |= (1 << 8); 4124 break; 4125 case 24: 4126 val |= (2 << 8); 4127 break; 4128 case 32: 4129 val |= (3 << 8); 4130 break; 4131 case 16: 4132 default: 4133 break; 4134 } 4135 4136 switch (dai->id) { 4137 case RT5677_AIF1: 4138 snd_soc_update_bits(codec, RT5677_TDM1_CTRL1, 0x1f00, val); 4139 break; 4140 case RT5677_AIF2: 4141 snd_soc_update_bits(codec, RT5677_TDM2_CTRL1, 0x1f00, val); 4142 break; 4143 default: 4144 break; 4145 } 4146 4147 return 0; 4148 } 4149 4150 static int rt5677_set_bias_level(struct snd_soc_codec *codec, 4151 enum snd_soc_bias_level level) 4152 { 4153 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec); 4154 4155 switch (level) { 4156 case SND_SOC_BIAS_ON: 4157 break; 4158 4159 case SND_SOC_BIAS_PREPARE: 4160 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY) { 4161 rt5677_set_dsp_vad(codec, false); 4162 4163 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1, 4164 RT5677_LDO1_SEL_MASK | RT5677_LDO2_SEL_MASK, 4165 0x0055); 4166 regmap_update_bits(rt5677->regmap, 4167 RT5677_PR_BASE + RT5677_BIAS_CUR4, 4168 0x0f00, 0x0f00); 4169 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1, 4170 RT5677_PWR_FV1 | RT5677_PWR_FV2 | 4171 RT5677_PWR_VREF1 | RT5677_PWR_MB | 4172 RT5677_PWR_BG | RT5677_PWR_VREF2, 4173 RT5677_PWR_VREF1 | RT5677_PWR_MB | 4174 RT5677_PWR_BG | RT5677_PWR_VREF2); 4175 rt5677->is_vref_slow = false; 4176 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2, 4177 RT5677_PWR_CORE, RT5677_PWR_CORE); 4178 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 4179 0x1, 0x1); 4180 } 4181 break; 4182 4183 case SND_SOC_BIAS_STANDBY: 4184 break; 4185 4186 case SND_SOC_BIAS_OFF: 4187 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x1, 0x0); 4188 regmap_write(rt5677->regmap, RT5677_PWR_DIG1, 0x0000); 4189 regmap_write(rt5677->regmap, RT5677_PWR_DIG2, 0x0000); 4190 regmap_write(rt5677->regmap, RT5677_PWR_ANLG1, 0x0022); 4191 regmap_write(rt5677->regmap, RT5677_PWR_ANLG2, 0x0000); 4192 regmap_update_bits(rt5677->regmap, 4193 RT5677_PR_BASE + RT5677_BIAS_CUR4, 0x0f00, 0x0000); 4194 4195 if (rt5677->dsp_vad_en) 4196 rt5677_set_dsp_vad(codec, true); 4197 break; 4198 4199 default: 4200 break; 4201 } 4202 codec->dapm.bias_level = level; 4203 4204 return 0; 4205 } 4206 4207 #ifdef CONFIG_GPIOLIB 4208 static inline struct rt5677_priv *gpio_to_rt5677(struct gpio_chip *chip) 4209 { 4210 return container_of(chip, struct rt5677_priv, gpio_chip); 4211 } 4212 4213 static void rt5677_gpio_set(struct gpio_chip *chip, unsigned offset, int value) 4214 { 4215 struct rt5677_priv *rt5677 = gpio_to_rt5677(chip); 4216 4217 switch (offset) { 4218 case RT5677_GPIO1 ... RT5677_GPIO5: 4219 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2, 4220 0x1 << (offset * 3 + 1), !!value << (offset * 3 + 1)); 4221 break; 4222 4223 case RT5677_GPIO6: 4224 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL3, 4225 RT5677_GPIO6_OUT_MASK, !!value << RT5677_GPIO6_OUT_SFT); 4226 break; 4227 4228 default: 4229 break; 4230 } 4231 } 4232 4233 static int rt5677_gpio_direction_out(struct gpio_chip *chip, 4234 unsigned offset, int value) 4235 { 4236 struct rt5677_priv *rt5677 = gpio_to_rt5677(chip); 4237 4238 switch (offset) { 4239 case RT5677_GPIO1 ... RT5677_GPIO5: 4240 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2, 4241 0x3 << (offset * 3 + 1), 4242 (0x2 | !!value) << (offset * 3 + 1)); 4243 break; 4244 4245 case RT5677_GPIO6: 4246 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL3, 4247 RT5677_GPIO6_DIR_MASK | RT5677_GPIO6_OUT_MASK, 4248 RT5677_GPIO6_DIR_OUT | !!value << RT5677_GPIO6_OUT_SFT); 4249 break; 4250 4251 default: 4252 break; 4253 } 4254 4255 return 0; 4256 } 4257 4258 static int rt5677_gpio_get(struct gpio_chip *chip, unsigned offset) 4259 { 4260 struct rt5677_priv *rt5677 = gpio_to_rt5677(chip); 4261 int value, ret; 4262 4263 ret = regmap_read(rt5677->regmap, RT5677_GPIO_ST, &value); 4264 if (ret < 0) 4265 return ret; 4266 4267 return (value & (0x1 << offset)) >> offset; 4268 } 4269 4270 static int rt5677_gpio_direction_in(struct gpio_chip *chip, unsigned offset) 4271 { 4272 struct rt5677_priv *rt5677 = gpio_to_rt5677(chip); 4273 4274 switch (offset) { 4275 case RT5677_GPIO1 ... RT5677_GPIO5: 4276 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2, 4277 0x1 << (offset * 3 + 2), 0x0); 4278 break; 4279 4280 case RT5677_GPIO6: 4281 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL3, 4282 RT5677_GPIO6_DIR_MASK, RT5677_GPIO6_DIR_IN); 4283 break; 4284 4285 default: 4286 break; 4287 } 4288 4289 return 0; 4290 } 4291 4292 /** Configures the gpio as 4293 * 0 - floating 4294 * 1 - pull down 4295 * 2 - pull up 4296 */ 4297 static void rt5677_gpio_config(struct rt5677_priv *rt5677, unsigned offset, 4298 int value) 4299 { 4300 int shift; 4301 4302 switch (offset) { 4303 case RT5677_GPIO1 ... RT5677_GPIO2: 4304 shift = 2 * (1 - offset); 4305 regmap_update_bits(rt5677->regmap, 4306 RT5677_PR_BASE + RT5677_DIG_IN_PIN_ST_CTRL2, 4307 0x3 << shift, 4308 (value & 0x3) << shift); 4309 break; 4310 4311 case RT5677_GPIO3 ... RT5677_GPIO6: 4312 shift = 2 * (9 - offset); 4313 regmap_update_bits(rt5677->regmap, 4314 RT5677_PR_BASE + RT5677_DIG_IN_PIN_ST_CTRL3, 4315 0x3 << shift, 4316 (value & 0x3) << shift); 4317 break; 4318 4319 default: 4320 break; 4321 } 4322 } 4323 4324 static int rt5677_to_irq(struct gpio_chip *chip, unsigned offset) 4325 { 4326 struct rt5677_priv *rt5677 = gpio_to_rt5677(chip); 4327 struct regmap_irq_chip_data *data = rt5677->irq_data; 4328 int irq; 4329 4330 if (offset >= RT5677_GPIO1 && offset <= RT5677_GPIO3) { 4331 if ((rt5677->pdata.jd1_gpio == 1 && offset == RT5677_GPIO1) || 4332 (rt5677->pdata.jd1_gpio == 2 && 4333 offset == RT5677_GPIO2) || 4334 (rt5677->pdata.jd1_gpio == 3 && 4335 offset == RT5677_GPIO3)) { 4336 irq = RT5677_IRQ_JD1; 4337 } else { 4338 return -ENXIO; 4339 } 4340 } 4341 4342 if (offset >= RT5677_GPIO4 && offset <= RT5677_GPIO6) { 4343 if ((rt5677->pdata.jd2_gpio == 1 && offset == RT5677_GPIO4) || 4344 (rt5677->pdata.jd2_gpio == 2 && 4345 offset == RT5677_GPIO5) || 4346 (rt5677->pdata.jd2_gpio == 3 && 4347 offset == RT5677_GPIO6)) { 4348 irq = RT5677_IRQ_JD2; 4349 } else if ((rt5677->pdata.jd3_gpio == 1 && 4350 offset == RT5677_GPIO4) || 4351 (rt5677->pdata.jd3_gpio == 2 && 4352 offset == RT5677_GPIO5) || 4353 (rt5677->pdata.jd3_gpio == 3 && 4354 offset == RT5677_GPIO6)) { 4355 irq = RT5677_IRQ_JD3; 4356 } else { 4357 return -ENXIO; 4358 } 4359 } 4360 4361 return regmap_irq_get_virq(data, irq); 4362 } 4363 4364 static struct gpio_chip rt5677_template_chip = { 4365 .label = "rt5677", 4366 .owner = THIS_MODULE, 4367 .direction_output = rt5677_gpio_direction_out, 4368 .set = rt5677_gpio_set, 4369 .direction_input = rt5677_gpio_direction_in, 4370 .get = rt5677_gpio_get, 4371 .to_irq = rt5677_to_irq, 4372 .can_sleep = 1, 4373 }; 4374 4375 static void rt5677_init_gpio(struct i2c_client *i2c) 4376 { 4377 struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c); 4378 int ret; 4379 4380 rt5677->gpio_chip = rt5677_template_chip; 4381 rt5677->gpio_chip.ngpio = RT5677_GPIO_NUM; 4382 rt5677->gpio_chip.dev = &i2c->dev; 4383 rt5677->gpio_chip.base = -1; 4384 4385 ret = gpiochip_add(&rt5677->gpio_chip); 4386 if (ret != 0) 4387 dev_err(&i2c->dev, "Failed to add GPIOs: %d\n", ret); 4388 } 4389 4390 static void rt5677_free_gpio(struct i2c_client *i2c) 4391 { 4392 struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c); 4393 4394 gpiochip_remove(&rt5677->gpio_chip); 4395 } 4396 #else 4397 static void rt5677_gpio_config(struct rt5677_priv *rt5677, unsigned offset, 4398 int value) 4399 { 4400 } 4401 4402 static void rt5677_init_gpio(struct i2c_client *i2c) 4403 { 4404 } 4405 4406 static void rt5677_free_gpio(struct i2c_client *i2c) 4407 { 4408 } 4409 #endif 4410 4411 static int rt5677_probe(struct snd_soc_codec *codec) 4412 { 4413 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec); 4414 int i; 4415 4416 rt5677->codec = codec; 4417 4418 if (rt5677->pdata.dmic2_clk_pin == RT5677_DMIC_CLK2) { 4419 snd_soc_dapm_add_routes(&codec->dapm, 4420 rt5677_dmic2_clk_2, 4421 ARRAY_SIZE(rt5677_dmic2_clk_2)); 4422 } else { /*use dmic1 clock by default*/ 4423 snd_soc_dapm_add_routes(&codec->dapm, 4424 rt5677_dmic2_clk_1, 4425 ARRAY_SIZE(rt5677_dmic2_clk_1)); 4426 } 4427 4428 rt5677_set_bias_level(codec, SND_SOC_BIAS_OFF); 4429 4430 regmap_write(rt5677->regmap, RT5677_DIG_MISC, 0x0020); 4431 regmap_write(rt5677->regmap, RT5677_PWR_DSP2, 0x0c00); 4432 4433 for (i = 0; i < RT5677_GPIO_NUM; i++) 4434 rt5677_gpio_config(rt5677, i, rt5677->pdata.gpio_config[i]); 4435 4436 if (rt5677->irq_data) { 4437 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL1, 0x8000, 4438 0x8000); 4439 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x0018, 4440 0x0008); 4441 4442 if (rt5677->pdata.jd1_gpio) 4443 regmap_update_bits(rt5677->regmap, RT5677_JD_CTRL1, 4444 RT5677_SEL_GPIO_JD1_MASK, 4445 rt5677->pdata.jd1_gpio << 4446 RT5677_SEL_GPIO_JD1_SFT); 4447 4448 if (rt5677->pdata.jd2_gpio) 4449 regmap_update_bits(rt5677->regmap, RT5677_JD_CTRL1, 4450 RT5677_SEL_GPIO_JD2_MASK, 4451 rt5677->pdata.jd2_gpio << 4452 RT5677_SEL_GPIO_JD2_SFT); 4453 4454 if (rt5677->pdata.jd3_gpio) 4455 regmap_update_bits(rt5677->regmap, RT5677_JD_CTRL1, 4456 RT5677_SEL_GPIO_JD3_MASK, 4457 rt5677->pdata.jd3_gpio << 4458 RT5677_SEL_GPIO_JD3_SFT); 4459 } 4460 4461 mutex_init(&rt5677->dsp_cmd_lock); 4462 mutex_init(&rt5677->dsp_pri_lock); 4463 4464 return 0; 4465 } 4466 4467 static int rt5677_remove(struct snd_soc_codec *codec) 4468 { 4469 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec); 4470 4471 regmap_write(rt5677->regmap, RT5677_RESET, 0x10ec); 4472 if (gpio_is_valid(rt5677->pow_ldo2)) 4473 gpio_set_value_cansleep(rt5677->pow_ldo2, 0); 4474 4475 return 0; 4476 } 4477 4478 #ifdef CONFIG_PM 4479 static int rt5677_suspend(struct snd_soc_codec *codec) 4480 { 4481 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec); 4482 4483 if (!rt5677->dsp_vad_en) { 4484 regcache_cache_only(rt5677->regmap, true); 4485 regcache_mark_dirty(rt5677->regmap); 4486 } 4487 4488 if (gpio_is_valid(rt5677->pow_ldo2)) 4489 gpio_set_value_cansleep(rt5677->pow_ldo2, 0); 4490 4491 return 0; 4492 } 4493 4494 static int rt5677_resume(struct snd_soc_codec *codec) 4495 { 4496 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec); 4497 4498 if (gpio_is_valid(rt5677->pow_ldo2)) { 4499 gpio_set_value_cansleep(rt5677->pow_ldo2, 1); 4500 msleep(10); 4501 } 4502 4503 if (!rt5677->dsp_vad_en) { 4504 regcache_cache_only(rt5677->regmap, false); 4505 regcache_sync(rt5677->regmap); 4506 } 4507 4508 return 0; 4509 } 4510 #else 4511 #define rt5677_suspend NULL 4512 #define rt5677_resume NULL 4513 #endif 4514 4515 static int rt5677_read(void *context, unsigned int reg, unsigned int *val) 4516 { 4517 struct i2c_client *client = context; 4518 struct rt5677_priv *rt5677 = i2c_get_clientdata(client); 4519 4520 if (rt5677->is_dsp_mode) { 4521 if (reg > 0xff) { 4522 mutex_lock(&rt5677->dsp_pri_lock); 4523 rt5677_dsp_mode_i2c_write(rt5677, RT5677_PRIV_INDEX, 4524 reg & 0xff); 4525 rt5677_dsp_mode_i2c_read(rt5677, RT5677_PRIV_DATA, val); 4526 mutex_unlock(&rt5677->dsp_pri_lock); 4527 } else { 4528 rt5677_dsp_mode_i2c_read(rt5677, reg, val); 4529 } 4530 } else { 4531 regmap_read(rt5677->regmap_physical, reg, val); 4532 } 4533 4534 return 0; 4535 } 4536 4537 static int rt5677_write(void *context, unsigned int reg, unsigned int val) 4538 { 4539 struct i2c_client *client = context; 4540 struct rt5677_priv *rt5677 = i2c_get_clientdata(client); 4541 4542 if (rt5677->is_dsp_mode) { 4543 if (reg > 0xff) { 4544 mutex_lock(&rt5677->dsp_pri_lock); 4545 rt5677_dsp_mode_i2c_write(rt5677, RT5677_PRIV_INDEX, 4546 reg & 0xff); 4547 rt5677_dsp_mode_i2c_write(rt5677, RT5677_PRIV_DATA, 4548 val); 4549 mutex_unlock(&rt5677->dsp_pri_lock); 4550 } else { 4551 rt5677_dsp_mode_i2c_write(rt5677, reg, val); 4552 } 4553 } else { 4554 regmap_write(rt5677->regmap_physical, reg, val); 4555 } 4556 4557 return 0; 4558 } 4559 4560 #define RT5677_STEREO_RATES SNDRV_PCM_RATE_8000_96000 4561 #define RT5677_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ 4562 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8) 4563 4564 static struct snd_soc_dai_ops rt5677_aif_dai_ops = { 4565 .hw_params = rt5677_hw_params, 4566 .set_fmt = rt5677_set_dai_fmt, 4567 .set_sysclk = rt5677_set_dai_sysclk, 4568 .set_pll = rt5677_set_dai_pll, 4569 .set_tdm_slot = rt5677_set_tdm_slot, 4570 }; 4571 4572 static struct snd_soc_dai_driver rt5677_dai[] = { 4573 { 4574 .name = "rt5677-aif1", 4575 .id = RT5677_AIF1, 4576 .playback = { 4577 .stream_name = "AIF1 Playback", 4578 .channels_min = 1, 4579 .channels_max = 2, 4580 .rates = RT5677_STEREO_RATES, 4581 .formats = RT5677_FORMATS, 4582 }, 4583 .capture = { 4584 .stream_name = "AIF1 Capture", 4585 .channels_min = 1, 4586 .channels_max = 2, 4587 .rates = RT5677_STEREO_RATES, 4588 .formats = RT5677_FORMATS, 4589 }, 4590 .ops = &rt5677_aif_dai_ops, 4591 }, 4592 { 4593 .name = "rt5677-aif2", 4594 .id = RT5677_AIF2, 4595 .playback = { 4596 .stream_name = "AIF2 Playback", 4597 .channels_min = 1, 4598 .channels_max = 2, 4599 .rates = RT5677_STEREO_RATES, 4600 .formats = RT5677_FORMATS, 4601 }, 4602 .capture = { 4603 .stream_name = "AIF2 Capture", 4604 .channels_min = 1, 4605 .channels_max = 2, 4606 .rates = RT5677_STEREO_RATES, 4607 .formats = RT5677_FORMATS, 4608 }, 4609 .ops = &rt5677_aif_dai_ops, 4610 }, 4611 { 4612 .name = "rt5677-aif3", 4613 .id = RT5677_AIF3, 4614 .playback = { 4615 .stream_name = "AIF3 Playback", 4616 .channels_min = 1, 4617 .channels_max = 2, 4618 .rates = RT5677_STEREO_RATES, 4619 .formats = RT5677_FORMATS, 4620 }, 4621 .capture = { 4622 .stream_name = "AIF3 Capture", 4623 .channels_min = 1, 4624 .channels_max = 2, 4625 .rates = RT5677_STEREO_RATES, 4626 .formats = RT5677_FORMATS, 4627 }, 4628 .ops = &rt5677_aif_dai_ops, 4629 }, 4630 { 4631 .name = "rt5677-aif4", 4632 .id = RT5677_AIF4, 4633 .playback = { 4634 .stream_name = "AIF4 Playback", 4635 .channels_min = 1, 4636 .channels_max = 2, 4637 .rates = RT5677_STEREO_RATES, 4638 .formats = RT5677_FORMATS, 4639 }, 4640 .capture = { 4641 .stream_name = "AIF4 Capture", 4642 .channels_min = 1, 4643 .channels_max = 2, 4644 .rates = RT5677_STEREO_RATES, 4645 .formats = RT5677_FORMATS, 4646 }, 4647 .ops = &rt5677_aif_dai_ops, 4648 }, 4649 { 4650 .name = "rt5677-slimbus", 4651 .id = RT5677_AIF5, 4652 .playback = { 4653 .stream_name = "SLIMBus Playback", 4654 .channels_min = 1, 4655 .channels_max = 2, 4656 .rates = RT5677_STEREO_RATES, 4657 .formats = RT5677_FORMATS, 4658 }, 4659 .capture = { 4660 .stream_name = "SLIMBus Capture", 4661 .channels_min = 1, 4662 .channels_max = 2, 4663 .rates = RT5677_STEREO_RATES, 4664 .formats = RT5677_FORMATS, 4665 }, 4666 .ops = &rt5677_aif_dai_ops, 4667 }, 4668 }; 4669 4670 static struct snd_soc_codec_driver soc_codec_dev_rt5677 = { 4671 .probe = rt5677_probe, 4672 .remove = rt5677_remove, 4673 .suspend = rt5677_suspend, 4674 .resume = rt5677_resume, 4675 .set_bias_level = rt5677_set_bias_level, 4676 .idle_bias_off = true, 4677 .controls = rt5677_snd_controls, 4678 .num_controls = ARRAY_SIZE(rt5677_snd_controls), 4679 .dapm_widgets = rt5677_dapm_widgets, 4680 .num_dapm_widgets = ARRAY_SIZE(rt5677_dapm_widgets), 4681 .dapm_routes = rt5677_dapm_routes, 4682 .num_dapm_routes = ARRAY_SIZE(rt5677_dapm_routes), 4683 }; 4684 4685 static const struct regmap_config rt5677_regmap_physical = { 4686 .name = "physical", 4687 .reg_bits = 8, 4688 .val_bits = 16, 4689 4690 .max_register = RT5677_VENDOR_ID2 + 1 + (ARRAY_SIZE(rt5677_ranges) * 4691 RT5677_PR_SPACING), 4692 .readable_reg = rt5677_readable_register, 4693 4694 .cache_type = REGCACHE_NONE, 4695 .ranges = rt5677_ranges, 4696 .num_ranges = ARRAY_SIZE(rt5677_ranges), 4697 }; 4698 4699 static const struct regmap_config rt5677_regmap = { 4700 .reg_bits = 8, 4701 .val_bits = 16, 4702 4703 .max_register = RT5677_VENDOR_ID2 + 1 + (ARRAY_SIZE(rt5677_ranges) * 4704 RT5677_PR_SPACING), 4705 4706 .volatile_reg = rt5677_volatile_register, 4707 .readable_reg = rt5677_readable_register, 4708 .reg_read = rt5677_read, 4709 .reg_write = rt5677_write, 4710 4711 .cache_type = REGCACHE_RBTREE, 4712 .reg_defaults = rt5677_reg, 4713 .num_reg_defaults = ARRAY_SIZE(rt5677_reg), 4714 .ranges = rt5677_ranges, 4715 .num_ranges = ARRAY_SIZE(rt5677_ranges), 4716 }; 4717 4718 static const struct i2c_device_id rt5677_i2c_id[] = { 4719 { "rt5677", 0 }, 4720 { } 4721 }; 4722 MODULE_DEVICE_TABLE(i2c, rt5677_i2c_id); 4723 4724 static int rt5677_parse_dt(struct rt5677_priv *rt5677, struct device_node *np) 4725 { 4726 rt5677->pdata.in1_diff = of_property_read_bool(np, 4727 "realtek,in1-differential"); 4728 rt5677->pdata.in2_diff = of_property_read_bool(np, 4729 "realtek,in2-differential"); 4730 rt5677->pdata.lout1_diff = of_property_read_bool(np, 4731 "realtek,lout1-differential"); 4732 rt5677->pdata.lout2_diff = of_property_read_bool(np, 4733 "realtek,lout2-differential"); 4734 rt5677->pdata.lout3_diff = of_property_read_bool(np, 4735 "realtek,lout3-differential"); 4736 4737 rt5677->pow_ldo2 = of_get_named_gpio(np, 4738 "realtek,pow-ldo2-gpio", 0); 4739 4740 /* 4741 * POW_LDO2 is optional (it may be statically tied on the board). 4742 * -ENOENT means that the property doesn't exist, i.e. there is no 4743 * GPIO, so is not an error. Any other error code means the property 4744 * exists, but could not be parsed. 4745 */ 4746 if (!gpio_is_valid(rt5677->pow_ldo2) && 4747 (rt5677->pow_ldo2 != -ENOENT)) 4748 return rt5677->pow_ldo2; 4749 4750 of_property_read_u8_array(np, "realtek,gpio-config", 4751 rt5677->pdata.gpio_config, RT5677_GPIO_NUM); 4752 4753 of_property_read_u32(np, "realtek,jd1-gpio", &rt5677->pdata.jd1_gpio); 4754 of_property_read_u32(np, "realtek,jd2-gpio", &rt5677->pdata.jd2_gpio); 4755 of_property_read_u32(np, "realtek,jd3-gpio", &rt5677->pdata.jd3_gpio); 4756 4757 return 0; 4758 } 4759 4760 static struct regmap_irq rt5677_irqs[] = { 4761 [RT5677_IRQ_JD1] = { 4762 .reg_offset = 0, 4763 .mask = RT5677_EN_IRQ_GPIO_JD1, 4764 }, 4765 [RT5677_IRQ_JD2] = { 4766 .reg_offset = 0, 4767 .mask = RT5677_EN_IRQ_GPIO_JD2, 4768 }, 4769 [RT5677_IRQ_JD3] = { 4770 .reg_offset = 0, 4771 .mask = RT5677_EN_IRQ_GPIO_JD3, 4772 }, 4773 }; 4774 4775 static struct regmap_irq_chip rt5677_irq_chip = { 4776 .name = "rt5677", 4777 .irqs = rt5677_irqs, 4778 .num_irqs = ARRAY_SIZE(rt5677_irqs), 4779 4780 .num_regs = 1, 4781 .status_base = RT5677_IRQ_CTRL1, 4782 .mask_base = RT5677_IRQ_CTRL1, 4783 .mask_invert = 1, 4784 }; 4785 4786 static int rt5677_init_irq(struct i2c_client *i2c) 4787 { 4788 int ret; 4789 struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c); 4790 4791 if (!rt5677->pdata.jd1_gpio && 4792 !rt5677->pdata.jd2_gpio && 4793 !rt5677->pdata.jd3_gpio) 4794 return 0; 4795 4796 if (!i2c->irq) { 4797 dev_err(&i2c->dev, "No interrupt specified\n"); 4798 return -EINVAL; 4799 } 4800 4801 ret = regmap_add_irq_chip(rt5677->regmap, i2c->irq, 4802 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING | IRQF_ONESHOT, 0, 4803 &rt5677_irq_chip, &rt5677->irq_data); 4804 4805 if (ret != 0) { 4806 dev_err(&i2c->dev, "Failed to register IRQ chip: %d\n", ret); 4807 return ret; 4808 } 4809 4810 return 0; 4811 } 4812 4813 static void rt5677_free_irq(struct i2c_client *i2c) 4814 { 4815 struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c); 4816 4817 if (rt5677->irq_data) 4818 regmap_del_irq_chip(i2c->irq, rt5677->irq_data); 4819 } 4820 4821 static int rt5677_i2c_probe(struct i2c_client *i2c, 4822 const struct i2c_device_id *id) 4823 { 4824 struct rt5677_platform_data *pdata = dev_get_platdata(&i2c->dev); 4825 struct rt5677_priv *rt5677; 4826 int ret; 4827 unsigned int val; 4828 4829 rt5677 = devm_kzalloc(&i2c->dev, sizeof(struct rt5677_priv), 4830 GFP_KERNEL); 4831 if (rt5677 == NULL) 4832 return -ENOMEM; 4833 4834 i2c_set_clientdata(i2c, rt5677); 4835 4836 if (pdata) 4837 rt5677->pdata = *pdata; 4838 4839 if (i2c->dev.of_node) { 4840 ret = rt5677_parse_dt(rt5677, i2c->dev.of_node); 4841 if (ret) { 4842 dev_err(&i2c->dev, "Failed to parse device tree: %d\n", 4843 ret); 4844 return ret; 4845 } 4846 } else { 4847 rt5677->pow_ldo2 = -EINVAL; 4848 } 4849 4850 if (gpio_is_valid(rt5677->pow_ldo2)) { 4851 ret = devm_gpio_request_one(&i2c->dev, rt5677->pow_ldo2, 4852 GPIOF_OUT_INIT_HIGH, 4853 "RT5677 POW_LDO2"); 4854 if (ret < 0) { 4855 dev_err(&i2c->dev, "Failed to request POW_LDO2 %d: %d\n", 4856 rt5677->pow_ldo2, ret); 4857 return ret; 4858 } 4859 /* Wait a while until I2C bus becomes available. The datasheet 4860 * does not specify the exact we should wait but startup 4861 * sequence mentiones at least a few milliseconds. 4862 */ 4863 msleep(10); 4864 } 4865 4866 rt5677->regmap_physical = devm_regmap_init_i2c(i2c, 4867 &rt5677_regmap_physical); 4868 if (IS_ERR(rt5677->regmap_physical)) { 4869 ret = PTR_ERR(rt5677->regmap_physical); 4870 dev_err(&i2c->dev, "Failed to allocate register map: %d\n", 4871 ret); 4872 return ret; 4873 } 4874 4875 rt5677->regmap = devm_regmap_init(&i2c->dev, NULL, i2c, &rt5677_regmap); 4876 if (IS_ERR(rt5677->regmap)) { 4877 ret = PTR_ERR(rt5677->regmap); 4878 dev_err(&i2c->dev, "Failed to allocate register map: %d\n", 4879 ret); 4880 return ret; 4881 } 4882 4883 regmap_read(rt5677->regmap, RT5677_VENDOR_ID2, &val); 4884 if (val != RT5677_DEVICE_ID) { 4885 dev_err(&i2c->dev, 4886 "Device with ID register %x is not rt5677\n", val); 4887 return -ENODEV; 4888 } 4889 4890 regmap_write(rt5677->regmap, RT5677_RESET, 0x10ec); 4891 4892 ret = regmap_register_patch(rt5677->regmap, init_list, 4893 ARRAY_SIZE(init_list)); 4894 if (ret != 0) 4895 dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret); 4896 4897 if (rt5677->pdata.in1_diff) 4898 regmap_update_bits(rt5677->regmap, RT5677_IN1, 4899 RT5677_IN_DF1, RT5677_IN_DF1); 4900 4901 if (rt5677->pdata.in2_diff) 4902 regmap_update_bits(rt5677->regmap, RT5677_IN1, 4903 RT5677_IN_DF2, RT5677_IN_DF2); 4904 4905 if (rt5677->pdata.lout1_diff) 4906 regmap_update_bits(rt5677->regmap, RT5677_LOUT1, 4907 RT5677_LOUT1_L_DF, RT5677_LOUT1_L_DF); 4908 4909 if (rt5677->pdata.lout2_diff) 4910 regmap_update_bits(rt5677->regmap, RT5677_LOUT1, 4911 RT5677_LOUT2_L_DF, RT5677_LOUT2_L_DF); 4912 4913 if (rt5677->pdata.lout3_diff) 4914 regmap_update_bits(rt5677->regmap, RT5677_LOUT1, 4915 RT5677_LOUT3_L_DF, RT5677_LOUT3_L_DF); 4916 4917 if (rt5677->pdata.dmic2_clk_pin == RT5677_DMIC_CLK2) { 4918 regmap_update_bits(rt5677->regmap, RT5677_GEN_CTRL2, 4919 RT5677_GPIO5_FUNC_MASK, 4920 RT5677_GPIO5_FUNC_DMIC); 4921 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2, 4922 RT5677_GPIO5_DIR_MASK, 4923 RT5677_GPIO5_DIR_OUT); 4924 } 4925 4926 rt5677_init_gpio(i2c); 4927 rt5677_init_irq(i2c); 4928 4929 return snd_soc_register_codec(&i2c->dev, &soc_codec_dev_rt5677, 4930 rt5677_dai, ARRAY_SIZE(rt5677_dai)); 4931 } 4932 4933 static int rt5677_i2c_remove(struct i2c_client *i2c) 4934 { 4935 snd_soc_unregister_codec(&i2c->dev); 4936 rt5677_free_irq(i2c); 4937 rt5677_free_gpio(i2c); 4938 4939 return 0; 4940 } 4941 4942 static struct i2c_driver rt5677_i2c_driver = { 4943 .driver = { 4944 .name = "rt5677", 4945 .owner = THIS_MODULE, 4946 }, 4947 .probe = rt5677_i2c_probe, 4948 .remove = rt5677_i2c_remove, 4949 .id_table = rt5677_i2c_id, 4950 }; 4951 module_i2c_driver(rt5677_i2c_driver); 4952 4953 MODULE_DESCRIPTION("ASoC RT5677 driver"); 4954 MODULE_AUTHOR("Oder Chiou <oder_chiou@realtek.com>"); 4955 MODULE_LICENSE("GPL v2"); 4956