1 /* 2 * rt5677.c -- RT5677 ALSA SoC audio codec driver 3 * 4 * Copyright 2013 Realtek Semiconductor Corp. 5 * Author: Oder Chiou <oder_chiou@realtek.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11 12 #include <linux/fs.h> 13 #include <linux/module.h> 14 #include <linux/moduleparam.h> 15 #include <linux/init.h> 16 #include <linux/delay.h> 17 #include <linux/pm.h> 18 #include <linux/of_gpio.h> 19 #include <linux/regmap.h> 20 #include <linux/i2c.h> 21 #include <linux/platform_device.h> 22 #include <linux/spi/spi.h> 23 #include <linux/firmware.h> 24 #include <linux/gpio.h> 25 #include <sound/core.h> 26 #include <sound/pcm.h> 27 #include <sound/pcm_params.h> 28 #include <sound/soc.h> 29 #include <sound/soc-dapm.h> 30 #include <sound/initval.h> 31 #include <sound/tlv.h> 32 33 #include "rl6231.h" 34 #include "rt5677.h" 35 #include "rt5677-spi.h" 36 37 #define RT5677_DEVICE_ID 0x6327 38 39 #define RT5677_PR_RANGE_BASE (0xff + 1) 40 #define RT5677_PR_SPACING 0x100 41 42 #define RT5677_PR_BASE (RT5677_PR_RANGE_BASE + (0 * RT5677_PR_SPACING)) 43 44 static const struct regmap_range_cfg rt5677_ranges[] = { 45 { 46 .name = "PR", 47 .range_min = RT5677_PR_BASE, 48 .range_max = RT5677_PR_BASE + 0xfd, 49 .selector_reg = RT5677_PRIV_INDEX, 50 .selector_mask = 0xff, 51 .selector_shift = 0x0, 52 .window_start = RT5677_PRIV_DATA, 53 .window_len = 0x1, 54 }, 55 }; 56 57 static const struct reg_default init_list[] = { 58 {RT5677_ASRC_12, 0x0018}, 59 {RT5677_PR_BASE + 0x3d, 0x364d}, 60 {RT5677_PR_BASE + 0x17, 0x4fc0}, 61 {RT5677_PR_BASE + 0x13, 0x0312}, 62 {RT5677_PR_BASE + 0x1e, 0x0000}, 63 {RT5677_PR_BASE + 0x12, 0x0eaa}, 64 {RT5677_PR_BASE + 0x14, 0x018a}, 65 }; 66 #define RT5677_INIT_REG_LEN ARRAY_SIZE(init_list) 67 68 static const struct reg_default rt5677_reg[] = { 69 {RT5677_RESET , 0x0000}, 70 {RT5677_LOUT1 , 0xa800}, 71 {RT5677_IN1 , 0x0000}, 72 {RT5677_MICBIAS , 0x0000}, 73 {RT5677_SLIMBUS_PARAM , 0x0000}, 74 {RT5677_SLIMBUS_RX , 0x0000}, 75 {RT5677_SLIMBUS_CTRL , 0x0000}, 76 {RT5677_SIDETONE_CTRL , 0x000b}, 77 {RT5677_ANA_DAC1_2_3_SRC , 0x0000}, 78 {RT5677_IF_DSP_DAC3_4_MIXER , 0x1111}, 79 {RT5677_DAC4_DIG_VOL , 0xafaf}, 80 {RT5677_DAC3_DIG_VOL , 0xafaf}, 81 {RT5677_DAC1_DIG_VOL , 0xafaf}, 82 {RT5677_DAC2_DIG_VOL , 0xafaf}, 83 {RT5677_IF_DSP_DAC2_MIXER , 0x0011}, 84 {RT5677_STO1_ADC_DIG_VOL , 0x2f2f}, 85 {RT5677_MONO_ADC_DIG_VOL , 0x2f2f}, 86 {RT5677_STO1_2_ADC_BST , 0x0000}, 87 {RT5677_STO2_ADC_DIG_VOL , 0x2f2f}, 88 {RT5677_ADC_BST_CTRL2 , 0x0000}, 89 {RT5677_STO3_4_ADC_BST , 0x0000}, 90 {RT5677_STO3_ADC_DIG_VOL , 0x2f2f}, 91 {RT5677_STO4_ADC_DIG_VOL , 0x2f2f}, 92 {RT5677_STO4_ADC_MIXER , 0xd4c0}, 93 {RT5677_STO3_ADC_MIXER , 0xd4c0}, 94 {RT5677_STO2_ADC_MIXER , 0xd4c0}, 95 {RT5677_STO1_ADC_MIXER , 0xd4c0}, 96 {RT5677_MONO_ADC_MIXER , 0xd4d1}, 97 {RT5677_ADC_IF_DSP_DAC1_MIXER , 0x8080}, 98 {RT5677_STO1_DAC_MIXER , 0xaaaa}, 99 {RT5677_MONO_DAC_MIXER , 0xaaaa}, 100 {RT5677_DD1_MIXER , 0xaaaa}, 101 {RT5677_DD2_MIXER , 0xaaaa}, 102 {RT5677_IF3_DATA , 0x0000}, 103 {RT5677_IF4_DATA , 0x0000}, 104 {RT5677_PDM_OUT_CTRL , 0x8888}, 105 {RT5677_PDM_DATA_CTRL1 , 0x0000}, 106 {RT5677_PDM_DATA_CTRL2 , 0x0000}, 107 {RT5677_PDM1_DATA_CTRL2 , 0x0000}, 108 {RT5677_PDM1_DATA_CTRL3 , 0x0000}, 109 {RT5677_PDM1_DATA_CTRL4 , 0x0000}, 110 {RT5677_PDM2_DATA_CTRL2 , 0x0000}, 111 {RT5677_PDM2_DATA_CTRL3 , 0x0000}, 112 {RT5677_PDM2_DATA_CTRL4 , 0x0000}, 113 {RT5677_TDM1_CTRL1 , 0x0300}, 114 {RT5677_TDM1_CTRL2 , 0x0000}, 115 {RT5677_TDM1_CTRL3 , 0x4000}, 116 {RT5677_TDM1_CTRL4 , 0x0123}, 117 {RT5677_TDM1_CTRL5 , 0x4567}, 118 {RT5677_TDM2_CTRL1 , 0x0300}, 119 {RT5677_TDM2_CTRL2 , 0x0000}, 120 {RT5677_TDM2_CTRL3 , 0x4000}, 121 {RT5677_TDM2_CTRL4 , 0x0123}, 122 {RT5677_TDM2_CTRL5 , 0x4567}, 123 {RT5677_I2C_MASTER_CTRL1 , 0x0001}, 124 {RT5677_I2C_MASTER_CTRL2 , 0x0000}, 125 {RT5677_I2C_MASTER_CTRL3 , 0x0000}, 126 {RT5677_I2C_MASTER_CTRL4 , 0x0000}, 127 {RT5677_I2C_MASTER_CTRL5 , 0x0000}, 128 {RT5677_I2C_MASTER_CTRL6 , 0x0000}, 129 {RT5677_I2C_MASTER_CTRL7 , 0x0000}, 130 {RT5677_I2C_MASTER_CTRL8 , 0x0000}, 131 {RT5677_DMIC_CTRL1 , 0x1505}, 132 {RT5677_DMIC_CTRL2 , 0x0055}, 133 {RT5677_HAP_GENE_CTRL1 , 0x0111}, 134 {RT5677_HAP_GENE_CTRL2 , 0x0064}, 135 {RT5677_HAP_GENE_CTRL3 , 0xef0e}, 136 {RT5677_HAP_GENE_CTRL4 , 0xf0f0}, 137 {RT5677_HAP_GENE_CTRL5 , 0xef0e}, 138 {RT5677_HAP_GENE_CTRL6 , 0xf0f0}, 139 {RT5677_HAP_GENE_CTRL7 , 0xef0e}, 140 {RT5677_HAP_GENE_CTRL8 , 0xf0f0}, 141 {RT5677_HAP_GENE_CTRL9 , 0xf000}, 142 {RT5677_HAP_GENE_CTRL10 , 0x0000}, 143 {RT5677_PWR_DIG1 , 0x0000}, 144 {RT5677_PWR_DIG2 , 0x0000}, 145 {RT5677_PWR_ANLG1 , 0x0055}, 146 {RT5677_PWR_ANLG2 , 0x0000}, 147 {RT5677_PWR_DSP1 , 0x0001}, 148 {RT5677_PWR_DSP_ST , 0x0000}, 149 {RT5677_PWR_DSP2 , 0x0000}, 150 {RT5677_ADC_DAC_HPF_CTRL1 , 0x0e00}, 151 {RT5677_PRIV_INDEX , 0x0000}, 152 {RT5677_PRIV_DATA , 0x0000}, 153 {RT5677_I2S4_SDP , 0x8000}, 154 {RT5677_I2S1_SDP , 0x8000}, 155 {RT5677_I2S2_SDP , 0x8000}, 156 {RT5677_I2S3_SDP , 0x8000}, 157 {RT5677_CLK_TREE_CTRL1 , 0x1111}, 158 {RT5677_CLK_TREE_CTRL2 , 0x1111}, 159 {RT5677_CLK_TREE_CTRL3 , 0x0000}, 160 {RT5677_PLL1_CTRL1 , 0x0000}, 161 {RT5677_PLL1_CTRL2 , 0x0000}, 162 {RT5677_PLL2_CTRL1 , 0x0c60}, 163 {RT5677_PLL2_CTRL2 , 0x2000}, 164 {RT5677_GLB_CLK1 , 0x0000}, 165 {RT5677_GLB_CLK2 , 0x0000}, 166 {RT5677_ASRC_1 , 0x0000}, 167 {RT5677_ASRC_2 , 0x0000}, 168 {RT5677_ASRC_3 , 0x0000}, 169 {RT5677_ASRC_4 , 0x0000}, 170 {RT5677_ASRC_5 , 0x0000}, 171 {RT5677_ASRC_6 , 0x0000}, 172 {RT5677_ASRC_7 , 0x0000}, 173 {RT5677_ASRC_8 , 0x0000}, 174 {RT5677_ASRC_9 , 0x0000}, 175 {RT5677_ASRC_10 , 0x0000}, 176 {RT5677_ASRC_11 , 0x0000}, 177 {RT5677_ASRC_12 , 0x0018}, 178 {RT5677_ASRC_13 , 0x0000}, 179 {RT5677_ASRC_14 , 0x0000}, 180 {RT5677_ASRC_15 , 0x0000}, 181 {RT5677_ASRC_16 , 0x0000}, 182 {RT5677_ASRC_17 , 0x0000}, 183 {RT5677_ASRC_18 , 0x0000}, 184 {RT5677_ASRC_19 , 0x0000}, 185 {RT5677_ASRC_20 , 0x0000}, 186 {RT5677_ASRC_21 , 0x000c}, 187 {RT5677_ASRC_22 , 0x0000}, 188 {RT5677_ASRC_23 , 0x0000}, 189 {RT5677_VAD_CTRL1 , 0x2184}, 190 {RT5677_VAD_CTRL2 , 0x010a}, 191 {RT5677_VAD_CTRL3 , 0x0aea}, 192 {RT5677_VAD_CTRL4 , 0x000c}, 193 {RT5677_VAD_CTRL5 , 0x0000}, 194 {RT5677_DSP_INB_CTRL1 , 0x0000}, 195 {RT5677_DSP_INB_CTRL2 , 0x0000}, 196 {RT5677_DSP_IN_OUTB_CTRL , 0x0000}, 197 {RT5677_DSP_OUTB0_1_DIG_VOL , 0x2f2f}, 198 {RT5677_DSP_OUTB2_3_DIG_VOL , 0x2f2f}, 199 {RT5677_DSP_OUTB4_5_DIG_VOL , 0x2f2f}, 200 {RT5677_DSP_OUTB6_7_DIG_VOL , 0x2f2f}, 201 {RT5677_ADC_EQ_CTRL1 , 0x6000}, 202 {RT5677_ADC_EQ_CTRL2 , 0x0000}, 203 {RT5677_EQ_CTRL1 , 0xc000}, 204 {RT5677_EQ_CTRL2 , 0x0000}, 205 {RT5677_EQ_CTRL3 , 0x0000}, 206 {RT5677_SOFT_VOL_ZERO_CROSS1 , 0x0009}, 207 {RT5677_JD_CTRL1 , 0x0000}, 208 {RT5677_JD_CTRL2 , 0x0000}, 209 {RT5677_JD_CTRL3 , 0x0000}, 210 {RT5677_IRQ_CTRL1 , 0x0000}, 211 {RT5677_IRQ_CTRL2 , 0x0000}, 212 {RT5677_GPIO_ST , 0x0000}, 213 {RT5677_GPIO_CTRL1 , 0x0000}, 214 {RT5677_GPIO_CTRL2 , 0x0000}, 215 {RT5677_GPIO_CTRL3 , 0x0000}, 216 {RT5677_STO1_ADC_HI_FILTER1 , 0xb320}, 217 {RT5677_STO1_ADC_HI_FILTER2 , 0x0000}, 218 {RT5677_MONO_ADC_HI_FILTER1 , 0xb300}, 219 {RT5677_MONO_ADC_HI_FILTER2 , 0x0000}, 220 {RT5677_STO2_ADC_HI_FILTER1 , 0xb300}, 221 {RT5677_STO2_ADC_HI_FILTER2 , 0x0000}, 222 {RT5677_STO3_ADC_HI_FILTER1 , 0xb300}, 223 {RT5677_STO3_ADC_HI_FILTER2 , 0x0000}, 224 {RT5677_STO4_ADC_HI_FILTER1 , 0xb300}, 225 {RT5677_STO4_ADC_HI_FILTER2 , 0x0000}, 226 {RT5677_MB_DRC_CTRL1 , 0x0f20}, 227 {RT5677_DRC1_CTRL1 , 0x001f}, 228 {RT5677_DRC1_CTRL2 , 0x020c}, 229 {RT5677_DRC1_CTRL3 , 0x1f00}, 230 {RT5677_DRC1_CTRL4 , 0x0000}, 231 {RT5677_DRC1_CTRL5 , 0x0000}, 232 {RT5677_DRC1_CTRL6 , 0x0029}, 233 {RT5677_DRC2_CTRL1 , 0x001f}, 234 {RT5677_DRC2_CTRL2 , 0x020c}, 235 {RT5677_DRC2_CTRL3 , 0x1f00}, 236 {RT5677_DRC2_CTRL4 , 0x0000}, 237 {RT5677_DRC2_CTRL5 , 0x0000}, 238 {RT5677_DRC2_CTRL6 , 0x0029}, 239 {RT5677_DRC1_HL_CTRL1 , 0x8000}, 240 {RT5677_DRC1_HL_CTRL2 , 0x0200}, 241 {RT5677_DRC2_HL_CTRL1 , 0x8000}, 242 {RT5677_DRC2_HL_CTRL2 , 0x0200}, 243 {RT5677_DSP_INB1_SRC_CTRL1 , 0x5800}, 244 {RT5677_DSP_INB1_SRC_CTRL2 , 0x0000}, 245 {RT5677_DSP_INB1_SRC_CTRL3 , 0x0000}, 246 {RT5677_DSP_INB1_SRC_CTRL4 , 0x0800}, 247 {RT5677_DSP_INB2_SRC_CTRL1 , 0x5800}, 248 {RT5677_DSP_INB2_SRC_CTRL2 , 0x0000}, 249 {RT5677_DSP_INB2_SRC_CTRL3 , 0x0000}, 250 {RT5677_DSP_INB2_SRC_CTRL4 , 0x0800}, 251 {RT5677_DSP_INB3_SRC_CTRL1 , 0x5800}, 252 {RT5677_DSP_INB3_SRC_CTRL2 , 0x0000}, 253 {RT5677_DSP_INB3_SRC_CTRL3 , 0x0000}, 254 {RT5677_DSP_INB3_SRC_CTRL4 , 0x0800}, 255 {RT5677_DSP_OUTB1_SRC_CTRL1 , 0x5800}, 256 {RT5677_DSP_OUTB1_SRC_CTRL2 , 0x0000}, 257 {RT5677_DSP_OUTB1_SRC_CTRL3 , 0x0000}, 258 {RT5677_DSP_OUTB1_SRC_CTRL4 , 0x0800}, 259 {RT5677_DSP_OUTB2_SRC_CTRL1 , 0x5800}, 260 {RT5677_DSP_OUTB2_SRC_CTRL2 , 0x0000}, 261 {RT5677_DSP_OUTB2_SRC_CTRL3 , 0x0000}, 262 {RT5677_DSP_OUTB2_SRC_CTRL4 , 0x0800}, 263 {RT5677_DSP_OUTB_0123_MIXER_CTRL, 0xfefe}, 264 {RT5677_DSP_OUTB_45_MIXER_CTRL , 0xfefe}, 265 {RT5677_DSP_OUTB_67_MIXER_CTRL , 0xfefe}, 266 {RT5677_DIG_MISC , 0x0000}, 267 {RT5677_GEN_CTRL1 , 0x0000}, 268 {RT5677_GEN_CTRL2 , 0x0000}, 269 {RT5677_VENDOR_ID , 0x0000}, 270 {RT5677_VENDOR_ID1 , 0x10ec}, 271 {RT5677_VENDOR_ID2 , 0x6327}, 272 }; 273 274 static bool rt5677_volatile_register(struct device *dev, unsigned int reg) 275 { 276 int i; 277 278 for (i = 0; i < ARRAY_SIZE(rt5677_ranges); i++) { 279 if (reg >= rt5677_ranges[i].range_min && 280 reg <= rt5677_ranges[i].range_max) { 281 return true; 282 } 283 } 284 285 switch (reg) { 286 case RT5677_RESET: 287 case RT5677_SLIMBUS_PARAM: 288 case RT5677_PDM_DATA_CTRL1: 289 case RT5677_PDM_DATA_CTRL2: 290 case RT5677_PDM1_DATA_CTRL4: 291 case RT5677_PDM2_DATA_CTRL4: 292 case RT5677_I2C_MASTER_CTRL1: 293 case RT5677_I2C_MASTER_CTRL7: 294 case RT5677_I2C_MASTER_CTRL8: 295 case RT5677_HAP_GENE_CTRL2: 296 case RT5677_PWR_DSP_ST: 297 case RT5677_PRIV_DATA: 298 case RT5677_PLL1_CTRL2: 299 case RT5677_PLL2_CTRL2: 300 case RT5677_ASRC_22: 301 case RT5677_ASRC_23: 302 case RT5677_VAD_CTRL5: 303 case RT5677_ADC_EQ_CTRL1: 304 case RT5677_EQ_CTRL1: 305 case RT5677_IRQ_CTRL1: 306 case RT5677_IRQ_CTRL2: 307 case RT5677_GPIO_ST: 308 case RT5677_DSP_INB1_SRC_CTRL4: 309 case RT5677_DSP_INB2_SRC_CTRL4: 310 case RT5677_DSP_INB3_SRC_CTRL4: 311 case RT5677_DSP_OUTB1_SRC_CTRL4: 312 case RT5677_DSP_OUTB2_SRC_CTRL4: 313 case RT5677_VENDOR_ID: 314 case RT5677_VENDOR_ID1: 315 case RT5677_VENDOR_ID2: 316 return true; 317 default: 318 return false; 319 } 320 } 321 322 static bool rt5677_readable_register(struct device *dev, unsigned int reg) 323 { 324 int i; 325 326 for (i = 0; i < ARRAY_SIZE(rt5677_ranges); i++) { 327 if (reg >= rt5677_ranges[i].range_min && 328 reg <= rt5677_ranges[i].range_max) { 329 return true; 330 } 331 } 332 333 switch (reg) { 334 case RT5677_RESET: 335 case RT5677_LOUT1: 336 case RT5677_IN1: 337 case RT5677_MICBIAS: 338 case RT5677_SLIMBUS_PARAM: 339 case RT5677_SLIMBUS_RX: 340 case RT5677_SLIMBUS_CTRL: 341 case RT5677_SIDETONE_CTRL: 342 case RT5677_ANA_DAC1_2_3_SRC: 343 case RT5677_IF_DSP_DAC3_4_MIXER: 344 case RT5677_DAC4_DIG_VOL: 345 case RT5677_DAC3_DIG_VOL: 346 case RT5677_DAC1_DIG_VOL: 347 case RT5677_DAC2_DIG_VOL: 348 case RT5677_IF_DSP_DAC2_MIXER: 349 case RT5677_STO1_ADC_DIG_VOL: 350 case RT5677_MONO_ADC_DIG_VOL: 351 case RT5677_STO1_2_ADC_BST: 352 case RT5677_STO2_ADC_DIG_VOL: 353 case RT5677_ADC_BST_CTRL2: 354 case RT5677_STO3_4_ADC_BST: 355 case RT5677_STO3_ADC_DIG_VOL: 356 case RT5677_STO4_ADC_DIG_VOL: 357 case RT5677_STO4_ADC_MIXER: 358 case RT5677_STO3_ADC_MIXER: 359 case RT5677_STO2_ADC_MIXER: 360 case RT5677_STO1_ADC_MIXER: 361 case RT5677_MONO_ADC_MIXER: 362 case RT5677_ADC_IF_DSP_DAC1_MIXER: 363 case RT5677_STO1_DAC_MIXER: 364 case RT5677_MONO_DAC_MIXER: 365 case RT5677_DD1_MIXER: 366 case RT5677_DD2_MIXER: 367 case RT5677_IF3_DATA: 368 case RT5677_IF4_DATA: 369 case RT5677_PDM_OUT_CTRL: 370 case RT5677_PDM_DATA_CTRL1: 371 case RT5677_PDM_DATA_CTRL2: 372 case RT5677_PDM1_DATA_CTRL2: 373 case RT5677_PDM1_DATA_CTRL3: 374 case RT5677_PDM1_DATA_CTRL4: 375 case RT5677_PDM2_DATA_CTRL2: 376 case RT5677_PDM2_DATA_CTRL3: 377 case RT5677_PDM2_DATA_CTRL4: 378 case RT5677_TDM1_CTRL1: 379 case RT5677_TDM1_CTRL2: 380 case RT5677_TDM1_CTRL3: 381 case RT5677_TDM1_CTRL4: 382 case RT5677_TDM1_CTRL5: 383 case RT5677_TDM2_CTRL1: 384 case RT5677_TDM2_CTRL2: 385 case RT5677_TDM2_CTRL3: 386 case RT5677_TDM2_CTRL4: 387 case RT5677_TDM2_CTRL5: 388 case RT5677_I2C_MASTER_CTRL1: 389 case RT5677_I2C_MASTER_CTRL2: 390 case RT5677_I2C_MASTER_CTRL3: 391 case RT5677_I2C_MASTER_CTRL4: 392 case RT5677_I2C_MASTER_CTRL5: 393 case RT5677_I2C_MASTER_CTRL6: 394 case RT5677_I2C_MASTER_CTRL7: 395 case RT5677_I2C_MASTER_CTRL8: 396 case RT5677_DMIC_CTRL1: 397 case RT5677_DMIC_CTRL2: 398 case RT5677_HAP_GENE_CTRL1: 399 case RT5677_HAP_GENE_CTRL2: 400 case RT5677_HAP_GENE_CTRL3: 401 case RT5677_HAP_GENE_CTRL4: 402 case RT5677_HAP_GENE_CTRL5: 403 case RT5677_HAP_GENE_CTRL6: 404 case RT5677_HAP_GENE_CTRL7: 405 case RT5677_HAP_GENE_CTRL8: 406 case RT5677_HAP_GENE_CTRL9: 407 case RT5677_HAP_GENE_CTRL10: 408 case RT5677_PWR_DIG1: 409 case RT5677_PWR_DIG2: 410 case RT5677_PWR_ANLG1: 411 case RT5677_PWR_ANLG2: 412 case RT5677_PWR_DSP1: 413 case RT5677_PWR_DSP_ST: 414 case RT5677_PWR_DSP2: 415 case RT5677_ADC_DAC_HPF_CTRL1: 416 case RT5677_PRIV_INDEX: 417 case RT5677_PRIV_DATA: 418 case RT5677_I2S4_SDP: 419 case RT5677_I2S1_SDP: 420 case RT5677_I2S2_SDP: 421 case RT5677_I2S3_SDP: 422 case RT5677_CLK_TREE_CTRL1: 423 case RT5677_CLK_TREE_CTRL2: 424 case RT5677_CLK_TREE_CTRL3: 425 case RT5677_PLL1_CTRL1: 426 case RT5677_PLL1_CTRL2: 427 case RT5677_PLL2_CTRL1: 428 case RT5677_PLL2_CTRL2: 429 case RT5677_GLB_CLK1: 430 case RT5677_GLB_CLK2: 431 case RT5677_ASRC_1: 432 case RT5677_ASRC_2: 433 case RT5677_ASRC_3: 434 case RT5677_ASRC_4: 435 case RT5677_ASRC_5: 436 case RT5677_ASRC_6: 437 case RT5677_ASRC_7: 438 case RT5677_ASRC_8: 439 case RT5677_ASRC_9: 440 case RT5677_ASRC_10: 441 case RT5677_ASRC_11: 442 case RT5677_ASRC_12: 443 case RT5677_ASRC_13: 444 case RT5677_ASRC_14: 445 case RT5677_ASRC_15: 446 case RT5677_ASRC_16: 447 case RT5677_ASRC_17: 448 case RT5677_ASRC_18: 449 case RT5677_ASRC_19: 450 case RT5677_ASRC_20: 451 case RT5677_ASRC_21: 452 case RT5677_ASRC_22: 453 case RT5677_ASRC_23: 454 case RT5677_VAD_CTRL1: 455 case RT5677_VAD_CTRL2: 456 case RT5677_VAD_CTRL3: 457 case RT5677_VAD_CTRL4: 458 case RT5677_VAD_CTRL5: 459 case RT5677_DSP_INB_CTRL1: 460 case RT5677_DSP_INB_CTRL2: 461 case RT5677_DSP_IN_OUTB_CTRL: 462 case RT5677_DSP_OUTB0_1_DIG_VOL: 463 case RT5677_DSP_OUTB2_3_DIG_VOL: 464 case RT5677_DSP_OUTB4_5_DIG_VOL: 465 case RT5677_DSP_OUTB6_7_DIG_VOL: 466 case RT5677_ADC_EQ_CTRL1: 467 case RT5677_ADC_EQ_CTRL2: 468 case RT5677_EQ_CTRL1: 469 case RT5677_EQ_CTRL2: 470 case RT5677_EQ_CTRL3: 471 case RT5677_SOFT_VOL_ZERO_CROSS1: 472 case RT5677_JD_CTRL1: 473 case RT5677_JD_CTRL2: 474 case RT5677_JD_CTRL3: 475 case RT5677_IRQ_CTRL1: 476 case RT5677_IRQ_CTRL2: 477 case RT5677_GPIO_ST: 478 case RT5677_GPIO_CTRL1: 479 case RT5677_GPIO_CTRL2: 480 case RT5677_GPIO_CTRL3: 481 case RT5677_STO1_ADC_HI_FILTER1: 482 case RT5677_STO1_ADC_HI_FILTER2: 483 case RT5677_MONO_ADC_HI_FILTER1: 484 case RT5677_MONO_ADC_HI_FILTER2: 485 case RT5677_STO2_ADC_HI_FILTER1: 486 case RT5677_STO2_ADC_HI_FILTER2: 487 case RT5677_STO3_ADC_HI_FILTER1: 488 case RT5677_STO3_ADC_HI_FILTER2: 489 case RT5677_STO4_ADC_HI_FILTER1: 490 case RT5677_STO4_ADC_HI_FILTER2: 491 case RT5677_MB_DRC_CTRL1: 492 case RT5677_DRC1_CTRL1: 493 case RT5677_DRC1_CTRL2: 494 case RT5677_DRC1_CTRL3: 495 case RT5677_DRC1_CTRL4: 496 case RT5677_DRC1_CTRL5: 497 case RT5677_DRC1_CTRL6: 498 case RT5677_DRC2_CTRL1: 499 case RT5677_DRC2_CTRL2: 500 case RT5677_DRC2_CTRL3: 501 case RT5677_DRC2_CTRL4: 502 case RT5677_DRC2_CTRL5: 503 case RT5677_DRC2_CTRL6: 504 case RT5677_DRC1_HL_CTRL1: 505 case RT5677_DRC1_HL_CTRL2: 506 case RT5677_DRC2_HL_CTRL1: 507 case RT5677_DRC2_HL_CTRL2: 508 case RT5677_DSP_INB1_SRC_CTRL1: 509 case RT5677_DSP_INB1_SRC_CTRL2: 510 case RT5677_DSP_INB1_SRC_CTRL3: 511 case RT5677_DSP_INB1_SRC_CTRL4: 512 case RT5677_DSP_INB2_SRC_CTRL1: 513 case RT5677_DSP_INB2_SRC_CTRL2: 514 case RT5677_DSP_INB2_SRC_CTRL3: 515 case RT5677_DSP_INB2_SRC_CTRL4: 516 case RT5677_DSP_INB3_SRC_CTRL1: 517 case RT5677_DSP_INB3_SRC_CTRL2: 518 case RT5677_DSP_INB3_SRC_CTRL3: 519 case RT5677_DSP_INB3_SRC_CTRL4: 520 case RT5677_DSP_OUTB1_SRC_CTRL1: 521 case RT5677_DSP_OUTB1_SRC_CTRL2: 522 case RT5677_DSP_OUTB1_SRC_CTRL3: 523 case RT5677_DSP_OUTB1_SRC_CTRL4: 524 case RT5677_DSP_OUTB2_SRC_CTRL1: 525 case RT5677_DSP_OUTB2_SRC_CTRL2: 526 case RT5677_DSP_OUTB2_SRC_CTRL3: 527 case RT5677_DSP_OUTB2_SRC_CTRL4: 528 case RT5677_DSP_OUTB_0123_MIXER_CTRL: 529 case RT5677_DSP_OUTB_45_MIXER_CTRL: 530 case RT5677_DSP_OUTB_67_MIXER_CTRL: 531 case RT5677_DIG_MISC: 532 case RT5677_GEN_CTRL1: 533 case RT5677_GEN_CTRL2: 534 case RT5677_VENDOR_ID: 535 case RT5677_VENDOR_ID1: 536 case RT5677_VENDOR_ID2: 537 return true; 538 default: 539 return false; 540 } 541 } 542 543 /** 544 * rt5677_dsp_mode_i2c_write_addr - Write value to address on DSP mode. 545 * @rt5677: Private Data. 546 * @addr: Address index. 547 * @value: Address data. 548 * 549 * 550 * Returns 0 for success or negative error code. 551 */ 552 static int rt5677_dsp_mode_i2c_write_addr(struct rt5677_priv *rt5677, 553 unsigned int addr, unsigned int value, unsigned int opcode) 554 { 555 struct snd_soc_codec *codec = rt5677->codec; 556 int ret; 557 558 mutex_lock(&rt5677->dsp_cmd_lock); 559 560 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_MSB, 561 addr >> 16); 562 if (ret < 0) { 563 dev_err(codec->dev, "Failed to set addr msb value: %d\n", ret); 564 goto err; 565 } 566 567 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_LSB, 568 addr & 0xffff); 569 if (ret < 0) { 570 dev_err(codec->dev, "Failed to set addr lsb value: %d\n", ret); 571 goto err; 572 } 573 574 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_MSB, 575 value >> 16); 576 if (ret < 0) { 577 dev_err(codec->dev, "Failed to set data msb value: %d\n", ret); 578 goto err; 579 } 580 581 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_LSB, 582 value & 0xffff); 583 if (ret < 0) { 584 dev_err(codec->dev, "Failed to set data lsb value: %d\n", ret); 585 goto err; 586 } 587 588 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_OP_CODE, 589 opcode); 590 if (ret < 0) { 591 dev_err(codec->dev, "Failed to set op code value: %d\n", ret); 592 goto err; 593 } 594 595 err: 596 mutex_unlock(&rt5677->dsp_cmd_lock); 597 598 return ret; 599 } 600 601 /** 602 * rt5677_dsp_mode_i2c_read_addr - Read value from address on DSP mode. 603 * rt5677: Private Data. 604 * @addr: Address index. 605 * @value: Address data. 606 * 607 * 608 * Returns 0 for success or negative error code. 609 */ 610 static int rt5677_dsp_mode_i2c_read_addr( 611 struct rt5677_priv *rt5677, unsigned int addr, unsigned int *value) 612 { 613 struct snd_soc_codec *codec = rt5677->codec; 614 int ret; 615 unsigned int msb, lsb; 616 617 mutex_lock(&rt5677->dsp_cmd_lock); 618 619 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_MSB, 620 addr >> 16); 621 if (ret < 0) { 622 dev_err(codec->dev, "Failed to set addr msb value: %d\n", ret); 623 goto err; 624 } 625 626 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_LSB, 627 addr & 0xffff); 628 if (ret < 0) { 629 dev_err(codec->dev, "Failed to set addr lsb value: %d\n", ret); 630 goto err; 631 } 632 633 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_OP_CODE, 634 0x0002); 635 if (ret < 0) { 636 dev_err(codec->dev, "Failed to set op code value: %d\n", ret); 637 goto err; 638 } 639 640 regmap_read(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_MSB, &msb); 641 regmap_read(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_LSB, &lsb); 642 *value = (msb << 16) | lsb; 643 644 err: 645 mutex_unlock(&rt5677->dsp_cmd_lock); 646 647 return ret; 648 } 649 650 /** 651 * rt5677_dsp_mode_i2c_write - Write register on DSP mode. 652 * rt5677: Private Data. 653 * @reg: Register index. 654 * @value: Register data. 655 * 656 * 657 * Returns 0 for success or negative error code. 658 */ 659 static int rt5677_dsp_mode_i2c_write(struct rt5677_priv *rt5677, 660 unsigned int reg, unsigned int value) 661 { 662 return rt5677_dsp_mode_i2c_write_addr(rt5677, 0x18020000 + reg * 2, 663 value, 0x0001); 664 } 665 666 /** 667 * rt5677_dsp_mode_i2c_read - Read register on DSP mode. 668 * @codec: SoC audio codec device. 669 * @reg: Register index. 670 * @value: Register data. 671 * 672 * 673 * Returns 0 for success or negative error code. 674 */ 675 static int rt5677_dsp_mode_i2c_read( 676 struct rt5677_priv *rt5677, unsigned int reg, unsigned int *value) 677 { 678 int ret = rt5677_dsp_mode_i2c_read_addr(rt5677, 0x18020000 + reg * 2, 679 value); 680 681 *value &= 0xffff; 682 683 return ret; 684 } 685 686 static void rt5677_set_dsp_mode(struct snd_soc_codec *codec, bool on) 687 { 688 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec); 689 690 if (on) { 691 regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, 0x2, 0x2); 692 rt5677->is_dsp_mode = true; 693 } else { 694 regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, 0x2, 0x0); 695 rt5677->is_dsp_mode = false; 696 } 697 } 698 699 static int rt5677_set_dsp_vad(struct snd_soc_codec *codec, bool on) 700 { 701 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec); 702 static bool activity; 703 int ret; 704 705 if (on && !activity) { 706 activity = true; 707 708 regcache_cache_only(rt5677->regmap, false); 709 regcache_cache_bypass(rt5677->regmap, true); 710 711 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x1, 0x1); 712 regmap_update_bits(rt5677->regmap, 713 RT5677_PR_BASE + RT5677_BIAS_CUR4, 0x0f00, 0x0f00); 714 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1, 715 RT5677_LDO1_SEL_MASK, 0x0); 716 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2, 717 RT5677_PWR_LDO1, RT5677_PWR_LDO1); 718 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1, 719 RT5677_MCLK_SRC_MASK, RT5677_MCLK2_SRC); 720 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK2, 721 RT5677_PLL2_PR_SRC_MASK | RT5677_DSP_CLK_SRC_MASK, 722 RT5677_PLL2_PR_SRC_MCLK2 | RT5677_DSP_CLK_SRC_BYPASS); 723 regmap_write(rt5677->regmap, RT5677_PWR_DSP2, 0x07ff); 724 regmap_write(rt5677->regmap, RT5677_PWR_DSP1, 0x07fd); 725 rt5677_set_dsp_mode(codec, true); 726 727 ret = request_firmware(&rt5677->fw1, RT5677_FIRMWARE1, 728 codec->dev); 729 if (ret == 0) { 730 rt5677_spi_burst_write(0x50000000, rt5677->fw1); 731 release_firmware(rt5677->fw1); 732 } 733 734 ret = request_firmware(&rt5677->fw2, RT5677_FIRMWARE2, 735 codec->dev); 736 if (ret == 0) { 737 rt5677_spi_burst_write(0x60000000, rt5677->fw2); 738 release_firmware(rt5677->fw2); 739 } 740 741 regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, 0x1, 0x0); 742 743 regcache_cache_bypass(rt5677->regmap, false); 744 regcache_cache_only(rt5677->regmap, true); 745 } else if (!on && activity) { 746 activity = false; 747 748 regcache_cache_only(rt5677->regmap, false); 749 regcache_cache_bypass(rt5677->regmap, true); 750 751 regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, 0x1, 0x1); 752 rt5677_set_dsp_mode(codec, false); 753 regmap_write(rt5677->regmap, RT5677_PWR_DSP1, 0x0001); 754 755 regmap_write(rt5677->regmap, RT5677_RESET, 0x10ec); 756 757 regcache_cache_bypass(rt5677->regmap, false); 758 regcache_mark_dirty(rt5677->regmap); 759 regcache_sync(rt5677->regmap); 760 } 761 762 return 0; 763 } 764 765 static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -4650, 150, 0); 766 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6525, 75, 0); 767 static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -3450, 150, 0); 768 static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0); 769 static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0); 770 static const DECLARE_TLV_DB_SCALE(st_vol_tlv, -4650, 150, 0); 771 772 /* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */ 773 static unsigned int bst_tlv[] = { 774 TLV_DB_RANGE_HEAD(7), 775 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0), 776 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0), 777 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0), 778 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0), 779 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0), 780 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0), 781 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0), 782 }; 783 784 static int rt5677_dsp_vad_get(struct snd_kcontrol *kcontrol, 785 struct snd_ctl_elem_value *ucontrol) 786 { 787 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 788 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component); 789 790 ucontrol->value.integer.value[0] = rt5677->dsp_vad_en; 791 792 return 0; 793 } 794 795 static int rt5677_dsp_vad_put(struct snd_kcontrol *kcontrol, 796 struct snd_ctl_elem_value *ucontrol) 797 { 798 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 799 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component); 800 struct snd_soc_codec *codec = snd_soc_component_to_codec(component); 801 802 rt5677->dsp_vad_en = !!ucontrol->value.integer.value[0]; 803 804 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) 805 rt5677_set_dsp_vad(codec, rt5677->dsp_vad_en); 806 807 return 0; 808 } 809 810 static const struct snd_kcontrol_new rt5677_snd_controls[] = { 811 /* OUTPUT Control */ 812 SOC_SINGLE("OUT1 Playback Switch", RT5677_LOUT1, 813 RT5677_LOUT1_L_MUTE_SFT, 1, 1), 814 SOC_SINGLE("OUT2 Playback Switch", RT5677_LOUT1, 815 RT5677_LOUT2_L_MUTE_SFT, 1, 1), 816 SOC_SINGLE("OUT3 Playback Switch", RT5677_LOUT1, 817 RT5677_LOUT3_L_MUTE_SFT, 1, 1), 818 819 /* DAC Digital Volume */ 820 SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5677_DAC1_DIG_VOL, 821 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 87, 0, dac_vol_tlv), 822 SOC_DOUBLE_TLV("DAC2 Playback Volume", RT5677_DAC2_DIG_VOL, 823 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 87, 0, dac_vol_tlv), 824 SOC_DOUBLE_TLV("DAC3 Playback Volume", RT5677_DAC3_DIG_VOL, 825 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 87, 0, dac_vol_tlv), 826 SOC_DOUBLE_TLV("DAC4 Playback Volume", RT5677_DAC4_DIG_VOL, 827 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 87, 0, dac_vol_tlv), 828 829 /* IN1/IN2 Control */ 830 SOC_SINGLE_TLV("IN1 Boost", RT5677_IN1, RT5677_BST_SFT1, 8, 0, bst_tlv), 831 SOC_SINGLE_TLV("IN2 Boost", RT5677_IN1, RT5677_BST_SFT2, 8, 0, bst_tlv), 832 833 /* ADC Digital Volume Control */ 834 SOC_DOUBLE("ADC1 Capture Switch", RT5677_STO1_ADC_DIG_VOL, 835 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1), 836 SOC_DOUBLE("ADC2 Capture Switch", RT5677_STO2_ADC_DIG_VOL, 837 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1), 838 SOC_DOUBLE("ADC3 Capture Switch", RT5677_STO3_ADC_DIG_VOL, 839 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1), 840 SOC_DOUBLE("ADC4 Capture Switch", RT5677_STO4_ADC_DIG_VOL, 841 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1), 842 SOC_DOUBLE("Mono ADC Capture Switch", RT5677_MONO_ADC_DIG_VOL, 843 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1), 844 845 SOC_DOUBLE_TLV("ADC1 Capture Volume", RT5677_STO1_ADC_DIG_VOL, 846 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 63, 0, 847 adc_vol_tlv), 848 SOC_DOUBLE_TLV("ADC2 Capture Volume", RT5677_STO2_ADC_DIG_VOL, 849 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 63, 0, 850 adc_vol_tlv), 851 SOC_DOUBLE_TLV("ADC3 Capture Volume", RT5677_STO3_ADC_DIG_VOL, 852 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 63, 0, 853 adc_vol_tlv), 854 SOC_DOUBLE_TLV("ADC4 Capture Volume", RT5677_STO4_ADC_DIG_VOL, 855 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 63, 0, 856 adc_vol_tlv), 857 SOC_DOUBLE_TLV("Mono ADC Capture Volume", RT5677_MONO_ADC_DIG_VOL, 858 RT5677_MONO_ADC_L_VOL_SFT, RT5677_MONO_ADC_R_VOL_SFT, 63, 0, 859 adc_vol_tlv), 860 861 /* Sidetone Control */ 862 SOC_SINGLE_TLV("Sidetone Volume", RT5677_SIDETONE_CTRL, 863 RT5677_ST_VOL_SFT, 31, 0, st_vol_tlv), 864 865 /* ADC Boost Volume Control */ 866 SOC_DOUBLE_TLV("STO1 ADC Boost Volume", RT5677_STO1_2_ADC_BST, 867 RT5677_STO1_ADC_L_BST_SFT, RT5677_STO1_ADC_R_BST_SFT, 3, 0, 868 adc_bst_tlv), 869 SOC_DOUBLE_TLV("STO2 ADC Boost Volume", RT5677_STO1_2_ADC_BST, 870 RT5677_STO2_ADC_L_BST_SFT, RT5677_STO2_ADC_R_BST_SFT, 3, 0, 871 adc_bst_tlv), 872 SOC_DOUBLE_TLV("STO3 ADC Boost Volume", RT5677_STO3_4_ADC_BST, 873 RT5677_STO3_ADC_L_BST_SFT, RT5677_STO3_ADC_R_BST_SFT, 3, 0, 874 adc_bst_tlv), 875 SOC_DOUBLE_TLV("STO4 ADC Boost Volume", RT5677_STO3_4_ADC_BST, 876 RT5677_STO4_ADC_L_BST_SFT, RT5677_STO4_ADC_R_BST_SFT, 3, 0, 877 adc_bst_tlv), 878 SOC_DOUBLE_TLV("Mono ADC Boost Volume", RT5677_ADC_BST_CTRL2, 879 RT5677_MONO_ADC_L_BST_SFT, RT5677_MONO_ADC_R_BST_SFT, 3, 0, 880 adc_bst_tlv), 881 882 SOC_SINGLE_EXT("DSP VAD Switch", SND_SOC_NOPM, 0, 1, 0, 883 rt5677_dsp_vad_get, rt5677_dsp_vad_put), 884 }; 885 886 /** 887 * set_dmic_clk - Set parameter of dmic. 888 * 889 * @w: DAPM widget. 890 * @kcontrol: The kcontrol of this widget. 891 * @event: Event id. 892 * 893 * Choose dmic clock between 1MHz and 3MHz. 894 * It is better for clock to approximate 3MHz. 895 */ 896 static int set_dmic_clk(struct snd_soc_dapm_widget *w, 897 struct snd_kcontrol *kcontrol, int event) 898 { 899 struct snd_soc_codec *codec = w->codec; 900 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec); 901 int idx = rl6231_calc_dmic_clk(rt5677->sysclk); 902 903 if (idx < 0) 904 dev_err(codec->dev, "Failed to set DMIC clock\n"); 905 else 906 regmap_update_bits(rt5677->regmap, RT5677_DMIC_CTRL1, 907 RT5677_DMIC_CLK_MASK, idx << RT5677_DMIC_CLK_SFT); 908 return idx; 909 } 910 911 static int is_sys_clk_from_pll(struct snd_soc_dapm_widget *source, 912 struct snd_soc_dapm_widget *sink) 913 { 914 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(source->codec); 915 unsigned int val; 916 917 regmap_read(rt5677->regmap, RT5677_GLB_CLK1, &val); 918 val &= RT5677_SCLK_SRC_MASK; 919 if (val == RT5677_SCLK_SRC_PLL1) 920 return 1; 921 else 922 return 0; 923 } 924 925 /* Digital Mixer */ 926 static const struct snd_kcontrol_new rt5677_sto1_adc_l_mix[] = { 927 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO1_ADC_MIXER, 928 RT5677_M_STO1_ADC_L1_SFT, 1, 1), 929 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO1_ADC_MIXER, 930 RT5677_M_STO1_ADC_L2_SFT, 1, 1), 931 }; 932 933 static const struct snd_kcontrol_new rt5677_sto1_adc_r_mix[] = { 934 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO1_ADC_MIXER, 935 RT5677_M_STO1_ADC_R1_SFT, 1, 1), 936 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO1_ADC_MIXER, 937 RT5677_M_STO1_ADC_R2_SFT, 1, 1), 938 }; 939 940 static const struct snd_kcontrol_new rt5677_sto2_adc_l_mix[] = { 941 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO2_ADC_MIXER, 942 RT5677_M_STO2_ADC_L1_SFT, 1, 1), 943 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO2_ADC_MIXER, 944 RT5677_M_STO2_ADC_L2_SFT, 1, 1), 945 }; 946 947 static const struct snd_kcontrol_new rt5677_sto2_adc_r_mix[] = { 948 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO2_ADC_MIXER, 949 RT5677_M_STO2_ADC_R1_SFT, 1, 1), 950 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO2_ADC_MIXER, 951 RT5677_M_STO2_ADC_R2_SFT, 1, 1), 952 }; 953 954 static const struct snd_kcontrol_new rt5677_sto3_adc_l_mix[] = { 955 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO3_ADC_MIXER, 956 RT5677_M_STO3_ADC_L1_SFT, 1, 1), 957 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO3_ADC_MIXER, 958 RT5677_M_STO3_ADC_L2_SFT, 1, 1), 959 }; 960 961 static const struct snd_kcontrol_new rt5677_sto3_adc_r_mix[] = { 962 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO3_ADC_MIXER, 963 RT5677_M_STO3_ADC_R1_SFT, 1, 1), 964 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO3_ADC_MIXER, 965 RT5677_M_STO3_ADC_R2_SFT, 1, 1), 966 }; 967 968 static const struct snd_kcontrol_new rt5677_sto4_adc_l_mix[] = { 969 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO4_ADC_MIXER, 970 RT5677_M_STO4_ADC_L1_SFT, 1, 1), 971 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO4_ADC_MIXER, 972 RT5677_M_STO4_ADC_L2_SFT, 1, 1), 973 }; 974 975 static const struct snd_kcontrol_new rt5677_sto4_adc_r_mix[] = { 976 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO4_ADC_MIXER, 977 RT5677_M_STO4_ADC_R1_SFT, 1, 1), 978 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO4_ADC_MIXER, 979 RT5677_M_STO4_ADC_R2_SFT, 1, 1), 980 }; 981 982 static const struct snd_kcontrol_new rt5677_mono_adc_l_mix[] = { 983 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_MONO_ADC_MIXER, 984 RT5677_M_MONO_ADC_L1_SFT, 1, 1), 985 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_MONO_ADC_MIXER, 986 RT5677_M_MONO_ADC_L2_SFT, 1, 1), 987 }; 988 989 static const struct snd_kcontrol_new rt5677_mono_adc_r_mix[] = { 990 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_MONO_ADC_MIXER, 991 RT5677_M_MONO_ADC_R1_SFT, 1, 1), 992 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_MONO_ADC_MIXER, 993 RT5677_M_MONO_ADC_R2_SFT, 1, 1), 994 }; 995 996 static const struct snd_kcontrol_new rt5677_dac_l_mix[] = { 997 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5677_ADC_IF_DSP_DAC1_MIXER, 998 RT5677_M_ADDA_MIXER1_L_SFT, 1, 1), 999 SOC_DAPM_SINGLE("DAC1 Switch", RT5677_ADC_IF_DSP_DAC1_MIXER, 1000 RT5677_M_DAC1_L_SFT, 1, 1), 1001 }; 1002 1003 static const struct snd_kcontrol_new rt5677_dac_r_mix[] = { 1004 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5677_ADC_IF_DSP_DAC1_MIXER, 1005 RT5677_M_ADDA_MIXER1_R_SFT, 1, 1), 1006 SOC_DAPM_SINGLE("DAC1 Switch", RT5677_ADC_IF_DSP_DAC1_MIXER, 1007 RT5677_M_DAC1_R_SFT, 1, 1), 1008 }; 1009 1010 static const struct snd_kcontrol_new rt5677_sto1_dac_l_mix[] = { 1011 SOC_DAPM_SINGLE("ST L Switch", RT5677_STO1_DAC_MIXER, 1012 RT5677_M_ST_DAC1_L_SFT, 1, 1), 1013 SOC_DAPM_SINGLE("DAC1 L Switch", RT5677_STO1_DAC_MIXER, 1014 RT5677_M_DAC1_L_STO_L_SFT, 1, 1), 1015 SOC_DAPM_SINGLE("DAC2 L Switch", RT5677_STO1_DAC_MIXER, 1016 RT5677_M_DAC2_L_STO_L_SFT, 1, 1), 1017 SOC_DAPM_SINGLE("DAC1 R Switch", RT5677_STO1_DAC_MIXER, 1018 RT5677_M_DAC1_R_STO_L_SFT, 1, 1), 1019 }; 1020 1021 static const struct snd_kcontrol_new rt5677_sto1_dac_r_mix[] = { 1022 SOC_DAPM_SINGLE("ST R Switch", RT5677_STO1_DAC_MIXER, 1023 RT5677_M_ST_DAC1_R_SFT, 1, 1), 1024 SOC_DAPM_SINGLE("DAC1 R Switch", RT5677_STO1_DAC_MIXER, 1025 RT5677_M_DAC1_R_STO_R_SFT, 1, 1), 1026 SOC_DAPM_SINGLE("DAC2 R Switch", RT5677_STO1_DAC_MIXER, 1027 RT5677_M_DAC2_R_STO_R_SFT, 1, 1), 1028 SOC_DAPM_SINGLE("DAC1 L Switch", RT5677_STO1_DAC_MIXER, 1029 RT5677_M_DAC1_L_STO_R_SFT, 1, 1), 1030 }; 1031 1032 static const struct snd_kcontrol_new rt5677_mono_dac_l_mix[] = { 1033 SOC_DAPM_SINGLE("ST L Switch", RT5677_MONO_DAC_MIXER, 1034 RT5677_M_ST_DAC2_L_SFT, 1, 1), 1035 SOC_DAPM_SINGLE("DAC1 L Switch", RT5677_MONO_DAC_MIXER, 1036 RT5677_M_DAC1_L_MONO_L_SFT, 1, 1), 1037 SOC_DAPM_SINGLE("DAC2 L Switch", RT5677_MONO_DAC_MIXER, 1038 RT5677_M_DAC2_L_MONO_L_SFT, 1, 1), 1039 SOC_DAPM_SINGLE("DAC2 R Switch", RT5677_MONO_DAC_MIXER, 1040 RT5677_M_DAC2_R_MONO_L_SFT, 1, 1), 1041 }; 1042 1043 static const struct snd_kcontrol_new rt5677_mono_dac_r_mix[] = { 1044 SOC_DAPM_SINGLE("ST R Switch", RT5677_MONO_DAC_MIXER, 1045 RT5677_M_ST_DAC2_R_SFT, 1, 1), 1046 SOC_DAPM_SINGLE("DAC1 R Switch", RT5677_MONO_DAC_MIXER, 1047 RT5677_M_DAC1_R_MONO_R_SFT, 1, 1), 1048 SOC_DAPM_SINGLE("DAC2 R Switch", RT5677_MONO_DAC_MIXER, 1049 RT5677_M_DAC2_R_MONO_R_SFT, 1, 1), 1050 SOC_DAPM_SINGLE("DAC2 L Switch", RT5677_MONO_DAC_MIXER, 1051 RT5677_M_DAC2_L_MONO_R_SFT, 1, 1), 1052 }; 1053 1054 static const struct snd_kcontrol_new rt5677_dd1_l_mix[] = { 1055 SOC_DAPM_SINGLE("Sto DAC Mix L Switch", RT5677_DD1_MIXER, 1056 RT5677_M_STO_L_DD1_L_SFT, 1, 1), 1057 SOC_DAPM_SINGLE("Mono DAC Mix L Switch", RT5677_DD1_MIXER, 1058 RT5677_M_MONO_L_DD1_L_SFT, 1, 1), 1059 SOC_DAPM_SINGLE("DAC3 L Switch", RT5677_DD1_MIXER, 1060 RT5677_M_DAC3_L_DD1_L_SFT, 1, 1), 1061 SOC_DAPM_SINGLE("DAC3 R Switch", RT5677_DD1_MIXER, 1062 RT5677_M_DAC3_R_DD1_L_SFT, 1, 1), 1063 }; 1064 1065 static const struct snd_kcontrol_new rt5677_dd1_r_mix[] = { 1066 SOC_DAPM_SINGLE("Sto DAC Mix R Switch", RT5677_DD1_MIXER, 1067 RT5677_M_STO_R_DD1_R_SFT, 1, 1), 1068 SOC_DAPM_SINGLE("Mono DAC Mix R Switch", RT5677_DD1_MIXER, 1069 RT5677_M_MONO_R_DD1_R_SFT, 1, 1), 1070 SOC_DAPM_SINGLE("DAC3 R Switch", RT5677_DD1_MIXER, 1071 RT5677_M_DAC3_R_DD1_R_SFT, 1, 1), 1072 SOC_DAPM_SINGLE("DAC3 L Switch", RT5677_DD1_MIXER, 1073 RT5677_M_DAC3_L_DD1_R_SFT, 1, 1), 1074 }; 1075 1076 static const struct snd_kcontrol_new rt5677_dd2_l_mix[] = { 1077 SOC_DAPM_SINGLE("Sto DAC Mix L Switch", RT5677_DD2_MIXER, 1078 RT5677_M_STO_L_DD2_L_SFT, 1, 1), 1079 SOC_DAPM_SINGLE("Mono DAC Mix L Switch", RT5677_DD2_MIXER, 1080 RT5677_M_MONO_L_DD2_L_SFT, 1, 1), 1081 SOC_DAPM_SINGLE("DAC4 L Switch", RT5677_DD2_MIXER, 1082 RT5677_M_DAC4_L_DD2_L_SFT, 1, 1), 1083 SOC_DAPM_SINGLE("DAC4 R Switch", RT5677_DD2_MIXER, 1084 RT5677_M_DAC4_R_DD2_L_SFT, 1, 1), 1085 }; 1086 1087 static const struct snd_kcontrol_new rt5677_dd2_r_mix[] = { 1088 SOC_DAPM_SINGLE("Sto DAC Mix R Switch", RT5677_DD2_MIXER, 1089 RT5677_M_STO_R_DD2_R_SFT, 1, 1), 1090 SOC_DAPM_SINGLE("Mono DAC Mix R Switch", RT5677_DD2_MIXER, 1091 RT5677_M_MONO_R_DD2_R_SFT, 1, 1), 1092 SOC_DAPM_SINGLE("DAC4 R Switch", RT5677_DD2_MIXER, 1093 RT5677_M_DAC4_R_DD2_R_SFT, 1, 1), 1094 SOC_DAPM_SINGLE("DAC4 L Switch", RT5677_DD2_MIXER, 1095 RT5677_M_DAC4_L_DD2_R_SFT, 1, 1), 1096 }; 1097 1098 static const struct snd_kcontrol_new rt5677_ob_01_mix[] = { 1099 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL, 1100 RT5677_DSP_IB_01_H_SFT, 1, 1), 1101 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL, 1102 RT5677_DSP_IB_23_H_SFT, 1, 1), 1103 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL, 1104 RT5677_DSP_IB_45_H_SFT, 1, 1), 1105 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL, 1106 RT5677_DSP_IB_6_H_SFT, 1, 1), 1107 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL, 1108 RT5677_DSP_IB_7_H_SFT, 1, 1), 1109 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL, 1110 RT5677_DSP_IB_8_H_SFT, 1, 1), 1111 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL, 1112 RT5677_DSP_IB_9_H_SFT, 1, 1), 1113 }; 1114 1115 static const struct snd_kcontrol_new rt5677_ob_23_mix[] = { 1116 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL, 1117 RT5677_DSP_IB_01_L_SFT, 1, 1), 1118 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL, 1119 RT5677_DSP_IB_23_L_SFT, 1, 1), 1120 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL, 1121 RT5677_DSP_IB_45_L_SFT, 1, 1), 1122 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL, 1123 RT5677_DSP_IB_6_L_SFT, 1, 1), 1124 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL, 1125 RT5677_DSP_IB_7_L_SFT, 1, 1), 1126 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL, 1127 RT5677_DSP_IB_8_L_SFT, 1, 1), 1128 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL, 1129 RT5677_DSP_IB_9_L_SFT, 1, 1), 1130 }; 1131 1132 static const struct snd_kcontrol_new rt5677_ob_4_mix[] = { 1133 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL, 1134 RT5677_DSP_IB_01_H_SFT, 1, 1), 1135 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL, 1136 RT5677_DSP_IB_23_H_SFT, 1, 1), 1137 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL, 1138 RT5677_DSP_IB_45_H_SFT, 1, 1), 1139 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL, 1140 RT5677_DSP_IB_6_H_SFT, 1, 1), 1141 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL, 1142 RT5677_DSP_IB_7_H_SFT, 1, 1), 1143 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL, 1144 RT5677_DSP_IB_8_H_SFT, 1, 1), 1145 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL, 1146 RT5677_DSP_IB_9_H_SFT, 1, 1), 1147 }; 1148 1149 static const struct snd_kcontrol_new rt5677_ob_5_mix[] = { 1150 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL, 1151 RT5677_DSP_IB_01_L_SFT, 1, 1), 1152 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL, 1153 RT5677_DSP_IB_23_L_SFT, 1, 1), 1154 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL, 1155 RT5677_DSP_IB_45_L_SFT, 1, 1), 1156 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL, 1157 RT5677_DSP_IB_6_L_SFT, 1, 1), 1158 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL, 1159 RT5677_DSP_IB_7_L_SFT, 1, 1), 1160 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL, 1161 RT5677_DSP_IB_8_L_SFT, 1, 1), 1162 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL, 1163 RT5677_DSP_IB_9_L_SFT, 1, 1), 1164 }; 1165 1166 static const struct snd_kcontrol_new rt5677_ob_6_mix[] = { 1167 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL, 1168 RT5677_DSP_IB_01_H_SFT, 1, 1), 1169 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL, 1170 RT5677_DSP_IB_23_H_SFT, 1, 1), 1171 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL, 1172 RT5677_DSP_IB_45_H_SFT, 1, 1), 1173 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL, 1174 RT5677_DSP_IB_6_H_SFT, 1, 1), 1175 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL, 1176 RT5677_DSP_IB_7_H_SFT, 1, 1), 1177 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL, 1178 RT5677_DSP_IB_8_H_SFT, 1, 1), 1179 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL, 1180 RT5677_DSP_IB_9_H_SFT, 1, 1), 1181 }; 1182 1183 static const struct snd_kcontrol_new rt5677_ob_7_mix[] = { 1184 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL, 1185 RT5677_DSP_IB_01_L_SFT, 1, 1), 1186 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL, 1187 RT5677_DSP_IB_23_L_SFT, 1, 1), 1188 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL, 1189 RT5677_DSP_IB_45_L_SFT, 1, 1), 1190 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL, 1191 RT5677_DSP_IB_6_L_SFT, 1, 1), 1192 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL, 1193 RT5677_DSP_IB_7_L_SFT, 1, 1), 1194 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL, 1195 RT5677_DSP_IB_8_L_SFT, 1, 1), 1196 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL, 1197 RT5677_DSP_IB_9_L_SFT, 1, 1), 1198 }; 1199 1200 1201 /* Mux */ 1202 /* DAC1 L/R Source */ /* MX-29 [10:8] */ 1203 static const char * const rt5677_dac1_src[] = { 1204 "IF1 DAC 01", "IF2 DAC 01", "IF3 DAC LR", "IF4 DAC LR", "SLB DAC 01", 1205 "OB 01" 1206 }; 1207 1208 static SOC_ENUM_SINGLE_DECL( 1209 rt5677_dac1_enum, RT5677_ADC_IF_DSP_DAC1_MIXER, 1210 RT5677_DAC1_L_SEL_SFT, rt5677_dac1_src); 1211 1212 static const struct snd_kcontrol_new rt5677_dac1_mux = 1213 SOC_DAPM_ENUM("DAC1 Source", rt5677_dac1_enum); 1214 1215 /* ADDA1 L/R Source */ /* MX-29 [1:0] */ 1216 static const char * const rt5677_adda1_src[] = { 1217 "STO1 ADC MIX", "STO2 ADC MIX", "OB 67", 1218 }; 1219 1220 static SOC_ENUM_SINGLE_DECL( 1221 rt5677_adda1_enum, RT5677_ADC_IF_DSP_DAC1_MIXER, 1222 RT5677_ADDA1_SEL_SFT, rt5677_adda1_src); 1223 1224 static const struct snd_kcontrol_new rt5677_adda1_mux = 1225 SOC_DAPM_ENUM("ADDA1 Source", rt5677_adda1_enum); 1226 1227 1228 /*DAC2 L/R Source*/ /* MX-1B [6:4] [2:0] */ 1229 static const char * const rt5677_dac2l_src[] = { 1230 "IF1 DAC 2", "IF2 DAC 2", "IF3 DAC L", "IF4 DAC L", "SLB DAC 2", 1231 "OB 2", 1232 }; 1233 1234 static SOC_ENUM_SINGLE_DECL( 1235 rt5677_dac2l_enum, RT5677_IF_DSP_DAC2_MIXER, 1236 RT5677_SEL_DAC2_L_SRC_SFT, rt5677_dac2l_src); 1237 1238 static const struct snd_kcontrol_new rt5677_dac2_l_mux = 1239 SOC_DAPM_ENUM("DAC2 L Source", rt5677_dac2l_enum); 1240 1241 static const char * const rt5677_dac2r_src[] = { 1242 "IF1 DAC 3", "IF2 DAC 3", "IF3 DAC R", "IF4 DAC R", "SLB DAC 3", 1243 "OB 3", "Haptic Generator", "VAD ADC" 1244 }; 1245 1246 static SOC_ENUM_SINGLE_DECL( 1247 rt5677_dac2r_enum, RT5677_IF_DSP_DAC2_MIXER, 1248 RT5677_SEL_DAC2_R_SRC_SFT, rt5677_dac2r_src); 1249 1250 static const struct snd_kcontrol_new rt5677_dac2_r_mux = 1251 SOC_DAPM_ENUM("DAC2 R Source", rt5677_dac2r_enum); 1252 1253 /*DAC3 L/R Source*/ /* MX-16 [6:4] [2:0] */ 1254 static const char * const rt5677_dac3l_src[] = { 1255 "IF1 DAC 4", "IF2 DAC 4", "IF3 DAC L", "IF4 DAC L", 1256 "SLB DAC 4", "OB 4" 1257 }; 1258 1259 static SOC_ENUM_SINGLE_DECL( 1260 rt5677_dac3l_enum, RT5677_IF_DSP_DAC3_4_MIXER, 1261 RT5677_SEL_DAC3_L_SRC_SFT, rt5677_dac3l_src); 1262 1263 static const struct snd_kcontrol_new rt5677_dac3_l_mux = 1264 SOC_DAPM_ENUM("DAC3 L Source", rt5677_dac3l_enum); 1265 1266 static const char * const rt5677_dac3r_src[] = { 1267 "IF1 DAC 5", "IF2 DAC 5", "IF3 DAC R", "IF4 DAC R", 1268 "SLB DAC 5", "OB 5" 1269 }; 1270 1271 static SOC_ENUM_SINGLE_DECL( 1272 rt5677_dac3r_enum, RT5677_IF_DSP_DAC3_4_MIXER, 1273 RT5677_SEL_DAC3_R_SRC_SFT, rt5677_dac3r_src); 1274 1275 static const struct snd_kcontrol_new rt5677_dac3_r_mux = 1276 SOC_DAPM_ENUM("DAC3 R Source", rt5677_dac3r_enum); 1277 1278 /*DAC4 L/R Source*/ /* MX-16 [14:12] [10:8] */ 1279 static const char * const rt5677_dac4l_src[] = { 1280 "IF1 DAC 6", "IF2 DAC 6", "IF3 DAC L", "IF4 DAC L", 1281 "SLB DAC 6", "OB 6" 1282 }; 1283 1284 static SOC_ENUM_SINGLE_DECL( 1285 rt5677_dac4l_enum, RT5677_IF_DSP_DAC3_4_MIXER, 1286 RT5677_SEL_DAC4_L_SRC_SFT, rt5677_dac4l_src); 1287 1288 static const struct snd_kcontrol_new rt5677_dac4_l_mux = 1289 SOC_DAPM_ENUM("DAC4 L Source", rt5677_dac4l_enum); 1290 1291 static const char * const rt5677_dac4r_src[] = { 1292 "IF1 DAC 7", "IF2 DAC 7", "IF3 DAC R", "IF4 DAC R", 1293 "SLB DAC 7", "OB 7" 1294 }; 1295 1296 static SOC_ENUM_SINGLE_DECL( 1297 rt5677_dac4r_enum, RT5677_IF_DSP_DAC3_4_MIXER, 1298 RT5677_SEL_DAC4_R_SRC_SFT, rt5677_dac4r_src); 1299 1300 static const struct snd_kcontrol_new rt5677_dac4_r_mux = 1301 SOC_DAPM_ENUM("DAC4 R Source", rt5677_dac4r_enum); 1302 1303 /* In/OutBound Source Pass SRC */ /* MX-A5 [3] [4] [0] [1] [2] */ 1304 static const char * const rt5677_iob_bypass_src[] = { 1305 "Bypass", "Pass SRC" 1306 }; 1307 1308 static SOC_ENUM_SINGLE_DECL( 1309 rt5677_ob01_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL, 1310 RT5677_SEL_SRC_OB01_SFT, rt5677_iob_bypass_src); 1311 1312 static const struct snd_kcontrol_new rt5677_ob01_bypass_src_mux = 1313 SOC_DAPM_ENUM("OB01 Bypass Source", rt5677_ob01_bypass_src_enum); 1314 1315 static SOC_ENUM_SINGLE_DECL( 1316 rt5677_ob23_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL, 1317 RT5677_SEL_SRC_OB23_SFT, rt5677_iob_bypass_src); 1318 1319 static const struct snd_kcontrol_new rt5677_ob23_bypass_src_mux = 1320 SOC_DAPM_ENUM("OB23 Bypass Source", rt5677_ob23_bypass_src_enum); 1321 1322 static SOC_ENUM_SINGLE_DECL( 1323 rt5677_ib01_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL, 1324 RT5677_SEL_SRC_IB01_SFT, rt5677_iob_bypass_src); 1325 1326 static const struct snd_kcontrol_new rt5677_ib01_bypass_src_mux = 1327 SOC_DAPM_ENUM("IB01 Bypass Source", rt5677_ib01_bypass_src_enum); 1328 1329 static SOC_ENUM_SINGLE_DECL( 1330 rt5677_ib23_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL, 1331 RT5677_SEL_SRC_IB23_SFT, rt5677_iob_bypass_src); 1332 1333 static const struct snd_kcontrol_new rt5677_ib23_bypass_src_mux = 1334 SOC_DAPM_ENUM("IB23 Bypass Source", rt5677_ib23_bypass_src_enum); 1335 1336 static SOC_ENUM_SINGLE_DECL( 1337 rt5677_ib45_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL, 1338 RT5677_SEL_SRC_IB45_SFT, rt5677_iob_bypass_src); 1339 1340 static const struct snd_kcontrol_new rt5677_ib45_bypass_src_mux = 1341 SOC_DAPM_ENUM("IB45 Bypass Source", rt5677_ib45_bypass_src_enum); 1342 1343 /* Stereo ADC Source 2 */ /* MX-27 MX26 MX25 [11:10] */ 1344 static const char * const rt5677_stereo_adc2_src[] = { 1345 "DD MIX1", "DMIC", "Stereo DAC MIX" 1346 }; 1347 1348 static SOC_ENUM_SINGLE_DECL( 1349 rt5677_stereo1_adc2_enum, RT5677_STO1_ADC_MIXER, 1350 RT5677_SEL_STO1_ADC2_SFT, rt5677_stereo_adc2_src); 1351 1352 static const struct snd_kcontrol_new rt5677_sto1_adc2_mux = 1353 SOC_DAPM_ENUM("Stereo1 ADC2 Source", rt5677_stereo1_adc2_enum); 1354 1355 static SOC_ENUM_SINGLE_DECL( 1356 rt5677_stereo2_adc2_enum, RT5677_STO2_ADC_MIXER, 1357 RT5677_SEL_STO2_ADC2_SFT, rt5677_stereo_adc2_src); 1358 1359 static const struct snd_kcontrol_new rt5677_sto2_adc2_mux = 1360 SOC_DAPM_ENUM("Stereo2 ADC2 Source", rt5677_stereo2_adc2_enum); 1361 1362 static SOC_ENUM_SINGLE_DECL( 1363 rt5677_stereo3_adc2_enum, RT5677_STO3_ADC_MIXER, 1364 RT5677_SEL_STO3_ADC2_SFT, rt5677_stereo_adc2_src); 1365 1366 static const struct snd_kcontrol_new rt5677_sto3_adc2_mux = 1367 SOC_DAPM_ENUM("Stereo3 ADC2 Source", rt5677_stereo3_adc2_enum); 1368 1369 /* DMIC Source */ /* MX-28 [9:8][1:0] MX-27 MX-26 MX-25 MX-24 [9:8] */ 1370 static const char * const rt5677_dmic_src[] = { 1371 "DMIC1", "DMIC2", "DMIC3", "DMIC4" 1372 }; 1373 1374 static SOC_ENUM_SINGLE_DECL( 1375 rt5677_mono_dmic_l_enum, RT5677_MONO_ADC_MIXER, 1376 RT5677_SEL_MONO_DMIC_L_SFT, rt5677_dmic_src); 1377 1378 static const struct snd_kcontrol_new rt5677_mono_dmic_l_mux = 1379 SOC_DAPM_ENUM("Mono DMIC L Source", rt5677_mono_dmic_l_enum); 1380 1381 static SOC_ENUM_SINGLE_DECL( 1382 rt5677_mono_dmic_r_enum, RT5677_MONO_ADC_MIXER, 1383 RT5677_SEL_MONO_DMIC_R_SFT, rt5677_dmic_src); 1384 1385 static const struct snd_kcontrol_new rt5677_mono_dmic_r_mux = 1386 SOC_DAPM_ENUM("Mono DMIC R Source", rt5677_mono_dmic_r_enum); 1387 1388 static SOC_ENUM_SINGLE_DECL( 1389 rt5677_stereo1_dmic_enum, RT5677_STO1_ADC_MIXER, 1390 RT5677_SEL_STO1_DMIC_SFT, rt5677_dmic_src); 1391 1392 static const struct snd_kcontrol_new rt5677_sto1_dmic_mux = 1393 SOC_DAPM_ENUM("Stereo1 DMIC Source", rt5677_stereo1_dmic_enum); 1394 1395 static SOC_ENUM_SINGLE_DECL( 1396 rt5677_stereo2_dmic_enum, RT5677_STO2_ADC_MIXER, 1397 RT5677_SEL_STO2_DMIC_SFT, rt5677_dmic_src); 1398 1399 static const struct snd_kcontrol_new rt5677_sto2_dmic_mux = 1400 SOC_DAPM_ENUM("Stereo2 DMIC Source", rt5677_stereo2_dmic_enum); 1401 1402 static SOC_ENUM_SINGLE_DECL( 1403 rt5677_stereo3_dmic_enum, RT5677_STO3_ADC_MIXER, 1404 RT5677_SEL_STO3_DMIC_SFT, rt5677_dmic_src); 1405 1406 static const struct snd_kcontrol_new rt5677_sto3_dmic_mux = 1407 SOC_DAPM_ENUM("Stereo3 DMIC Source", rt5677_stereo3_dmic_enum); 1408 1409 static SOC_ENUM_SINGLE_DECL( 1410 rt5677_stereo4_dmic_enum, RT5677_STO4_ADC_MIXER, 1411 RT5677_SEL_STO4_DMIC_SFT, rt5677_dmic_src); 1412 1413 static const struct snd_kcontrol_new rt5677_sto4_dmic_mux = 1414 SOC_DAPM_ENUM("Stereo4 DMIC Source", rt5677_stereo4_dmic_enum); 1415 1416 /* Stereo2 ADC Source */ /* MX-26 [0] */ 1417 static const char * const rt5677_stereo2_adc_lr_src[] = { 1418 "L", "LR" 1419 }; 1420 1421 static SOC_ENUM_SINGLE_DECL( 1422 rt5677_stereo2_adc_lr_enum, RT5677_STO2_ADC_MIXER, 1423 RT5677_SEL_STO2_LR_MIX_SFT, rt5677_stereo2_adc_lr_src); 1424 1425 static const struct snd_kcontrol_new rt5677_sto2_adc_lr_mux = 1426 SOC_DAPM_ENUM("Stereo2 ADC LR Source", rt5677_stereo2_adc_lr_enum); 1427 1428 /* Stereo1 ADC Source 1 */ /* MX-27 MX26 MX25 [13:12] */ 1429 static const char * const rt5677_stereo_adc1_src[] = { 1430 "DD MIX1", "ADC1/2", "Stereo DAC MIX" 1431 }; 1432 1433 static SOC_ENUM_SINGLE_DECL( 1434 rt5677_stereo1_adc1_enum, RT5677_STO1_ADC_MIXER, 1435 RT5677_SEL_STO1_ADC1_SFT, rt5677_stereo_adc1_src); 1436 1437 static const struct snd_kcontrol_new rt5677_sto1_adc1_mux = 1438 SOC_DAPM_ENUM("Stereo1 ADC1 Source", rt5677_stereo1_adc1_enum); 1439 1440 static SOC_ENUM_SINGLE_DECL( 1441 rt5677_stereo2_adc1_enum, RT5677_STO2_ADC_MIXER, 1442 RT5677_SEL_STO2_ADC1_SFT, rt5677_stereo_adc1_src); 1443 1444 static const struct snd_kcontrol_new rt5677_sto2_adc1_mux = 1445 SOC_DAPM_ENUM("Stereo2 ADC1 Source", rt5677_stereo2_adc1_enum); 1446 1447 static SOC_ENUM_SINGLE_DECL( 1448 rt5677_stereo3_adc1_enum, RT5677_STO3_ADC_MIXER, 1449 RT5677_SEL_STO3_ADC1_SFT, rt5677_stereo_adc1_src); 1450 1451 static const struct snd_kcontrol_new rt5677_sto3_adc1_mux = 1452 SOC_DAPM_ENUM("Stereo3 ADC1 Source", rt5677_stereo3_adc1_enum); 1453 1454 /* Mono ADC Left Source 2 */ /* MX-28 [11:10] */ 1455 static const char * const rt5677_mono_adc2_l_src[] = { 1456 "DD MIX1L", "DMIC", "MONO DAC MIXL" 1457 }; 1458 1459 static SOC_ENUM_SINGLE_DECL( 1460 rt5677_mono_adc2_l_enum, RT5677_MONO_ADC_MIXER, 1461 RT5677_SEL_MONO_ADC_L2_SFT, rt5677_mono_adc2_l_src); 1462 1463 static const struct snd_kcontrol_new rt5677_mono_adc2_l_mux = 1464 SOC_DAPM_ENUM("Mono ADC2 L Source", rt5677_mono_adc2_l_enum); 1465 1466 /* Mono ADC Left Source 1 */ /* MX-28 [13:12] */ 1467 static const char * const rt5677_mono_adc1_l_src[] = { 1468 "DD MIX1L", "ADC1", "MONO DAC MIXL" 1469 }; 1470 1471 static SOC_ENUM_SINGLE_DECL( 1472 rt5677_mono_adc1_l_enum, RT5677_MONO_ADC_MIXER, 1473 RT5677_SEL_MONO_ADC_L1_SFT, rt5677_mono_adc1_l_src); 1474 1475 static const struct snd_kcontrol_new rt5677_mono_adc1_l_mux = 1476 SOC_DAPM_ENUM("Mono ADC1 L Source", rt5677_mono_adc1_l_enum); 1477 1478 /* Mono ADC Right Source 2 */ /* MX-28 [3:2] */ 1479 static const char * const rt5677_mono_adc2_r_src[] = { 1480 "DD MIX1R", "DMIC", "MONO DAC MIXR" 1481 }; 1482 1483 static SOC_ENUM_SINGLE_DECL( 1484 rt5677_mono_adc2_r_enum, RT5677_MONO_ADC_MIXER, 1485 RT5677_SEL_MONO_ADC_R2_SFT, rt5677_mono_adc2_r_src); 1486 1487 static const struct snd_kcontrol_new rt5677_mono_adc2_r_mux = 1488 SOC_DAPM_ENUM("Mono ADC2 R Source", rt5677_mono_adc2_r_enum); 1489 1490 /* Mono ADC Right Source 1 */ /* MX-28 [5:4] */ 1491 static const char * const rt5677_mono_adc1_r_src[] = { 1492 "DD MIX1R", "ADC2", "MONO DAC MIXR" 1493 }; 1494 1495 static SOC_ENUM_SINGLE_DECL( 1496 rt5677_mono_adc1_r_enum, RT5677_MONO_ADC_MIXER, 1497 RT5677_SEL_MONO_ADC_R1_SFT, rt5677_mono_adc1_r_src); 1498 1499 static const struct snd_kcontrol_new rt5677_mono_adc1_r_mux = 1500 SOC_DAPM_ENUM("Mono ADC1 R Source", rt5677_mono_adc1_r_enum); 1501 1502 /* Stereo4 ADC Source 2 */ /* MX-24 [11:10] */ 1503 static const char * const rt5677_stereo4_adc2_src[] = { 1504 "DD MIX1", "DMIC", "DD MIX2" 1505 }; 1506 1507 static SOC_ENUM_SINGLE_DECL( 1508 rt5677_stereo4_adc2_enum, RT5677_STO4_ADC_MIXER, 1509 RT5677_SEL_STO4_ADC2_SFT, rt5677_stereo4_adc2_src); 1510 1511 static const struct snd_kcontrol_new rt5677_sto4_adc2_mux = 1512 SOC_DAPM_ENUM("Stereo4 ADC2 Source", rt5677_stereo4_adc2_enum); 1513 1514 1515 /* Stereo4 ADC Source 1 */ /* MX-24 [13:12] */ 1516 static const char * const rt5677_stereo4_adc1_src[] = { 1517 "DD MIX1", "ADC1/2", "DD MIX2" 1518 }; 1519 1520 static SOC_ENUM_SINGLE_DECL( 1521 rt5677_stereo4_adc1_enum, RT5677_STO4_ADC_MIXER, 1522 RT5677_SEL_STO4_ADC1_SFT, rt5677_stereo4_adc1_src); 1523 1524 static const struct snd_kcontrol_new rt5677_sto4_adc1_mux = 1525 SOC_DAPM_ENUM("Stereo4 ADC1 Source", rt5677_stereo4_adc1_enum); 1526 1527 /* InBound0/1 Source */ /* MX-A3 [14:12] */ 1528 static const char * const rt5677_inbound01_src[] = { 1529 "IF1 DAC 01", "IF2 DAC 01", "SLB DAC 01", "STO1 ADC MIX", 1530 "VAD ADC/DAC1 FS" 1531 }; 1532 1533 static SOC_ENUM_SINGLE_DECL( 1534 rt5677_inbound01_enum, RT5677_DSP_INB_CTRL1, 1535 RT5677_IB01_SRC_SFT, rt5677_inbound01_src); 1536 1537 static const struct snd_kcontrol_new rt5677_ib01_src_mux = 1538 SOC_DAPM_ENUM("InBound0/1 Source", rt5677_inbound01_enum); 1539 1540 /* InBound2/3 Source */ /* MX-A3 [10:8] */ 1541 static const char * const rt5677_inbound23_src[] = { 1542 "IF1 DAC 23", "IF2 DAC 23", "SLB DAC 23", "STO2 ADC MIX", 1543 "DAC1 FS", "IF4 DAC" 1544 }; 1545 1546 static SOC_ENUM_SINGLE_DECL( 1547 rt5677_inbound23_enum, RT5677_DSP_INB_CTRL1, 1548 RT5677_IB23_SRC_SFT, rt5677_inbound23_src); 1549 1550 static const struct snd_kcontrol_new rt5677_ib23_src_mux = 1551 SOC_DAPM_ENUM("InBound2/3 Source", rt5677_inbound23_enum); 1552 1553 /* InBound4/5 Source */ /* MX-A3 [6:4] */ 1554 static const char * const rt5677_inbound45_src[] = { 1555 "IF1 DAC 45", "IF2 DAC 45", "SLB DAC 45", "STO3 ADC MIX", 1556 "IF3 DAC" 1557 }; 1558 1559 static SOC_ENUM_SINGLE_DECL( 1560 rt5677_inbound45_enum, RT5677_DSP_INB_CTRL1, 1561 RT5677_IB45_SRC_SFT, rt5677_inbound45_src); 1562 1563 static const struct snd_kcontrol_new rt5677_ib45_src_mux = 1564 SOC_DAPM_ENUM("InBound4/5 Source", rt5677_inbound45_enum); 1565 1566 /* InBound6 Source */ /* MX-A3 [2:0] */ 1567 static const char * const rt5677_inbound6_src[] = { 1568 "IF1 DAC 6", "IF2 DAC 6", "SLB DAC 6", "STO4 ADC MIX L", 1569 "IF4 DAC L", "STO1 ADC MIX L", "STO2 ADC MIX L", "STO3 ADC MIX L" 1570 }; 1571 1572 static SOC_ENUM_SINGLE_DECL( 1573 rt5677_inbound6_enum, RT5677_DSP_INB_CTRL1, 1574 RT5677_IB6_SRC_SFT, rt5677_inbound6_src); 1575 1576 static const struct snd_kcontrol_new rt5677_ib6_src_mux = 1577 SOC_DAPM_ENUM("InBound6 Source", rt5677_inbound6_enum); 1578 1579 /* InBound7 Source */ /* MX-A4 [14:12] */ 1580 static const char * const rt5677_inbound7_src[] = { 1581 "IF1 DAC 7", "IF2 DAC 7", "SLB DAC 7", "STO4 ADC MIX R", 1582 "IF4 DAC R", "STO1 ADC MIX R", "STO2 ADC MIX R", "STO3 ADC MIX R" 1583 }; 1584 1585 static SOC_ENUM_SINGLE_DECL( 1586 rt5677_inbound7_enum, RT5677_DSP_INB_CTRL2, 1587 RT5677_IB7_SRC_SFT, rt5677_inbound7_src); 1588 1589 static const struct snd_kcontrol_new rt5677_ib7_src_mux = 1590 SOC_DAPM_ENUM("InBound7 Source", rt5677_inbound7_enum); 1591 1592 /* InBound8 Source */ /* MX-A4 [10:8] */ 1593 static const char * const rt5677_inbound8_src[] = { 1594 "STO1 ADC MIX L", "STO2 ADC MIX L", "STO3 ADC MIX L", "STO4 ADC MIX L", 1595 "MONO ADC MIX L", "DACL1 FS" 1596 }; 1597 1598 static SOC_ENUM_SINGLE_DECL( 1599 rt5677_inbound8_enum, RT5677_DSP_INB_CTRL2, 1600 RT5677_IB8_SRC_SFT, rt5677_inbound8_src); 1601 1602 static const struct snd_kcontrol_new rt5677_ib8_src_mux = 1603 SOC_DAPM_ENUM("InBound8 Source", rt5677_inbound8_enum); 1604 1605 /* InBound9 Source */ /* MX-A4 [6:4] */ 1606 static const char * const rt5677_inbound9_src[] = { 1607 "STO1 ADC MIX R", "STO2 ADC MIX R", "STO3 ADC MIX R", "STO4 ADC MIX R", 1608 "MONO ADC MIX R", "DACR1 FS", "DAC1 FS" 1609 }; 1610 1611 static SOC_ENUM_SINGLE_DECL( 1612 rt5677_inbound9_enum, RT5677_DSP_INB_CTRL2, 1613 RT5677_IB9_SRC_SFT, rt5677_inbound9_src); 1614 1615 static const struct snd_kcontrol_new rt5677_ib9_src_mux = 1616 SOC_DAPM_ENUM("InBound9 Source", rt5677_inbound9_enum); 1617 1618 /* VAD Source */ /* MX-9F [6:4] */ 1619 static const char * const rt5677_vad_src[] = { 1620 "STO1 ADC MIX L", "MONO ADC MIX L", "MONO ADC MIX R", "STO2 ADC MIX L", 1621 "STO3 ADC MIX L" 1622 }; 1623 1624 static SOC_ENUM_SINGLE_DECL( 1625 rt5677_vad_enum, RT5677_VAD_CTRL4, 1626 RT5677_VAD_SRC_SFT, rt5677_vad_src); 1627 1628 static const struct snd_kcontrol_new rt5677_vad_src_mux = 1629 SOC_DAPM_ENUM("VAD Source", rt5677_vad_enum); 1630 1631 /* Sidetone Source */ /* MX-13 [11:9] */ 1632 static const char * const rt5677_sidetone_src[] = { 1633 "DMIC1 L", "DMIC2 L", "DMIC3 L", "DMIC4 L", "ADC1", "ADC2" 1634 }; 1635 1636 static SOC_ENUM_SINGLE_DECL( 1637 rt5677_sidetone_enum, RT5677_SIDETONE_CTRL, 1638 RT5677_ST_SEL_SFT, rt5677_sidetone_src); 1639 1640 static const struct snd_kcontrol_new rt5677_sidetone_mux = 1641 SOC_DAPM_ENUM("Sidetone Source", rt5677_sidetone_enum); 1642 1643 /* DAC1/2 Source */ /* MX-15 [1:0] */ 1644 static const char * const rt5677_dac12_src[] = { 1645 "STO1 DAC MIX", "MONO DAC MIX", "DD MIX1", "DD MIX2" 1646 }; 1647 1648 static SOC_ENUM_SINGLE_DECL( 1649 rt5677_dac12_enum, RT5677_ANA_DAC1_2_3_SRC, 1650 RT5677_ANA_DAC1_2_SRC_SEL_SFT, rt5677_dac12_src); 1651 1652 static const struct snd_kcontrol_new rt5677_dac12_mux = 1653 SOC_DAPM_ENUM("Analog DAC1/2 Source", rt5677_dac12_enum); 1654 1655 /* DAC3 Source */ /* MX-15 [5:4] */ 1656 static const char * const rt5677_dac3_src[] = { 1657 "MONO DAC MIXL", "MONO DAC MIXR", "DD MIX1L", "DD MIX2L" 1658 }; 1659 1660 static SOC_ENUM_SINGLE_DECL( 1661 rt5677_dac3_enum, RT5677_ANA_DAC1_2_3_SRC, 1662 RT5677_ANA_DAC3_SRC_SEL_SFT, rt5677_dac3_src); 1663 1664 static const struct snd_kcontrol_new rt5677_dac3_mux = 1665 SOC_DAPM_ENUM("Analog DAC3 Source", rt5677_dac3_enum); 1666 1667 /* PDM channel Source */ /* MX-31 [13:12][9:8][5:4][1:0] */ 1668 static const char * const rt5677_pdm_src[] = { 1669 "STO1 DAC MIX", "MONO DAC MIX", "DD MIX1", "DD MIX2" 1670 }; 1671 1672 static SOC_ENUM_SINGLE_DECL( 1673 rt5677_pdm1_l_enum, RT5677_PDM_OUT_CTRL, 1674 RT5677_SEL_PDM1_L_SFT, rt5677_pdm_src); 1675 1676 static const struct snd_kcontrol_new rt5677_pdm1_l_mux = 1677 SOC_DAPM_ENUM("PDM1 Source", rt5677_pdm1_l_enum); 1678 1679 static SOC_ENUM_SINGLE_DECL( 1680 rt5677_pdm2_l_enum, RT5677_PDM_OUT_CTRL, 1681 RT5677_SEL_PDM2_L_SFT, rt5677_pdm_src); 1682 1683 static const struct snd_kcontrol_new rt5677_pdm2_l_mux = 1684 SOC_DAPM_ENUM("PDM2 Source", rt5677_pdm2_l_enum); 1685 1686 static SOC_ENUM_SINGLE_DECL( 1687 rt5677_pdm1_r_enum, RT5677_PDM_OUT_CTRL, 1688 RT5677_SEL_PDM1_R_SFT, rt5677_pdm_src); 1689 1690 static const struct snd_kcontrol_new rt5677_pdm1_r_mux = 1691 SOC_DAPM_ENUM("PDM1 Source", rt5677_pdm1_r_enum); 1692 1693 static SOC_ENUM_SINGLE_DECL( 1694 rt5677_pdm2_r_enum, RT5677_PDM_OUT_CTRL, 1695 RT5677_SEL_PDM2_R_SFT, rt5677_pdm_src); 1696 1697 static const struct snd_kcontrol_new rt5677_pdm2_r_mux = 1698 SOC_DAPM_ENUM("PDM2 Source", rt5677_pdm2_r_enum); 1699 1700 /* TDM IF1/2 SLB ADC1 Data Selection */ /* MX-3C MX-41 [5:4] MX-08 [1:0] */ 1701 static const char * const rt5677_if12_adc1_src[] = { 1702 "STO1 ADC MIX", "OB01", "VAD ADC" 1703 }; 1704 1705 static SOC_ENUM_SINGLE_DECL( 1706 rt5677_if1_adc1_enum, RT5677_TDM1_CTRL2, 1707 RT5677_IF1_ADC1_SFT, rt5677_if12_adc1_src); 1708 1709 static const struct snd_kcontrol_new rt5677_if1_adc1_mux = 1710 SOC_DAPM_ENUM("IF1 ADC1 Source", rt5677_if1_adc1_enum); 1711 1712 static SOC_ENUM_SINGLE_DECL( 1713 rt5677_if2_adc1_enum, RT5677_TDM2_CTRL2, 1714 RT5677_IF2_ADC1_SFT, rt5677_if12_adc1_src); 1715 1716 static const struct snd_kcontrol_new rt5677_if2_adc1_mux = 1717 SOC_DAPM_ENUM("IF2 ADC1 Source", rt5677_if2_adc1_enum); 1718 1719 static SOC_ENUM_SINGLE_DECL( 1720 rt5677_slb_adc1_enum, RT5677_SLIMBUS_RX, 1721 RT5677_SLB_ADC1_SFT, rt5677_if12_adc1_src); 1722 1723 static const struct snd_kcontrol_new rt5677_slb_adc1_mux = 1724 SOC_DAPM_ENUM("SLB ADC1 Source", rt5677_slb_adc1_enum); 1725 1726 /* TDM IF1/2 SLB ADC2 Data Selection */ /* MX-3C MX-41 [7:6] MX-08 [3:2] */ 1727 static const char * const rt5677_if12_adc2_src[] = { 1728 "STO2 ADC MIX", "OB23" 1729 }; 1730 1731 static SOC_ENUM_SINGLE_DECL( 1732 rt5677_if1_adc2_enum, RT5677_TDM1_CTRL2, 1733 RT5677_IF1_ADC2_SFT, rt5677_if12_adc2_src); 1734 1735 static const struct snd_kcontrol_new rt5677_if1_adc2_mux = 1736 SOC_DAPM_ENUM("IF1 ADC2 Source", rt5677_if1_adc2_enum); 1737 1738 static SOC_ENUM_SINGLE_DECL( 1739 rt5677_if2_adc2_enum, RT5677_TDM2_CTRL2, 1740 RT5677_IF2_ADC2_SFT, rt5677_if12_adc2_src); 1741 1742 static const struct snd_kcontrol_new rt5677_if2_adc2_mux = 1743 SOC_DAPM_ENUM("IF2 ADC2 Source", rt5677_if2_adc2_enum); 1744 1745 static SOC_ENUM_SINGLE_DECL( 1746 rt5677_slb_adc2_enum, RT5677_SLIMBUS_RX, 1747 RT5677_SLB_ADC2_SFT, rt5677_if12_adc2_src); 1748 1749 static const struct snd_kcontrol_new rt5677_slb_adc2_mux = 1750 SOC_DAPM_ENUM("SLB ADC2 Source", rt5677_slb_adc2_enum); 1751 1752 /* TDM IF1/2 SLB ADC3 Data Selection */ /* MX-3C MX-41 [9:8] MX-08 [5:4] */ 1753 static const char * const rt5677_if12_adc3_src[] = { 1754 "STO3 ADC MIX", "MONO ADC MIX", "OB45" 1755 }; 1756 1757 static SOC_ENUM_SINGLE_DECL( 1758 rt5677_if1_adc3_enum, RT5677_TDM1_CTRL2, 1759 RT5677_IF1_ADC3_SFT, rt5677_if12_adc3_src); 1760 1761 static const struct snd_kcontrol_new rt5677_if1_adc3_mux = 1762 SOC_DAPM_ENUM("IF1 ADC3 Source", rt5677_if1_adc3_enum); 1763 1764 static SOC_ENUM_SINGLE_DECL( 1765 rt5677_if2_adc3_enum, RT5677_TDM2_CTRL2, 1766 RT5677_IF2_ADC3_SFT, rt5677_if12_adc3_src); 1767 1768 static const struct snd_kcontrol_new rt5677_if2_adc3_mux = 1769 SOC_DAPM_ENUM("IF2 ADC3 Source", rt5677_if2_adc3_enum); 1770 1771 static SOC_ENUM_SINGLE_DECL( 1772 rt5677_slb_adc3_enum, RT5677_SLIMBUS_RX, 1773 RT5677_SLB_ADC3_SFT, rt5677_if12_adc3_src); 1774 1775 static const struct snd_kcontrol_new rt5677_slb_adc3_mux = 1776 SOC_DAPM_ENUM("SLB ADC3 Source", rt5677_slb_adc3_enum); 1777 1778 /* TDM IF1/2 SLB ADC4 Data Selection */ /* MX-3C MX-41 [11:10] MX-08 [7:6] */ 1779 static const char * const rt5677_if12_adc4_src[] = { 1780 "STO4 ADC MIX", "OB67", "OB01" 1781 }; 1782 1783 static SOC_ENUM_SINGLE_DECL( 1784 rt5677_if1_adc4_enum, RT5677_TDM1_CTRL2, 1785 RT5677_IF1_ADC4_SFT, rt5677_if12_adc4_src); 1786 1787 static const struct snd_kcontrol_new rt5677_if1_adc4_mux = 1788 SOC_DAPM_ENUM("IF1 ADC4 Source", rt5677_if1_adc4_enum); 1789 1790 static SOC_ENUM_SINGLE_DECL( 1791 rt5677_if2_adc4_enum, RT5677_TDM2_CTRL2, 1792 RT5677_IF2_ADC4_SFT, rt5677_if12_adc4_src); 1793 1794 static const struct snd_kcontrol_new rt5677_if2_adc4_mux = 1795 SOC_DAPM_ENUM("IF2 ADC4 Source", rt5677_if2_adc4_enum); 1796 1797 static SOC_ENUM_SINGLE_DECL( 1798 rt5677_slb_adc4_enum, RT5677_SLIMBUS_RX, 1799 RT5677_SLB_ADC4_SFT, rt5677_if12_adc4_src); 1800 1801 static const struct snd_kcontrol_new rt5677_slb_adc4_mux = 1802 SOC_DAPM_ENUM("SLB ADC4 Source", rt5677_slb_adc4_enum); 1803 1804 /* Interface3/4 ADC Data Input */ /* MX-2F [3:0] MX-30 [7:4] */ 1805 static const char * const rt5677_if34_adc_src[] = { 1806 "STO1 ADC MIX", "STO2 ADC MIX", "STO3 ADC MIX", "STO4 ADC MIX", 1807 "MONO ADC MIX", "OB01", "OB23", "VAD ADC" 1808 }; 1809 1810 static SOC_ENUM_SINGLE_DECL( 1811 rt5677_if3_adc_enum, RT5677_IF3_DATA, 1812 RT5677_IF3_ADC_IN_SFT, rt5677_if34_adc_src); 1813 1814 static const struct snd_kcontrol_new rt5677_if3_adc_mux = 1815 SOC_DAPM_ENUM("IF3 ADC Source", rt5677_if3_adc_enum); 1816 1817 static SOC_ENUM_SINGLE_DECL( 1818 rt5677_if4_adc_enum, RT5677_IF4_DATA, 1819 RT5677_IF4_ADC_IN_SFT, rt5677_if34_adc_src); 1820 1821 static const struct snd_kcontrol_new rt5677_if4_adc_mux = 1822 SOC_DAPM_ENUM("IF4 ADC Source", rt5677_if4_adc_enum); 1823 1824 /* TDM IF1/2 ADC Data Selection */ /* MX-3B MX-40 [7:6][5:4][3:2][1:0] */ 1825 static const char * const rt5677_if12_adc_swap_src[] = { 1826 "L/R", "R/L", "L/L", "R/R" 1827 }; 1828 1829 static SOC_ENUM_SINGLE_DECL( 1830 rt5677_if1_adc1_swap_enum, RT5677_TDM1_CTRL1, 1831 RT5677_IF1_ADC1_SWAP_SFT, rt5677_if12_adc_swap_src); 1832 1833 static const struct snd_kcontrol_new rt5677_if1_adc1_swap_mux = 1834 SOC_DAPM_ENUM("IF1 ADC1 Swap Source", rt5677_if1_adc1_swap_enum); 1835 1836 static SOC_ENUM_SINGLE_DECL( 1837 rt5677_if1_adc2_swap_enum, RT5677_TDM1_CTRL1, 1838 RT5677_IF1_ADC2_SWAP_SFT, rt5677_if12_adc_swap_src); 1839 1840 static const struct snd_kcontrol_new rt5677_if1_adc2_swap_mux = 1841 SOC_DAPM_ENUM("IF1 ADC2 Swap Source", rt5677_if1_adc2_swap_enum); 1842 1843 static SOC_ENUM_SINGLE_DECL( 1844 rt5677_if1_adc3_swap_enum, RT5677_TDM1_CTRL1, 1845 RT5677_IF1_ADC3_SWAP_SFT, rt5677_if12_adc_swap_src); 1846 1847 static const struct snd_kcontrol_new rt5677_if1_adc3_swap_mux = 1848 SOC_DAPM_ENUM("IF1 ADC3 Swap Source", rt5677_if1_adc3_swap_enum); 1849 1850 static SOC_ENUM_SINGLE_DECL( 1851 rt5677_if1_adc4_swap_enum, RT5677_TDM1_CTRL1, 1852 RT5677_IF1_ADC4_SWAP_SFT, rt5677_if12_adc_swap_src); 1853 1854 static const struct snd_kcontrol_new rt5677_if1_adc4_swap_mux = 1855 SOC_DAPM_ENUM("IF1 ADC4 Swap Source", rt5677_if1_adc4_swap_enum); 1856 1857 static SOC_ENUM_SINGLE_DECL( 1858 rt5677_if2_adc1_swap_enum, RT5677_TDM2_CTRL1, 1859 RT5677_IF1_ADC2_SWAP_SFT, rt5677_if12_adc_swap_src); 1860 1861 static const struct snd_kcontrol_new rt5677_if2_adc1_swap_mux = 1862 SOC_DAPM_ENUM("IF1 ADC2 Swap Source", rt5677_if2_adc1_swap_enum); 1863 1864 static SOC_ENUM_SINGLE_DECL( 1865 rt5677_if2_adc2_swap_enum, RT5677_TDM2_CTRL1, 1866 RT5677_IF2_ADC2_SWAP_SFT, rt5677_if12_adc_swap_src); 1867 1868 static const struct snd_kcontrol_new rt5677_if2_adc2_swap_mux = 1869 SOC_DAPM_ENUM("IF2 ADC2 Swap Source", rt5677_if2_adc2_swap_enum); 1870 1871 static SOC_ENUM_SINGLE_DECL( 1872 rt5677_if2_adc3_swap_enum, RT5677_TDM2_CTRL1, 1873 RT5677_IF2_ADC3_SWAP_SFT, rt5677_if12_adc_swap_src); 1874 1875 static const struct snd_kcontrol_new rt5677_if2_adc3_swap_mux = 1876 SOC_DAPM_ENUM("IF2 ADC3 Swap Source", rt5677_if2_adc3_swap_enum); 1877 1878 static SOC_ENUM_SINGLE_DECL( 1879 rt5677_if2_adc4_swap_enum, RT5677_TDM2_CTRL1, 1880 RT5677_IF2_ADC4_SWAP_SFT, rt5677_if12_adc_swap_src); 1881 1882 static const struct snd_kcontrol_new rt5677_if2_adc4_swap_mux = 1883 SOC_DAPM_ENUM("IF2 ADC4 Swap Source", rt5677_if2_adc4_swap_enum); 1884 1885 /* TDM IF1 ADC Data Selection */ /* MX-3C [2:0] */ 1886 static const char * const rt5677_if1_adc_tdm_swap_src[] = { 1887 "1/2/3/4", "2/1/3/4", "2/3/1/4", "4/1/2/3", "1/3/2/4", "1/4/2/3", 1888 "3/1/2/4", "3/4/1/2" 1889 }; 1890 1891 static SOC_ENUM_SINGLE_DECL( 1892 rt5677_if1_adc_tdm_swap_enum, RT5677_TDM1_CTRL2, 1893 RT5677_IF1_ADC_CTRL_SFT, rt5677_if1_adc_tdm_swap_src); 1894 1895 static const struct snd_kcontrol_new rt5677_if1_adc_tdm_swap_mux = 1896 SOC_DAPM_ENUM("IF1 ADC TDM Swap Source", rt5677_if1_adc_tdm_swap_enum); 1897 1898 /* TDM IF2 ADC Data Selection */ /* MX-41[2:0] */ 1899 static const char * const rt5677_if2_adc_tdm_swap_src[] = { 1900 "1/2/3/4", "2/1/3/4", "3/1/2/4", "4/1/2/3", "1/3/2/4", "1/4/2/3", 1901 "2/3/1/4", "3/4/1/2" 1902 }; 1903 1904 static SOC_ENUM_SINGLE_DECL( 1905 rt5677_if2_adc_tdm_swap_enum, RT5677_TDM2_CTRL2, 1906 RT5677_IF2_ADC_CTRL_SFT, rt5677_if2_adc_tdm_swap_src); 1907 1908 static const struct snd_kcontrol_new rt5677_if2_adc_tdm_swap_mux = 1909 SOC_DAPM_ENUM("IF2 ADC TDM Swap Source", rt5677_if2_adc_tdm_swap_enum); 1910 1911 /* TDM IF1/2 DAC Data Selection */ /* MX-3E[14:12][10:8][6:4][2:0] 1912 MX-3F[14:12][10:8][6:4][2:0] 1913 MX-43[14:12][10:8][6:4][2:0] 1914 MX-44[14:12][10:8][6:4][2:0] */ 1915 static const char * const rt5677_if12_dac_tdm_sel_src[] = { 1916 "Slot0", "Slot1", "Slot2", "Slot3", "Slot4", "Slot5", "Slot6", "Slot7" 1917 }; 1918 1919 static SOC_ENUM_SINGLE_DECL( 1920 rt5677_if1_dac0_tdm_sel_enum, RT5677_TDM1_CTRL4, 1921 RT5677_IF1_DAC0_SFT, rt5677_if12_dac_tdm_sel_src); 1922 1923 static const struct snd_kcontrol_new rt5677_if1_dac0_tdm_sel_mux = 1924 SOC_DAPM_ENUM("IF1 DAC0 TDM Source", rt5677_if1_dac0_tdm_sel_enum); 1925 1926 static SOC_ENUM_SINGLE_DECL( 1927 rt5677_if1_dac1_tdm_sel_enum, RT5677_TDM1_CTRL4, 1928 RT5677_IF1_DAC1_SFT, rt5677_if12_dac_tdm_sel_src); 1929 1930 static const struct snd_kcontrol_new rt5677_if1_dac1_tdm_sel_mux = 1931 SOC_DAPM_ENUM("IF1 DAC1 TDM Source", rt5677_if1_dac1_tdm_sel_enum); 1932 1933 static SOC_ENUM_SINGLE_DECL( 1934 rt5677_if1_dac2_tdm_sel_enum, RT5677_TDM1_CTRL4, 1935 RT5677_IF1_DAC2_SFT, rt5677_if12_dac_tdm_sel_src); 1936 1937 static const struct snd_kcontrol_new rt5677_if1_dac2_tdm_sel_mux = 1938 SOC_DAPM_ENUM("IF1 DAC2 TDM Source", rt5677_if1_dac2_tdm_sel_enum); 1939 1940 static SOC_ENUM_SINGLE_DECL( 1941 rt5677_if1_dac3_tdm_sel_enum, RT5677_TDM1_CTRL4, 1942 RT5677_IF1_DAC3_SFT, rt5677_if12_dac_tdm_sel_src); 1943 1944 static const struct snd_kcontrol_new rt5677_if1_dac3_tdm_sel_mux = 1945 SOC_DAPM_ENUM("IF1 DAC3 TDM Source", rt5677_if1_dac3_tdm_sel_enum); 1946 1947 static SOC_ENUM_SINGLE_DECL( 1948 rt5677_if1_dac4_tdm_sel_enum, RT5677_TDM1_CTRL5, 1949 RT5677_IF1_DAC4_SFT, rt5677_if12_dac_tdm_sel_src); 1950 1951 static const struct snd_kcontrol_new rt5677_if1_dac4_tdm_sel_mux = 1952 SOC_DAPM_ENUM("IF1 DAC4 TDM Source", rt5677_if1_dac4_tdm_sel_enum); 1953 1954 static SOC_ENUM_SINGLE_DECL( 1955 rt5677_if1_dac5_tdm_sel_enum, RT5677_TDM1_CTRL5, 1956 RT5677_IF1_DAC5_SFT, rt5677_if12_dac_tdm_sel_src); 1957 1958 static const struct snd_kcontrol_new rt5677_if1_dac5_tdm_sel_mux = 1959 SOC_DAPM_ENUM("IF1 DAC5 TDM Source", rt5677_if1_dac5_tdm_sel_enum); 1960 1961 static SOC_ENUM_SINGLE_DECL( 1962 rt5677_if1_dac6_tdm_sel_enum, RT5677_TDM1_CTRL5, 1963 RT5677_IF1_DAC6_SFT, rt5677_if12_dac_tdm_sel_src); 1964 1965 static const struct snd_kcontrol_new rt5677_if1_dac6_tdm_sel_mux = 1966 SOC_DAPM_ENUM("IF1 DAC6 TDM Source", rt5677_if1_dac6_tdm_sel_enum); 1967 1968 static SOC_ENUM_SINGLE_DECL( 1969 rt5677_if1_dac7_tdm_sel_enum, RT5677_TDM1_CTRL5, 1970 RT5677_IF1_DAC7_SFT, rt5677_if12_dac_tdm_sel_src); 1971 1972 static const struct snd_kcontrol_new rt5677_if1_dac7_tdm_sel_mux = 1973 SOC_DAPM_ENUM("IF1 DAC7 TDM Source", rt5677_if1_dac7_tdm_sel_enum); 1974 1975 static SOC_ENUM_SINGLE_DECL( 1976 rt5677_if2_dac0_tdm_sel_enum, RT5677_TDM2_CTRL4, 1977 RT5677_IF2_DAC0_SFT, rt5677_if12_dac_tdm_sel_src); 1978 1979 static const struct snd_kcontrol_new rt5677_if2_dac0_tdm_sel_mux = 1980 SOC_DAPM_ENUM("IF2 DAC0 TDM Source", rt5677_if2_dac0_tdm_sel_enum); 1981 1982 static SOC_ENUM_SINGLE_DECL( 1983 rt5677_if2_dac1_tdm_sel_enum, RT5677_TDM2_CTRL4, 1984 RT5677_IF2_DAC1_SFT, rt5677_if12_dac_tdm_sel_src); 1985 1986 static const struct snd_kcontrol_new rt5677_if2_dac1_tdm_sel_mux = 1987 SOC_DAPM_ENUM("IF2 DAC1 TDM Source", rt5677_if2_dac1_tdm_sel_enum); 1988 1989 static SOC_ENUM_SINGLE_DECL( 1990 rt5677_if2_dac2_tdm_sel_enum, RT5677_TDM2_CTRL4, 1991 RT5677_IF2_DAC2_SFT, rt5677_if12_dac_tdm_sel_src); 1992 1993 static const struct snd_kcontrol_new rt5677_if2_dac2_tdm_sel_mux = 1994 SOC_DAPM_ENUM("IF2 DAC2 TDM Source", rt5677_if2_dac2_tdm_sel_enum); 1995 1996 static SOC_ENUM_SINGLE_DECL( 1997 rt5677_if2_dac3_tdm_sel_enum, RT5677_TDM2_CTRL4, 1998 RT5677_IF2_DAC3_SFT, rt5677_if12_dac_tdm_sel_src); 1999 2000 static const struct snd_kcontrol_new rt5677_if2_dac3_tdm_sel_mux = 2001 SOC_DAPM_ENUM("IF2 DAC3 TDM Source", rt5677_if2_dac3_tdm_sel_enum); 2002 2003 static SOC_ENUM_SINGLE_DECL( 2004 rt5677_if2_dac4_tdm_sel_enum, RT5677_TDM2_CTRL5, 2005 RT5677_IF2_DAC4_SFT, rt5677_if12_dac_tdm_sel_src); 2006 2007 static const struct snd_kcontrol_new rt5677_if2_dac4_tdm_sel_mux = 2008 SOC_DAPM_ENUM("IF2 DAC4 TDM Source", rt5677_if2_dac4_tdm_sel_enum); 2009 2010 static SOC_ENUM_SINGLE_DECL( 2011 rt5677_if2_dac5_tdm_sel_enum, RT5677_TDM2_CTRL5, 2012 RT5677_IF2_DAC5_SFT, rt5677_if12_dac_tdm_sel_src); 2013 2014 static const struct snd_kcontrol_new rt5677_if2_dac5_tdm_sel_mux = 2015 SOC_DAPM_ENUM("IF2 DAC5 TDM Source", rt5677_if2_dac5_tdm_sel_enum); 2016 2017 static SOC_ENUM_SINGLE_DECL( 2018 rt5677_if2_dac6_tdm_sel_enum, RT5677_TDM2_CTRL5, 2019 RT5677_IF2_DAC6_SFT, rt5677_if12_dac_tdm_sel_src); 2020 2021 static const struct snd_kcontrol_new rt5677_if2_dac6_tdm_sel_mux = 2022 SOC_DAPM_ENUM("IF2 DAC6 TDM Source", rt5677_if2_dac6_tdm_sel_enum); 2023 2024 static SOC_ENUM_SINGLE_DECL( 2025 rt5677_if2_dac7_tdm_sel_enum, RT5677_TDM2_CTRL5, 2026 RT5677_IF2_DAC7_SFT, rt5677_if12_dac_tdm_sel_src); 2027 2028 static const struct snd_kcontrol_new rt5677_if2_dac7_tdm_sel_mux = 2029 SOC_DAPM_ENUM("IF2 DAC7 TDM Source", rt5677_if2_dac7_tdm_sel_enum); 2030 2031 static int rt5677_bst1_event(struct snd_soc_dapm_widget *w, 2032 struct snd_kcontrol *kcontrol, int event) 2033 { 2034 struct snd_soc_codec *codec = w->codec; 2035 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec); 2036 2037 switch (event) { 2038 case SND_SOC_DAPM_POST_PMU: 2039 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2, 2040 RT5677_PWR_BST1_P, RT5677_PWR_BST1_P); 2041 break; 2042 2043 case SND_SOC_DAPM_PRE_PMD: 2044 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2, 2045 RT5677_PWR_BST1_P, 0); 2046 break; 2047 2048 default: 2049 return 0; 2050 } 2051 2052 return 0; 2053 } 2054 2055 static int rt5677_bst2_event(struct snd_soc_dapm_widget *w, 2056 struct snd_kcontrol *kcontrol, int event) 2057 { 2058 struct snd_soc_codec *codec = w->codec; 2059 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec); 2060 2061 switch (event) { 2062 case SND_SOC_DAPM_POST_PMU: 2063 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2, 2064 RT5677_PWR_BST2_P, RT5677_PWR_BST2_P); 2065 break; 2066 2067 case SND_SOC_DAPM_PRE_PMD: 2068 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2, 2069 RT5677_PWR_BST2_P, 0); 2070 break; 2071 2072 default: 2073 return 0; 2074 } 2075 2076 return 0; 2077 } 2078 2079 static int rt5677_set_pll1_event(struct snd_soc_dapm_widget *w, 2080 struct snd_kcontrol *kcontrol, int event) 2081 { 2082 struct snd_soc_codec *codec = w->codec; 2083 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec); 2084 2085 switch (event) { 2086 case SND_SOC_DAPM_PRE_PMU: 2087 regmap_update_bits(rt5677->regmap, RT5677_PLL1_CTRL2, 0x2, 0x2); 2088 break; 2089 2090 case SND_SOC_DAPM_POST_PMU: 2091 regmap_update_bits(rt5677->regmap, RT5677_PLL1_CTRL2, 0x2, 0x0); 2092 break; 2093 2094 default: 2095 return 0; 2096 } 2097 2098 return 0; 2099 } 2100 2101 static int rt5677_set_pll2_event(struct snd_soc_dapm_widget *w, 2102 struct snd_kcontrol *kcontrol, int event) 2103 { 2104 struct snd_soc_codec *codec = w->codec; 2105 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec); 2106 2107 switch (event) { 2108 case SND_SOC_DAPM_PRE_PMU: 2109 regmap_update_bits(rt5677->regmap, RT5677_PLL2_CTRL2, 0x2, 0x2); 2110 break; 2111 2112 case SND_SOC_DAPM_POST_PMU: 2113 regmap_update_bits(rt5677->regmap, RT5677_PLL2_CTRL2, 0x2, 0x0); 2114 break; 2115 2116 default: 2117 return 0; 2118 } 2119 2120 return 0; 2121 } 2122 2123 static int rt5677_set_micbias1_event(struct snd_soc_dapm_widget *w, 2124 struct snd_kcontrol *kcontrol, int event) 2125 { 2126 struct snd_soc_codec *codec = w->codec; 2127 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec); 2128 2129 switch (event) { 2130 case SND_SOC_DAPM_POST_PMU: 2131 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2, 2132 RT5677_PWR_CLK_MB1 | RT5677_PWR_PP_MB1 | 2133 RT5677_PWR_CLK_MB, RT5677_PWR_CLK_MB1 | 2134 RT5677_PWR_PP_MB1 | RT5677_PWR_CLK_MB); 2135 break; 2136 2137 case SND_SOC_DAPM_PRE_PMD: 2138 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2, 2139 RT5677_PWR_CLK_MB1 | RT5677_PWR_PP_MB1 | 2140 RT5677_PWR_CLK_MB, 0); 2141 break; 2142 2143 default: 2144 return 0; 2145 } 2146 2147 return 0; 2148 } 2149 2150 static int rt5677_if1_adc_tdm_event(struct snd_soc_dapm_widget *w, 2151 struct snd_kcontrol *kcontrol, int event) 2152 { 2153 struct snd_soc_codec *codec = w->codec; 2154 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec); 2155 unsigned int value; 2156 2157 switch (event) { 2158 case SND_SOC_DAPM_PRE_PMU: 2159 regmap_read(rt5677->regmap, RT5677_TDM1_CTRL2, &value); 2160 if (value & RT5677_IF1_ADC_CTRL_MASK) 2161 regmap_update_bits(rt5677->regmap, RT5677_TDM1_CTRL1, 2162 RT5677_IF1_ADC_MODE_MASK, 2163 RT5677_IF1_ADC_MODE_TDM); 2164 break; 2165 2166 default: 2167 return 0; 2168 } 2169 2170 return 0; 2171 } 2172 2173 static int rt5677_if2_adc_tdm_event(struct snd_soc_dapm_widget *w, 2174 struct snd_kcontrol *kcontrol, int event) 2175 { 2176 struct snd_soc_codec *codec = w->codec; 2177 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec); 2178 unsigned int value; 2179 2180 switch (event) { 2181 case SND_SOC_DAPM_PRE_PMU: 2182 regmap_read(rt5677->regmap, RT5677_TDM2_CTRL2, &value); 2183 if (value & RT5677_IF2_ADC_CTRL_MASK) 2184 regmap_update_bits(rt5677->regmap, RT5677_TDM2_CTRL1, 2185 RT5677_IF2_ADC_MODE_MASK, 2186 RT5677_IF2_ADC_MODE_TDM); 2187 break; 2188 2189 default: 2190 return 0; 2191 } 2192 2193 return 0; 2194 } 2195 2196 static int rt5677_vref_event(struct snd_soc_dapm_widget *w, 2197 struct snd_kcontrol *kcontrol, int event) 2198 { 2199 struct snd_soc_codec *codec = w->codec; 2200 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec); 2201 2202 switch (event) { 2203 case SND_SOC_DAPM_POST_PMU: 2204 if (codec->dapm.bias_level != SND_SOC_BIAS_ON && 2205 !rt5677->is_vref_slow) { 2206 mdelay(20); 2207 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1, 2208 RT5677_PWR_FV1 | RT5677_PWR_FV2, 2209 RT5677_PWR_FV1 | RT5677_PWR_FV2); 2210 rt5677->is_vref_slow = true; 2211 } 2212 break; 2213 2214 default: 2215 return 0; 2216 } 2217 2218 return 0; 2219 } 2220 2221 static const struct snd_soc_dapm_widget rt5677_dapm_widgets[] = { 2222 SND_SOC_DAPM_SUPPLY("PLL1", RT5677_PWR_ANLG2, RT5677_PWR_PLL1_BIT, 2223 0, rt5677_set_pll1_event, SND_SOC_DAPM_PRE_PMU | 2224 SND_SOC_DAPM_POST_PMU), 2225 SND_SOC_DAPM_SUPPLY("PLL2", RT5677_PWR_ANLG2, RT5677_PWR_PLL2_BIT, 2226 0, rt5677_set_pll2_event, SND_SOC_DAPM_PRE_PMU | 2227 SND_SOC_DAPM_POST_PMU), 2228 2229 /* Input Side */ 2230 /* micbias */ 2231 SND_SOC_DAPM_SUPPLY("MICBIAS1", RT5677_PWR_ANLG2, RT5677_PWR_MB1_BIT, 2232 0, rt5677_set_micbias1_event, SND_SOC_DAPM_PRE_PMD | 2233 SND_SOC_DAPM_POST_PMU), 2234 2235 /* Input Lines */ 2236 SND_SOC_DAPM_INPUT("DMIC L1"), 2237 SND_SOC_DAPM_INPUT("DMIC R1"), 2238 SND_SOC_DAPM_INPUT("DMIC L2"), 2239 SND_SOC_DAPM_INPUT("DMIC R2"), 2240 SND_SOC_DAPM_INPUT("DMIC L3"), 2241 SND_SOC_DAPM_INPUT("DMIC R3"), 2242 SND_SOC_DAPM_INPUT("DMIC L4"), 2243 SND_SOC_DAPM_INPUT("DMIC R4"), 2244 2245 SND_SOC_DAPM_INPUT("IN1P"), 2246 SND_SOC_DAPM_INPUT("IN1N"), 2247 SND_SOC_DAPM_INPUT("IN2P"), 2248 SND_SOC_DAPM_INPUT("IN2N"), 2249 2250 SND_SOC_DAPM_INPUT("Haptic Generator"), 2251 2252 SND_SOC_DAPM_PGA("DMIC1", SND_SOC_NOPM, 0, 0, NULL, 0), 2253 SND_SOC_DAPM_PGA("DMIC2", SND_SOC_NOPM, 0, 0, NULL, 0), 2254 SND_SOC_DAPM_PGA("DMIC3", SND_SOC_NOPM, 0, 0, NULL, 0), 2255 SND_SOC_DAPM_PGA("DMIC4", SND_SOC_NOPM, 0, 0, NULL, 0), 2256 2257 SND_SOC_DAPM_SUPPLY("DMIC1 power", RT5677_DMIC_CTRL1, 2258 RT5677_DMIC_1_EN_SFT, 0, NULL, 0), 2259 SND_SOC_DAPM_SUPPLY("DMIC2 power", RT5677_DMIC_CTRL1, 2260 RT5677_DMIC_2_EN_SFT, 0, NULL, 0), 2261 SND_SOC_DAPM_SUPPLY("DMIC3 power", RT5677_DMIC_CTRL1, 2262 RT5677_DMIC_3_EN_SFT, 0, NULL, 0), 2263 SND_SOC_DAPM_SUPPLY("DMIC4 power", RT5677_DMIC_CTRL2, 2264 RT5677_DMIC_4_EN_SFT, 0, NULL, 0), 2265 2266 SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0, 2267 set_dmic_clk, SND_SOC_DAPM_PRE_PMU), 2268 2269 /* Boost */ 2270 SND_SOC_DAPM_PGA_E("BST1", RT5677_PWR_ANLG2, 2271 RT5677_PWR_BST1_BIT, 0, NULL, 0, rt5677_bst1_event, 2272 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU), 2273 SND_SOC_DAPM_PGA_E("BST2", RT5677_PWR_ANLG2, 2274 RT5677_PWR_BST2_BIT, 0, NULL, 0, rt5677_bst2_event, 2275 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU), 2276 2277 /* ADCs */ 2278 SND_SOC_DAPM_ADC("ADC 1", NULL, SND_SOC_NOPM, 2279 0, 0), 2280 SND_SOC_DAPM_ADC("ADC 2", NULL, SND_SOC_NOPM, 2281 0, 0), 2282 SND_SOC_DAPM_PGA("ADC 1_2", SND_SOC_NOPM, 0, 0, NULL, 0), 2283 2284 SND_SOC_DAPM_SUPPLY("ADC 1 power", RT5677_PWR_DIG1, 2285 RT5677_PWR_ADC_L_BIT, 0, NULL, 0), 2286 SND_SOC_DAPM_SUPPLY("ADC 2 power", RT5677_PWR_DIG1, 2287 RT5677_PWR_ADC_R_BIT, 0, NULL, 0), 2288 SND_SOC_DAPM_SUPPLY("ADC1 clock", RT5677_PWR_DIG1, 2289 RT5677_PWR_ADCFED1_BIT, 0, NULL, 0), 2290 SND_SOC_DAPM_SUPPLY("ADC2 clock", RT5677_PWR_DIG1, 2291 RT5677_PWR_ADCFED2_BIT, 0, NULL, 0), 2292 2293 /* ADC Mux */ 2294 SND_SOC_DAPM_MUX("Stereo1 DMIC Mux", SND_SOC_NOPM, 0, 0, 2295 &rt5677_sto1_dmic_mux), 2296 SND_SOC_DAPM_MUX("Stereo1 ADC1 Mux", SND_SOC_NOPM, 0, 0, 2297 &rt5677_sto1_adc1_mux), 2298 SND_SOC_DAPM_MUX("Stereo1 ADC2 Mux", SND_SOC_NOPM, 0, 0, 2299 &rt5677_sto1_adc2_mux), 2300 SND_SOC_DAPM_MUX("Stereo2 DMIC Mux", SND_SOC_NOPM, 0, 0, 2301 &rt5677_sto2_dmic_mux), 2302 SND_SOC_DAPM_MUX("Stereo2 ADC1 Mux", SND_SOC_NOPM, 0, 0, 2303 &rt5677_sto2_adc1_mux), 2304 SND_SOC_DAPM_MUX("Stereo2 ADC2 Mux", SND_SOC_NOPM, 0, 0, 2305 &rt5677_sto2_adc2_mux), 2306 SND_SOC_DAPM_MUX("Stereo2 ADC LR Mux", SND_SOC_NOPM, 0, 0, 2307 &rt5677_sto2_adc_lr_mux), 2308 SND_SOC_DAPM_MUX("Stereo3 DMIC Mux", SND_SOC_NOPM, 0, 0, 2309 &rt5677_sto3_dmic_mux), 2310 SND_SOC_DAPM_MUX("Stereo3 ADC1 Mux", SND_SOC_NOPM, 0, 0, 2311 &rt5677_sto3_adc1_mux), 2312 SND_SOC_DAPM_MUX("Stereo3 ADC2 Mux", SND_SOC_NOPM, 0, 0, 2313 &rt5677_sto3_adc2_mux), 2314 SND_SOC_DAPM_MUX("Stereo4 DMIC Mux", SND_SOC_NOPM, 0, 0, 2315 &rt5677_sto4_dmic_mux), 2316 SND_SOC_DAPM_MUX("Stereo4 ADC1 Mux", SND_SOC_NOPM, 0, 0, 2317 &rt5677_sto4_adc1_mux), 2318 SND_SOC_DAPM_MUX("Stereo4 ADC2 Mux", SND_SOC_NOPM, 0, 0, 2319 &rt5677_sto4_adc2_mux), 2320 SND_SOC_DAPM_MUX("Mono DMIC L Mux", SND_SOC_NOPM, 0, 0, 2321 &rt5677_mono_dmic_l_mux), 2322 SND_SOC_DAPM_MUX("Mono DMIC R Mux", SND_SOC_NOPM, 0, 0, 2323 &rt5677_mono_dmic_r_mux), 2324 SND_SOC_DAPM_MUX("Mono ADC2 L Mux", SND_SOC_NOPM, 0, 0, 2325 &rt5677_mono_adc2_l_mux), 2326 SND_SOC_DAPM_MUX("Mono ADC1 L Mux", SND_SOC_NOPM, 0, 0, 2327 &rt5677_mono_adc1_l_mux), 2328 SND_SOC_DAPM_MUX("Mono ADC1 R Mux", SND_SOC_NOPM, 0, 0, 2329 &rt5677_mono_adc1_r_mux), 2330 SND_SOC_DAPM_MUX("Mono ADC2 R Mux", SND_SOC_NOPM, 0, 0, 2331 &rt5677_mono_adc2_r_mux), 2332 2333 /* ADC Mixer */ 2334 SND_SOC_DAPM_SUPPLY("adc stereo1 filter", RT5677_PWR_DIG2, 2335 RT5677_PWR_ADC_S1F_BIT, 0, NULL, 0), 2336 SND_SOC_DAPM_SUPPLY("adc stereo2 filter", RT5677_PWR_DIG2, 2337 RT5677_PWR_ADC_S2F_BIT, 0, NULL, 0), 2338 SND_SOC_DAPM_SUPPLY("adc stereo3 filter", RT5677_PWR_DIG2, 2339 RT5677_PWR_ADC_S3F_BIT, 0, NULL, 0), 2340 SND_SOC_DAPM_SUPPLY("adc stereo4 filter", RT5677_PWR_DIG2, 2341 RT5677_PWR_ADC_S4F_BIT, 0, NULL, 0), 2342 SND_SOC_DAPM_MIXER("Sto1 ADC MIXL", SND_SOC_NOPM, 0, 0, 2343 rt5677_sto1_adc_l_mix, ARRAY_SIZE(rt5677_sto1_adc_l_mix)), 2344 SND_SOC_DAPM_MIXER("Sto1 ADC MIXR", SND_SOC_NOPM, 0, 0, 2345 rt5677_sto1_adc_r_mix, ARRAY_SIZE(rt5677_sto1_adc_r_mix)), 2346 SND_SOC_DAPM_MIXER("Sto2 ADC MIXL", SND_SOC_NOPM, 0, 0, 2347 rt5677_sto2_adc_l_mix, ARRAY_SIZE(rt5677_sto2_adc_l_mix)), 2348 SND_SOC_DAPM_MIXER("Sto2 ADC MIXR", SND_SOC_NOPM, 0, 0, 2349 rt5677_sto2_adc_r_mix, ARRAY_SIZE(rt5677_sto2_adc_r_mix)), 2350 SND_SOC_DAPM_MIXER("Sto3 ADC MIXL", SND_SOC_NOPM, 0, 0, 2351 rt5677_sto3_adc_l_mix, ARRAY_SIZE(rt5677_sto3_adc_l_mix)), 2352 SND_SOC_DAPM_MIXER("Sto3 ADC MIXR", SND_SOC_NOPM, 0, 0, 2353 rt5677_sto3_adc_r_mix, ARRAY_SIZE(rt5677_sto3_adc_r_mix)), 2354 SND_SOC_DAPM_MIXER("Sto4 ADC MIXL", SND_SOC_NOPM, 0, 0, 2355 rt5677_sto4_adc_l_mix, ARRAY_SIZE(rt5677_sto4_adc_l_mix)), 2356 SND_SOC_DAPM_MIXER("Sto4 ADC MIXR", SND_SOC_NOPM, 0, 0, 2357 rt5677_sto4_adc_r_mix, ARRAY_SIZE(rt5677_sto4_adc_r_mix)), 2358 SND_SOC_DAPM_SUPPLY("adc mono left filter", RT5677_PWR_DIG2, 2359 RT5677_PWR_ADC_MF_L_BIT, 0, NULL, 0), 2360 SND_SOC_DAPM_MIXER("Mono ADC MIXL", SND_SOC_NOPM, 0, 0, 2361 rt5677_mono_adc_l_mix, ARRAY_SIZE(rt5677_mono_adc_l_mix)), 2362 SND_SOC_DAPM_SUPPLY("adc mono right filter", RT5677_PWR_DIG2, 2363 RT5677_PWR_ADC_MF_R_BIT, 0, NULL, 0), 2364 SND_SOC_DAPM_MIXER("Mono ADC MIXR", SND_SOC_NOPM, 0, 0, 2365 rt5677_mono_adc_r_mix, ARRAY_SIZE(rt5677_mono_adc_r_mix)), 2366 2367 /* ADC PGA */ 2368 SND_SOC_DAPM_PGA("Stereo1 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0), 2369 SND_SOC_DAPM_PGA("Stereo1 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0), 2370 SND_SOC_DAPM_PGA("Stereo1 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 2371 SND_SOC_DAPM_PGA("Stereo2 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0), 2372 SND_SOC_DAPM_PGA("Stereo2 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0), 2373 SND_SOC_DAPM_PGA("Stereo2 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 2374 SND_SOC_DAPM_PGA("Stereo3 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0), 2375 SND_SOC_DAPM_PGA("Stereo3 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0), 2376 SND_SOC_DAPM_PGA("Stereo3 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 2377 SND_SOC_DAPM_PGA("Stereo4 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0), 2378 SND_SOC_DAPM_PGA("Stereo4 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0), 2379 SND_SOC_DAPM_PGA("Stereo4 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 2380 SND_SOC_DAPM_PGA("Sto2 ADC LR MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 2381 SND_SOC_DAPM_PGA("Mono ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 2382 SND_SOC_DAPM_PGA("IF1 ADC", SND_SOC_NOPM, 0, 0, NULL, 0), 2383 SND_SOC_DAPM_PGA("IF2 ADC", SND_SOC_NOPM, 0, 0, NULL, 0), 2384 2385 /* DSP */ 2386 SND_SOC_DAPM_MUX("IB9 Mux", SND_SOC_NOPM, 0, 0, 2387 &rt5677_ib9_src_mux), 2388 SND_SOC_DAPM_MUX("IB8 Mux", SND_SOC_NOPM, 0, 0, 2389 &rt5677_ib8_src_mux), 2390 SND_SOC_DAPM_MUX("IB7 Mux", SND_SOC_NOPM, 0, 0, 2391 &rt5677_ib7_src_mux), 2392 SND_SOC_DAPM_MUX("IB6 Mux", SND_SOC_NOPM, 0, 0, 2393 &rt5677_ib6_src_mux), 2394 SND_SOC_DAPM_MUX("IB45 Mux", SND_SOC_NOPM, 0, 0, 2395 &rt5677_ib45_src_mux), 2396 SND_SOC_DAPM_MUX("IB23 Mux", SND_SOC_NOPM, 0, 0, 2397 &rt5677_ib23_src_mux), 2398 SND_SOC_DAPM_MUX("IB01 Mux", SND_SOC_NOPM, 0, 0, 2399 &rt5677_ib01_src_mux), 2400 SND_SOC_DAPM_MUX("IB45 Bypass Mux", SND_SOC_NOPM, 0, 0, 2401 &rt5677_ib45_bypass_src_mux), 2402 SND_SOC_DAPM_MUX("IB23 Bypass Mux", SND_SOC_NOPM, 0, 0, 2403 &rt5677_ib23_bypass_src_mux), 2404 SND_SOC_DAPM_MUX("IB01 Bypass Mux", SND_SOC_NOPM, 0, 0, 2405 &rt5677_ib01_bypass_src_mux), 2406 SND_SOC_DAPM_MUX("OB23 Bypass Mux", SND_SOC_NOPM, 0, 0, 2407 &rt5677_ob23_bypass_src_mux), 2408 SND_SOC_DAPM_MUX("OB01 Bypass Mux", SND_SOC_NOPM, 0, 0, 2409 &rt5677_ob01_bypass_src_mux), 2410 2411 SND_SOC_DAPM_PGA("OB45", SND_SOC_NOPM, 0, 0, NULL, 0), 2412 SND_SOC_DAPM_PGA("OB67", SND_SOC_NOPM, 0, 0, NULL, 0), 2413 2414 SND_SOC_DAPM_PGA("OutBound2", SND_SOC_NOPM, 0, 0, NULL, 0), 2415 SND_SOC_DAPM_PGA("OutBound3", SND_SOC_NOPM, 0, 0, NULL, 0), 2416 SND_SOC_DAPM_PGA("OutBound4", SND_SOC_NOPM, 0, 0, NULL, 0), 2417 SND_SOC_DAPM_PGA("OutBound5", SND_SOC_NOPM, 0, 0, NULL, 0), 2418 SND_SOC_DAPM_PGA("OutBound6", SND_SOC_NOPM, 0, 0, NULL, 0), 2419 SND_SOC_DAPM_PGA("OutBound7", SND_SOC_NOPM, 0, 0, NULL, 0), 2420 2421 /* Digital Interface */ 2422 SND_SOC_DAPM_SUPPLY("I2S1", RT5677_PWR_DIG1, 2423 RT5677_PWR_I2S1_BIT, 0, NULL, 0), 2424 SND_SOC_DAPM_PGA("IF1 DAC0", SND_SOC_NOPM, 0, 0, NULL, 0), 2425 SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0), 2426 SND_SOC_DAPM_PGA("IF1 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0), 2427 SND_SOC_DAPM_PGA("IF1 DAC3", SND_SOC_NOPM, 0, 0, NULL, 0), 2428 SND_SOC_DAPM_PGA("IF1 DAC4", SND_SOC_NOPM, 0, 0, NULL, 0), 2429 SND_SOC_DAPM_PGA("IF1 DAC5", SND_SOC_NOPM, 0, 0, NULL, 0), 2430 SND_SOC_DAPM_PGA("IF1 DAC6", SND_SOC_NOPM, 0, 0, NULL, 0), 2431 SND_SOC_DAPM_PGA("IF1 DAC7", SND_SOC_NOPM, 0, 0, NULL, 0), 2432 SND_SOC_DAPM_PGA("IF1 DAC01", SND_SOC_NOPM, 0, 0, NULL, 0), 2433 SND_SOC_DAPM_PGA("IF1 DAC23", SND_SOC_NOPM, 0, 0, NULL, 0), 2434 SND_SOC_DAPM_PGA("IF1 DAC45", SND_SOC_NOPM, 0, 0, NULL, 0), 2435 SND_SOC_DAPM_PGA("IF1 DAC67", SND_SOC_NOPM, 0, 0, NULL, 0), 2436 SND_SOC_DAPM_PGA("IF1 ADC1", SND_SOC_NOPM, 0, 0, NULL, 0), 2437 SND_SOC_DAPM_PGA("IF1 ADC2", SND_SOC_NOPM, 0, 0, NULL, 0), 2438 SND_SOC_DAPM_PGA("IF1 ADC3", SND_SOC_NOPM, 0, 0, NULL, 0), 2439 SND_SOC_DAPM_PGA("IF1 ADC4", SND_SOC_NOPM, 0, 0, NULL, 0), 2440 2441 SND_SOC_DAPM_SUPPLY("I2S2", RT5677_PWR_DIG1, 2442 RT5677_PWR_I2S2_BIT, 0, NULL, 0), 2443 SND_SOC_DAPM_PGA("IF2 DAC0", SND_SOC_NOPM, 0, 0, NULL, 0), 2444 SND_SOC_DAPM_PGA("IF2 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0), 2445 SND_SOC_DAPM_PGA("IF2 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0), 2446 SND_SOC_DAPM_PGA("IF2 DAC3", SND_SOC_NOPM, 0, 0, NULL, 0), 2447 SND_SOC_DAPM_PGA("IF2 DAC4", SND_SOC_NOPM, 0, 0, NULL, 0), 2448 SND_SOC_DAPM_PGA("IF2 DAC5", SND_SOC_NOPM, 0, 0, NULL, 0), 2449 SND_SOC_DAPM_PGA("IF2 DAC6", SND_SOC_NOPM, 0, 0, NULL, 0), 2450 SND_SOC_DAPM_PGA("IF2 DAC7", SND_SOC_NOPM, 0, 0, NULL, 0), 2451 SND_SOC_DAPM_PGA("IF2 DAC01", SND_SOC_NOPM, 0, 0, NULL, 0), 2452 SND_SOC_DAPM_PGA("IF2 DAC23", SND_SOC_NOPM, 0, 0, NULL, 0), 2453 SND_SOC_DAPM_PGA("IF2 DAC45", SND_SOC_NOPM, 0, 0, NULL, 0), 2454 SND_SOC_DAPM_PGA("IF2 DAC67", SND_SOC_NOPM, 0, 0, NULL, 0), 2455 SND_SOC_DAPM_PGA("IF2 ADC1", SND_SOC_NOPM, 0, 0, NULL, 0), 2456 SND_SOC_DAPM_PGA("IF2 ADC2", SND_SOC_NOPM, 0, 0, NULL, 0), 2457 SND_SOC_DAPM_PGA("IF2 ADC3", SND_SOC_NOPM, 0, 0, NULL, 0), 2458 SND_SOC_DAPM_PGA("IF2 ADC4", SND_SOC_NOPM, 0, 0, NULL, 0), 2459 2460 SND_SOC_DAPM_SUPPLY("I2S3", RT5677_PWR_DIG1, 2461 RT5677_PWR_I2S3_BIT, 0, NULL, 0), 2462 SND_SOC_DAPM_PGA("IF3 DAC", SND_SOC_NOPM, 0, 0, NULL, 0), 2463 SND_SOC_DAPM_PGA("IF3 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0), 2464 SND_SOC_DAPM_PGA("IF3 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0), 2465 SND_SOC_DAPM_PGA("IF3 ADC", SND_SOC_NOPM, 0, 0, NULL, 0), 2466 SND_SOC_DAPM_PGA("IF3 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0), 2467 SND_SOC_DAPM_PGA("IF3 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0), 2468 2469 SND_SOC_DAPM_SUPPLY("I2S4", RT5677_PWR_DIG1, 2470 RT5677_PWR_I2S4_BIT, 0, NULL, 0), 2471 SND_SOC_DAPM_PGA("IF4 DAC", SND_SOC_NOPM, 0, 0, NULL, 0), 2472 SND_SOC_DAPM_PGA("IF4 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0), 2473 SND_SOC_DAPM_PGA("IF4 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0), 2474 SND_SOC_DAPM_PGA("IF4 ADC", SND_SOC_NOPM, 0, 0, NULL, 0), 2475 SND_SOC_DAPM_PGA("IF4 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0), 2476 SND_SOC_DAPM_PGA("IF4 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0), 2477 2478 SND_SOC_DAPM_SUPPLY("SLB", RT5677_PWR_DIG1, 2479 RT5677_PWR_SLB_BIT, 0, NULL, 0), 2480 SND_SOC_DAPM_PGA("SLB DAC0", SND_SOC_NOPM, 0, 0, NULL, 0), 2481 SND_SOC_DAPM_PGA("SLB DAC1", SND_SOC_NOPM, 0, 0, NULL, 0), 2482 SND_SOC_DAPM_PGA("SLB DAC2", SND_SOC_NOPM, 0, 0, NULL, 0), 2483 SND_SOC_DAPM_PGA("SLB DAC3", SND_SOC_NOPM, 0, 0, NULL, 0), 2484 SND_SOC_DAPM_PGA("SLB DAC4", SND_SOC_NOPM, 0, 0, NULL, 0), 2485 SND_SOC_DAPM_PGA("SLB DAC5", SND_SOC_NOPM, 0, 0, NULL, 0), 2486 SND_SOC_DAPM_PGA("SLB DAC6", SND_SOC_NOPM, 0, 0, NULL, 0), 2487 SND_SOC_DAPM_PGA("SLB DAC7", SND_SOC_NOPM, 0, 0, NULL, 0), 2488 SND_SOC_DAPM_PGA("SLB DAC01", SND_SOC_NOPM, 0, 0, NULL, 0), 2489 SND_SOC_DAPM_PGA("SLB DAC23", SND_SOC_NOPM, 0, 0, NULL, 0), 2490 SND_SOC_DAPM_PGA("SLB DAC45", SND_SOC_NOPM, 0, 0, NULL, 0), 2491 SND_SOC_DAPM_PGA("SLB DAC67", SND_SOC_NOPM, 0, 0, NULL, 0), 2492 SND_SOC_DAPM_PGA("SLB ADC1", SND_SOC_NOPM, 0, 0, NULL, 0), 2493 SND_SOC_DAPM_PGA("SLB ADC2", SND_SOC_NOPM, 0, 0, NULL, 0), 2494 SND_SOC_DAPM_PGA("SLB ADC3", SND_SOC_NOPM, 0, 0, NULL, 0), 2495 SND_SOC_DAPM_PGA("SLB ADC4", SND_SOC_NOPM, 0, 0, NULL, 0), 2496 2497 /* Digital Interface Select */ 2498 SND_SOC_DAPM_MUX("IF1 ADC1 Mux", SND_SOC_NOPM, 0, 0, 2499 &rt5677_if1_adc1_mux), 2500 SND_SOC_DAPM_MUX("IF1 ADC2 Mux", SND_SOC_NOPM, 0, 0, 2501 &rt5677_if1_adc2_mux), 2502 SND_SOC_DAPM_MUX("IF1 ADC3 Mux", SND_SOC_NOPM, 0, 0, 2503 &rt5677_if1_adc3_mux), 2504 SND_SOC_DAPM_MUX("IF1 ADC4 Mux", SND_SOC_NOPM, 0, 0, 2505 &rt5677_if1_adc4_mux), 2506 SND_SOC_DAPM_MUX("IF1 ADC1 Swap Mux", SND_SOC_NOPM, 0, 0, 2507 &rt5677_if1_adc1_swap_mux), 2508 SND_SOC_DAPM_MUX("IF1 ADC2 Swap Mux", SND_SOC_NOPM, 0, 0, 2509 &rt5677_if1_adc2_swap_mux), 2510 SND_SOC_DAPM_MUX("IF1 ADC3 Swap Mux", SND_SOC_NOPM, 0, 0, 2511 &rt5677_if1_adc3_swap_mux), 2512 SND_SOC_DAPM_MUX("IF1 ADC4 Swap Mux", SND_SOC_NOPM, 0, 0, 2513 &rt5677_if1_adc4_swap_mux), 2514 SND_SOC_DAPM_MUX_E("IF1 ADC TDM Swap Mux", SND_SOC_NOPM, 0, 0, 2515 &rt5677_if1_adc_tdm_swap_mux, rt5677_if1_adc_tdm_event, 2516 SND_SOC_DAPM_PRE_PMU), 2517 SND_SOC_DAPM_MUX("IF2 ADC1 Mux", SND_SOC_NOPM, 0, 0, 2518 &rt5677_if2_adc1_mux), 2519 SND_SOC_DAPM_MUX("IF2 ADC2 Mux", SND_SOC_NOPM, 0, 0, 2520 &rt5677_if2_adc2_mux), 2521 SND_SOC_DAPM_MUX("IF2 ADC3 Mux", SND_SOC_NOPM, 0, 0, 2522 &rt5677_if2_adc3_mux), 2523 SND_SOC_DAPM_MUX("IF2 ADC4 Mux", SND_SOC_NOPM, 0, 0, 2524 &rt5677_if2_adc4_mux), 2525 SND_SOC_DAPM_MUX("IF2 ADC1 Swap Mux", SND_SOC_NOPM, 0, 0, 2526 &rt5677_if2_adc1_swap_mux), 2527 SND_SOC_DAPM_MUX("IF2 ADC2 Swap Mux", SND_SOC_NOPM, 0, 0, 2528 &rt5677_if2_adc2_swap_mux), 2529 SND_SOC_DAPM_MUX("IF2 ADC3 Swap Mux", SND_SOC_NOPM, 0, 0, 2530 &rt5677_if2_adc3_swap_mux), 2531 SND_SOC_DAPM_MUX("IF2 ADC4 Swap Mux", SND_SOC_NOPM, 0, 0, 2532 &rt5677_if2_adc4_swap_mux), 2533 SND_SOC_DAPM_MUX_E("IF2 ADC TDM Swap Mux", SND_SOC_NOPM, 0, 0, 2534 &rt5677_if2_adc_tdm_swap_mux, rt5677_if2_adc_tdm_event, 2535 SND_SOC_DAPM_PRE_PMU), 2536 SND_SOC_DAPM_MUX("IF3 ADC Mux", SND_SOC_NOPM, 0, 0, 2537 &rt5677_if3_adc_mux), 2538 SND_SOC_DAPM_MUX("IF4 ADC Mux", SND_SOC_NOPM, 0, 0, 2539 &rt5677_if4_adc_mux), 2540 SND_SOC_DAPM_MUX("SLB ADC1 Mux", SND_SOC_NOPM, 0, 0, 2541 &rt5677_slb_adc1_mux), 2542 SND_SOC_DAPM_MUX("SLB ADC2 Mux", SND_SOC_NOPM, 0, 0, 2543 &rt5677_slb_adc2_mux), 2544 SND_SOC_DAPM_MUX("SLB ADC3 Mux", SND_SOC_NOPM, 0, 0, 2545 &rt5677_slb_adc3_mux), 2546 SND_SOC_DAPM_MUX("SLB ADC4 Mux", SND_SOC_NOPM, 0, 0, 2547 &rt5677_slb_adc4_mux), 2548 2549 SND_SOC_DAPM_MUX("IF1 DAC0 Mux", SND_SOC_NOPM, 0, 0, 2550 &rt5677_if1_dac0_tdm_sel_mux), 2551 SND_SOC_DAPM_MUX("IF1 DAC1 Mux", SND_SOC_NOPM, 0, 0, 2552 &rt5677_if1_dac1_tdm_sel_mux), 2553 SND_SOC_DAPM_MUX("IF1 DAC2 Mux", SND_SOC_NOPM, 0, 0, 2554 &rt5677_if1_dac2_tdm_sel_mux), 2555 SND_SOC_DAPM_MUX("IF1 DAC3 Mux", SND_SOC_NOPM, 0, 0, 2556 &rt5677_if1_dac3_tdm_sel_mux), 2557 SND_SOC_DAPM_MUX("IF1 DAC4 Mux", SND_SOC_NOPM, 0, 0, 2558 &rt5677_if1_dac4_tdm_sel_mux), 2559 SND_SOC_DAPM_MUX("IF1 DAC5 Mux", SND_SOC_NOPM, 0, 0, 2560 &rt5677_if1_dac5_tdm_sel_mux), 2561 SND_SOC_DAPM_MUX("IF1 DAC6 Mux", SND_SOC_NOPM, 0, 0, 2562 &rt5677_if1_dac6_tdm_sel_mux), 2563 SND_SOC_DAPM_MUX("IF1 DAC7 Mux", SND_SOC_NOPM, 0, 0, 2564 &rt5677_if1_dac7_tdm_sel_mux), 2565 2566 SND_SOC_DAPM_MUX("IF2 DAC0 Mux", SND_SOC_NOPM, 0, 0, 2567 &rt5677_if2_dac0_tdm_sel_mux), 2568 SND_SOC_DAPM_MUX("IF2 DAC1 Mux", SND_SOC_NOPM, 0, 0, 2569 &rt5677_if2_dac1_tdm_sel_mux), 2570 SND_SOC_DAPM_MUX("IF2 DAC2 Mux", SND_SOC_NOPM, 0, 0, 2571 &rt5677_if2_dac2_tdm_sel_mux), 2572 SND_SOC_DAPM_MUX("IF2 DAC3 Mux", SND_SOC_NOPM, 0, 0, 2573 &rt5677_if2_dac3_tdm_sel_mux), 2574 SND_SOC_DAPM_MUX("IF2 DAC4 Mux", SND_SOC_NOPM, 0, 0, 2575 &rt5677_if2_dac4_tdm_sel_mux), 2576 SND_SOC_DAPM_MUX("IF2 DAC5 Mux", SND_SOC_NOPM, 0, 0, 2577 &rt5677_if2_dac5_tdm_sel_mux), 2578 SND_SOC_DAPM_MUX("IF2 DAC6 Mux", SND_SOC_NOPM, 0, 0, 2579 &rt5677_if2_dac6_tdm_sel_mux), 2580 SND_SOC_DAPM_MUX("IF2 DAC7 Mux", SND_SOC_NOPM, 0, 0, 2581 &rt5677_if2_dac7_tdm_sel_mux), 2582 2583 /* Audio Interface */ 2584 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0), 2585 SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0), 2586 SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0), 2587 SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0), 2588 SND_SOC_DAPM_AIF_IN("AIF3RX", "AIF3 Playback", 0, SND_SOC_NOPM, 0, 0), 2589 SND_SOC_DAPM_AIF_OUT("AIF3TX", "AIF3 Capture", 0, SND_SOC_NOPM, 0, 0), 2590 SND_SOC_DAPM_AIF_IN("AIF4RX", "AIF4 Playback", 0, SND_SOC_NOPM, 0, 0), 2591 SND_SOC_DAPM_AIF_OUT("AIF4TX", "AIF4 Capture", 0, SND_SOC_NOPM, 0, 0), 2592 SND_SOC_DAPM_AIF_IN("SLBRX", "SLIMBus Playback", 0, SND_SOC_NOPM, 0, 0), 2593 SND_SOC_DAPM_AIF_OUT("SLBTX", "SLIMBus Capture", 0, SND_SOC_NOPM, 0, 0), 2594 2595 /* Sidetone Mux */ 2596 SND_SOC_DAPM_MUX("Sidetone Mux", SND_SOC_NOPM, 0, 0, 2597 &rt5677_sidetone_mux), 2598 SND_SOC_DAPM_SUPPLY("Sidetone Power", RT5677_SIDETONE_CTRL, 2599 RT5677_ST_EN_SFT, 0, NULL, 0), 2600 2601 /* VAD Mux*/ 2602 SND_SOC_DAPM_MUX("VAD ADC Mux", SND_SOC_NOPM, 0, 0, 2603 &rt5677_vad_src_mux), 2604 2605 /* Tensilica DSP */ 2606 SND_SOC_DAPM_PGA("Tensilica DSP", SND_SOC_NOPM, 0, 0, NULL, 0), 2607 SND_SOC_DAPM_MIXER("OB01 MIX", SND_SOC_NOPM, 0, 0, 2608 rt5677_ob_01_mix, ARRAY_SIZE(rt5677_ob_01_mix)), 2609 SND_SOC_DAPM_MIXER("OB23 MIX", SND_SOC_NOPM, 0, 0, 2610 rt5677_ob_23_mix, ARRAY_SIZE(rt5677_ob_23_mix)), 2611 SND_SOC_DAPM_MIXER("OB4 MIX", SND_SOC_NOPM, 0, 0, 2612 rt5677_ob_4_mix, ARRAY_SIZE(rt5677_ob_4_mix)), 2613 SND_SOC_DAPM_MIXER("OB5 MIX", SND_SOC_NOPM, 0, 0, 2614 rt5677_ob_5_mix, ARRAY_SIZE(rt5677_ob_5_mix)), 2615 SND_SOC_DAPM_MIXER("OB6 MIX", SND_SOC_NOPM, 0, 0, 2616 rt5677_ob_6_mix, ARRAY_SIZE(rt5677_ob_6_mix)), 2617 SND_SOC_DAPM_MIXER("OB7 MIX", SND_SOC_NOPM, 0, 0, 2618 rt5677_ob_7_mix, ARRAY_SIZE(rt5677_ob_7_mix)), 2619 2620 /* Output Side */ 2621 /* DAC mixer before sound effect */ 2622 SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0, 2623 rt5677_dac_l_mix, ARRAY_SIZE(rt5677_dac_l_mix)), 2624 SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0, 2625 rt5677_dac_r_mix, ARRAY_SIZE(rt5677_dac_r_mix)), 2626 SND_SOC_DAPM_PGA("DAC1 FS", SND_SOC_NOPM, 0, 0, NULL, 0), 2627 2628 /* DAC Mux */ 2629 SND_SOC_DAPM_MUX("DAC1 Mux", SND_SOC_NOPM, 0, 0, 2630 &rt5677_dac1_mux), 2631 SND_SOC_DAPM_MUX("ADDA1 Mux", SND_SOC_NOPM, 0, 0, 2632 &rt5677_adda1_mux), 2633 SND_SOC_DAPM_MUX("DAC12 SRC Mux", SND_SOC_NOPM, 0, 0, 2634 &rt5677_dac12_mux), 2635 SND_SOC_DAPM_MUX("DAC3 SRC Mux", SND_SOC_NOPM, 0, 0, 2636 &rt5677_dac3_mux), 2637 2638 /* DAC2 channel Mux */ 2639 SND_SOC_DAPM_MUX("DAC2 L Mux", SND_SOC_NOPM, 0, 0, 2640 &rt5677_dac2_l_mux), 2641 SND_SOC_DAPM_MUX("DAC2 R Mux", SND_SOC_NOPM, 0, 0, 2642 &rt5677_dac2_r_mux), 2643 2644 /* DAC3 channel Mux */ 2645 SND_SOC_DAPM_MUX("DAC3 L Mux", SND_SOC_NOPM, 0, 0, 2646 &rt5677_dac3_l_mux), 2647 SND_SOC_DAPM_MUX("DAC3 R Mux", SND_SOC_NOPM, 0, 0, 2648 &rt5677_dac3_r_mux), 2649 2650 /* DAC4 channel Mux */ 2651 SND_SOC_DAPM_MUX("DAC4 L Mux", SND_SOC_NOPM, 0, 0, 2652 &rt5677_dac4_l_mux), 2653 SND_SOC_DAPM_MUX("DAC4 R Mux", SND_SOC_NOPM, 0, 0, 2654 &rt5677_dac4_r_mux), 2655 2656 /* DAC Mixer */ 2657 SND_SOC_DAPM_SUPPLY("dac stereo1 filter", RT5677_PWR_DIG2, 2658 RT5677_PWR_DAC_S1F_BIT, 0, NULL, 0), 2659 SND_SOC_DAPM_SUPPLY("dac mono left filter", RT5677_PWR_DIG2, 2660 RT5677_PWR_DAC_M2F_L_BIT, 0, NULL, 0), 2661 SND_SOC_DAPM_SUPPLY("dac mono right filter", RT5677_PWR_DIG2, 2662 RT5677_PWR_DAC_M2F_R_BIT, 0, NULL, 0), 2663 2664 SND_SOC_DAPM_MIXER("Stereo DAC MIXL", SND_SOC_NOPM, 0, 0, 2665 rt5677_sto1_dac_l_mix, ARRAY_SIZE(rt5677_sto1_dac_l_mix)), 2666 SND_SOC_DAPM_MIXER("Stereo DAC MIXR", SND_SOC_NOPM, 0, 0, 2667 rt5677_sto1_dac_r_mix, ARRAY_SIZE(rt5677_sto1_dac_r_mix)), 2668 SND_SOC_DAPM_MIXER("Mono DAC MIXL", SND_SOC_NOPM, 0, 0, 2669 rt5677_mono_dac_l_mix, ARRAY_SIZE(rt5677_mono_dac_l_mix)), 2670 SND_SOC_DAPM_MIXER("Mono DAC MIXR", SND_SOC_NOPM, 0, 0, 2671 rt5677_mono_dac_r_mix, ARRAY_SIZE(rt5677_mono_dac_r_mix)), 2672 SND_SOC_DAPM_MIXER("DD1 MIXL", SND_SOC_NOPM, 0, 0, 2673 rt5677_dd1_l_mix, ARRAY_SIZE(rt5677_dd1_l_mix)), 2674 SND_SOC_DAPM_MIXER("DD1 MIXR", SND_SOC_NOPM, 0, 0, 2675 rt5677_dd1_r_mix, ARRAY_SIZE(rt5677_dd1_r_mix)), 2676 SND_SOC_DAPM_MIXER("DD2 MIXL", SND_SOC_NOPM, 0, 0, 2677 rt5677_dd2_l_mix, ARRAY_SIZE(rt5677_dd2_l_mix)), 2678 SND_SOC_DAPM_MIXER("DD2 MIXR", SND_SOC_NOPM, 0, 0, 2679 rt5677_dd2_r_mix, ARRAY_SIZE(rt5677_dd2_r_mix)), 2680 SND_SOC_DAPM_PGA("Stereo DAC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 2681 SND_SOC_DAPM_PGA("Mono DAC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 2682 SND_SOC_DAPM_PGA("DD1 MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 2683 SND_SOC_DAPM_PGA("DD2 MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 2684 2685 /* DACs */ 2686 SND_SOC_DAPM_DAC("DAC 1", NULL, RT5677_PWR_DIG1, 2687 RT5677_PWR_DAC1_BIT, 0), 2688 SND_SOC_DAPM_DAC("DAC 2", NULL, RT5677_PWR_DIG1, 2689 RT5677_PWR_DAC2_BIT, 0), 2690 SND_SOC_DAPM_DAC("DAC 3", NULL, RT5677_PWR_DIG1, 2691 RT5677_PWR_DAC3_BIT, 0), 2692 2693 /* PDM */ 2694 SND_SOC_DAPM_SUPPLY("PDM1 Power", RT5677_PWR_DIG2, 2695 RT5677_PWR_PDM1_BIT, 0, NULL, 0), 2696 SND_SOC_DAPM_SUPPLY("PDM2 Power", RT5677_PWR_DIG2, 2697 RT5677_PWR_PDM2_BIT, 0, NULL, 0), 2698 2699 SND_SOC_DAPM_MUX("PDM1 L Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM1_L_SFT, 2700 1, &rt5677_pdm1_l_mux), 2701 SND_SOC_DAPM_MUX("PDM1 R Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM1_R_SFT, 2702 1, &rt5677_pdm1_r_mux), 2703 SND_SOC_DAPM_MUX("PDM2 L Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM2_L_SFT, 2704 1, &rt5677_pdm2_l_mux), 2705 SND_SOC_DAPM_MUX("PDM2 R Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM2_R_SFT, 2706 1, &rt5677_pdm2_r_mux), 2707 2708 SND_SOC_DAPM_PGA_S("LOUT1 amp", 0, RT5677_PWR_ANLG1, RT5677_PWR_LO1_BIT, 2709 0, NULL, 0), 2710 SND_SOC_DAPM_PGA_S("LOUT2 amp", 0, RT5677_PWR_ANLG1, RT5677_PWR_LO2_BIT, 2711 0, NULL, 0), 2712 SND_SOC_DAPM_PGA_S("LOUT3 amp", 0, RT5677_PWR_ANLG1, RT5677_PWR_LO3_BIT, 2713 0, NULL, 0), 2714 2715 SND_SOC_DAPM_PGA_S("LOUT1 vref", 1, SND_SOC_NOPM, 0, 0, 2716 rt5677_vref_event, SND_SOC_DAPM_POST_PMU), 2717 SND_SOC_DAPM_PGA_S("LOUT2 vref", 1, SND_SOC_NOPM, 0, 0, 2718 rt5677_vref_event, SND_SOC_DAPM_POST_PMU), 2719 SND_SOC_DAPM_PGA_S("LOUT3 vref", 1, SND_SOC_NOPM, 0, 0, 2720 rt5677_vref_event, SND_SOC_DAPM_POST_PMU), 2721 2722 /* Output Lines */ 2723 SND_SOC_DAPM_OUTPUT("LOUT1"), 2724 SND_SOC_DAPM_OUTPUT("LOUT2"), 2725 SND_SOC_DAPM_OUTPUT("LOUT3"), 2726 SND_SOC_DAPM_OUTPUT("PDM1L"), 2727 SND_SOC_DAPM_OUTPUT("PDM1R"), 2728 SND_SOC_DAPM_OUTPUT("PDM2L"), 2729 SND_SOC_DAPM_OUTPUT("PDM2R"), 2730 2731 SND_SOC_DAPM_POST("vref", rt5677_vref_event), 2732 }; 2733 2734 static const struct snd_soc_dapm_route rt5677_dapm_routes[] = { 2735 { "DMIC1", NULL, "DMIC L1" }, 2736 { "DMIC1", NULL, "DMIC R1" }, 2737 { "DMIC2", NULL, "DMIC L2" }, 2738 { "DMIC2", NULL, "DMIC R2" }, 2739 { "DMIC3", NULL, "DMIC L3" }, 2740 { "DMIC3", NULL, "DMIC R3" }, 2741 { "DMIC4", NULL, "DMIC L4" }, 2742 { "DMIC4", NULL, "DMIC R4" }, 2743 2744 { "DMIC L1", NULL, "DMIC CLK" }, 2745 { "DMIC R1", NULL, "DMIC CLK" }, 2746 { "DMIC L2", NULL, "DMIC CLK" }, 2747 { "DMIC R2", NULL, "DMIC CLK" }, 2748 { "DMIC L3", NULL, "DMIC CLK" }, 2749 { "DMIC R3", NULL, "DMIC CLK" }, 2750 { "DMIC L4", NULL, "DMIC CLK" }, 2751 { "DMIC R4", NULL, "DMIC CLK" }, 2752 2753 { "DMIC L1", NULL, "DMIC1 power" }, 2754 { "DMIC R1", NULL, "DMIC1 power" }, 2755 { "DMIC L3", NULL, "DMIC3 power" }, 2756 { "DMIC R3", NULL, "DMIC3 power" }, 2757 { "DMIC L4", NULL, "DMIC4 power" }, 2758 { "DMIC R4", NULL, "DMIC4 power" }, 2759 2760 { "BST1", NULL, "IN1P" }, 2761 { "BST1", NULL, "IN1N" }, 2762 { "BST2", NULL, "IN2P" }, 2763 { "BST2", NULL, "IN2N" }, 2764 2765 { "IN1P", NULL, "MICBIAS1" }, 2766 { "IN1N", NULL, "MICBIAS1" }, 2767 { "IN2P", NULL, "MICBIAS1" }, 2768 { "IN2N", NULL, "MICBIAS1" }, 2769 2770 { "ADC 1", NULL, "BST1" }, 2771 { "ADC 1", NULL, "ADC 1 power" }, 2772 { "ADC 1", NULL, "ADC1 clock" }, 2773 { "ADC 2", NULL, "BST2" }, 2774 { "ADC 2", NULL, "ADC 2 power" }, 2775 { "ADC 2", NULL, "ADC2 clock" }, 2776 2777 { "Stereo1 DMIC Mux", "DMIC1", "DMIC1" }, 2778 { "Stereo1 DMIC Mux", "DMIC2", "DMIC2" }, 2779 { "Stereo1 DMIC Mux", "DMIC3", "DMIC3" }, 2780 { "Stereo1 DMIC Mux", "DMIC4", "DMIC4" }, 2781 2782 { "Stereo2 DMIC Mux", "DMIC1", "DMIC1" }, 2783 { "Stereo2 DMIC Mux", "DMIC2", "DMIC2" }, 2784 { "Stereo2 DMIC Mux", "DMIC3", "DMIC3" }, 2785 { "Stereo2 DMIC Mux", "DMIC4", "DMIC4" }, 2786 2787 { "Stereo3 DMIC Mux", "DMIC1", "DMIC1" }, 2788 { "Stereo3 DMIC Mux", "DMIC2", "DMIC2" }, 2789 { "Stereo3 DMIC Mux", "DMIC3", "DMIC3" }, 2790 { "Stereo3 DMIC Mux", "DMIC4", "DMIC4" }, 2791 2792 { "Stereo4 DMIC Mux", "DMIC1", "DMIC1" }, 2793 { "Stereo4 DMIC Mux", "DMIC2", "DMIC2" }, 2794 { "Stereo4 DMIC Mux", "DMIC3", "DMIC3" }, 2795 { "Stereo4 DMIC Mux", "DMIC4", "DMIC4" }, 2796 2797 { "Mono DMIC L Mux", "DMIC1", "DMIC1" }, 2798 { "Mono DMIC L Mux", "DMIC2", "DMIC2" }, 2799 { "Mono DMIC L Mux", "DMIC3", "DMIC3" }, 2800 { "Mono DMIC L Mux", "DMIC4", "DMIC4" }, 2801 2802 { "Mono DMIC R Mux", "DMIC1", "DMIC1" }, 2803 { "Mono DMIC R Mux", "DMIC2", "DMIC2" }, 2804 { "Mono DMIC R Mux", "DMIC3", "DMIC3" }, 2805 { "Mono DMIC R Mux", "DMIC4", "DMIC4" }, 2806 2807 { "ADC 1_2", NULL, "ADC 1" }, 2808 { "ADC 1_2", NULL, "ADC 2" }, 2809 2810 { "Stereo1 ADC1 Mux", "DD MIX1", "DD1 MIX" }, 2811 { "Stereo1 ADC1 Mux", "ADC1/2", "ADC 1_2" }, 2812 { "Stereo1 ADC1 Mux", "Stereo DAC MIX", "Stereo DAC MIX" }, 2813 2814 { "Stereo1 ADC2 Mux", "DD MIX1", "DD1 MIX" }, 2815 { "Stereo1 ADC2 Mux", "DMIC", "Stereo1 DMIC Mux" }, 2816 { "Stereo1 ADC2 Mux", "Stereo DAC MIX", "Stereo DAC MIX" }, 2817 2818 { "Stereo2 ADC1 Mux", "DD MIX1", "DD1 MIX" }, 2819 { "Stereo2 ADC1 Mux", "ADC1/2", "ADC 1_2" }, 2820 { "Stereo2 ADC1 Mux", "Stereo DAC MIX", "Stereo DAC MIX" }, 2821 2822 { "Stereo2 ADC2 Mux", "DD MIX1", "DD1 MIX" }, 2823 { "Stereo2 ADC2 Mux", "DMIC", "Stereo2 DMIC Mux" }, 2824 { "Stereo2 ADC2 Mux", "Stereo DAC MIX", "Stereo DAC MIX" }, 2825 2826 { "Stereo3 ADC1 Mux", "DD MIX1", "DD1 MIX" }, 2827 { "Stereo3 ADC1 Mux", "ADC1/2", "ADC 1_2" }, 2828 { "Stereo3 ADC1 Mux", "Stereo DAC MIX", "Stereo DAC MIX" }, 2829 2830 { "Stereo3 ADC2 Mux", "DD MIX1", "DD1 MIX" }, 2831 { "Stereo3 ADC2 Mux", "DMIC", "Stereo3 DMIC Mux" }, 2832 { "Stereo3 ADC2 Mux", "Stereo DAC MIX", "Stereo DAC MIX" }, 2833 2834 { "Stereo4 ADC1 Mux", "DD MIX1", "DD1 MIX" }, 2835 { "Stereo4 ADC1 Mux", "ADC1/2", "ADC 1_2" }, 2836 { "Stereo4 ADC1 Mux", "DD MIX2", "DD2 MIX" }, 2837 2838 { "Stereo4 ADC2 Mux", "DD MIX1", "DD1 MIX" }, 2839 { "Stereo4 ADC2 Mux", "DMIC", "Stereo3 DMIC Mux" }, 2840 { "Stereo4 ADC2 Mux", "DD MIX2", "DD2 MIX" }, 2841 2842 { "Mono ADC2 L Mux", "DD MIX1L", "DD1 MIXL" }, 2843 { "Mono ADC2 L Mux", "DMIC", "Mono DMIC L Mux" }, 2844 { "Mono ADC2 L Mux", "MONO DAC MIXL", "Mono DAC MIXL" }, 2845 2846 { "Mono ADC1 L Mux", "DD MIX1L", "DD1 MIXL" }, 2847 { "Mono ADC1 L Mux", "ADC1", "ADC 1" }, 2848 { "Mono ADC1 L Mux", "MONO DAC MIXL", "Mono DAC MIXL" }, 2849 2850 { "Mono ADC1 R Mux", "DD MIX1R", "DD1 MIXR" }, 2851 { "Mono ADC1 R Mux", "ADC2", "ADC 2" }, 2852 { "Mono ADC1 R Mux", "MONO DAC MIXR", "Mono DAC MIXR" }, 2853 2854 { "Mono ADC2 R Mux", "DD MIX1R", "DD1 MIXR" }, 2855 { "Mono ADC2 R Mux", "DMIC", "Mono DMIC R Mux" }, 2856 { "Mono ADC2 R Mux", "MONO DAC MIXR", "Mono DAC MIXR" }, 2857 2858 { "Sto1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC1 Mux" }, 2859 { "Sto1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC2 Mux" }, 2860 { "Sto1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC1 Mux" }, 2861 { "Sto1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC2 Mux" }, 2862 2863 { "Stereo1 ADC MIXL", NULL, "Sto1 ADC MIXL" }, 2864 { "Stereo1 ADC MIXL", NULL, "adc stereo1 filter" }, 2865 { "adc stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll }, 2866 2867 { "Stereo1 ADC MIXR", NULL, "Sto1 ADC MIXR" }, 2868 { "Stereo1 ADC MIXR", NULL, "adc stereo1 filter" }, 2869 { "adc stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll }, 2870 2871 { "Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXL" }, 2872 { "Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXR" }, 2873 2874 { "Sto2 ADC MIXL", "ADC1 Switch", "Stereo2 ADC1 Mux" }, 2875 { "Sto2 ADC MIXL", "ADC2 Switch", "Stereo2 ADC2 Mux" }, 2876 { "Sto2 ADC MIXR", "ADC1 Switch", "Stereo2 ADC1 Mux" }, 2877 { "Sto2 ADC MIXR", "ADC2 Switch", "Stereo2 ADC2 Mux" }, 2878 2879 { "Sto2 ADC LR MIX", NULL, "Sto2 ADC MIXL" }, 2880 { "Sto2 ADC LR MIX", NULL, "Sto2 ADC MIXR" }, 2881 2882 { "Stereo2 ADC LR Mux", "L", "Sto2 ADC MIXL" }, 2883 { "Stereo2 ADC LR Mux", "LR", "Sto2 ADC LR MIX" }, 2884 2885 { "Stereo2 ADC MIXL", NULL, "Stereo2 ADC LR Mux" }, 2886 { "Stereo2 ADC MIXL", NULL, "adc stereo2 filter" }, 2887 { "adc stereo2 filter", NULL, "PLL1", is_sys_clk_from_pll }, 2888 2889 { "Stereo2 ADC MIXR", NULL, "Sto2 ADC MIXR" }, 2890 { "Stereo2 ADC MIXR", NULL, "adc stereo2 filter" }, 2891 { "adc stereo2 filter", NULL, "PLL1", is_sys_clk_from_pll }, 2892 2893 { "Stereo2 ADC MIX", NULL, "Stereo2 ADC MIXL" }, 2894 { "Stereo2 ADC MIX", NULL, "Stereo2 ADC MIXR" }, 2895 2896 { "Sto3 ADC MIXL", "ADC1 Switch", "Stereo3 ADC1 Mux" }, 2897 { "Sto3 ADC MIXL", "ADC2 Switch", "Stereo3 ADC2 Mux" }, 2898 { "Sto3 ADC MIXR", "ADC1 Switch", "Stereo3 ADC1 Mux" }, 2899 { "Sto3 ADC MIXR", "ADC2 Switch", "Stereo3 ADC2 Mux" }, 2900 2901 { "Stereo3 ADC MIXL", NULL, "Sto3 ADC MIXL" }, 2902 { "Stereo3 ADC MIXL", NULL, "adc stereo3 filter" }, 2903 { "adc stereo3 filter", NULL, "PLL1", is_sys_clk_from_pll }, 2904 2905 { "Stereo3 ADC MIXR", NULL, "Sto3 ADC MIXR" }, 2906 { "Stereo3 ADC MIXR", NULL, "adc stereo3 filter" }, 2907 { "adc stereo3 filter", NULL, "PLL1", is_sys_clk_from_pll }, 2908 2909 { "Stereo3 ADC MIX", NULL, "Stereo3 ADC MIXL" }, 2910 { "Stereo3 ADC MIX", NULL, "Stereo3 ADC MIXR" }, 2911 2912 { "Sto4 ADC MIXL", "ADC1 Switch", "Stereo4 ADC1 Mux" }, 2913 { "Sto4 ADC MIXL", "ADC2 Switch", "Stereo4 ADC2 Mux" }, 2914 { "Sto4 ADC MIXR", "ADC1 Switch", "Stereo4 ADC1 Mux" }, 2915 { "Sto4 ADC MIXR", "ADC2 Switch", "Stereo4 ADC2 Mux" }, 2916 2917 { "Stereo4 ADC MIXL", NULL, "Sto4 ADC MIXL" }, 2918 { "Stereo4 ADC MIXL", NULL, "adc stereo4 filter" }, 2919 { "adc stereo4 filter", NULL, "PLL1", is_sys_clk_from_pll }, 2920 2921 { "Stereo4 ADC MIXR", NULL, "Sto4 ADC MIXR" }, 2922 { "Stereo4 ADC MIXR", NULL, "adc stereo4 filter" }, 2923 { "adc stereo4 filter", NULL, "PLL1", is_sys_clk_from_pll }, 2924 2925 { "Stereo4 ADC MIX", NULL, "Stereo4 ADC MIXL" }, 2926 { "Stereo4 ADC MIX", NULL, "Stereo4 ADC MIXR" }, 2927 2928 { "Mono ADC MIXL", "ADC1 Switch", "Mono ADC1 L Mux" }, 2929 { "Mono ADC MIXL", "ADC2 Switch", "Mono ADC2 L Mux" }, 2930 { "Mono ADC MIXL", NULL, "adc mono left filter" }, 2931 { "adc mono left filter", NULL, "PLL1", is_sys_clk_from_pll }, 2932 2933 { "Mono ADC MIXR", "ADC1 Switch", "Mono ADC1 R Mux" }, 2934 { "Mono ADC MIXR", "ADC2 Switch", "Mono ADC2 R Mux" }, 2935 { "Mono ADC MIXR", NULL, "adc mono right filter" }, 2936 { "adc mono right filter", NULL, "PLL1", is_sys_clk_from_pll }, 2937 2938 { "Mono ADC MIX", NULL, "Mono ADC MIXL" }, 2939 { "Mono ADC MIX", NULL, "Mono ADC MIXR" }, 2940 2941 { "VAD ADC Mux", "STO1 ADC MIX L", "Stereo1 ADC MIXL" }, 2942 { "VAD ADC Mux", "MONO ADC MIX L", "Mono ADC MIXL" }, 2943 { "VAD ADC Mux", "MONO ADC MIX R", "Mono ADC MIXR" }, 2944 { "VAD ADC Mux", "STO2 ADC MIX L", "Stereo2 ADC MIXL" }, 2945 { "VAD ADC Mux", "STO3 ADC MIX L", "Stereo3 ADC MIXL" }, 2946 2947 { "IF1 ADC1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" }, 2948 { "IF1 ADC1 Mux", "OB01", "OB01 Bypass Mux" }, 2949 { "IF1 ADC1 Mux", "VAD ADC", "VAD ADC Mux" }, 2950 2951 { "IF1 ADC2 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" }, 2952 { "IF1 ADC2 Mux", "OB23", "OB23 Bypass Mux" }, 2953 2954 { "IF1 ADC3 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" }, 2955 { "IF1 ADC3 Mux", "MONO ADC MIX", "Mono ADC MIX" }, 2956 { "IF1 ADC3 Mux", "OB45", "OB45" }, 2957 2958 { "IF1 ADC4 Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" }, 2959 { "IF1 ADC4 Mux", "OB67", "OB67" }, 2960 { "IF1 ADC4 Mux", "OB01", "OB01 Bypass Mux" }, 2961 2962 { "IF1 ADC1 Swap Mux", "L/R", "IF1 ADC1 Mux" }, 2963 { "IF1 ADC1 Swap Mux", "R/L", "IF1 ADC1 Mux" }, 2964 { "IF1 ADC1 Swap Mux", "L/L", "IF1 ADC1 Mux" }, 2965 { "IF1 ADC1 Swap Mux", "R/R", "IF1 ADC1 Mux" }, 2966 2967 { "IF1 ADC2 Swap Mux", "L/R", "IF1 ADC2 Mux" }, 2968 { "IF1 ADC2 Swap Mux", "R/L", "IF1 ADC2 Mux" }, 2969 { "IF1 ADC2 Swap Mux", "L/L", "IF1 ADC2 Mux" }, 2970 { "IF1 ADC2 Swap Mux", "R/R", "IF1 ADC2 Mux" }, 2971 2972 { "IF1 ADC3 Swap Mux", "L/R", "IF1 ADC3 Mux" }, 2973 { "IF1 ADC3 Swap Mux", "R/L", "IF1 ADC3 Mux" }, 2974 { "IF1 ADC3 Swap Mux", "L/L", "IF1 ADC3 Mux" }, 2975 { "IF1 ADC3 Swap Mux", "R/R", "IF1 ADC3 Mux" }, 2976 2977 { "IF1 ADC4 Swap Mux", "L/R", "IF1 ADC4 Mux" }, 2978 { "IF1 ADC4 Swap Mux", "R/L", "IF1 ADC4 Mux" }, 2979 { "IF1 ADC4 Swap Mux", "L/L", "IF1 ADC4 Mux" }, 2980 { "IF1 ADC4 Swap Mux", "R/R", "IF1 ADC4 Mux" }, 2981 2982 { "IF1 ADC", NULL, "IF1 ADC1 Swap Mux" }, 2983 { "IF1 ADC", NULL, "IF1 ADC2 Swap Mux" }, 2984 { "IF1 ADC", NULL, "IF1 ADC3 Swap Mux" }, 2985 { "IF1 ADC", NULL, "IF1 ADC4 Swap Mux" }, 2986 2987 { "IF1 ADC TDM Swap Mux", "1/2/3/4", "IF1 ADC" }, 2988 { "IF1 ADC TDM Swap Mux", "2/1/3/4", "IF1 ADC" }, 2989 { "IF1 ADC TDM Swap Mux", "2/3/1/4", "IF1 ADC" }, 2990 { "IF1 ADC TDM Swap Mux", "4/1/2/3", "IF1 ADC" }, 2991 { "IF1 ADC TDM Swap Mux", "1/3/2/4", "IF1 ADC" }, 2992 { "IF1 ADC TDM Swap Mux", "1/4/2/3", "IF1 ADC" }, 2993 { "IF1 ADC TDM Swap Mux", "3/1/2/4", "IF1 ADC" }, 2994 { "IF1 ADC TDM Swap Mux", "3/4/1/2", "IF1 ADC" }, 2995 2996 { "AIF1TX", NULL, "I2S1" }, 2997 { "AIF1TX", NULL, "IF1 ADC TDM Swap Mux" }, 2998 2999 { "IF2 ADC1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" }, 3000 { "IF2 ADC1 Mux", "OB01", "OB01 Bypass Mux" }, 3001 { "IF2 ADC1 Mux", "VAD ADC", "VAD ADC Mux" }, 3002 3003 { "IF2 ADC2 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" }, 3004 { "IF2 ADC2 Mux", "OB23", "OB23 Bypass Mux" }, 3005 3006 { "IF2 ADC3 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" }, 3007 { "IF2 ADC3 Mux", "MONO ADC MIX", "Mono ADC MIX" }, 3008 { "IF2 ADC3 Mux", "OB45", "OB45" }, 3009 3010 { "IF2 ADC4 Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" }, 3011 { "IF2 ADC4 Mux", "OB67", "OB67" }, 3012 { "IF2 ADC4 Mux", "OB01", "OB01 Bypass Mux" }, 3013 3014 { "IF2 ADC1 Swap Mux", "L/R", "IF2 ADC1 Mux" }, 3015 { "IF2 ADC1 Swap Mux", "R/L", "IF2 ADC1 Mux" }, 3016 { "IF2 ADC1 Swap Mux", "L/L", "IF2 ADC1 Mux" }, 3017 { "IF2 ADC1 Swap Mux", "R/R", "IF2 ADC1 Mux" }, 3018 3019 { "IF2 ADC2 Swap Mux", "L/R", "IF2 ADC2 Mux" }, 3020 { "IF2 ADC2 Swap Mux", "R/L", "IF2 ADC2 Mux" }, 3021 { "IF2 ADC2 Swap Mux", "L/L", "IF2 ADC2 Mux" }, 3022 { "IF2 ADC2 Swap Mux", "R/R", "IF2 ADC2 Mux" }, 3023 3024 { "IF2 ADC3 Swap Mux", "L/R", "IF2 ADC3 Mux" }, 3025 { "IF2 ADC3 Swap Mux", "R/L", "IF2 ADC3 Mux" }, 3026 { "IF2 ADC3 Swap Mux", "L/L", "IF2 ADC3 Mux" }, 3027 { "IF2 ADC3 Swap Mux", "R/R", "IF2 ADC3 Mux" }, 3028 3029 { "IF2 ADC4 Swap Mux", "L/R", "IF2 ADC4 Mux" }, 3030 { "IF2 ADC4 Swap Mux", "R/L", "IF2 ADC4 Mux" }, 3031 { "IF2 ADC4 Swap Mux", "L/L", "IF2 ADC4 Mux" }, 3032 { "IF2 ADC4 Swap Mux", "R/R", "IF2 ADC4 Mux" }, 3033 3034 { "IF2 ADC", NULL, "IF2 ADC1 Swap Mux" }, 3035 { "IF2 ADC", NULL, "IF2 ADC2 Swap Mux" }, 3036 { "IF2 ADC", NULL, "IF2 ADC3 Swap Mux" }, 3037 { "IF2 ADC", NULL, "IF2 ADC4 Swap Mux" }, 3038 3039 { "IF2 ADC TDM Swap Mux", "1/2/3/4", "IF2 ADC" }, 3040 { "IF2 ADC TDM Swap Mux", "2/1/3/4", "IF2 ADC" }, 3041 { "IF2 ADC TDM Swap Mux", "3/1/2/4", "IF2 ADC" }, 3042 { "IF2 ADC TDM Swap Mux", "4/1/2/3", "IF2 ADC" }, 3043 { "IF2 ADC TDM Swap Mux", "1/3/2/4", "IF2 ADC" }, 3044 { "IF2 ADC TDM Swap Mux", "1/4/2/3", "IF2 ADC" }, 3045 { "IF2 ADC TDM Swap Mux", "2/3/1/4", "IF2 ADC" }, 3046 { "IF2 ADC TDM Swap Mux", "3/4/1/2", "IF2 ADC" }, 3047 3048 { "AIF2TX", NULL, "I2S2" }, 3049 { "AIF2TX", NULL, "IF2 ADC TDM Swap Mux" }, 3050 3051 { "IF3 ADC Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" }, 3052 { "IF3 ADC Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" }, 3053 { "IF3 ADC Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" }, 3054 { "IF3 ADC Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" }, 3055 { "IF3 ADC Mux", "MONO ADC MIX", "Mono ADC MIX" }, 3056 { "IF3 ADC Mux", "OB01", "OB01 Bypass Mux" }, 3057 { "IF3 ADC Mux", "OB23", "OB23 Bypass Mux" }, 3058 { "IF3 ADC Mux", "VAD ADC", "VAD ADC Mux" }, 3059 3060 { "AIF3TX", NULL, "I2S3" }, 3061 { "AIF3TX", NULL, "IF3 ADC Mux" }, 3062 3063 { "IF4 ADC Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" }, 3064 { "IF4 ADC Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" }, 3065 { "IF4 ADC Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" }, 3066 { "IF4 ADC Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" }, 3067 { "IF4 ADC Mux", "MONO ADC MIX", "Mono ADC MIX" }, 3068 { "IF4 ADC Mux", "OB01", "OB01 Bypass Mux" }, 3069 { "IF4 ADC Mux", "OB23", "OB23 Bypass Mux" }, 3070 { "IF4 ADC Mux", "VAD ADC", "VAD ADC Mux" }, 3071 3072 { "AIF4TX", NULL, "I2S4" }, 3073 { "AIF4TX", NULL, "IF4 ADC Mux" }, 3074 3075 { "SLB ADC1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" }, 3076 { "SLB ADC1 Mux", "OB01", "OB01 Bypass Mux" }, 3077 { "SLB ADC1 Mux", "VAD ADC", "VAD ADC Mux" }, 3078 3079 { "SLB ADC2 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" }, 3080 { "SLB ADC2 Mux", "OB23", "OB23 Bypass Mux" }, 3081 3082 { "SLB ADC3 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" }, 3083 { "SLB ADC3 Mux", "MONO ADC MIX", "Mono ADC MIX" }, 3084 { "SLB ADC3 Mux", "OB45", "OB45" }, 3085 3086 { "SLB ADC4 Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" }, 3087 { "SLB ADC4 Mux", "OB67", "OB67" }, 3088 { "SLB ADC4 Mux", "OB01", "OB01 Bypass Mux" }, 3089 3090 { "SLBTX", NULL, "SLB" }, 3091 { "SLBTX", NULL, "SLB ADC1 Mux" }, 3092 { "SLBTX", NULL, "SLB ADC2 Mux" }, 3093 { "SLBTX", NULL, "SLB ADC3 Mux" }, 3094 { "SLBTX", NULL, "SLB ADC4 Mux" }, 3095 3096 { "IB01 Mux", "IF1 DAC 01", "IF1 DAC01" }, 3097 { "IB01 Mux", "IF2 DAC 01", "IF2 DAC01" }, 3098 { "IB01 Mux", "SLB DAC 01", "SLB DAC01" }, 3099 { "IB01 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" }, 3100 { "IB01 Mux", "VAD ADC/DAC1 FS", "DAC1 FS" }, 3101 3102 { "IB01 Bypass Mux", "Bypass", "IB01 Mux" }, 3103 { "IB01 Bypass Mux", "Pass SRC", "IB01 Mux" }, 3104 3105 { "IB23 Mux", "IF1 DAC 23", "IF1 DAC23" }, 3106 { "IB23 Mux", "IF2 DAC 23", "IF2 DAC23" }, 3107 { "IB23 Mux", "SLB DAC 23", "SLB DAC23" }, 3108 { "IB23 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" }, 3109 { "IB23 Mux", "DAC1 FS", "DAC1 FS" }, 3110 { "IB23 Mux", "IF4 DAC", "IF4 DAC" }, 3111 3112 { "IB23 Bypass Mux", "Bypass", "IB23 Mux" }, 3113 { "IB23 Bypass Mux", "Pass SRC", "IB23 Mux" }, 3114 3115 { "IB45 Mux", "IF1 DAC 45", "IF1 DAC45" }, 3116 { "IB45 Mux", "IF2 DAC 45", "IF2 DAC45" }, 3117 { "IB45 Mux", "SLB DAC 45", "SLB DAC45" }, 3118 { "IB45 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" }, 3119 { "IB45 Mux", "IF3 DAC", "IF3 DAC" }, 3120 3121 { "IB45 Bypass Mux", "Bypass", "IB45 Mux" }, 3122 { "IB45 Bypass Mux", "Pass SRC", "IB45 Mux" }, 3123 3124 { "IB6 Mux", "IF1 DAC 6", "IF1 DAC6" }, 3125 { "IB6 Mux", "IF2 DAC 6", "IF2 DAC6" }, 3126 { "IB6 Mux", "SLB DAC 6", "SLB DAC6" }, 3127 { "IB6 Mux", "STO4 ADC MIX L", "Stereo4 ADC MIXL" }, 3128 { "IB6 Mux", "IF4 DAC L", "IF4 DAC L" }, 3129 { "IB6 Mux", "STO1 ADC MIX L", "Stereo1 ADC MIXL" }, 3130 { "IB6 Mux", "STO2 ADC MIX L", "Stereo2 ADC MIXL" }, 3131 { "IB6 Mux", "STO3 ADC MIX L", "Stereo3 ADC MIXL" }, 3132 3133 { "IB7 Mux", "IF1 DAC 7", "IF1 DAC7" }, 3134 { "IB7 Mux", "IF2 DAC 7", "IF2 DAC7" }, 3135 { "IB7 Mux", "SLB DAC 7", "SLB DAC7" }, 3136 { "IB7 Mux", "STO4 ADC MIX R", "Stereo4 ADC MIXR" }, 3137 { "IB7 Mux", "IF4 DAC R", "IF4 DAC R" }, 3138 { "IB7 Mux", "STO1 ADC MIX R", "Stereo1 ADC MIXR" }, 3139 { "IB7 Mux", "STO2 ADC MIX R", "Stereo2 ADC MIXR" }, 3140 { "IB7 Mux", "STO3 ADC MIX R", "Stereo3 ADC MIXR" }, 3141 3142 { "IB8 Mux", "STO1 ADC MIX L", "Stereo1 ADC MIXL" }, 3143 { "IB8 Mux", "STO2 ADC MIX L", "Stereo2 ADC MIXL" }, 3144 { "IB8 Mux", "STO3 ADC MIX L", "Stereo3 ADC MIXL" }, 3145 { "IB8 Mux", "STO4 ADC MIX L", "Stereo4 ADC MIXL" }, 3146 { "IB8 Mux", "MONO ADC MIX L", "Mono ADC MIXL" }, 3147 { "IB8 Mux", "DACL1 FS", "DAC1 MIXL" }, 3148 3149 { "IB9 Mux", "STO1 ADC MIX R", "Stereo1 ADC MIXR" }, 3150 { "IB9 Mux", "STO2 ADC MIX R", "Stereo2 ADC MIXR" }, 3151 { "IB9 Mux", "STO3 ADC MIX R", "Stereo3 ADC MIXR" }, 3152 { "IB9 Mux", "STO4 ADC MIX R", "Stereo4 ADC MIXR" }, 3153 { "IB9 Mux", "MONO ADC MIX R", "Mono ADC MIXR" }, 3154 { "IB9 Mux", "DACR1 FS", "DAC1 MIXR" }, 3155 { "IB9 Mux", "DAC1 FS", "DAC1 FS" }, 3156 3157 { "OB01 MIX", "IB01 Switch", "IB01 Bypass Mux" }, 3158 { "OB01 MIX", "IB23 Switch", "IB23 Bypass Mux" }, 3159 { "OB01 MIX", "IB45 Switch", "IB45 Bypass Mux" }, 3160 { "OB01 MIX", "IB6 Switch", "IB6 Mux" }, 3161 { "OB01 MIX", "IB7 Switch", "IB7 Mux" }, 3162 { "OB01 MIX", "IB8 Switch", "IB8 Mux" }, 3163 { "OB01 MIX", "IB9 Switch", "IB9 Mux" }, 3164 3165 { "OB23 MIX", "IB01 Switch", "IB01 Bypass Mux" }, 3166 { "OB23 MIX", "IB23 Switch", "IB23 Bypass Mux" }, 3167 { "OB23 MIX", "IB45 Switch", "IB45 Bypass Mux" }, 3168 { "OB23 MIX", "IB6 Switch", "IB6 Mux" }, 3169 { "OB23 MIX", "IB7 Switch", "IB7 Mux" }, 3170 { "OB23 MIX", "IB8 Switch", "IB8 Mux" }, 3171 { "OB23 MIX", "IB9 Switch", "IB9 Mux" }, 3172 3173 { "OB4 MIX", "IB01 Switch", "IB01 Bypass Mux" }, 3174 { "OB4 MIX", "IB23 Switch", "IB23 Bypass Mux" }, 3175 { "OB4 MIX", "IB45 Switch", "IB45 Bypass Mux" }, 3176 { "OB4 MIX", "IB6 Switch", "IB6 Mux" }, 3177 { "OB4 MIX", "IB7 Switch", "IB7 Mux" }, 3178 { "OB4 MIX", "IB8 Switch", "IB8 Mux" }, 3179 { "OB4 MIX", "IB9 Switch", "IB9 Mux" }, 3180 3181 { "OB5 MIX", "IB01 Switch", "IB01 Bypass Mux" }, 3182 { "OB5 MIX", "IB23 Switch", "IB23 Bypass Mux" }, 3183 { "OB5 MIX", "IB45 Switch", "IB45 Bypass Mux" }, 3184 { "OB5 MIX", "IB6 Switch", "IB6 Mux" }, 3185 { "OB5 MIX", "IB7 Switch", "IB7 Mux" }, 3186 { "OB5 MIX", "IB8 Switch", "IB8 Mux" }, 3187 { "OB5 MIX", "IB9 Switch", "IB9 Mux" }, 3188 3189 { "OB6 MIX", "IB01 Switch", "IB01 Bypass Mux" }, 3190 { "OB6 MIX", "IB23 Switch", "IB23 Bypass Mux" }, 3191 { "OB6 MIX", "IB45 Switch", "IB45 Bypass Mux" }, 3192 { "OB6 MIX", "IB6 Switch", "IB6 Mux" }, 3193 { "OB6 MIX", "IB7 Switch", "IB7 Mux" }, 3194 { "OB6 MIX", "IB8 Switch", "IB8 Mux" }, 3195 { "OB6 MIX", "IB9 Switch", "IB9 Mux" }, 3196 3197 { "OB7 MIX", "IB01 Switch", "IB01 Bypass Mux" }, 3198 { "OB7 MIX", "IB23 Switch", "IB23 Bypass Mux" }, 3199 { "OB7 MIX", "IB45 Switch", "IB45 Bypass Mux" }, 3200 { "OB7 MIX", "IB6 Switch", "IB6 Mux" }, 3201 { "OB7 MIX", "IB7 Switch", "IB7 Mux" }, 3202 { "OB7 MIX", "IB8 Switch", "IB8 Mux" }, 3203 { "OB7 MIX", "IB9 Switch", "IB9 Mux" }, 3204 3205 { "OB01 Bypass Mux", "Bypass", "OB01 MIX" }, 3206 { "OB01 Bypass Mux", "Pass SRC", "OB01 MIX" }, 3207 { "OB23 Bypass Mux", "Bypass", "OB23 MIX" }, 3208 { "OB23 Bypass Mux", "Pass SRC", "OB23 MIX" }, 3209 3210 { "OutBound2", NULL, "OB23 Bypass Mux" }, 3211 { "OutBound3", NULL, "OB23 Bypass Mux" }, 3212 { "OutBound4", NULL, "OB4 MIX" }, 3213 { "OutBound5", NULL, "OB5 MIX" }, 3214 { "OutBound6", NULL, "OB6 MIX" }, 3215 { "OutBound7", NULL, "OB7 MIX" }, 3216 3217 { "OB45", NULL, "OutBound4" }, 3218 { "OB45", NULL, "OutBound5" }, 3219 { "OB67", NULL, "OutBound6" }, 3220 { "OB67", NULL, "OutBound7" }, 3221 3222 { "IF1 DAC0", NULL, "AIF1RX" }, 3223 { "IF1 DAC1", NULL, "AIF1RX" }, 3224 { "IF1 DAC2", NULL, "AIF1RX" }, 3225 { "IF1 DAC3", NULL, "AIF1RX" }, 3226 { "IF1 DAC4", NULL, "AIF1RX" }, 3227 { "IF1 DAC5", NULL, "AIF1RX" }, 3228 { "IF1 DAC6", NULL, "AIF1RX" }, 3229 { "IF1 DAC7", NULL, "AIF1RX" }, 3230 { "IF1 DAC0", NULL, "I2S1" }, 3231 { "IF1 DAC1", NULL, "I2S1" }, 3232 { "IF1 DAC2", NULL, "I2S1" }, 3233 { "IF1 DAC3", NULL, "I2S1" }, 3234 { "IF1 DAC4", NULL, "I2S1" }, 3235 { "IF1 DAC5", NULL, "I2S1" }, 3236 { "IF1 DAC6", NULL, "I2S1" }, 3237 { "IF1 DAC7", NULL, "I2S1" }, 3238 3239 { "IF1 DAC0 Mux", "Slot0", "IF1 DAC0" }, 3240 { "IF1 DAC0 Mux", "Slot1", "IF1 DAC1" }, 3241 { "IF1 DAC0 Mux", "Slot2", "IF1 DAC2" }, 3242 { "IF1 DAC0 Mux", "Slot3", "IF1 DAC3" }, 3243 { "IF1 DAC0 Mux", "Slot4", "IF1 DAC4" }, 3244 { "IF1 DAC0 Mux", "Slot5", "IF1 DAC5" }, 3245 { "IF1 DAC0 Mux", "Slot6", "IF1 DAC6" }, 3246 { "IF1 DAC0 Mux", "Slot7", "IF1 DAC7" }, 3247 3248 { "IF1 DAC1 Mux", "Slot0", "IF1 DAC0" }, 3249 { "IF1 DAC1 Mux", "Slot1", "IF1 DAC1" }, 3250 { "IF1 DAC1 Mux", "Slot2", "IF1 DAC2" }, 3251 { "IF1 DAC1 Mux", "Slot3", "IF1 DAC3" }, 3252 { "IF1 DAC1 Mux", "Slot4", "IF1 DAC4" }, 3253 { "IF1 DAC1 Mux", "Slot5", "IF1 DAC5" }, 3254 { "IF1 DAC1 Mux", "Slot6", "IF1 DAC6" }, 3255 { "IF1 DAC1 Mux", "Slot7", "IF1 DAC7" }, 3256 3257 { "IF1 DAC2 Mux", "Slot0", "IF1 DAC0" }, 3258 { "IF1 DAC2 Mux", "Slot1", "IF1 DAC1" }, 3259 { "IF1 DAC2 Mux", "Slot2", "IF1 DAC2" }, 3260 { "IF1 DAC2 Mux", "Slot3", "IF1 DAC3" }, 3261 { "IF1 DAC2 Mux", "Slot4", "IF1 DAC4" }, 3262 { "IF1 DAC2 Mux", "Slot5", "IF1 DAC5" }, 3263 { "IF1 DAC2 Mux", "Slot6", "IF1 DAC6" }, 3264 { "IF1 DAC2 Mux", "Slot7", "IF1 DAC7" }, 3265 3266 { "IF1 DAC3 Mux", "Slot0", "IF1 DAC0" }, 3267 { "IF1 DAC3 Mux", "Slot1", "IF1 DAC1" }, 3268 { "IF1 DAC3 Mux", "Slot2", "IF1 DAC2" }, 3269 { "IF1 DAC3 Mux", "Slot3", "IF1 DAC3" }, 3270 { "IF1 DAC3 Mux", "Slot4", "IF1 DAC4" }, 3271 { "IF1 DAC3 Mux", "Slot5", "IF1 DAC5" }, 3272 { "IF1 DAC3 Mux", "Slot6", "IF1 DAC6" }, 3273 { "IF1 DAC3 Mux", "Slot7", "IF1 DAC7" }, 3274 3275 { "IF1 DAC4 Mux", "Slot0", "IF1 DAC0" }, 3276 { "IF1 DAC4 Mux", "Slot1", "IF1 DAC1" }, 3277 { "IF1 DAC4 Mux", "Slot2", "IF1 DAC2" }, 3278 { "IF1 DAC4 Mux", "Slot3", "IF1 DAC3" }, 3279 { "IF1 DAC4 Mux", "Slot4", "IF1 DAC4" }, 3280 { "IF1 DAC4 Mux", "Slot5", "IF1 DAC5" }, 3281 { "IF1 DAC4 Mux", "Slot6", "IF1 DAC6" }, 3282 { "IF1 DAC4 Mux", "Slot7", "IF1 DAC7" }, 3283 3284 { "IF1 DAC5 Mux", "Slot0", "IF1 DAC0" }, 3285 { "IF1 DAC5 Mux", "Slot1", "IF1 DAC1" }, 3286 { "IF1 DAC5 Mux", "Slot2", "IF1 DAC2" }, 3287 { "IF1 DAC5 Mux", "Slot3", "IF1 DAC3" }, 3288 { "IF1 DAC5 Mux", "Slot4", "IF1 DAC4" }, 3289 { "IF1 DAC5 Mux", "Slot5", "IF1 DAC5" }, 3290 { "IF1 DAC5 Mux", "Slot6", "IF1 DAC6" }, 3291 { "IF1 DAC5 Mux", "Slot7", "IF1 DAC7" }, 3292 3293 { "IF1 DAC6 Mux", "Slot0", "IF1 DAC0" }, 3294 { "IF1 DAC6 Mux", "Slot1", "IF1 DAC1" }, 3295 { "IF1 DAC6 Mux", "Slot2", "IF1 DAC2" }, 3296 { "IF1 DAC6 Mux", "Slot3", "IF1 DAC3" }, 3297 { "IF1 DAC6 Mux", "Slot4", "IF1 DAC4" }, 3298 { "IF1 DAC6 Mux", "Slot5", "IF1 DAC5" }, 3299 { "IF1 DAC6 Mux", "Slot6", "IF1 DAC6" }, 3300 { "IF1 DAC6 Mux", "Slot7", "IF1 DAC7" }, 3301 3302 { "IF1 DAC7 Mux", "Slot0", "IF1 DAC0" }, 3303 { "IF1 DAC7 Mux", "Slot1", "IF1 DAC1" }, 3304 { "IF1 DAC7 Mux", "Slot2", "IF1 DAC2" }, 3305 { "IF1 DAC7 Mux", "Slot3", "IF1 DAC3" }, 3306 { "IF1 DAC7 Mux", "Slot4", "IF1 DAC4" }, 3307 { "IF1 DAC7 Mux", "Slot5", "IF1 DAC5" }, 3308 { "IF1 DAC7 Mux", "Slot6", "IF1 DAC6" }, 3309 { "IF1 DAC7 Mux", "Slot7", "IF1 DAC7" }, 3310 3311 { "IF1 DAC01", NULL, "IF1 DAC0 Mux" }, 3312 { "IF1 DAC01", NULL, "IF1 DAC1 Mux" }, 3313 { "IF1 DAC23", NULL, "IF1 DAC2 Mux" }, 3314 { "IF1 DAC23", NULL, "IF1 DAC3 Mux" }, 3315 { "IF1 DAC45", NULL, "IF1 DAC4 Mux" }, 3316 { "IF1 DAC45", NULL, "IF1 DAC5 Mux" }, 3317 { "IF1 DAC67", NULL, "IF1 DAC6 Mux" }, 3318 { "IF1 DAC67", NULL, "IF1 DAC7 Mux" }, 3319 3320 { "IF2 DAC0", NULL, "AIF2RX" }, 3321 { "IF2 DAC1", NULL, "AIF2RX" }, 3322 { "IF2 DAC2", NULL, "AIF2RX" }, 3323 { "IF2 DAC3", NULL, "AIF2RX" }, 3324 { "IF2 DAC4", NULL, "AIF2RX" }, 3325 { "IF2 DAC5", NULL, "AIF2RX" }, 3326 { "IF2 DAC6", NULL, "AIF2RX" }, 3327 { "IF2 DAC7", NULL, "AIF2RX" }, 3328 { "IF2 DAC0", NULL, "I2S2" }, 3329 { "IF2 DAC1", NULL, "I2S2" }, 3330 { "IF2 DAC2", NULL, "I2S2" }, 3331 { "IF2 DAC3", NULL, "I2S2" }, 3332 { "IF2 DAC4", NULL, "I2S2" }, 3333 { "IF2 DAC5", NULL, "I2S2" }, 3334 { "IF2 DAC6", NULL, "I2S2" }, 3335 { "IF2 DAC7", NULL, "I2S2" }, 3336 3337 { "IF2 DAC0 Mux", "Slot0", "IF2 DAC0" }, 3338 { "IF2 DAC0 Mux", "Slot1", "IF2 DAC1" }, 3339 { "IF2 DAC0 Mux", "Slot2", "IF2 DAC2" }, 3340 { "IF2 DAC0 Mux", "Slot3", "IF2 DAC3" }, 3341 { "IF2 DAC0 Mux", "Slot4", "IF2 DAC4" }, 3342 { "IF2 DAC0 Mux", "Slot5", "IF2 DAC5" }, 3343 { "IF2 DAC0 Mux", "Slot6", "IF2 DAC6" }, 3344 { "IF2 DAC0 Mux", "Slot7", "IF2 DAC7" }, 3345 3346 { "IF2 DAC1 Mux", "Slot0", "IF2 DAC0" }, 3347 { "IF2 DAC1 Mux", "Slot1", "IF2 DAC1" }, 3348 { "IF2 DAC1 Mux", "Slot2", "IF2 DAC2" }, 3349 { "IF2 DAC1 Mux", "Slot3", "IF2 DAC3" }, 3350 { "IF2 DAC1 Mux", "Slot4", "IF2 DAC4" }, 3351 { "IF2 DAC1 Mux", "Slot5", "IF2 DAC5" }, 3352 { "IF2 DAC1 Mux", "Slot6", "IF2 DAC6" }, 3353 { "IF2 DAC1 Mux", "Slot7", "IF2 DAC7" }, 3354 3355 { "IF2 DAC2 Mux", "Slot0", "IF2 DAC0" }, 3356 { "IF2 DAC2 Mux", "Slot1", "IF2 DAC1" }, 3357 { "IF2 DAC2 Mux", "Slot2", "IF2 DAC2" }, 3358 { "IF2 DAC2 Mux", "Slot3", "IF2 DAC3" }, 3359 { "IF2 DAC2 Mux", "Slot4", "IF2 DAC4" }, 3360 { "IF2 DAC2 Mux", "Slot5", "IF2 DAC5" }, 3361 { "IF2 DAC2 Mux", "Slot6", "IF2 DAC6" }, 3362 { "IF2 DAC2 Mux", "Slot7", "IF2 DAC7" }, 3363 3364 { "IF2 DAC3 Mux", "Slot0", "IF2 DAC0" }, 3365 { "IF2 DAC3 Mux", "Slot1", "IF2 DAC1" }, 3366 { "IF2 DAC3 Mux", "Slot2", "IF2 DAC2" }, 3367 { "IF2 DAC3 Mux", "Slot3", "IF2 DAC3" }, 3368 { "IF2 DAC3 Mux", "Slot4", "IF2 DAC4" }, 3369 { "IF2 DAC3 Mux", "Slot5", "IF2 DAC5" }, 3370 { "IF2 DAC3 Mux", "Slot6", "IF2 DAC6" }, 3371 { "IF2 DAC3 Mux", "Slot7", "IF2 DAC7" }, 3372 3373 { "IF2 DAC4 Mux", "Slot0", "IF2 DAC0" }, 3374 { "IF2 DAC4 Mux", "Slot1", "IF2 DAC1" }, 3375 { "IF2 DAC4 Mux", "Slot2", "IF2 DAC2" }, 3376 { "IF2 DAC4 Mux", "Slot3", "IF2 DAC3" }, 3377 { "IF2 DAC4 Mux", "Slot4", "IF2 DAC4" }, 3378 { "IF2 DAC4 Mux", "Slot5", "IF2 DAC5" }, 3379 { "IF2 DAC4 Mux", "Slot6", "IF2 DAC6" }, 3380 { "IF2 DAC4 Mux", "Slot7", "IF2 DAC7" }, 3381 3382 { "IF2 DAC5 Mux", "Slot0", "IF2 DAC0" }, 3383 { "IF2 DAC5 Mux", "Slot1", "IF2 DAC1" }, 3384 { "IF2 DAC5 Mux", "Slot2", "IF2 DAC2" }, 3385 { "IF2 DAC5 Mux", "Slot3", "IF2 DAC3" }, 3386 { "IF2 DAC5 Mux", "Slot4", "IF2 DAC4" }, 3387 { "IF2 DAC5 Mux", "Slot5", "IF2 DAC5" }, 3388 { "IF2 DAC5 Mux", "Slot6", "IF2 DAC6" }, 3389 { "IF2 DAC5 Mux", "Slot7", "IF2 DAC7" }, 3390 3391 { "IF2 DAC6 Mux", "Slot0", "IF2 DAC0" }, 3392 { "IF2 DAC6 Mux", "Slot1", "IF2 DAC1" }, 3393 { "IF2 DAC6 Mux", "Slot2", "IF2 DAC2" }, 3394 { "IF2 DAC6 Mux", "Slot3", "IF2 DAC3" }, 3395 { "IF2 DAC6 Mux", "Slot4", "IF2 DAC4" }, 3396 { "IF2 DAC6 Mux", "Slot5", "IF2 DAC5" }, 3397 { "IF2 DAC6 Mux", "Slot6", "IF2 DAC6" }, 3398 { "IF2 DAC6 Mux", "Slot7", "IF2 DAC7" }, 3399 3400 { "IF2 DAC7 Mux", "Slot0", "IF2 DAC0" }, 3401 { "IF2 DAC7 Mux", "Slot1", "IF2 DAC1" }, 3402 { "IF2 DAC7 Mux", "Slot2", "IF2 DAC2" }, 3403 { "IF2 DAC7 Mux", "Slot3", "IF2 DAC3" }, 3404 { "IF2 DAC7 Mux", "Slot4", "IF2 DAC4" }, 3405 { "IF2 DAC7 Mux", "Slot5", "IF2 DAC5" }, 3406 { "IF2 DAC7 Mux", "Slot6", "IF2 DAC6" }, 3407 { "IF2 DAC7 Mux", "Slot7", "IF2 DAC7" }, 3408 3409 { "IF2 DAC01", NULL, "IF2 DAC0 Mux" }, 3410 { "IF2 DAC01", NULL, "IF2 DAC1 Mux" }, 3411 { "IF2 DAC23", NULL, "IF2 DAC2 Mux" }, 3412 { "IF2 DAC23", NULL, "IF2 DAC3 Mux" }, 3413 { "IF2 DAC45", NULL, "IF2 DAC4 Mux" }, 3414 { "IF2 DAC45", NULL, "IF2 DAC5 Mux" }, 3415 { "IF2 DAC67", NULL, "IF2 DAC6 Mux" }, 3416 { "IF2 DAC67", NULL, "IF2 DAC7 Mux" }, 3417 3418 { "IF3 DAC", NULL, "AIF3RX" }, 3419 { "IF3 DAC", NULL, "I2S3" }, 3420 3421 { "IF4 DAC", NULL, "AIF4RX" }, 3422 { "IF4 DAC", NULL, "I2S4" }, 3423 3424 { "IF3 DAC L", NULL, "IF3 DAC" }, 3425 { "IF3 DAC R", NULL, "IF3 DAC" }, 3426 3427 { "IF4 DAC L", NULL, "IF4 DAC" }, 3428 { "IF4 DAC R", NULL, "IF4 DAC" }, 3429 3430 { "SLB DAC0", NULL, "SLBRX" }, 3431 { "SLB DAC1", NULL, "SLBRX" }, 3432 { "SLB DAC2", NULL, "SLBRX" }, 3433 { "SLB DAC3", NULL, "SLBRX" }, 3434 { "SLB DAC4", NULL, "SLBRX" }, 3435 { "SLB DAC5", NULL, "SLBRX" }, 3436 { "SLB DAC6", NULL, "SLBRX" }, 3437 { "SLB DAC7", NULL, "SLBRX" }, 3438 { "SLB DAC0", NULL, "SLB" }, 3439 { "SLB DAC1", NULL, "SLB" }, 3440 { "SLB DAC2", NULL, "SLB" }, 3441 { "SLB DAC3", NULL, "SLB" }, 3442 { "SLB DAC4", NULL, "SLB" }, 3443 { "SLB DAC5", NULL, "SLB" }, 3444 { "SLB DAC6", NULL, "SLB" }, 3445 { "SLB DAC7", NULL, "SLB" }, 3446 3447 { "SLB DAC01", NULL, "SLB DAC0" }, 3448 { "SLB DAC01", NULL, "SLB DAC1" }, 3449 { "SLB DAC23", NULL, "SLB DAC2" }, 3450 { "SLB DAC23", NULL, "SLB DAC3" }, 3451 { "SLB DAC45", NULL, "SLB DAC4" }, 3452 { "SLB DAC45", NULL, "SLB DAC5" }, 3453 { "SLB DAC67", NULL, "SLB DAC6" }, 3454 { "SLB DAC67", NULL, "SLB DAC7" }, 3455 3456 { "ADDA1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" }, 3457 { "ADDA1 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" }, 3458 { "ADDA1 Mux", "OB 67", "OB67" }, 3459 3460 { "DAC1 Mux", "IF1 DAC 01", "IF1 DAC01" }, 3461 { "DAC1 Mux", "IF2 DAC 01", "IF2 DAC01" }, 3462 { "DAC1 Mux", "IF3 DAC LR", "IF3 DAC" }, 3463 { "DAC1 Mux", "IF4 DAC LR", "IF4 DAC" }, 3464 { "DAC1 Mux", "SLB DAC 01", "SLB DAC01" }, 3465 { "DAC1 Mux", "OB 01", "OB01 Bypass Mux" }, 3466 3467 { "DAC1 MIXL", "Stereo ADC Switch", "ADDA1 Mux" }, 3468 { "DAC1 MIXL", "DAC1 Switch", "DAC1 Mux" }, 3469 { "DAC1 MIXL", NULL, "dac stereo1 filter" }, 3470 { "DAC1 MIXR", "Stereo ADC Switch", "ADDA1 Mux" }, 3471 { "DAC1 MIXR", "DAC1 Switch", "DAC1 Mux" }, 3472 { "DAC1 MIXR", NULL, "dac stereo1 filter" }, 3473 3474 { "DAC1 FS", NULL, "DAC1 MIXL" }, 3475 { "DAC1 FS", NULL, "DAC1 MIXR" }, 3476 3477 { "DAC2 L Mux", "IF1 DAC 2", "IF1 DAC2" }, 3478 { "DAC2 L Mux", "IF2 DAC 2", "IF2 DAC2" }, 3479 { "DAC2 L Mux", "IF3 DAC L", "IF3 DAC L" }, 3480 { "DAC2 L Mux", "IF4 DAC L", "IF4 DAC L" }, 3481 { "DAC2 L Mux", "SLB DAC 2", "SLB DAC2" }, 3482 { "DAC2 L Mux", "OB 2", "OutBound2" }, 3483 3484 { "DAC2 R Mux", "IF1 DAC 3", "IF1 DAC3" }, 3485 { "DAC2 R Mux", "IF2 DAC 3", "IF2 DAC3" }, 3486 { "DAC2 R Mux", "IF3 DAC R", "IF3 DAC R" }, 3487 { "DAC2 R Mux", "IF4 DAC R", "IF4 DAC R" }, 3488 { "DAC2 R Mux", "SLB DAC 3", "SLB DAC3" }, 3489 { "DAC2 R Mux", "OB 3", "OutBound3" }, 3490 { "DAC2 R Mux", "Haptic Generator", "Haptic Generator" }, 3491 { "DAC2 R Mux", "VAD ADC", "VAD ADC Mux" }, 3492 3493 { "DAC3 L Mux", "IF1 DAC 4", "IF1 DAC4" }, 3494 { "DAC3 L Mux", "IF2 DAC 4", "IF2 DAC4" }, 3495 { "DAC3 L Mux", "IF3 DAC L", "IF3 DAC L" }, 3496 { "DAC3 L Mux", "IF4 DAC L", "IF4 DAC L" }, 3497 { "DAC3 L Mux", "SLB DAC 4", "SLB DAC4" }, 3498 { "DAC3 L Mux", "OB 4", "OutBound4" }, 3499 3500 { "DAC3 R Mux", "IF1 DAC 5", "IF1 DAC4" }, 3501 { "DAC3 R Mux", "IF2 DAC 5", "IF2 DAC4" }, 3502 { "DAC3 R Mux", "IF3 DAC R", "IF3 DAC R" }, 3503 { "DAC3 R Mux", "IF4 DAC R", "IF4 DAC R" }, 3504 { "DAC3 R Mux", "SLB DAC 5", "SLB DAC5" }, 3505 { "DAC3 R Mux", "OB 5", "OutBound5" }, 3506 3507 { "DAC4 L Mux", "IF1 DAC 6", "IF1 DAC6" }, 3508 { "DAC4 L Mux", "IF2 DAC 6", "IF2 DAC6" }, 3509 { "DAC4 L Mux", "IF3 DAC L", "IF3 DAC L" }, 3510 { "DAC4 L Mux", "IF4 DAC L", "IF4 DAC L" }, 3511 { "DAC4 L Mux", "SLB DAC 6", "SLB DAC6" }, 3512 { "DAC4 L Mux", "OB 6", "OutBound6" }, 3513 3514 { "DAC4 R Mux", "IF1 DAC 7", "IF1 DAC7" }, 3515 { "DAC4 R Mux", "IF2 DAC 7", "IF2 DAC7" }, 3516 { "DAC4 R Mux", "IF3 DAC R", "IF3 DAC R" }, 3517 { "DAC4 R Mux", "IF4 DAC R", "IF4 DAC R" }, 3518 { "DAC4 R Mux", "SLB DAC 7", "SLB DAC7" }, 3519 { "DAC4 R Mux", "OB 7", "OutBound7" }, 3520 3521 { "Sidetone Mux", "DMIC1 L", "DMIC L1" }, 3522 { "Sidetone Mux", "DMIC2 L", "DMIC L2" }, 3523 { "Sidetone Mux", "DMIC3 L", "DMIC L3" }, 3524 { "Sidetone Mux", "DMIC4 L", "DMIC L4" }, 3525 { "Sidetone Mux", "ADC1", "ADC 1" }, 3526 { "Sidetone Mux", "ADC2", "ADC 2" }, 3527 { "Sidetone Mux", NULL, "Sidetone Power" }, 3528 3529 { "Stereo DAC MIXL", "ST L Switch", "Sidetone Mux" }, 3530 { "Stereo DAC MIXL", "DAC1 L Switch", "DAC1 MIXL" }, 3531 { "Stereo DAC MIXL", "DAC2 L Switch", "DAC2 L Mux" }, 3532 { "Stereo DAC MIXL", "DAC1 R Switch", "DAC1 MIXR" }, 3533 { "Stereo DAC MIXL", NULL, "dac stereo1 filter" }, 3534 { "Stereo DAC MIXR", "ST R Switch", "Sidetone Mux" }, 3535 { "Stereo DAC MIXR", "DAC1 R Switch", "DAC1 MIXR" }, 3536 { "Stereo DAC MIXR", "DAC2 R Switch", "DAC2 R Mux" }, 3537 { "Stereo DAC MIXR", "DAC1 L Switch", "DAC1 MIXL" }, 3538 { "Stereo DAC MIXR", NULL, "dac stereo1 filter" }, 3539 3540 { "Mono DAC MIXL", "ST L Switch", "Sidetone Mux" }, 3541 { "Mono DAC MIXL", "DAC1 L Switch", "DAC1 MIXL" }, 3542 { "Mono DAC MIXL", "DAC2 L Switch", "DAC2 L Mux" }, 3543 { "Mono DAC MIXL", "DAC2 R Switch", "DAC2 R Mux" }, 3544 { "Mono DAC MIXL", NULL, "dac mono left filter" }, 3545 { "Mono DAC MIXR", "ST R Switch", "Sidetone Mux" }, 3546 { "Mono DAC MIXR", "DAC1 R Switch", "DAC1 MIXR" }, 3547 { "Mono DAC MIXR", "DAC2 R Switch", "DAC2 R Mux" }, 3548 { "Mono DAC MIXR", "DAC2 L Switch", "DAC2 L Mux" }, 3549 { "Mono DAC MIXR", NULL, "dac mono right filter" }, 3550 3551 { "DD1 MIXL", "Sto DAC Mix L Switch", "Stereo DAC MIXL" }, 3552 { "DD1 MIXL", "Mono DAC Mix L Switch", "Mono DAC MIXL" }, 3553 { "DD1 MIXL", "DAC3 L Switch", "DAC3 L Mux" }, 3554 { "DD1 MIXL", "DAC3 R Switch", "DAC3 R Mux" }, 3555 { "DD1 MIXR", "Sto DAC Mix R Switch", "Stereo DAC MIXR" }, 3556 { "DD1 MIXR", "Mono DAC Mix R Switch", "Mono DAC MIXR" }, 3557 { "DD1 MIXR", "DAC3 L Switch", "DAC3 L Mux" }, 3558 { "DD1 MIXR", "DAC3 R Switch", "DAC3 R Mux" }, 3559 3560 { "DD2 MIXL", "Sto DAC Mix L Switch", "Stereo DAC MIXL" }, 3561 { "DD2 MIXL", "Mono DAC Mix L Switch", "Mono DAC MIXL" }, 3562 { "DD2 MIXL", "DAC4 L Switch", "DAC4 L Mux" }, 3563 { "DD2 MIXL", "DAC4 R Switch", "DAC4 R Mux" }, 3564 { "DD2 MIXR", "Sto DAC Mix R Switch", "Stereo DAC MIXR" }, 3565 { "DD2 MIXR", "Mono DAC Mix R Switch", "Mono DAC MIXR" }, 3566 { "DD2 MIXR", "DAC4 L Switch", "DAC4 L Mux" }, 3567 { "DD2 MIXR", "DAC4 R Switch", "DAC4 R Mux" }, 3568 3569 { "Stereo DAC MIX", NULL, "Stereo DAC MIXL" }, 3570 { "Stereo DAC MIX", NULL, "Stereo DAC MIXR" }, 3571 { "Mono DAC MIX", NULL, "Mono DAC MIXL" }, 3572 { "Mono DAC MIX", NULL, "Mono DAC MIXR" }, 3573 { "DD1 MIX", NULL, "DD1 MIXL" }, 3574 { "DD1 MIX", NULL, "DD1 MIXR" }, 3575 { "DD2 MIX", NULL, "DD2 MIXL" }, 3576 { "DD2 MIX", NULL, "DD2 MIXR" }, 3577 3578 { "DAC12 SRC Mux", "STO1 DAC MIX", "Stereo DAC MIX" }, 3579 { "DAC12 SRC Mux", "MONO DAC MIX", "Mono DAC MIX" }, 3580 { "DAC12 SRC Mux", "DD MIX1", "DD1 MIX" }, 3581 { "DAC12 SRC Mux", "DD MIX2", "DD2 MIX" }, 3582 3583 { "DAC3 SRC Mux", "MONO DAC MIXL", "Mono DAC MIXL" }, 3584 { "DAC3 SRC Mux", "MONO DAC MIXR", "Mono DAC MIXR" }, 3585 { "DAC3 SRC Mux", "DD MIX1L", "DD1 MIXL" }, 3586 { "DAC3 SRC Mux", "DD MIX2L", "DD2 MIXL" }, 3587 3588 { "DAC 1", NULL, "DAC12 SRC Mux" }, 3589 { "DAC 1", NULL, "PLL1", is_sys_clk_from_pll }, 3590 { "DAC 2", NULL, "DAC12 SRC Mux" }, 3591 { "DAC 2", NULL, "PLL1", is_sys_clk_from_pll }, 3592 { "DAC 3", NULL, "DAC3 SRC Mux" }, 3593 { "DAC 3", NULL, "PLL1", is_sys_clk_from_pll }, 3594 3595 { "PDM1 L Mux", "STO1 DAC MIX", "Stereo DAC MIXL" }, 3596 { "PDM1 L Mux", "MONO DAC MIX", "Mono DAC MIXL" }, 3597 { "PDM1 L Mux", "DD MIX1", "DD1 MIXL" }, 3598 { "PDM1 L Mux", "DD MIX2", "DD2 MIXL" }, 3599 { "PDM1 L Mux", NULL, "PDM1 Power" }, 3600 { "PDM1 R Mux", "STO1 DAC MIX", "Stereo DAC MIXR" }, 3601 { "PDM1 R Mux", "MONO DAC MIX", "Mono DAC MIXR" }, 3602 { "PDM1 R Mux", "DD MIX1", "DD1 MIXR" }, 3603 { "PDM1 R Mux", "DD MIX2", "DD2 MIXR" }, 3604 { "PDM1 R Mux", NULL, "PDM1 Power" }, 3605 { "PDM2 L Mux", "STO1 DAC MIX", "Stereo DAC MIXL" }, 3606 { "PDM2 L Mux", "MONO DAC MIX", "Mono DAC MIXL" }, 3607 { "PDM2 L Mux", "DD MIX1", "DD1 MIXL" }, 3608 { "PDM2 L Mux", "DD MIX2", "DD2 MIXL" }, 3609 { "PDM2 L Mux", NULL, "PDM2 Power" }, 3610 { "PDM2 R Mux", "STO1 DAC MIX", "Stereo DAC MIXR" }, 3611 { "PDM2 R Mux", "MONO DAC MIX", "Mono DAC MIXR" }, 3612 { "PDM2 R Mux", "DD MIX1", "DD1 MIXR" }, 3613 { "PDM2 R Mux", "DD MIX1", "DD2 MIXR" }, 3614 { "PDM2 R Mux", NULL, "PDM2 Power" }, 3615 3616 { "LOUT1 amp", NULL, "DAC 1" }, 3617 { "LOUT2 amp", NULL, "DAC 2" }, 3618 { "LOUT3 amp", NULL, "DAC 3" }, 3619 3620 { "LOUT1 vref", NULL, "LOUT1 amp" }, 3621 { "LOUT2 vref", NULL, "LOUT2 amp" }, 3622 { "LOUT3 vref", NULL, "LOUT3 amp" }, 3623 3624 { "LOUT1", NULL, "LOUT1 vref" }, 3625 { "LOUT2", NULL, "LOUT2 vref" }, 3626 { "LOUT3", NULL, "LOUT3 vref" }, 3627 3628 { "PDM1L", NULL, "PDM1 L Mux" }, 3629 { "PDM1R", NULL, "PDM1 R Mux" }, 3630 { "PDM2L", NULL, "PDM2 L Mux" }, 3631 { "PDM2R", NULL, "PDM2 R Mux" }, 3632 }; 3633 3634 static const struct snd_soc_dapm_route rt5677_dmic2_clk_1[] = { 3635 { "DMIC L2", NULL, "DMIC1 power" }, 3636 { "DMIC R2", NULL, "DMIC1 power" }, 3637 }; 3638 3639 static const struct snd_soc_dapm_route rt5677_dmic2_clk_2[] = { 3640 { "DMIC L2", NULL, "DMIC2 power" }, 3641 { "DMIC R2", NULL, "DMIC2 power" }, 3642 }; 3643 3644 static int rt5677_hw_params(struct snd_pcm_substream *substream, 3645 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) 3646 { 3647 struct snd_soc_codec *codec = dai->codec; 3648 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec); 3649 unsigned int val_len = 0, val_clk, mask_clk; 3650 int pre_div, bclk_ms, frame_size; 3651 3652 rt5677->lrck[dai->id] = params_rate(params); 3653 pre_div = rl6231_get_clk_info(rt5677->sysclk, rt5677->lrck[dai->id]); 3654 if (pre_div < 0) { 3655 dev_err(codec->dev, "Unsupported clock setting: sysclk=%dHz lrck=%dHz\n", 3656 rt5677->sysclk, rt5677->lrck[dai->id]); 3657 return -EINVAL; 3658 } 3659 frame_size = snd_soc_params_to_frame_size(params); 3660 if (frame_size < 0) { 3661 dev_err(codec->dev, "Unsupported frame size: %d\n", frame_size); 3662 return -EINVAL; 3663 } 3664 bclk_ms = frame_size > 32; 3665 rt5677->bclk[dai->id] = rt5677->lrck[dai->id] * (32 << bclk_ms); 3666 3667 dev_dbg(dai->dev, "bclk is %dHz and lrck is %dHz\n", 3668 rt5677->bclk[dai->id], rt5677->lrck[dai->id]); 3669 dev_dbg(dai->dev, "bclk_ms is %d and pre_div is %d for iis %d\n", 3670 bclk_ms, pre_div, dai->id); 3671 3672 switch (params_width(params)) { 3673 case 16: 3674 break; 3675 case 20: 3676 val_len |= RT5677_I2S_DL_20; 3677 break; 3678 case 24: 3679 val_len |= RT5677_I2S_DL_24; 3680 break; 3681 case 8: 3682 val_len |= RT5677_I2S_DL_8; 3683 break; 3684 default: 3685 return -EINVAL; 3686 } 3687 3688 switch (dai->id) { 3689 case RT5677_AIF1: 3690 mask_clk = RT5677_I2S_PD1_MASK; 3691 val_clk = pre_div << RT5677_I2S_PD1_SFT; 3692 regmap_update_bits(rt5677->regmap, RT5677_I2S1_SDP, 3693 RT5677_I2S_DL_MASK, val_len); 3694 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1, 3695 mask_clk, val_clk); 3696 break; 3697 case RT5677_AIF2: 3698 mask_clk = RT5677_I2S_PD2_MASK; 3699 val_clk = pre_div << RT5677_I2S_PD2_SFT; 3700 regmap_update_bits(rt5677->regmap, RT5677_I2S2_SDP, 3701 RT5677_I2S_DL_MASK, val_len); 3702 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1, 3703 mask_clk, val_clk); 3704 break; 3705 case RT5677_AIF3: 3706 mask_clk = RT5677_I2S_BCLK_MS3_MASK | RT5677_I2S_PD3_MASK; 3707 val_clk = bclk_ms << RT5677_I2S_BCLK_MS3_SFT | 3708 pre_div << RT5677_I2S_PD3_SFT; 3709 regmap_update_bits(rt5677->regmap, RT5677_I2S3_SDP, 3710 RT5677_I2S_DL_MASK, val_len); 3711 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1, 3712 mask_clk, val_clk); 3713 break; 3714 case RT5677_AIF4: 3715 mask_clk = RT5677_I2S_BCLK_MS4_MASK | RT5677_I2S_PD4_MASK; 3716 val_clk = bclk_ms << RT5677_I2S_BCLK_MS4_SFT | 3717 pre_div << RT5677_I2S_PD4_SFT; 3718 regmap_update_bits(rt5677->regmap, RT5677_I2S4_SDP, 3719 RT5677_I2S_DL_MASK, val_len); 3720 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1, 3721 mask_clk, val_clk); 3722 break; 3723 default: 3724 break; 3725 } 3726 3727 return 0; 3728 } 3729 3730 static int rt5677_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) 3731 { 3732 struct snd_soc_codec *codec = dai->codec; 3733 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec); 3734 unsigned int reg_val = 0; 3735 3736 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 3737 case SND_SOC_DAIFMT_CBM_CFM: 3738 rt5677->master[dai->id] = 1; 3739 break; 3740 case SND_SOC_DAIFMT_CBS_CFS: 3741 reg_val |= RT5677_I2S_MS_S; 3742 rt5677->master[dai->id] = 0; 3743 break; 3744 default: 3745 return -EINVAL; 3746 } 3747 3748 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 3749 case SND_SOC_DAIFMT_NB_NF: 3750 break; 3751 case SND_SOC_DAIFMT_IB_NF: 3752 reg_val |= RT5677_I2S_BP_INV; 3753 break; 3754 default: 3755 return -EINVAL; 3756 } 3757 3758 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 3759 case SND_SOC_DAIFMT_I2S: 3760 break; 3761 case SND_SOC_DAIFMT_LEFT_J: 3762 reg_val |= RT5677_I2S_DF_LEFT; 3763 break; 3764 case SND_SOC_DAIFMT_DSP_A: 3765 reg_val |= RT5677_I2S_DF_PCM_A; 3766 break; 3767 case SND_SOC_DAIFMT_DSP_B: 3768 reg_val |= RT5677_I2S_DF_PCM_B; 3769 break; 3770 default: 3771 return -EINVAL; 3772 } 3773 3774 switch (dai->id) { 3775 case RT5677_AIF1: 3776 regmap_update_bits(rt5677->regmap, RT5677_I2S1_SDP, 3777 RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK | 3778 RT5677_I2S_DF_MASK, reg_val); 3779 break; 3780 case RT5677_AIF2: 3781 regmap_update_bits(rt5677->regmap, RT5677_I2S2_SDP, 3782 RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK | 3783 RT5677_I2S_DF_MASK, reg_val); 3784 break; 3785 case RT5677_AIF3: 3786 regmap_update_bits(rt5677->regmap, RT5677_I2S3_SDP, 3787 RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK | 3788 RT5677_I2S_DF_MASK, reg_val); 3789 break; 3790 case RT5677_AIF4: 3791 regmap_update_bits(rt5677->regmap, RT5677_I2S4_SDP, 3792 RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK | 3793 RT5677_I2S_DF_MASK, reg_val); 3794 break; 3795 default: 3796 break; 3797 } 3798 3799 3800 return 0; 3801 } 3802 3803 static int rt5677_set_dai_sysclk(struct snd_soc_dai *dai, 3804 int clk_id, unsigned int freq, int dir) 3805 { 3806 struct snd_soc_codec *codec = dai->codec; 3807 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec); 3808 unsigned int reg_val = 0; 3809 3810 if (freq == rt5677->sysclk && clk_id == rt5677->sysclk_src) 3811 return 0; 3812 3813 switch (clk_id) { 3814 case RT5677_SCLK_S_MCLK: 3815 reg_val |= RT5677_SCLK_SRC_MCLK; 3816 break; 3817 case RT5677_SCLK_S_PLL1: 3818 reg_val |= RT5677_SCLK_SRC_PLL1; 3819 break; 3820 case RT5677_SCLK_S_RCCLK: 3821 reg_val |= RT5677_SCLK_SRC_RCCLK; 3822 break; 3823 default: 3824 dev_err(codec->dev, "Invalid clock id (%d)\n", clk_id); 3825 return -EINVAL; 3826 } 3827 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1, 3828 RT5677_SCLK_SRC_MASK, reg_val); 3829 rt5677->sysclk = freq; 3830 rt5677->sysclk_src = clk_id; 3831 3832 dev_dbg(dai->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id); 3833 3834 return 0; 3835 } 3836 3837 /** 3838 * rt5677_pll_calc - Calcualte PLL M/N/K code. 3839 * @freq_in: external clock provided to codec. 3840 * @freq_out: target clock which codec works on. 3841 * @pll_code: Pointer to structure with M, N, K, bypass K and bypass M flag. 3842 * 3843 * Calcualte M/N/K code and bypass K/M flag to configure PLL for codec. 3844 * 3845 * Returns 0 for success or negative error code. 3846 */ 3847 static int rt5677_pll_calc(const unsigned int freq_in, 3848 const unsigned int freq_out, struct rl6231_pll_code *pll_code) 3849 { 3850 if (RT5677_PLL_INP_MIN > freq_in) 3851 return -EINVAL; 3852 3853 return rl6231_pll_calc(freq_in, freq_out, pll_code); 3854 } 3855 3856 static int rt5677_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source, 3857 unsigned int freq_in, unsigned int freq_out) 3858 { 3859 struct snd_soc_codec *codec = dai->codec; 3860 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec); 3861 struct rl6231_pll_code pll_code; 3862 int ret; 3863 3864 if (source == rt5677->pll_src && freq_in == rt5677->pll_in && 3865 freq_out == rt5677->pll_out) 3866 return 0; 3867 3868 if (!freq_in || !freq_out) { 3869 dev_dbg(codec->dev, "PLL disabled\n"); 3870 3871 rt5677->pll_in = 0; 3872 rt5677->pll_out = 0; 3873 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1, 3874 RT5677_SCLK_SRC_MASK, RT5677_SCLK_SRC_MCLK); 3875 return 0; 3876 } 3877 3878 switch (source) { 3879 case RT5677_PLL1_S_MCLK: 3880 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1, 3881 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_MCLK); 3882 break; 3883 case RT5677_PLL1_S_BCLK1: 3884 case RT5677_PLL1_S_BCLK2: 3885 case RT5677_PLL1_S_BCLK3: 3886 case RT5677_PLL1_S_BCLK4: 3887 switch (dai->id) { 3888 case RT5677_AIF1: 3889 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1, 3890 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK1); 3891 break; 3892 case RT5677_AIF2: 3893 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1, 3894 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK2); 3895 break; 3896 case RT5677_AIF3: 3897 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1, 3898 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK3); 3899 break; 3900 case RT5677_AIF4: 3901 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1, 3902 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK4); 3903 break; 3904 default: 3905 break; 3906 } 3907 break; 3908 default: 3909 dev_err(codec->dev, "Unknown PLL source %d\n", source); 3910 return -EINVAL; 3911 } 3912 3913 ret = rt5677_pll_calc(freq_in, freq_out, &pll_code); 3914 if (ret < 0) { 3915 dev_err(codec->dev, "Unsupport input clock %d\n", freq_in); 3916 return ret; 3917 } 3918 3919 dev_dbg(codec->dev, "m_bypass=%d m=%d n=%d k=%d\n", 3920 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code), 3921 pll_code.n_code, pll_code.k_code); 3922 3923 regmap_write(rt5677->regmap, RT5677_PLL1_CTRL1, 3924 pll_code.n_code << RT5677_PLL_N_SFT | pll_code.k_code); 3925 regmap_write(rt5677->regmap, RT5677_PLL1_CTRL2, 3926 (pll_code.m_bp ? 0 : pll_code.m_code) << RT5677_PLL_M_SFT | 3927 pll_code.m_bp << RT5677_PLL_M_BP_SFT); 3928 3929 rt5677->pll_in = freq_in; 3930 rt5677->pll_out = freq_out; 3931 rt5677->pll_src = source; 3932 3933 return 0; 3934 } 3935 3936 static int rt5677_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask, 3937 unsigned int rx_mask, int slots, int slot_width) 3938 { 3939 struct snd_soc_codec *codec = dai->codec; 3940 unsigned int val = 0; 3941 3942 if (rx_mask || tx_mask) 3943 val |= (1 << 12); 3944 3945 switch (slots) { 3946 case 4: 3947 val |= (1 << 10); 3948 break; 3949 case 6: 3950 val |= (2 << 10); 3951 break; 3952 case 8: 3953 val |= (3 << 10); 3954 break; 3955 case 2: 3956 default: 3957 break; 3958 } 3959 3960 switch (slot_width) { 3961 case 20: 3962 val |= (1 << 8); 3963 break; 3964 case 24: 3965 val |= (2 << 8); 3966 break; 3967 case 32: 3968 val |= (3 << 8); 3969 break; 3970 case 16: 3971 default: 3972 break; 3973 } 3974 3975 switch (dai->id) { 3976 case RT5677_AIF1: 3977 snd_soc_update_bits(codec, RT5677_TDM1_CTRL1, 0x1f00, val); 3978 break; 3979 case RT5677_AIF2: 3980 snd_soc_update_bits(codec, RT5677_TDM2_CTRL1, 0x1f00, val); 3981 break; 3982 default: 3983 break; 3984 } 3985 3986 return 0; 3987 } 3988 3989 static int rt5677_set_bias_level(struct snd_soc_codec *codec, 3990 enum snd_soc_bias_level level) 3991 { 3992 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec); 3993 3994 switch (level) { 3995 case SND_SOC_BIAS_ON: 3996 break; 3997 3998 case SND_SOC_BIAS_PREPARE: 3999 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY) { 4000 rt5677_set_dsp_vad(codec, false); 4001 4002 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1, 4003 RT5677_LDO1_SEL_MASK | RT5677_LDO2_SEL_MASK, 4004 0x0055); 4005 regmap_update_bits(rt5677->regmap, 4006 RT5677_PR_BASE + RT5677_BIAS_CUR4, 4007 0x0f00, 0x0f00); 4008 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1, 4009 RT5677_PWR_FV1 | RT5677_PWR_FV2 | 4010 RT5677_PWR_VREF1 | RT5677_PWR_MB | 4011 RT5677_PWR_BG | RT5677_PWR_VREF2, 4012 RT5677_PWR_VREF1 | RT5677_PWR_MB | 4013 RT5677_PWR_BG | RT5677_PWR_VREF2); 4014 rt5677->is_vref_slow = false; 4015 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2, 4016 RT5677_PWR_CORE, RT5677_PWR_CORE); 4017 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 4018 0x1, 0x1); 4019 } 4020 break; 4021 4022 case SND_SOC_BIAS_STANDBY: 4023 break; 4024 4025 case SND_SOC_BIAS_OFF: 4026 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x1, 0x0); 4027 regmap_write(rt5677->regmap, RT5677_PWR_DIG1, 0x0000); 4028 regmap_write(rt5677->regmap, RT5677_PWR_DIG2, 0x0000); 4029 regmap_write(rt5677->regmap, RT5677_PWR_ANLG1, 0x0022); 4030 regmap_write(rt5677->regmap, RT5677_PWR_ANLG2, 0x0000); 4031 regmap_update_bits(rt5677->regmap, 4032 RT5677_PR_BASE + RT5677_BIAS_CUR4, 0x0f00, 0x0000); 4033 4034 if (rt5677->dsp_vad_en) 4035 rt5677_set_dsp_vad(codec, true); 4036 break; 4037 4038 default: 4039 break; 4040 } 4041 codec->dapm.bias_level = level; 4042 4043 return 0; 4044 } 4045 4046 #ifdef CONFIG_GPIOLIB 4047 static inline struct rt5677_priv *gpio_to_rt5677(struct gpio_chip *chip) 4048 { 4049 return container_of(chip, struct rt5677_priv, gpio_chip); 4050 } 4051 4052 static void rt5677_gpio_set(struct gpio_chip *chip, unsigned offset, int value) 4053 { 4054 struct rt5677_priv *rt5677 = gpio_to_rt5677(chip); 4055 4056 switch (offset) { 4057 case RT5677_GPIO1 ... RT5677_GPIO5: 4058 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2, 4059 0x1 << (offset * 3 + 1), !!value << (offset * 3 + 1)); 4060 break; 4061 4062 case RT5677_GPIO6: 4063 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL3, 4064 RT5677_GPIO6_OUT_MASK, !!value << RT5677_GPIO6_OUT_SFT); 4065 break; 4066 4067 default: 4068 break; 4069 } 4070 } 4071 4072 static int rt5677_gpio_direction_out(struct gpio_chip *chip, 4073 unsigned offset, int value) 4074 { 4075 struct rt5677_priv *rt5677 = gpio_to_rt5677(chip); 4076 4077 switch (offset) { 4078 case RT5677_GPIO1 ... RT5677_GPIO5: 4079 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2, 4080 0x3 << (offset * 3 + 1), 4081 (0x2 | !!value) << (offset * 3 + 1)); 4082 break; 4083 4084 case RT5677_GPIO6: 4085 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL3, 4086 RT5677_GPIO6_DIR_MASK | RT5677_GPIO6_OUT_MASK, 4087 RT5677_GPIO6_DIR_OUT | !!value << RT5677_GPIO6_OUT_SFT); 4088 break; 4089 4090 default: 4091 break; 4092 } 4093 4094 return 0; 4095 } 4096 4097 static int rt5677_gpio_get(struct gpio_chip *chip, unsigned offset) 4098 { 4099 struct rt5677_priv *rt5677 = gpio_to_rt5677(chip); 4100 int value, ret; 4101 4102 ret = regmap_read(rt5677->regmap, RT5677_GPIO_ST, &value); 4103 if (ret < 0) 4104 return ret; 4105 4106 return (value & (0x1 << offset)) >> offset; 4107 } 4108 4109 static int rt5677_gpio_direction_in(struct gpio_chip *chip, unsigned offset) 4110 { 4111 struct rt5677_priv *rt5677 = gpio_to_rt5677(chip); 4112 4113 switch (offset) { 4114 case RT5677_GPIO1 ... RT5677_GPIO5: 4115 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2, 4116 0x1 << (offset * 3 + 2), 0x0); 4117 break; 4118 4119 case RT5677_GPIO6: 4120 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL3, 4121 RT5677_GPIO6_DIR_MASK, RT5677_GPIO6_DIR_IN); 4122 break; 4123 4124 default: 4125 break; 4126 } 4127 4128 return 0; 4129 } 4130 4131 /** Configures the gpio as 4132 * 0 - floating 4133 * 1 - pull down 4134 * 2 - pull up 4135 */ 4136 static void rt5677_gpio_config(struct rt5677_priv *rt5677, unsigned offset, 4137 int value) 4138 { 4139 int shift; 4140 4141 switch (offset) { 4142 case RT5677_GPIO1 ... RT5677_GPIO2: 4143 shift = 2 * (1 - offset); 4144 regmap_update_bits(rt5677->regmap, 4145 RT5677_PR_BASE + RT5677_DIG_IN_PIN_ST_CTRL2, 4146 0x3 << shift, 4147 (value & 0x3) << shift); 4148 break; 4149 4150 case RT5677_GPIO3 ... RT5677_GPIO6: 4151 shift = 2 * (9 - offset); 4152 regmap_update_bits(rt5677->regmap, 4153 RT5677_PR_BASE + RT5677_DIG_IN_PIN_ST_CTRL3, 4154 0x3 << shift, 4155 (value & 0x3) << shift); 4156 break; 4157 4158 default: 4159 break; 4160 } 4161 } 4162 4163 static int rt5677_to_irq(struct gpio_chip *chip, unsigned offset) 4164 { 4165 struct rt5677_priv *rt5677 = gpio_to_rt5677(chip); 4166 struct regmap_irq_chip_data *data = rt5677->irq_data; 4167 int irq; 4168 4169 if (offset >= RT5677_GPIO1 && offset <= RT5677_GPIO3) { 4170 if ((rt5677->pdata.jd1_gpio == 1 && offset == RT5677_GPIO1) || 4171 (rt5677->pdata.jd1_gpio == 2 && 4172 offset == RT5677_GPIO2) || 4173 (rt5677->pdata.jd1_gpio == 3 && 4174 offset == RT5677_GPIO3)) { 4175 irq = RT5677_IRQ_JD1; 4176 } else { 4177 return -ENXIO; 4178 } 4179 } 4180 4181 if (offset >= RT5677_GPIO4 && offset <= RT5677_GPIO6) { 4182 if ((rt5677->pdata.jd2_gpio == 1 && offset == RT5677_GPIO4) || 4183 (rt5677->pdata.jd2_gpio == 2 && 4184 offset == RT5677_GPIO5) || 4185 (rt5677->pdata.jd2_gpio == 3 && 4186 offset == RT5677_GPIO6)) { 4187 irq = RT5677_IRQ_JD2; 4188 } else if ((rt5677->pdata.jd3_gpio == 1 && 4189 offset == RT5677_GPIO4) || 4190 (rt5677->pdata.jd3_gpio == 2 && 4191 offset == RT5677_GPIO5) || 4192 (rt5677->pdata.jd3_gpio == 3 && 4193 offset == RT5677_GPIO6)) { 4194 irq = RT5677_IRQ_JD3; 4195 } else { 4196 return -ENXIO; 4197 } 4198 } 4199 4200 return regmap_irq_get_virq(data, irq); 4201 } 4202 4203 static struct gpio_chip rt5677_template_chip = { 4204 .label = "rt5677", 4205 .owner = THIS_MODULE, 4206 .direction_output = rt5677_gpio_direction_out, 4207 .set = rt5677_gpio_set, 4208 .direction_input = rt5677_gpio_direction_in, 4209 .get = rt5677_gpio_get, 4210 .to_irq = rt5677_to_irq, 4211 .can_sleep = 1, 4212 }; 4213 4214 static void rt5677_init_gpio(struct i2c_client *i2c) 4215 { 4216 struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c); 4217 int ret; 4218 4219 rt5677->gpio_chip = rt5677_template_chip; 4220 rt5677->gpio_chip.ngpio = RT5677_GPIO_NUM; 4221 rt5677->gpio_chip.dev = &i2c->dev; 4222 rt5677->gpio_chip.base = -1; 4223 4224 ret = gpiochip_add(&rt5677->gpio_chip); 4225 if (ret != 0) 4226 dev_err(&i2c->dev, "Failed to add GPIOs: %d\n", ret); 4227 } 4228 4229 static void rt5677_free_gpio(struct i2c_client *i2c) 4230 { 4231 struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c); 4232 4233 gpiochip_remove(&rt5677->gpio_chip); 4234 } 4235 #else 4236 static void rt5677_gpio_config(struct rt5677_priv *rt5677, unsigned offset, 4237 int value) 4238 { 4239 } 4240 4241 static void rt5677_init_gpio(struct i2c_client *i2c) 4242 { 4243 } 4244 4245 static void rt5677_free_gpio(struct i2c_client *i2c) 4246 { 4247 } 4248 #endif 4249 4250 static int rt5677_probe(struct snd_soc_codec *codec) 4251 { 4252 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec); 4253 int i; 4254 4255 rt5677->codec = codec; 4256 4257 if (rt5677->pdata.dmic2_clk_pin == RT5677_DMIC_CLK2) { 4258 snd_soc_dapm_add_routes(&codec->dapm, 4259 rt5677_dmic2_clk_2, 4260 ARRAY_SIZE(rt5677_dmic2_clk_2)); 4261 } else { /*use dmic1 clock by default*/ 4262 snd_soc_dapm_add_routes(&codec->dapm, 4263 rt5677_dmic2_clk_1, 4264 ARRAY_SIZE(rt5677_dmic2_clk_1)); 4265 } 4266 4267 rt5677_set_bias_level(codec, SND_SOC_BIAS_OFF); 4268 4269 regmap_write(rt5677->regmap, RT5677_DIG_MISC, 0x0020); 4270 regmap_write(rt5677->regmap, RT5677_PWR_DSP2, 0x0c00); 4271 4272 for (i = 0; i < RT5677_GPIO_NUM; i++) 4273 rt5677_gpio_config(rt5677, i, rt5677->pdata.gpio_config[i]); 4274 4275 if (rt5677->irq_data) { 4276 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL1, 0x8000, 4277 0x8000); 4278 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x0018, 4279 0x0008); 4280 4281 if (rt5677->pdata.jd1_gpio) 4282 regmap_update_bits(rt5677->regmap, RT5677_JD_CTRL1, 4283 RT5677_SEL_GPIO_JD1_MASK, 4284 rt5677->pdata.jd1_gpio << 4285 RT5677_SEL_GPIO_JD1_SFT); 4286 4287 if (rt5677->pdata.jd2_gpio) 4288 regmap_update_bits(rt5677->regmap, RT5677_JD_CTRL1, 4289 RT5677_SEL_GPIO_JD2_MASK, 4290 rt5677->pdata.jd2_gpio << 4291 RT5677_SEL_GPIO_JD2_SFT); 4292 4293 if (rt5677->pdata.jd3_gpio) 4294 regmap_update_bits(rt5677->regmap, RT5677_JD_CTRL1, 4295 RT5677_SEL_GPIO_JD3_MASK, 4296 rt5677->pdata.jd3_gpio << 4297 RT5677_SEL_GPIO_JD3_SFT); 4298 } 4299 4300 mutex_init(&rt5677->dsp_cmd_lock); 4301 mutex_init(&rt5677->dsp_pri_lock); 4302 4303 return 0; 4304 } 4305 4306 static int rt5677_remove(struct snd_soc_codec *codec) 4307 { 4308 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec); 4309 4310 regmap_write(rt5677->regmap, RT5677_RESET, 0x10ec); 4311 if (gpio_is_valid(rt5677->pow_ldo2)) 4312 gpio_set_value_cansleep(rt5677->pow_ldo2, 0); 4313 4314 return 0; 4315 } 4316 4317 #ifdef CONFIG_PM 4318 static int rt5677_suspend(struct snd_soc_codec *codec) 4319 { 4320 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec); 4321 4322 if (!rt5677->dsp_vad_en) { 4323 regcache_cache_only(rt5677->regmap, true); 4324 regcache_mark_dirty(rt5677->regmap); 4325 } 4326 4327 if (gpio_is_valid(rt5677->pow_ldo2)) 4328 gpio_set_value_cansleep(rt5677->pow_ldo2, 0); 4329 4330 return 0; 4331 } 4332 4333 static int rt5677_resume(struct snd_soc_codec *codec) 4334 { 4335 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec); 4336 4337 if (gpio_is_valid(rt5677->pow_ldo2)) { 4338 gpio_set_value_cansleep(rt5677->pow_ldo2, 1); 4339 msleep(10); 4340 } 4341 4342 if (!rt5677->dsp_vad_en) { 4343 regcache_cache_only(rt5677->regmap, false); 4344 regcache_sync(rt5677->regmap); 4345 } 4346 4347 return 0; 4348 } 4349 #else 4350 #define rt5677_suspend NULL 4351 #define rt5677_resume NULL 4352 #endif 4353 4354 static int rt5677_read(void *context, unsigned int reg, unsigned int *val) 4355 { 4356 struct i2c_client *client = context; 4357 struct rt5677_priv *rt5677 = i2c_get_clientdata(client); 4358 4359 if (rt5677->is_dsp_mode) { 4360 if (reg > 0xff) { 4361 mutex_lock(&rt5677->dsp_pri_lock); 4362 rt5677_dsp_mode_i2c_write(rt5677, RT5677_PRIV_INDEX, 4363 reg & 0xff); 4364 rt5677_dsp_mode_i2c_read(rt5677, RT5677_PRIV_DATA, val); 4365 mutex_unlock(&rt5677->dsp_pri_lock); 4366 } else { 4367 rt5677_dsp_mode_i2c_read(rt5677, reg, val); 4368 } 4369 } else { 4370 regmap_read(rt5677->regmap_physical, reg, val); 4371 } 4372 4373 return 0; 4374 } 4375 4376 static int rt5677_write(void *context, unsigned int reg, unsigned int val) 4377 { 4378 struct i2c_client *client = context; 4379 struct rt5677_priv *rt5677 = i2c_get_clientdata(client); 4380 4381 if (rt5677->is_dsp_mode) { 4382 if (reg > 0xff) { 4383 mutex_lock(&rt5677->dsp_pri_lock); 4384 rt5677_dsp_mode_i2c_write(rt5677, RT5677_PRIV_INDEX, 4385 reg & 0xff); 4386 rt5677_dsp_mode_i2c_write(rt5677, RT5677_PRIV_DATA, 4387 val); 4388 mutex_unlock(&rt5677->dsp_pri_lock); 4389 } else { 4390 rt5677_dsp_mode_i2c_write(rt5677, reg, val); 4391 } 4392 } else { 4393 regmap_write(rt5677->regmap_physical, reg, val); 4394 } 4395 4396 return 0; 4397 } 4398 4399 #define RT5677_STEREO_RATES SNDRV_PCM_RATE_8000_96000 4400 #define RT5677_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ 4401 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8) 4402 4403 static struct snd_soc_dai_ops rt5677_aif_dai_ops = { 4404 .hw_params = rt5677_hw_params, 4405 .set_fmt = rt5677_set_dai_fmt, 4406 .set_sysclk = rt5677_set_dai_sysclk, 4407 .set_pll = rt5677_set_dai_pll, 4408 .set_tdm_slot = rt5677_set_tdm_slot, 4409 }; 4410 4411 static struct snd_soc_dai_driver rt5677_dai[] = { 4412 { 4413 .name = "rt5677-aif1", 4414 .id = RT5677_AIF1, 4415 .playback = { 4416 .stream_name = "AIF1 Playback", 4417 .channels_min = 1, 4418 .channels_max = 2, 4419 .rates = RT5677_STEREO_RATES, 4420 .formats = RT5677_FORMATS, 4421 }, 4422 .capture = { 4423 .stream_name = "AIF1 Capture", 4424 .channels_min = 1, 4425 .channels_max = 2, 4426 .rates = RT5677_STEREO_RATES, 4427 .formats = RT5677_FORMATS, 4428 }, 4429 .ops = &rt5677_aif_dai_ops, 4430 }, 4431 { 4432 .name = "rt5677-aif2", 4433 .id = RT5677_AIF2, 4434 .playback = { 4435 .stream_name = "AIF2 Playback", 4436 .channels_min = 1, 4437 .channels_max = 2, 4438 .rates = RT5677_STEREO_RATES, 4439 .formats = RT5677_FORMATS, 4440 }, 4441 .capture = { 4442 .stream_name = "AIF2 Capture", 4443 .channels_min = 1, 4444 .channels_max = 2, 4445 .rates = RT5677_STEREO_RATES, 4446 .formats = RT5677_FORMATS, 4447 }, 4448 .ops = &rt5677_aif_dai_ops, 4449 }, 4450 { 4451 .name = "rt5677-aif3", 4452 .id = RT5677_AIF3, 4453 .playback = { 4454 .stream_name = "AIF3 Playback", 4455 .channels_min = 1, 4456 .channels_max = 2, 4457 .rates = RT5677_STEREO_RATES, 4458 .formats = RT5677_FORMATS, 4459 }, 4460 .capture = { 4461 .stream_name = "AIF3 Capture", 4462 .channels_min = 1, 4463 .channels_max = 2, 4464 .rates = RT5677_STEREO_RATES, 4465 .formats = RT5677_FORMATS, 4466 }, 4467 .ops = &rt5677_aif_dai_ops, 4468 }, 4469 { 4470 .name = "rt5677-aif4", 4471 .id = RT5677_AIF4, 4472 .playback = { 4473 .stream_name = "AIF4 Playback", 4474 .channels_min = 1, 4475 .channels_max = 2, 4476 .rates = RT5677_STEREO_RATES, 4477 .formats = RT5677_FORMATS, 4478 }, 4479 .capture = { 4480 .stream_name = "AIF4 Capture", 4481 .channels_min = 1, 4482 .channels_max = 2, 4483 .rates = RT5677_STEREO_RATES, 4484 .formats = RT5677_FORMATS, 4485 }, 4486 .ops = &rt5677_aif_dai_ops, 4487 }, 4488 { 4489 .name = "rt5677-slimbus", 4490 .id = RT5677_AIF5, 4491 .playback = { 4492 .stream_name = "SLIMBus Playback", 4493 .channels_min = 1, 4494 .channels_max = 2, 4495 .rates = RT5677_STEREO_RATES, 4496 .formats = RT5677_FORMATS, 4497 }, 4498 .capture = { 4499 .stream_name = "SLIMBus Capture", 4500 .channels_min = 1, 4501 .channels_max = 2, 4502 .rates = RT5677_STEREO_RATES, 4503 .formats = RT5677_FORMATS, 4504 }, 4505 .ops = &rt5677_aif_dai_ops, 4506 }, 4507 }; 4508 4509 static struct snd_soc_codec_driver soc_codec_dev_rt5677 = { 4510 .probe = rt5677_probe, 4511 .remove = rt5677_remove, 4512 .suspend = rt5677_suspend, 4513 .resume = rt5677_resume, 4514 .set_bias_level = rt5677_set_bias_level, 4515 .idle_bias_off = true, 4516 .controls = rt5677_snd_controls, 4517 .num_controls = ARRAY_SIZE(rt5677_snd_controls), 4518 .dapm_widgets = rt5677_dapm_widgets, 4519 .num_dapm_widgets = ARRAY_SIZE(rt5677_dapm_widgets), 4520 .dapm_routes = rt5677_dapm_routes, 4521 .num_dapm_routes = ARRAY_SIZE(rt5677_dapm_routes), 4522 }; 4523 4524 static const struct regmap_config rt5677_regmap_physical = { 4525 .name = "physical", 4526 .reg_bits = 8, 4527 .val_bits = 16, 4528 4529 .max_register = RT5677_VENDOR_ID2 + 1 + (ARRAY_SIZE(rt5677_ranges) * 4530 RT5677_PR_SPACING), 4531 .readable_reg = rt5677_readable_register, 4532 4533 .cache_type = REGCACHE_NONE, 4534 .ranges = rt5677_ranges, 4535 .num_ranges = ARRAY_SIZE(rt5677_ranges), 4536 }; 4537 4538 static const struct regmap_config rt5677_regmap = { 4539 .reg_bits = 8, 4540 .val_bits = 16, 4541 4542 .max_register = RT5677_VENDOR_ID2 + 1 + (ARRAY_SIZE(rt5677_ranges) * 4543 RT5677_PR_SPACING), 4544 4545 .volatile_reg = rt5677_volatile_register, 4546 .readable_reg = rt5677_readable_register, 4547 .reg_read = rt5677_read, 4548 .reg_write = rt5677_write, 4549 4550 .cache_type = REGCACHE_RBTREE, 4551 .reg_defaults = rt5677_reg, 4552 .num_reg_defaults = ARRAY_SIZE(rt5677_reg), 4553 .ranges = rt5677_ranges, 4554 .num_ranges = ARRAY_SIZE(rt5677_ranges), 4555 }; 4556 4557 static const struct i2c_device_id rt5677_i2c_id[] = { 4558 { "rt5677", 0 }, 4559 { } 4560 }; 4561 MODULE_DEVICE_TABLE(i2c, rt5677_i2c_id); 4562 4563 static int rt5677_parse_dt(struct rt5677_priv *rt5677, struct device_node *np) 4564 { 4565 rt5677->pdata.in1_diff = of_property_read_bool(np, 4566 "realtek,in1-differential"); 4567 rt5677->pdata.in2_diff = of_property_read_bool(np, 4568 "realtek,in2-differential"); 4569 rt5677->pdata.lout1_diff = of_property_read_bool(np, 4570 "realtek,lout1-differential"); 4571 rt5677->pdata.lout2_diff = of_property_read_bool(np, 4572 "realtek,lout2-differential"); 4573 rt5677->pdata.lout3_diff = of_property_read_bool(np, 4574 "realtek,lout3-differential"); 4575 4576 rt5677->pow_ldo2 = of_get_named_gpio(np, 4577 "realtek,pow-ldo2-gpio", 0); 4578 4579 /* 4580 * POW_LDO2 is optional (it may be statically tied on the board). 4581 * -ENOENT means that the property doesn't exist, i.e. there is no 4582 * GPIO, so is not an error. Any other error code means the property 4583 * exists, but could not be parsed. 4584 */ 4585 if (!gpio_is_valid(rt5677->pow_ldo2) && 4586 (rt5677->pow_ldo2 != -ENOENT)) 4587 return rt5677->pow_ldo2; 4588 4589 of_property_read_u8_array(np, "realtek,gpio-config", 4590 rt5677->pdata.gpio_config, RT5677_GPIO_NUM); 4591 4592 of_property_read_u32(np, "realtek,jd1-gpio", &rt5677->pdata.jd1_gpio); 4593 of_property_read_u32(np, "realtek,jd2-gpio", &rt5677->pdata.jd2_gpio); 4594 of_property_read_u32(np, "realtek,jd3-gpio", &rt5677->pdata.jd3_gpio); 4595 4596 return 0; 4597 } 4598 4599 static struct regmap_irq rt5677_irqs[] = { 4600 [RT5677_IRQ_JD1] = { 4601 .reg_offset = 0, 4602 .mask = RT5677_EN_IRQ_GPIO_JD1, 4603 }, 4604 [RT5677_IRQ_JD2] = { 4605 .reg_offset = 0, 4606 .mask = RT5677_EN_IRQ_GPIO_JD2, 4607 }, 4608 [RT5677_IRQ_JD3] = { 4609 .reg_offset = 0, 4610 .mask = RT5677_EN_IRQ_GPIO_JD3, 4611 }, 4612 }; 4613 4614 static struct regmap_irq_chip rt5677_irq_chip = { 4615 .name = "rt5677", 4616 .irqs = rt5677_irqs, 4617 .num_irqs = ARRAY_SIZE(rt5677_irqs), 4618 4619 .num_regs = 1, 4620 .status_base = RT5677_IRQ_CTRL1, 4621 .mask_base = RT5677_IRQ_CTRL1, 4622 .mask_invert = 1, 4623 }; 4624 4625 static int rt5677_init_irq(struct i2c_client *i2c) 4626 { 4627 int ret; 4628 struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c); 4629 4630 if (!rt5677->pdata.jd1_gpio && 4631 !rt5677->pdata.jd2_gpio && 4632 !rt5677->pdata.jd3_gpio) 4633 return 0; 4634 4635 if (!i2c->irq) { 4636 dev_err(&i2c->dev, "No interrupt specified\n"); 4637 return -EINVAL; 4638 } 4639 4640 ret = regmap_add_irq_chip(rt5677->regmap, i2c->irq, 4641 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING | IRQF_ONESHOT, 0, 4642 &rt5677_irq_chip, &rt5677->irq_data); 4643 4644 if (ret != 0) { 4645 dev_err(&i2c->dev, "Failed to register IRQ chip: %d\n", ret); 4646 return ret; 4647 } 4648 4649 return 0; 4650 } 4651 4652 static void rt5677_free_irq(struct i2c_client *i2c) 4653 { 4654 struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c); 4655 4656 if (rt5677->irq_data) 4657 regmap_del_irq_chip(i2c->irq, rt5677->irq_data); 4658 } 4659 4660 static int rt5677_i2c_probe(struct i2c_client *i2c, 4661 const struct i2c_device_id *id) 4662 { 4663 struct rt5677_platform_data *pdata = dev_get_platdata(&i2c->dev); 4664 struct rt5677_priv *rt5677; 4665 int ret; 4666 unsigned int val; 4667 4668 rt5677 = devm_kzalloc(&i2c->dev, sizeof(struct rt5677_priv), 4669 GFP_KERNEL); 4670 if (rt5677 == NULL) 4671 return -ENOMEM; 4672 4673 i2c_set_clientdata(i2c, rt5677); 4674 4675 if (pdata) 4676 rt5677->pdata = *pdata; 4677 4678 if (i2c->dev.of_node) { 4679 ret = rt5677_parse_dt(rt5677, i2c->dev.of_node); 4680 if (ret) { 4681 dev_err(&i2c->dev, "Failed to parse device tree: %d\n", 4682 ret); 4683 return ret; 4684 } 4685 } else { 4686 rt5677->pow_ldo2 = -EINVAL; 4687 } 4688 4689 if (gpio_is_valid(rt5677->pow_ldo2)) { 4690 ret = devm_gpio_request_one(&i2c->dev, rt5677->pow_ldo2, 4691 GPIOF_OUT_INIT_HIGH, 4692 "RT5677 POW_LDO2"); 4693 if (ret < 0) { 4694 dev_err(&i2c->dev, "Failed to request POW_LDO2 %d: %d\n", 4695 rt5677->pow_ldo2, ret); 4696 return ret; 4697 } 4698 /* Wait a while until I2C bus becomes available. The datasheet 4699 * does not specify the exact we should wait but startup 4700 * sequence mentiones at least a few milliseconds. 4701 */ 4702 msleep(10); 4703 } 4704 4705 rt5677->regmap_physical = devm_regmap_init_i2c(i2c, 4706 &rt5677_regmap_physical); 4707 if (IS_ERR(rt5677->regmap_physical)) { 4708 ret = PTR_ERR(rt5677->regmap_physical); 4709 dev_err(&i2c->dev, "Failed to allocate register map: %d\n", 4710 ret); 4711 return ret; 4712 } 4713 4714 rt5677->regmap = devm_regmap_init(&i2c->dev, NULL, i2c, &rt5677_regmap); 4715 if (IS_ERR(rt5677->regmap)) { 4716 ret = PTR_ERR(rt5677->regmap); 4717 dev_err(&i2c->dev, "Failed to allocate register map: %d\n", 4718 ret); 4719 return ret; 4720 } 4721 4722 regmap_read(rt5677->regmap, RT5677_VENDOR_ID2, &val); 4723 if (val != RT5677_DEVICE_ID) { 4724 dev_err(&i2c->dev, 4725 "Device with ID register %x is not rt5677\n", val); 4726 return -ENODEV; 4727 } 4728 4729 regmap_write(rt5677->regmap, RT5677_RESET, 0x10ec); 4730 4731 ret = regmap_register_patch(rt5677->regmap, init_list, 4732 ARRAY_SIZE(init_list)); 4733 if (ret != 0) 4734 dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret); 4735 4736 if (rt5677->pdata.in1_diff) 4737 regmap_update_bits(rt5677->regmap, RT5677_IN1, 4738 RT5677_IN_DF1, RT5677_IN_DF1); 4739 4740 if (rt5677->pdata.in2_diff) 4741 regmap_update_bits(rt5677->regmap, RT5677_IN1, 4742 RT5677_IN_DF2, RT5677_IN_DF2); 4743 4744 if (rt5677->pdata.lout1_diff) 4745 regmap_update_bits(rt5677->regmap, RT5677_LOUT1, 4746 RT5677_LOUT1_L_DF, RT5677_LOUT1_L_DF); 4747 4748 if (rt5677->pdata.lout2_diff) 4749 regmap_update_bits(rt5677->regmap, RT5677_LOUT1, 4750 RT5677_LOUT2_L_DF, RT5677_LOUT2_L_DF); 4751 4752 if (rt5677->pdata.lout3_diff) 4753 regmap_update_bits(rt5677->regmap, RT5677_LOUT1, 4754 RT5677_LOUT3_L_DF, RT5677_LOUT3_L_DF); 4755 4756 if (rt5677->pdata.dmic2_clk_pin == RT5677_DMIC_CLK2) { 4757 regmap_update_bits(rt5677->regmap, RT5677_GEN_CTRL2, 4758 RT5677_GPIO5_FUNC_MASK, 4759 RT5677_GPIO5_FUNC_DMIC); 4760 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2, 4761 RT5677_GPIO5_DIR_MASK, 4762 RT5677_GPIO5_DIR_OUT); 4763 } 4764 4765 rt5677_init_gpio(i2c); 4766 rt5677_init_irq(i2c); 4767 4768 return snd_soc_register_codec(&i2c->dev, &soc_codec_dev_rt5677, 4769 rt5677_dai, ARRAY_SIZE(rt5677_dai)); 4770 } 4771 4772 static int rt5677_i2c_remove(struct i2c_client *i2c) 4773 { 4774 snd_soc_unregister_codec(&i2c->dev); 4775 rt5677_free_irq(i2c); 4776 rt5677_free_gpio(i2c); 4777 4778 return 0; 4779 } 4780 4781 static struct i2c_driver rt5677_i2c_driver = { 4782 .driver = { 4783 .name = "rt5677", 4784 .owner = THIS_MODULE, 4785 }, 4786 .probe = rt5677_i2c_probe, 4787 .remove = rt5677_i2c_remove, 4788 .id_table = rt5677_i2c_id, 4789 }; 4790 module_i2c_driver(rt5677_i2c_driver); 4791 4792 MODULE_DESCRIPTION("ASoC RT5677 driver"); 4793 MODULE_AUTHOR("Oder Chiou <oder_chiou@realtek.com>"); 4794 MODULE_LICENSE("GPL v2"); 4795