1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * rt5677.c -- RT5677 ALSA SoC audio codec driver 4 * 5 * Copyright 2013 Realtek Semiconductor Corp. 6 * Author: Oder Chiou <oder_chiou@realtek.com> 7 */ 8 9 #include <linux/acpi.h> 10 #include <linux/fs.h> 11 #include <linux/module.h> 12 #include <linux/moduleparam.h> 13 #include <linux/init.h> 14 #include <linux/delay.h> 15 #include <linux/pm.h> 16 #include <linux/regmap.h> 17 #include <linux/i2c.h> 18 #include <linux/platform_device.h> 19 #include <linux/spi/spi.h> 20 #include <linux/firmware.h> 21 #include <linux/of_device.h> 22 #include <linux/property.h> 23 #include <linux/irq.h> 24 #include <linux/interrupt.h> 25 #include <linux/irqdomain.h> 26 #include <linux/workqueue.h> 27 #include <sound/core.h> 28 #include <sound/pcm.h> 29 #include <sound/pcm_params.h> 30 #include <sound/soc.h> 31 #include <sound/soc-dapm.h> 32 #include <sound/initval.h> 33 #include <sound/tlv.h> 34 35 #include "rl6231.h" 36 #include "rt5677.h" 37 #include "rt5677-spi.h" 38 39 #define RT5677_DEVICE_ID 0x6327 40 41 /* Register controlling boot vector */ 42 #define RT5677_DSP_BOOT_VECTOR 0x1801f090 43 #define RT5677_MODEL_ADDR 0x5FFC9800 44 45 #define RT5677_PR_RANGE_BASE (0xff + 1) 46 #define RT5677_PR_SPACING 0x100 47 48 #define RT5677_PR_BASE (RT5677_PR_RANGE_BASE + (0 * RT5677_PR_SPACING)) 49 50 static const struct regmap_range_cfg rt5677_ranges[] = { 51 { 52 .name = "PR", 53 .range_min = RT5677_PR_BASE, 54 .range_max = RT5677_PR_BASE + 0xfd, 55 .selector_reg = RT5677_PRIV_INDEX, 56 .selector_mask = 0xff, 57 .selector_shift = 0x0, 58 .window_start = RT5677_PRIV_DATA, 59 .window_len = 0x1, 60 }, 61 }; 62 63 static const struct reg_sequence init_list[] = { 64 {RT5677_ASRC_12, 0x0018}, 65 {RT5677_PR_BASE + 0x3d, 0x364d}, 66 {RT5677_PR_BASE + 0x17, 0x4fc0}, 67 {RT5677_PR_BASE + 0x13, 0x0312}, 68 {RT5677_PR_BASE + 0x1e, 0x0000}, 69 {RT5677_PR_BASE + 0x12, 0x0eaa}, 70 {RT5677_PR_BASE + 0x14, 0x018a}, 71 {RT5677_PR_BASE + 0x15, 0x0490}, 72 {RT5677_PR_BASE + 0x38, 0x0f71}, 73 {RT5677_PR_BASE + 0x39, 0x0f71}, 74 }; 75 #define RT5677_INIT_REG_LEN ARRAY_SIZE(init_list) 76 77 static const struct reg_default rt5677_reg[] = { 78 {RT5677_RESET , 0x0000}, 79 {RT5677_LOUT1 , 0xa800}, 80 {RT5677_IN1 , 0x0000}, 81 {RT5677_MICBIAS , 0x0000}, 82 {RT5677_SLIMBUS_PARAM , 0x0000}, 83 {RT5677_SLIMBUS_RX , 0x0000}, 84 {RT5677_SLIMBUS_CTRL , 0x0000}, 85 {RT5677_SIDETONE_CTRL , 0x000b}, 86 {RT5677_ANA_DAC1_2_3_SRC , 0x0000}, 87 {RT5677_IF_DSP_DAC3_4_MIXER , 0x1111}, 88 {RT5677_DAC4_DIG_VOL , 0xafaf}, 89 {RT5677_DAC3_DIG_VOL , 0xafaf}, 90 {RT5677_DAC1_DIG_VOL , 0xafaf}, 91 {RT5677_DAC2_DIG_VOL , 0xafaf}, 92 {RT5677_IF_DSP_DAC2_MIXER , 0x0011}, 93 {RT5677_STO1_ADC_DIG_VOL , 0x2f2f}, 94 {RT5677_MONO_ADC_DIG_VOL , 0x2f2f}, 95 {RT5677_STO1_2_ADC_BST , 0x0000}, 96 {RT5677_STO2_ADC_DIG_VOL , 0x2f2f}, 97 {RT5677_ADC_BST_CTRL2 , 0x0000}, 98 {RT5677_STO3_4_ADC_BST , 0x0000}, 99 {RT5677_STO3_ADC_DIG_VOL , 0x2f2f}, 100 {RT5677_STO4_ADC_DIG_VOL , 0x2f2f}, 101 {RT5677_STO4_ADC_MIXER , 0xd4c0}, 102 {RT5677_STO3_ADC_MIXER , 0xd4c0}, 103 {RT5677_STO2_ADC_MIXER , 0xd4c0}, 104 {RT5677_STO1_ADC_MIXER , 0xd4c0}, 105 {RT5677_MONO_ADC_MIXER , 0xd4d1}, 106 {RT5677_ADC_IF_DSP_DAC1_MIXER , 0x8080}, 107 {RT5677_STO1_DAC_MIXER , 0xaaaa}, 108 {RT5677_MONO_DAC_MIXER , 0xaaaa}, 109 {RT5677_DD1_MIXER , 0xaaaa}, 110 {RT5677_DD2_MIXER , 0xaaaa}, 111 {RT5677_IF3_DATA , 0x0000}, 112 {RT5677_IF4_DATA , 0x0000}, 113 {RT5677_PDM_OUT_CTRL , 0x8888}, 114 {RT5677_PDM_DATA_CTRL1 , 0x0000}, 115 {RT5677_PDM_DATA_CTRL2 , 0x0000}, 116 {RT5677_PDM1_DATA_CTRL2 , 0x0000}, 117 {RT5677_PDM1_DATA_CTRL3 , 0x0000}, 118 {RT5677_PDM1_DATA_CTRL4 , 0x0000}, 119 {RT5677_PDM2_DATA_CTRL2 , 0x0000}, 120 {RT5677_PDM2_DATA_CTRL3 , 0x0000}, 121 {RT5677_PDM2_DATA_CTRL4 , 0x0000}, 122 {RT5677_TDM1_CTRL1 , 0x0300}, 123 {RT5677_TDM1_CTRL2 , 0x0000}, 124 {RT5677_TDM1_CTRL3 , 0x4000}, 125 {RT5677_TDM1_CTRL4 , 0x0123}, 126 {RT5677_TDM1_CTRL5 , 0x4567}, 127 {RT5677_TDM2_CTRL1 , 0x0300}, 128 {RT5677_TDM2_CTRL2 , 0x0000}, 129 {RT5677_TDM2_CTRL3 , 0x4000}, 130 {RT5677_TDM2_CTRL4 , 0x0123}, 131 {RT5677_TDM2_CTRL5 , 0x4567}, 132 {RT5677_I2C_MASTER_CTRL1 , 0x0001}, 133 {RT5677_I2C_MASTER_CTRL2 , 0x0000}, 134 {RT5677_I2C_MASTER_CTRL3 , 0x0000}, 135 {RT5677_I2C_MASTER_CTRL4 , 0x0000}, 136 {RT5677_I2C_MASTER_CTRL5 , 0x0000}, 137 {RT5677_I2C_MASTER_CTRL6 , 0x0000}, 138 {RT5677_I2C_MASTER_CTRL7 , 0x0000}, 139 {RT5677_I2C_MASTER_CTRL8 , 0x0000}, 140 {RT5677_DMIC_CTRL1 , 0x1505}, 141 {RT5677_DMIC_CTRL2 , 0x0055}, 142 {RT5677_HAP_GENE_CTRL1 , 0x0111}, 143 {RT5677_HAP_GENE_CTRL2 , 0x0064}, 144 {RT5677_HAP_GENE_CTRL3 , 0xef0e}, 145 {RT5677_HAP_GENE_CTRL4 , 0xf0f0}, 146 {RT5677_HAP_GENE_CTRL5 , 0xef0e}, 147 {RT5677_HAP_GENE_CTRL6 , 0xf0f0}, 148 {RT5677_HAP_GENE_CTRL7 , 0xef0e}, 149 {RT5677_HAP_GENE_CTRL8 , 0xf0f0}, 150 {RT5677_HAP_GENE_CTRL9 , 0xf000}, 151 {RT5677_HAP_GENE_CTRL10 , 0x0000}, 152 {RT5677_PWR_DIG1 , 0x0000}, 153 {RT5677_PWR_DIG2 , 0x0000}, 154 {RT5677_PWR_ANLG1 , 0x0055}, 155 {RT5677_PWR_ANLG2 , 0x0000}, 156 {RT5677_PWR_DSP1 , 0x0001}, 157 {RT5677_PWR_DSP_ST , 0x0000}, 158 {RT5677_PWR_DSP2 , 0x0000}, 159 {RT5677_ADC_DAC_HPF_CTRL1 , 0x0e00}, 160 {RT5677_PRIV_INDEX , 0x0000}, 161 {RT5677_PRIV_DATA , 0x0000}, 162 {RT5677_I2S4_SDP , 0x8000}, 163 {RT5677_I2S1_SDP , 0x8000}, 164 {RT5677_I2S2_SDP , 0x8000}, 165 {RT5677_I2S3_SDP , 0x8000}, 166 {RT5677_CLK_TREE_CTRL1 , 0x1111}, 167 {RT5677_CLK_TREE_CTRL2 , 0x1111}, 168 {RT5677_CLK_TREE_CTRL3 , 0x0000}, 169 {RT5677_PLL1_CTRL1 , 0x0000}, 170 {RT5677_PLL1_CTRL2 , 0x0000}, 171 {RT5677_PLL2_CTRL1 , 0x0c60}, 172 {RT5677_PLL2_CTRL2 , 0x2000}, 173 {RT5677_GLB_CLK1 , 0x0000}, 174 {RT5677_GLB_CLK2 , 0x0000}, 175 {RT5677_ASRC_1 , 0x0000}, 176 {RT5677_ASRC_2 , 0x0000}, 177 {RT5677_ASRC_3 , 0x0000}, 178 {RT5677_ASRC_4 , 0x0000}, 179 {RT5677_ASRC_5 , 0x0000}, 180 {RT5677_ASRC_6 , 0x0000}, 181 {RT5677_ASRC_7 , 0x0000}, 182 {RT5677_ASRC_8 , 0x0000}, 183 {RT5677_ASRC_9 , 0x0000}, 184 {RT5677_ASRC_10 , 0x0000}, 185 {RT5677_ASRC_11 , 0x0000}, 186 {RT5677_ASRC_12 , 0x0018}, 187 {RT5677_ASRC_13 , 0x0000}, 188 {RT5677_ASRC_14 , 0x0000}, 189 {RT5677_ASRC_15 , 0x0000}, 190 {RT5677_ASRC_16 , 0x0000}, 191 {RT5677_ASRC_17 , 0x0000}, 192 {RT5677_ASRC_18 , 0x0000}, 193 {RT5677_ASRC_19 , 0x0000}, 194 {RT5677_ASRC_20 , 0x0000}, 195 {RT5677_ASRC_21 , 0x000c}, 196 {RT5677_ASRC_22 , 0x0000}, 197 {RT5677_ASRC_23 , 0x0000}, 198 {RT5677_VAD_CTRL1 , 0x2184}, 199 {RT5677_VAD_CTRL2 , 0x010a}, 200 {RT5677_VAD_CTRL3 , 0x0aea}, 201 {RT5677_VAD_CTRL4 , 0x000c}, 202 {RT5677_VAD_CTRL5 , 0x0000}, 203 {RT5677_DSP_INB_CTRL1 , 0x0000}, 204 {RT5677_DSP_INB_CTRL2 , 0x0000}, 205 {RT5677_DSP_IN_OUTB_CTRL , 0x0000}, 206 {RT5677_DSP_OUTB0_1_DIG_VOL , 0x2f2f}, 207 {RT5677_DSP_OUTB2_3_DIG_VOL , 0x2f2f}, 208 {RT5677_DSP_OUTB4_5_DIG_VOL , 0x2f2f}, 209 {RT5677_DSP_OUTB6_7_DIG_VOL , 0x2f2f}, 210 {RT5677_ADC_EQ_CTRL1 , 0x6000}, 211 {RT5677_ADC_EQ_CTRL2 , 0x0000}, 212 {RT5677_EQ_CTRL1 , 0xc000}, 213 {RT5677_EQ_CTRL2 , 0x0000}, 214 {RT5677_EQ_CTRL3 , 0x0000}, 215 {RT5677_SOFT_VOL_ZERO_CROSS1 , 0x0009}, 216 {RT5677_JD_CTRL1 , 0x0000}, 217 {RT5677_JD_CTRL2 , 0x0000}, 218 {RT5677_JD_CTRL3 , 0x0000}, 219 {RT5677_IRQ_CTRL1 , 0x0000}, 220 {RT5677_IRQ_CTRL2 , 0x0000}, 221 {RT5677_GPIO_ST , 0x0000}, 222 {RT5677_GPIO_CTRL1 , 0x0000}, 223 {RT5677_GPIO_CTRL2 , 0x0000}, 224 {RT5677_GPIO_CTRL3 , 0x0000}, 225 {RT5677_STO1_ADC_HI_FILTER1 , 0xb320}, 226 {RT5677_STO1_ADC_HI_FILTER2 , 0x0000}, 227 {RT5677_MONO_ADC_HI_FILTER1 , 0xb300}, 228 {RT5677_MONO_ADC_HI_FILTER2 , 0x0000}, 229 {RT5677_STO2_ADC_HI_FILTER1 , 0xb300}, 230 {RT5677_STO2_ADC_HI_FILTER2 , 0x0000}, 231 {RT5677_STO3_ADC_HI_FILTER1 , 0xb300}, 232 {RT5677_STO3_ADC_HI_FILTER2 , 0x0000}, 233 {RT5677_STO4_ADC_HI_FILTER1 , 0xb300}, 234 {RT5677_STO4_ADC_HI_FILTER2 , 0x0000}, 235 {RT5677_MB_DRC_CTRL1 , 0x0f20}, 236 {RT5677_DRC1_CTRL1 , 0x001f}, 237 {RT5677_DRC1_CTRL2 , 0x020c}, 238 {RT5677_DRC1_CTRL3 , 0x1f00}, 239 {RT5677_DRC1_CTRL4 , 0x0000}, 240 {RT5677_DRC1_CTRL5 , 0x0000}, 241 {RT5677_DRC1_CTRL6 , 0x0029}, 242 {RT5677_DRC2_CTRL1 , 0x001f}, 243 {RT5677_DRC2_CTRL2 , 0x020c}, 244 {RT5677_DRC2_CTRL3 , 0x1f00}, 245 {RT5677_DRC2_CTRL4 , 0x0000}, 246 {RT5677_DRC2_CTRL5 , 0x0000}, 247 {RT5677_DRC2_CTRL6 , 0x0029}, 248 {RT5677_DRC1_HL_CTRL1 , 0x8000}, 249 {RT5677_DRC1_HL_CTRL2 , 0x0200}, 250 {RT5677_DRC2_HL_CTRL1 , 0x8000}, 251 {RT5677_DRC2_HL_CTRL2 , 0x0200}, 252 {RT5677_DSP_INB1_SRC_CTRL1 , 0x5800}, 253 {RT5677_DSP_INB1_SRC_CTRL2 , 0x0000}, 254 {RT5677_DSP_INB1_SRC_CTRL3 , 0x0000}, 255 {RT5677_DSP_INB1_SRC_CTRL4 , 0x0800}, 256 {RT5677_DSP_INB2_SRC_CTRL1 , 0x5800}, 257 {RT5677_DSP_INB2_SRC_CTRL2 , 0x0000}, 258 {RT5677_DSP_INB2_SRC_CTRL3 , 0x0000}, 259 {RT5677_DSP_INB2_SRC_CTRL4 , 0x0800}, 260 {RT5677_DSP_INB3_SRC_CTRL1 , 0x5800}, 261 {RT5677_DSP_INB3_SRC_CTRL2 , 0x0000}, 262 {RT5677_DSP_INB3_SRC_CTRL3 , 0x0000}, 263 {RT5677_DSP_INB3_SRC_CTRL4 , 0x0800}, 264 {RT5677_DSP_OUTB1_SRC_CTRL1 , 0x5800}, 265 {RT5677_DSP_OUTB1_SRC_CTRL2 , 0x0000}, 266 {RT5677_DSP_OUTB1_SRC_CTRL3 , 0x0000}, 267 {RT5677_DSP_OUTB1_SRC_CTRL4 , 0x0800}, 268 {RT5677_DSP_OUTB2_SRC_CTRL1 , 0x5800}, 269 {RT5677_DSP_OUTB2_SRC_CTRL2 , 0x0000}, 270 {RT5677_DSP_OUTB2_SRC_CTRL3 , 0x0000}, 271 {RT5677_DSP_OUTB2_SRC_CTRL4 , 0x0800}, 272 {RT5677_DSP_OUTB_0123_MIXER_CTRL, 0xfefe}, 273 {RT5677_DSP_OUTB_45_MIXER_CTRL , 0xfefe}, 274 {RT5677_DSP_OUTB_67_MIXER_CTRL , 0xfefe}, 275 {RT5677_DIG_MISC , 0x0000}, 276 {RT5677_GEN_CTRL1 , 0x0000}, 277 {RT5677_GEN_CTRL2 , 0x0000}, 278 {RT5677_VENDOR_ID , 0x0000}, 279 {RT5677_VENDOR_ID1 , 0x10ec}, 280 {RT5677_VENDOR_ID2 , 0x6327}, 281 }; 282 283 static bool rt5677_volatile_register(struct device *dev, unsigned int reg) 284 { 285 int i; 286 287 for (i = 0; i < ARRAY_SIZE(rt5677_ranges); i++) { 288 if (reg >= rt5677_ranges[i].range_min && 289 reg <= rt5677_ranges[i].range_max) { 290 return true; 291 } 292 } 293 294 switch (reg) { 295 case RT5677_RESET: 296 case RT5677_SLIMBUS_PARAM: 297 case RT5677_PDM_DATA_CTRL1: 298 case RT5677_PDM_DATA_CTRL2: 299 case RT5677_PDM1_DATA_CTRL4: 300 case RT5677_PDM2_DATA_CTRL4: 301 case RT5677_I2C_MASTER_CTRL1: 302 case RT5677_I2C_MASTER_CTRL7: 303 case RT5677_I2C_MASTER_CTRL8: 304 case RT5677_HAP_GENE_CTRL2: 305 case RT5677_PWR_ANLG2: /* Modified by DSP firmware */ 306 case RT5677_PWR_DSP_ST: 307 case RT5677_PRIV_DATA: 308 case RT5677_ASRC_22: 309 case RT5677_ASRC_23: 310 case RT5677_VAD_CTRL5: 311 case RT5677_ADC_EQ_CTRL1: 312 case RT5677_EQ_CTRL1: 313 case RT5677_IRQ_CTRL1: 314 case RT5677_IRQ_CTRL2: 315 case RT5677_GPIO_ST: 316 case RT5677_GPIO_CTRL1: /* Modified by DSP firmware */ 317 case RT5677_GPIO_CTRL2: /* Modified by DSP firmware */ 318 case RT5677_DSP_INB1_SRC_CTRL4: 319 case RT5677_DSP_INB2_SRC_CTRL4: 320 case RT5677_DSP_INB3_SRC_CTRL4: 321 case RT5677_DSP_OUTB1_SRC_CTRL4: 322 case RT5677_DSP_OUTB2_SRC_CTRL4: 323 case RT5677_VENDOR_ID: 324 case RT5677_VENDOR_ID1: 325 case RT5677_VENDOR_ID2: 326 return true; 327 default: 328 return false; 329 } 330 } 331 332 static bool rt5677_readable_register(struct device *dev, unsigned int reg) 333 { 334 int i; 335 336 for (i = 0; i < ARRAY_SIZE(rt5677_ranges); i++) { 337 if (reg >= rt5677_ranges[i].range_min && 338 reg <= rt5677_ranges[i].range_max) { 339 return true; 340 } 341 } 342 343 switch (reg) { 344 case RT5677_RESET: 345 case RT5677_LOUT1: 346 case RT5677_IN1: 347 case RT5677_MICBIAS: 348 case RT5677_SLIMBUS_PARAM: 349 case RT5677_SLIMBUS_RX: 350 case RT5677_SLIMBUS_CTRL: 351 case RT5677_SIDETONE_CTRL: 352 case RT5677_ANA_DAC1_2_3_SRC: 353 case RT5677_IF_DSP_DAC3_4_MIXER: 354 case RT5677_DAC4_DIG_VOL: 355 case RT5677_DAC3_DIG_VOL: 356 case RT5677_DAC1_DIG_VOL: 357 case RT5677_DAC2_DIG_VOL: 358 case RT5677_IF_DSP_DAC2_MIXER: 359 case RT5677_STO1_ADC_DIG_VOL: 360 case RT5677_MONO_ADC_DIG_VOL: 361 case RT5677_STO1_2_ADC_BST: 362 case RT5677_STO2_ADC_DIG_VOL: 363 case RT5677_ADC_BST_CTRL2: 364 case RT5677_STO3_4_ADC_BST: 365 case RT5677_STO3_ADC_DIG_VOL: 366 case RT5677_STO4_ADC_DIG_VOL: 367 case RT5677_STO4_ADC_MIXER: 368 case RT5677_STO3_ADC_MIXER: 369 case RT5677_STO2_ADC_MIXER: 370 case RT5677_STO1_ADC_MIXER: 371 case RT5677_MONO_ADC_MIXER: 372 case RT5677_ADC_IF_DSP_DAC1_MIXER: 373 case RT5677_STO1_DAC_MIXER: 374 case RT5677_MONO_DAC_MIXER: 375 case RT5677_DD1_MIXER: 376 case RT5677_DD2_MIXER: 377 case RT5677_IF3_DATA: 378 case RT5677_IF4_DATA: 379 case RT5677_PDM_OUT_CTRL: 380 case RT5677_PDM_DATA_CTRL1: 381 case RT5677_PDM_DATA_CTRL2: 382 case RT5677_PDM1_DATA_CTRL2: 383 case RT5677_PDM1_DATA_CTRL3: 384 case RT5677_PDM1_DATA_CTRL4: 385 case RT5677_PDM2_DATA_CTRL2: 386 case RT5677_PDM2_DATA_CTRL3: 387 case RT5677_PDM2_DATA_CTRL4: 388 case RT5677_TDM1_CTRL1: 389 case RT5677_TDM1_CTRL2: 390 case RT5677_TDM1_CTRL3: 391 case RT5677_TDM1_CTRL4: 392 case RT5677_TDM1_CTRL5: 393 case RT5677_TDM2_CTRL1: 394 case RT5677_TDM2_CTRL2: 395 case RT5677_TDM2_CTRL3: 396 case RT5677_TDM2_CTRL4: 397 case RT5677_TDM2_CTRL5: 398 case RT5677_I2C_MASTER_CTRL1: 399 case RT5677_I2C_MASTER_CTRL2: 400 case RT5677_I2C_MASTER_CTRL3: 401 case RT5677_I2C_MASTER_CTRL4: 402 case RT5677_I2C_MASTER_CTRL5: 403 case RT5677_I2C_MASTER_CTRL6: 404 case RT5677_I2C_MASTER_CTRL7: 405 case RT5677_I2C_MASTER_CTRL8: 406 case RT5677_DMIC_CTRL1: 407 case RT5677_DMIC_CTRL2: 408 case RT5677_HAP_GENE_CTRL1: 409 case RT5677_HAP_GENE_CTRL2: 410 case RT5677_HAP_GENE_CTRL3: 411 case RT5677_HAP_GENE_CTRL4: 412 case RT5677_HAP_GENE_CTRL5: 413 case RT5677_HAP_GENE_CTRL6: 414 case RT5677_HAP_GENE_CTRL7: 415 case RT5677_HAP_GENE_CTRL8: 416 case RT5677_HAP_GENE_CTRL9: 417 case RT5677_HAP_GENE_CTRL10: 418 case RT5677_PWR_DIG1: 419 case RT5677_PWR_DIG2: 420 case RT5677_PWR_ANLG1: 421 case RT5677_PWR_ANLG2: 422 case RT5677_PWR_DSP1: 423 case RT5677_PWR_DSP_ST: 424 case RT5677_PWR_DSP2: 425 case RT5677_ADC_DAC_HPF_CTRL1: 426 case RT5677_PRIV_INDEX: 427 case RT5677_PRIV_DATA: 428 case RT5677_I2S4_SDP: 429 case RT5677_I2S1_SDP: 430 case RT5677_I2S2_SDP: 431 case RT5677_I2S3_SDP: 432 case RT5677_CLK_TREE_CTRL1: 433 case RT5677_CLK_TREE_CTRL2: 434 case RT5677_CLK_TREE_CTRL3: 435 case RT5677_PLL1_CTRL1: 436 case RT5677_PLL1_CTRL2: 437 case RT5677_PLL2_CTRL1: 438 case RT5677_PLL2_CTRL2: 439 case RT5677_GLB_CLK1: 440 case RT5677_GLB_CLK2: 441 case RT5677_ASRC_1: 442 case RT5677_ASRC_2: 443 case RT5677_ASRC_3: 444 case RT5677_ASRC_4: 445 case RT5677_ASRC_5: 446 case RT5677_ASRC_6: 447 case RT5677_ASRC_7: 448 case RT5677_ASRC_8: 449 case RT5677_ASRC_9: 450 case RT5677_ASRC_10: 451 case RT5677_ASRC_11: 452 case RT5677_ASRC_12: 453 case RT5677_ASRC_13: 454 case RT5677_ASRC_14: 455 case RT5677_ASRC_15: 456 case RT5677_ASRC_16: 457 case RT5677_ASRC_17: 458 case RT5677_ASRC_18: 459 case RT5677_ASRC_19: 460 case RT5677_ASRC_20: 461 case RT5677_ASRC_21: 462 case RT5677_ASRC_22: 463 case RT5677_ASRC_23: 464 case RT5677_VAD_CTRL1: 465 case RT5677_VAD_CTRL2: 466 case RT5677_VAD_CTRL3: 467 case RT5677_VAD_CTRL4: 468 case RT5677_VAD_CTRL5: 469 case RT5677_DSP_INB_CTRL1: 470 case RT5677_DSP_INB_CTRL2: 471 case RT5677_DSP_IN_OUTB_CTRL: 472 case RT5677_DSP_OUTB0_1_DIG_VOL: 473 case RT5677_DSP_OUTB2_3_DIG_VOL: 474 case RT5677_DSP_OUTB4_5_DIG_VOL: 475 case RT5677_DSP_OUTB6_7_DIG_VOL: 476 case RT5677_ADC_EQ_CTRL1: 477 case RT5677_ADC_EQ_CTRL2: 478 case RT5677_EQ_CTRL1: 479 case RT5677_EQ_CTRL2: 480 case RT5677_EQ_CTRL3: 481 case RT5677_SOFT_VOL_ZERO_CROSS1: 482 case RT5677_JD_CTRL1: 483 case RT5677_JD_CTRL2: 484 case RT5677_JD_CTRL3: 485 case RT5677_IRQ_CTRL1: 486 case RT5677_IRQ_CTRL2: 487 case RT5677_GPIO_ST: 488 case RT5677_GPIO_CTRL1: 489 case RT5677_GPIO_CTRL2: 490 case RT5677_GPIO_CTRL3: 491 case RT5677_STO1_ADC_HI_FILTER1: 492 case RT5677_STO1_ADC_HI_FILTER2: 493 case RT5677_MONO_ADC_HI_FILTER1: 494 case RT5677_MONO_ADC_HI_FILTER2: 495 case RT5677_STO2_ADC_HI_FILTER1: 496 case RT5677_STO2_ADC_HI_FILTER2: 497 case RT5677_STO3_ADC_HI_FILTER1: 498 case RT5677_STO3_ADC_HI_FILTER2: 499 case RT5677_STO4_ADC_HI_FILTER1: 500 case RT5677_STO4_ADC_HI_FILTER2: 501 case RT5677_MB_DRC_CTRL1: 502 case RT5677_DRC1_CTRL1: 503 case RT5677_DRC1_CTRL2: 504 case RT5677_DRC1_CTRL3: 505 case RT5677_DRC1_CTRL4: 506 case RT5677_DRC1_CTRL5: 507 case RT5677_DRC1_CTRL6: 508 case RT5677_DRC2_CTRL1: 509 case RT5677_DRC2_CTRL2: 510 case RT5677_DRC2_CTRL3: 511 case RT5677_DRC2_CTRL4: 512 case RT5677_DRC2_CTRL5: 513 case RT5677_DRC2_CTRL6: 514 case RT5677_DRC1_HL_CTRL1: 515 case RT5677_DRC1_HL_CTRL2: 516 case RT5677_DRC2_HL_CTRL1: 517 case RT5677_DRC2_HL_CTRL2: 518 case RT5677_DSP_INB1_SRC_CTRL1: 519 case RT5677_DSP_INB1_SRC_CTRL2: 520 case RT5677_DSP_INB1_SRC_CTRL3: 521 case RT5677_DSP_INB1_SRC_CTRL4: 522 case RT5677_DSP_INB2_SRC_CTRL1: 523 case RT5677_DSP_INB2_SRC_CTRL2: 524 case RT5677_DSP_INB2_SRC_CTRL3: 525 case RT5677_DSP_INB2_SRC_CTRL4: 526 case RT5677_DSP_INB3_SRC_CTRL1: 527 case RT5677_DSP_INB3_SRC_CTRL2: 528 case RT5677_DSP_INB3_SRC_CTRL3: 529 case RT5677_DSP_INB3_SRC_CTRL4: 530 case RT5677_DSP_OUTB1_SRC_CTRL1: 531 case RT5677_DSP_OUTB1_SRC_CTRL2: 532 case RT5677_DSP_OUTB1_SRC_CTRL3: 533 case RT5677_DSP_OUTB1_SRC_CTRL4: 534 case RT5677_DSP_OUTB2_SRC_CTRL1: 535 case RT5677_DSP_OUTB2_SRC_CTRL2: 536 case RT5677_DSP_OUTB2_SRC_CTRL3: 537 case RT5677_DSP_OUTB2_SRC_CTRL4: 538 case RT5677_DSP_OUTB_0123_MIXER_CTRL: 539 case RT5677_DSP_OUTB_45_MIXER_CTRL: 540 case RT5677_DSP_OUTB_67_MIXER_CTRL: 541 case RT5677_DIG_MISC: 542 case RT5677_GEN_CTRL1: 543 case RT5677_GEN_CTRL2: 544 case RT5677_VENDOR_ID: 545 case RT5677_VENDOR_ID1: 546 case RT5677_VENDOR_ID2: 547 return true; 548 default: 549 return false; 550 } 551 } 552 553 /** 554 * rt5677_dsp_mode_i2c_write_addr - Write value to address on DSP mode. 555 * @rt5677: Private Data. 556 * @addr: Address index. 557 * @value: Address data. 558 * @opcode: opcode value 559 * 560 * Returns 0 for success or negative error code. 561 */ 562 static int rt5677_dsp_mode_i2c_write_addr(struct rt5677_priv *rt5677, 563 unsigned int addr, unsigned int value, unsigned int opcode) 564 { 565 struct snd_soc_component *component = rt5677->component; 566 int ret; 567 568 mutex_lock(&rt5677->dsp_cmd_lock); 569 570 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_MSB, 571 addr >> 16); 572 if (ret < 0) { 573 dev_err(component->dev, "Failed to set addr msb value: %d\n", ret); 574 goto err; 575 } 576 577 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_LSB, 578 addr & 0xffff); 579 if (ret < 0) { 580 dev_err(component->dev, "Failed to set addr lsb value: %d\n", ret); 581 goto err; 582 } 583 584 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_MSB, 585 value >> 16); 586 if (ret < 0) { 587 dev_err(component->dev, "Failed to set data msb value: %d\n", ret); 588 goto err; 589 } 590 591 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_LSB, 592 value & 0xffff); 593 if (ret < 0) { 594 dev_err(component->dev, "Failed to set data lsb value: %d\n", ret); 595 goto err; 596 } 597 598 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_OP_CODE, 599 opcode); 600 if (ret < 0) { 601 dev_err(component->dev, "Failed to set op code value: %d\n", ret); 602 goto err; 603 } 604 605 err: 606 mutex_unlock(&rt5677->dsp_cmd_lock); 607 608 return ret; 609 } 610 611 /** 612 * rt5677_dsp_mode_i2c_read_addr - Read value from address on DSP mode. 613 * @rt5677: Private Data. 614 * @addr: Address index. 615 * @value: Address data. 616 * 617 * 618 * Returns 0 for success or negative error code. 619 */ 620 static int rt5677_dsp_mode_i2c_read_addr( 621 struct rt5677_priv *rt5677, unsigned int addr, unsigned int *value) 622 { 623 struct snd_soc_component *component = rt5677->component; 624 int ret; 625 unsigned int msb, lsb; 626 627 mutex_lock(&rt5677->dsp_cmd_lock); 628 629 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_MSB, 630 addr >> 16); 631 if (ret < 0) { 632 dev_err(component->dev, "Failed to set addr msb value: %d\n", ret); 633 goto err; 634 } 635 636 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_LSB, 637 addr & 0xffff); 638 if (ret < 0) { 639 dev_err(component->dev, "Failed to set addr lsb value: %d\n", ret); 640 goto err; 641 } 642 643 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_OP_CODE, 644 0x0002); 645 if (ret < 0) { 646 dev_err(component->dev, "Failed to set op code value: %d\n", ret); 647 goto err; 648 } 649 650 regmap_read(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_MSB, &msb); 651 regmap_read(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_LSB, &lsb); 652 *value = (msb << 16) | lsb; 653 654 err: 655 mutex_unlock(&rt5677->dsp_cmd_lock); 656 657 return ret; 658 } 659 660 /** 661 * rt5677_dsp_mode_i2c_write - Write register on DSP mode. 662 * @rt5677: Private Data. 663 * @reg: Register index. 664 * @value: Register data. 665 * 666 * 667 * Returns 0 for success or negative error code. 668 */ 669 static int rt5677_dsp_mode_i2c_write(struct rt5677_priv *rt5677, 670 unsigned int reg, unsigned int value) 671 { 672 return rt5677_dsp_mode_i2c_write_addr(rt5677, 0x18020000 + reg * 2, 673 value, 0x0001); 674 } 675 676 /** 677 * rt5677_dsp_mode_i2c_read - Read register on DSP mode. 678 * @rt5677: Private Data 679 * @reg: Register index. 680 * @value: Register data. 681 * 682 * 683 * Returns 0 for success or negative error code. 684 */ 685 static int rt5677_dsp_mode_i2c_read( 686 struct rt5677_priv *rt5677, unsigned int reg, unsigned int *value) 687 { 688 int ret = rt5677_dsp_mode_i2c_read_addr(rt5677, 0x18020000 + reg * 2, 689 value); 690 691 *value &= 0xffff; 692 693 return ret; 694 } 695 696 static void rt5677_set_dsp_mode(struct rt5677_priv *rt5677, bool on) 697 { 698 if (on) { 699 regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, 700 RT5677_PWR_DSP, RT5677_PWR_DSP); 701 rt5677->is_dsp_mode = true; 702 } else { 703 regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, 704 RT5677_PWR_DSP, 0x0); 705 rt5677->is_dsp_mode = false; 706 } 707 } 708 709 static unsigned int rt5677_set_vad_source(struct rt5677_priv *rt5677) 710 { 711 struct snd_soc_dapm_context *dapm = 712 snd_soc_component_get_dapm(rt5677->component); 713 /* Force dapm to sync before we enable the 714 * DSP to prevent write corruption 715 */ 716 snd_soc_dapm_sync(dapm); 717 718 /* DMIC1 power = enabled 719 * DMIC CLK = 256 * fs / 12 720 */ 721 regmap_update_bits(rt5677->regmap, RT5677_DMIC_CTRL1, 722 RT5677_DMIC_CLK_MASK, 5 << RT5677_DMIC_CLK_SFT); 723 724 /* I2S pre divide 2 = /6 (clk_sys2) */ 725 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1, 726 RT5677_I2S_PD2_MASK, RT5677_I2S_PD2_6); 727 728 /* DSP Clock = MCLK1 (bypassed PLL2) */ 729 regmap_write(rt5677->regmap, RT5677_GLB_CLK2, 730 RT5677_DSP_CLK_SRC_BYPASS); 731 732 /* SAD Threshold1 */ 733 regmap_write(rt5677->regmap, RT5677_VAD_CTRL2, 0x013f); 734 /* SAD Threshold2 */ 735 regmap_write(rt5677->regmap, RT5677_VAD_CTRL3, 0x0ae5); 736 /* SAD Sample Rate Converter = Up 6 (8K to 48K) 737 * SAD Output Sample Rate = Same as I2S 738 * SAD Threshold3 739 */ 740 regmap_update_bits(rt5677->regmap, RT5677_VAD_CTRL4, 741 RT5677_VAD_OUT_SRC_RATE_MASK | RT5677_VAD_OUT_SRC_MASK | 742 RT5677_VAD_LV_DIFF_MASK, 0x7f << RT5677_VAD_LV_DIFF_SFT); 743 /* Minimum frame level within a pre-determined duration = 32 frames 744 * Bypass ADPCM Encoder/Decoder = Bypass ADPCM 745 * Automatic Push Data to SAD Buffer Once SAD Flag is triggered = enable 746 * SAD Buffer Over-Writing = enable 747 * SAD Buffer Pop Mode Control = disable 748 * SAD Buffer Push Mode Control = enable 749 * SAD Detector Control = enable 750 * SAD Function Control = enable 751 * SAD Function Reset = normal 752 */ 753 regmap_write(rt5677->regmap, RT5677_VAD_CTRL1, 754 RT5677_VAD_FUNC_RESET | RT5677_VAD_FUNC_ENABLE | 755 RT5677_VAD_DET_ENABLE | RT5677_VAD_BUF_PUSH | 756 RT5677_VAD_BUF_OW | RT5677_VAD_FG2ENC | 757 RT5677_VAD_ADPCM_BYPASS | 1 << RT5677_VAD_MIN_DUR_SFT); 758 759 /* VAD/SAD is not routed to the IRQ output (i.e. MX-BE[14] = 0), but it 760 * is routed to DSP_IRQ_0, so DSP firmware may use it to sleep and save 761 * power. See ALC5677 datasheet section 9.17 "GPIO, Interrupt and Jack 762 * Detection" for more info. 763 */ 764 765 /* Private register, no doc */ 766 regmap_update_bits(rt5677->regmap, RT5677_PR_BASE + RT5677_BIAS_CUR4, 767 0x0f00, 0x0100); 768 769 /* LDO2 output = 1.2V 770 * LDO1 output = 1.2V (LDO_IN = 1.8V) 771 */ 772 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1, 773 RT5677_LDO1_SEL_MASK | RT5677_LDO2_SEL_MASK, 774 5 << RT5677_LDO1_SEL_SFT | 5 << RT5677_LDO2_SEL_SFT); 775 776 /* Codec core power = power on 777 * LDO1 power = power on 778 */ 779 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2, 780 RT5677_PWR_CORE | RT5677_PWR_LDO1, 781 RT5677_PWR_CORE | RT5677_PWR_LDO1); 782 783 /* Isolation for DCVDD4 = normal (set during probe) 784 * Isolation for DCVDD2 = normal (set during probe) 785 * Isolation for DSP = normal 786 * Isolation for Band 0~7 = disable 787 * Isolation for InBound 4~10 and OutBound 4~10 = disable 788 */ 789 regmap_write(rt5677->regmap, RT5677_PWR_DSP2, 790 RT5677_PWR_CORE_ISO | RT5677_PWR_DSP_ISO | 791 RT5677_PWR_SR7_ISO | RT5677_PWR_SR6_ISO | 792 RT5677_PWR_SR5_ISO | RT5677_PWR_SR4_ISO | 793 RT5677_PWR_SR3_ISO | RT5677_PWR_SR2_ISO | 794 RT5677_PWR_SR1_ISO | RT5677_PWR_SR0_ISO | 795 RT5677_PWR_MLT_ISO); 796 797 /* System Band 0~7 = power on 798 * InBound 4~10 and OutBound 4~10 = power on 799 * DSP = power on 800 * DSP CPU = stop (will be set to "run" after firmware loaded) 801 */ 802 regmap_write(rt5677->regmap, RT5677_PWR_DSP1, 803 RT5677_PWR_SR7 | RT5677_PWR_SR6 | 804 RT5677_PWR_SR5 | RT5677_PWR_SR4 | 805 RT5677_PWR_SR3 | RT5677_PWR_SR2 | 806 RT5677_PWR_SR1 | RT5677_PWR_SR0 | 807 RT5677_PWR_MLT | RT5677_PWR_DSP | 808 RT5677_PWR_DSP_CPU); 809 810 return 0; 811 } 812 813 static int rt5677_parse_and_load_dsp(struct rt5677_priv *rt5677, const u8 *buf, 814 unsigned int len) 815 { 816 struct snd_soc_component *component = rt5677->component; 817 Elf32_Ehdr *elf_hdr; 818 Elf32_Phdr *pr_hdr; 819 Elf32_Half i; 820 int ret = 0; 821 822 if (!buf || (len < sizeof(Elf32_Ehdr))) 823 return -ENOMEM; 824 825 elf_hdr = (Elf32_Ehdr *)buf; 826 #ifndef EM_XTENSA 827 #define EM_XTENSA 94 828 #endif 829 if (strncmp(elf_hdr->e_ident, ELFMAG, sizeof(ELFMAG) - 1)) 830 dev_err(component->dev, "Wrong ELF header prefix\n"); 831 if (elf_hdr->e_ehsize != sizeof(Elf32_Ehdr)) 832 dev_err(component->dev, "Wrong Elf header size\n"); 833 if (elf_hdr->e_machine != EM_XTENSA) 834 dev_err(component->dev, "Wrong DSP code file\n"); 835 836 if (len < elf_hdr->e_phoff) 837 return -ENOMEM; 838 pr_hdr = (Elf32_Phdr *)(buf + elf_hdr->e_phoff); 839 for (i = 0; i < elf_hdr->e_phnum; i++) { 840 /* TODO: handle p_memsz != p_filesz */ 841 if (pr_hdr->p_paddr && pr_hdr->p_filesz) { 842 dev_info(component->dev, "Load 0x%x bytes to 0x%x\n", 843 pr_hdr->p_filesz, pr_hdr->p_paddr); 844 845 ret = rt5677_spi_write(pr_hdr->p_paddr, 846 buf + pr_hdr->p_offset, 847 pr_hdr->p_filesz); 848 if (ret) 849 dev_err(component->dev, "Load firmware failed %d\n", 850 ret); 851 } 852 pr_hdr++; 853 } 854 return ret; 855 } 856 857 static int rt5677_load_dsp_from_file(struct rt5677_priv *rt5677) 858 { 859 const struct firmware *fwp; 860 struct device *dev = rt5677->component->dev; 861 int ret = 0; 862 863 /* Load dsp firmware from rt5677_elf_vad file */ 864 ret = request_firmware(&fwp, "rt5677_elf_vad", dev); 865 if (ret) { 866 dev_err(dev, "Request rt5677_elf_vad failed %d\n", ret); 867 return ret; 868 } 869 dev_info(dev, "Requested rt5677_elf_vad (%zu)\n", fwp->size); 870 871 ret = rt5677_parse_and_load_dsp(rt5677, fwp->data, fwp->size); 872 release_firmware(fwp); 873 return ret; 874 } 875 876 static int rt5677_set_dsp_vad(struct snd_soc_component *component, bool on) 877 { 878 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component); 879 rt5677->dsp_vad_en_request = on; 880 rt5677->dsp_vad_en = on; 881 882 if (!IS_ENABLED(CONFIG_SND_SOC_RT5677_SPI)) 883 return -ENXIO; 884 885 schedule_delayed_work(&rt5677->dsp_work, 0); 886 return 0; 887 } 888 889 static void rt5677_dsp_work(struct work_struct *work) 890 { 891 struct rt5677_priv *rt5677 = 892 container_of(work, struct rt5677_priv, dsp_work.work); 893 static bool activity; 894 bool enable = rt5677->dsp_vad_en; 895 int i, val; 896 897 898 dev_info(rt5677->component->dev, "DSP VAD: enable=%d, activity=%d\n", 899 enable, activity); 900 901 if (enable && !activity) { 902 activity = true; 903 904 /* Before a hotword is detected, GPIO1 pin is configured as IRQ 905 * output so that jack detect works. When a hotword is detected, 906 * the DSP firmware configures the GPIO1 pin as GPIO1 and 907 * drives a 1. rt5677_irq() is called after a rising edge on 908 * the GPIO1 pin, due to either jack detect event or hotword 909 * event, or both. All possible events are checked and handled 910 * in rt5677_irq() where GPIO1 pin is configured back to IRQ 911 * output if a hotword is detected. 912 */ 913 914 rt5677_set_vad_source(rt5677); 915 rt5677_set_dsp_mode(rt5677, true); 916 917 #define RT5677_BOOT_RETRY 20 918 for (i = 0; i < RT5677_BOOT_RETRY; i++) { 919 regmap_read(rt5677->regmap, RT5677_PWR_DSP_ST, &val); 920 if (val == 0x3ff) 921 break; 922 udelay(500); 923 } 924 if (i == RT5677_BOOT_RETRY && val != 0x3ff) { 925 dev_err(rt5677->component->dev, "DSP Boot Timed Out!"); 926 return; 927 } 928 929 /* Boot the firmware from IRAM instead of SRAM0. */ 930 rt5677_dsp_mode_i2c_write_addr(rt5677, RT5677_DSP_BOOT_VECTOR, 931 0x0009, 0x0003); 932 rt5677_dsp_mode_i2c_write_addr(rt5677, RT5677_DSP_BOOT_VECTOR, 933 0x0019, 0x0003); 934 rt5677_dsp_mode_i2c_write_addr(rt5677, RT5677_DSP_BOOT_VECTOR, 935 0x0009, 0x0003); 936 937 rt5677_load_dsp_from_file(rt5677); 938 939 /* Set DSP CPU to Run */ 940 regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, 941 RT5677_PWR_DSP_CPU, 0x0); 942 } else if (!enable && activity) { 943 activity = false; 944 945 /* Don't turn off the DSP while handling irqs */ 946 mutex_lock(&rt5677->irq_lock); 947 /* Set DSP CPU to Stop */ 948 regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, 949 RT5677_PWR_DSP_CPU, RT5677_PWR_DSP_CPU); 950 951 rt5677_set_dsp_mode(rt5677, false); 952 953 /* Disable and clear VAD interrupt */ 954 regmap_write(rt5677->regmap, RT5677_VAD_CTRL1, 0x2184); 955 956 /* Set GPIO1 pin back to be IRQ output for jack detect */ 957 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL1, 958 RT5677_GPIO1_PIN_MASK, RT5677_GPIO1_PIN_IRQ); 959 960 mutex_unlock(&rt5677->irq_lock); 961 } 962 } 963 964 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6525, 75, 0); 965 static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0); 966 static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0); 967 static const DECLARE_TLV_DB_SCALE(st_vol_tlv, -4650, 150, 0); 968 969 /* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */ 970 static const DECLARE_TLV_DB_RANGE(bst_tlv, 971 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0), 972 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0), 973 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0), 974 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0), 975 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0), 976 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0), 977 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0) 978 ); 979 980 static int rt5677_dsp_vad_get(struct snd_kcontrol *kcontrol, 981 struct snd_ctl_elem_value *ucontrol) 982 { 983 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 984 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component); 985 986 ucontrol->value.integer.value[0] = rt5677->dsp_vad_en_request; 987 988 return 0; 989 } 990 991 static int rt5677_dsp_vad_put(struct snd_kcontrol *kcontrol, 992 struct snd_ctl_elem_value *ucontrol) 993 { 994 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 995 996 rt5677_set_dsp_vad(component, !!ucontrol->value.integer.value[0]); 997 998 return 0; 999 } 1000 1001 static const struct snd_kcontrol_new rt5677_snd_controls[] = { 1002 /* OUTPUT Control */ 1003 SOC_SINGLE("OUT1 Playback Switch", RT5677_LOUT1, 1004 RT5677_LOUT1_L_MUTE_SFT, 1, 1), 1005 SOC_SINGLE("OUT2 Playback Switch", RT5677_LOUT1, 1006 RT5677_LOUT2_L_MUTE_SFT, 1, 1), 1007 SOC_SINGLE("OUT3 Playback Switch", RT5677_LOUT1, 1008 RT5677_LOUT3_L_MUTE_SFT, 1, 1), 1009 1010 /* DAC Digital Volume */ 1011 SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5677_DAC1_DIG_VOL, 1012 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 127, 0, dac_vol_tlv), 1013 SOC_DOUBLE_TLV("DAC2 Playback Volume", RT5677_DAC2_DIG_VOL, 1014 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 127, 0, dac_vol_tlv), 1015 SOC_DOUBLE_TLV("DAC3 Playback Volume", RT5677_DAC3_DIG_VOL, 1016 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 127, 0, dac_vol_tlv), 1017 SOC_DOUBLE_TLV("DAC4 Playback Volume", RT5677_DAC4_DIG_VOL, 1018 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 127, 0, dac_vol_tlv), 1019 1020 /* IN1/IN2 Control */ 1021 SOC_SINGLE_TLV("IN1 Boost", RT5677_IN1, RT5677_BST_SFT1, 8, 0, bst_tlv), 1022 SOC_SINGLE_TLV("IN2 Boost", RT5677_IN1, RT5677_BST_SFT2, 8, 0, bst_tlv), 1023 1024 /* ADC Digital Volume Control */ 1025 SOC_DOUBLE("ADC1 Capture Switch", RT5677_STO1_ADC_DIG_VOL, 1026 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1), 1027 SOC_DOUBLE("ADC2 Capture Switch", RT5677_STO2_ADC_DIG_VOL, 1028 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1), 1029 SOC_DOUBLE("ADC3 Capture Switch", RT5677_STO3_ADC_DIG_VOL, 1030 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1), 1031 SOC_DOUBLE("ADC4 Capture Switch", RT5677_STO4_ADC_DIG_VOL, 1032 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1), 1033 SOC_DOUBLE("Mono ADC Capture Switch", RT5677_MONO_ADC_DIG_VOL, 1034 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1), 1035 1036 SOC_DOUBLE_TLV("ADC1 Capture Volume", RT5677_STO1_ADC_DIG_VOL, 1037 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 63, 0, 1038 adc_vol_tlv), 1039 SOC_DOUBLE_TLV("ADC2 Capture Volume", RT5677_STO2_ADC_DIG_VOL, 1040 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 63, 0, 1041 adc_vol_tlv), 1042 SOC_DOUBLE_TLV("ADC3 Capture Volume", RT5677_STO3_ADC_DIG_VOL, 1043 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 63, 0, 1044 adc_vol_tlv), 1045 SOC_DOUBLE_TLV("ADC4 Capture Volume", RT5677_STO4_ADC_DIG_VOL, 1046 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 63, 0, 1047 adc_vol_tlv), 1048 SOC_DOUBLE_TLV("Mono ADC Capture Volume", RT5677_MONO_ADC_DIG_VOL, 1049 RT5677_MONO_ADC_L_VOL_SFT, RT5677_MONO_ADC_R_VOL_SFT, 63, 0, 1050 adc_vol_tlv), 1051 1052 /* Sidetone Control */ 1053 SOC_SINGLE_TLV("Sidetone Volume", RT5677_SIDETONE_CTRL, 1054 RT5677_ST_VOL_SFT, 31, 0, st_vol_tlv), 1055 1056 /* ADC Boost Volume Control */ 1057 SOC_DOUBLE_TLV("STO1 ADC Boost Volume", RT5677_STO1_2_ADC_BST, 1058 RT5677_STO1_ADC_L_BST_SFT, RT5677_STO1_ADC_R_BST_SFT, 3, 0, 1059 adc_bst_tlv), 1060 SOC_DOUBLE_TLV("STO2 ADC Boost Volume", RT5677_STO1_2_ADC_BST, 1061 RT5677_STO2_ADC_L_BST_SFT, RT5677_STO2_ADC_R_BST_SFT, 3, 0, 1062 adc_bst_tlv), 1063 SOC_DOUBLE_TLV("STO3 ADC Boost Volume", RT5677_STO3_4_ADC_BST, 1064 RT5677_STO3_ADC_L_BST_SFT, RT5677_STO3_ADC_R_BST_SFT, 3, 0, 1065 adc_bst_tlv), 1066 SOC_DOUBLE_TLV("STO4 ADC Boost Volume", RT5677_STO3_4_ADC_BST, 1067 RT5677_STO4_ADC_L_BST_SFT, RT5677_STO4_ADC_R_BST_SFT, 3, 0, 1068 adc_bst_tlv), 1069 SOC_DOUBLE_TLV("Mono ADC Boost Volume", RT5677_ADC_BST_CTRL2, 1070 RT5677_MONO_ADC_L_BST_SFT, RT5677_MONO_ADC_R_BST_SFT, 3, 0, 1071 adc_bst_tlv), 1072 1073 SOC_SINGLE_EXT("DSP VAD Switch", SND_SOC_NOPM, 0, 1, 0, 1074 rt5677_dsp_vad_get, rt5677_dsp_vad_put), 1075 }; 1076 1077 /** 1078 * set_dmic_clk - Set parameter of dmic. 1079 * 1080 * @w: DAPM widget. 1081 * @kcontrol: The kcontrol of this widget. 1082 * @event: Event id. 1083 * 1084 * Choose dmic clock between 1MHz and 3MHz. 1085 * It is better for clock to approximate 3MHz. 1086 */ 1087 static int set_dmic_clk(struct snd_soc_dapm_widget *w, 1088 struct snd_kcontrol *kcontrol, int event) 1089 { 1090 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1091 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component); 1092 int idx, rate; 1093 1094 rate = rt5677->sysclk / rl6231_get_pre_div(rt5677->regmap, 1095 RT5677_CLK_TREE_CTRL1, RT5677_I2S_PD1_SFT); 1096 idx = rl6231_calc_dmic_clk(rate); 1097 if (idx < 0) 1098 dev_err(component->dev, "Failed to set DMIC clock\n"); 1099 else 1100 regmap_update_bits(rt5677->regmap, RT5677_DMIC_CTRL1, 1101 RT5677_DMIC_CLK_MASK, idx << RT5677_DMIC_CLK_SFT); 1102 return idx; 1103 } 1104 1105 static int is_sys_clk_from_pll(struct snd_soc_dapm_widget *source, 1106 struct snd_soc_dapm_widget *sink) 1107 { 1108 struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm); 1109 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component); 1110 unsigned int val; 1111 1112 regmap_read(rt5677->regmap, RT5677_GLB_CLK1, &val); 1113 val &= RT5677_SCLK_SRC_MASK; 1114 if (val == RT5677_SCLK_SRC_PLL1) 1115 return 1; 1116 else 1117 return 0; 1118 } 1119 1120 static int is_using_asrc(struct snd_soc_dapm_widget *source, 1121 struct snd_soc_dapm_widget *sink) 1122 { 1123 struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm); 1124 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component); 1125 unsigned int reg, shift, val; 1126 1127 if (source->reg == RT5677_ASRC_1) { 1128 switch (source->shift) { 1129 case 12: 1130 reg = RT5677_ASRC_4; 1131 shift = 0; 1132 break; 1133 case 13: 1134 reg = RT5677_ASRC_4; 1135 shift = 4; 1136 break; 1137 case 14: 1138 reg = RT5677_ASRC_4; 1139 shift = 8; 1140 break; 1141 case 15: 1142 reg = RT5677_ASRC_4; 1143 shift = 12; 1144 break; 1145 default: 1146 return 0; 1147 } 1148 } else { 1149 switch (source->shift) { 1150 case 0: 1151 reg = RT5677_ASRC_6; 1152 shift = 8; 1153 break; 1154 case 1: 1155 reg = RT5677_ASRC_6; 1156 shift = 12; 1157 break; 1158 case 2: 1159 reg = RT5677_ASRC_5; 1160 shift = 0; 1161 break; 1162 case 3: 1163 reg = RT5677_ASRC_5; 1164 shift = 4; 1165 break; 1166 case 4: 1167 reg = RT5677_ASRC_5; 1168 shift = 8; 1169 break; 1170 case 5: 1171 reg = RT5677_ASRC_5; 1172 shift = 12; 1173 break; 1174 case 12: 1175 reg = RT5677_ASRC_3; 1176 shift = 0; 1177 break; 1178 case 13: 1179 reg = RT5677_ASRC_3; 1180 shift = 4; 1181 break; 1182 case 14: 1183 reg = RT5677_ASRC_3; 1184 shift = 12; 1185 break; 1186 default: 1187 return 0; 1188 } 1189 } 1190 1191 regmap_read(rt5677->regmap, reg, &val); 1192 val = (val >> shift) & 0xf; 1193 1194 switch (val) { 1195 case 1 ... 6: 1196 return 1; 1197 default: 1198 return 0; 1199 } 1200 1201 } 1202 1203 static int can_use_asrc(struct snd_soc_dapm_widget *source, 1204 struct snd_soc_dapm_widget *sink) 1205 { 1206 struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm); 1207 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component); 1208 1209 if (rt5677->sysclk > rt5677->lrck[RT5677_AIF1] * 384) 1210 return 1; 1211 1212 return 0; 1213 } 1214 1215 /** 1216 * rt5677_sel_asrc_clk_src - select ASRC clock source for a set of filters 1217 * @component: SoC audio component device. 1218 * @filter_mask: mask of filters. 1219 * @clk_src: clock source 1220 * 1221 * The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5677 can 1222 * only support standard 32fs or 64fs i2s format, ASRC should be enabled to 1223 * support special i2s clock format such as Intel's 100fs(100 * sampling rate). 1224 * ASRC function will track i2s clock and generate a corresponding system clock 1225 * for codec. This function provides an API to select the clock source for a 1226 * set of filters specified by the mask. And the codec driver will turn on ASRC 1227 * for these filters if ASRC is selected as their clock source. 1228 */ 1229 int rt5677_sel_asrc_clk_src(struct snd_soc_component *component, 1230 unsigned int filter_mask, unsigned int clk_src) 1231 { 1232 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component); 1233 unsigned int asrc3_mask = 0, asrc3_value = 0; 1234 unsigned int asrc4_mask = 0, asrc4_value = 0; 1235 unsigned int asrc5_mask = 0, asrc5_value = 0; 1236 unsigned int asrc6_mask = 0, asrc6_value = 0; 1237 unsigned int asrc7_mask = 0, asrc7_value = 0; 1238 unsigned int asrc8_mask = 0, asrc8_value = 0; 1239 1240 switch (clk_src) { 1241 case RT5677_CLK_SEL_SYS: 1242 case RT5677_CLK_SEL_I2S1_ASRC: 1243 case RT5677_CLK_SEL_I2S2_ASRC: 1244 case RT5677_CLK_SEL_I2S3_ASRC: 1245 case RT5677_CLK_SEL_I2S4_ASRC: 1246 case RT5677_CLK_SEL_I2S5_ASRC: 1247 case RT5677_CLK_SEL_I2S6_ASRC: 1248 case RT5677_CLK_SEL_SYS2: 1249 case RT5677_CLK_SEL_SYS3: 1250 case RT5677_CLK_SEL_SYS4: 1251 case RT5677_CLK_SEL_SYS5: 1252 case RT5677_CLK_SEL_SYS6: 1253 case RT5677_CLK_SEL_SYS7: 1254 break; 1255 1256 default: 1257 return -EINVAL; 1258 } 1259 1260 /* ASRC 3 */ 1261 if (filter_mask & RT5677_DA_STEREO_FILTER) { 1262 asrc3_mask |= RT5677_DA_STO_CLK_SEL_MASK; 1263 asrc3_value = (asrc3_value & ~RT5677_DA_STO_CLK_SEL_MASK) 1264 | (clk_src << RT5677_DA_STO_CLK_SEL_SFT); 1265 } 1266 1267 if (filter_mask & RT5677_DA_MONO2_L_FILTER) { 1268 asrc3_mask |= RT5677_DA_MONO2L_CLK_SEL_MASK; 1269 asrc3_value = (asrc3_value & ~RT5677_DA_MONO2L_CLK_SEL_MASK) 1270 | (clk_src << RT5677_DA_MONO2L_CLK_SEL_SFT); 1271 } 1272 1273 if (filter_mask & RT5677_DA_MONO2_R_FILTER) { 1274 asrc3_mask |= RT5677_DA_MONO2R_CLK_SEL_MASK; 1275 asrc3_value = (asrc3_value & ~RT5677_DA_MONO2R_CLK_SEL_MASK) 1276 | (clk_src << RT5677_DA_MONO2R_CLK_SEL_SFT); 1277 } 1278 1279 if (asrc3_mask) 1280 regmap_update_bits(rt5677->regmap, RT5677_ASRC_3, asrc3_mask, 1281 asrc3_value); 1282 1283 /* ASRC 4 */ 1284 if (filter_mask & RT5677_DA_MONO3_L_FILTER) { 1285 asrc4_mask |= RT5677_DA_MONO3L_CLK_SEL_MASK; 1286 asrc4_value = (asrc4_value & ~RT5677_DA_MONO3L_CLK_SEL_MASK) 1287 | (clk_src << RT5677_DA_MONO3L_CLK_SEL_SFT); 1288 } 1289 1290 if (filter_mask & RT5677_DA_MONO3_R_FILTER) { 1291 asrc4_mask |= RT5677_DA_MONO3R_CLK_SEL_MASK; 1292 asrc4_value = (asrc4_value & ~RT5677_DA_MONO3R_CLK_SEL_MASK) 1293 | (clk_src << RT5677_DA_MONO3R_CLK_SEL_SFT); 1294 } 1295 1296 if (filter_mask & RT5677_DA_MONO4_L_FILTER) { 1297 asrc4_mask |= RT5677_DA_MONO4L_CLK_SEL_MASK; 1298 asrc4_value = (asrc4_value & ~RT5677_DA_MONO4L_CLK_SEL_MASK) 1299 | (clk_src << RT5677_DA_MONO4L_CLK_SEL_SFT); 1300 } 1301 1302 if (filter_mask & RT5677_DA_MONO4_R_FILTER) { 1303 asrc4_mask |= RT5677_DA_MONO4R_CLK_SEL_MASK; 1304 asrc4_value = (asrc4_value & ~RT5677_DA_MONO4R_CLK_SEL_MASK) 1305 | (clk_src << RT5677_DA_MONO4R_CLK_SEL_SFT); 1306 } 1307 1308 if (asrc4_mask) 1309 regmap_update_bits(rt5677->regmap, RT5677_ASRC_4, asrc4_mask, 1310 asrc4_value); 1311 1312 /* ASRC 5 */ 1313 if (filter_mask & RT5677_AD_STEREO1_FILTER) { 1314 asrc5_mask |= RT5677_AD_STO1_CLK_SEL_MASK; 1315 asrc5_value = (asrc5_value & ~RT5677_AD_STO1_CLK_SEL_MASK) 1316 | (clk_src << RT5677_AD_STO1_CLK_SEL_SFT); 1317 } 1318 1319 if (filter_mask & RT5677_AD_STEREO2_FILTER) { 1320 asrc5_mask |= RT5677_AD_STO2_CLK_SEL_MASK; 1321 asrc5_value = (asrc5_value & ~RT5677_AD_STO2_CLK_SEL_MASK) 1322 | (clk_src << RT5677_AD_STO2_CLK_SEL_SFT); 1323 } 1324 1325 if (filter_mask & RT5677_AD_STEREO3_FILTER) { 1326 asrc5_mask |= RT5677_AD_STO3_CLK_SEL_MASK; 1327 asrc5_value = (asrc5_value & ~RT5677_AD_STO3_CLK_SEL_MASK) 1328 | (clk_src << RT5677_AD_STO3_CLK_SEL_SFT); 1329 } 1330 1331 if (filter_mask & RT5677_AD_STEREO4_FILTER) { 1332 asrc5_mask |= RT5677_AD_STO4_CLK_SEL_MASK; 1333 asrc5_value = (asrc5_value & ~RT5677_AD_STO4_CLK_SEL_MASK) 1334 | (clk_src << RT5677_AD_STO4_CLK_SEL_SFT); 1335 } 1336 1337 if (asrc5_mask) 1338 regmap_update_bits(rt5677->regmap, RT5677_ASRC_5, asrc5_mask, 1339 asrc5_value); 1340 1341 /* ASRC 6 */ 1342 if (filter_mask & RT5677_AD_MONO_L_FILTER) { 1343 asrc6_mask |= RT5677_AD_MONOL_CLK_SEL_MASK; 1344 asrc6_value = (asrc6_value & ~RT5677_AD_MONOL_CLK_SEL_MASK) 1345 | (clk_src << RT5677_AD_MONOL_CLK_SEL_SFT); 1346 } 1347 1348 if (filter_mask & RT5677_AD_MONO_R_FILTER) { 1349 asrc6_mask |= RT5677_AD_MONOR_CLK_SEL_MASK; 1350 asrc6_value = (asrc6_value & ~RT5677_AD_MONOR_CLK_SEL_MASK) 1351 | (clk_src << RT5677_AD_MONOR_CLK_SEL_SFT); 1352 } 1353 1354 if (asrc6_mask) 1355 regmap_update_bits(rt5677->regmap, RT5677_ASRC_6, asrc6_mask, 1356 asrc6_value); 1357 1358 /* ASRC 7 */ 1359 if (filter_mask & RT5677_DSP_OB_0_3_FILTER) { 1360 asrc7_mask |= RT5677_DSP_OB_0_3_CLK_SEL_MASK; 1361 asrc7_value = (asrc7_value & ~RT5677_DSP_OB_0_3_CLK_SEL_MASK) 1362 | (clk_src << RT5677_DSP_OB_0_3_CLK_SEL_SFT); 1363 } 1364 1365 if (filter_mask & RT5677_DSP_OB_4_7_FILTER) { 1366 asrc7_mask |= RT5677_DSP_OB_4_7_CLK_SEL_MASK; 1367 asrc7_value = (asrc7_value & ~RT5677_DSP_OB_4_7_CLK_SEL_MASK) 1368 | (clk_src << RT5677_DSP_OB_4_7_CLK_SEL_SFT); 1369 } 1370 1371 if (asrc7_mask) 1372 regmap_update_bits(rt5677->regmap, RT5677_ASRC_7, asrc7_mask, 1373 asrc7_value); 1374 1375 /* ASRC 8 */ 1376 if (filter_mask & RT5677_I2S1_SOURCE) { 1377 asrc8_mask |= RT5677_I2S1_CLK_SEL_MASK; 1378 asrc8_value = (asrc8_value & ~RT5677_I2S1_CLK_SEL_MASK) 1379 | ((clk_src - 1) << RT5677_I2S1_CLK_SEL_SFT); 1380 } 1381 1382 if (filter_mask & RT5677_I2S2_SOURCE) { 1383 asrc8_mask |= RT5677_I2S2_CLK_SEL_MASK; 1384 asrc8_value = (asrc8_value & ~RT5677_I2S2_CLK_SEL_MASK) 1385 | ((clk_src - 1) << RT5677_I2S2_CLK_SEL_SFT); 1386 } 1387 1388 if (filter_mask & RT5677_I2S3_SOURCE) { 1389 asrc8_mask |= RT5677_I2S3_CLK_SEL_MASK; 1390 asrc8_value = (asrc8_value & ~RT5677_I2S3_CLK_SEL_MASK) 1391 | ((clk_src - 1) << RT5677_I2S3_CLK_SEL_SFT); 1392 } 1393 1394 if (filter_mask & RT5677_I2S4_SOURCE) { 1395 asrc8_mask |= RT5677_I2S4_CLK_SEL_MASK; 1396 asrc8_value = (asrc8_value & ~RT5677_I2S4_CLK_SEL_MASK) 1397 | ((clk_src - 1) << RT5677_I2S4_CLK_SEL_SFT); 1398 } 1399 1400 if (asrc8_mask) 1401 regmap_update_bits(rt5677->regmap, RT5677_ASRC_8, asrc8_mask, 1402 asrc8_value); 1403 1404 return 0; 1405 } 1406 EXPORT_SYMBOL_GPL(rt5677_sel_asrc_clk_src); 1407 1408 static int rt5677_dmic_use_asrc(struct snd_soc_dapm_widget *source, 1409 struct snd_soc_dapm_widget *sink) 1410 { 1411 struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm); 1412 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component); 1413 unsigned int asrc_setting; 1414 1415 switch (source->shift) { 1416 case 11: 1417 regmap_read(rt5677->regmap, RT5677_ASRC_5, &asrc_setting); 1418 asrc_setting = (asrc_setting & RT5677_AD_STO1_CLK_SEL_MASK) >> 1419 RT5677_AD_STO1_CLK_SEL_SFT; 1420 break; 1421 1422 case 10: 1423 regmap_read(rt5677->regmap, RT5677_ASRC_5, &asrc_setting); 1424 asrc_setting = (asrc_setting & RT5677_AD_STO2_CLK_SEL_MASK) >> 1425 RT5677_AD_STO2_CLK_SEL_SFT; 1426 break; 1427 1428 case 9: 1429 regmap_read(rt5677->regmap, RT5677_ASRC_5, &asrc_setting); 1430 asrc_setting = (asrc_setting & RT5677_AD_STO3_CLK_SEL_MASK) >> 1431 RT5677_AD_STO3_CLK_SEL_SFT; 1432 break; 1433 1434 case 8: 1435 regmap_read(rt5677->regmap, RT5677_ASRC_5, &asrc_setting); 1436 asrc_setting = (asrc_setting & RT5677_AD_STO4_CLK_SEL_MASK) >> 1437 RT5677_AD_STO4_CLK_SEL_SFT; 1438 break; 1439 1440 case 7: 1441 regmap_read(rt5677->regmap, RT5677_ASRC_6, &asrc_setting); 1442 asrc_setting = (asrc_setting & RT5677_AD_MONOL_CLK_SEL_MASK) >> 1443 RT5677_AD_MONOL_CLK_SEL_SFT; 1444 break; 1445 1446 case 6: 1447 regmap_read(rt5677->regmap, RT5677_ASRC_6, &asrc_setting); 1448 asrc_setting = (asrc_setting & RT5677_AD_MONOR_CLK_SEL_MASK) >> 1449 RT5677_AD_MONOR_CLK_SEL_SFT; 1450 break; 1451 1452 default: 1453 return 0; 1454 } 1455 1456 if (asrc_setting >= RT5677_CLK_SEL_I2S1_ASRC && 1457 asrc_setting <= RT5677_CLK_SEL_I2S6_ASRC) 1458 return 1; 1459 1460 return 0; 1461 } 1462 1463 /* Digital Mixer */ 1464 static const struct snd_kcontrol_new rt5677_sto1_adc_l_mix[] = { 1465 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO1_ADC_MIXER, 1466 RT5677_M_STO1_ADC_L1_SFT, 1, 1), 1467 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO1_ADC_MIXER, 1468 RT5677_M_STO1_ADC_L2_SFT, 1, 1), 1469 }; 1470 1471 static const struct snd_kcontrol_new rt5677_sto1_adc_r_mix[] = { 1472 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO1_ADC_MIXER, 1473 RT5677_M_STO1_ADC_R1_SFT, 1, 1), 1474 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO1_ADC_MIXER, 1475 RT5677_M_STO1_ADC_R2_SFT, 1, 1), 1476 }; 1477 1478 static const struct snd_kcontrol_new rt5677_sto2_adc_l_mix[] = { 1479 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO2_ADC_MIXER, 1480 RT5677_M_STO2_ADC_L1_SFT, 1, 1), 1481 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO2_ADC_MIXER, 1482 RT5677_M_STO2_ADC_L2_SFT, 1, 1), 1483 }; 1484 1485 static const struct snd_kcontrol_new rt5677_sto2_adc_r_mix[] = { 1486 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO2_ADC_MIXER, 1487 RT5677_M_STO2_ADC_R1_SFT, 1, 1), 1488 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO2_ADC_MIXER, 1489 RT5677_M_STO2_ADC_R2_SFT, 1, 1), 1490 }; 1491 1492 static const struct snd_kcontrol_new rt5677_sto3_adc_l_mix[] = { 1493 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO3_ADC_MIXER, 1494 RT5677_M_STO3_ADC_L1_SFT, 1, 1), 1495 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO3_ADC_MIXER, 1496 RT5677_M_STO3_ADC_L2_SFT, 1, 1), 1497 }; 1498 1499 static const struct snd_kcontrol_new rt5677_sto3_adc_r_mix[] = { 1500 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO3_ADC_MIXER, 1501 RT5677_M_STO3_ADC_R1_SFT, 1, 1), 1502 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO3_ADC_MIXER, 1503 RT5677_M_STO3_ADC_R2_SFT, 1, 1), 1504 }; 1505 1506 static const struct snd_kcontrol_new rt5677_sto4_adc_l_mix[] = { 1507 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO4_ADC_MIXER, 1508 RT5677_M_STO4_ADC_L1_SFT, 1, 1), 1509 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO4_ADC_MIXER, 1510 RT5677_M_STO4_ADC_L2_SFT, 1, 1), 1511 }; 1512 1513 static const struct snd_kcontrol_new rt5677_sto4_adc_r_mix[] = { 1514 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO4_ADC_MIXER, 1515 RT5677_M_STO4_ADC_R1_SFT, 1, 1), 1516 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO4_ADC_MIXER, 1517 RT5677_M_STO4_ADC_R2_SFT, 1, 1), 1518 }; 1519 1520 static const struct snd_kcontrol_new rt5677_mono_adc_l_mix[] = { 1521 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_MONO_ADC_MIXER, 1522 RT5677_M_MONO_ADC_L1_SFT, 1, 1), 1523 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_MONO_ADC_MIXER, 1524 RT5677_M_MONO_ADC_L2_SFT, 1, 1), 1525 }; 1526 1527 static const struct snd_kcontrol_new rt5677_mono_adc_r_mix[] = { 1528 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_MONO_ADC_MIXER, 1529 RT5677_M_MONO_ADC_R1_SFT, 1, 1), 1530 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_MONO_ADC_MIXER, 1531 RT5677_M_MONO_ADC_R2_SFT, 1, 1), 1532 }; 1533 1534 static const struct snd_kcontrol_new rt5677_dac_l_mix[] = { 1535 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5677_ADC_IF_DSP_DAC1_MIXER, 1536 RT5677_M_ADDA_MIXER1_L_SFT, 1, 1), 1537 SOC_DAPM_SINGLE("DAC1 Switch", RT5677_ADC_IF_DSP_DAC1_MIXER, 1538 RT5677_M_DAC1_L_SFT, 1, 1), 1539 }; 1540 1541 static const struct snd_kcontrol_new rt5677_dac_r_mix[] = { 1542 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5677_ADC_IF_DSP_DAC1_MIXER, 1543 RT5677_M_ADDA_MIXER1_R_SFT, 1, 1), 1544 SOC_DAPM_SINGLE("DAC1 Switch", RT5677_ADC_IF_DSP_DAC1_MIXER, 1545 RT5677_M_DAC1_R_SFT, 1, 1), 1546 }; 1547 1548 static const struct snd_kcontrol_new rt5677_sto1_dac_l_mix[] = { 1549 SOC_DAPM_SINGLE_AUTODISABLE("ST L Switch", RT5677_STO1_DAC_MIXER, 1550 RT5677_M_ST_DAC1_L_SFT, 1, 1), 1551 SOC_DAPM_SINGLE_AUTODISABLE("DAC1 L Switch", RT5677_STO1_DAC_MIXER, 1552 RT5677_M_DAC1_L_STO_L_SFT, 1, 1), 1553 SOC_DAPM_SINGLE_AUTODISABLE("DAC2 L Switch", RT5677_STO1_DAC_MIXER, 1554 RT5677_M_DAC2_L_STO_L_SFT, 1, 1), 1555 SOC_DAPM_SINGLE_AUTODISABLE("DAC1 R Switch", RT5677_STO1_DAC_MIXER, 1556 RT5677_M_DAC1_R_STO_L_SFT, 1, 1), 1557 }; 1558 1559 static const struct snd_kcontrol_new rt5677_sto1_dac_r_mix[] = { 1560 SOC_DAPM_SINGLE_AUTODISABLE("ST R Switch", RT5677_STO1_DAC_MIXER, 1561 RT5677_M_ST_DAC1_R_SFT, 1, 1), 1562 SOC_DAPM_SINGLE_AUTODISABLE("DAC1 R Switch", RT5677_STO1_DAC_MIXER, 1563 RT5677_M_DAC1_R_STO_R_SFT, 1, 1), 1564 SOC_DAPM_SINGLE_AUTODISABLE("DAC2 R Switch", RT5677_STO1_DAC_MIXER, 1565 RT5677_M_DAC2_R_STO_R_SFT, 1, 1), 1566 SOC_DAPM_SINGLE_AUTODISABLE("DAC1 L Switch", RT5677_STO1_DAC_MIXER, 1567 RT5677_M_DAC1_L_STO_R_SFT, 1, 1), 1568 }; 1569 1570 static const struct snd_kcontrol_new rt5677_mono_dac_l_mix[] = { 1571 SOC_DAPM_SINGLE_AUTODISABLE("ST L Switch", RT5677_MONO_DAC_MIXER, 1572 RT5677_M_ST_DAC2_L_SFT, 1, 1), 1573 SOC_DAPM_SINGLE_AUTODISABLE("DAC1 L Switch", RT5677_MONO_DAC_MIXER, 1574 RT5677_M_DAC1_L_MONO_L_SFT, 1, 1), 1575 SOC_DAPM_SINGLE_AUTODISABLE("DAC2 L Switch", RT5677_MONO_DAC_MIXER, 1576 RT5677_M_DAC2_L_MONO_L_SFT, 1, 1), 1577 SOC_DAPM_SINGLE_AUTODISABLE("DAC2 R Switch", RT5677_MONO_DAC_MIXER, 1578 RT5677_M_DAC2_R_MONO_L_SFT, 1, 1), 1579 }; 1580 1581 static const struct snd_kcontrol_new rt5677_mono_dac_r_mix[] = { 1582 SOC_DAPM_SINGLE_AUTODISABLE("ST R Switch", RT5677_MONO_DAC_MIXER, 1583 RT5677_M_ST_DAC2_R_SFT, 1, 1), 1584 SOC_DAPM_SINGLE_AUTODISABLE("DAC1 R Switch", RT5677_MONO_DAC_MIXER, 1585 RT5677_M_DAC1_R_MONO_R_SFT, 1, 1), 1586 SOC_DAPM_SINGLE_AUTODISABLE("DAC2 R Switch", RT5677_MONO_DAC_MIXER, 1587 RT5677_M_DAC2_R_MONO_R_SFT, 1, 1), 1588 SOC_DAPM_SINGLE_AUTODISABLE("DAC2 L Switch", RT5677_MONO_DAC_MIXER, 1589 RT5677_M_DAC2_L_MONO_R_SFT, 1, 1), 1590 }; 1591 1592 static const struct snd_kcontrol_new rt5677_dd1_l_mix[] = { 1593 SOC_DAPM_SINGLE_AUTODISABLE("Sto DAC Mix L Switch", RT5677_DD1_MIXER, 1594 RT5677_M_STO_L_DD1_L_SFT, 1, 1), 1595 SOC_DAPM_SINGLE_AUTODISABLE("Mono DAC Mix L Switch", RT5677_DD1_MIXER, 1596 RT5677_M_MONO_L_DD1_L_SFT, 1, 1), 1597 SOC_DAPM_SINGLE_AUTODISABLE("DAC3 L Switch", RT5677_DD1_MIXER, 1598 RT5677_M_DAC3_L_DD1_L_SFT, 1, 1), 1599 SOC_DAPM_SINGLE_AUTODISABLE("DAC3 R Switch", RT5677_DD1_MIXER, 1600 RT5677_M_DAC3_R_DD1_L_SFT, 1, 1), 1601 }; 1602 1603 static const struct snd_kcontrol_new rt5677_dd1_r_mix[] = { 1604 SOC_DAPM_SINGLE_AUTODISABLE("Sto DAC Mix R Switch", RT5677_DD1_MIXER, 1605 RT5677_M_STO_R_DD1_R_SFT, 1, 1), 1606 SOC_DAPM_SINGLE_AUTODISABLE("Mono DAC Mix R Switch", RT5677_DD1_MIXER, 1607 RT5677_M_MONO_R_DD1_R_SFT, 1, 1), 1608 SOC_DAPM_SINGLE_AUTODISABLE("DAC3 R Switch", RT5677_DD1_MIXER, 1609 RT5677_M_DAC3_R_DD1_R_SFT, 1, 1), 1610 SOC_DAPM_SINGLE_AUTODISABLE("DAC3 L Switch", RT5677_DD1_MIXER, 1611 RT5677_M_DAC3_L_DD1_R_SFT, 1, 1), 1612 }; 1613 1614 static const struct snd_kcontrol_new rt5677_dd2_l_mix[] = { 1615 SOC_DAPM_SINGLE_AUTODISABLE("Sto DAC Mix L Switch", RT5677_DD2_MIXER, 1616 RT5677_M_STO_L_DD2_L_SFT, 1, 1), 1617 SOC_DAPM_SINGLE_AUTODISABLE("Mono DAC Mix L Switch", RT5677_DD2_MIXER, 1618 RT5677_M_MONO_L_DD2_L_SFT, 1, 1), 1619 SOC_DAPM_SINGLE_AUTODISABLE("DAC4 L Switch", RT5677_DD2_MIXER, 1620 RT5677_M_DAC4_L_DD2_L_SFT, 1, 1), 1621 SOC_DAPM_SINGLE_AUTODISABLE("DAC4 R Switch", RT5677_DD2_MIXER, 1622 RT5677_M_DAC4_R_DD2_L_SFT, 1, 1), 1623 }; 1624 1625 static const struct snd_kcontrol_new rt5677_dd2_r_mix[] = { 1626 SOC_DAPM_SINGLE_AUTODISABLE("Sto DAC Mix R Switch", RT5677_DD2_MIXER, 1627 RT5677_M_STO_R_DD2_R_SFT, 1, 1), 1628 SOC_DAPM_SINGLE_AUTODISABLE("Mono DAC Mix R Switch", RT5677_DD2_MIXER, 1629 RT5677_M_MONO_R_DD2_R_SFT, 1, 1), 1630 SOC_DAPM_SINGLE_AUTODISABLE("DAC4 R Switch", RT5677_DD2_MIXER, 1631 RT5677_M_DAC4_R_DD2_R_SFT, 1, 1), 1632 SOC_DAPM_SINGLE_AUTODISABLE("DAC4 L Switch", RT5677_DD2_MIXER, 1633 RT5677_M_DAC4_L_DD2_R_SFT, 1, 1), 1634 }; 1635 1636 static const struct snd_kcontrol_new rt5677_ob_01_mix[] = { 1637 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL, 1638 RT5677_DSP_IB_01_H_SFT, 1, 1), 1639 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL, 1640 RT5677_DSP_IB_23_H_SFT, 1, 1), 1641 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL, 1642 RT5677_DSP_IB_45_H_SFT, 1, 1), 1643 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL, 1644 RT5677_DSP_IB_6_H_SFT, 1, 1), 1645 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL, 1646 RT5677_DSP_IB_7_H_SFT, 1, 1), 1647 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL, 1648 RT5677_DSP_IB_8_H_SFT, 1, 1), 1649 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL, 1650 RT5677_DSP_IB_9_H_SFT, 1, 1), 1651 }; 1652 1653 static const struct snd_kcontrol_new rt5677_ob_23_mix[] = { 1654 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL, 1655 RT5677_DSP_IB_01_L_SFT, 1, 1), 1656 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL, 1657 RT5677_DSP_IB_23_L_SFT, 1, 1), 1658 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL, 1659 RT5677_DSP_IB_45_L_SFT, 1, 1), 1660 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL, 1661 RT5677_DSP_IB_6_L_SFT, 1, 1), 1662 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL, 1663 RT5677_DSP_IB_7_L_SFT, 1, 1), 1664 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL, 1665 RT5677_DSP_IB_8_L_SFT, 1, 1), 1666 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL, 1667 RT5677_DSP_IB_9_L_SFT, 1, 1), 1668 }; 1669 1670 static const struct snd_kcontrol_new rt5677_ob_4_mix[] = { 1671 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL, 1672 RT5677_DSP_IB_01_H_SFT, 1, 1), 1673 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL, 1674 RT5677_DSP_IB_23_H_SFT, 1, 1), 1675 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL, 1676 RT5677_DSP_IB_45_H_SFT, 1, 1), 1677 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL, 1678 RT5677_DSP_IB_6_H_SFT, 1, 1), 1679 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL, 1680 RT5677_DSP_IB_7_H_SFT, 1, 1), 1681 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL, 1682 RT5677_DSP_IB_8_H_SFT, 1, 1), 1683 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL, 1684 RT5677_DSP_IB_9_H_SFT, 1, 1), 1685 }; 1686 1687 static const struct snd_kcontrol_new rt5677_ob_5_mix[] = { 1688 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL, 1689 RT5677_DSP_IB_01_L_SFT, 1, 1), 1690 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL, 1691 RT5677_DSP_IB_23_L_SFT, 1, 1), 1692 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL, 1693 RT5677_DSP_IB_45_L_SFT, 1, 1), 1694 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL, 1695 RT5677_DSP_IB_6_L_SFT, 1, 1), 1696 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL, 1697 RT5677_DSP_IB_7_L_SFT, 1, 1), 1698 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL, 1699 RT5677_DSP_IB_8_L_SFT, 1, 1), 1700 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL, 1701 RT5677_DSP_IB_9_L_SFT, 1, 1), 1702 }; 1703 1704 static const struct snd_kcontrol_new rt5677_ob_6_mix[] = { 1705 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL, 1706 RT5677_DSP_IB_01_H_SFT, 1, 1), 1707 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL, 1708 RT5677_DSP_IB_23_H_SFT, 1, 1), 1709 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL, 1710 RT5677_DSP_IB_45_H_SFT, 1, 1), 1711 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL, 1712 RT5677_DSP_IB_6_H_SFT, 1, 1), 1713 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL, 1714 RT5677_DSP_IB_7_H_SFT, 1, 1), 1715 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL, 1716 RT5677_DSP_IB_8_H_SFT, 1, 1), 1717 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL, 1718 RT5677_DSP_IB_9_H_SFT, 1, 1), 1719 }; 1720 1721 static const struct snd_kcontrol_new rt5677_ob_7_mix[] = { 1722 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL, 1723 RT5677_DSP_IB_01_L_SFT, 1, 1), 1724 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL, 1725 RT5677_DSP_IB_23_L_SFT, 1, 1), 1726 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL, 1727 RT5677_DSP_IB_45_L_SFT, 1, 1), 1728 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL, 1729 RT5677_DSP_IB_6_L_SFT, 1, 1), 1730 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL, 1731 RT5677_DSP_IB_7_L_SFT, 1, 1), 1732 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL, 1733 RT5677_DSP_IB_8_L_SFT, 1, 1), 1734 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL, 1735 RT5677_DSP_IB_9_L_SFT, 1, 1), 1736 }; 1737 1738 1739 /* Mux */ 1740 /* DAC1 L/R Source */ /* MX-29 [10:8] */ 1741 static const char * const rt5677_dac1_src[] = { 1742 "IF1 DAC 01", "IF2 DAC 01", "IF3 DAC LR", "IF4 DAC LR", "SLB DAC 01", 1743 "OB 01" 1744 }; 1745 1746 static SOC_ENUM_SINGLE_DECL( 1747 rt5677_dac1_enum, RT5677_ADC_IF_DSP_DAC1_MIXER, 1748 RT5677_DAC1_L_SEL_SFT, rt5677_dac1_src); 1749 1750 static const struct snd_kcontrol_new rt5677_dac1_mux = 1751 SOC_DAPM_ENUM("DAC1 Source", rt5677_dac1_enum); 1752 1753 /* ADDA1 L/R Source */ /* MX-29 [1:0] */ 1754 static const char * const rt5677_adda1_src[] = { 1755 "STO1 ADC MIX", "STO2 ADC MIX", "OB 67", 1756 }; 1757 1758 static SOC_ENUM_SINGLE_DECL( 1759 rt5677_adda1_enum, RT5677_ADC_IF_DSP_DAC1_MIXER, 1760 RT5677_ADDA1_SEL_SFT, rt5677_adda1_src); 1761 1762 static const struct snd_kcontrol_new rt5677_adda1_mux = 1763 SOC_DAPM_ENUM("ADDA1 Source", rt5677_adda1_enum); 1764 1765 1766 /*DAC2 L/R Source*/ /* MX-1B [6:4] [2:0] */ 1767 static const char * const rt5677_dac2l_src[] = { 1768 "IF1 DAC 2", "IF2 DAC 2", "IF3 DAC L", "IF4 DAC L", "SLB DAC 2", 1769 "OB 2", 1770 }; 1771 1772 static SOC_ENUM_SINGLE_DECL( 1773 rt5677_dac2l_enum, RT5677_IF_DSP_DAC2_MIXER, 1774 RT5677_SEL_DAC2_L_SRC_SFT, rt5677_dac2l_src); 1775 1776 static const struct snd_kcontrol_new rt5677_dac2_l_mux = 1777 SOC_DAPM_ENUM("DAC2 L Source", rt5677_dac2l_enum); 1778 1779 static const char * const rt5677_dac2r_src[] = { 1780 "IF1 DAC 3", "IF2 DAC 3", "IF3 DAC R", "IF4 DAC R", "SLB DAC 3", 1781 "OB 3", "Haptic Generator", "VAD ADC" 1782 }; 1783 1784 static SOC_ENUM_SINGLE_DECL( 1785 rt5677_dac2r_enum, RT5677_IF_DSP_DAC2_MIXER, 1786 RT5677_SEL_DAC2_R_SRC_SFT, rt5677_dac2r_src); 1787 1788 static const struct snd_kcontrol_new rt5677_dac2_r_mux = 1789 SOC_DAPM_ENUM("DAC2 R Source", rt5677_dac2r_enum); 1790 1791 /*DAC3 L/R Source*/ /* MX-16 [6:4] [2:0] */ 1792 static const char * const rt5677_dac3l_src[] = { 1793 "IF1 DAC 4", "IF2 DAC 4", "IF3 DAC L", "IF4 DAC L", 1794 "SLB DAC 4", "OB 4" 1795 }; 1796 1797 static SOC_ENUM_SINGLE_DECL( 1798 rt5677_dac3l_enum, RT5677_IF_DSP_DAC3_4_MIXER, 1799 RT5677_SEL_DAC3_L_SRC_SFT, rt5677_dac3l_src); 1800 1801 static const struct snd_kcontrol_new rt5677_dac3_l_mux = 1802 SOC_DAPM_ENUM("DAC3 L Source", rt5677_dac3l_enum); 1803 1804 static const char * const rt5677_dac3r_src[] = { 1805 "IF1 DAC 5", "IF2 DAC 5", "IF3 DAC R", "IF4 DAC R", 1806 "SLB DAC 5", "OB 5" 1807 }; 1808 1809 static SOC_ENUM_SINGLE_DECL( 1810 rt5677_dac3r_enum, RT5677_IF_DSP_DAC3_4_MIXER, 1811 RT5677_SEL_DAC3_R_SRC_SFT, rt5677_dac3r_src); 1812 1813 static const struct snd_kcontrol_new rt5677_dac3_r_mux = 1814 SOC_DAPM_ENUM("DAC3 R Source", rt5677_dac3r_enum); 1815 1816 /*DAC4 L/R Source*/ /* MX-16 [14:12] [10:8] */ 1817 static const char * const rt5677_dac4l_src[] = { 1818 "IF1 DAC 6", "IF2 DAC 6", "IF3 DAC L", "IF4 DAC L", 1819 "SLB DAC 6", "OB 6" 1820 }; 1821 1822 static SOC_ENUM_SINGLE_DECL( 1823 rt5677_dac4l_enum, RT5677_IF_DSP_DAC3_4_MIXER, 1824 RT5677_SEL_DAC4_L_SRC_SFT, rt5677_dac4l_src); 1825 1826 static const struct snd_kcontrol_new rt5677_dac4_l_mux = 1827 SOC_DAPM_ENUM("DAC4 L Source", rt5677_dac4l_enum); 1828 1829 static const char * const rt5677_dac4r_src[] = { 1830 "IF1 DAC 7", "IF2 DAC 7", "IF3 DAC R", "IF4 DAC R", 1831 "SLB DAC 7", "OB 7" 1832 }; 1833 1834 static SOC_ENUM_SINGLE_DECL( 1835 rt5677_dac4r_enum, RT5677_IF_DSP_DAC3_4_MIXER, 1836 RT5677_SEL_DAC4_R_SRC_SFT, rt5677_dac4r_src); 1837 1838 static const struct snd_kcontrol_new rt5677_dac4_r_mux = 1839 SOC_DAPM_ENUM("DAC4 R Source", rt5677_dac4r_enum); 1840 1841 /* In/OutBound Source Pass SRC */ /* MX-A5 [3] [4] [0] [1] [2] */ 1842 static const char * const rt5677_iob_bypass_src[] = { 1843 "Bypass", "Pass SRC" 1844 }; 1845 1846 static SOC_ENUM_SINGLE_DECL( 1847 rt5677_ob01_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL, 1848 RT5677_SEL_SRC_OB01_SFT, rt5677_iob_bypass_src); 1849 1850 static const struct snd_kcontrol_new rt5677_ob01_bypass_src_mux = 1851 SOC_DAPM_ENUM("OB01 Bypass Source", rt5677_ob01_bypass_src_enum); 1852 1853 static SOC_ENUM_SINGLE_DECL( 1854 rt5677_ob23_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL, 1855 RT5677_SEL_SRC_OB23_SFT, rt5677_iob_bypass_src); 1856 1857 static const struct snd_kcontrol_new rt5677_ob23_bypass_src_mux = 1858 SOC_DAPM_ENUM("OB23 Bypass Source", rt5677_ob23_bypass_src_enum); 1859 1860 static SOC_ENUM_SINGLE_DECL( 1861 rt5677_ib01_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL, 1862 RT5677_SEL_SRC_IB01_SFT, rt5677_iob_bypass_src); 1863 1864 static const struct snd_kcontrol_new rt5677_ib01_bypass_src_mux = 1865 SOC_DAPM_ENUM("IB01 Bypass Source", rt5677_ib01_bypass_src_enum); 1866 1867 static SOC_ENUM_SINGLE_DECL( 1868 rt5677_ib23_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL, 1869 RT5677_SEL_SRC_IB23_SFT, rt5677_iob_bypass_src); 1870 1871 static const struct snd_kcontrol_new rt5677_ib23_bypass_src_mux = 1872 SOC_DAPM_ENUM("IB23 Bypass Source", rt5677_ib23_bypass_src_enum); 1873 1874 static SOC_ENUM_SINGLE_DECL( 1875 rt5677_ib45_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL, 1876 RT5677_SEL_SRC_IB45_SFT, rt5677_iob_bypass_src); 1877 1878 static const struct snd_kcontrol_new rt5677_ib45_bypass_src_mux = 1879 SOC_DAPM_ENUM("IB45 Bypass Source", rt5677_ib45_bypass_src_enum); 1880 1881 /* Stereo ADC Source 2 */ /* MX-27 MX26 MX25 [11:10] */ 1882 static const char * const rt5677_stereo_adc2_src[] = { 1883 "DD MIX1", "DMIC", "Stereo DAC MIX" 1884 }; 1885 1886 static SOC_ENUM_SINGLE_DECL( 1887 rt5677_stereo1_adc2_enum, RT5677_STO1_ADC_MIXER, 1888 RT5677_SEL_STO1_ADC2_SFT, rt5677_stereo_adc2_src); 1889 1890 static const struct snd_kcontrol_new rt5677_sto1_adc2_mux = 1891 SOC_DAPM_ENUM("Stereo1 ADC2 Source", rt5677_stereo1_adc2_enum); 1892 1893 static SOC_ENUM_SINGLE_DECL( 1894 rt5677_stereo2_adc2_enum, RT5677_STO2_ADC_MIXER, 1895 RT5677_SEL_STO2_ADC2_SFT, rt5677_stereo_adc2_src); 1896 1897 static const struct snd_kcontrol_new rt5677_sto2_adc2_mux = 1898 SOC_DAPM_ENUM("Stereo2 ADC2 Source", rt5677_stereo2_adc2_enum); 1899 1900 static SOC_ENUM_SINGLE_DECL( 1901 rt5677_stereo3_adc2_enum, RT5677_STO3_ADC_MIXER, 1902 RT5677_SEL_STO3_ADC2_SFT, rt5677_stereo_adc2_src); 1903 1904 static const struct snd_kcontrol_new rt5677_sto3_adc2_mux = 1905 SOC_DAPM_ENUM("Stereo3 ADC2 Source", rt5677_stereo3_adc2_enum); 1906 1907 /* DMIC Source */ /* MX-28 [9:8][1:0] MX-27 MX-26 MX-25 MX-24 [9:8] */ 1908 static const char * const rt5677_dmic_src[] = { 1909 "DMIC1", "DMIC2", "DMIC3", "DMIC4" 1910 }; 1911 1912 static SOC_ENUM_SINGLE_DECL( 1913 rt5677_mono_dmic_l_enum, RT5677_MONO_ADC_MIXER, 1914 RT5677_SEL_MONO_DMIC_L_SFT, rt5677_dmic_src); 1915 1916 static const struct snd_kcontrol_new rt5677_mono_dmic_l_mux = 1917 SOC_DAPM_ENUM("Mono DMIC L Source", rt5677_mono_dmic_l_enum); 1918 1919 static SOC_ENUM_SINGLE_DECL( 1920 rt5677_mono_dmic_r_enum, RT5677_MONO_ADC_MIXER, 1921 RT5677_SEL_MONO_DMIC_R_SFT, rt5677_dmic_src); 1922 1923 static const struct snd_kcontrol_new rt5677_mono_dmic_r_mux = 1924 SOC_DAPM_ENUM("Mono DMIC R Source", rt5677_mono_dmic_r_enum); 1925 1926 static SOC_ENUM_SINGLE_DECL( 1927 rt5677_stereo1_dmic_enum, RT5677_STO1_ADC_MIXER, 1928 RT5677_SEL_STO1_DMIC_SFT, rt5677_dmic_src); 1929 1930 static const struct snd_kcontrol_new rt5677_sto1_dmic_mux = 1931 SOC_DAPM_ENUM("Stereo1 DMIC Source", rt5677_stereo1_dmic_enum); 1932 1933 static SOC_ENUM_SINGLE_DECL( 1934 rt5677_stereo2_dmic_enum, RT5677_STO2_ADC_MIXER, 1935 RT5677_SEL_STO2_DMIC_SFT, rt5677_dmic_src); 1936 1937 static const struct snd_kcontrol_new rt5677_sto2_dmic_mux = 1938 SOC_DAPM_ENUM("Stereo2 DMIC Source", rt5677_stereo2_dmic_enum); 1939 1940 static SOC_ENUM_SINGLE_DECL( 1941 rt5677_stereo3_dmic_enum, RT5677_STO3_ADC_MIXER, 1942 RT5677_SEL_STO3_DMIC_SFT, rt5677_dmic_src); 1943 1944 static const struct snd_kcontrol_new rt5677_sto3_dmic_mux = 1945 SOC_DAPM_ENUM("Stereo3 DMIC Source", rt5677_stereo3_dmic_enum); 1946 1947 static SOC_ENUM_SINGLE_DECL( 1948 rt5677_stereo4_dmic_enum, RT5677_STO4_ADC_MIXER, 1949 RT5677_SEL_STO4_DMIC_SFT, rt5677_dmic_src); 1950 1951 static const struct snd_kcontrol_new rt5677_sto4_dmic_mux = 1952 SOC_DAPM_ENUM("Stereo4 DMIC Source", rt5677_stereo4_dmic_enum); 1953 1954 /* Stereo2 ADC Source */ /* MX-26 [0] */ 1955 static const char * const rt5677_stereo2_adc_lr_src[] = { 1956 "L", "LR" 1957 }; 1958 1959 static SOC_ENUM_SINGLE_DECL( 1960 rt5677_stereo2_adc_lr_enum, RT5677_STO2_ADC_MIXER, 1961 RT5677_SEL_STO2_LR_MIX_SFT, rt5677_stereo2_adc_lr_src); 1962 1963 static const struct snd_kcontrol_new rt5677_sto2_adc_lr_mux = 1964 SOC_DAPM_ENUM("Stereo2 ADC LR Source", rt5677_stereo2_adc_lr_enum); 1965 1966 /* Stereo1 ADC Source 1 */ /* MX-27 MX26 MX25 [13:12] */ 1967 static const char * const rt5677_stereo_adc1_src[] = { 1968 "DD MIX1", "ADC1/2", "Stereo DAC MIX" 1969 }; 1970 1971 static SOC_ENUM_SINGLE_DECL( 1972 rt5677_stereo1_adc1_enum, RT5677_STO1_ADC_MIXER, 1973 RT5677_SEL_STO1_ADC1_SFT, rt5677_stereo_adc1_src); 1974 1975 static const struct snd_kcontrol_new rt5677_sto1_adc1_mux = 1976 SOC_DAPM_ENUM("Stereo1 ADC1 Source", rt5677_stereo1_adc1_enum); 1977 1978 static SOC_ENUM_SINGLE_DECL( 1979 rt5677_stereo2_adc1_enum, RT5677_STO2_ADC_MIXER, 1980 RT5677_SEL_STO2_ADC1_SFT, rt5677_stereo_adc1_src); 1981 1982 static const struct snd_kcontrol_new rt5677_sto2_adc1_mux = 1983 SOC_DAPM_ENUM("Stereo2 ADC1 Source", rt5677_stereo2_adc1_enum); 1984 1985 static SOC_ENUM_SINGLE_DECL( 1986 rt5677_stereo3_adc1_enum, RT5677_STO3_ADC_MIXER, 1987 RT5677_SEL_STO3_ADC1_SFT, rt5677_stereo_adc1_src); 1988 1989 static const struct snd_kcontrol_new rt5677_sto3_adc1_mux = 1990 SOC_DAPM_ENUM("Stereo3 ADC1 Source", rt5677_stereo3_adc1_enum); 1991 1992 /* Mono ADC Left Source 2 */ /* MX-28 [11:10] */ 1993 static const char * const rt5677_mono_adc2_l_src[] = { 1994 "DD MIX1L", "DMIC", "MONO DAC MIXL" 1995 }; 1996 1997 static SOC_ENUM_SINGLE_DECL( 1998 rt5677_mono_adc2_l_enum, RT5677_MONO_ADC_MIXER, 1999 RT5677_SEL_MONO_ADC_L2_SFT, rt5677_mono_adc2_l_src); 2000 2001 static const struct snd_kcontrol_new rt5677_mono_adc2_l_mux = 2002 SOC_DAPM_ENUM("Mono ADC2 L Source", rt5677_mono_adc2_l_enum); 2003 2004 /* Mono ADC Left Source 1 */ /* MX-28 [13:12] */ 2005 static const char * const rt5677_mono_adc1_l_src[] = { 2006 "DD MIX1L", "ADC1", "MONO DAC MIXL" 2007 }; 2008 2009 static SOC_ENUM_SINGLE_DECL( 2010 rt5677_mono_adc1_l_enum, RT5677_MONO_ADC_MIXER, 2011 RT5677_SEL_MONO_ADC_L1_SFT, rt5677_mono_adc1_l_src); 2012 2013 static const struct snd_kcontrol_new rt5677_mono_adc1_l_mux = 2014 SOC_DAPM_ENUM("Mono ADC1 L Source", rt5677_mono_adc1_l_enum); 2015 2016 /* Mono ADC Right Source 2 */ /* MX-28 [3:2] */ 2017 static const char * const rt5677_mono_adc2_r_src[] = { 2018 "DD MIX1R", "DMIC", "MONO DAC MIXR" 2019 }; 2020 2021 static SOC_ENUM_SINGLE_DECL( 2022 rt5677_mono_adc2_r_enum, RT5677_MONO_ADC_MIXER, 2023 RT5677_SEL_MONO_ADC_R2_SFT, rt5677_mono_adc2_r_src); 2024 2025 static const struct snd_kcontrol_new rt5677_mono_adc2_r_mux = 2026 SOC_DAPM_ENUM("Mono ADC2 R Source", rt5677_mono_adc2_r_enum); 2027 2028 /* Mono ADC Right Source 1 */ /* MX-28 [5:4] */ 2029 static const char * const rt5677_mono_adc1_r_src[] = { 2030 "DD MIX1R", "ADC2", "MONO DAC MIXR" 2031 }; 2032 2033 static SOC_ENUM_SINGLE_DECL( 2034 rt5677_mono_adc1_r_enum, RT5677_MONO_ADC_MIXER, 2035 RT5677_SEL_MONO_ADC_R1_SFT, rt5677_mono_adc1_r_src); 2036 2037 static const struct snd_kcontrol_new rt5677_mono_adc1_r_mux = 2038 SOC_DAPM_ENUM("Mono ADC1 R Source", rt5677_mono_adc1_r_enum); 2039 2040 /* Stereo4 ADC Source 2 */ /* MX-24 [11:10] */ 2041 static const char * const rt5677_stereo4_adc2_src[] = { 2042 "DD MIX1", "DMIC", "DD MIX2" 2043 }; 2044 2045 static SOC_ENUM_SINGLE_DECL( 2046 rt5677_stereo4_adc2_enum, RT5677_STO4_ADC_MIXER, 2047 RT5677_SEL_STO4_ADC2_SFT, rt5677_stereo4_adc2_src); 2048 2049 static const struct snd_kcontrol_new rt5677_sto4_adc2_mux = 2050 SOC_DAPM_ENUM("Stereo4 ADC2 Source", rt5677_stereo4_adc2_enum); 2051 2052 2053 /* Stereo4 ADC Source 1 */ /* MX-24 [13:12] */ 2054 static const char * const rt5677_stereo4_adc1_src[] = { 2055 "DD MIX1", "ADC1/2", "DD MIX2" 2056 }; 2057 2058 static SOC_ENUM_SINGLE_DECL( 2059 rt5677_stereo4_adc1_enum, RT5677_STO4_ADC_MIXER, 2060 RT5677_SEL_STO4_ADC1_SFT, rt5677_stereo4_adc1_src); 2061 2062 static const struct snd_kcontrol_new rt5677_sto4_adc1_mux = 2063 SOC_DAPM_ENUM("Stereo4 ADC1 Source", rt5677_stereo4_adc1_enum); 2064 2065 /* InBound0/1 Source */ /* MX-A3 [14:12] */ 2066 static const char * const rt5677_inbound01_src[] = { 2067 "IF1 DAC 01", "IF2 DAC 01", "SLB DAC 01", "STO1 ADC MIX", 2068 "VAD ADC/DAC1 FS" 2069 }; 2070 2071 static SOC_ENUM_SINGLE_DECL( 2072 rt5677_inbound01_enum, RT5677_DSP_INB_CTRL1, 2073 RT5677_IB01_SRC_SFT, rt5677_inbound01_src); 2074 2075 static const struct snd_kcontrol_new rt5677_ib01_src_mux = 2076 SOC_DAPM_ENUM("InBound0/1 Source", rt5677_inbound01_enum); 2077 2078 /* InBound2/3 Source */ /* MX-A3 [10:8] */ 2079 static const char * const rt5677_inbound23_src[] = { 2080 "IF1 DAC 23", "IF2 DAC 23", "SLB DAC 23", "STO2 ADC MIX", 2081 "DAC1 FS", "IF4 DAC" 2082 }; 2083 2084 static SOC_ENUM_SINGLE_DECL( 2085 rt5677_inbound23_enum, RT5677_DSP_INB_CTRL1, 2086 RT5677_IB23_SRC_SFT, rt5677_inbound23_src); 2087 2088 static const struct snd_kcontrol_new rt5677_ib23_src_mux = 2089 SOC_DAPM_ENUM("InBound2/3 Source", rt5677_inbound23_enum); 2090 2091 /* InBound4/5 Source */ /* MX-A3 [6:4] */ 2092 static const char * const rt5677_inbound45_src[] = { 2093 "IF1 DAC 45", "IF2 DAC 45", "SLB DAC 45", "STO3 ADC MIX", 2094 "IF3 DAC" 2095 }; 2096 2097 static SOC_ENUM_SINGLE_DECL( 2098 rt5677_inbound45_enum, RT5677_DSP_INB_CTRL1, 2099 RT5677_IB45_SRC_SFT, rt5677_inbound45_src); 2100 2101 static const struct snd_kcontrol_new rt5677_ib45_src_mux = 2102 SOC_DAPM_ENUM("InBound4/5 Source", rt5677_inbound45_enum); 2103 2104 /* InBound6 Source */ /* MX-A3 [2:0] */ 2105 static const char * const rt5677_inbound6_src[] = { 2106 "IF1 DAC 6", "IF2 DAC 6", "SLB DAC 6", "STO4 ADC MIX L", 2107 "IF4 DAC L", "STO1 ADC MIX L", "STO2 ADC MIX L", "STO3 ADC MIX L" 2108 }; 2109 2110 static SOC_ENUM_SINGLE_DECL( 2111 rt5677_inbound6_enum, RT5677_DSP_INB_CTRL1, 2112 RT5677_IB6_SRC_SFT, rt5677_inbound6_src); 2113 2114 static const struct snd_kcontrol_new rt5677_ib6_src_mux = 2115 SOC_DAPM_ENUM("InBound6 Source", rt5677_inbound6_enum); 2116 2117 /* InBound7 Source */ /* MX-A4 [14:12] */ 2118 static const char * const rt5677_inbound7_src[] = { 2119 "IF1 DAC 7", "IF2 DAC 7", "SLB DAC 7", "STO4 ADC MIX R", 2120 "IF4 DAC R", "STO1 ADC MIX R", "STO2 ADC MIX R", "STO3 ADC MIX R" 2121 }; 2122 2123 static SOC_ENUM_SINGLE_DECL( 2124 rt5677_inbound7_enum, RT5677_DSP_INB_CTRL2, 2125 RT5677_IB7_SRC_SFT, rt5677_inbound7_src); 2126 2127 static const struct snd_kcontrol_new rt5677_ib7_src_mux = 2128 SOC_DAPM_ENUM("InBound7 Source", rt5677_inbound7_enum); 2129 2130 /* InBound8 Source */ /* MX-A4 [10:8] */ 2131 static const char * const rt5677_inbound8_src[] = { 2132 "STO1 ADC MIX L", "STO2 ADC MIX L", "STO3 ADC MIX L", "STO4 ADC MIX L", 2133 "MONO ADC MIX L", "DACL1 FS" 2134 }; 2135 2136 static SOC_ENUM_SINGLE_DECL( 2137 rt5677_inbound8_enum, RT5677_DSP_INB_CTRL2, 2138 RT5677_IB8_SRC_SFT, rt5677_inbound8_src); 2139 2140 static const struct snd_kcontrol_new rt5677_ib8_src_mux = 2141 SOC_DAPM_ENUM("InBound8 Source", rt5677_inbound8_enum); 2142 2143 /* InBound9 Source */ /* MX-A4 [6:4] */ 2144 static const char * const rt5677_inbound9_src[] = { 2145 "STO1 ADC MIX R", "STO2 ADC MIX R", "STO3 ADC MIX R", "STO4 ADC MIX R", 2146 "MONO ADC MIX R", "DACR1 FS", "DAC1 FS" 2147 }; 2148 2149 static SOC_ENUM_SINGLE_DECL( 2150 rt5677_inbound9_enum, RT5677_DSP_INB_CTRL2, 2151 RT5677_IB9_SRC_SFT, rt5677_inbound9_src); 2152 2153 static const struct snd_kcontrol_new rt5677_ib9_src_mux = 2154 SOC_DAPM_ENUM("InBound9 Source", rt5677_inbound9_enum); 2155 2156 /* VAD Source */ /* MX-9F [6:4] */ 2157 static const char * const rt5677_vad_src[] = { 2158 "STO1 ADC MIX L", "MONO ADC MIX L", "MONO ADC MIX R", "STO2 ADC MIX L", 2159 "STO3 ADC MIX L" 2160 }; 2161 2162 static SOC_ENUM_SINGLE_DECL( 2163 rt5677_vad_enum, RT5677_VAD_CTRL4, 2164 RT5677_VAD_SRC_SFT, rt5677_vad_src); 2165 2166 static const struct snd_kcontrol_new rt5677_vad_src_mux = 2167 SOC_DAPM_ENUM("VAD Source", rt5677_vad_enum); 2168 2169 /* Sidetone Source */ /* MX-13 [11:9] */ 2170 static const char * const rt5677_sidetone_src[] = { 2171 "DMIC1 L", "DMIC2 L", "DMIC3 L", "DMIC4 L", "ADC1", "ADC2" 2172 }; 2173 2174 static SOC_ENUM_SINGLE_DECL( 2175 rt5677_sidetone_enum, RT5677_SIDETONE_CTRL, 2176 RT5677_ST_SEL_SFT, rt5677_sidetone_src); 2177 2178 static const struct snd_kcontrol_new rt5677_sidetone_mux = 2179 SOC_DAPM_ENUM("Sidetone Source", rt5677_sidetone_enum); 2180 2181 /* DAC1/2 Source */ /* MX-15 [1:0] */ 2182 static const char * const rt5677_dac12_src[] = { 2183 "STO1 DAC MIX", "MONO DAC MIX", "DD MIX1", "DD MIX2" 2184 }; 2185 2186 static SOC_ENUM_SINGLE_DECL( 2187 rt5677_dac12_enum, RT5677_ANA_DAC1_2_3_SRC, 2188 RT5677_ANA_DAC1_2_SRC_SEL_SFT, rt5677_dac12_src); 2189 2190 static const struct snd_kcontrol_new rt5677_dac12_mux = 2191 SOC_DAPM_ENUM("Analog DAC1/2 Source", rt5677_dac12_enum); 2192 2193 /* DAC3 Source */ /* MX-15 [5:4] */ 2194 static const char * const rt5677_dac3_src[] = { 2195 "MONO DAC MIXL", "MONO DAC MIXR", "DD MIX1L", "DD MIX2L" 2196 }; 2197 2198 static SOC_ENUM_SINGLE_DECL( 2199 rt5677_dac3_enum, RT5677_ANA_DAC1_2_3_SRC, 2200 RT5677_ANA_DAC3_SRC_SEL_SFT, rt5677_dac3_src); 2201 2202 static const struct snd_kcontrol_new rt5677_dac3_mux = 2203 SOC_DAPM_ENUM("Analog DAC3 Source", rt5677_dac3_enum); 2204 2205 /* PDM channel Source */ /* MX-31 [13:12][9:8][5:4][1:0] */ 2206 static const char * const rt5677_pdm_src[] = { 2207 "STO1 DAC MIX", "MONO DAC MIX", "DD MIX1", "DD MIX2" 2208 }; 2209 2210 static SOC_ENUM_SINGLE_DECL( 2211 rt5677_pdm1_l_enum, RT5677_PDM_OUT_CTRL, 2212 RT5677_SEL_PDM1_L_SFT, rt5677_pdm_src); 2213 2214 static const struct snd_kcontrol_new rt5677_pdm1_l_mux = 2215 SOC_DAPM_ENUM("PDM1 Source", rt5677_pdm1_l_enum); 2216 2217 static SOC_ENUM_SINGLE_DECL( 2218 rt5677_pdm2_l_enum, RT5677_PDM_OUT_CTRL, 2219 RT5677_SEL_PDM2_L_SFT, rt5677_pdm_src); 2220 2221 static const struct snd_kcontrol_new rt5677_pdm2_l_mux = 2222 SOC_DAPM_ENUM("PDM2 Source", rt5677_pdm2_l_enum); 2223 2224 static SOC_ENUM_SINGLE_DECL( 2225 rt5677_pdm1_r_enum, RT5677_PDM_OUT_CTRL, 2226 RT5677_SEL_PDM1_R_SFT, rt5677_pdm_src); 2227 2228 static const struct snd_kcontrol_new rt5677_pdm1_r_mux = 2229 SOC_DAPM_ENUM("PDM1 Source", rt5677_pdm1_r_enum); 2230 2231 static SOC_ENUM_SINGLE_DECL( 2232 rt5677_pdm2_r_enum, RT5677_PDM_OUT_CTRL, 2233 RT5677_SEL_PDM2_R_SFT, rt5677_pdm_src); 2234 2235 static const struct snd_kcontrol_new rt5677_pdm2_r_mux = 2236 SOC_DAPM_ENUM("PDM2 Source", rt5677_pdm2_r_enum); 2237 2238 /* TDM IF1/2 SLB ADC1 Data Selection */ /* MX-3C MX-41 [5:4] MX-08 [1:0] */ 2239 static const char * const rt5677_if12_adc1_src[] = { 2240 "STO1 ADC MIX", "OB01", "VAD ADC" 2241 }; 2242 2243 static SOC_ENUM_SINGLE_DECL( 2244 rt5677_if1_adc1_enum, RT5677_TDM1_CTRL2, 2245 RT5677_IF1_ADC1_SFT, rt5677_if12_adc1_src); 2246 2247 static const struct snd_kcontrol_new rt5677_if1_adc1_mux = 2248 SOC_DAPM_ENUM("IF1 ADC1 Source", rt5677_if1_adc1_enum); 2249 2250 static SOC_ENUM_SINGLE_DECL( 2251 rt5677_if2_adc1_enum, RT5677_TDM2_CTRL2, 2252 RT5677_IF2_ADC1_SFT, rt5677_if12_adc1_src); 2253 2254 static const struct snd_kcontrol_new rt5677_if2_adc1_mux = 2255 SOC_DAPM_ENUM("IF2 ADC1 Source", rt5677_if2_adc1_enum); 2256 2257 static SOC_ENUM_SINGLE_DECL( 2258 rt5677_slb_adc1_enum, RT5677_SLIMBUS_RX, 2259 RT5677_SLB_ADC1_SFT, rt5677_if12_adc1_src); 2260 2261 static const struct snd_kcontrol_new rt5677_slb_adc1_mux = 2262 SOC_DAPM_ENUM("SLB ADC1 Source", rt5677_slb_adc1_enum); 2263 2264 /* TDM IF1/2 SLB ADC2 Data Selection */ /* MX-3C MX-41 [7:6] MX-08 [3:2] */ 2265 static const char * const rt5677_if12_adc2_src[] = { 2266 "STO2 ADC MIX", "OB23" 2267 }; 2268 2269 static SOC_ENUM_SINGLE_DECL( 2270 rt5677_if1_adc2_enum, RT5677_TDM1_CTRL2, 2271 RT5677_IF1_ADC2_SFT, rt5677_if12_adc2_src); 2272 2273 static const struct snd_kcontrol_new rt5677_if1_adc2_mux = 2274 SOC_DAPM_ENUM("IF1 ADC2 Source", rt5677_if1_adc2_enum); 2275 2276 static SOC_ENUM_SINGLE_DECL( 2277 rt5677_if2_adc2_enum, RT5677_TDM2_CTRL2, 2278 RT5677_IF2_ADC2_SFT, rt5677_if12_adc2_src); 2279 2280 static const struct snd_kcontrol_new rt5677_if2_adc2_mux = 2281 SOC_DAPM_ENUM("IF2 ADC2 Source", rt5677_if2_adc2_enum); 2282 2283 static SOC_ENUM_SINGLE_DECL( 2284 rt5677_slb_adc2_enum, RT5677_SLIMBUS_RX, 2285 RT5677_SLB_ADC2_SFT, rt5677_if12_adc2_src); 2286 2287 static const struct snd_kcontrol_new rt5677_slb_adc2_mux = 2288 SOC_DAPM_ENUM("SLB ADC2 Source", rt5677_slb_adc2_enum); 2289 2290 /* TDM IF1/2 SLB ADC3 Data Selection */ /* MX-3C MX-41 [9:8] MX-08 [5:4] */ 2291 static const char * const rt5677_if12_adc3_src[] = { 2292 "STO3 ADC MIX", "MONO ADC MIX", "OB45" 2293 }; 2294 2295 static SOC_ENUM_SINGLE_DECL( 2296 rt5677_if1_adc3_enum, RT5677_TDM1_CTRL2, 2297 RT5677_IF1_ADC3_SFT, rt5677_if12_adc3_src); 2298 2299 static const struct snd_kcontrol_new rt5677_if1_adc3_mux = 2300 SOC_DAPM_ENUM("IF1 ADC3 Source", rt5677_if1_adc3_enum); 2301 2302 static SOC_ENUM_SINGLE_DECL( 2303 rt5677_if2_adc3_enum, RT5677_TDM2_CTRL2, 2304 RT5677_IF2_ADC3_SFT, rt5677_if12_adc3_src); 2305 2306 static const struct snd_kcontrol_new rt5677_if2_adc3_mux = 2307 SOC_DAPM_ENUM("IF2 ADC3 Source", rt5677_if2_adc3_enum); 2308 2309 static SOC_ENUM_SINGLE_DECL( 2310 rt5677_slb_adc3_enum, RT5677_SLIMBUS_RX, 2311 RT5677_SLB_ADC3_SFT, rt5677_if12_adc3_src); 2312 2313 static const struct snd_kcontrol_new rt5677_slb_adc3_mux = 2314 SOC_DAPM_ENUM("SLB ADC3 Source", rt5677_slb_adc3_enum); 2315 2316 /* TDM IF1/2 SLB ADC4 Data Selection */ /* MX-3C MX-41 [11:10] MX-08 [7:6] */ 2317 static const char * const rt5677_if12_adc4_src[] = { 2318 "STO4 ADC MIX", "OB67", "OB01" 2319 }; 2320 2321 static SOC_ENUM_SINGLE_DECL( 2322 rt5677_if1_adc4_enum, RT5677_TDM1_CTRL2, 2323 RT5677_IF1_ADC4_SFT, rt5677_if12_adc4_src); 2324 2325 static const struct snd_kcontrol_new rt5677_if1_adc4_mux = 2326 SOC_DAPM_ENUM("IF1 ADC4 Source", rt5677_if1_adc4_enum); 2327 2328 static SOC_ENUM_SINGLE_DECL( 2329 rt5677_if2_adc4_enum, RT5677_TDM2_CTRL2, 2330 RT5677_IF2_ADC4_SFT, rt5677_if12_adc4_src); 2331 2332 static const struct snd_kcontrol_new rt5677_if2_adc4_mux = 2333 SOC_DAPM_ENUM("IF2 ADC4 Source", rt5677_if2_adc4_enum); 2334 2335 static SOC_ENUM_SINGLE_DECL( 2336 rt5677_slb_adc4_enum, RT5677_SLIMBUS_RX, 2337 RT5677_SLB_ADC4_SFT, rt5677_if12_adc4_src); 2338 2339 static const struct snd_kcontrol_new rt5677_slb_adc4_mux = 2340 SOC_DAPM_ENUM("SLB ADC4 Source", rt5677_slb_adc4_enum); 2341 2342 /* Interface3/4 ADC Data Input */ /* MX-2F [3:0] MX-30 [7:4] */ 2343 static const char * const rt5677_if34_adc_src[] = { 2344 "STO1 ADC MIX", "STO2 ADC MIX", "STO3 ADC MIX", "STO4 ADC MIX", 2345 "MONO ADC MIX", "OB01", "OB23", "VAD ADC" 2346 }; 2347 2348 static SOC_ENUM_SINGLE_DECL( 2349 rt5677_if3_adc_enum, RT5677_IF3_DATA, 2350 RT5677_IF3_ADC_IN_SFT, rt5677_if34_adc_src); 2351 2352 static const struct snd_kcontrol_new rt5677_if3_adc_mux = 2353 SOC_DAPM_ENUM("IF3 ADC Source", rt5677_if3_adc_enum); 2354 2355 static SOC_ENUM_SINGLE_DECL( 2356 rt5677_if4_adc_enum, RT5677_IF4_DATA, 2357 RT5677_IF4_ADC_IN_SFT, rt5677_if34_adc_src); 2358 2359 static const struct snd_kcontrol_new rt5677_if4_adc_mux = 2360 SOC_DAPM_ENUM("IF4 ADC Source", rt5677_if4_adc_enum); 2361 2362 /* TDM IF1/2 ADC Data Selection */ /* MX-3B MX-40 [7:6][5:4][3:2][1:0] */ 2363 static const char * const rt5677_if12_adc_swap_src[] = { 2364 "L/R", "R/L", "L/L", "R/R" 2365 }; 2366 2367 static SOC_ENUM_SINGLE_DECL( 2368 rt5677_if1_adc1_swap_enum, RT5677_TDM1_CTRL1, 2369 RT5677_IF1_ADC1_SWAP_SFT, rt5677_if12_adc_swap_src); 2370 2371 static const struct snd_kcontrol_new rt5677_if1_adc1_swap_mux = 2372 SOC_DAPM_ENUM("IF1 ADC1 Swap Source", rt5677_if1_adc1_swap_enum); 2373 2374 static SOC_ENUM_SINGLE_DECL( 2375 rt5677_if1_adc2_swap_enum, RT5677_TDM1_CTRL1, 2376 RT5677_IF1_ADC2_SWAP_SFT, rt5677_if12_adc_swap_src); 2377 2378 static const struct snd_kcontrol_new rt5677_if1_adc2_swap_mux = 2379 SOC_DAPM_ENUM("IF1 ADC2 Swap Source", rt5677_if1_adc2_swap_enum); 2380 2381 static SOC_ENUM_SINGLE_DECL( 2382 rt5677_if1_adc3_swap_enum, RT5677_TDM1_CTRL1, 2383 RT5677_IF1_ADC3_SWAP_SFT, rt5677_if12_adc_swap_src); 2384 2385 static const struct snd_kcontrol_new rt5677_if1_adc3_swap_mux = 2386 SOC_DAPM_ENUM("IF1 ADC3 Swap Source", rt5677_if1_adc3_swap_enum); 2387 2388 static SOC_ENUM_SINGLE_DECL( 2389 rt5677_if1_adc4_swap_enum, RT5677_TDM1_CTRL1, 2390 RT5677_IF1_ADC4_SWAP_SFT, rt5677_if12_adc_swap_src); 2391 2392 static const struct snd_kcontrol_new rt5677_if1_adc4_swap_mux = 2393 SOC_DAPM_ENUM("IF1 ADC4 Swap Source", rt5677_if1_adc4_swap_enum); 2394 2395 static SOC_ENUM_SINGLE_DECL( 2396 rt5677_if2_adc1_swap_enum, RT5677_TDM2_CTRL1, 2397 RT5677_IF1_ADC2_SWAP_SFT, rt5677_if12_adc_swap_src); 2398 2399 static const struct snd_kcontrol_new rt5677_if2_adc1_swap_mux = 2400 SOC_DAPM_ENUM("IF1 ADC2 Swap Source", rt5677_if2_adc1_swap_enum); 2401 2402 static SOC_ENUM_SINGLE_DECL( 2403 rt5677_if2_adc2_swap_enum, RT5677_TDM2_CTRL1, 2404 RT5677_IF2_ADC2_SWAP_SFT, rt5677_if12_adc_swap_src); 2405 2406 static const struct snd_kcontrol_new rt5677_if2_adc2_swap_mux = 2407 SOC_DAPM_ENUM("IF2 ADC2 Swap Source", rt5677_if2_adc2_swap_enum); 2408 2409 static SOC_ENUM_SINGLE_DECL( 2410 rt5677_if2_adc3_swap_enum, RT5677_TDM2_CTRL1, 2411 RT5677_IF2_ADC3_SWAP_SFT, rt5677_if12_adc_swap_src); 2412 2413 static const struct snd_kcontrol_new rt5677_if2_adc3_swap_mux = 2414 SOC_DAPM_ENUM("IF2 ADC3 Swap Source", rt5677_if2_adc3_swap_enum); 2415 2416 static SOC_ENUM_SINGLE_DECL( 2417 rt5677_if2_adc4_swap_enum, RT5677_TDM2_CTRL1, 2418 RT5677_IF2_ADC4_SWAP_SFT, rt5677_if12_adc_swap_src); 2419 2420 static const struct snd_kcontrol_new rt5677_if2_adc4_swap_mux = 2421 SOC_DAPM_ENUM("IF2 ADC4 Swap Source", rt5677_if2_adc4_swap_enum); 2422 2423 /* TDM IF1 ADC Data Selection */ /* MX-3C [2:0] */ 2424 static const char * const rt5677_if1_adc_tdm_swap_src[] = { 2425 "1/2/3/4", "2/1/3/4", "2/3/1/4", "4/1/2/3", "1/3/2/4", "1/4/2/3", 2426 "3/1/2/4", "3/4/1/2" 2427 }; 2428 2429 static SOC_ENUM_SINGLE_DECL( 2430 rt5677_if1_adc_tdm_swap_enum, RT5677_TDM1_CTRL2, 2431 RT5677_IF1_ADC_CTRL_SFT, rt5677_if1_adc_tdm_swap_src); 2432 2433 static const struct snd_kcontrol_new rt5677_if1_adc_tdm_swap_mux = 2434 SOC_DAPM_ENUM("IF1 ADC TDM Swap Source", rt5677_if1_adc_tdm_swap_enum); 2435 2436 /* TDM IF2 ADC Data Selection */ /* MX-41[2:0] */ 2437 static const char * const rt5677_if2_adc_tdm_swap_src[] = { 2438 "1/2/3/4", "2/1/3/4", "3/1/2/4", "4/1/2/3", "1/3/2/4", "1/4/2/3", 2439 "2/3/1/4", "3/4/1/2" 2440 }; 2441 2442 static SOC_ENUM_SINGLE_DECL( 2443 rt5677_if2_adc_tdm_swap_enum, RT5677_TDM2_CTRL2, 2444 RT5677_IF2_ADC_CTRL_SFT, rt5677_if2_adc_tdm_swap_src); 2445 2446 static const struct snd_kcontrol_new rt5677_if2_adc_tdm_swap_mux = 2447 SOC_DAPM_ENUM("IF2 ADC TDM Swap Source", rt5677_if2_adc_tdm_swap_enum); 2448 2449 /* TDM IF1/2 DAC Data Selection */ /* MX-3E[14:12][10:8][6:4][2:0] 2450 MX-3F[14:12][10:8][6:4][2:0] 2451 MX-43[14:12][10:8][6:4][2:0] 2452 MX-44[14:12][10:8][6:4][2:0] */ 2453 static const char * const rt5677_if12_dac_tdm_sel_src[] = { 2454 "Slot0", "Slot1", "Slot2", "Slot3", "Slot4", "Slot5", "Slot6", "Slot7" 2455 }; 2456 2457 static SOC_ENUM_SINGLE_DECL( 2458 rt5677_if1_dac0_tdm_sel_enum, RT5677_TDM1_CTRL4, 2459 RT5677_IF1_DAC0_SFT, rt5677_if12_dac_tdm_sel_src); 2460 2461 static const struct snd_kcontrol_new rt5677_if1_dac0_tdm_sel_mux = 2462 SOC_DAPM_ENUM("IF1 DAC0 TDM Source", rt5677_if1_dac0_tdm_sel_enum); 2463 2464 static SOC_ENUM_SINGLE_DECL( 2465 rt5677_if1_dac1_tdm_sel_enum, RT5677_TDM1_CTRL4, 2466 RT5677_IF1_DAC1_SFT, rt5677_if12_dac_tdm_sel_src); 2467 2468 static const struct snd_kcontrol_new rt5677_if1_dac1_tdm_sel_mux = 2469 SOC_DAPM_ENUM("IF1 DAC1 TDM Source", rt5677_if1_dac1_tdm_sel_enum); 2470 2471 static SOC_ENUM_SINGLE_DECL( 2472 rt5677_if1_dac2_tdm_sel_enum, RT5677_TDM1_CTRL4, 2473 RT5677_IF1_DAC2_SFT, rt5677_if12_dac_tdm_sel_src); 2474 2475 static const struct snd_kcontrol_new rt5677_if1_dac2_tdm_sel_mux = 2476 SOC_DAPM_ENUM("IF1 DAC2 TDM Source", rt5677_if1_dac2_tdm_sel_enum); 2477 2478 static SOC_ENUM_SINGLE_DECL( 2479 rt5677_if1_dac3_tdm_sel_enum, RT5677_TDM1_CTRL4, 2480 RT5677_IF1_DAC3_SFT, rt5677_if12_dac_tdm_sel_src); 2481 2482 static const struct snd_kcontrol_new rt5677_if1_dac3_tdm_sel_mux = 2483 SOC_DAPM_ENUM("IF1 DAC3 TDM Source", rt5677_if1_dac3_tdm_sel_enum); 2484 2485 static SOC_ENUM_SINGLE_DECL( 2486 rt5677_if1_dac4_tdm_sel_enum, RT5677_TDM1_CTRL5, 2487 RT5677_IF1_DAC4_SFT, rt5677_if12_dac_tdm_sel_src); 2488 2489 static const struct snd_kcontrol_new rt5677_if1_dac4_tdm_sel_mux = 2490 SOC_DAPM_ENUM("IF1 DAC4 TDM Source", rt5677_if1_dac4_tdm_sel_enum); 2491 2492 static SOC_ENUM_SINGLE_DECL( 2493 rt5677_if1_dac5_tdm_sel_enum, RT5677_TDM1_CTRL5, 2494 RT5677_IF1_DAC5_SFT, rt5677_if12_dac_tdm_sel_src); 2495 2496 static const struct snd_kcontrol_new rt5677_if1_dac5_tdm_sel_mux = 2497 SOC_DAPM_ENUM("IF1 DAC5 TDM Source", rt5677_if1_dac5_tdm_sel_enum); 2498 2499 static SOC_ENUM_SINGLE_DECL( 2500 rt5677_if1_dac6_tdm_sel_enum, RT5677_TDM1_CTRL5, 2501 RT5677_IF1_DAC6_SFT, rt5677_if12_dac_tdm_sel_src); 2502 2503 static const struct snd_kcontrol_new rt5677_if1_dac6_tdm_sel_mux = 2504 SOC_DAPM_ENUM("IF1 DAC6 TDM Source", rt5677_if1_dac6_tdm_sel_enum); 2505 2506 static SOC_ENUM_SINGLE_DECL( 2507 rt5677_if1_dac7_tdm_sel_enum, RT5677_TDM1_CTRL5, 2508 RT5677_IF1_DAC7_SFT, rt5677_if12_dac_tdm_sel_src); 2509 2510 static const struct snd_kcontrol_new rt5677_if1_dac7_tdm_sel_mux = 2511 SOC_DAPM_ENUM("IF1 DAC7 TDM Source", rt5677_if1_dac7_tdm_sel_enum); 2512 2513 static SOC_ENUM_SINGLE_DECL( 2514 rt5677_if2_dac0_tdm_sel_enum, RT5677_TDM2_CTRL4, 2515 RT5677_IF2_DAC0_SFT, rt5677_if12_dac_tdm_sel_src); 2516 2517 static const struct snd_kcontrol_new rt5677_if2_dac0_tdm_sel_mux = 2518 SOC_DAPM_ENUM("IF2 DAC0 TDM Source", rt5677_if2_dac0_tdm_sel_enum); 2519 2520 static SOC_ENUM_SINGLE_DECL( 2521 rt5677_if2_dac1_tdm_sel_enum, RT5677_TDM2_CTRL4, 2522 RT5677_IF2_DAC1_SFT, rt5677_if12_dac_tdm_sel_src); 2523 2524 static const struct snd_kcontrol_new rt5677_if2_dac1_tdm_sel_mux = 2525 SOC_DAPM_ENUM("IF2 DAC1 TDM Source", rt5677_if2_dac1_tdm_sel_enum); 2526 2527 static SOC_ENUM_SINGLE_DECL( 2528 rt5677_if2_dac2_tdm_sel_enum, RT5677_TDM2_CTRL4, 2529 RT5677_IF2_DAC2_SFT, rt5677_if12_dac_tdm_sel_src); 2530 2531 static const struct snd_kcontrol_new rt5677_if2_dac2_tdm_sel_mux = 2532 SOC_DAPM_ENUM("IF2 DAC2 TDM Source", rt5677_if2_dac2_tdm_sel_enum); 2533 2534 static SOC_ENUM_SINGLE_DECL( 2535 rt5677_if2_dac3_tdm_sel_enum, RT5677_TDM2_CTRL4, 2536 RT5677_IF2_DAC3_SFT, rt5677_if12_dac_tdm_sel_src); 2537 2538 static const struct snd_kcontrol_new rt5677_if2_dac3_tdm_sel_mux = 2539 SOC_DAPM_ENUM("IF2 DAC3 TDM Source", rt5677_if2_dac3_tdm_sel_enum); 2540 2541 static SOC_ENUM_SINGLE_DECL( 2542 rt5677_if2_dac4_tdm_sel_enum, RT5677_TDM2_CTRL5, 2543 RT5677_IF2_DAC4_SFT, rt5677_if12_dac_tdm_sel_src); 2544 2545 static const struct snd_kcontrol_new rt5677_if2_dac4_tdm_sel_mux = 2546 SOC_DAPM_ENUM("IF2 DAC4 TDM Source", rt5677_if2_dac4_tdm_sel_enum); 2547 2548 static SOC_ENUM_SINGLE_DECL( 2549 rt5677_if2_dac5_tdm_sel_enum, RT5677_TDM2_CTRL5, 2550 RT5677_IF2_DAC5_SFT, rt5677_if12_dac_tdm_sel_src); 2551 2552 static const struct snd_kcontrol_new rt5677_if2_dac5_tdm_sel_mux = 2553 SOC_DAPM_ENUM("IF2 DAC5 TDM Source", rt5677_if2_dac5_tdm_sel_enum); 2554 2555 static SOC_ENUM_SINGLE_DECL( 2556 rt5677_if2_dac6_tdm_sel_enum, RT5677_TDM2_CTRL5, 2557 RT5677_IF2_DAC6_SFT, rt5677_if12_dac_tdm_sel_src); 2558 2559 static const struct snd_kcontrol_new rt5677_if2_dac6_tdm_sel_mux = 2560 SOC_DAPM_ENUM("IF2 DAC6 TDM Source", rt5677_if2_dac6_tdm_sel_enum); 2561 2562 static SOC_ENUM_SINGLE_DECL( 2563 rt5677_if2_dac7_tdm_sel_enum, RT5677_TDM2_CTRL5, 2564 RT5677_IF2_DAC7_SFT, rt5677_if12_dac_tdm_sel_src); 2565 2566 static const struct snd_kcontrol_new rt5677_if2_dac7_tdm_sel_mux = 2567 SOC_DAPM_ENUM("IF2 DAC7 TDM Source", rt5677_if2_dac7_tdm_sel_enum); 2568 2569 static int rt5677_bst1_event(struct snd_soc_dapm_widget *w, 2570 struct snd_kcontrol *kcontrol, int event) 2571 { 2572 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 2573 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component); 2574 2575 switch (event) { 2576 case SND_SOC_DAPM_POST_PMU: 2577 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2, 2578 RT5677_PWR_BST1_P, RT5677_PWR_BST1_P); 2579 break; 2580 2581 case SND_SOC_DAPM_PRE_PMD: 2582 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2, 2583 RT5677_PWR_BST1_P, 0); 2584 break; 2585 2586 default: 2587 return 0; 2588 } 2589 2590 return 0; 2591 } 2592 2593 static int rt5677_bst2_event(struct snd_soc_dapm_widget *w, 2594 struct snd_kcontrol *kcontrol, int event) 2595 { 2596 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 2597 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component); 2598 2599 switch (event) { 2600 case SND_SOC_DAPM_POST_PMU: 2601 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2, 2602 RT5677_PWR_BST2_P, RT5677_PWR_BST2_P); 2603 break; 2604 2605 case SND_SOC_DAPM_PRE_PMD: 2606 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2, 2607 RT5677_PWR_BST2_P, 0); 2608 break; 2609 2610 default: 2611 return 0; 2612 } 2613 2614 return 0; 2615 } 2616 2617 static int rt5677_set_pll1_event(struct snd_soc_dapm_widget *w, 2618 struct snd_kcontrol *kcontrol, int event) 2619 { 2620 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 2621 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component); 2622 2623 switch (event) { 2624 case SND_SOC_DAPM_PRE_PMU: 2625 regmap_update_bits(rt5677->regmap, RT5677_PLL1_CTRL2, 0x2, 0x2); 2626 break; 2627 2628 case SND_SOC_DAPM_POST_PMU: 2629 regmap_update_bits(rt5677->regmap, RT5677_PLL1_CTRL2, 0x2, 0x0); 2630 break; 2631 2632 default: 2633 return 0; 2634 } 2635 2636 return 0; 2637 } 2638 2639 static int rt5677_set_pll2_event(struct snd_soc_dapm_widget *w, 2640 struct snd_kcontrol *kcontrol, int event) 2641 { 2642 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 2643 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component); 2644 2645 switch (event) { 2646 case SND_SOC_DAPM_PRE_PMU: 2647 regmap_update_bits(rt5677->regmap, RT5677_PLL2_CTRL2, 0x2, 0x2); 2648 break; 2649 2650 case SND_SOC_DAPM_POST_PMU: 2651 regmap_update_bits(rt5677->regmap, RT5677_PLL2_CTRL2, 0x2, 0x0); 2652 break; 2653 2654 default: 2655 return 0; 2656 } 2657 2658 return 0; 2659 } 2660 2661 static int rt5677_set_micbias1_event(struct snd_soc_dapm_widget *w, 2662 struct snd_kcontrol *kcontrol, int event) 2663 { 2664 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 2665 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component); 2666 2667 switch (event) { 2668 case SND_SOC_DAPM_POST_PMU: 2669 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2, 2670 RT5677_PWR_CLK_MB1 | RT5677_PWR_PP_MB1 | 2671 RT5677_PWR_CLK_MB, RT5677_PWR_CLK_MB1 | 2672 RT5677_PWR_PP_MB1 | RT5677_PWR_CLK_MB); 2673 break; 2674 2675 case SND_SOC_DAPM_PRE_PMD: 2676 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2, 2677 RT5677_PWR_CLK_MB1 | RT5677_PWR_PP_MB1 | 2678 RT5677_PWR_CLK_MB, 0); 2679 break; 2680 2681 default: 2682 return 0; 2683 } 2684 2685 return 0; 2686 } 2687 2688 static int rt5677_if1_adc_tdm_event(struct snd_soc_dapm_widget *w, 2689 struct snd_kcontrol *kcontrol, int event) 2690 { 2691 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 2692 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component); 2693 unsigned int value; 2694 2695 switch (event) { 2696 case SND_SOC_DAPM_PRE_PMU: 2697 regmap_read(rt5677->regmap, RT5677_TDM1_CTRL2, &value); 2698 if (value & RT5677_IF1_ADC_CTRL_MASK) 2699 regmap_update_bits(rt5677->regmap, RT5677_TDM1_CTRL1, 2700 RT5677_IF1_ADC_MODE_MASK, 2701 RT5677_IF1_ADC_MODE_TDM); 2702 break; 2703 2704 default: 2705 return 0; 2706 } 2707 2708 return 0; 2709 } 2710 2711 static int rt5677_if2_adc_tdm_event(struct snd_soc_dapm_widget *w, 2712 struct snd_kcontrol *kcontrol, int event) 2713 { 2714 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 2715 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component); 2716 unsigned int value; 2717 2718 switch (event) { 2719 case SND_SOC_DAPM_PRE_PMU: 2720 regmap_read(rt5677->regmap, RT5677_TDM2_CTRL2, &value); 2721 if (value & RT5677_IF2_ADC_CTRL_MASK) 2722 regmap_update_bits(rt5677->regmap, RT5677_TDM2_CTRL1, 2723 RT5677_IF2_ADC_MODE_MASK, 2724 RT5677_IF2_ADC_MODE_TDM); 2725 break; 2726 2727 default: 2728 return 0; 2729 } 2730 2731 return 0; 2732 } 2733 2734 static int rt5677_vref_event(struct snd_soc_dapm_widget *w, 2735 struct snd_kcontrol *kcontrol, int event) 2736 { 2737 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 2738 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component); 2739 2740 switch (event) { 2741 case SND_SOC_DAPM_POST_PMU: 2742 if (snd_soc_component_get_bias_level(component) != SND_SOC_BIAS_ON && 2743 !rt5677->is_vref_slow) { 2744 mdelay(20); 2745 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1, 2746 RT5677_PWR_FV1 | RT5677_PWR_FV2, 2747 RT5677_PWR_FV1 | RT5677_PWR_FV2); 2748 rt5677->is_vref_slow = true; 2749 } 2750 break; 2751 2752 default: 2753 return 0; 2754 } 2755 2756 return 0; 2757 } 2758 2759 static int rt5677_filter_power_event(struct snd_soc_dapm_widget *w, 2760 struct snd_kcontrol *kcontrol, int event) 2761 { 2762 switch (event) { 2763 case SND_SOC_DAPM_POST_PMU: 2764 msleep(50); 2765 break; 2766 2767 default: 2768 return 0; 2769 } 2770 2771 return 0; 2772 } 2773 2774 static const struct snd_soc_dapm_widget rt5677_dapm_widgets[] = { 2775 SND_SOC_DAPM_SUPPLY("PLL1", RT5677_PWR_ANLG2, RT5677_PWR_PLL1_BIT, 2776 0, rt5677_set_pll1_event, SND_SOC_DAPM_PRE_PMU | 2777 SND_SOC_DAPM_POST_PMU), 2778 SND_SOC_DAPM_SUPPLY("PLL2", RT5677_PWR_ANLG2, RT5677_PWR_PLL2_BIT, 2779 0, rt5677_set_pll2_event, SND_SOC_DAPM_PRE_PMU | 2780 SND_SOC_DAPM_POST_PMU), 2781 2782 /* ASRC */ 2783 SND_SOC_DAPM_SUPPLY_S("I2S1 ASRC", 1, RT5677_ASRC_1, 0, 0, NULL, 0), 2784 SND_SOC_DAPM_SUPPLY_S("I2S2 ASRC", 1, RT5677_ASRC_1, 1, 0, NULL, 0), 2785 SND_SOC_DAPM_SUPPLY_S("I2S3 ASRC", 1, RT5677_ASRC_1, 2, 0, NULL, 0), 2786 SND_SOC_DAPM_SUPPLY_S("I2S4 ASRC", 1, RT5677_ASRC_1, 3, 0, NULL, 0), 2787 SND_SOC_DAPM_SUPPLY_S("DAC STO ASRC", 1, RT5677_ASRC_2, 14, 0, 2788 rt5677_filter_power_event, SND_SOC_DAPM_POST_PMU), 2789 SND_SOC_DAPM_SUPPLY_S("DAC MONO2 L ASRC", 1, RT5677_ASRC_2, 13, 0, NULL, 2790 0), 2791 SND_SOC_DAPM_SUPPLY_S("DAC MONO2 R ASRC", 1, RT5677_ASRC_2, 12, 0, NULL, 2792 0), 2793 SND_SOC_DAPM_SUPPLY_S("DAC MONO3 L ASRC", 1, RT5677_ASRC_1, 15, 0, NULL, 2794 0), 2795 SND_SOC_DAPM_SUPPLY_S("DAC MONO3 R ASRC", 1, RT5677_ASRC_1, 14, 0, NULL, 2796 0), 2797 SND_SOC_DAPM_SUPPLY_S("DAC MONO4 L ASRC", 1, RT5677_ASRC_1, 13, 0, NULL, 2798 0), 2799 SND_SOC_DAPM_SUPPLY_S("DAC MONO4 R ASRC", 1, RT5677_ASRC_1, 12, 0, NULL, 2800 0), 2801 SND_SOC_DAPM_SUPPLY_S("DMIC STO1 ASRC", 1, RT5677_ASRC_2, 11, 0, NULL, 2802 0), 2803 SND_SOC_DAPM_SUPPLY_S("DMIC STO2 ASRC", 1, RT5677_ASRC_2, 10, 0, NULL, 2804 0), 2805 SND_SOC_DAPM_SUPPLY_S("DMIC STO3 ASRC", 1, RT5677_ASRC_2, 9, 0, NULL, 2806 0), 2807 SND_SOC_DAPM_SUPPLY_S("DMIC STO4 ASRC", 1, RT5677_ASRC_2, 8, 0, NULL, 2808 0), 2809 SND_SOC_DAPM_SUPPLY_S("DMIC MONO L ASRC", 1, RT5677_ASRC_2, 7, 0, NULL, 2810 0), 2811 SND_SOC_DAPM_SUPPLY_S("DMIC MONO R ASRC", 1, RT5677_ASRC_2, 6, 0, NULL, 2812 0), 2813 SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5677_ASRC_2, 5, 0, NULL, 0), 2814 SND_SOC_DAPM_SUPPLY_S("ADC STO2 ASRC", 1, RT5677_ASRC_2, 4, 0, NULL, 0), 2815 SND_SOC_DAPM_SUPPLY_S("ADC STO3 ASRC", 1, RT5677_ASRC_2, 3, 0, NULL, 0), 2816 SND_SOC_DAPM_SUPPLY_S("ADC STO4 ASRC", 1, RT5677_ASRC_2, 2, 0, NULL, 0), 2817 SND_SOC_DAPM_SUPPLY_S("ADC MONO L ASRC", 1, RT5677_ASRC_2, 1, 0, NULL, 2818 0), 2819 SND_SOC_DAPM_SUPPLY_S("ADC MONO R ASRC", 1, RT5677_ASRC_2, 0, 0, NULL, 2820 0), 2821 2822 /* Input Side */ 2823 /* micbias */ 2824 SND_SOC_DAPM_SUPPLY("MICBIAS1", RT5677_PWR_ANLG2, RT5677_PWR_MB1_BIT, 2825 0, rt5677_set_micbias1_event, SND_SOC_DAPM_PRE_PMD | 2826 SND_SOC_DAPM_POST_PMU), 2827 2828 /* Input Lines */ 2829 SND_SOC_DAPM_INPUT("DMIC L1"), 2830 SND_SOC_DAPM_INPUT("DMIC R1"), 2831 SND_SOC_DAPM_INPUT("DMIC L2"), 2832 SND_SOC_DAPM_INPUT("DMIC R2"), 2833 SND_SOC_DAPM_INPUT("DMIC L3"), 2834 SND_SOC_DAPM_INPUT("DMIC R3"), 2835 SND_SOC_DAPM_INPUT("DMIC L4"), 2836 SND_SOC_DAPM_INPUT("DMIC R4"), 2837 2838 SND_SOC_DAPM_INPUT("IN1P"), 2839 SND_SOC_DAPM_INPUT("IN1N"), 2840 SND_SOC_DAPM_INPUT("IN2P"), 2841 SND_SOC_DAPM_INPUT("IN2N"), 2842 2843 SND_SOC_DAPM_INPUT("Haptic Generator"), 2844 2845 SND_SOC_DAPM_PGA("DMIC1", SND_SOC_NOPM, 0, 0, NULL, 0), 2846 SND_SOC_DAPM_PGA("DMIC2", SND_SOC_NOPM, 0, 0, NULL, 0), 2847 SND_SOC_DAPM_PGA("DMIC3", SND_SOC_NOPM, 0, 0, NULL, 0), 2848 SND_SOC_DAPM_PGA("DMIC4", SND_SOC_NOPM, 0, 0, NULL, 0), 2849 2850 SND_SOC_DAPM_SUPPLY("DMIC1 power", RT5677_DMIC_CTRL1, 2851 RT5677_DMIC_1_EN_SFT, 0, NULL, 0), 2852 SND_SOC_DAPM_SUPPLY("DMIC2 power", RT5677_DMIC_CTRL1, 2853 RT5677_DMIC_2_EN_SFT, 0, NULL, 0), 2854 SND_SOC_DAPM_SUPPLY("DMIC3 power", RT5677_DMIC_CTRL1, 2855 RT5677_DMIC_3_EN_SFT, 0, NULL, 0), 2856 SND_SOC_DAPM_SUPPLY("DMIC4 power", RT5677_DMIC_CTRL2, 2857 RT5677_DMIC_4_EN_SFT, 0, NULL, 0), 2858 2859 SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0, 2860 set_dmic_clk, SND_SOC_DAPM_PRE_PMU), 2861 2862 /* Boost */ 2863 SND_SOC_DAPM_PGA_E("BST1", RT5677_PWR_ANLG2, 2864 RT5677_PWR_BST1_BIT, 0, NULL, 0, rt5677_bst1_event, 2865 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU), 2866 SND_SOC_DAPM_PGA_E("BST2", RT5677_PWR_ANLG2, 2867 RT5677_PWR_BST2_BIT, 0, NULL, 0, rt5677_bst2_event, 2868 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU), 2869 2870 /* ADCs */ 2871 SND_SOC_DAPM_ADC("ADC 1", NULL, SND_SOC_NOPM, 2872 0, 0), 2873 SND_SOC_DAPM_ADC("ADC 2", NULL, SND_SOC_NOPM, 2874 0, 0), 2875 SND_SOC_DAPM_PGA("ADC 1_2", SND_SOC_NOPM, 0, 0, NULL, 0), 2876 2877 SND_SOC_DAPM_SUPPLY("ADC 1 power", RT5677_PWR_DIG1, 2878 RT5677_PWR_ADC_L_BIT, 0, NULL, 0), 2879 SND_SOC_DAPM_SUPPLY("ADC 2 power", RT5677_PWR_DIG1, 2880 RT5677_PWR_ADC_R_BIT, 0, NULL, 0), 2881 SND_SOC_DAPM_SUPPLY("ADC1 clock", RT5677_PWR_DIG1, 2882 RT5677_PWR_ADCFED1_BIT, 0, NULL, 0), 2883 SND_SOC_DAPM_SUPPLY("ADC2 clock", RT5677_PWR_DIG1, 2884 RT5677_PWR_ADCFED2_BIT, 0, NULL, 0), 2885 2886 /* ADC Mux */ 2887 SND_SOC_DAPM_MUX("Stereo1 DMIC Mux", SND_SOC_NOPM, 0, 0, 2888 &rt5677_sto1_dmic_mux), 2889 SND_SOC_DAPM_MUX("Stereo1 ADC1 Mux", SND_SOC_NOPM, 0, 0, 2890 &rt5677_sto1_adc1_mux), 2891 SND_SOC_DAPM_MUX("Stereo1 ADC2 Mux", SND_SOC_NOPM, 0, 0, 2892 &rt5677_sto1_adc2_mux), 2893 SND_SOC_DAPM_MUX("Stereo2 DMIC Mux", SND_SOC_NOPM, 0, 0, 2894 &rt5677_sto2_dmic_mux), 2895 SND_SOC_DAPM_MUX("Stereo2 ADC1 Mux", SND_SOC_NOPM, 0, 0, 2896 &rt5677_sto2_adc1_mux), 2897 SND_SOC_DAPM_MUX("Stereo2 ADC2 Mux", SND_SOC_NOPM, 0, 0, 2898 &rt5677_sto2_adc2_mux), 2899 SND_SOC_DAPM_MUX("Stereo2 ADC LR Mux", SND_SOC_NOPM, 0, 0, 2900 &rt5677_sto2_adc_lr_mux), 2901 SND_SOC_DAPM_MUX("Stereo3 DMIC Mux", SND_SOC_NOPM, 0, 0, 2902 &rt5677_sto3_dmic_mux), 2903 SND_SOC_DAPM_MUX("Stereo3 ADC1 Mux", SND_SOC_NOPM, 0, 0, 2904 &rt5677_sto3_adc1_mux), 2905 SND_SOC_DAPM_MUX("Stereo3 ADC2 Mux", SND_SOC_NOPM, 0, 0, 2906 &rt5677_sto3_adc2_mux), 2907 SND_SOC_DAPM_MUX("Stereo4 DMIC Mux", SND_SOC_NOPM, 0, 0, 2908 &rt5677_sto4_dmic_mux), 2909 SND_SOC_DAPM_MUX("Stereo4 ADC1 Mux", SND_SOC_NOPM, 0, 0, 2910 &rt5677_sto4_adc1_mux), 2911 SND_SOC_DAPM_MUX("Stereo4 ADC2 Mux", SND_SOC_NOPM, 0, 0, 2912 &rt5677_sto4_adc2_mux), 2913 SND_SOC_DAPM_MUX("Mono DMIC L Mux", SND_SOC_NOPM, 0, 0, 2914 &rt5677_mono_dmic_l_mux), 2915 SND_SOC_DAPM_MUX("Mono DMIC R Mux", SND_SOC_NOPM, 0, 0, 2916 &rt5677_mono_dmic_r_mux), 2917 SND_SOC_DAPM_MUX("Mono ADC2 L Mux", SND_SOC_NOPM, 0, 0, 2918 &rt5677_mono_adc2_l_mux), 2919 SND_SOC_DAPM_MUX("Mono ADC1 L Mux", SND_SOC_NOPM, 0, 0, 2920 &rt5677_mono_adc1_l_mux), 2921 SND_SOC_DAPM_MUX("Mono ADC1 R Mux", SND_SOC_NOPM, 0, 0, 2922 &rt5677_mono_adc1_r_mux), 2923 SND_SOC_DAPM_MUX("Mono ADC2 R Mux", SND_SOC_NOPM, 0, 0, 2924 &rt5677_mono_adc2_r_mux), 2925 2926 /* ADC Mixer */ 2927 SND_SOC_DAPM_SUPPLY("adc stereo1 filter", RT5677_PWR_DIG2, 2928 RT5677_PWR_ADC_S1F_BIT, 0, NULL, 0), 2929 SND_SOC_DAPM_SUPPLY("adc stereo2 filter", RT5677_PWR_DIG2, 2930 RT5677_PWR_ADC_S2F_BIT, 0, NULL, 0), 2931 SND_SOC_DAPM_SUPPLY("adc stereo3 filter", RT5677_PWR_DIG2, 2932 RT5677_PWR_ADC_S3F_BIT, 0, NULL, 0), 2933 SND_SOC_DAPM_SUPPLY("adc stereo4 filter", RT5677_PWR_DIG2, 2934 RT5677_PWR_ADC_S4F_BIT, 0, NULL, 0), 2935 SND_SOC_DAPM_MIXER("Sto1 ADC MIXL", SND_SOC_NOPM, 0, 0, 2936 rt5677_sto1_adc_l_mix, ARRAY_SIZE(rt5677_sto1_adc_l_mix)), 2937 SND_SOC_DAPM_MIXER("Sto1 ADC MIXR", SND_SOC_NOPM, 0, 0, 2938 rt5677_sto1_adc_r_mix, ARRAY_SIZE(rt5677_sto1_adc_r_mix)), 2939 SND_SOC_DAPM_MIXER("Sto2 ADC MIXL", SND_SOC_NOPM, 0, 0, 2940 rt5677_sto2_adc_l_mix, ARRAY_SIZE(rt5677_sto2_adc_l_mix)), 2941 SND_SOC_DAPM_MIXER("Sto2 ADC MIXR", SND_SOC_NOPM, 0, 0, 2942 rt5677_sto2_adc_r_mix, ARRAY_SIZE(rt5677_sto2_adc_r_mix)), 2943 SND_SOC_DAPM_MIXER("Sto3 ADC MIXL", SND_SOC_NOPM, 0, 0, 2944 rt5677_sto3_adc_l_mix, ARRAY_SIZE(rt5677_sto3_adc_l_mix)), 2945 SND_SOC_DAPM_MIXER("Sto3 ADC MIXR", SND_SOC_NOPM, 0, 0, 2946 rt5677_sto3_adc_r_mix, ARRAY_SIZE(rt5677_sto3_adc_r_mix)), 2947 SND_SOC_DAPM_MIXER("Sto4 ADC MIXL", SND_SOC_NOPM, 0, 0, 2948 rt5677_sto4_adc_l_mix, ARRAY_SIZE(rt5677_sto4_adc_l_mix)), 2949 SND_SOC_DAPM_MIXER("Sto4 ADC MIXR", SND_SOC_NOPM, 0, 0, 2950 rt5677_sto4_adc_r_mix, ARRAY_SIZE(rt5677_sto4_adc_r_mix)), 2951 SND_SOC_DAPM_SUPPLY("adc mono left filter", RT5677_PWR_DIG2, 2952 RT5677_PWR_ADC_MF_L_BIT, 0, NULL, 0), 2953 SND_SOC_DAPM_MIXER("Mono ADC MIXL", SND_SOC_NOPM, 0, 0, 2954 rt5677_mono_adc_l_mix, ARRAY_SIZE(rt5677_mono_adc_l_mix)), 2955 SND_SOC_DAPM_SUPPLY("adc mono right filter", RT5677_PWR_DIG2, 2956 RT5677_PWR_ADC_MF_R_BIT, 0, NULL, 0), 2957 SND_SOC_DAPM_MIXER("Mono ADC MIXR", SND_SOC_NOPM, 0, 0, 2958 rt5677_mono_adc_r_mix, ARRAY_SIZE(rt5677_mono_adc_r_mix)), 2959 2960 /* ADC PGA */ 2961 SND_SOC_DAPM_PGA("Stereo1 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0), 2962 SND_SOC_DAPM_PGA("Stereo1 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0), 2963 SND_SOC_DAPM_PGA("Stereo1 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 2964 SND_SOC_DAPM_PGA("Stereo2 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0), 2965 SND_SOC_DAPM_PGA("Stereo2 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0), 2966 SND_SOC_DAPM_PGA("Stereo2 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 2967 SND_SOC_DAPM_PGA("Stereo3 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0), 2968 SND_SOC_DAPM_PGA("Stereo3 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0), 2969 SND_SOC_DAPM_PGA("Stereo3 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 2970 SND_SOC_DAPM_PGA("Stereo4 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0), 2971 SND_SOC_DAPM_PGA("Stereo4 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0), 2972 SND_SOC_DAPM_PGA("Stereo4 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 2973 SND_SOC_DAPM_PGA("Sto2 ADC LR MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 2974 SND_SOC_DAPM_PGA("Mono ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 2975 SND_SOC_DAPM_PGA("IF1 ADC", SND_SOC_NOPM, 0, 0, NULL, 0), 2976 SND_SOC_DAPM_PGA("IF2 ADC", SND_SOC_NOPM, 0, 0, NULL, 0), 2977 2978 /* DSP */ 2979 SND_SOC_DAPM_MUX("IB9 Mux", SND_SOC_NOPM, 0, 0, 2980 &rt5677_ib9_src_mux), 2981 SND_SOC_DAPM_MUX("IB8 Mux", SND_SOC_NOPM, 0, 0, 2982 &rt5677_ib8_src_mux), 2983 SND_SOC_DAPM_MUX("IB7 Mux", SND_SOC_NOPM, 0, 0, 2984 &rt5677_ib7_src_mux), 2985 SND_SOC_DAPM_MUX("IB6 Mux", SND_SOC_NOPM, 0, 0, 2986 &rt5677_ib6_src_mux), 2987 SND_SOC_DAPM_MUX("IB45 Mux", SND_SOC_NOPM, 0, 0, 2988 &rt5677_ib45_src_mux), 2989 SND_SOC_DAPM_MUX("IB23 Mux", SND_SOC_NOPM, 0, 0, 2990 &rt5677_ib23_src_mux), 2991 SND_SOC_DAPM_MUX("IB01 Mux", SND_SOC_NOPM, 0, 0, 2992 &rt5677_ib01_src_mux), 2993 SND_SOC_DAPM_MUX("IB45 Bypass Mux", SND_SOC_NOPM, 0, 0, 2994 &rt5677_ib45_bypass_src_mux), 2995 SND_SOC_DAPM_MUX("IB23 Bypass Mux", SND_SOC_NOPM, 0, 0, 2996 &rt5677_ib23_bypass_src_mux), 2997 SND_SOC_DAPM_MUX("IB01 Bypass Mux", SND_SOC_NOPM, 0, 0, 2998 &rt5677_ib01_bypass_src_mux), 2999 SND_SOC_DAPM_MUX("OB23 Bypass Mux", SND_SOC_NOPM, 0, 0, 3000 &rt5677_ob23_bypass_src_mux), 3001 SND_SOC_DAPM_MUX("OB01 Bypass Mux", SND_SOC_NOPM, 0, 0, 3002 &rt5677_ob01_bypass_src_mux), 3003 3004 SND_SOC_DAPM_PGA("OB45", SND_SOC_NOPM, 0, 0, NULL, 0), 3005 SND_SOC_DAPM_PGA("OB67", SND_SOC_NOPM, 0, 0, NULL, 0), 3006 3007 SND_SOC_DAPM_PGA("OutBound2", SND_SOC_NOPM, 0, 0, NULL, 0), 3008 SND_SOC_DAPM_PGA("OutBound3", SND_SOC_NOPM, 0, 0, NULL, 0), 3009 SND_SOC_DAPM_PGA("OutBound4", SND_SOC_NOPM, 0, 0, NULL, 0), 3010 SND_SOC_DAPM_PGA("OutBound5", SND_SOC_NOPM, 0, 0, NULL, 0), 3011 SND_SOC_DAPM_PGA("OutBound6", SND_SOC_NOPM, 0, 0, NULL, 0), 3012 SND_SOC_DAPM_PGA("OutBound7", SND_SOC_NOPM, 0, 0, NULL, 0), 3013 3014 /* Digital Interface */ 3015 SND_SOC_DAPM_SUPPLY("I2S1", RT5677_PWR_DIG1, 3016 RT5677_PWR_I2S1_BIT, 0, NULL, 0), 3017 SND_SOC_DAPM_PGA("IF1 DAC0", SND_SOC_NOPM, 0, 0, NULL, 0), 3018 SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0), 3019 SND_SOC_DAPM_PGA("IF1 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0), 3020 SND_SOC_DAPM_PGA("IF1 DAC3", SND_SOC_NOPM, 0, 0, NULL, 0), 3021 SND_SOC_DAPM_PGA("IF1 DAC4", SND_SOC_NOPM, 0, 0, NULL, 0), 3022 SND_SOC_DAPM_PGA("IF1 DAC5", SND_SOC_NOPM, 0, 0, NULL, 0), 3023 SND_SOC_DAPM_PGA("IF1 DAC6", SND_SOC_NOPM, 0, 0, NULL, 0), 3024 SND_SOC_DAPM_PGA("IF1 DAC7", SND_SOC_NOPM, 0, 0, NULL, 0), 3025 SND_SOC_DAPM_PGA("IF1 DAC01", SND_SOC_NOPM, 0, 0, NULL, 0), 3026 SND_SOC_DAPM_PGA("IF1 DAC23", SND_SOC_NOPM, 0, 0, NULL, 0), 3027 SND_SOC_DAPM_PGA("IF1 DAC45", SND_SOC_NOPM, 0, 0, NULL, 0), 3028 SND_SOC_DAPM_PGA("IF1 DAC67", SND_SOC_NOPM, 0, 0, NULL, 0), 3029 SND_SOC_DAPM_PGA("IF1 ADC1", SND_SOC_NOPM, 0, 0, NULL, 0), 3030 SND_SOC_DAPM_PGA("IF1 ADC2", SND_SOC_NOPM, 0, 0, NULL, 0), 3031 SND_SOC_DAPM_PGA("IF1 ADC3", SND_SOC_NOPM, 0, 0, NULL, 0), 3032 SND_SOC_DAPM_PGA("IF1 ADC4", SND_SOC_NOPM, 0, 0, NULL, 0), 3033 3034 SND_SOC_DAPM_SUPPLY("I2S2", RT5677_PWR_DIG1, 3035 RT5677_PWR_I2S2_BIT, 0, NULL, 0), 3036 SND_SOC_DAPM_PGA("IF2 DAC0", SND_SOC_NOPM, 0, 0, NULL, 0), 3037 SND_SOC_DAPM_PGA("IF2 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0), 3038 SND_SOC_DAPM_PGA("IF2 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0), 3039 SND_SOC_DAPM_PGA("IF2 DAC3", SND_SOC_NOPM, 0, 0, NULL, 0), 3040 SND_SOC_DAPM_PGA("IF2 DAC4", SND_SOC_NOPM, 0, 0, NULL, 0), 3041 SND_SOC_DAPM_PGA("IF2 DAC5", SND_SOC_NOPM, 0, 0, NULL, 0), 3042 SND_SOC_DAPM_PGA("IF2 DAC6", SND_SOC_NOPM, 0, 0, NULL, 0), 3043 SND_SOC_DAPM_PGA("IF2 DAC7", SND_SOC_NOPM, 0, 0, NULL, 0), 3044 SND_SOC_DAPM_PGA("IF2 DAC01", SND_SOC_NOPM, 0, 0, NULL, 0), 3045 SND_SOC_DAPM_PGA("IF2 DAC23", SND_SOC_NOPM, 0, 0, NULL, 0), 3046 SND_SOC_DAPM_PGA("IF2 DAC45", SND_SOC_NOPM, 0, 0, NULL, 0), 3047 SND_SOC_DAPM_PGA("IF2 DAC67", SND_SOC_NOPM, 0, 0, NULL, 0), 3048 SND_SOC_DAPM_PGA("IF2 ADC1", SND_SOC_NOPM, 0, 0, NULL, 0), 3049 SND_SOC_DAPM_PGA("IF2 ADC2", SND_SOC_NOPM, 0, 0, NULL, 0), 3050 SND_SOC_DAPM_PGA("IF2 ADC3", SND_SOC_NOPM, 0, 0, NULL, 0), 3051 SND_SOC_DAPM_PGA("IF2 ADC4", SND_SOC_NOPM, 0, 0, NULL, 0), 3052 3053 SND_SOC_DAPM_SUPPLY("I2S3", RT5677_PWR_DIG1, 3054 RT5677_PWR_I2S3_BIT, 0, NULL, 0), 3055 SND_SOC_DAPM_PGA("IF3 DAC", SND_SOC_NOPM, 0, 0, NULL, 0), 3056 SND_SOC_DAPM_PGA("IF3 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0), 3057 SND_SOC_DAPM_PGA("IF3 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0), 3058 SND_SOC_DAPM_PGA("IF3 ADC", SND_SOC_NOPM, 0, 0, NULL, 0), 3059 SND_SOC_DAPM_PGA("IF3 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0), 3060 SND_SOC_DAPM_PGA("IF3 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0), 3061 3062 SND_SOC_DAPM_SUPPLY("I2S4", RT5677_PWR_DIG1, 3063 RT5677_PWR_I2S4_BIT, 0, NULL, 0), 3064 SND_SOC_DAPM_PGA("IF4 DAC", SND_SOC_NOPM, 0, 0, NULL, 0), 3065 SND_SOC_DAPM_PGA("IF4 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0), 3066 SND_SOC_DAPM_PGA("IF4 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0), 3067 SND_SOC_DAPM_PGA("IF4 ADC", SND_SOC_NOPM, 0, 0, NULL, 0), 3068 SND_SOC_DAPM_PGA("IF4 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0), 3069 SND_SOC_DAPM_PGA("IF4 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0), 3070 3071 SND_SOC_DAPM_SUPPLY("SLB", RT5677_PWR_DIG1, 3072 RT5677_PWR_SLB_BIT, 0, NULL, 0), 3073 SND_SOC_DAPM_PGA("SLB DAC0", SND_SOC_NOPM, 0, 0, NULL, 0), 3074 SND_SOC_DAPM_PGA("SLB DAC1", SND_SOC_NOPM, 0, 0, NULL, 0), 3075 SND_SOC_DAPM_PGA("SLB DAC2", SND_SOC_NOPM, 0, 0, NULL, 0), 3076 SND_SOC_DAPM_PGA("SLB DAC3", SND_SOC_NOPM, 0, 0, NULL, 0), 3077 SND_SOC_DAPM_PGA("SLB DAC4", SND_SOC_NOPM, 0, 0, NULL, 0), 3078 SND_SOC_DAPM_PGA("SLB DAC5", SND_SOC_NOPM, 0, 0, NULL, 0), 3079 SND_SOC_DAPM_PGA("SLB DAC6", SND_SOC_NOPM, 0, 0, NULL, 0), 3080 SND_SOC_DAPM_PGA("SLB DAC7", SND_SOC_NOPM, 0, 0, NULL, 0), 3081 SND_SOC_DAPM_PGA("SLB DAC01", SND_SOC_NOPM, 0, 0, NULL, 0), 3082 SND_SOC_DAPM_PGA("SLB DAC23", SND_SOC_NOPM, 0, 0, NULL, 0), 3083 SND_SOC_DAPM_PGA("SLB DAC45", SND_SOC_NOPM, 0, 0, NULL, 0), 3084 SND_SOC_DAPM_PGA("SLB DAC67", SND_SOC_NOPM, 0, 0, NULL, 0), 3085 SND_SOC_DAPM_PGA("SLB ADC1", SND_SOC_NOPM, 0, 0, NULL, 0), 3086 SND_SOC_DAPM_PGA("SLB ADC2", SND_SOC_NOPM, 0, 0, NULL, 0), 3087 SND_SOC_DAPM_PGA("SLB ADC3", SND_SOC_NOPM, 0, 0, NULL, 0), 3088 SND_SOC_DAPM_PGA("SLB ADC4", SND_SOC_NOPM, 0, 0, NULL, 0), 3089 3090 /* Digital Interface Select */ 3091 SND_SOC_DAPM_MUX("IF1 ADC1 Mux", SND_SOC_NOPM, 0, 0, 3092 &rt5677_if1_adc1_mux), 3093 SND_SOC_DAPM_MUX("IF1 ADC2 Mux", SND_SOC_NOPM, 0, 0, 3094 &rt5677_if1_adc2_mux), 3095 SND_SOC_DAPM_MUX("IF1 ADC3 Mux", SND_SOC_NOPM, 0, 0, 3096 &rt5677_if1_adc3_mux), 3097 SND_SOC_DAPM_MUX("IF1 ADC4 Mux", SND_SOC_NOPM, 0, 0, 3098 &rt5677_if1_adc4_mux), 3099 SND_SOC_DAPM_MUX("IF1 ADC1 Swap Mux", SND_SOC_NOPM, 0, 0, 3100 &rt5677_if1_adc1_swap_mux), 3101 SND_SOC_DAPM_MUX("IF1 ADC2 Swap Mux", SND_SOC_NOPM, 0, 0, 3102 &rt5677_if1_adc2_swap_mux), 3103 SND_SOC_DAPM_MUX("IF1 ADC3 Swap Mux", SND_SOC_NOPM, 0, 0, 3104 &rt5677_if1_adc3_swap_mux), 3105 SND_SOC_DAPM_MUX("IF1 ADC4 Swap Mux", SND_SOC_NOPM, 0, 0, 3106 &rt5677_if1_adc4_swap_mux), 3107 SND_SOC_DAPM_MUX_E("IF1 ADC TDM Swap Mux", SND_SOC_NOPM, 0, 0, 3108 &rt5677_if1_adc_tdm_swap_mux, rt5677_if1_adc_tdm_event, 3109 SND_SOC_DAPM_PRE_PMU), 3110 SND_SOC_DAPM_MUX("IF2 ADC1 Mux", SND_SOC_NOPM, 0, 0, 3111 &rt5677_if2_adc1_mux), 3112 SND_SOC_DAPM_MUX("IF2 ADC2 Mux", SND_SOC_NOPM, 0, 0, 3113 &rt5677_if2_adc2_mux), 3114 SND_SOC_DAPM_MUX("IF2 ADC3 Mux", SND_SOC_NOPM, 0, 0, 3115 &rt5677_if2_adc3_mux), 3116 SND_SOC_DAPM_MUX("IF2 ADC4 Mux", SND_SOC_NOPM, 0, 0, 3117 &rt5677_if2_adc4_mux), 3118 SND_SOC_DAPM_MUX("IF2 ADC1 Swap Mux", SND_SOC_NOPM, 0, 0, 3119 &rt5677_if2_adc1_swap_mux), 3120 SND_SOC_DAPM_MUX("IF2 ADC2 Swap Mux", SND_SOC_NOPM, 0, 0, 3121 &rt5677_if2_adc2_swap_mux), 3122 SND_SOC_DAPM_MUX("IF2 ADC3 Swap Mux", SND_SOC_NOPM, 0, 0, 3123 &rt5677_if2_adc3_swap_mux), 3124 SND_SOC_DAPM_MUX("IF2 ADC4 Swap Mux", SND_SOC_NOPM, 0, 0, 3125 &rt5677_if2_adc4_swap_mux), 3126 SND_SOC_DAPM_MUX_E("IF2 ADC TDM Swap Mux", SND_SOC_NOPM, 0, 0, 3127 &rt5677_if2_adc_tdm_swap_mux, rt5677_if2_adc_tdm_event, 3128 SND_SOC_DAPM_PRE_PMU), 3129 SND_SOC_DAPM_MUX("IF3 ADC Mux", SND_SOC_NOPM, 0, 0, 3130 &rt5677_if3_adc_mux), 3131 SND_SOC_DAPM_MUX("IF4 ADC Mux", SND_SOC_NOPM, 0, 0, 3132 &rt5677_if4_adc_mux), 3133 SND_SOC_DAPM_MUX("SLB ADC1 Mux", SND_SOC_NOPM, 0, 0, 3134 &rt5677_slb_adc1_mux), 3135 SND_SOC_DAPM_MUX("SLB ADC2 Mux", SND_SOC_NOPM, 0, 0, 3136 &rt5677_slb_adc2_mux), 3137 SND_SOC_DAPM_MUX("SLB ADC3 Mux", SND_SOC_NOPM, 0, 0, 3138 &rt5677_slb_adc3_mux), 3139 SND_SOC_DAPM_MUX("SLB ADC4 Mux", SND_SOC_NOPM, 0, 0, 3140 &rt5677_slb_adc4_mux), 3141 3142 SND_SOC_DAPM_MUX("IF1 DAC0 Mux", SND_SOC_NOPM, 0, 0, 3143 &rt5677_if1_dac0_tdm_sel_mux), 3144 SND_SOC_DAPM_MUX("IF1 DAC1 Mux", SND_SOC_NOPM, 0, 0, 3145 &rt5677_if1_dac1_tdm_sel_mux), 3146 SND_SOC_DAPM_MUX("IF1 DAC2 Mux", SND_SOC_NOPM, 0, 0, 3147 &rt5677_if1_dac2_tdm_sel_mux), 3148 SND_SOC_DAPM_MUX("IF1 DAC3 Mux", SND_SOC_NOPM, 0, 0, 3149 &rt5677_if1_dac3_tdm_sel_mux), 3150 SND_SOC_DAPM_MUX("IF1 DAC4 Mux", SND_SOC_NOPM, 0, 0, 3151 &rt5677_if1_dac4_tdm_sel_mux), 3152 SND_SOC_DAPM_MUX("IF1 DAC5 Mux", SND_SOC_NOPM, 0, 0, 3153 &rt5677_if1_dac5_tdm_sel_mux), 3154 SND_SOC_DAPM_MUX("IF1 DAC6 Mux", SND_SOC_NOPM, 0, 0, 3155 &rt5677_if1_dac6_tdm_sel_mux), 3156 SND_SOC_DAPM_MUX("IF1 DAC7 Mux", SND_SOC_NOPM, 0, 0, 3157 &rt5677_if1_dac7_tdm_sel_mux), 3158 3159 SND_SOC_DAPM_MUX("IF2 DAC0 Mux", SND_SOC_NOPM, 0, 0, 3160 &rt5677_if2_dac0_tdm_sel_mux), 3161 SND_SOC_DAPM_MUX("IF2 DAC1 Mux", SND_SOC_NOPM, 0, 0, 3162 &rt5677_if2_dac1_tdm_sel_mux), 3163 SND_SOC_DAPM_MUX("IF2 DAC2 Mux", SND_SOC_NOPM, 0, 0, 3164 &rt5677_if2_dac2_tdm_sel_mux), 3165 SND_SOC_DAPM_MUX("IF2 DAC3 Mux", SND_SOC_NOPM, 0, 0, 3166 &rt5677_if2_dac3_tdm_sel_mux), 3167 SND_SOC_DAPM_MUX("IF2 DAC4 Mux", SND_SOC_NOPM, 0, 0, 3168 &rt5677_if2_dac4_tdm_sel_mux), 3169 SND_SOC_DAPM_MUX("IF2 DAC5 Mux", SND_SOC_NOPM, 0, 0, 3170 &rt5677_if2_dac5_tdm_sel_mux), 3171 SND_SOC_DAPM_MUX("IF2 DAC6 Mux", SND_SOC_NOPM, 0, 0, 3172 &rt5677_if2_dac6_tdm_sel_mux), 3173 SND_SOC_DAPM_MUX("IF2 DAC7 Mux", SND_SOC_NOPM, 0, 0, 3174 &rt5677_if2_dac7_tdm_sel_mux), 3175 3176 /* Audio Interface */ 3177 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0), 3178 SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0), 3179 SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0), 3180 SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0), 3181 SND_SOC_DAPM_AIF_IN("AIF3RX", "AIF3 Playback", 0, SND_SOC_NOPM, 0, 0), 3182 SND_SOC_DAPM_AIF_OUT("AIF3TX", "AIF3 Capture", 0, SND_SOC_NOPM, 0, 0), 3183 SND_SOC_DAPM_AIF_IN("AIF4RX", "AIF4 Playback", 0, SND_SOC_NOPM, 0, 0), 3184 SND_SOC_DAPM_AIF_OUT("AIF4TX", "AIF4 Capture", 0, SND_SOC_NOPM, 0, 0), 3185 SND_SOC_DAPM_AIF_IN("SLBRX", "SLIMBus Playback", 0, SND_SOC_NOPM, 0, 0), 3186 SND_SOC_DAPM_AIF_OUT("SLBTX", "SLIMBus Capture", 0, SND_SOC_NOPM, 0, 0), 3187 SND_SOC_DAPM_AIF_OUT("DSPTX", "DSP Buffer", 0, SND_SOC_NOPM, 0, 0), 3188 3189 /* Sidetone Mux */ 3190 SND_SOC_DAPM_MUX("Sidetone Mux", SND_SOC_NOPM, 0, 0, 3191 &rt5677_sidetone_mux), 3192 SND_SOC_DAPM_SUPPLY("Sidetone Power", RT5677_SIDETONE_CTRL, 3193 RT5677_ST_EN_SFT, 0, NULL, 0), 3194 3195 /* VAD Mux*/ 3196 SND_SOC_DAPM_MUX("VAD ADC Mux", SND_SOC_NOPM, 0, 0, 3197 &rt5677_vad_src_mux), 3198 3199 /* Tensilica DSP */ 3200 SND_SOC_DAPM_PGA("Tensilica DSP", SND_SOC_NOPM, 0, 0, NULL, 0), 3201 SND_SOC_DAPM_MIXER("OB01 MIX", SND_SOC_NOPM, 0, 0, 3202 rt5677_ob_01_mix, ARRAY_SIZE(rt5677_ob_01_mix)), 3203 SND_SOC_DAPM_MIXER("OB23 MIX", SND_SOC_NOPM, 0, 0, 3204 rt5677_ob_23_mix, ARRAY_SIZE(rt5677_ob_23_mix)), 3205 SND_SOC_DAPM_MIXER("OB4 MIX", SND_SOC_NOPM, 0, 0, 3206 rt5677_ob_4_mix, ARRAY_SIZE(rt5677_ob_4_mix)), 3207 SND_SOC_DAPM_MIXER("OB5 MIX", SND_SOC_NOPM, 0, 0, 3208 rt5677_ob_5_mix, ARRAY_SIZE(rt5677_ob_5_mix)), 3209 SND_SOC_DAPM_MIXER("OB6 MIX", SND_SOC_NOPM, 0, 0, 3210 rt5677_ob_6_mix, ARRAY_SIZE(rt5677_ob_6_mix)), 3211 SND_SOC_DAPM_MIXER("OB7 MIX", SND_SOC_NOPM, 0, 0, 3212 rt5677_ob_7_mix, ARRAY_SIZE(rt5677_ob_7_mix)), 3213 3214 /* Output Side */ 3215 /* DAC mixer before sound effect */ 3216 SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0, 3217 rt5677_dac_l_mix, ARRAY_SIZE(rt5677_dac_l_mix)), 3218 SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0, 3219 rt5677_dac_r_mix, ARRAY_SIZE(rt5677_dac_r_mix)), 3220 SND_SOC_DAPM_PGA("DAC1 FS", SND_SOC_NOPM, 0, 0, NULL, 0), 3221 3222 /* DAC Mux */ 3223 SND_SOC_DAPM_MUX("DAC1 Mux", SND_SOC_NOPM, 0, 0, 3224 &rt5677_dac1_mux), 3225 SND_SOC_DAPM_MUX("ADDA1 Mux", SND_SOC_NOPM, 0, 0, 3226 &rt5677_adda1_mux), 3227 SND_SOC_DAPM_MUX("DAC12 SRC Mux", SND_SOC_NOPM, 0, 0, 3228 &rt5677_dac12_mux), 3229 SND_SOC_DAPM_MUX("DAC3 SRC Mux", SND_SOC_NOPM, 0, 0, 3230 &rt5677_dac3_mux), 3231 3232 /* DAC2 channel Mux */ 3233 SND_SOC_DAPM_MUX("DAC2 L Mux", SND_SOC_NOPM, 0, 0, 3234 &rt5677_dac2_l_mux), 3235 SND_SOC_DAPM_MUX("DAC2 R Mux", SND_SOC_NOPM, 0, 0, 3236 &rt5677_dac2_r_mux), 3237 3238 /* DAC3 channel Mux */ 3239 SND_SOC_DAPM_MUX("DAC3 L Mux", SND_SOC_NOPM, 0, 0, 3240 &rt5677_dac3_l_mux), 3241 SND_SOC_DAPM_MUX("DAC3 R Mux", SND_SOC_NOPM, 0, 0, 3242 &rt5677_dac3_r_mux), 3243 3244 /* DAC4 channel Mux */ 3245 SND_SOC_DAPM_MUX("DAC4 L Mux", SND_SOC_NOPM, 0, 0, 3246 &rt5677_dac4_l_mux), 3247 SND_SOC_DAPM_MUX("DAC4 R Mux", SND_SOC_NOPM, 0, 0, 3248 &rt5677_dac4_r_mux), 3249 3250 /* DAC Mixer */ 3251 SND_SOC_DAPM_SUPPLY("dac stereo1 filter", RT5677_PWR_DIG2, 3252 RT5677_PWR_DAC_S1F_BIT, 0, rt5677_filter_power_event, 3253 SND_SOC_DAPM_POST_PMU), 3254 SND_SOC_DAPM_SUPPLY("dac mono2 left filter", RT5677_PWR_DIG2, 3255 RT5677_PWR_DAC_M2F_L_BIT, 0, rt5677_filter_power_event, 3256 SND_SOC_DAPM_POST_PMU), 3257 SND_SOC_DAPM_SUPPLY("dac mono2 right filter", RT5677_PWR_DIG2, 3258 RT5677_PWR_DAC_M2F_R_BIT, 0, rt5677_filter_power_event, 3259 SND_SOC_DAPM_POST_PMU), 3260 SND_SOC_DAPM_SUPPLY("dac mono3 left filter", RT5677_PWR_DIG2, 3261 RT5677_PWR_DAC_M3F_L_BIT, 0, rt5677_filter_power_event, 3262 SND_SOC_DAPM_POST_PMU), 3263 SND_SOC_DAPM_SUPPLY("dac mono3 right filter", RT5677_PWR_DIG2, 3264 RT5677_PWR_DAC_M3F_R_BIT, 0, rt5677_filter_power_event, 3265 SND_SOC_DAPM_POST_PMU), 3266 SND_SOC_DAPM_SUPPLY("dac mono4 left filter", RT5677_PWR_DIG2, 3267 RT5677_PWR_DAC_M4F_L_BIT, 0, rt5677_filter_power_event, 3268 SND_SOC_DAPM_POST_PMU), 3269 SND_SOC_DAPM_SUPPLY("dac mono4 right filter", RT5677_PWR_DIG2, 3270 RT5677_PWR_DAC_M4F_R_BIT, 0, rt5677_filter_power_event, 3271 SND_SOC_DAPM_POST_PMU), 3272 3273 SND_SOC_DAPM_MIXER("Stereo DAC MIXL", SND_SOC_NOPM, 0, 0, 3274 rt5677_sto1_dac_l_mix, ARRAY_SIZE(rt5677_sto1_dac_l_mix)), 3275 SND_SOC_DAPM_MIXER("Stereo DAC MIXR", SND_SOC_NOPM, 0, 0, 3276 rt5677_sto1_dac_r_mix, ARRAY_SIZE(rt5677_sto1_dac_r_mix)), 3277 SND_SOC_DAPM_MIXER("Mono DAC MIXL", SND_SOC_NOPM, 0, 0, 3278 rt5677_mono_dac_l_mix, ARRAY_SIZE(rt5677_mono_dac_l_mix)), 3279 SND_SOC_DAPM_MIXER("Mono DAC MIXR", SND_SOC_NOPM, 0, 0, 3280 rt5677_mono_dac_r_mix, ARRAY_SIZE(rt5677_mono_dac_r_mix)), 3281 SND_SOC_DAPM_MIXER("DD1 MIXL", SND_SOC_NOPM, 0, 0, 3282 rt5677_dd1_l_mix, ARRAY_SIZE(rt5677_dd1_l_mix)), 3283 SND_SOC_DAPM_MIXER("DD1 MIXR", SND_SOC_NOPM, 0, 0, 3284 rt5677_dd1_r_mix, ARRAY_SIZE(rt5677_dd1_r_mix)), 3285 SND_SOC_DAPM_MIXER("DD2 MIXL", SND_SOC_NOPM, 0, 0, 3286 rt5677_dd2_l_mix, ARRAY_SIZE(rt5677_dd2_l_mix)), 3287 SND_SOC_DAPM_MIXER("DD2 MIXR", SND_SOC_NOPM, 0, 0, 3288 rt5677_dd2_r_mix, ARRAY_SIZE(rt5677_dd2_r_mix)), 3289 SND_SOC_DAPM_PGA("Stereo DAC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 3290 SND_SOC_DAPM_PGA("Mono DAC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 3291 SND_SOC_DAPM_PGA("DD1 MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 3292 SND_SOC_DAPM_PGA("DD2 MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 3293 3294 /* DACs */ 3295 SND_SOC_DAPM_DAC("DAC 1", NULL, RT5677_PWR_DIG1, 3296 RT5677_PWR_DAC1_BIT, 0), 3297 SND_SOC_DAPM_DAC("DAC 2", NULL, RT5677_PWR_DIG1, 3298 RT5677_PWR_DAC2_BIT, 0), 3299 SND_SOC_DAPM_DAC("DAC 3", NULL, RT5677_PWR_DIG1, 3300 RT5677_PWR_DAC3_BIT, 0), 3301 3302 /* PDM */ 3303 SND_SOC_DAPM_SUPPLY("PDM1 Power", RT5677_PWR_DIG2, 3304 RT5677_PWR_PDM1_BIT, 0, NULL, 0), 3305 SND_SOC_DAPM_SUPPLY("PDM2 Power", RT5677_PWR_DIG2, 3306 RT5677_PWR_PDM2_BIT, 0, NULL, 0), 3307 3308 SND_SOC_DAPM_MUX("PDM1 L Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM1_L_SFT, 3309 1, &rt5677_pdm1_l_mux), 3310 SND_SOC_DAPM_MUX("PDM1 R Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM1_R_SFT, 3311 1, &rt5677_pdm1_r_mux), 3312 SND_SOC_DAPM_MUX("PDM2 L Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM2_L_SFT, 3313 1, &rt5677_pdm2_l_mux), 3314 SND_SOC_DAPM_MUX("PDM2 R Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM2_R_SFT, 3315 1, &rt5677_pdm2_r_mux), 3316 3317 SND_SOC_DAPM_PGA_S("LOUT1 amp", 0, RT5677_PWR_ANLG1, RT5677_PWR_LO1_BIT, 3318 0, NULL, 0), 3319 SND_SOC_DAPM_PGA_S("LOUT2 amp", 0, RT5677_PWR_ANLG1, RT5677_PWR_LO2_BIT, 3320 0, NULL, 0), 3321 SND_SOC_DAPM_PGA_S("LOUT3 amp", 0, RT5677_PWR_ANLG1, RT5677_PWR_LO3_BIT, 3322 0, NULL, 0), 3323 3324 SND_SOC_DAPM_PGA_S("LOUT1 vref", 1, SND_SOC_NOPM, 0, 0, 3325 rt5677_vref_event, SND_SOC_DAPM_POST_PMU), 3326 SND_SOC_DAPM_PGA_S("LOUT2 vref", 1, SND_SOC_NOPM, 0, 0, 3327 rt5677_vref_event, SND_SOC_DAPM_POST_PMU), 3328 SND_SOC_DAPM_PGA_S("LOUT3 vref", 1, SND_SOC_NOPM, 0, 0, 3329 rt5677_vref_event, SND_SOC_DAPM_POST_PMU), 3330 3331 /* Output Lines */ 3332 SND_SOC_DAPM_OUTPUT("LOUT1"), 3333 SND_SOC_DAPM_OUTPUT("LOUT2"), 3334 SND_SOC_DAPM_OUTPUT("LOUT3"), 3335 SND_SOC_DAPM_OUTPUT("PDM1L"), 3336 SND_SOC_DAPM_OUTPUT("PDM1R"), 3337 SND_SOC_DAPM_OUTPUT("PDM2L"), 3338 SND_SOC_DAPM_OUTPUT("PDM2R"), 3339 3340 SND_SOC_DAPM_POST("vref", rt5677_vref_event), 3341 }; 3342 3343 static const struct snd_soc_dapm_route rt5677_dapm_routes[] = { 3344 { "Stereo1 DMIC Mux", NULL, "DMIC STO1 ASRC", rt5677_dmic_use_asrc }, 3345 { "Stereo2 DMIC Mux", NULL, "DMIC STO2 ASRC", rt5677_dmic_use_asrc }, 3346 { "Stereo3 DMIC Mux", NULL, "DMIC STO3 ASRC", rt5677_dmic_use_asrc }, 3347 { "Stereo4 DMIC Mux", NULL, "DMIC STO4 ASRC", rt5677_dmic_use_asrc }, 3348 { "Mono DMIC L Mux", NULL, "DMIC MONO L ASRC", rt5677_dmic_use_asrc }, 3349 { "Mono DMIC R Mux", NULL, "DMIC MONO R ASRC", rt5677_dmic_use_asrc }, 3350 { "I2S1", NULL, "I2S1 ASRC", can_use_asrc}, 3351 { "I2S2", NULL, "I2S2 ASRC", can_use_asrc}, 3352 { "I2S3", NULL, "I2S3 ASRC", can_use_asrc}, 3353 { "I2S4", NULL, "I2S4 ASRC", can_use_asrc}, 3354 3355 { "dac stereo1 filter", NULL, "DAC STO ASRC", is_using_asrc }, 3356 { "dac mono2 left filter", NULL, "DAC MONO2 L ASRC", is_using_asrc }, 3357 { "dac mono2 right filter", NULL, "DAC MONO2 R ASRC", is_using_asrc }, 3358 { "dac mono3 left filter", NULL, "DAC MONO3 L ASRC", is_using_asrc }, 3359 { "dac mono3 right filter", NULL, "DAC MONO3 R ASRC", is_using_asrc }, 3360 { "dac mono4 left filter", NULL, "DAC MONO4 L ASRC", is_using_asrc }, 3361 { "dac mono4 right filter", NULL, "DAC MONO4 R ASRC", is_using_asrc }, 3362 { "adc stereo1 filter", NULL, "ADC STO1 ASRC", is_using_asrc }, 3363 { "adc stereo2 filter", NULL, "ADC STO2 ASRC", is_using_asrc }, 3364 { "adc stereo3 filter", NULL, "ADC STO3 ASRC", is_using_asrc }, 3365 { "adc stereo4 filter", NULL, "ADC STO4 ASRC", is_using_asrc }, 3366 { "adc mono left filter", NULL, "ADC MONO L ASRC", is_using_asrc }, 3367 { "adc mono right filter", NULL, "ADC MONO R ASRC", is_using_asrc }, 3368 3369 { "DMIC1", NULL, "DMIC L1" }, 3370 { "DMIC1", NULL, "DMIC R1" }, 3371 { "DMIC2", NULL, "DMIC L2" }, 3372 { "DMIC2", NULL, "DMIC R2" }, 3373 { "DMIC3", NULL, "DMIC L3" }, 3374 { "DMIC3", NULL, "DMIC R3" }, 3375 { "DMIC4", NULL, "DMIC L4" }, 3376 { "DMIC4", NULL, "DMIC R4" }, 3377 3378 { "DMIC L1", NULL, "DMIC CLK" }, 3379 { "DMIC R1", NULL, "DMIC CLK" }, 3380 { "DMIC L2", NULL, "DMIC CLK" }, 3381 { "DMIC R2", NULL, "DMIC CLK" }, 3382 { "DMIC L3", NULL, "DMIC CLK" }, 3383 { "DMIC R3", NULL, "DMIC CLK" }, 3384 { "DMIC L4", NULL, "DMIC CLK" }, 3385 { "DMIC R4", NULL, "DMIC CLK" }, 3386 3387 { "DMIC L1", NULL, "DMIC1 power" }, 3388 { "DMIC R1", NULL, "DMIC1 power" }, 3389 { "DMIC L3", NULL, "DMIC3 power" }, 3390 { "DMIC R3", NULL, "DMIC3 power" }, 3391 { "DMIC L4", NULL, "DMIC4 power" }, 3392 { "DMIC R4", NULL, "DMIC4 power" }, 3393 3394 { "BST1", NULL, "IN1P" }, 3395 { "BST1", NULL, "IN1N" }, 3396 { "BST2", NULL, "IN2P" }, 3397 { "BST2", NULL, "IN2N" }, 3398 3399 { "IN1P", NULL, "MICBIAS1" }, 3400 { "IN1N", NULL, "MICBIAS1" }, 3401 { "IN2P", NULL, "MICBIAS1" }, 3402 { "IN2N", NULL, "MICBIAS1" }, 3403 3404 { "ADC 1", NULL, "BST1" }, 3405 { "ADC 1", NULL, "ADC 1 power" }, 3406 { "ADC 1", NULL, "ADC1 clock" }, 3407 { "ADC 2", NULL, "BST2" }, 3408 { "ADC 2", NULL, "ADC 2 power" }, 3409 { "ADC 2", NULL, "ADC2 clock" }, 3410 3411 { "Stereo1 DMIC Mux", "DMIC1", "DMIC1" }, 3412 { "Stereo1 DMIC Mux", "DMIC2", "DMIC2" }, 3413 { "Stereo1 DMIC Mux", "DMIC3", "DMIC3" }, 3414 { "Stereo1 DMIC Mux", "DMIC4", "DMIC4" }, 3415 3416 { "Stereo2 DMIC Mux", "DMIC1", "DMIC1" }, 3417 { "Stereo2 DMIC Mux", "DMIC2", "DMIC2" }, 3418 { "Stereo2 DMIC Mux", "DMIC3", "DMIC3" }, 3419 { "Stereo2 DMIC Mux", "DMIC4", "DMIC4" }, 3420 3421 { "Stereo3 DMIC Mux", "DMIC1", "DMIC1" }, 3422 { "Stereo3 DMIC Mux", "DMIC2", "DMIC2" }, 3423 { "Stereo3 DMIC Mux", "DMIC3", "DMIC3" }, 3424 { "Stereo3 DMIC Mux", "DMIC4", "DMIC4" }, 3425 3426 { "Stereo4 DMIC Mux", "DMIC1", "DMIC1" }, 3427 { "Stereo4 DMIC Mux", "DMIC2", "DMIC2" }, 3428 { "Stereo4 DMIC Mux", "DMIC3", "DMIC3" }, 3429 { "Stereo4 DMIC Mux", "DMIC4", "DMIC4" }, 3430 3431 { "Mono DMIC L Mux", "DMIC1", "DMIC1" }, 3432 { "Mono DMIC L Mux", "DMIC2", "DMIC2" }, 3433 { "Mono DMIC L Mux", "DMIC3", "DMIC3" }, 3434 { "Mono DMIC L Mux", "DMIC4", "DMIC4" }, 3435 3436 { "Mono DMIC R Mux", "DMIC1", "DMIC1" }, 3437 { "Mono DMIC R Mux", "DMIC2", "DMIC2" }, 3438 { "Mono DMIC R Mux", "DMIC3", "DMIC3" }, 3439 { "Mono DMIC R Mux", "DMIC4", "DMIC4" }, 3440 3441 { "ADC 1_2", NULL, "ADC 1" }, 3442 { "ADC 1_2", NULL, "ADC 2" }, 3443 3444 { "Stereo1 ADC1 Mux", "DD MIX1", "DD1 MIX" }, 3445 { "Stereo1 ADC1 Mux", "ADC1/2", "ADC 1_2" }, 3446 { "Stereo1 ADC1 Mux", "Stereo DAC MIX", "Stereo DAC MIX" }, 3447 3448 { "Stereo1 ADC2 Mux", "DD MIX1", "DD1 MIX" }, 3449 { "Stereo1 ADC2 Mux", "DMIC", "Stereo1 DMIC Mux" }, 3450 { "Stereo1 ADC2 Mux", "Stereo DAC MIX", "Stereo DAC MIX" }, 3451 3452 { "Stereo2 ADC1 Mux", "DD MIX1", "DD1 MIX" }, 3453 { "Stereo2 ADC1 Mux", "ADC1/2", "ADC 1_2" }, 3454 { "Stereo2 ADC1 Mux", "Stereo DAC MIX", "Stereo DAC MIX" }, 3455 3456 { "Stereo2 ADC2 Mux", "DD MIX1", "DD1 MIX" }, 3457 { "Stereo2 ADC2 Mux", "DMIC", "Stereo2 DMIC Mux" }, 3458 { "Stereo2 ADC2 Mux", "Stereo DAC MIX", "Stereo DAC MIX" }, 3459 3460 { "Stereo3 ADC1 Mux", "DD MIX1", "DD1 MIX" }, 3461 { "Stereo3 ADC1 Mux", "ADC1/2", "ADC 1_2" }, 3462 { "Stereo3 ADC1 Mux", "Stereo DAC MIX", "Stereo DAC MIX" }, 3463 3464 { "Stereo3 ADC2 Mux", "DD MIX1", "DD1 MIX" }, 3465 { "Stereo3 ADC2 Mux", "DMIC", "Stereo3 DMIC Mux" }, 3466 { "Stereo3 ADC2 Mux", "Stereo DAC MIX", "Stereo DAC MIX" }, 3467 3468 { "Stereo4 ADC1 Mux", "DD MIX1", "DD1 MIX" }, 3469 { "Stereo4 ADC1 Mux", "ADC1/2", "ADC 1_2" }, 3470 { "Stereo4 ADC1 Mux", "DD MIX2", "DD2 MIX" }, 3471 3472 { "Stereo4 ADC2 Mux", "DD MIX1", "DD1 MIX" }, 3473 { "Stereo4 ADC2 Mux", "DMIC", "Stereo3 DMIC Mux" }, 3474 { "Stereo4 ADC2 Mux", "DD MIX2", "DD2 MIX" }, 3475 3476 { "Mono ADC2 L Mux", "DD MIX1L", "DD1 MIXL" }, 3477 { "Mono ADC2 L Mux", "DMIC", "Mono DMIC L Mux" }, 3478 { "Mono ADC2 L Mux", "MONO DAC MIXL", "Mono DAC MIXL" }, 3479 3480 { "Mono ADC1 L Mux", "DD MIX1L", "DD1 MIXL" }, 3481 { "Mono ADC1 L Mux", "ADC1", "ADC 1" }, 3482 { "Mono ADC1 L Mux", "MONO DAC MIXL", "Mono DAC MIXL" }, 3483 3484 { "Mono ADC1 R Mux", "DD MIX1R", "DD1 MIXR" }, 3485 { "Mono ADC1 R Mux", "ADC2", "ADC 2" }, 3486 { "Mono ADC1 R Mux", "MONO DAC MIXR", "Mono DAC MIXR" }, 3487 3488 { "Mono ADC2 R Mux", "DD MIX1R", "DD1 MIXR" }, 3489 { "Mono ADC2 R Mux", "DMIC", "Mono DMIC R Mux" }, 3490 { "Mono ADC2 R Mux", "MONO DAC MIXR", "Mono DAC MIXR" }, 3491 3492 { "Sto1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC1 Mux" }, 3493 { "Sto1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC2 Mux" }, 3494 { "Sto1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC1 Mux" }, 3495 { "Sto1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC2 Mux" }, 3496 3497 { "Stereo1 ADC MIXL", NULL, "Sto1 ADC MIXL" }, 3498 { "Stereo1 ADC MIXL", NULL, "adc stereo1 filter" }, 3499 { "Stereo1 ADC MIXR", NULL, "Sto1 ADC MIXR" }, 3500 { "Stereo1 ADC MIXR", NULL, "adc stereo1 filter" }, 3501 { "adc stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll }, 3502 3503 { "Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXL" }, 3504 { "Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXR" }, 3505 3506 { "Sto2 ADC MIXL", "ADC1 Switch", "Stereo2 ADC1 Mux" }, 3507 { "Sto2 ADC MIXL", "ADC2 Switch", "Stereo2 ADC2 Mux" }, 3508 { "Sto2 ADC MIXR", "ADC1 Switch", "Stereo2 ADC1 Mux" }, 3509 { "Sto2 ADC MIXR", "ADC2 Switch", "Stereo2 ADC2 Mux" }, 3510 3511 { "Sto2 ADC LR MIX", NULL, "Sto2 ADC MIXL" }, 3512 { "Sto2 ADC LR MIX", NULL, "Sto2 ADC MIXR" }, 3513 3514 { "Stereo2 ADC LR Mux", "L", "Sto2 ADC MIXL" }, 3515 { "Stereo2 ADC LR Mux", "LR", "Sto2 ADC LR MIX" }, 3516 3517 { "Stereo2 ADC MIXL", NULL, "Stereo2 ADC LR Mux" }, 3518 { "Stereo2 ADC MIXL", NULL, "adc stereo2 filter" }, 3519 { "Stereo2 ADC MIXR", NULL, "Sto2 ADC MIXR" }, 3520 { "Stereo2 ADC MIXR", NULL, "adc stereo2 filter" }, 3521 { "adc stereo2 filter", NULL, "PLL1", is_sys_clk_from_pll }, 3522 3523 { "Stereo2 ADC MIX", NULL, "Stereo2 ADC MIXL" }, 3524 { "Stereo2 ADC MIX", NULL, "Stereo2 ADC MIXR" }, 3525 3526 { "Sto3 ADC MIXL", "ADC1 Switch", "Stereo3 ADC1 Mux" }, 3527 { "Sto3 ADC MIXL", "ADC2 Switch", "Stereo3 ADC2 Mux" }, 3528 { "Sto3 ADC MIXR", "ADC1 Switch", "Stereo3 ADC1 Mux" }, 3529 { "Sto3 ADC MIXR", "ADC2 Switch", "Stereo3 ADC2 Mux" }, 3530 3531 { "Stereo3 ADC MIXL", NULL, "Sto3 ADC MIXL" }, 3532 { "Stereo3 ADC MIXL", NULL, "adc stereo3 filter" }, 3533 { "Stereo3 ADC MIXR", NULL, "Sto3 ADC MIXR" }, 3534 { "Stereo3 ADC MIXR", NULL, "adc stereo3 filter" }, 3535 { "adc stereo3 filter", NULL, "PLL1", is_sys_clk_from_pll }, 3536 3537 { "Stereo3 ADC MIX", NULL, "Stereo3 ADC MIXL" }, 3538 { "Stereo3 ADC MIX", NULL, "Stereo3 ADC MIXR" }, 3539 3540 { "Sto4 ADC MIXL", "ADC1 Switch", "Stereo4 ADC1 Mux" }, 3541 { "Sto4 ADC MIXL", "ADC2 Switch", "Stereo4 ADC2 Mux" }, 3542 { "Sto4 ADC MIXR", "ADC1 Switch", "Stereo4 ADC1 Mux" }, 3543 { "Sto4 ADC MIXR", "ADC2 Switch", "Stereo4 ADC2 Mux" }, 3544 3545 { "Stereo4 ADC MIXL", NULL, "Sto4 ADC MIXL" }, 3546 { "Stereo4 ADC MIXL", NULL, "adc stereo4 filter" }, 3547 { "Stereo4 ADC MIXR", NULL, "Sto4 ADC MIXR" }, 3548 { "Stereo4 ADC MIXR", NULL, "adc stereo4 filter" }, 3549 { "adc stereo4 filter", NULL, "PLL1", is_sys_clk_from_pll }, 3550 3551 { "Stereo4 ADC MIX", NULL, "Stereo4 ADC MIXL" }, 3552 { "Stereo4 ADC MIX", NULL, "Stereo4 ADC MIXR" }, 3553 3554 { "Mono ADC MIXL", "ADC1 Switch", "Mono ADC1 L Mux" }, 3555 { "Mono ADC MIXL", "ADC2 Switch", "Mono ADC2 L Mux" }, 3556 { "Mono ADC MIXL", NULL, "adc mono left filter" }, 3557 { "adc mono left filter", NULL, "PLL1", is_sys_clk_from_pll }, 3558 3559 { "Mono ADC MIXR", "ADC1 Switch", "Mono ADC1 R Mux" }, 3560 { "Mono ADC MIXR", "ADC2 Switch", "Mono ADC2 R Mux" }, 3561 { "Mono ADC MIXR", NULL, "adc mono right filter" }, 3562 { "adc mono right filter", NULL, "PLL1", is_sys_clk_from_pll }, 3563 3564 { "Mono ADC MIX", NULL, "Mono ADC MIXL" }, 3565 { "Mono ADC MIX", NULL, "Mono ADC MIXR" }, 3566 3567 { "VAD ADC Mux", "STO1 ADC MIX L", "Stereo1 ADC MIXL" }, 3568 { "VAD ADC Mux", "MONO ADC MIX L", "Mono ADC MIXL" }, 3569 { "VAD ADC Mux", "MONO ADC MIX R", "Mono ADC MIXR" }, 3570 { "VAD ADC Mux", "STO2 ADC MIX L", "Stereo2 ADC MIXL" }, 3571 { "VAD ADC Mux", "STO3 ADC MIX L", "Stereo3 ADC MIXL" }, 3572 3573 { "IF1 ADC1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" }, 3574 { "IF1 ADC1 Mux", "OB01", "OB01 Bypass Mux" }, 3575 { "IF1 ADC1 Mux", "VAD ADC", "VAD ADC Mux" }, 3576 3577 { "IF1 ADC2 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" }, 3578 { "IF1 ADC2 Mux", "OB23", "OB23 Bypass Mux" }, 3579 3580 { "IF1 ADC3 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" }, 3581 { "IF1 ADC3 Mux", "MONO ADC MIX", "Mono ADC MIX" }, 3582 { "IF1 ADC3 Mux", "OB45", "OB45" }, 3583 3584 { "IF1 ADC4 Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" }, 3585 { "IF1 ADC4 Mux", "OB67", "OB67" }, 3586 { "IF1 ADC4 Mux", "OB01", "OB01 Bypass Mux" }, 3587 3588 { "IF1 ADC1 Swap Mux", "L/R", "IF1 ADC1 Mux" }, 3589 { "IF1 ADC1 Swap Mux", "R/L", "IF1 ADC1 Mux" }, 3590 { "IF1 ADC1 Swap Mux", "L/L", "IF1 ADC1 Mux" }, 3591 { "IF1 ADC1 Swap Mux", "R/R", "IF1 ADC1 Mux" }, 3592 3593 { "IF1 ADC2 Swap Mux", "L/R", "IF1 ADC2 Mux" }, 3594 { "IF1 ADC2 Swap Mux", "R/L", "IF1 ADC2 Mux" }, 3595 { "IF1 ADC2 Swap Mux", "L/L", "IF1 ADC2 Mux" }, 3596 { "IF1 ADC2 Swap Mux", "R/R", "IF1 ADC2 Mux" }, 3597 3598 { "IF1 ADC3 Swap Mux", "L/R", "IF1 ADC3 Mux" }, 3599 { "IF1 ADC3 Swap Mux", "R/L", "IF1 ADC3 Mux" }, 3600 { "IF1 ADC3 Swap Mux", "L/L", "IF1 ADC3 Mux" }, 3601 { "IF1 ADC3 Swap Mux", "R/R", "IF1 ADC3 Mux" }, 3602 3603 { "IF1 ADC4 Swap Mux", "L/R", "IF1 ADC4 Mux" }, 3604 { "IF1 ADC4 Swap Mux", "R/L", "IF1 ADC4 Mux" }, 3605 { "IF1 ADC4 Swap Mux", "L/L", "IF1 ADC4 Mux" }, 3606 { "IF1 ADC4 Swap Mux", "R/R", "IF1 ADC4 Mux" }, 3607 3608 { "IF1 ADC", NULL, "IF1 ADC1 Swap Mux" }, 3609 { "IF1 ADC", NULL, "IF1 ADC2 Swap Mux" }, 3610 { "IF1 ADC", NULL, "IF1 ADC3 Swap Mux" }, 3611 { "IF1 ADC", NULL, "IF1 ADC4 Swap Mux" }, 3612 3613 { "IF1 ADC TDM Swap Mux", "1/2/3/4", "IF1 ADC" }, 3614 { "IF1 ADC TDM Swap Mux", "2/1/3/4", "IF1 ADC" }, 3615 { "IF1 ADC TDM Swap Mux", "2/3/1/4", "IF1 ADC" }, 3616 { "IF1 ADC TDM Swap Mux", "4/1/2/3", "IF1 ADC" }, 3617 { "IF1 ADC TDM Swap Mux", "1/3/2/4", "IF1 ADC" }, 3618 { "IF1 ADC TDM Swap Mux", "1/4/2/3", "IF1 ADC" }, 3619 { "IF1 ADC TDM Swap Mux", "3/1/2/4", "IF1 ADC" }, 3620 { "IF1 ADC TDM Swap Mux", "3/4/1/2", "IF1 ADC" }, 3621 3622 { "AIF1TX", NULL, "I2S1" }, 3623 { "AIF1TX", NULL, "IF1 ADC TDM Swap Mux" }, 3624 3625 { "IF2 ADC1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" }, 3626 { "IF2 ADC1 Mux", "OB01", "OB01 Bypass Mux" }, 3627 { "IF2 ADC1 Mux", "VAD ADC", "VAD ADC Mux" }, 3628 3629 { "IF2 ADC2 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" }, 3630 { "IF2 ADC2 Mux", "OB23", "OB23 Bypass Mux" }, 3631 3632 { "IF2 ADC3 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" }, 3633 { "IF2 ADC3 Mux", "MONO ADC MIX", "Mono ADC MIX" }, 3634 { "IF2 ADC3 Mux", "OB45", "OB45" }, 3635 3636 { "IF2 ADC4 Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" }, 3637 { "IF2 ADC4 Mux", "OB67", "OB67" }, 3638 { "IF2 ADC4 Mux", "OB01", "OB01 Bypass Mux" }, 3639 3640 { "IF2 ADC1 Swap Mux", "L/R", "IF2 ADC1 Mux" }, 3641 { "IF2 ADC1 Swap Mux", "R/L", "IF2 ADC1 Mux" }, 3642 { "IF2 ADC1 Swap Mux", "L/L", "IF2 ADC1 Mux" }, 3643 { "IF2 ADC1 Swap Mux", "R/R", "IF2 ADC1 Mux" }, 3644 3645 { "IF2 ADC2 Swap Mux", "L/R", "IF2 ADC2 Mux" }, 3646 { "IF2 ADC2 Swap Mux", "R/L", "IF2 ADC2 Mux" }, 3647 { "IF2 ADC2 Swap Mux", "L/L", "IF2 ADC2 Mux" }, 3648 { "IF2 ADC2 Swap Mux", "R/R", "IF2 ADC2 Mux" }, 3649 3650 { "IF2 ADC3 Swap Mux", "L/R", "IF2 ADC3 Mux" }, 3651 { "IF2 ADC3 Swap Mux", "R/L", "IF2 ADC3 Mux" }, 3652 { "IF2 ADC3 Swap Mux", "L/L", "IF2 ADC3 Mux" }, 3653 { "IF2 ADC3 Swap Mux", "R/R", "IF2 ADC3 Mux" }, 3654 3655 { "IF2 ADC4 Swap Mux", "L/R", "IF2 ADC4 Mux" }, 3656 { "IF2 ADC4 Swap Mux", "R/L", "IF2 ADC4 Mux" }, 3657 { "IF2 ADC4 Swap Mux", "L/L", "IF2 ADC4 Mux" }, 3658 { "IF2 ADC4 Swap Mux", "R/R", "IF2 ADC4 Mux" }, 3659 3660 { "IF2 ADC", NULL, "IF2 ADC1 Swap Mux" }, 3661 { "IF2 ADC", NULL, "IF2 ADC2 Swap Mux" }, 3662 { "IF2 ADC", NULL, "IF2 ADC3 Swap Mux" }, 3663 { "IF2 ADC", NULL, "IF2 ADC4 Swap Mux" }, 3664 3665 { "IF2 ADC TDM Swap Mux", "1/2/3/4", "IF2 ADC" }, 3666 { "IF2 ADC TDM Swap Mux", "2/1/3/4", "IF2 ADC" }, 3667 { "IF2 ADC TDM Swap Mux", "3/1/2/4", "IF2 ADC" }, 3668 { "IF2 ADC TDM Swap Mux", "4/1/2/3", "IF2 ADC" }, 3669 { "IF2 ADC TDM Swap Mux", "1/3/2/4", "IF2 ADC" }, 3670 { "IF2 ADC TDM Swap Mux", "1/4/2/3", "IF2 ADC" }, 3671 { "IF2 ADC TDM Swap Mux", "2/3/1/4", "IF2 ADC" }, 3672 { "IF2 ADC TDM Swap Mux", "3/4/1/2", "IF2 ADC" }, 3673 3674 { "AIF2TX", NULL, "I2S2" }, 3675 { "AIF2TX", NULL, "IF2 ADC TDM Swap Mux" }, 3676 3677 { "IF3 ADC Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" }, 3678 { "IF3 ADC Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" }, 3679 { "IF3 ADC Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" }, 3680 { "IF3 ADC Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" }, 3681 { "IF3 ADC Mux", "MONO ADC MIX", "Mono ADC MIX" }, 3682 { "IF3 ADC Mux", "OB01", "OB01 Bypass Mux" }, 3683 { "IF3 ADC Mux", "OB23", "OB23 Bypass Mux" }, 3684 { "IF3 ADC Mux", "VAD ADC", "VAD ADC Mux" }, 3685 3686 { "AIF3TX", NULL, "I2S3" }, 3687 { "AIF3TX", NULL, "IF3 ADC Mux" }, 3688 3689 { "IF4 ADC Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" }, 3690 { "IF4 ADC Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" }, 3691 { "IF4 ADC Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" }, 3692 { "IF4 ADC Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" }, 3693 { "IF4 ADC Mux", "MONO ADC MIX", "Mono ADC MIX" }, 3694 { "IF4 ADC Mux", "OB01", "OB01 Bypass Mux" }, 3695 { "IF4 ADC Mux", "OB23", "OB23 Bypass Mux" }, 3696 { "IF4 ADC Mux", "VAD ADC", "VAD ADC Mux" }, 3697 3698 { "AIF4TX", NULL, "I2S4" }, 3699 { "AIF4TX", NULL, "IF4 ADC Mux" }, 3700 3701 { "SLB ADC1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" }, 3702 { "SLB ADC1 Mux", "OB01", "OB01 Bypass Mux" }, 3703 { "SLB ADC1 Mux", "VAD ADC", "VAD ADC Mux" }, 3704 3705 { "SLB ADC2 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" }, 3706 { "SLB ADC2 Mux", "OB23", "OB23 Bypass Mux" }, 3707 3708 { "SLB ADC3 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" }, 3709 { "SLB ADC3 Mux", "MONO ADC MIX", "Mono ADC MIX" }, 3710 { "SLB ADC3 Mux", "OB45", "OB45" }, 3711 3712 { "SLB ADC4 Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" }, 3713 { "SLB ADC4 Mux", "OB67", "OB67" }, 3714 { "SLB ADC4 Mux", "OB01", "OB01 Bypass Mux" }, 3715 3716 { "SLBTX", NULL, "SLB" }, 3717 { "SLBTX", NULL, "SLB ADC1 Mux" }, 3718 { "SLBTX", NULL, "SLB ADC2 Mux" }, 3719 { "SLBTX", NULL, "SLB ADC3 Mux" }, 3720 { "SLBTX", NULL, "SLB ADC4 Mux" }, 3721 3722 { "DSPTX", NULL, "IB01 Bypass Mux" }, 3723 3724 { "IB01 Mux", "IF1 DAC 01", "IF1 DAC01" }, 3725 { "IB01 Mux", "IF2 DAC 01", "IF2 DAC01" }, 3726 { "IB01 Mux", "SLB DAC 01", "SLB DAC01" }, 3727 { "IB01 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" }, 3728 /* The IB01 Mux controls the source for InBound0 and InBound1. 3729 * When the mux option "VAD ADC/DAC1 FS" is selected, "VAD ADC" goes to 3730 * InBound0 and "DAC1 FS" goes to InBound1. "VAD ADC" is used for 3731 * hotwording. "DAC1 FS" is not used currently. 3732 * 3733 * Creating a common widget node for "VAD ADC" + "DAC1 FS" and 3734 * connecting the common widget to IB01 Mux causes the issue where 3735 * there is an active path going from system playback -> "DAC1 FS" -> 3736 * IB01 Mux -> DSP Buffer -> hotword stream. This wrong path confuses 3737 * DAPM. Therefore "DAC1 FS" is ignored for now. 3738 */ 3739 { "IB01 Mux", "VAD ADC/DAC1 FS", "VAD ADC Mux" }, 3740 3741 { "IB01 Bypass Mux", "Bypass", "IB01 Mux" }, 3742 { "IB01 Bypass Mux", "Pass SRC", "IB01 Mux" }, 3743 3744 { "IB23 Mux", "IF1 DAC 23", "IF1 DAC23" }, 3745 { "IB23 Mux", "IF2 DAC 23", "IF2 DAC23" }, 3746 { "IB23 Mux", "SLB DAC 23", "SLB DAC23" }, 3747 { "IB23 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" }, 3748 { "IB23 Mux", "DAC1 FS", "DAC1 FS" }, 3749 { "IB23 Mux", "IF4 DAC", "IF4 DAC" }, 3750 3751 { "IB23 Bypass Mux", "Bypass", "IB23 Mux" }, 3752 { "IB23 Bypass Mux", "Pass SRC", "IB23 Mux" }, 3753 3754 { "IB45 Mux", "IF1 DAC 45", "IF1 DAC45" }, 3755 { "IB45 Mux", "IF2 DAC 45", "IF2 DAC45" }, 3756 { "IB45 Mux", "SLB DAC 45", "SLB DAC45" }, 3757 { "IB45 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" }, 3758 { "IB45 Mux", "IF3 DAC", "IF3 DAC" }, 3759 3760 { "IB45 Bypass Mux", "Bypass", "IB45 Mux" }, 3761 { "IB45 Bypass Mux", "Pass SRC", "IB45 Mux" }, 3762 3763 { "IB6 Mux", "IF1 DAC 6", "IF1 DAC6 Mux" }, 3764 { "IB6 Mux", "IF2 DAC 6", "IF2 DAC6 Mux" }, 3765 { "IB6 Mux", "SLB DAC 6", "SLB DAC6" }, 3766 { "IB6 Mux", "STO4 ADC MIX L", "Stereo4 ADC MIXL" }, 3767 { "IB6 Mux", "IF4 DAC L", "IF4 DAC L" }, 3768 { "IB6 Mux", "STO1 ADC MIX L", "Stereo1 ADC MIXL" }, 3769 { "IB6 Mux", "STO2 ADC MIX L", "Stereo2 ADC MIXL" }, 3770 { "IB6 Mux", "STO3 ADC MIX L", "Stereo3 ADC MIXL" }, 3771 3772 { "IB7 Mux", "IF1 DAC 7", "IF1 DAC7 Mux" }, 3773 { "IB7 Mux", "IF2 DAC 7", "IF2 DAC7 Mux" }, 3774 { "IB7 Mux", "SLB DAC 7", "SLB DAC7" }, 3775 { "IB7 Mux", "STO4 ADC MIX R", "Stereo4 ADC MIXR" }, 3776 { "IB7 Mux", "IF4 DAC R", "IF4 DAC R" }, 3777 { "IB7 Mux", "STO1 ADC MIX R", "Stereo1 ADC MIXR" }, 3778 { "IB7 Mux", "STO2 ADC MIX R", "Stereo2 ADC MIXR" }, 3779 { "IB7 Mux", "STO3 ADC MIX R", "Stereo3 ADC MIXR" }, 3780 3781 { "IB8 Mux", "STO1 ADC MIX L", "Stereo1 ADC MIXL" }, 3782 { "IB8 Mux", "STO2 ADC MIX L", "Stereo2 ADC MIXL" }, 3783 { "IB8 Mux", "STO3 ADC MIX L", "Stereo3 ADC MIXL" }, 3784 { "IB8 Mux", "STO4 ADC MIX L", "Stereo4 ADC MIXL" }, 3785 { "IB8 Mux", "MONO ADC MIX L", "Mono ADC MIXL" }, 3786 { "IB8 Mux", "DACL1 FS", "DAC1 MIXL" }, 3787 3788 { "IB9 Mux", "STO1 ADC MIX R", "Stereo1 ADC MIXR" }, 3789 { "IB9 Mux", "STO2 ADC MIX R", "Stereo2 ADC MIXR" }, 3790 { "IB9 Mux", "STO3 ADC MIX R", "Stereo3 ADC MIXR" }, 3791 { "IB9 Mux", "STO4 ADC MIX R", "Stereo4 ADC MIXR" }, 3792 { "IB9 Mux", "MONO ADC MIX R", "Mono ADC MIXR" }, 3793 { "IB9 Mux", "DACR1 FS", "DAC1 MIXR" }, 3794 { "IB9 Mux", "DAC1 FS", "DAC1 FS" }, 3795 3796 { "OB01 MIX", "IB01 Switch", "IB01 Bypass Mux" }, 3797 { "OB01 MIX", "IB23 Switch", "IB23 Bypass Mux" }, 3798 { "OB01 MIX", "IB45 Switch", "IB45 Bypass Mux" }, 3799 { "OB01 MIX", "IB6 Switch", "IB6 Mux" }, 3800 { "OB01 MIX", "IB7 Switch", "IB7 Mux" }, 3801 { "OB01 MIX", "IB8 Switch", "IB8 Mux" }, 3802 { "OB01 MIX", "IB9 Switch", "IB9 Mux" }, 3803 3804 { "OB23 MIX", "IB01 Switch", "IB01 Bypass Mux" }, 3805 { "OB23 MIX", "IB23 Switch", "IB23 Bypass Mux" }, 3806 { "OB23 MIX", "IB45 Switch", "IB45 Bypass Mux" }, 3807 { "OB23 MIX", "IB6 Switch", "IB6 Mux" }, 3808 { "OB23 MIX", "IB7 Switch", "IB7 Mux" }, 3809 { "OB23 MIX", "IB8 Switch", "IB8 Mux" }, 3810 { "OB23 MIX", "IB9 Switch", "IB9 Mux" }, 3811 3812 { "OB4 MIX", "IB01 Switch", "IB01 Bypass Mux" }, 3813 { "OB4 MIX", "IB23 Switch", "IB23 Bypass Mux" }, 3814 { "OB4 MIX", "IB45 Switch", "IB45 Bypass Mux" }, 3815 { "OB4 MIX", "IB6 Switch", "IB6 Mux" }, 3816 { "OB4 MIX", "IB7 Switch", "IB7 Mux" }, 3817 { "OB4 MIX", "IB8 Switch", "IB8 Mux" }, 3818 { "OB4 MIX", "IB9 Switch", "IB9 Mux" }, 3819 3820 { "OB5 MIX", "IB01 Switch", "IB01 Bypass Mux" }, 3821 { "OB5 MIX", "IB23 Switch", "IB23 Bypass Mux" }, 3822 { "OB5 MIX", "IB45 Switch", "IB45 Bypass Mux" }, 3823 { "OB5 MIX", "IB6 Switch", "IB6 Mux" }, 3824 { "OB5 MIX", "IB7 Switch", "IB7 Mux" }, 3825 { "OB5 MIX", "IB8 Switch", "IB8 Mux" }, 3826 { "OB5 MIX", "IB9 Switch", "IB9 Mux" }, 3827 3828 { "OB6 MIX", "IB01 Switch", "IB01 Bypass Mux" }, 3829 { "OB6 MIX", "IB23 Switch", "IB23 Bypass Mux" }, 3830 { "OB6 MIX", "IB45 Switch", "IB45 Bypass Mux" }, 3831 { "OB6 MIX", "IB6 Switch", "IB6 Mux" }, 3832 { "OB6 MIX", "IB7 Switch", "IB7 Mux" }, 3833 { "OB6 MIX", "IB8 Switch", "IB8 Mux" }, 3834 { "OB6 MIX", "IB9 Switch", "IB9 Mux" }, 3835 3836 { "OB7 MIX", "IB01 Switch", "IB01 Bypass Mux" }, 3837 { "OB7 MIX", "IB23 Switch", "IB23 Bypass Mux" }, 3838 { "OB7 MIX", "IB45 Switch", "IB45 Bypass Mux" }, 3839 { "OB7 MIX", "IB6 Switch", "IB6 Mux" }, 3840 { "OB7 MIX", "IB7 Switch", "IB7 Mux" }, 3841 { "OB7 MIX", "IB8 Switch", "IB8 Mux" }, 3842 { "OB7 MIX", "IB9 Switch", "IB9 Mux" }, 3843 3844 { "OB01 Bypass Mux", "Bypass", "OB01 MIX" }, 3845 { "OB01 Bypass Mux", "Pass SRC", "OB01 MIX" }, 3846 { "OB23 Bypass Mux", "Bypass", "OB23 MIX" }, 3847 { "OB23 Bypass Mux", "Pass SRC", "OB23 MIX" }, 3848 3849 { "OutBound2", NULL, "OB23 Bypass Mux" }, 3850 { "OutBound3", NULL, "OB23 Bypass Mux" }, 3851 { "OutBound4", NULL, "OB4 MIX" }, 3852 { "OutBound5", NULL, "OB5 MIX" }, 3853 { "OutBound6", NULL, "OB6 MIX" }, 3854 { "OutBound7", NULL, "OB7 MIX" }, 3855 3856 { "OB45", NULL, "OutBound4" }, 3857 { "OB45", NULL, "OutBound5" }, 3858 { "OB67", NULL, "OutBound6" }, 3859 { "OB67", NULL, "OutBound7" }, 3860 3861 { "IF1 DAC0", NULL, "AIF1RX" }, 3862 { "IF1 DAC1", NULL, "AIF1RX" }, 3863 { "IF1 DAC2", NULL, "AIF1RX" }, 3864 { "IF1 DAC3", NULL, "AIF1RX" }, 3865 { "IF1 DAC4", NULL, "AIF1RX" }, 3866 { "IF1 DAC5", NULL, "AIF1RX" }, 3867 { "IF1 DAC6", NULL, "AIF1RX" }, 3868 { "IF1 DAC7", NULL, "AIF1RX" }, 3869 { "IF1 DAC0", NULL, "I2S1" }, 3870 { "IF1 DAC1", NULL, "I2S1" }, 3871 { "IF1 DAC2", NULL, "I2S1" }, 3872 { "IF1 DAC3", NULL, "I2S1" }, 3873 { "IF1 DAC4", NULL, "I2S1" }, 3874 { "IF1 DAC5", NULL, "I2S1" }, 3875 { "IF1 DAC6", NULL, "I2S1" }, 3876 { "IF1 DAC7", NULL, "I2S1" }, 3877 3878 { "IF1 DAC0 Mux", "Slot0", "IF1 DAC0" }, 3879 { "IF1 DAC0 Mux", "Slot1", "IF1 DAC1" }, 3880 { "IF1 DAC0 Mux", "Slot2", "IF1 DAC2" }, 3881 { "IF1 DAC0 Mux", "Slot3", "IF1 DAC3" }, 3882 { "IF1 DAC0 Mux", "Slot4", "IF1 DAC4" }, 3883 { "IF1 DAC0 Mux", "Slot5", "IF1 DAC5" }, 3884 { "IF1 DAC0 Mux", "Slot6", "IF1 DAC6" }, 3885 { "IF1 DAC0 Mux", "Slot7", "IF1 DAC7" }, 3886 3887 { "IF1 DAC1 Mux", "Slot0", "IF1 DAC0" }, 3888 { "IF1 DAC1 Mux", "Slot1", "IF1 DAC1" }, 3889 { "IF1 DAC1 Mux", "Slot2", "IF1 DAC2" }, 3890 { "IF1 DAC1 Mux", "Slot3", "IF1 DAC3" }, 3891 { "IF1 DAC1 Mux", "Slot4", "IF1 DAC4" }, 3892 { "IF1 DAC1 Mux", "Slot5", "IF1 DAC5" }, 3893 { "IF1 DAC1 Mux", "Slot6", "IF1 DAC6" }, 3894 { "IF1 DAC1 Mux", "Slot7", "IF1 DAC7" }, 3895 3896 { "IF1 DAC2 Mux", "Slot0", "IF1 DAC0" }, 3897 { "IF1 DAC2 Mux", "Slot1", "IF1 DAC1" }, 3898 { "IF1 DAC2 Mux", "Slot2", "IF1 DAC2" }, 3899 { "IF1 DAC2 Mux", "Slot3", "IF1 DAC3" }, 3900 { "IF1 DAC2 Mux", "Slot4", "IF1 DAC4" }, 3901 { "IF1 DAC2 Mux", "Slot5", "IF1 DAC5" }, 3902 { "IF1 DAC2 Mux", "Slot6", "IF1 DAC6" }, 3903 { "IF1 DAC2 Mux", "Slot7", "IF1 DAC7" }, 3904 3905 { "IF1 DAC3 Mux", "Slot0", "IF1 DAC0" }, 3906 { "IF1 DAC3 Mux", "Slot1", "IF1 DAC1" }, 3907 { "IF1 DAC3 Mux", "Slot2", "IF1 DAC2" }, 3908 { "IF1 DAC3 Mux", "Slot3", "IF1 DAC3" }, 3909 { "IF1 DAC3 Mux", "Slot4", "IF1 DAC4" }, 3910 { "IF1 DAC3 Mux", "Slot5", "IF1 DAC5" }, 3911 { "IF1 DAC3 Mux", "Slot6", "IF1 DAC6" }, 3912 { "IF1 DAC3 Mux", "Slot7", "IF1 DAC7" }, 3913 3914 { "IF1 DAC4 Mux", "Slot0", "IF1 DAC0" }, 3915 { "IF1 DAC4 Mux", "Slot1", "IF1 DAC1" }, 3916 { "IF1 DAC4 Mux", "Slot2", "IF1 DAC2" }, 3917 { "IF1 DAC4 Mux", "Slot3", "IF1 DAC3" }, 3918 { "IF1 DAC4 Mux", "Slot4", "IF1 DAC4" }, 3919 { "IF1 DAC4 Mux", "Slot5", "IF1 DAC5" }, 3920 { "IF1 DAC4 Mux", "Slot6", "IF1 DAC6" }, 3921 { "IF1 DAC4 Mux", "Slot7", "IF1 DAC7" }, 3922 3923 { "IF1 DAC5 Mux", "Slot0", "IF1 DAC0" }, 3924 { "IF1 DAC5 Mux", "Slot1", "IF1 DAC1" }, 3925 { "IF1 DAC5 Mux", "Slot2", "IF1 DAC2" }, 3926 { "IF1 DAC5 Mux", "Slot3", "IF1 DAC3" }, 3927 { "IF1 DAC5 Mux", "Slot4", "IF1 DAC4" }, 3928 { "IF1 DAC5 Mux", "Slot5", "IF1 DAC5" }, 3929 { "IF1 DAC5 Mux", "Slot6", "IF1 DAC6" }, 3930 { "IF1 DAC5 Mux", "Slot7", "IF1 DAC7" }, 3931 3932 { "IF1 DAC6 Mux", "Slot0", "IF1 DAC0" }, 3933 { "IF1 DAC6 Mux", "Slot1", "IF1 DAC1" }, 3934 { "IF1 DAC6 Mux", "Slot2", "IF1 DAC2" }, 3935 { "IF1 DAC6 Mux", "Slot3", "IF1 DAC3" }, 3936 { "IF1 DAC6 Mux", "Slot4", "IF1 DAC4" }, 3937 { "IF1 DAC6 Mux", "Slot5", "IF1 DAC5" }, 3938 { "IF1 DAC6 Mux", "Slot6", "IF1 DAC6" }, 3939 { "IF1 DAC6 Mux", "Slot7", "IF1 DAC7" }, 3940 3941 { "IF1 DAC7 Mux", "Slot0", "IF1 DAC0" }, 3942 { "IF1 DAC7 Mux", "Slot1", "IF1 DAC1" }, 3943 { "IF1 DAC7 Mux", "Slot2", "IF1 DAC2" }, 3944 { "IF1 DAC7 Mux", "Slot3", "IF1 DAC3" }, 3945 { "IF1 DAC7 Mux", "Slot4", "IF1 DAC4" }, 3946 { "IF1 DAC7 Mux", "Slot5", "IF1 DAC5" }, 3947 { "IF1 DAC7 Mux", "Slot6", "IF1 DAC6" }, 3948 { "IF1 DAC7 Mux", "Slot7", "IF1 DAC7" }, 3949 3950 { "IF1 DAC01", NULL, "IF1 DAC0 Mux" }, 3951 { "IF1 DAC01", NULL, "IF1 DAC1 Mux" }, 3952 { "IF1 DAC23", NULL, "IF1 DAC2 Mux" }, 3953 { "IF1 DAC23", NULL, "IF1 DAC3 Mux" }, 3954 { "IF1 DAC45", NULL, "IF1 DAC4 Mux" }, 3955 { "IF1 DAC45", NULL, "IF1 DAC5 Mux" }, 3956 { "IF1 DAC67", NULL, "IF1 DAC6 Mux" }, 3957 { "IF1 DAC67", NULL, "IF1 DAC7 Mux" }, 3958 3959 { "IF2 DAC0", NULL, "AIF2RX" }, 3960 { "IF2 DAC1", NULL, "AIF2RX" }, 3961 { "IF2 DAC2", NULL, "AIF2RX" }, 3962 { "IF2 DAC3", NULL, "AIF2RX" }, 3963 { "IF2 DAC4", NULL, "AIF2RX" }, 3964 { "IF2 DAC5", NULL, "AIF2RX" }, 3965 { "IF2 DAC6", NULL, "AIF2RX" }, 3966 { "IF2 DAC7", NULL, "AIF2RX" }, 3967 { "IF2 DAC0", NULL, "I2S2" }, 3968 { "IF2 DAC1", NULL, "I2S2" }, 3969 { "IF2 DAC2", NULL, "I2S2" }, 3970 { "IF2 DAC3", NULL, "I2S2" }, 3971 { "IF2 DAC4", NULL, "I2S2" }, 3972 { "IF2 DAC5", NULL, "I2S2" }, 3973 { "IF2 DAC6", NULL, "I2S2" }, 3974 { "IF2 DAC7", NULL, "I2S2" }, 3975 3976 { "IF2 DAC0 Mux", "Slot0", "IF2 DAC0" }, 3977 { "IF2 DAC0 Mux", "Slot1", "IF2 DAC1" }, 3978 { "IF2 DAC0 Mux", "Slot2", "IF2 DAC2" }, 3979 { "IF2 DAC0 Mux", "Slot3", "IF2 DAC3" }, 3980 { "IF2 DAC0 Mux", "Slot4", "IF2 DAC4" }, 3981 { "IF2 DAC0 Mux", "Slot5", "IF2 DAC5" }, 3982 { "IF2 DAC0 Mux", "Slot6", "IF2 DAC6" }, 3983 { "IF2 DAC0 Mux", "Slot7", "IF2 DAC7" }, 3984 3985 { "IF2 DAC1 Mux", "Slot0", "IF2 DAC0" }, 3986 { "IF2 DAC1 Mux", "Slot1", "IF2 DAC1" }, 3987 { "IF2 DAC1 Mux", "Slot2", "IF2 DAC2" }, 3988 { "IF2 DAC1 Mux", "Slot3", "IF2 DAC3" }, 3989 { "IF2 DAC1 Mux", "Slot4", "IF2 DAC4" }, 3990 { "IF2 DAC1 Mux", "Slot5", "IF2 DAC5" }, 3991 { "IF2 DAC1 Mux", "Slot6", "IF2 DAC6" }, 3992 { "IF2 DAC1 Mux", "Slot7", "IF2 DAC7" }, 3993 3994 { "IF2 DAC2 Mux", "Slot0", "IF2 DAC0" }, 3995 { "IF2 DAC2 Mux", "Slot1", "IF2 DAC1" }, 3996 { "IF2 DAC2 Mux", "Slot2", "IF2 DAC2" }, 3997 { "IF2 DAC2 Mux", "Slot3", "IF2 DAC3" }, 3998 { "IF2 DAC2 Mux", "Slot4", "IF2 DAC4" }, 3999 { "IF2 DAC2 Mux", "Slot5", "IF2 DAC5" }, 4000 { "IF2 DAC2 Mux", "Slot6", "IF2 DAC6" }, 4001 { "IF2 DAC2 Mux", "Slot7", "IF2 DAC7" }, 4002 4003 { "IF2 DAC3 Mux", "Slot0", "IF2 DAC0" }, 4004 { "IF2 DAC3 Mux", "Slot1", "IF2 DAC1" }, 4005 { "IF2 DAC3 Mux", "Slot2", "IF2 DAC2" }, 4006 { "IF2 DAC3 Mux", "Slot3", "IF2 DAC3" }, 4007 { "IF2 DAC3 Mux", "Slot4", "IF2 DAC4" }, 4008 { "IF2 DAC3 Mux", "Slot5", "IF2 DAC5" }, 4009 { "IF2 DAC3 Mux", "Slot6", "IF2 DAC6" }, 4010 { "IF2 DAC3 Mux", "Slot7", "IF2 DAC7" }, 4011 4012 { "IF2 DAC4 Mux", "Slot0", "IF2 DAC0" }, 4013 { "IF2 DAC4 Mux", "Slot1", "IF2 DAC1" }, 4014 { "IF2 DAC4 Mux", "Slot2", "IF2 DAC2" }, 4015 { "IF2 DAC4 Mux", "Slot3", "IF2 DAC3" }, 4016 { "IF2 DAC4 Mux", "Slot4", "IF2 DAC4" }, 4017 { "IF2 DAC4 Mux", "Slot5", "IF2 DAC5" }, 4018 { "IF2 DAC4 Mux", "Slot6", "IF2 DAC6" }, 4019 { "IF2 DAC4 Mux", "Slot7", "IF2 DAC7" }, 4020 4021 { "IF2 DAC5 Mux", "Slot0", "IF2 DAC0" }, 4022 { "IF2 DAC5 Mux", "Slot1", "IF2 DAC1" }, 4023 { "IF2 DAC5 Mux", "Slot2", "IF2 DAC2" }, 4024 { "IF2 DAC5 Mux", "Slot3", "IF2 DAC3" }, 4025 { "IF2 DAC5 Mux", "Slot4", "IF2 DAC4" }, 4026 { "IF2 DAC5 Mux", "Slot5", "IF2 DAC5" }, 4027 { "IF2 DAC5 Mux", "Slot6", "IF2 DAC6" }, 4028 { "IF2 DAC5 Mux", "Slot7", "IF2 DAC7" }, 4029 4030 { "IF2 DAC6 Mux", "Slot0", "IF2 DAC0" }, 4031 { "IF2 DAC6 Mux", "Slot1", "IF2 DAC1" }, 4032 { "IF2 DAC6 Mux", "Slot2", "IF2 DAC2" }, 4033 { "IF2 DAC6 Mux", "Slot3", "IF2 DAC3" }, 4034 { "IF2 DAC6 Mux", "Slot4", "IF2 DAC4" }, 4035 { "IF2 DAC6 Mux", "Slot5", "IF2 DAC5" }, 4036 { "IF2 DAC6 Mux", "Slot6", "IF2 DAC6" }, 4037 { "IF2 DAC6 Mux", "Slot7", "IF2 DAC7" }, 4038 4039 { "IF2 DAC7 Mux", "Slot0", "IF2 DAC0" }, 4040 { "IF2 DAC7 Mux", "Slot1", "IF2 DAC1" }, 4041 { "IF2 DAC7 Mux", "Slot2", "IF2 DAC2" }, 4042 { "IF2 DAC7 Mux", "Slot3", "IF2 DAC3" }, 4043 { "IF2 DAC7 Mux", "Slot4", "IF2 DAC4" }, 4044 { "IF2 DAC7 Mux", "Slot5", "IF2 DAC5" }, 4045 { "IF2 DAC7 Mux", "Slot6", "IF2 DAC6" }, 4046 { "IF2 DAC7 Mux", "Slot7", "IF2 DAC7" }, 4047 4048 { "IF2 DAC01", NULL, "IF2 DAC0 Mux" }, 4049 { "IF2 DAC01", NULL, "IF2 DAC1 Mux" }, 4050 { "IF2 DAC23", NULL, "IF2 DAC2 Mux" }, 4051 { "IF2 DAC23", NULL, "IF2 DAC3 Mux" }, 4052 { "IF2 DAC45", NULL, "IF2 DAC4 Mux" }, 4053 { "IF2 DAC45", NULL, "IF2 DAC5 Mux" }, 4054 { "IF2 DAC67", NULL, "IF2 DAC6 Mux" }, 4055 { "IF2 DAC67", NULL, "IF2 DAC7 Mux" }, 4056 4057 { "IF3 DAC", NULL, "AIF3RX" }, 4058 { "IF3 DAC", NULL, "I2S3" }, 4059 4060 { "IF4 DAC", NULL, "AIF4RX" }, 4061 { "IF4 DAC", NULL, "I2S4" }, 4062 4063 { "IF3 DAC L", NULL, "IF3 DAC" }, 4064 { "IF3 DAC R", NULL, "IF3 DAC" }, 4065 4066 { "IF4 DAC L", NULL, "IF4 DAC" }, 4067 { "IF4 DAC R", NULL, "IF4 DAC" }, 4068 4069 { "SLB DAC0", NULL, "SLBRX" }, 4070 { "SLB DAC1", NULL, "SLBRX" }, 4071 { "SLB DAC2", NULL, "SLBRX" }, 4072 { "SLB DAC3", NULL, "SLBRX" }, 4073 { "SLB DAC4", NULL, "SLBRX" }, 4074 { "SLB DAC5", NULL, "SLBRX" }, 4075 { "SLB DAC6", NULL, "SLBRX" }, 4076 { "SLB DAC7", NULL, "SLBRX" }, 4077 { "SLB DAC0", NULL, "SLB" }, 4078 { "SLB DAC1", NULL, "SLB" }, 4079 { "SLB DAC2", NULL, "SLB" }, 4080 { "SLB DAC3", NULL, "SLB" }, 4081 { "SLB DAC4", NULL, "SLB" }, 4082 { "SLB DAC5", NULL, "SLB" }, 4083 { "SLB DAC6", NULL, "SLB" }, 4084 { "SLB DAC7", NULL, "SLB" }, 4085 4086 { "SLB DAC01", NULL, "SLB DAC0" }, 4087 { "SLB DAC01", NULL, "SLB DAC1" }, 4088 { "SLB DAC23", NULL, "SLB DAC2" }, 4089 { "SLB DAC23", NULL, "SLB DAC3" }, 4090 { "SLB DAC45", NULL, "SLB DAC4" }, 4091 { "SLB DAC45", NULL, "SLB DAC5" }, 4092 { "SLB DAC67", NULL, "SLB DAC6" }, 4093 { "SLB DAC67", NULL, "SLB DAC7" }, 4094 4095 { "ADDA1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" }, 4096 { "ADDA1 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" }, 4097 { "ADDA1 Mux", "OB 67", "OB67" }, 4098 4099 { "DAC1 Mux", "IF1 DAC 01", "IF1 DAC01" }, 4100 { "DAC1 Mux", "IF2 DAC 01", "IF2 DAC01" }, 4101 { "DAC1 Mux", "IF3 DAC LR", "IF3 DAC" }, 4102 { "DAC1 Mux", "IF4 DAC LR", "IF4 DAC" }, 4103 { "DAC1 Mux", "SLB DAC 01", "SLB DAC01" }, 4104 { "DAC1 Mux", "OB 01", "OB01 Bypass Mux" }, 4105 4106 { "DAC1 MIXL", "Stereo ADC Switch", "ADDA1 Mux" }, 4107 { "DAC1 MIXL", "DAC1 Switch", "DAC1 Mux" }, 4108 { "DAC1 MIXR", "Stereo ADC Switch", "ADDA1 Mux" }, 4109 { "DAC1 MIXR", "DAC1 Switch", "DAC1 Mux" }, 4110 4111 { "DAC1 FS", NULL, "DAC1 MIXL" }, 4112 { "DAC1 FS", NULL, "DAC1 MIXR" }, 4113 4114 { "DAC2 L Mux", "IF1 DAC 2", "IF1 DAC2 Mux" }, 4115 { "DAC2 L Mux", "IF2 DAC 2", "IF2 DAC2 Mux" }, 4116 { "DAC2 L Mux", "IF3 DAC L", "IF3 DAC L" }, 4117 { "DAC2 L Mux", "IF4 DAC L", "IF4 DAC L" }, 4118 { "DAC2 L Mux", "SLB DAC 2", "SLB DAC2" }, 4119 { "DAC2 L Mux", "OB 2", "OutBound2" }, 4120 4121 { "DAC2 R Mux", "IF1 DAC 3", "IF1 DAC3 Mux" }, 4122 { "DAC2 R Mux", "IF2 DAC 3", "IF2 DAC3 Mux" }, 4123 { "DAC2 R Mux", "IF3 DAC R", "IF3 DAC R" }, 4124 { "DAC2 R Mux", "IF4 DAC R", "IF4 DAC R" }, 4125 { "DAC2 R Mux", "SLB DAC 3", "SLB DAC3" }, 4126 { "DAC2 R Mux", "OB 3", "OutBound3" }, 4127 { "DAC2 R Mux", "Haptic Generator", "Haptic Generator" }, 4128 { "DAC2 R Mux", "VAD ADC", "VAD ADC Mux" }, 4129 4130 { "DAC3 L Mux", "IF1 DAC 4", "IF1 DAC4 Mux" }, 4131 { "DAC3 L Mux", "IF2 DAC 4", "IF2 DAC4 Mux" }, 4132 { "DAC3 L Mux", "IF3 DAC L", "IF3 DAC L" }, 4133 { "DAC3 L Mux", "IF4 DAC L", "IF4 DAC L" }, 4134 { "DAC3 L Mux", "SLB DAC 4", "SLB DAC4" }, 4135 { "DAC3 L Mux", "OB 4", "OutBound4" }, 4136 4137 { "DAC3 R Mux", "IF1 DAC 5", "IF1 DAC5 Mux" }, 4138 { "DAC3 R Mux", "IF2 DAC 5", "IF2 DAC5 Mux" }, 4139 { "DAC3 R Mux", "IF3 DAC R", "IF3 DAC R" }, 4140 { "DAC3 R Mux", "IF4 DAC R", "IF4 DAC R" }, 4141 { "DAC3 R Mux", "SLB DAC 5", "SLB DAC5" }, 4142 { "DAC3 R Mux", "OB 5", "OutBound5" }, 4143 4144 { "DAC4 L Mux", "IF1 DAC 6", "IF1 DAC6 Mux" }, 4145 { "DAC4 L Mux", "IF2 DAC 6", "IF2 DAC6 Mux" }, 4146 { "DAC4 L Mux", "IF3 DAC L", "IF3 DAC L" }, 4147 { "DAC4 L Mux", "IF4 DAC L", "IF4 DAC L" }, 4148 { "DAC4 L Mux", "SLB DAC 6", "SLB DAC6" }, 4149 { "DAC4 L Mux", "OB 6", "OutBound6" }, 4150 4151 { "DAC4 R Mux", "IF1 DAC 7", "IF1 DAC7 Mux" }, 4152 { "DAC4 R Mux", "IF2 DAC 7", "IF2 DAC7 Mux" }, 4153 { "DAC4 R Mux", "IF3 DAC R", "IF3 DAC R" }, 4154 { "DAC4 R Mux", "IF4 DAC R", "IF4 DAC R" }, 4155 { "DAC4 R Mux", "SLB DAC 7", "SLB DAC7" }, 4156 { "DAC4 R Mux", "OB 7", "OutBound7" }, 4157 4158 { "Sidetone Mux", "DMIC1 L", "DMIC L1" }, 4159 { "Sidetone Mux", "DMIC2 L", "DMIC L2" }, 4160 { "Sidetone Mux", "DMIC3 L", "DMIC L3" }, 4161 { "Sidetone Mux", "DMIC4 L", "DMIC L4" }, 4162 { "Sidetone Mux", "ADC1", "ADC 1" }, 4163 { "Sidetone Mux", "ADC2", "ADC 2" }, 4164 { "Sidetone Mux", NULL, "Sidetone Power" }, 4165 4166 { "Stereo DAC MIXL", "ST L Switch", "Sidetone Mux" }, 4167 { "Stereo DAC MIXL", "DAC1 L Switch", "DAC1 MIXL" }, 4168 { "Stereo DAC MIXL", "DAC2 L Switch", "DAC2 L Mux" }, 4169 { "Stereo DAC MIXL", "DAC1 R Switch", "DAC1 MIXR" }, 4170 { "Stereo DAC MIXL", NULL, "dac stereo1 filter" }, 4171 { "Stereo DAC MIXR", "ST R Switch", "Sidetone Mux" }, 4172 { "Stereo DAC MIXR", "DAC1 R Switch", "DAC1 MIXR" }, 4173 { "Stereo DAC MIXR", "DAC2 R Switch", "DAC2 R Mux" }, 4174 { "Stereo DAC MIXR", "DAC1 L Switch", "DAC1 MIXL" }, 4175 { "Stereo DAC MIXR", NULL, "dac stereo1 filter" }, 4176 { "dac stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll }, 4177 4178 { "Mono DAC MIXL", "ST L Switch", "Sidetone Mux" }, 4179 { "Mono DAC MIXL", "DAC1 L Switch", "DAC1 MIXL" }, 4180 { "Mono DAC MIXL", "DAC2 L Switch", "DAC2 L Mux" }, 4181 { "Mono DAC MIXL", "DAC2 R Switch", "DAC2 R Mux" }, 4182 { "Mono DAC MIXL", NULL, "dac mono2 left filter" }, 4183 { "dac mono2 left filter", NULL, "PLL1", is_sys_clk_from_pll }, 4184 { "Mono DAC MIXR", "ST R Switch", "Sidetone Mux" }, 4185 { "Mono DAC MIXR", "DAC1 R Switch", "DAC1 MIXR" }, 4186 { "Mono DAC MIXR", "DAC2 R Switch", "DAC2 R Mux" }, 4187 { "Mono DAC MIXR", "DAC2 L Switch", "DAC2 L Mux" }, 4188 { "Mono DAC MIXR", NULL, "dac mono2 right filter" }, 4189 { "dac mono2 right filter", NULL, "PLL1", is_sys_clk_from_pll }, 4190 4191 { "DD1 MIXL", "Sto DAC Mix L Switch", "Stereo DAC MIXL" }, 4192 { "DD1 MIXL", "Mono DAC Mix L Switch", "Mono DAC MIXL" }, 4193 { "DD1 MIXL", "DAC3 L Switch", "DAC3 L Mux" }, 4194 { "DD1 MIXL", "DAC3 R Switch", "DAC3 R Mux" }, 4195 { "DD1 MIXL", NULL, "dac mono3 left filter" }, 4196 { "dac mono3 left filter", NULL, "PLL1", is_sys_clk_from_pll }, 4197 { "DD1 MIXR", "Sto DAC Mix R Switch", "Stereo DAC MIXR" }, 4198 { "DD1 MIXR", "Mono DAC Mix R Switch", "Mono DAC MIXR" }, 4199 { "DD1 MIXR", "DAC3 L Switch", "DAC3 L Mux" }, 4200 { "DD1 MIXR", "DAC3 R Switch", "DAC3 R Mux" }, 4201 { "DD1 MIXR", NULL, "dac mono3 right filter" }, 4202 { "dac mono3 right filter", NULL, "PLL1", is_sys_clk_from_pll }, 4203 4204 { "DD2 MIXL", "Sto DAC Mix L Switch", "Stereo DAC MIXL" }, 4205 { "DD2 MIXL", "Mono DAC Mix L Switch", "Mono DAC MIXL" }, 4206 { "DD2 MIXL", "DAC4 L Switch", "DAC4 L Mux" }, 4207 { "DD2 MIXL", "DAC4 R Switch", "DAC4 R Mux" }, 4208 { "DD2 MIXL", NULL, "dac mono4 left filter" }, 4209 { "dac mono4 left filter", NULL, "PLL1", is_sys_clk_from_pll }, 4210 { "DD2 MIXR", "Sto DAC Mix R Switch", "Stereo DAC MIXR" }, 4211 { "DD2 MIXR", "Mono DAC Mix R Switch", "Mono DAC MIXR" }, 4212 { "DD2 MIXR", "DAC4 L Switch", "DAC4 L Mux" }, 4213 { "DD2 MIXR", "DAC4 R Switch", "DAC4 R Mux" }, 4214 { "DD2 MIXR", NULL, "dac mono4 right filter" }, 4215 { "dac mono4 right filter", NULL, "PLL1", is_sys_clk_from_pll }, 4216 4217 { "Stereo DAC MIX", NULL, "Stereo DAC MIXL" }, 4218 { "Stereo DAC MIX", NULL, "Stereo DAC MIXR" }, 4219 { "Mono DAC MIX", NULL, "Mono DAC MIXL" }, 4220 { "Mono DAC MIX", NULL, "Mono DAC MIXR" }, 4221 { "DD1 MIX", NULL, "DD1 MIXL" }, 4222 { "DD1 MIX", NULL, "DD1 MIXR" }, 4223 { "DD2 MIX", NULL, "DD2 MIXL" }, 4224 { "DD2 MIX", NULL, "DD2 MIXR" }, 4225 4226 { "DAC12 SRC Mux", "STO1 DAC MIX", "Stereo DAC MIX" }, 4227 { "DAC12 SRC Mux", "MONO DAC MIX", "Mono DAC MIX" }, 4228 { "DAC12 SRC Mux", "DD MIX1", "DD1 MIX" }, 4229 { "DAC12 SRC Mux", "DD MIX2", "DD2 MIX" }, 4230 4231 { "DAC3 SRC Mux", "MONO DAC MIXL", "Mono DAC MIXL" }, 4232 { "DAC3 SRC Mux", "MONO DAC MIXR", "Mono DAC MIXR" }, 4233 { "DAC3 SRC Mux", "DD MIX1L", "DD1 MIXL" }, 4234 { "DAC3 SRC Mux", "DD MIX2L", "DD2 MIXL" }, 4235 4236 { "DAC 1", NULL, "DAC12 SRC Mux" }, 4237 { "DAC 2", NULL, "DAC12 SRC Mux" }, 4238 { "DAC 3", NULL, "DAC3 SRC Mux" }, 4239 4240 { "PDM1 L Mux", "STO1 DAC MIX", "Stereo DAC MIXL" }, 4241 { "PDM1 L Mux", "MONO DAC MIX", "Mono DAC MIXL" }, 4242 { "PDM1 L Mux", "DD MIX1", "DD1 MIXL" }, 4243 { "PDM1 L Mux", "DD MIX2", "DD2 MIXL" }, 4244 { "PDM1 L Mux", NULL, "PDM1 Power" }, 4245 { "PDM1 R Mux", "STO1 DAC MIX", "Stereo DAC MIXR" }, 4246 { "PDM1 R Mux", "MONO DAC MIX", "Mono DAC MIXR" }, 4247 { "PDM1 R Mux", "DD MIX1", "DD1 MIXR" }, 4248 { "PDM1 R Mux", "DD MIX2", "DD2 MIXR" }, 4249 { "PDM1 R Mux", NULL, "PDM1 Power" }, 4250 { "PDM2 L Mux", "STO1 DAC MIX", "Stereo DAC MIXL" }, 4251 { "PDM2 L Mux", "MONO DAC MIX", "Mono DAC MIXL" }, 4252 { "PDM2 L Mux", "DD MIX1", "DD1 MIXL" }, 4253 { "PDM2 L Mux", "DD MIX2", "DD2 MIXL" }, 4254 { "PDM2 L Mux", NULL, "PDM2 Power" }, 4255 { "PDM2 R Mux", "STO1 DAC MIX", "Stereo DAC MIXR" }, 4256 { "PDM2 R Mux", "MONO DAC MIX", "Mono DAC MIXR" }, 4257 { "PDM2 R Mux", "DD MIX1", "DD1 MIXR" }, 4258 { "PDM2 R Mux", "DD MIX1", "DD2 MIXR" }, 4259 { "PDM2 R Mux", NULL, "PDM2 Power" }, 4260 4261 { "LOUT1 amp", NULL, "DAC 1" }, 4262 { "LOUT2 amp", NULL, "DAC 2" }, 4263 { "LOUT3 amp", NULL, "DAC 3" }, 4264 4265 { "LOUT1 vref", NULL, "LOUT1 amp" }, 4266 { "LOUT2 vref", NULL, "LOUT2 amp" }, 4267 { "LOUT3 vref", NULL, "LOUT3 amp" }, 4268 4269 { "LOUT1", NULL, "LOUT1 vref" }, 4270 { "LOUT2", NULL, "LOUT2 vref" }, 4271 { "LOUT3", NULL, "LOUT3 vref" }, 4272 4273 { "PDM1L", NULL, "PDM1 L Mux" }, 4274 { "PDM1R", NULL, "PDM1 R Mux" }, 4275 { "PDM2L", NULL, "PDM2 L Mux" }, 4276 { "PDM2R", NULL, "PDM2 R Mux" }, 4277 }; 4278 4279 static const struct snd_soc_dapm_route rt5677_dmic2_clk_1[] = { 4280 { "DMIC L2", NULL, "DMIC1 power" }, 4281 { "DMIC R2", NULL, "DMIC1 power" }, 4282 }; 4283 4284 static const struct snd_soc_dapm_route rt5677_dmic2_clk_2[] = { 4285 { "DMIC L2", NULL, "DMIC2 power" }, 4286 { "DMIC R2", NULL, "DMIC2 power" }, 4287 }; 4288 4289 static int rt5677_hw_params(struct snd_pcm_substream *substream, 4290 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) 4291 { 4292 struct snd_soc_component *component = dai->component; 4293 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component); 4294 unsigned int val_len = 0, val_clk, mask_clk; 4295 int pre_div, bclk_ms, frame_size; 4296 4297 rt5677->lrck[dai->id] = params_rate(params); 4298 pre_div = rl6231_get_clk_info(rt5677->sysclk, rt5677->lrck[dai->id]); 4299 if (pre_div < 0) { 4300 dev_err(component->dev, "Unsupported clock setting: sysclk=%dHz lrck=%dHz\n", 4301 rt5677->sysclk, rt5677->lrck[dai->id]); 4302 return -EINVAL; 4303 } 4304 frame_size = snd_soc_params_to_frame_size(params); 4305 if (frame_size < 0) { 4306 dev_err(component->dev, "Unsupported frame size: %d\n", frame_size); 4307 return -EINVAL; 4308 } 4309 bclk_ms = frame_size > 32; 4310 rt5677->bclk[dai->id] = rt5677->lrck[dai->id] * (32 << bclk_ms); 4311 4312 dev_dbg(dai->dev, "bclk is %dHz and lrck is %dHz\n", 4313 rt5677->bclk[dai->id], rt5677->lrck[dai->id]); 4314 dev_dbg(dai->dev, "bclk_ms is %d and pre_div is %d for iis %d\n", 4315 bclk_ms, pre_div, dai->id); 4316 4317 switch (params_width(params)) { 4318 case 16: 4319 break; 4320 case 20: 4321 val_len |= RT5677_I2S_DL_20; 4322 break; 4323 case 24: 4324 val_len |= RT5677_I2S_DL_24; 4325 break; 4326 case 8: 4327 val_len |= RT5677_I2S_DL_8; 4328 break; 4329 default: 4330 return -EINVAL; 4331 } 4332 4333 switch (dai->id) { 4334 case RT5677_AIF1: 4335 mask_clk = RT5677_I2S_PD1_MASK; 4336 val_clk = pre_div << RT5677_I2S_PD1_SFT; 4337 regmap_update_bits(rt5677->regmap, RT5677_I2S1_SDP, 4338 RT5677_I2S_DL_MASK, val_len); 4339 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1, 4340 mask_clk, val_clk); 4341 break; 4342 case RT5677_AIF2: 4343 mask_clk = RT5677_I2S_PD2_MASK; 4344 val_clk = pre_div << RT5677_I2S_PD2_SFT; 4345 regmap_update_bits(rt5677->regmap, RT5677_I2S2_SDP, 4346 RT5677_I2S_DL_MASK, val_len); 4347 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1, 4348 mask_clk, val_clk); 4349 break; 4350 case RT5677_AIF3: 4351 mask_clk = RT5677_I2S_BCLK_MS3_MASK | RT5677_I2S_PD3_MASK; 4352 val_clk = bclk_ms << RT5677_I2S_BCLK_MS3_SFT | 4353 pre_div << RT5677_I2S_PD3_SFT; 4354 regmap_update_bits(rt5677->regmap, RT5677_I2S3_SDP, 4355 RT5677_I2S_DL_MASK, val_len); 4356 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1, 4357 mask_clk, val_clk); 4358 break; 4359 case RT5677_AIF4: 4360 mask_clk = RT5677_I2S_BCLK_MS4_MASK | RT5677_I2S_PD4_MASK; 4361 val_clk = bclk_ms << RT5677_I2S_BCLK_MS4_SFT | 4362 pre_div << RT5677_I2S_PD4_SFT; 4363 regmap_update_bits(rt5677->regmap, RT5677_I2S4_SDP, 4364 RT5677_I2S_DL_MASK, val_len); 4365 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1, 4366 mask_clk, val_clk); 4367 break; 4368 default: 4369 break; 4370 } 4371 4372 return 0; 4373 } 4374 4375 static int rt5677_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) 4376 { 4377 struct snd_soc_component *component = dai->component; 4378 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component); 4379 unsigned int reg_val = 0; 4380 4381 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 4382 case SND_SOC_DAIFMT_CBM_CFM: 4383 rt5677->master[dai->id] = 1; 4384 break; 4385 case SND_SOC_DAIFMT_CBS_CFS: 4386 reg_val |= RT5677_I2S_MS_S; 4387 rt5677->master[dai->id] = 0; 4388 break; 4389 default: 4390 return -EINVAL; 4391 } 4392 4393 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 4394 case SND_SOC_DAIFMT_NB_NF: 4395 break; 4396 case SND_SOC_DAIFMT_IB_NF: 4397 reg_val |= RT5677_I2S_BP_INV; 4398 break; 4399 default: 4400 return -EINVAL; 4401 } 4402 4403 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 4404 case SND_SOC_DAIFMT_I2S: 4405 break; 4406 case SND_SOC_DAIFMT_LEFT_J: 4407 reg_val |= RT5677_I2S_DF_LEFT; 4408 break; 4409 case SND_SOC_DAIFMT_DSP_A: 4410 reg_val |= RT5677_I2S_DF_PCM_A; 4411 break; 4412 case SND_SOC_DAIFMT_DSP_B: 4413 reg_val |= RT5677_I2S_DF_PCM_B; 4414 break; 4415 default: 4416 return -EINVAL; 4417 } 4418 4419 switch (dai->id) { 4420 case RT5677_AIF1: 4421 regmap_update_bits(rt5677->regmap, RT5677_I2S1_SDP, 4422 RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK | 4423 RT5677_I2S_DF_MASK, reg_val); 4424 break; 4425 case RT5677_AIF2: 4426 regmap_update_bits(rt5677->regmap, RT5677_I2S2_SDP, 4427 RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK | 4428 RT5677_I2S_DF_MASK, reg_val); 4429 break; 4430 case RT5677_AIF3: 4431 regmap_update_bits(rt5677->regmap, RT5677_I2S3_SDP, 4432 RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK | 4433 RT5677_I2S_DF_MASK, reg_val); 4434 break; 4435 case RT5677_AIF4: 4436 regmap_update_bits(rt5677->regmap, RT5677_I2S4_SDP, 4437 RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK | 4438 RT5677_I2S_DF_MASK, reg_val); 4439 break; 4440 default: 4441 break; 4442 } 4443 4444 4445 return 0; 4446 } 4447 4448 static int rt5677_set_dai_sysclk(struct snd_soc_dai *dai, 4449 int clk_id, unsigned int freq, int dir) 4450 { 4451 struct snd_soc_component *component = dai->component; 4452 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component); 4453 unsigned int reg_val = 0; 4454 4455 if (freq == rt5677->sysclk && clk_id == rt5677->sysclk_src) 4456 return 0; 4457 4458 switch (clk_id) { 4459 case RT5677_SCLK_S_MCLK: 4460 reg_val |= RT5677_SCLK_SRC_MCLK; 4461 break; 4462 case RT5677_SCLK_S_PLL1: 4463 reg_val |= RT5677_SCLK_SRC_PLL1; 4464 break; 4465 case RT5677_SCLK_S_RCCLK: 4466 reg_val |= RT5677_SCLK_SRC_RCCLK; 4467 break; 4468 default: 4469 dev_err(component->dev, "Invalid clock id (%d)\n", clk_id); 4470 return -EINVAL; 4471 } 4472 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1, 4473 RT5677_SCLK_SRC_MASK, reg_val); 4474 rt5677->sysclk = freq; 4475 rt5677->sysclk_src = clk_id; 4476 4477 dev_dbg(dai->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id); 4478 4479 return 0; 4480 } 4481 4482 /** 4483 * rt5677_pll_calc - Calcualte PLL M/N/K code. 4484 * @freq_in: external clock provided to codec. 4485 * @freq_out: target clock which codec works on. 4486 * @pll_code: Pointer to structure with M, N, K, bypass K and bypass M flag. 4487 * 4488 * Calcualte M/N/K code and bypass K/M flag to configure PLL for codec. 4489 * 4490 * Returns 0 for success or negative error code. 4491 */ 4492 static int rt5677_pll_calc(const unsigned int freq_in, 4493 const unsigned int freq_out, struct rl6231_pll_code *pll_code) 4494 { 4495 if (RT5677_PLL_INP_MIN > freq_in) 4496 return -EINVAL; 4497 4498 return rl6231_pll_calc(freq_in, freq_out, pll_code); 4499 } 4500 4501 static int rt5677_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source, 4502 unsigned int freq_in, unsigned int freq_out) 4503 { 4504 struct snd_soc_component *component = dai->component; 4505 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component); 4506 struct rl6231_pll_code pll_code; 4507 int ret; 4508 4509 if (source == rt5677->pll_src && freq_in == rt5677->pll_in && 4510 freq_out == rt5677->pll_out) 4511 return 0; 4512 4513 if (!freq_in || !freq_out) { 4514 dev_dbg(component->dev, "PLL disabled\n"); 4515 4516 rt5677->pll_in = 0; 4517 rt5677->pll_out = 0; 4518 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1, 4519 RT5677_SCLK_SRC_MASK, RT5677_SCLK_SRC_MCLK); 4520 return 0; 4521 } 4522 4523 switch (source) { 4524 case RT5677_PLL1_S_MCLK: 4525 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1, 4526 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_MCLK); 4527 break; 4528 case RT5677_PLL1_S_BCLK1: 4529 case RT5677_PLL1_S_BCLK2: 4530 case RT5677_PLL1_S_BCLK3: 4531 case RT5677_PLL1_S_BCLK4: 4532 switch (dai->id) { 4533 case RT5677_AIF1: 4534 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1, 4535 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK1); 4536 break; 4537 case RT5677_AIF2: 4538 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1, 4539 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK2); 4540 break; 4541 case RT5677_AIF3: 4542 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1, 4543 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK3); 4544 break; 4545 case RT5677_AIF4: 4546 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1, 4547 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK4); 4548 break; 4549 default: 4550 break; 4551 } 4552 break; 4553 default: 4554 dev_err(component->dev, "Unknown PLL source %d\n", source); 4555 return -EINVAL; 4556 } 4557 4558 ret = rt5677_pll_calc(freq_in, freq_out, &pll_code); 4559 if (ret < 0) { 4560 dev_err(component->dev, "Unsupport input clock %d\n", freq_in); 4561 return ret; 4562 } 4563 4564 dev_dbg(component->dev, "m_bypass=%d m=%d n=%d k=%d\n", 4565 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code), 4566 pll_code.n_code, pll_code.k_code); 4567 4568 regmap_write(rt5677->regmap, RT5677_PLL1_CTRL1, 4569 pll_code.n_code << RT5677_PLL_N_SFT | pll_code.k_code); 4570 regmap_write(rt5677->regmap, RT5677_PLL1_CTRL2, 4571 ((pll_code.m_bp ? 0 : pll_code.m_code) << RT5677_PLL_M_SFT) | 4572 (pll_code.m_bp << RT5677_PLL_M_BP_SFT)); 4573 4574 rt5677->pll_in = freq_in; 4575 rt5677->pll_out = freq_out; 4576 rt5677->pll_src = source; 4577 4578 return 0; 4579 } 4580 4581 static int rt5677_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask, 4582 unsigned int rx_mask, int slots, int slot_width) 4583 { 4584 struct snd_soc_component *component = dai->component; 4585 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component); 4586 unsigned int val = 0, slot_width_25 = 0; 4587 4588 if (rx_mask || tx_mask) 4589 val |= (1 << 12); 4590 4591 switch (slots) { 4592 case 4: 4593 val |= (1 << 10); 4594 break; 4595 case 6: 4596 val |= (2 << 10); 4597 break; 4598 case 8: 4599 val |= (3 << 10); 4600 break; 4601 case 2: 4602 default: 4603 break; 4604 } 4605 4606 switch (slot_width) { 4607 case 20: 4608 val |= (1 << 8); 4609 break; 4610 case 25: 4611 slot_width_25 = 0x8080; 4612 fallthrough; 4613 case 24: 4614 val |= (2 << 8); 4615 break; 4616 case 32: 4617 val |= (3 << 8); 4618 break; 4619 case 16: 4620 default: 4621 break; 4622 } 4623 4624 switch (dai->id) { 4625 case RT5677_AIF1: 4626 regmap_update_bits(rt5677->regmap, RT5677_TDM1_CTRL1, 0x1f00, 4627 val); 4628 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x8000, 4629 slot_width_25); 4630 break; 4631 case RT5677_AIF2: 4632 regmap_update_bits(rt5677->regmap, RT5677_TDM2_CTRL1, 0x1f00, 4633 val); 4634 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x80, 4635 slot_width_25); 4636 break; 4637 default: 4638 break; 4639 } 4640 4641 return 0; 4642 } 4643 4644 static int rt5677_set_bias_level(struct snd_soc_component *component, 4645 enum snd_soc_bias_level level) 4646 { 4647 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component); 4648 enum snd_soc_bias_level prev_bias = 4649 snd_soc_component_get_bias_level(component); 4650 4651 switch (level) { 4652 case SND_SOC_BIAS_ON: 4653 break; 4654 4655 case SND_SOC_BIAS_PREPARE: 4656 if (prev_bias == SND_SOC_BIAS_STANDBY) { 4657 4658 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1, 4659 RT5677_LDO1_SEL_MASK | RT5677_LDO2_SEL_MASK, 4660 5 << RT5677_LDO1_SEL_SFT | 4661 5 << RT5677_LDO2_SEL_SFT); 4662 regmap_update_bits(rt5677->regmap, 4663 RT5677_PR_BASE + RT5677_BIAS_CUR4, 4664 0x0f00, 0x0f00); 4665 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1, 4666 RT5677_PWR_FV1 | RT5677_PWR_FV2 | 4667 RT5677_PWR_VREF1 | RT5677_PWR_MB | 4668 RT5677_PWR_BG | RT5677_PWR_VREF2, 4669 RT5677_PWR_VREF1 | RT5677_PWR_MB | 4670 RT5677_PWR_BG | RT5677_PWR_VREF2); 4671 rt5677->is_vref_slow = false; 4672 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2, 4673 RT5677_PWR_CORE, RT5677_PWR_CORE); 4674 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 4675 0x1, 0x1); 4676 } 4677 break; 4678 4679 case SND_SOC_BIAS_STANDBY: 4680 if (prev_bias == SND_SOC_BIAS_OFF && 4681 rt5677->dsp_vad_en_request) { 4682 /* Re-enable the DSP if it was turned off at suspend */ 4683 rt5677->dsp_vad_en = true; 4684 /* The delay is to wait for MCLK */ 4685 schedule_delayed_work(&rt5677->dsp_work, 4686 msecs_to_jiffies(1000)); 4687 } 4688 break; 4689 4690 case SND_SOC_BIAS_OFF: 4691 flush_delayed_work(&rt5677->dsp_work); 4692 if (rt5677->is_dsp_mode) { 4693 /* Turn off the DSP before suspend */ 4694 rt5677->dsp_vad_en = false; 4695 schedule_delayed_work(&rt5677->dsp_work, 0); 4696 flush_delayed_work(&rt5677->dsp_work); 4697 } 4698 4699 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x1, 0x0); 4700 regmap_write(rt5677->regmap, RT5677_PWR_DIG1, 0x0000); 4701 regmap_write(rt5677->regmap, RT5677_PWR_ANLG1, 4702 2 << RT5677_LDO1_SEL_SFT | 4703 2 << RT5677_LDO2_SEL_SFT); 4704 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2, 4705 RT5677_PWR_CORE, 0); 4706 regmap_update_bits(rt5677->regmap, 4707 RT5677_PR_BASE + RT5677_BIAS_CUR4, 0x0f00, 0x0000); 4708 4709 if (rt5677->dsp_vad_en) 4710 rt5677_set_dsp_vad(component, true); 4711 break; 4712 4713 default: 4714 break; 4715 } 4716 4717 return 0; 4718 } 4719 4720 #ifdef CONFIG_GPIOLIB 4721 static void rt5677_gpio_set(struct gpio_chip *chip, unsigned offset, int value) 4722 { 4723 struct rt5677_priv *rt5677 = gpiochip_get_data(chip); 4724 4725 switch (offset) { 4726 case RT5677_GPIO1 ... RT5677_GPIO5: 4727 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2, 4728 0x1 << (offset * 3 + 1), !!value << (offset * 3 + 1)); 4729 break; 4730 4731 case RT5677_GPIO6: 4732 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL3, 4733 RT5677_GPIO6_OUT_MASK, !!value << RT5677_GPIO6_OUT_SFT); 4734 break; 4735 4736 default: 4737 break; 4738 } 4739 } 4740 4741 static int rt5677_gpio_direction_out(struct gpio_chip *chip, 4742 unsigned offset, int value) 4743 { 4744 struct rt5677_priv *rt5677 = gpiochip_get_data(chip); 4745 4746 switch (offset) { 4747 case RT5677_GPIO1 ... RT5677_GPIO5: 4748 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2, 4749 0x3 << (offset * 3 + 1), 4750 (0x2 | !!value) << (offset * 3 + 1)); 4751 break; 4752 4753 case RT5677_GPIO6: 4754 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL3, 4755 RT5677_GPIO6_DIR_MASK | RT5677_GPIO6_OUT_MASK, 4756 RT5677_GPIO6_DIR_OUT | !!value << RT5677_GPIO6_OUT_SFT); 4757 break; 4758 4759 default: 4760 break; 4761 } 4762 4763 return 0; 4764 } 4765 4766 static int rt5677_gpio_get(struct gpio_chip *chip, unsigned offset) 4767 { 4768 struct rt5677_priv *rt5677 = gpiochip_get_data(chip); 4769 int value, ret; 4770 4771 ret = regmap_read(rt5677->regmap, RT5677_GPIO_ST, &value); 4772 if (ret < 0) 4773 return ret; 4774 4775 return (value & (0x1 << offset)) >> offset; 4776 } 4777 4778 static int rt5677_gpio_direction_in(struct gpio_chip *chip, unsigned offset) 4779 { 4780 struct rt5677_priv *rt5677 = gpiochip_get_data(chip); 4781 4782 switch (offset) { 4783 case RT5677_GPIO1 ... RT5677_GPIO5: 4784 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2, 4785 0x1 << (offset * 3 + 2), 0x0); 4786 break; 4787 4788 case RT5677_GPIO6: 4789 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL3, 4790 RT5677_GPIO6_DIR_MASK, RT5677_GPIO6_DIR_IN); 4791 break; 4792 4793 default: 4794 break; 4795 } 4796 4797 return 0; 4798 } 4799 4800 /** Configures the gpio as 4801 * 0 - floating 4802 * 1 - pull down 4803 * 2 - pull up 4804 */ 4805 static void rt5677_gpio_config(struct rt5677_priv *rt5677, unsigned offset, 4806 int value) 4807 { 4808 int shift; 4809 4810 switch (offset) { 4811 case RT5677_GPIO1 ... RT5677_GPIO2: 4812 shift = 2 * (1 - offset); 4813 regmap_update_bits(rt5677->regmap, 4814 RT5677_PR_BASE + RT5677_DIG_IN_PIN_ST_CTRL2, 4815 0x3 << shift, 4816 (value & 0x3) << shift); 4817 break; 4818 4819 case RT5677_GPIO3 ... RT5677_GPIO6: 4820 shift = 2 * (9 - offset); 4821 regmap_update_bits(rt5677->regmap, 4822 RT5677_PR_BASE + RT5677_DIG_IN_PIN_ST_CTRL3, 4823 0x3 << shift, 4824 (value & 0x3) << shift); 4825 break; 4826 4827 default: 4828 break; 4829 } 4830 } 4831 4832 static int rt5677_to_irq(struct gpio_chip *chip, unsigned offset) 4833 { 4834 struct rt5677_priv *rt5677 = gpiochip_get_data(chip); 4835 int irq; 4836 4837 if ((rt5677->pdata.jd1_gpio == 1 && offset == RT5677_GPIO1) || 4838 (rt5677->pdata.jd1_gpio == 2 && 4839 offset == RT5677_GPIO2) || 4840 (rt5677->pdata.jd1_gpio == 3 && 4841 offset == RT5677_GPIO3)) { 4842 irq = RT5677_IRQ_JD1; 4843 } else if ((rt5677->pdata.jd2_gpio == 1 && offset == RT5677_GPIO4) || 4844 (rt5677->pdata.jd2_gpio == 2 && 4845 offset == RT5677_GPIO5) || 4846 (rt5677->pdata.jd2_gpio == 3 && 4847 offset == RT5677_GPIO6)) { 4848 irq = RT5677_IRQ_JD2; 4849 } else if ((rt5677->pdata.jd3_gpio == 1 && 4850 offset == RT5677_GPIO4) || 4851 (rt5677->pdata.jd3_gpio == 2 && 4852 offset == RT5677_GPIO5) || 4853 (rt5677->pdata.jd3_gpio == 3 && 4854 offset == RT5677_GPIO6)) { 4855 irq = RT5677_IRQ_JD3; 4856 } else { 4857 return -ENXIO; 4858 } 4859 4860 return irq_create_mapping(rt5677->domain, irq); 4861 } 4862 4863 static const struct gpio_chip rt5677_template_chip = { 4864 .label = RT5677_DRV_NAME, 4865 .owner = THIS_MODULE, 4866 .direction_output = rt5677_gpio_direction_out, 4867 .set = rt5677_gpio_set, 4868 .direction_input = rt5677_gpio_direction_in, 4869 .get = rt5677_gpio_get, 4870 .to_irq = rt5677_to_irq, 4871 .can_sleep = 1, 4872 }; 4873 4874 static void rt5677_init_gpio(struct i2c_client *i2c) 4875 { 4876 struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c); 4877 int ret; 4878 4879 rt5677->gpio_chip = rt5677_template_chip; 4880 rt5677->gpio_chip.ngpio = RT5677_GPIO_NUM; 4881 rt5677->gpio_chip.parent = &i2c->dev; 4882 rt5677->gpio_chip.base = -1; 4883 4884 ret = gpiochip_add_data(&rt5677->gpio_chip, rt5677); 4885 if (ret != 0) 4886 dev_err(&i2c->dev, "Failed to add GPIOs: %d\n", ret); 4887 } 4888 4889 static void rt5677_free_gpio(struct i2c_client *i2c) 4890 { 4891 struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c); 4892 4893 gpiochip_remove(&rt5677->gpio_chip); 4894 } 4895 #else 4896 static void rt5677_gpio_config(struct rt5677_priv *rt5677, unsigned offset, 4897 int value) 4898 { 4899 } 4900 4901 static void rt5677_init_gpio(struct i2c_client *i2c) 4902 { 4903 } 4904 4905 static void rt5677_free_gpio(struct i2c_client *i2c) 4906 { 4907 } 4908 #endif 4909 4910 static int rt5677_probe(struct snd_soc_component *component) 4911 { 4912 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); 4913 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component); 4914 int i; 4915 4916 rt5677->component = component; 4917 4918 if (rt5677->pdata.dmic2_clk_pin == RT5677_DMIC_CLK2) { 4919 snd_soc_dapm_add_routes(dapm, 4920 rt5677_dmic2_clk_2, 4921 ARRAY_SIZE(rt5677_dmic2_clk_2)); 4922 } else { /*use dmic1 clock by default*/ 4923 snd_soc_dapm_add_routes(dapm, 4924 rt5677_dmic2_clk_1, 4925 ARRAY_SIZE(rt5677_dmic2_clk_1)); 4926 } 4927 4928 snd_soc_component_force_bias_level(component, SND_SOC_BIAS_OFF); 4929 4930 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 4931 ~RT5677_IRQ_DEBOUNCE_SEL_MASK, 0x0020); 4932 regmap_write(rt5677->regmap, RT5677_PWR_DSP2, 4933 RT5677_PWR_SLIM_ISO | RT5677_PWR_CORE_ISO); 4934 4935 for (i = 0; i < RT5677_GPIO_NUM; i++) 4936 rt5677_gpio_config(rt5677, i, rt5677->pdata.gpio_config[i]); 4937 4938 mutex_init(&rt5677->dsp_cmd_lock); 4939 mutex_init(&rt5677->dsp_pri_lock); 4940 4941 return 0; 4942 } 4943 4944 static void rt5677_remove(struct snd_soc_component *component) 4945 { 4946 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component); 4947 4948 cancel_delayed_work_sync(&rt5677->dsp_work); 4949 4950 regmap_write(rt5677->regmap, RT5677_RESET, 0x10ec); 4951 gpiod_set_value_cansleep(rt5677->pow_ldo2, 0); 4952 gpiod_set_value_cansleep(rt5677->reset_pin, 1); 4953 } 4954 4955 #ifdef CONFIG_PM 4956 static int rt5677_suspend(struct snd_soc_component *component) 4957 { 4958 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component); 4959 4960 if (rt5677->irq) { 4961 cancel_delayed_work_sync(&rt5677->resume_irq_check); 4962 disable_irq(rt5677->irq); 4963 } 4964 4965 if (!rt5677->dsp_vad_en) { 4966 regcache_cache_only(rt5677->regmap, true); 4967 regcache_mark_dirty(rt5677->regmap); 4968 4969 gpiod_set_value_cansleep(rt5677->pow_ldo2, 0); 4970 gpiod_set_value_cansleep(rt5677->reset_pin, 1); 4971 } 4972 4973 return 0; 4974 } 4975 4976 static int rt5677_resume(struct snd_soc_component *component) 4977 { 4978 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component); 4979 4980 if (!rt5677->dsp_vad_en) { 4981 rt5677->pll_src = 0; 4982 rt5677->pll_in = 0; 4983 rt5677->pll_out = 0; 4984 gpiod_set_value_cansleep(rt5677->pow_ldo2, 1); 4985 gpiod_set_value_cansleep(rt5677->reset_pin, 0); 4986 if (rt5677->pow_ldo2 || rt5677->reset_pin) 4987 msleep(10); 4988 4989 regcache_cache_only(rt5677->regmap, false); 4990 regcache_sync(rt5677->regmap); 4991 } 4992 4993 if (rt5677->irq) { 4994 enable_irq(rt5677->irq); 4995 schedule_delayed_work(&rt5677->resume_irq_check, 0); 4996 } 4997 4998 return 0; 4999 } 5000 #else 5001 #define rt5677_suspend NULL 5002 #define rt5677_resume NULL 5003 #endif 5004 5005 static int rt5677_read(void *context, unsigned int reg, unsigned int *val) 5006 { 5007 struct i2c_client *client = context; 5008 struct rt5677_priv *rt5677 = i2c_get_clientdata(client); 5009 5010 if (rt5677->is_dsp_mode) { 5011 if (reg > 0xff) { 5012 mutex_lock(&rt5677->dsp_pri_lock); 5013 rt5677_dsp_mode_i2c_write(rt5677, RT5677_PRIV_INDEX, 5014 reg & 0xff); 5015 rt5677_dsp_mode_i2c_read(rt5677, RT5677_PRIV_DATA, val); 5016 mutex_unlock(&rt5677->dsp_pri_lock); 5017 } else { 5018 rt5677_dsp_mode_i2c_read(rt5677, reg, val); 5019 } 5020 } else { 5021 regmap_read(rt5677->regmap_physical, reg, val); 5022 } 5023 5024 return 0; 5025 } 5026 5027 static int rt5677_write(void *context, unsigned int reg, unsigned int val) 5028 { 5029 struct i2c_client *client = context; 5030 struct rt5677_priv *rt5677 = i2c_get_clientdata(client); 5031 5032 if (rt5677->is_dsp_mode) { 5033 if (reg > 0xff) { 5034 mutex_lock(&rt5677->dsp_pri_lock); 5035 rt5677_dsp_mode_i2c_write(rt5677, RT5677_PRIV_INDEX, 5036 reg & 0xff); 5037 rt5677_dsp_mode_i2c_write(rt5677, RT5677_PRIV_DATA, 5038 val); 5039 mutex_unlock(&rt5677->dsp_pri_lock); 5040 } else { 5041 rt5677_dsp_mode_i2c_write(rt5677, reg, val); 5042 } 5043 } else { 5044 regmap_write(rt5677->regmap_physical, reg, val); 5045 } 5046 5047 return 0; 5048 } 5049 5050 #define RT5677_STEREO_RATES SNDRV_PCM_RATE_8000_96000 5051 #define RT5677_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ 5052 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8) 5053 5054 static const struct snd_soc_dai_ops rt5677_aif_dai_ops = { 5055 .hw_params = rt5677_hw_params, 5056 .set_fmt = rt5677_set_dai_fmt, 5057 .set_sysclk = rt5677_set_dai_sysclk, 5058 .set_pll = rt5677_set_dai_pll, 5059 .set_tdm_slot = rt5677_set_tdm_slot, 5060 }; 5061 5062 static const struct snd_soc_dai_ops rt5677_dsp_dai_ops = { 5063 .set_sysclk = rt5677_set_dai_sysclk, 5064 .set_pll = rt5677_set_dai_pll, 5065 }; 5066 5067 static struct snd_soc_dai_driver rt5677_dai[] = { 5068 { 5069 .name = "rt5677-aif1", 5070 .id = RT5677_AIF1, 5071 .playback = { 5072 .stream_name = "AIF1 Playback", 5073 .channels_min = 1, 5074 .channels_max = 2, 5075 .rates = RT5677_STEREO_RATES, 5076 .formats = RT5677_FORMATS, 5077 }, 5078 .capture = { 5079 .stream_name = "AIF1 Capture", 5080 .channels_min = 1, 5081 .channels_max = 2, 5082 .rates = RT5677_STEREO_RATES, 5083 .formats = RT5677_FORMATS, 5084 }, 5085 .ops = &rt5677_aif_dai_ops, 5086 }, 5087 { 5088 .name = "rt5677-aif2", 5089 .id = RT5677_AIF2, 5090 .playback = { 5091 .stream_name = "AIF2 Playback", 5092 .channels_min = 1, 5093 .channels_max = 2, 5094 .rates = RT5677_STEREO_RATES, 5095 .formats = RT5677_FORMATS, 5096 }, 5097 .capture = { 5098 .stream_name = "AIF2 Capture", 5099 .channels_min = 1, 5100 .channels_max = 2, 5101 .rates = RT5677_STEREO_RATES, 5102 .formats = RT5677_FORMATS, 5103 }, 5104 .ops = &rt5677_aif_dai_ops, 5105 }, 5106 { 5107 .name = "rt5677-aif3", 5108 .id = RT5677_AIF3, 5109 .playback = { 5110 .stream_name = "AIF3 Playback", 5111 .channels_min = 1, 5112 .channels_max = 2, 5113 .rates = RT5677_STEREO_RATES, 5114 .formats = RT5677_FORMATS, 5115 }, 5116 .capture = { 5117 .stream_name = "AIF3 Capture", 5118 .channels_min = 1, 5119 .channels_max = 2, 5120 .rates = RT5677_STEREO_RATES, 5121 .formats = RT5677_FORMATS, 5122 }, 5123 .ops = &rt5677_aif_dai_ops, 5124 }, 5125 { 5126 .name = "rt5677-aif4", 5127 .id = RT5677_AIF4, 5128 .playback = { 5129 .stream_name = "AIF4 Playback", 5130 .channels_min = 1, 5131 .channels_max = 2, 5132 .rates = RT5677_STEREO_RATES, 5133 .formats = RT5677_FORMATS, 5134 }, 5135 .capture = { 5136 .stream_name = "AIF4 Capture", 5137 .channels_min = 1, 5138 .channels_max = 2, 5139 .rates = RT5677_STEREO_RATES, 5140 .formats = RT5677_FORMATS, 5141 }, 5142 .ops = &rt5677_aif_dai_ops, 5143 }, 5144 { 5145 .name = "rt5677-slimbus", 5146 .id = RT5677_AIF5, 5147 .playback = { 5148 .stream_name = "SLIMBus Playback", 5149 .channels_min = 1, 5150 .channels_max = 2, 5151 .rates = RT5677_STEREO_RATES, 5152 .formats = RT5677_FORMATS, 5153 }, 5154 .capture = { 5155 .stream_name = "SLIMBus Capture", 5156 .channels_min = 1, 5157 .channels_max = 2, 5158 .rates = RT5677_STEREO_RATES, 5159 .formats = RT5677_FORMATS, 5160 }, 5161 .ops = &rt5677_aif_dai_ops, 5162 }, 5163 { 5164 .name = "rt5677-dspbuffer", 5165 .id = RT5677_DSPBUFF, 5166 .capture = { 5167 .stream_name = "DSP Buffer", 5168 .channels_min = 1, 5169 .channels_max = 1, 5170 .rates = SNDRV_PCM_RATE_16000, 5171 .formats = SNDRV_PCM_FMTBIT_S16_LE, 5172 }, 5173 .ops = &rt5677_dsp_dai_ops, 5174 }, 5175 }; 5176 5177 static const struct snd_soc_component_driver soc_component_dev_rt5677 = { 5178 .name = RT5677_DRV_NAME, 5179 .probe = rt5677_probe, 5180 .remove = rt5677_remove, 5181 .suspend = rt5677_suspend, 5182 .resume = rt5677_resume, 5183 .set_bias_level = rt5677_set_bias_level, 5184 .controls = rt5677_snd_controls, 5185 .num_controls = ARRAY_SIZE(rt5677_snd_controls), 5186 .dapm_widgets = rt5677_dapm_widgets, 5187 .num_dapm_widgets = ARRAY_SIZE(rt5677_dapm_widgets), 5188 .dapm_routes = rt5677_dapm_routes, 5189 .num_dapm_routes = ARRAY_SIZE(rt5677_dapm_routes), 5190 .use_pmdown_time = 1, 5191 .endianness = 1, 5192 .non_legacy_dai_naming = 1, 5193 }; 5194 5195 static const struct regmap_config rt5677_regmap_physical = { 5196 .name = "physical", 5197 .reg_bits = 8, 5198 .val_bits = 16, 5199 5200 .max_register = RT5677_VENDOR_ID2 + 1 + (ARRAY_SIZE(rt5677_ranges) * 5201 RT5677_PR_SPACING), 5202 .readable_reg = rt5677_readable_register, 5203 5204 .cache_type = REGCACHE_NONE, 5205 .ranges = rt5677_ranges, 5206 .num_ranges = ARRAY_SIZE(rt5677_ranges), 5207 }; 5208 5209 static const struct regmap_config rt5677_regmap = { 5210 .reg_bits = 8, 5211 .val_bits = 16, 5212 5213 .max_register = RT5677_VENDOR_ID2 + 1 + (ARRAY_SIZE(rt5677_ranges) * 5214 RT5677_PR_SPACING), 5215 5216 .volatile_reg = rt5677_volatile_register, 5217 .readable_reg = rt5677_readable_register, 5218 .reg_read = rt5677_read, 5219 .reg_write = rt5677_write, 5220 5221 .cache_type = REGCACHE_RBTREE, 5222 .reg_defaults = rt5677_reg, 5223 .num_reg_defaults = ARRAY_SIZE(rt5677_reg), 5224 .ranges = rt5677_ranges, 5225 .num_ranges = ARRAY_SIZE(rt5677_ranges), 5226 }; 5227 5228 static const struct of_device_id rt5677_of_match[] = { 5229 { .compatible = "realtek,rt5677", .data = (const void *)RT5677 }, 5230 { } 5231 }; 5232 MODULE_DEVICE_TABLE(of, rt5677_of_match); 5233 5234 static const struct acpi_device_id rt5677_acpi_match[] = { 5235 { "RT5677CE", RT5677 }, 5236 { } 5237 }; 5238 MODULE_DEVICE_TABLE(acpi, rt5677_acpi_match); 5239 5240 static void rt5677_read_device_properties(struct rt5677_priv *rt5677, 5241 struct device *dev) 5242 { 5243 u32 val; 5244 5245 rt5677->pdata.in1_diff = 5246 device_property_read_bool(dev, "IN1") || 5247 device_property_read_bool(dev, "realtek,in1-differential"); 5248 5249 rt5677->pdata.in2_diff = 5250 device_property_read_bool(dev, "IN2") || 5251 device_property_read_bool(dev, "realtek,in2-differential"); 5252 5253 rt5677->pdata.lout1_diff = 5254 device_property_read_bool(dev, "OUT1") || 5255 device_property_read_bool(dev, "realtek,lout1-differential"); 5256 5257 rt5677->pdata.lout2_diff = 5258 device_property_read_bool(dev, "OUT2") || 5259 device_property_read_bool(dev, "realtek,lout2-differential"); 5260 5261 rt5677->pdata.lout3_diff = 5262 device_property_read_bool(dev, "OUT3") || 5263 device_property_read_bool(dev, "realtek,lout3-differential"); 5264 5265 device_property_read_u8_array(dev, "realtek,gpio-config", 5266 rt5677->pdata.gpio_config, 5267 RT5677_GPIO_NUM); 5268 5269 if (!device_property_read_u32(dev, "DCLK", &val) || 5270 !device_property_read_u32(dev, "realtek,dmic2_clk_pin", &val)) 5271 rt5677->pdata.dmic2_clk_pin = val; 5272 5273 if (!device_property_read_u32(dev, "JD1", &val) || 5274 !device_property_read_u32(dev, "realtek,jd1-gpio", &val)) 5275 rt5677->pdata.jd1_gpio = val; 5276 5277 if (!device_property_read_u32(dev, "JD2", &val) || 5278 !device_property_read_u32(dev, "realtek,jd2-gpio", &val)) 5279 rt5677->pdata.jd2_gpio = val; 5280 5281 if (!device_property_read_u32(dev, "JD3", &val) || 5282 !device_property_read_u32(dev, "realtek,jd3-gpio", &val)) 5283 rt5677->pdata.jd3_gpio = val; 5284 } 5285 5286 struct rt5677_irq_desc { 5287 unsigned int enable_mask; 5288 unsigned int status_mask; 5289 unsigned int polarity_mask; 5290 }; 5291 5292 static const struct rt5677_irq_desc rt5677_irq_descs[] = { 5293 [RT5677_IRQ_JD1] = { 5294 .enable_mask = RT5677_EN_IRQ_GPIO_JD1, 5295 .status_mask = RT5677_STA_GPIO_JD1, 5296 .polarity_mask = RT5677_INV_GPIO_JD1, 5297 }, 5298 [RT5677_IRQ_JD2] = { 5299 .enable_mask = RT5677_EN_IRQ_GPIO_JD2, 5300 .status_mask = RT5677_STA_GPIO_JD2, 5301 .polarity_mask = RT5677_INV_GPIO_JD2, 5302 }, 5303 [RT5677_IRQ_JD3] = { 5304 .enable_mask = RT5677_EN_IRQ_GPIO_JD3, 5305 .status_mask = RT5677_STA_GPIO_JD3, 5306 .polarity_mask = RT5677_INV_GPIO_JD3, 5307 }, 5308 }; 5309 5310 static bool rt5677_check_hotword(struct rt5677_priv *rt5677) 5311 { 5312 int reg_gpio; 5313 5314 if (!rt5677->is_dsp_mode) 5315 return false; 5316 5317 if (regmap_read(rt5677->regmap, RT5677_GPIO_CTRL1, ®_gpio)) 5318 return false; 5319 5320 /* Firmware sets GPIO1 pin to be GPIO1 after hotword is detected */ 5321 if ((reg_gpio & RT5677_GPIO1_PIN_MASK) == RT5677_GPIO1_PIN_IRQ) 5322 return false; 5323 5324 /* Set GPIO1 pin back to be IRQ output for jack detect */ 5325 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL1, 5326 RT5677_GPIO1_PIN_MASK, RT5677_GPIO1_PIN_IRQ); 5327 5328 rt5677_spi_hotword_detected(); 5329 return true; 5330 } 5331 5332 static irqreturn_t rt5677_irq(int unused, void *data) 5333 { 5334 struct rt5677_priv *rt5677 = data; 5335 int ret, loop, i, reg_irq, virq; 5336 bool irq_fired = false; 5337 5338 mutex_lock(&rt5677->irq_lock); 5339 5340 /* 5341 * Loop to handle interrupts until the last i2c read shows no pending 5342 * irqs. The interrupt line is shared by multiple interrupt sources. 5343 * After the regmap_read() below, a new interrupt source line may 5344 * become high before the regmap_write() finishes, so there isn't a 5345 * rising edge on the shared interrupt line for the new interrupt. Thus, 5346 * the loop is needed to avoid missing irqs. 5347 * 5348 * A safeguard of 20 loops is used to avoid hanging in the irq handler 5349 * if there is something wrong with the interrupt status update. The 5350 * interrupt sources here are audio jack plug/unplug events which 5351 * shouldn't happen at a high frequency for a long period of time. 5352 * Empirically, more than 3 loops have never been seen. 5353 */ 5354 for (loop = 0; loop < 20; loop++) { 5355 /* Read interrupt status */ 5356 ret = regmap_read(rt5677->regmap, RT5677_IRQ_CTRL1, ®_irq); 5357 if (ret) { 5358 dev_err(rt5677->dev, "failed reading IRQ status: %d\n", 5359 ret); 5360 goto exit; 5361 } 5362 5363 irq_fired = false; 5364 for (i = 0; i < RT5677_IRQ_NUM; i++) { 5365 if (reg_irq & rt5677_irq_descs[i].status_mask) { 5366 irq_fired = true; 5367 virq = irq_find_mapping(rt5677->domain, i); 5368 if (virq) 5369 handle_nested_irq(virq); 5370 5371 /* Clear the interrupt by flipping the polarity 5372 * of the interrupt source line that fired 5373 */ 5374 reg_irq ^= rt5677_irq_descs[i].polarity_mask; 5375 } 5376 } 5377 5378 /* Exit the loop only when we know for sure that GPIO1 pin 5379 * was low at some point since irq_lock was acquired. Any event 5380 * after that point creates a rising edge that triggers another 5381 * call to rt5677_irq(). 5382 */ 5383 if (!irq_fired && !rt5677_check_hotword(rt5677)) 5384 goto exit; 5385 5386 ret = regmap_write(rt5677->regmap, RT5677_IRQ_CTRL1, reg_irq); 5387 if (ret) { 5388 dev_err(rt5677->dev, "failed updating IRQ status: %d\n", 5389 ret); 5390 goto exit; 5391 } 5392 } 5393 exit: 5394 WARN_ON_ONCE(loop == 20); 5395 mutex_unlock(&rt5677->irq_lock); 5396 if (irq_fired) 5397 return IRQ_HANDLED; 5398 else 5399 return IRQ_NONE; 5400 } 5401 5402 static void rt5677_resume_irq_check(struct work_struct *work) 5403 { 5404 int i, virq; 5405 struct rt5677_priv *rt5677 = 5406 container_of(work, struct rt5677_priv, resume_irq_check.work); 5407 5408 /* This is needed to check and clear the interrupt status register 5409 * at resume. If the headset is plugged/unplugged when the device is 5410 * fully suspended, there won't be a rising edge at resume to trigger 5411 * the interrupt. Without this, we miss the next unplug/plug event. 5412 */ 5413 rt5677_irq(0, rt5677); 5414 5415 /* Call all enabled jack detect irq handlers again. This is needed in 5416 * addition to the above check for a corner case caused by jack gpio 5417 * debounce. After codec irq is disabled at suspend, the delayed work 5418 * scheduled by soc-jack may run and read wrong jack gpio values, since 5419 * the regmap is in cache only mode. At resume, there is no irq because 5420 * rt5677_irq has already ran and cleared the irq status at suspend. 5421 * Without this explicit check, unplug the headset right after suspend 5422 * starts, then after resume the headset is still shown as plugged in. 5423 */ 5424 mutex_lock(&rt5677->irq_lock); 5425 for (i = 0; i < RT5677_IRQ_NUM; i++) { 5426 if (rt5677->irq_en & rt5677_irq_descs[i].enable_mask) { 5427 virq = irq_find_mapping(rt5677->domain, i); 5428 if (virq) 5429 handle_nested_irq(virq); 5430 } 5431 } 5432 mutex_unlock(&rt5677->irq_lock); 5433 } 5434 5435 static void rt5677_irq_bus_lock(struct irq_data *data) 5436 { 5437 struct rt5677_priv *rt5677 = irq_data_get_irq_chip_data(data); 5438 5439 mutex_lock(&rt5677->irq_lock); 5440 } 5441 5442 static void rt5677_irq_bus_sync_unlock(struct irq_data *data) 5443 { 5444 struct rt5677_priv *rt5677 = irq_data_get_irq_chip_data(data); 5445 5446 // Set the enable/disable bits for the jack detect IRQs. 5447 regmap_update_bits(rt5677->regmap, RT5677_IRQ_CTRL1, 5448 RT5677_EN_IRQ_GPIO_JD1 | RT5677_EN_IRQ_GPIO_JD2 | 5449 RT5677_EN_IRQ_GPIO_JD3, rt5677->irq_en); 5450 mutex_unlock(&rt5677->irq_lock); 5451 } 5452 5453 static void rt5677_irq_enable(struct irq_data *data) 5454 { 5455 struct rt5677_priv *rt5677 = irq_data_get_irq_chip_data(data); 5456 5457 rt5677->irq_en |= rt5677_irq_descs[data->hwirq].enable_mask; 5458 } 5459 5460 static void rt5677_irq_disable(struct irq_data *data) 5461 { 5462 struct rt5677_priv *rt5677 = irq_data_get_irq_chip_data(data); 5463 5464 rt5677->irq_en &= ~rt5677_irq_descs[data->hwirq].enable_mask; 5465 } 5466 5467 static struct irq_chip rt5677_irq_chip = { 5468 .name = "rt5677_irq_chip", 5469 .irq_bus_lock = rt5677_irq_bus_lock, 5470 .irq_bus_sync_unlock = rt5677_irq_bus_sync_unlock, 5471 .irq_disable = rt5677_irq_disable, 5472 .irq_enable = rt5677_irq_enable, 5473 }; 5474 5475 static int rt5677_irq_map(struct irq_domain *h, unsigned int virq, 5476 irq_hw_number_t hw) 5477 { 5478 struct rt5677_priv *rt5677 = h->host_data; 5479 5480 irq_set_chip_data(virq, rt5677); 5481 irq_set_chip(virq, &rt5677_irq_chip); 5482 irq_set_nested_thread(virq, 1); 5483 irq_set_noprobe(virq); 5484 return 0; 5485 } 5486 5487 5488 static const struct irq_domain_ops rt5677_domain_ops = { 5489 .map = rt5677_irq_map, 5490 .xlate = irq_domain_xlate_twocell, 5491 }; 5492 5493 static int rt5677_init_irq(struct i2c_client *i2c) 5494 { 5495 int ret; 5496 struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c); 5497 unsigned int jd_mask = 0, jd_val = 0; 5498 5499 if (!rt5677->pdata.jd1_gpio && 5500 !rt5677->pdata.jd2_gpio && 5501 !rt5677->pdata.jd3_gpio) 5502 return 0; 5503 5504 if (!i2c->irq) { 5505 dev_err(&i2c->dev, "No interrupt specified\n"); 5506 return -EINVAL; 5507 } 5508 5509 mutex_init(&rt5677->irq_lock); 5510 INIT_DELAYED_WORK(&rt5677->resume_irq_check, rt5677_resume_irq_check); 5511 5512 /* 5513 * Select RC as the debounce clock so that GPIO works even when 5514 * MCLK is gated which happens when there is no audio stream 5515 * (SND_SOC_BIAS_OFF). 5516 */ 5517 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 5518 RT5677_IRQ_DEBOUNCE_SEL_MASK, 5519 RT5677_IRQ_DEBOUNCE_SEL_RC); 5520 /* Enable auto power on RC when GPIO states are changed */ 5521 regmap_update_bits(rt5677->regmap, RT5677_GEN_CTRL1, 0xff, 0xff); 5522 5523 /* Select and enable jack detection sources per platform data */ 5524 if (rt5677->pdata.jd1_gpio) { 5525 jd_mask |= RT5677_SEL_GPIO_JD1_MASK; 5526 jd_val |= rt5677->pdata.jd1_gpio << RT5677_SEL_GPIO_JD1_SFT; 5527 } 5528 if (rt5677->pdata.jd2_gpio) { 5529 jd_mask |= RT5677_SEL_GPIO_JD2_MASK; 5530 jd_val |= rt5677->pdata.jd2_gpio << RT5677_SEL_GPIO_JD2_SFT; 5531 } 5532 if (rt5677->pdata.jd3_gpio) { 5533 jd_mask |= RT5677_SEL_GPIO_JD3_MASK; 5534 jd_val |= rt5677->pdata.jd3_gpio << RT5677_SEL_GPIO_JD3_SFT; 5535 } 5536 regmap_update_bits(rt5677->regmap, RT5677_JD_CTRL1, jd_mask, jd_val); 5537 5538 /* Set GPIO1 pin to be IRQ output */ 5539 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL1, 5540 RT5677_GPIO1_PIN_MASK, RT5677_GPIO1_PIN_IRQ); 5541 5542 /* Ready to listen for interrupts */ 5543 rt5677->domain = irq_domain_add_linear(i2c->dev.of_node, 5544 RT5677_IRQ_NUM, &rt5677_domain_ops, rt5677); 5545 if (!rt5677->domain) { 5546 dev_err(&i2c->dev, "Failed to create IRQ domain\n"); 5547 return -ENOMEM; 5548 } 5549 5550 ret = devm_request_threaded_irq(&i2c->dev, i2c->irq, NULL, rt5677_irq, 5551 IRQF_TRIGGER_RISING | IRQF_ONESHOT, 5552 "rt5677", rt5677); 5553 if (ret) 5554 dev_err(&i2c->dev, "Failed to request IRQ: %d\n", ret); 5555 5556 rt5677->irq = i2c->irq; 5557 5558 return ret; 5559 } 5560 5561 static int rt5677_i2c_probe(struct i2c_client *i2c) 5562 { 5563 struct rt5677_priv *rt5677; 5564 int ret; 5565 unsigned int val; 5566 5567 rt5677 = devm_kzalloc(&i2c->dev, sizeof(struct rt5677_priv), 5568 GFP_KERNEL); 5569 if (rt5677 == NULL) 5570 return -ENOMEM; 5571 5572 rt5677->dev = &i2c->dev; 5573 rt5677->set_dsp_vad = rt5677_set_dsp_vad; 5574 INIT_DELAYED_WORK(&rt5677->dsp_work, rt5677_dsp_work); 5575 i2c_set_clientdata(i2c, rt5677); 5576 5577 if (i2c->dev.of_node) { 5578 const struct of_device_id *match_id; 5579 5580 match_id = of_match_device(rt5677_of_match, &i2c->dev); 5581 if (match_id) 5582 rt5677->type = (enum rt5677_type)match_id->data; 5583 } else if (ACPI_HANDLE(&i2c->dev)) { 5584 const struct acpi_device_id *acpi_id; 5585 5586 acpi_id = acpi_match_device(rt5677_acpi_match, &i2c->dev); 5587 if (acpi_id) 5588 rt5677->type = (enum rt5677_type)acpi_id->driver_data; 5589 } else { 5590 return -EINVAL; 5591 } 5592 5593 rt5677_read_device_properties(rt5677, &i2c->dev); 5594 5595 /* pow-ldo2 and reset are optional. The codec pins may be statically 5596 * connected on the board without gpios. If the gpio device property 5597 * isn't specified, devm_gpiod_get_optional returns NULL. 5598 */ 5599 rt5677->pow_ldo2 = devm_gpiod_get_optional(&i2c->dev, 5600 "realtek,pow-ldo2", GPIOD_OUT_HIGH); 5601 if (IS_ERR(rt5677->pow_ldo2)) { 5602 ret = PTR_ERR(rt5677->pow_ldo2); 5603 dev_err(&i2c->dev, "Failed to request POW_LDO2: %d\n", ret); 5604 return ret; 5605 } 5606 rt5677->reset_pin = devm_gpiod_get_optional(&i2c->dev, 5607 "realtek,reset", GPIOD_OUT_LOW); 5608 if (IS_ERR(rt5677->reset_pin)) { 5609 ret = PTR_ERR(rt5677->reset_pin); 5610 dev_err(&i2c->dev, "Failed to request RESET: %d\n", ret); 5611 return ret; 5612 } 5613 5614 if (rt5677->pow_ldo2 || rt5677->reset_pin) { 5615 /* Wait a while until I2C bus becomes available. The datasheet 5616 * does not specify the exact we should wait but startup 5617 * sequence mentiones at least a few milliseconds. 5618 */ 5619 msleep(10); 5620 } 5621 5622 rt5677->regmap_physical = devm_regmap_init_i2c(i2c, 5623 &rt5677_regmap_physical); 5624 if (IS_ERR(rt5677->regmap_physical)) { 5625 ret = PTR_ERR(rt5677->regmap_physical); 5626 dev_err(&i2c->dev, "Failed to allocate register map: %d\n", 5627 ret); 5628 return ret; 5629 } 5630 5631 rt5677->regmap = devm_regmap_init(&i2c->dev, NULL, i2c, &rt5677_regmap); 5632 if (IS_ERR(rt5677->regmap)) { 5633 ret = PTR_ERR(rt5677->regmap); 5634 dev_err(&i2c->dev, "Failed to allocate register map: %d\n", 5635 ret); 5636 return ret; 5637 } 5638 5639 regmap_read(rt5677->regmap, RT5677_VENDOR_ID2, &val); 5640 if (val != RT5677_DEVICE_ID) { 5641 dev_err(&i2c->dev, 5642 "Device with ID register %#x is not rt5677\n", val); 5643 return -ENODEV; 5644 } 5645 5646 regmap_write(rt5677->regmap, RT5677_RESET, 0x10ec); 5647 5648 ret = regmap_register_patch(rt5677->regmap, init_list, 5649 ARRAY_SIZE(init_list)); 5650 if (ret != 0) 5651 dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret); 5652 5653 if (rt5677->pdata.in1_diff) 5654 regmap_update_bits(rt5677->regmap, RT5677_IN1, 5655 RT5677_IN_DF1, RT5677_IN_DF1); 5656 5657 if (rt5677->pdata.in2_diff) 5658 regmap_update_bits(rt5677->regmap, RT5677_IN1, 5659 RT5677_IN_DF2, RT5677_IN_DF2); 5660 5661 if (rt5677->pdata.lout1_diff) 5662 regmap_update_bits(rt5677->regmap, RT5677_LOUT1, 5663 RT5677_LOUT1_L_DF, RT5677_LOUT1_L_DF); 5664 5665 if (rt5677->pdata.lout2_diff) 5666 regmap_update_bits(rt5677->regmap, RT5677_LOUT1, 5667 RT5677_LOUT2_L_DF, RT5677_LOUT2_L_DF); 5668 5669 if (rt5677->pdata.lout3_diff) 5670 regmap_update_bits(rt5677->regmap, RT5677_LOUT1, 5671 RT5677_LOUT3_L_DF, RT5677_LOUT3_L_DF); 5672 5673 if (rt5677->pdata.dmic2_clk_pin == RT5677_DMIC_CLK2) { 5674 regmap_update_bits(rt5677->regmap, RT5677_GEN_CTRL2, 5675 RT5677_GPIO5_FUNC_MASK, 5676 RT5677_GPIO5_FUNC_DMIC); 5677 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2, 5678 RT5677_GPIO5_DIR_MASK, 5679 RT5677_GPIO5_DIR_OUT); 5680 } 5681 5682 if (rt5677->pdata.micbias1_vdd_3v3) 5683 regmap_update_bits(rt5677->regmap, RT5677_MICBIAS, 5684 RT5677_MICBIAS1_CTRL_VDD_MASK, 5685 RT5677_MICBIAS1_CTRL_VDD_3_3V); 5686 5687 rt5677_init_gpio(i2c); 5688 ret = rt5677_init_irq(i2c); 5689 if (ret) 5690 dev_err(&i2c->dev, "Failed to initialize irq: %d\n", ret); 5691 5692 return devm_snd_soc_register_component(&i2c->dev, 5693 &soc_component_dev_rt5677, 5694 rt5677_dai, ARRAY_SIZE(rt5677_dai)); 5695 } 5696 5697 static int rt5677_i2c_remove(struct i2c_client *i2c) 5698 { 5699 rt5677_free_gpio(i2c); 5700 5701 return 0; 5702 } 5703 5704 static struct i2c_driver rt5677_i2c_driver = { 5705 .driver = { 5706 .name = RT5677_DRV_NAME, 5707 .of_match_table = rt5677_of_match, 5708 .acpi_match_table = ACPI_PTR(rt5677_acpi_match), 5709 }, 5710 .probe_new = rt5677_i2c_probe, 5711 .remove = rt5677_i2c_remove, 5712 }; 5713 module_i2c_driver(rt5677_i2c_driver); 5714 5715 MODULE_DESCRIPTION("ASoC RT5677 driver"); 5716 MODULE_AUTHOR("Oder Chiou <oder_chiou@realtek.com>"); 5717 MODULE_LICENSE("GPL v2"); 5718