1 /* 2 * rt5677-spi.c -- RT5677 ALSA SoC audio codec driver 3 * 4 * Copyright 2013 Realtek Semiconductor Corp. 5 * Author: Oder Chiou <oder_chiou@realtek.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11 12 #include <linux/module.h> 13 #include <linux/input.h> 14 #include <linux/spi/spi.h> 15 #include <linux/device.h> 16 #include <linux/init.h> 17 #include <linux/delay.h> 18 #include <linux/interrupt.h> 19 #include <linux/irq.h> 20 #include <linux/slab.h> 21 #include <linux/gpio.h> 22 #include <linux/sched.h> 23 #include <linux/uaccess.h> 24 #include <linux/miscdevice.h> 25 #include <linux/regulator/consumer.h> 26 #include <linux/pm_qos.h> 27 #include <linux/sysfs.h> 28 #include <linux/clk.h> 29 #include <linux/firmware.h> 30 31 #include "rt5677-spi.h" 32 33 #define RT5677_SPI_BURST_LEN 240 34 #define RT5677_SPI_HEADER 5 35 #define RT5677_SPI_FREQ 6000000 36 37 /* The AddressPhase and DataPhase of SPI commands are MSB first on the wire. 38 * DataPhase word size of 16-bit commands is 2 bytes. 39 * DataPhase word size of 32-bit commands is 4 bytes. 40 * DataPhase word size of burst commands is 8 bytes. 41 * The DSP CPU is little-endian. 42 */ 43 #define RT5677_SPI_WRITE_BURST 0x5 44 #define RT5677_SPI_READ_BURST 0x4 45 #define RT5677_SPI_WRITE_32 0x3 46 #define RT5677_SPI_READ_32 0x2 47 #define RT5677_SPI_WRITE_16 0x1 48 #define RT5677_SPI_READ_16 0x0 49 50 static struct spi_device *g_spi; 51 static DEFINE_MUTEX(spi_mutex); 52 53 /* Select a suitable transfer command for the next transfer to ensure 54 * the transfer address is always naturally aligned while minimizing 55 * the total number of transfers required. 56 * 57 * 3 transfer commands are available: 58 * RT5677_SPI_READ/WRITE_16: Transfer 2 bytes 59 * RT5677_SPI_READ/WRITE_32: Transfer 4 bytes 60 * RT5677_SPI_READ/WRITE_BURST: Transfer any multiples of 8 bytes 61 * 62 * For example, reading 260 bytes at 0x60030002 uses the following commands: 63 * 0x60030002 RT5677_SPI_READ_16 2 bytes 64 * 0x60030004 RT5677_SPI_READ_32 4 bytes 65 * 0x60030008 RT5677_SPI_READ_BURST 240 bytes 66 * 0x600300F8 RT5677_SPI_READ_BURST 8 bytes 67 * 0x60030100 RT5677_SPI_READ_32 4 bytes 68 * 0x60030104 RT5677_SPI_READ_16 2 bytes 69 * 70 * Input: 71 * @read: true for read commands; false for write commands 72 * @align: alignment of the next transfer address 73 * @remain: number of bytes remaining to transfer 74 * 75 * Output: 76 * @len: number of bytes to transfer with the selected command 77 * Returns the selected command 78 */ 79 static u8 rt5677_spi_select_cmd(bool read, u32 align, u32 remain, u32 *len) 80 { 81 u8 cmd; 82 83 if (align == 2 || align == 6 || remain == 2) { 84 cmd = RT5677_SPI_READ_16; 85 *len = 2; 86 } else if (align == 4 || remain <= 6) { 87 cmd = RT5677_SPI_READ_32; 88 *len = 4; 89 } else { 90 cmd = RT5677_SPI_READ_BURST; 91 *len = min_t(u32, remain & ~7, RT5677_SPI_BURST_LEN); 92 } 93 return read ? cmd : cmd + 1; 94 } 95 96 /* Copy dstlen bytes from src to dst, while reversing byte order for each word. 97 * If srclen < dstlen, zeros are padded. 98 */ 99 static void rt5677_spi_reverse(u8 *dst, u32 dstlen, const u8 *src, u32 srclen) 100 { 101 u32 w, i, si; 102 u32 word_size = min_t(u32, dstlen, 8); 103 104 for (w = 0; w < dstlen; w += word_size) { 105 for (i = 0; i < word_size; i++) { 106 si = w + word_size - i - 1; 107 dst[w + i] = si < srclen ? src[si] : 0; 108 } 109 } 110 } 111 112 /* Read DSP address space using SPI. addr and len have to be 2-byte aligned. */ 113 int rt5677_spi_read(u32 addr, void *rxbuf, size_t len) 114 { 115 u32 offset; 116 int status = 0; 117 struct spi_transfer t[2]; 118 struct spi_message m; 119 /* +4 bytes is for the DummyPhase following the AddressPhase */ 120 u8 header[RT5677_SPI_HEADER + 4]; 121 u8 body[RT5677_SPI_BURST_LEN]; 122 u8 spi_cmd; 123 u8 *cb = rxbuf; 124 125 if (!g_spi) 126 return -ENODEV; 127 128 if ((addr & 1) || (len & 1)) { 129 dev_err(&g_spi->dev, "Bad read align 0x%x(%zu)\n", addr, len); 130 return -EACCES; 131 } 132 133 memset(t, 0, sizeof(t)); 134 t[0].tx_buf = header; 135 t[0].len = sizeof(header); 136 t[0].speed_hz = RT5677_SPI_FREQ; 137 t[1].rx_buf = body; 138 t[1].speed_hz = RT5677_SPI_FREQ; 139 spi_message_init_with_transfers(&m, t, ARRAY_SIZE(t)); 140 141 for (offset = 0; offset < len; offset += t[1].len) { 142 spi_cmd = rt5677_spi_select_cmd(true, (addr + offset) & 7, 143 len - offset, &t[1].len); 144 145 /* Construct SPI message header */ 146 header[0] = spi_cmd; 147 header[1] = ((addr + offset) & 0xff000000) >> 24; 148 header[2] = ((addr + offset) & 0x00ff0000) >> 16; 149 header[3] = ((addr + offset) & 0x0000ff00) >> 8; 150 header[4] = ((addr + offset) & 0x000000ff) >> 0; 151 152 mutex_lock(&spi_mutex); 153 status |= spi_sync(g_spi, &m); 154 mutex_unlock(&spi_mutex); 155 156 /* Copy data back to caller buffer */ 157 rt5677_spi_reverse(cb + offset, t[1].len, body, t[1].len); 158 } 159 return status; 160 } 161 EXPORT_SYMBOL_GPL(rt5677_spi_read); 162 163 /* Write DSP address space using SPI. addr has to be 2-byte aligned. 164 * If len is not 2-byte aligned, an extra byte of zero is written at the end 165 * as padding. 166 */ 167 int rt5677_spi_write(u32 addr, const void *txbuf, size_t len) 168 { 169 u32 offset, len_with_pad = len; 170 int status = 0; 171 struct spi_transfer t; 172 struct spi_message m; 173 /* +1 byte is for the DummyPhase following the DataPhase */ 174 u8 buf[RT5677_SPI_HEADER + RT5677_SPI_BURST_LEN + 1]; 175 u8 *body = buf + RT5677_SPI_HEADER; 176 u8 spi_cmd; 177 const u8 *cb = txbuf; 178 179 if (!g_spi) 180 return -ENODEV; 181 182 if (addr & 1) { 183 dev_err(&g_spi->dev, "Bad write align 0x%x(%zu)\n", addr, len); 184 return -EACCES; 185 } 186 187 if (len & 1) 188 len_with_pad = len + 1; 189 190 memset(&t, 0, sizeof(t)); 191 t.tx_buf = buf; 192 t.speed_hz = RT5677_SPI_FREQ; 193 spi_message_init_with_transfers(&m, &t, 1); 194 195 for (offset = 0; offset < len_with_pad;) { 196 spi_cmd = rt5677_spi_select_cmd(false, (addr + offset) & 7, 197 len_with_pad - offset, &t.len); 198 199 /* Construct SPI message header */ 200 buf[0] = spi_cmd; 201 buf[1] = ((addr + offset) & 0xff000000) >> 24; 202 buf[2] = ((addr + offset) & 0x00ff0000) >> 16; 203 buf[3] = ((addr + offset) & 0x0000ff00) >> 8; 204 buf[4] = ((addr + offset) & 0x000000ff) >> 0; 205 206 /* Fetch data from caller buffer */ 207 rt5677_spi_reverse(body, t.len, cb + offset, len - offset); 208 offset += t.len; 209 t.len += RT5677_SPI_HEADER + 1; 210 211 mutex_lock(&spi_mutex); 212 status |= spi_sync(g_spi, &m); 213 mutex_unlock(&spi_mutex); 214 } 215 return status; 216 } 217 EXPORT_SYMBOL_GPL(rt5677_spi_write); 218 219 int rt5677_spi_write_firmware(u32 addr, const struct firmware *fw) 220 { 221 return rt5677_spi_write(addr, fw->data, fw->size); 222 } 223 EXPORT_SYMBOL_GPL(rt5677_spi_write_firmware); 224 225 static int rt5677_spi_probe(struct spi_device *spi) 226 { 227 g_spi = spi; 228 return 0; 229 } 230 231 static struct spi_driver rt5677_spi_driver = { 232 .driver = { 233 .name = "rt5677", 234 }, 235 .probe = rt5677_spi_probe, 236 }; 237 module_spi_driver(rt5677_spi_driver); 238 239 MODULE_DESCRIPTION("ASoC RT5677 SPI driver"); 240 MODULE_AUTHOR("Oder Chiou <oder_chiou@realtek.com>"); 241 MODULE_LICENSE("GPL v2"); 242