1 /* 2 * rt5677-spi.c -- RT5677 ALSA SoC audio codec driver 3 * 4 * Copyright 2013 Realtek Semiconductor Corp. 5 * Author: Oder Chiou <oder_chiou@realtek.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11 12 #include <linux/module.h> 13 #include <linux/input.h> 14 #include <linux/spi/spi.h> 15 #include <linux/device.h> 16 #include <linux/init.h> 17 #include <linux/delay.h> 18 #include <linux/interrupt.h> 19 #include <linux/irq.h> 20 #include <linux/slab.h> 21 #include <linux/sched.h> 22 #include <linux/uaccess.h> 23 #include <linux/regulator/consumer.h> 24 #include <linux/pm_qos.h> 25 #include <linux/sysfs.h> 26 #include <linux/clk.h> 27 #include <linux/firmware.h> 28 #include <linux/acpi.h> 29 30 #include "rt5677-spi.h" 31 32 #define RT5677_SPI_BURST_LEN 240 33 #define RT5677_SPI_HEADER 5 34 #define RT5677_SPI_FREQ 6000000 35 36 /* The AddressPhase and DataPhase of SPI commands are MSB first on the wire. 37 * DataPhase word size of 16-bit commands is 2 bytes. 38 * DataPhase word size of 32-bit commands is 4 bytes. 39 * DataPhase word size of burst commands is 8 bytes. 40 * The DSP CPU is little-endian. 41 */ 42 #define RT5677_SPI_WRITE_BURST 0x5 43 #define RT5677_SPI_READ_BURST 0x4 44 #define RT5677_SPI_WRITE_32 0x3 45 #define RT5677_SPI_READ_32 0x2 46 #define RT5677_SPI_WRITE_16 0x1 47 #define RT5677_SPI_READ_16 0x0 48 49 static struct spi_device *g_spi; 50 static DEFINE_MUTEX(spi_mutex); 51 52 /* Select a suitable transfer command for the next transfer to ensure 53 * the transfer address is always naturally aligned while minimizing 54 * the total number of transfers required. 55 * 56 * 3 transfer commands are available: 57 * RT5677_SPI_READ/WRITE_16: Transfer 2 bytes 58 * RT5677_SPI_READ/WRITE_32: Transfer 4 bytes 59 * RT5677_SPI_READ/WRITE_BURST: Transfer any multiples of 8 bytes 60 * 61 * Note: 62 * 16 Bit writes and reads are restricted to the address range 63 * 0x18020000 ~ 0x18021000 64 * 65 * For example, reading 256 bytes at 0x60030004 uses the following commands: 66 * 0x60030004 RT5677_SPI_READ_32 4 bytes 67 * 0x60030008 RT5677_SPI_READ_BURST 240 bytes 68 * 0x600300F8 RT5677_SPI_READ_BURST 8 bytes 69 * 0x60030100 RT5677_SPI_READ_32 4 bytes 70 * 71 * Input: 72 * @read: true for read commands; false for write commands 73 * @align: alignment of the next transfer address 74 * @remain: number of bytes remaining to transfer 75 * 76 * Output: 77 * @len: number of bytes to transfer with the selected command 78 * Returns the selected command 79 */ 80 static u8 rt5677_spi_select_cmd(bool read, u32 align, u32 remain, u32 *len) 81 { 82 u8 cmd; 83 84 if (align == 4 || remain <= 4) { 85 cmd = RT5677_SPI_READ_32; 86 *len = 4; 87 } else { 88 cmd = RT5677_SPI_READ_BURST; 89 *len = (((remain - 1) >> 3) + 1) << 3; 90 *len = min_t(u32, *len, RT5677_SPI_BURST_LEN); 91 } 92 return read ? cmd : cmd + 1; 93 } 94 95 /* Copy dstlen bytes from src to dst, while reversing byte order for each word. 96 * If srclen < dstlen, zeros are padded. 97 */ 98 static void rt5677_spi_reverse(u8 *dst, u32 dstlen, const u8 *src, u32 srclen) 99 { 100 u32 w, i, si; 101 u32 word_size = min_t(u32, dstlen, 8); 102 103 for (w = 0; w < dstlen; w += word_size) { 104 for (i = 0; i < word_size; i++) { 105 si = w + word_size - i - 1; 106 dst[w + i] = si < srclen ? src[si] : 0; 107 } 108 } 109 } 110 111 /* Read DSP address space using SPI. addr and len have to be 4-byte aligned. */ 112 int rt5677_spi_read(u32 addr, void *rxbuf, size_t len) 113 { 114 u32 offset; 115 int status = 0; 116 struct spi_transfer t[2]; 117 struct spi_message m; 118 /* +4 bytes is for the DummyPhase following the AddressPhase */ 119 u8 header[RT5677_SPI_HEADER + 4]; 120 u8 body[RT5677_SPI_BURST_LEN]; 121 u8 spi_cmd; 122 u8 *cb = rxbuf; 123 124 if (!g_spi) 125 return -ENODEV; 126 127 if ((addr & 3) || (len & 3)) { 128 dev_err(&g_spi->dev, "Bad read align 0x%x(%zu)\n", addr, len); 129 return -EACCES; 130 } 131 132 memset(t, 0, sizeof(t)); 133 t[0].tx_buf = header; 134 t[0].len = sizeof(header); 135 t[0].speed_hz = RT5677_SPI_FREQ; 136 t[1].rx_buf = body; 137 t[1].speed_hz = RT5677_SPI_FREQ; 138 spi_message_init_with_transfers(&m, t, ARRAY_SIZE(t)); 139 140 for (offset = 0; offset < len; offset += t[1].len) { 141 spi_cmd = rt5677_spi_select_cmd(true, (addr + offset) & 7, 142 len - offset, &t[1].len); 143 144 /* Construct SPI message header */ 145 header[0] = spi_cmd; 146 header[1] = ((addr + offset) & 0xff000000) >> 24; 147 header[2] = ((addr + offset) & 0x00ff0000) >> 16; 148 header[3] = ((addr + offset) & 0x0000ff00) >> 8; 149 header[4] = ((addr + offset) & 0x000000ff) >> 0; 150 151 mutex_lock(&spi_mutex); 152 status |= spi_sync(g_spi, &m); 153 mutex_unlock(&spi_mutex); 154 155 /* Copy data back to caller buffer */ 156 rt5677_spi_reverse(cb + offset, t[1].len, body, t[1].len); 157 } 158 return status; 159 } 160 EXPORT_SYMBOL_GPL(rt5677_spi_read); 161 162 /* Write DSP address space using SPI. addr has to be 4-byte aligned. 163 * If len is not 4-byte aligned, then extra zeros are written at the end 164 * as padding. 165 */ 166 int rt5677_spi_write(u32 addr, const void *txbuf, size_t len) 167 { 168 u32 offset; 169 int status = 0; 170 struct spi_transfer t; 171 struct spi_message m; 172 /* +1 byte is for the DummyPhase following the DataPhase */ 173 u8 buf[RT5677_SPI_HEADER + RT5677_SPI_BURST_LEN + 1]; 174 u8 *body = buf + RT5677_SPI_HEADER; 175 u8 spi_cmd; 176 const u8 *cb = txbuf; 177 178 if (!g_spi) 179 return -ENODEV; 180 181 if (addr & 3) { 182 dev_err(&g_spi->dev, "Bad write align 0x%x(%zu)\n", addr, len); 183 return -EACCES; 184 } 185 186 memset(&t, 0, sizeof(t)); 187 t.tx_buf = buf; 188 t.speed_hz = RT5677_SPI_FREQ; 189 spi_message_init_with_transfers(&m, &t, 1); 190 191 for (offset = 0; offset < len;) { 192 spi_cmd = rt5677_spi_select_cmd(false, (addr + offset) & 7, 193 len - offset, &t.len); 194 195 /* Construct SPI message header */ 196 buf[0] = spi_cmd; 197 buf[1] = ((addr + offset) & 0xff000000) >> 24; 198 buf[2] = ((addr + offset) & 0x00ff0000) >> 16; 199 buf[3] = ((addr + offset) & 0x0000ff00) >> 8; 200 buf[4] = ((addr + offset) & 0x000000ff) >> 0; 201 202 /* Fetch data from caller buffer */ 203 rt5677_spi_reverse(body, t.len, cb + offset, len - offset); 204 offset += t.len; 205 t.len += RT5677_SPI_HEADER + 1; 206 207 mutex_lock(&spi_mutex); 208 status |= spi_sync(g_spi, &m); 209 mutex_unlock(&spi_mutex); 210 } 211 return status; 212 } 213 EXPORT_SYMBOL_GPL(rt5677_spi_write); 214 215 int rt5677_spi_write_firmware(u32 addr, const struct firmware *fw) 216 { 217 return rt5677_spi_write(addr, fw->data, fw->size); 218 } 219 EXPORT_SYMBOL_GPL(rt5677_spi_write_firmware); 220 221 static int rt5677_spi_probe(struct spi_device *spi) 222 { 223 g_spi = spi; 224 return 0; 225 } 226 227 static const struct acpi_device_id rt5677_spi_acpi_id[] = { 228 { "RT5677AA", 0 }, 229 { } 230 }; 231 MODULE_DEVICE_TABLE(acpi, rt5677_spi_acpi_id); 232 233 static struct spi_driver rt5677_spi_driver = { 234 .driver = { 235 .name = "rt5677", 236 .acpi_match_table = ACPI_PTR(rt5677_spi_acpi_id), 237 }, 238 .probe = rt5677_spi_probe, 239 }; 240 module_spi_driver(rt5677_spi_driver); 241 242 MODULE_DESCRIPTION("ASoC RT5677 SPI driver"); 243 MODULE_AUTHOR("Oder Chiou <oder_chiou@realtek.com>"); 244 MODULE_LICENSE("GPL v2"); 245