1 /* 2 * rt5677-spi.c -- RT5677 ALSA SoC audio codec driver 3 * 4 * Copyright 2013 Realtek Semiconductor Corp. 5 * Author: Oder Chiou <oder_chiou@realtek.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11 12 #include <linux/module.h> 13 #include <linux/input.h> 14 #include <linux/spi/spi.h> 15 #include <linux/device.h> 16 #include <linux/init.h> 17 #include <linux/delay.h> 18 #include <linux/interrupt.h> 19 #include <linux/irq.h> 20 #include <linux/slab.h> 21 #include <linux/gpio.h> 22 #include <linux/sched.h> 23 #include <linux/uaccess.h> 24 #include <linux/regulator/consumer.h> 25 #include <linux/pm_qos.h> 26 #include <linux/sysfs.h> 27 #include <linux/clk.h> 28 #include <linux/firmware.h> 29 30 #include "rt5677-spi.h" 31 32 #define RT5677_SPI_BURST_LEN 240 33 #define RT5677_SPI_HEADER 5 34 #define RT5677_SPI_FREQ 6000000 35 36 /* The AddressPhase and DataPhase of SPI commands are MSB first on the wire. 37 * DataPhase word size of 16-bit commands is 2 bytes. 38 * DataPhase word size of 32-bit commands is 4 bytes. 39 * DataPhase word size of burst commands is 8 bytes. 40 * The DSP CPU is little-endian. 41 */ 42 #define RT5677_SPI_WRITE_BURST 0x5 43 #define RT5677_SPI_READ_BURST 0x4 44 #define RT5677_SPI_WRITE_32 0x3 45 #define RT5677_SPI_READ_32 0x2 46 #define RT5677_SPI_WRITE_16 0x1 47 #define RT5677_SPI_READ_16 0x0 48 49 static struct spi_device *g_spi; 50 static DEFINE_MUTEX(spi_mutex); 51 52 /* Select a suitable transfer command for the next transfer to ensure 53 * the transfer address is always naturally aligned while minimizing 54 * the total number of transfers required. 55 * 56 * 3 transfer commands are available: 57 * RT5677_SPI_READ/WRITE_16: Transfer 2 bytes 58 * RT5677_SPI_READ/WRITE_32: Transfer 4 bytes 59 * RT5677_SPI_READ/WRITE_BURST: Transfer any multiples of 8 bytes 60 * 61 * For example, reading 260 bytes at 0x60030002 uses the following commands: 62 * 0x60030002 RT5677_SPI_READ_16 2 bytes 63 * 0x60030004 RT5677_SPI_READ_32 4 bytes 64 * 0x60030008 RT5677_SPI_READ_BURST 240 bytes 65 * 0x600300F8 RT5677_SPI_READ_BURST 8 bytes 66 * 0x60030100 RT5677_SPI_READ_32 4 bytes 67 * 0x60030104 RT5677_SPI_READ_16 2 bytes 68 * 69 * Input: 70 * @read: true for read commands; false for write commands 71 * @align: alignment of the next transfer address 72 * @remain: number of bytes remaining to transfer 73 * 74 * Output: 75 * @len: number of bytes to transfer with the selected command 76 * Returns the selected command 77 */ 78 static u8 rt5677_spi_select_cmd(bool read, u32 align, u32 remain, u32 *len) 79 { 80 u8 cmd; 81 82 if (align == 2 || align == 6 || remain == 2) { 83 cmd = RT5677_SPI_READ_16; 84 *len = 2; 85 } else if (align == 4 || remain <= 6) { 86 cmd = RT5677_SPI_READ_32; 87 *len = 4; 88 } else { 89 cmd = RT5677_SPI_READ_BURST; 90 *len = min_t(u32, remain & ~7, RT5677_SPI_BURST_LEN); 91 } 92 return read ? cmd : cmd + 1; 93 } 94 95 /* Copy dstlen bytes from src to dst, while reversing byte order for each word. 96 * If srclen < dstlen, zeros are padded. 97 */ 98 static void rt5677_spi_reverse(u8 *dst, u32 dstlen, const u8 *src, u32 srclen) 99 { 100 u32 w, i, si; 101 u32 word_size = min_t(u32, dstlen, 8); 102 103 for (w = 0; w < dstlen; w += word_size) { 104 for (i = 0; i < word_size; i++) { 105 si = w + word_size - i - 1; 106 dst[w + i] = si < srclen ? src[si] : 0; 107 } 108 } 109 } 110 111 /* Read DSP address space using SPI. addr and len have to be 2-byte aligned. */ 112 int rt5677_spi_read(u32 addr, void *rxbuf, size_t len) 113 { 114 u32 offset; 115 int status = 0; 116 struct spi_transfer t[2]; 117 struct spi_message m; 118 /* +4 bytes is for the DummyPhase following the AddressPhase */ 119 u8 header[RT5677_SPI_HEADER + 4]; 120 u8 body[RT5677_SPI_BURST_LEN]; 121 u8 spi_cmd; 122 u8 *cb = rxbuf; 123 124 if (!g_spi) 125 return -ENODEV; 126 127 if ((addr & 1) || (len & 1)) { 128 dev_err(&g_spi->dev, "Bad read align 0x%x(%zu)\n", addr, len); 129 return -EACCES; 130 } 131 132 memset(t, 0, sizeof(t)); 133 t[0].tx_buf = header; 134 t[0].len = sizeof(header); 135 t[0].speed_hz = RT5677_SPI_FREQ; 136 t[1].rx_buf = body; 137 t[1].speed_hz = RT5677_SPI_FREQ; 138 spi_message_init_with_transfers(&m, t, ARRAY_SIZE(t)); 139 140 for (offset = 0; offset < len; offset += t[1].len) { 141 spi_cmd = rt5677_spi_select_cmd(true, (addr + offset) & 7, 142 len - offset, &t[1].len); 143 144 /* Construct SPI message header */ 145 header[0] = spi_cmd; 146 header[1] = ((addr + offset) & 0xff000000) >> 24; 147 header[2] = ((addr + offset) & 0x00ff0000) >> 16; 148 header[3] = ((addr + offset) & 0x0000ff00) >> 8; 149 header[4] = ((addr + offset) & 0x000000ff) >> 0; 150 151 mutex_lock(&spi_mutex); 152 status |= spi_sync(g_spi, &m); 153 mutex_unlock(&spi_mutex); 154 155 /* Copy data back to caller buffer */ 156 rt5677_spi_reverse(cb + offset, t[1].len, body, t[1].len); 157 } 158 return status; 159 } 160 EXPORT_SYMBOL_GPL(rt5677_spi_read); 161 162 /* Write DSP address space using SPI. addr has to be 2-byte aligned. 163 * If len is not 2-byte aligned, an extra byte of zero is written at the end 164 * as padding. 165 */ 166 int rt5677_spi_write(u32 addr, const void *txbuf, size_t len) 167 { 168 u32 offset, len_with_pad = len; 169 int status = 0; 170 struct spi_transfer t; 171 struct spi_message m; 172 /* +1 byte is for the DummyPhase following the DataPhase */ 173 u8 buf[RT5677_SPI_HEADER + RT5677_SPI_BURST_LEN + 1]; 174 u8 *body = buf + RT5677_SPI_HEADER; 175 u8 spi_cmd; 176 const u8 *cb = txbuf; 177 178 if (!g_spi) 179 return -ENODEV; 180 181 if (addr & 1) { 182 dev_err(&g_spi->dev, "Bad write align 0x%x(%zu)\n", addr, len); 183 return -EACCES; 184 } 185 186 if (len & 1) 187 len_with_pad = len + 1; 188 189 memset(&t, 0, sizeof(t)); 190 t.tx_buf = buf; 191 t.speed_hz = RT5677_SPI_FREQ; 192 spi_message_init_with_transfers(&m, &t, 1); 193 194 for (offset = 0; offset < len_with_pad;) { 195 spi_cmd = rt5677_spi_select_cmd(false, (addr + offset) & 7, 196 len_with_pad - offset, &t.len); 197 198 /* Construct SPI message header */ 199 buf[0] = spi_cmd; 200 buf[1] = ((addr + offset) & 0xff000000) >> 24; 201 buf[2] = ((addr + offset) & 0x00ff0000) >> 16; 202 buf[3] = ((addr + offset) & 0x0000ff00) >> 8; 203 buf[4] = ((addr + offset) & 0x000000ff) >> 0; 204 205 /* Fetch data from caller buffer */ 206 rt5677_spi_reverse(body, t.len, cb + offset, len - offset); 207 offset += t.len; 208 t.len += RT5677_SPI_HEADER + 1; 209 210 mutex_lock(&spi_mutex); 211 status |= spi_sync(g_spi, &m); 212 mutex_unlock(&spi_mutex); 213 } 214 return status; 215 } 216 EXPORT_SYMBOL_GPL(rt5677_spi_write); 217 218 int rt5677_spi_write_firmware(u32 addr, const struct firmware *fw) 219 { 220 return rt5677_spi_write(addr, fw->data, fw->size); 221 } 222 EXPORT_SYMBOL_GPL(rt5677_spi_write_firmware); 223 224 static int rt5677_spi_probe(struct spi_device *spi) 225 { 226 g_spi = spi; 227 return 0; 228 } 229 230 static struct spi_driver rt5677_spi_driver = { 231 .driver = { 232 .name = "rt5677", 233 }, 234 .probe = rt5677_spi_probe, 235 }; 236 module_spi_driver(rt5677_spi_driver); 237 238 MODULE_DESCRIPTION("ASoC RT5677 SPI driver"); 239 MODULE_AUTHOR("Oder Chiou <oder_chiou@realtek.com>"); 240 MODULE_LICENSE("GPL v2"); 241