1 /* 2 * rt5677-spi.c -- RT5677 ALSA SoC audio codec driver 3 * 4 * Copyright 2013 Realtek Semiconductor Corp. 5 * Author: Oder Chiou <oder_chiou@realtek.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11 12 #include <linux/module.h> 13 #include <linux/input.h> 14 #include <linux/spi/spi.h> 15 #include <linux/device.h> 16 #include <linux/init.h> 17 #include <linux/delay.h> 18 #include <linux/interrupt.h> 19 #include <linux/irq.h> 20 #include <linux/slab.h> 21 #include <linux/sched.h> 22 #include <linux/uaccess.h> 23 #include <linux/regulator/consumer.h> 24 #include <linux/pm_qos.h> 25 #include <linux/sysfs.h> 26 #include <linux/clk.h> 27 #include <linux/firmware.h> 28 29 #include "rt5677-spi.h" 30 31 #define RT5677_SPI_BURST_LEN 240 32 #define RT5677_SPI_HEADER 5 33 #define RT5677_SPI_FREQ 6000000 34 35 /* The AddressPhase and DataPhase of SPI commands are MSB first on the wire. 36 * DataPhase word size of 16-bit commands is 2 bytes. 37 * DataPhase word size of 32-bit commands is 4 bytes. 38 * DataPhase word size of burst commands is 8 bytes. 39 * The DSP CPU is little-endian. 40 */ 41 #define RT5677_SPI_WRITE_BURST 0x5 42 #define RT5677_SPI_READ_BURST 0x4 43 #define RT5677_SPI_WRITE_32 0x3 44 #define RT5677_SPI_READ_32 0x2 45 #define RT5677_SPI_WRITE_16 0x1 46 #define RT5677_SPI_READ_16 0x0 47 48 static struct spi_device *g_spi; 49 static DEFINE_MUTEX(spi_mutex); 50 51 /* Select a suitable transfer command for the next transfer to ensure 52 * the transfer address is always naturally aligned while minimizing 53 * the total number of transfers required. 54 * 55 * 3 transfer commands are available: 56 * RT5677_SPI_READ/WRITE_16: Transfer 2 bytes 57 * RT5677_SPI_READ/WRITE_32: Transfer 4 bytes 58 * RT5677_SPI_READ/WRITE_BURST: Transfer any multiples of 8 bytes 59 * 60 * For example, reading 260 bytes at 0x60030002 uses the following commands: 61 * 0x60030002 RT5677_SPI_READ_16 2 bytes 62 * 0x60030004 RT5677_SPI_READ_32 4 bytes 63 * 0x60030008 RT5677_SPI_READ_BURST 240 bytes 64 * 0x600300F8 RT5677_SPI_READ_BURST 8 bytes 65 * 0x60030100 RT5677_SPI_READ_32 4 bytes 66 * 0x60030104 RT5677_SPI_READ_16 2 bytes 67 * 68 * Input: 69 * @read: true for read commands; false for write commands 70 * @align: alignment of the next transfer address 71 * @remain: number of bytes remaining to transfer 72 * 73 * Output: 74 * @len: number of bytes to transfer with the selected command 75 * Returns the selected command 76 */ 77 static u8 rt5677_spi_select_cmd(bool read, u32 align, u32 remain, u32 *len) 78 { 79 u8 cmd; 80 81 if (align == 2 || align == 6 || remain == 2) { 82 cmd = RT5677_SPI_READ_16; 83 *len = 2; 84 } else if (align == 4 || remain <= 6) { 85 cmd = RT5677_SPI_READ_32; 86 *len = 4; 87 } else { 88 cmd = RT5677_SPI_READ_BURST; 89 *len = min_t(u32, remain & ~7, RT5677_SPI_BURST_LEN); 90 } 91 return read ? cmd : cmd + 1; 92 } 93 94 /* Copy dstlen bytes from src to dst, while reversing byte order for each word. 95 * If srclen < dstlen, zeros are padded. 96 */ 97 static void rt5677_spi_reverse(u8 *dst, u32 dstlen, const u8 *src, u32 srclen) 98 { 99 u32 w, i, si; 100 u32 word_size = min_t(u32, dstlen, 8); 101 102 for (w = 0; w < dstlen; w += word_size) { 103 for (i = 0; i < word_size; i++) { 104 si = w + word_size - i - 1; 105 dst[w + i] = si < srclen ? src[si] : 0; 106 } 107 } 108 } 109 110 /* Read DSP address space using SPI. addr and len have to be 2-byte aligned. */ 111 int rt5677_spi_read(u32 addr, void *rxbuf, size_t len) 112 { 113 u32 offset; 114 int status = 0; 115 struct spi_transfer t[2]; 116 struct spi_message m; 117 /* +4 bytes is for the DummyPhase following the AddressPhase */ 118 u8 header[RT5677_SPI_HEADER + 4]; 119 u8 body[RT5677_SPI_BURST_LEN]; 120 u8 spi_cmd; 121 u8 *cb = rxbuf; 122 123 if (!g_spi) 124 return -ENODEV; 125 126 if ((addr & 1) || (len & 1)) { 127 dev_err(&g_spi->dev, "Bad read align 0x%x(%zu)\n", addr, len); 128 return -EACCES; 129 } 130 131 memset(t, 0, sizeof(t)); 132 t[0].tx_buf = header; 133 t[0].len = sizeof(header); 134 t[0].speed_hz = RT5677_SPI_FREQ; 135 t[1].rx_buf = body; 136 t[1].speed_hz = RT5677_SPI_FREQ; 137 spi_message_init_with_transfers(&m, t, ARRAY_SIZE(t)); 138 139 for (offset = 0; offset < len; offset += t[1].len) { 140 spi_cmd = rt5677_spi_select_cmd(true, (addr + offset) & 7, 141 len - offset, &t[1].len); 142 143 /* Construct SPI message header */ 144 header[0] = spi_cmd; 145 header[1] = ((addr + offset) & 0xff000000) >> 24; 146 header[2] = ((addr + offset) & 0x00ff0000) >> 16; 147 header[3] = ((addr + offset) & 0x0000ff00) >> 8; 148 header[4] = ((addr + offset) & 0x000000ff) >> 0; 149 150 mutex_lock(&spi_mutex); 151 status |= spi_sync(g_spi, &m); 152 mutex_unlock(&spi_mutex); 153 154 /* Copy data back to caller buffer */ 155 rt5677_spi_reverse(cb + offset, t[1].len, body, t[1].len); 156 } 157 return status; 158 } 159 EXPORT_SYMBOL_GPL(rt5677_spi_read); 160 161 /* Write DSP address space using SPI. addr has to be 2-byte aligned. 162 * If len is not 2-byte aligned, an extra byte of zero is written at the end 163 * as padding. 164 */ 165 int rt5677_spi_write(u32 addr, const void *txbuf, size_t len) 166 { 167 u32 offset, len_with_pad = len; 168 int status = 0; 169 struct spi_transfer t; 170 struct spi_message m; 171 /* +1 byte is for the DummyPhase following the DataPhase */ 172 u8 buf[RT5677_SPI_HEADER + RT5677_SPI_BURST_LEN + 1]; 173 u8 *body = buf + RT5677_SPI_HEADER; 174 u8 spi_cmd; 175 const u8 *cb = txbuf; 176 177 if (!g_spi) 178 return -ENODEV; 179 180 if (addr & 1) { 181 dev_err(&g_spi->dev, "Bad write align 0x%x(%zu)\n", addr, len); 182 return -EACCES; 183 } 184 185 if (len & 1) 186 len_with_pad = len + 1; 187 188 memset(&t, 0, sizeof(t)); 189 t.tx_buf = buf; 190 t.speed_hz = RT5677_SPI_FREQ; 191 spi_message_init_with_transfers(&m, &t, 1); 192 193 for (offset = 0; offset < len_with_pad;) { 194 spi_cmd = rt5677_spi_select_cmd(false, (addr + offset) & 7, 195 len_with_pad - offset, &t.len); 196 197 /* Construct SPI message header */ 198 buf[0] = spi_cmd; 199 buf[1] = ((addr + offset) & 0xff000000) >> 24; 200 buf[2] = ((addr + offset) & 0x00ff0000) >> 16; 201 buf[3] = ((addr + offset) & 0x0000ff00) >> 8; 202 buf[4] = ((addr + offset) & 0x000000ff) >> 0; 203 204 /* Fetch data from caller buffer */ 205 rt5677_spi_reverse(body, t.len, cb + offset, len - offset); 206 offset += t.len; 207 t.len += RT5677_SPI_HEADER + 1; 208 209 mutex_lock(&spi_mutex); 210 status |= spi_sync(g_spi, &m); 211 mutex_unlock(&spi_mutex); 212 } 213 return status; 214 } 215 EXPORT_SYMBOL_GPL(rt5677_spi_write); 216 217 int rt5677_spi_write_firmware(u32 addr, const struct firmware *fw) 218 { 219 return rt5677_spi_write(addr, fw->data, fw->size); 220 } 221 EXPORT_SYMBOL_GPL(rt5677_spi_write_firmware); 222 223 static int rt5677_spi_probe(struct spi_device *spi) 224 { 225 g_spi = spi; 226 return 0; 227 } 228 229 static struct spi_driver rt5677_spi_driver = { 230 .driver = { 231 .name = "rt5677", 232 }, 233 .probe = rt5677_spi_probe, 234 }; 235 module_spi_driver(rt5677_spi_driver); 236 237 MODULE_DESCRIPTION("ASoC RT5677 SPI driver"); 238 MODULE_AUTHOR("Oder Chiou <oder_chiou@realtek.com>"); 239 MODULE_LICENSE("GPL v2"); 240