1 /* 2 * rt5670.h -- RT5670 ALSA SoC audio driver 3 * 4 * Copyright 2014 Realtek Microelectronics 5 * Author: Bard Liao <bardliao@realtek.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11 12 #ifndef __RT5670_H__ 13 #define __RT5670_H__ 14 15 #include <sound/rt5670.h> 16 17 /* Info */ 18 #define RT5670_RESET 0x00 19 #define RT5670_VENDOR_ID 0xfd 20 #define RT5670_VENDOR_ID1 0xfe 21 #define RT5670_VENDOR_ID2 0xff 22 /* I/O - Output */ 23 #define RT5670_HP_VOL 0x02 24 #define RT5670_LOUT1 0x03 25 /* I/O - Input */ 26 #define RT5670_CJ_CTRL1 0x0a 27 #define RT5670_CJ_CTRL2 0x0b 28 #define RT5670_CJ_CTRL3 0x0c 29 #define RT5670_IN2 0x0e 30 #define RT5670_INL1_INR1_VOL 0x0f 31 /* I/O - ADC/DAC/DMIC */ 32 #define RT5670_DAC1_DIG_VOL 0x19 33 #define RT5670_DAC2_DIG_VOL 0x1a 34 #define RT5670_DAC_CTRL 0x1b 35 #define RT5670_STO1_ADC_DIG_VOL 0x1c 36 #define RT5670_MONO_ADC_DIG_VOL 0x1d 37 #define RT5670_ADC_BST_VOL1 0x1e 38 #define RT5670_STO2_ADC_DIG_VOL 0x1f 39 /* Mixer - D-D */ 40 #define RT5670_ADC_BST_VOL2 0x20 41 #define RT5670_STO2_ADC_MIXER 0x26 42 #define RT5670_STO1_ADC_MIXER 0x27 43 #define RT5670_MONO_ADC_MIXER 0x28 44 #define RT5670_AD_DA_MIXER 0x29 45 #define RT5670_STO_DAC_MIXER 0x2a 46 #define RT5670_DD_MIXER 0x2b 47 #define RT5670_DIG_MIXER 0x2c 48 #define RT5670_DSP_PATH1 0x2d 49 #define RT5670_DSP_PATH2 0x2e 50 #define RT5670_DIG_INF1_DATA 0x2f 51 #define RT5670_DIG_INF2_DATA 0x30 52 /* Mixer - PDM */ 53 #define RT5670_PDM_OUT_CTRL 0x31 54 #define RT5670_PDM_DATA_CTRL1 0x32 55 #define RT5670_PDM1_DATA_CTRL2 0x33 56 #define RT5670_PDM1_DATA_CTRL3 0x34 57 #define RT5670_PDM1_DATA_CTRL4 0x35 58 #define RT5670_PDM2_DATA_CTRL2 0x36 59 #define RT5670_PDM2_DATA_CTRL3 0x37 60 #define RT5670_PDM2_DATA_CTRL4 0x38 61 /* Mixer - ADC */ 62 #define RT5670_REC_L1_MIXER 0x3b 63 #define RT5670_REC_L2_MIXER 0x3c 64 #define RT5670_REC_R1_MIXER 0x3d 65 #define RT5670_REC_R2_MIXER 0x3e 66 /* Mixer - DAC */ 67 #define RT5670_HPO_MIXER 0x45 68 #define RT5670_MONO_MIXER 0x4c 69 #define RT5670_OUT_L1_MIXER 0x4f 70 #define RT5670_OUT_R1_MIXER 0x52 71 #define RT5670_LOUT_MIXER 0x53 72 /* Power */ 73 #define RT5670_PWR_DIG1 0x61 74 #define RT5670_PWR_DIG2 0x62 75 #define RT5670_PWR_ANLG1 0x63 76 #define RT5670_PWR_ANLG2 0x64 77 #define RT5670_PWR_MIXER 0x65 78 #define RT5670_PWR_VOL 0x66 79 /* Private Register Control */ 80 #define RT5670_PRIV_INDEX 0x6a 81 #define RT5670_PRIV_DATA 0x6c 82 /* Format - ADC/DAC */ 83 #define RT5670_I2S4_SDP 0x6f 84 #define RT5670_I2S1_SDP 0x70 85 #define RT5670_I2S2_SDP 0x71 86 #define RT5670_I2S3_SDP 0x72 87 #define RT5670_ADDA_CLK1 0x73 88 #define RT5670_ADDA_CLK2 0x74 89 #define RT5670_DMIC_CTRL1 0x75 90 #define RT5670_DMIC_CTRL2 0x76 91 /* Format - TDM Control */ 92 #define RT5670_TDM_CTRL_1 0x77 93 #define RT5670_TDM_CTRL_2 0x78 94 #define RT5670_TDM_CTRL_3 0x79 95 96 /* Function - Analog */ 97 #define RT5670_DSP_CLK 0x7f 98 #define RT5670_GLB_CLK 0x80 99 #define RT5670_PLL_CTRL1 0x81 100 #define RT5670_PLL_CTRL2 0x82 101 #define RT5670_ASRC_1 0x83 102 #define RT5670_ASRC_2 0x84 103 #define RT5670_ASRC_3 0x85 104 #define RT5670_ASRC_4 0x86 105 #define RT5670_ASRC_5 0x87 106 #define RT5670_ASRC_7 0x89 107 #define RT5670_ASRC_8 0x8a 108 #define RT5670_ASRC_9 0x8b 109 #define RT5670_ASRC_10 0x8c 110 #define RT5670_ASRC_11 0x8d 111 #define RT5670_DEPOP_M1 0x8e 112 #define RT5670_DEPOP_M2 0x8f 113 #define RT5670_DEPOP_M3 0x90 114 #define RT5670_CHARGE_PUMP 0x91 115 #define RT5670_MICBIAS 0x93 116 #define RT5670_A_JD_CTRL1 0x94 117 #define RT5670_A_JD_CTRL2 0x95 118 #define RT5670_ASRC_12 0x97 119 #define RT5670_ASRC_13 0x98 120 #define RT5670_ASRC_14 0x99 121 #define RT5670_VAD_CTRL1 0x9a 122 #define RT5670_VAD_CTRL2 0x9b 123 #define RT5670_VAD_CTRL3 0x9c 124 #define RT5670_VAD_CTRL4 0x9d 125 #define RT5670_VAD_CTRL5 0x9e 126 /* Function - Digital */ 127 #define RT5670_ADC_EQ_CTRL1 0xae 128 #define RT5670_ADC_EQ_CTRL2 0xaf 129 #define RT5670_EQ_CTRL1 0xb0 130 #define RT5670_EQ_CTRL2 0xb1 131 #define RT5670_ALC_DRC_CTRL1 0xb2 132 #define RT5670_ALC_DRC_CTRL2 0xb3 133 #define RT5670_ALC_CTRL_1 0xb4 134 #define RT5670_ALC_CTRL_2 0xb5 135 #define RT5670_ALC_CTRL_3 0xb6 136 #define RT5670_ALC_CTRL_4 0xb7 137 #define RT5670_JD_CTRL 0xbb 138 #define RT5670_IRQ_CTRL1 0xbd 139 #define RT5670_IRQ_CTRL2 0xbe 140 #define RT5670_INT_IRQ_ST 0xbf 141 #define RT5670_GPIO_CTRL1 0xc0 142 #define RT5670_GPIO_CTRL2 0xc1 143 #define RT5670_GPIO_CTRL3 0xc2 144 #define RT5670_SCRABBLE_FUN 0xcd 145 #define RT5670_SCRABBLE_CTRL 0xce 146 #define RT5670_BASE_BACK 0xcf 147 #define RT5670_MP3_PLUS1 0xd0 148 #define RT5670_MP3_PLUS2 0xd1 149 #define RT5670_ADJ_HPF1 0xd3 150 #define RT5670_ADJ_HPF2 0xd4 151 #define RT5670_HP_CALIB_AMP_DET 0xd6 152 #define RT5670_SV_ZCD1 0xd9 153 #define RT5670_SV_ZCD2 0xda 154 #define RT5670_IL_CMD 0xdb 155 #define RT5670_IL_CMD2 0xdc 156 #define RT5670_IL_CMD3 0xdd 157 #define RT5670_DRC_HL_CTRL1 0xe6 158 #define RT5670_DRC_HL_CTRL2 0xe7 159 #define RT5670_ADC_MONO_HP_CTRL1 0xec 160 #define RT5670_ADC_MONO_HP_CTRL2 0xed 161 #define RT5670_ADC_STO2_HP_CTRL1 0xee 162 #define RT5670_ADC_STO2_HP_CTRL2 0xef 163 #define RT5670_JD_CTRL3 0xf8 164 #define RT5670_JD_CTRL4 0xf9 165 /* General Control */ 166 #define RT5670_DIG_MISC 0xfa 167 #define RT5670_GEN_CTRL2 0xfb 168 #define RT5670_GEN_CTRL3 0xfc 169 170 171 /* Index of Codec Private Register definition */ 172 #define RT5670_DIG_VOL 0x00 173 #define RT5670_PR_ALC_CTRL_1 0x01 174 #define RT5670_PR_ALC_CTRL_2 0x02 175 #define RT5670_PR_ALC_CTRL_3 0x03 176 #define RT5670_PR_ALC_CTRL_4 0x04 177 #define RT5670_PR_ALC_CTRL_5 0x05 178 #define RT5670_PR_ALC_CTRL_6 0x06 179 #define RT5670_BIAS_CUR1 0x12 180 #define RT5670_BIAS_CUR3 0x14 181 #define RT5670_CLSD_INT_REG1 0x1c 182 #define RT5670_MAMP_INT_REG2 0x37 183 #define RT5670_CHOP_DAC_ADC 0x3d 184 #define RT5670_MIXER_INT_REG 0x3f 185 #define RT5670_3D_SPK 0x63 186 #define RT5670_WND_1 0x6c 187 #define RT5670_WND_2 0x6d 188 #define RT5670_WND_3 0x6e 189 #define RT5670_WND_4 0x6f 190 #define RT5670_WND_5 0x70 191 #define RT5670_WND_8 0x73 192 #define RT5670_DIP_SPK_INF 0x75 193 #define RT5670_HP_DCC_INT1 0x77 194 #define RT5670_EQ_BW_LOP 0xa0 195 #define RT5670_EQ_GN_LOP 0xa1 196 #define RT5670_EQ_FC_BP1 0xa2 197 #define RT5670_EQ_BW_BP1 0xa3 198 #define RT5670_EQ_GN_BP1 0xa4 199 #define RT5670_EQ_FC_BP2 0xa5 200 #define RT5670_EQ_BW_BP2 0xa6 201 #define RT5670_EQ_GN_BP2 0xa7 202 #define RT5670_EQ_FC_BP3 0xa8 203 #define RT5670_EQ_BW_BP3 0xa9 204 #define RT5670_EQ_GN_BP3 0xaa 205 #define RT5670_EQ_FC_BP4 0xab 206 #define RT5670_EQ_BW_BP4 0xac 207 #define RT5670_EQ_GN_BP4 0xad 208 #define RT5670_EQ_FC_HIP1 0xae 209 #define RT5670_EQ_GN_HIP1 0xaf 210 #define RT5670_EQ_FC_HIP2 0xb0 211 #define RT5670_EQ_BW_HIP2 0xb1 212 #define RT5670_EQ_GN_HIP2 0xb2 213 #define RT5670_EQ_PRE_VOL 0xb3 214 #define RT5670_EQ_PST_VOL 0xb4 215 216 217 /* global definition */ 218 #define RT5670_L_MUTE (0x1 << 15) 219 #define RT5670_L_MUTE_SFT 15 220 #define RT5670_VOL_L_MUTE (0x1 << 14) 221 #define RT5670_VOL_L_SFT 14 222 #define RT5670_R_MUTE (0x1 << 7) 223 #define RT5670_R_MUTE_SFT 7 224 #define RT5670_VOL_R_MUTE (0x1 << 6) 225 #define RT5670_VOL_R_SFT 6 226 #define RT5670_L_VOL_MASK (0x3f << 8) 227 #define RT5670_L_VOL_SFT 8 228 #define RT5670_R_VOL_MASK (0x3f) 229 #define RT5670_R_VOL_SFT 0 230 231 /* SW Reset & Device ID (0x00) */ 232 #define RT5670_ID_MASK (0x3 << 1) 233 #define RT5670_ID_5670 (0x0 << 1) 234 #define RT5670_ID_5672 (0x1 << 1) 235 #define RT5670_ID_5671 (0x2 << 1) 236 237 /* Combo Jack Control 1 (0x0a) */ 238 #define RT5670_CBJ_BST1_MASK (0xf << 12) 239 #define RT5670_CBJ_BST1_SFT (12) 240 #define RT5670_CBJ_JD_HP_EN (0x1 << 9) 241 #define RT5670_CBJ_JD_MIC_EN (0x1 << 8) 242 #define RT5670_CBJ_BST1_EN (0x1 << 2) 243 244 /* Combo Jack Control 1 (0x0b) */ 245 #define RT5670_CBJ_MN_JD (0x1 << 12) 246 #define RT5670_CAPLESS_EN (0x1 << 11) 247 #define RT5670_CBJ_DET_MODE (0x1 << 7) 248 249 /* IN2 Control (0x0e) */ 250 #define RT5670_BST_MASK1 (0xf<<12) 251 #define RT5670_BST_SFT1 12 252 #define RT5670_BST_MASK2 (0xf<<8) 253 #define RT5670_BST_SFT2 8 254 #define RT5670_IN_DF1 (0x1 << 7) 255 #define RT5670_IN_SFT1 7 256 #define RT5670_IN_DF2 (0x1 << 6) 257 #define RT5670_IN_SFT2 6 258 259 /* INL and INR Volume Control (0x0f) */ 260 #define RT5670_INL_SEL_MASK (0x1 << 15) 261 #define RT5670_INL_SEL_SFT 15 262 #define RT5670_INL_SEL_IN4P (0x0 << 15) 263 #define RT5670_INL_SEL_MONOP (0x1 << 15) 264 #define RT5670_INL_VOL_MASK (0x1f << 8) 265 #define RT5670_INL_VOL_SFT 8 266 #define RT5670_INR_SEL_MASK (0x1 << 7) 267 #define RT5670_INR_SEL_SFT 7 268 #define RT5670_INR_SEL_IN4N (0x0 << 7) 269 #define RT5670_INR_SEL_MONON (0x1 << 7) 270 #define RT5670_INR_VOL_MASK (0x1f) 271 #define RT5670_INR_VOL_SFT 0 272 273 /* Sidetone Control (0x18) */ 274 #define RT5670_ST_SEL_MASK (0x7 << 9) 275 #define RT5670_ST_SEL_SFT 9 276 #define RT5670_M_ST_DACR2 (0x1 << 8) 277 #define RT5670_M_ST_DACR2_SFT 8 278 #define RT5670_M_ST_DACL2 (0x1 << 7) 279 #define RT5670_M_ST_DACL2_SFT 7 280 #define RT5670_ST_EN (0x1 << 6) 281 #define RT5670_ST_EN_SFT 6 282 283 /* DAC1 Digital Volume (0x19) */ 284 #define RT5670_DAC_L1_VOL_MASK (0xff << 8) 285 #define RT5670_DAC_L1_VOL_SFT 8 286 #define RT5670_DAC_R1_VOL_MASK (0xff) 287 #define RT5670_DAC_R1_VOL_SFT 0 288 289 /* DAC2 Digital Volume (0x1a) */ 290 #define RT5670_DAC_L2_VOL_MASK (0xff << 8) 291 #define RT5670_DAC_L2_VOL_SFT 8 292 #define RT5670_DAC_R2_VOL_MASK (0xff) 293 #define RT5670_DAC_R2_VOL_SFT 0 294 295 /* DAC2 Control (0x1b) */ 296 #define RT5670_M_DAC_L2_VOL (0x1 << 13) 297 #define RT5670_M_DAC_L2_VOL_SFT 13 298 #define RT5670_M_DAC_R2_VOL (0x1 << 12) 299 #define RT5670_M_DAC_R2_VOL_SFT 12 300 #define RT5670_DAC2_L_SEL_MASK (0x7 << 4) 301 #define RT5670_DAC2_L_SEL_SFT 4 302 #define RT5670_DAC2_R_SEL_MASK (0x7 << 0) 303 #define RT5670_DAC2_R_SEL_SFT 0 304 305 /* ADC Digital Volume Control (0x1c) */ 306 #define RT5670_ADC_L_VOL_MASK (0x7f << 8) 307 #define RT5670_ADC_L_VOL_SFT 8 308 #define RT5670_ADC_R_VOL_MASK (0x7f) 309 #define RT5670_ADC_R_VOL_SFT 0 310 311 /* Mono ADC Digital Volume Control (0x1d) */ 312 #define RT5670_MONO_ADC_L_VOL_MASK (0x7f << 8) 313 #define RT5670_MONO_ADC_L_VOL_SFT 8 314 #define RT5670_MONO_ADC_R_VOL_MASK (0x7f) 315 #define RT5670_MONO_ADC_R_VOL_SFT 0 316 317 /* ADC Boost Volume Control (0x1e) */ 318 #define RT5670_STO1_ADC_L_BST_MASK (0x3 << 14) 319 #define RT5670_STO1_ADC_L_BST_SFT 14 320 #define RT5670_STO1_ADC_R_BST_MASK (0x3 << 12) 321 #define RT5670_STO1_ADC_R_BST_SFT 12 322 #define RT5670_STO1_ADC_COMP_MASK (0x3 << 10) 323 #define RT5670_STO1_ADC_COMP_SFT 10 324 #define RT5670_STO2_ADC_L_BST_MASK (0x3 << 8) 325 #define RT5670_STO2_ADC_L_BST_SFT 8 326 #define RT5670_STO2_ADC_R_BST_MASK (0x3 << 6) 327 #define RT5670_STO2_ADC_R_BST_SFT 6 328 #define RT5670_STO2_ADC_COMP_MASK (0x3 << 4) 329 #define RT5670_STO2_ADC_COMP_SFT 4 330 331 /* Stereo2 ADC Mixer Control (0x26) */ 332 #define RT5670_STO2_ADC_SRC_MASK (0x1 << 15) 333 #define RT5670_STO2_ADC_SRC_SFT 15 334 335 /* Stereo ADC Mixer Control (0x26 0x27) */ 336 #define RT5670_M_ADC_L1 (0x1 << 14) 337 #define RT5670_M_ADC_L1_SFT 14 338 #define RT5670_M_ADC_L2 (0x1 << 13) 339 #define RT5670_M_ADC_L2_SFT 13 340 #define RT5670_ADC_1_SRC_MASK (0x1 << 12) 341 #define RT5670_ADC_1_SRC_SFT 12 342 #define RT5670_ADC_1_SRC_ADC (0x1 << 12) 343 #define RT5670_ADC_1_SRC_DACMIX (0x0 << 12) 344 #define RT5670_ADC_2_SRC_MASK (0x1 << 11) 345 #define RT5670_ADC_2_SRC_SFT 11 346 #define RT5670_ADC_SRC_MASK (0x1 << 10) 347 #define RT5670_ADC_SRC_SFT 10 348 #define RT5670_DMIC_SRC_MASK (0x3 << 8) 349 #define RT5670_DMIC_SRC_SFT 8 350 #define RT5670_M_ADC_R1 (0x1 << 6) 351 #define RT5670_M_ADC_R1_SFT 6 352 #define RT5670_M_ADC_R2 (0x1 << 5) 353 #define RT5670_M_ADC_R2_SFT 5 354 #define RT5670_DMIC3_SRC_MASK (0x1 << 1) 355 #define RT5670_DMIC3_SRC_SFT 0 356 357 /* Mono ADC Mixer Control (0x28) */ 358 #define RT5670_M_MONO_ADC_L1 (0x1 << 14) 359 #define RT5670_M_MONO_ADC_L1_SFT 14 360 #define RT5670_M_MONO_ADC_L2 (0x1 << 13) 361 #define RT5670_M_MONO_ADC_L2_SFT 13 362 #define RT5670_MONO_ADC_L1_SRC_MASK (0x1 << 12) 363 #define RT5670_MONO_ADC_L1_SRC_SFT 12 364 #define RT5670_MONO_ADC_L1_SRC_DACMIXL (0x0 << 12) 365 #define RT5670_MONO_ADC_L1_SRC_ADCL (0x1 << 12) 366 #define RT5670_MONO_ADC_L2_SRC_MASK (0x1 << 11) 367 #define RT5670_MONO_ADC_L2_SRC_SFT 11 368 #define RT5670_MONO_ADC_L_SRC_MASK (0x1 << 10) 369 #define RT5670_MONO_ADC_L_SRC_SFT 10 370 #define RT5670_MONO_DMIC_L_SRC_MASK (0x3 << 8) 371 #define RT5670_MONO_DMIC_L_SRC_SFT 8 372 #define RT5670_M_MONO_ADC_R1 (0x1 << 6) 373 #define RT5670_M_MONO_ADC_R1_SFT 6 374 #define RT5670_M_MONO_ADC_R2 (0x1 << 5) 375 #define RT5670_M_MONO_ADC_R2_SFT 5 376 #define RT5670_MONO_ADC_R1_SRC_MASK (0x1 << 4) 377 #define RT5670_MONO_ADC_R1_SRC_SFT 4 378 #define RT5670_MONO_ADC_R1_SRC_ADCR (0x1 << 4) 379 #define RT5670_MONO_ADC_R1_SRC_DACMIXR (0x0 << 4) 380 #define RT5670_MONO_ADC_R2_SRC_MASK (0x1 << 3) 381 #define RT5670_MONO_ADC_R2_SRC_SFT 3 382 #define RT5670_MONO_DMIC_R_SRC_MASK (0x3) 383 #define RT5670_MONO_DMIC_R_SRC_SFT 0 384 385 /* ADC Mixer to DAC Mixer Control (0x29) */ 386 #define RT5670_M_ADCMIX_L (0x1 << 15) 387 #define RT5670_M_ADCMIX_L_SFT 15 388 #define RT5670_M_DAC1_L (0x1 << 14) 389 #define RT5670_M_DAC1_L_SFT 14 390 #define RT5670_DAC1_R_SEL_MASK (0x3 << 10) 391 #define RT5670_DAC1_R_SEL_SFT 10 392 #define RT5670_DAC1_R_SEL_IF1 (0x0 << 10) 393 #define RT5670_DAC1_R_SEL_IF2 (0x1 << 10) 394 #define RT5670_DAC1_R_SEL_IF3 (0x2 << 10) 395 #define RT5670_DAC1_R_SEL_IF4 (0x3 << 10) 396 #define RT5670_DAC1_L_SEL_MASK (0x3 << 8) 397 #define RT5670_DAC1_L_SEL_SFT 8 398 #define RT5670_DAC1_L_SEL_IF1 (0x0 << 8) 399 #define RT5670_DAC1_L_SEL_IF2 (0x1 << 8) 400 #define RT5670_DAC1_L_SEL_IF3 (0x2 << 8) 401 #define RT5670_DAC1_L_SEL_IF4 (0x3 << 8) 402 #define RT5670_M_ADCMIX_R (0x1 << 7) 403 #define RT5670_M_ADCMIX_R_SFT 7 404 #define RT5670_M_DAC1_R (0x1 << 6) 405 #define RT5670_M_DAC1_R_SFT 6 406 407 /* Stereo DAC Mixer Control (0x2a) */ 408 #define RT5670_M_DAC_L1 (0x1 << 14) 409 #define RT5670_M_DAC_L1_SFT 14 410 #define RT5670_DAC_L1_STO_L_VOL_MASK (0x1 << 13) 411 #define RT5670_DAC_L1_STO_L_VOL_SFT 13 412 #define RT5670_M_DAC_L2 (0x1 << 12) 413 #define RT5670_M_DAC_L2_SFT 12 414 #define RT5670_DAC_L2_STO_L_VOL_MASK (0x1 << 11) 415 #define RT5670_DAC_L2_STO_L_VOL_SFT 11 416 #define RT5670_M_DAC_R1_STO_L (0x1 << 9) 417 #define RT5670_M_DAC_R1_STO_L_SFT 9 418 #define RT5670_DAC_R1_STO_L_VOL_MASK (0x1 << 8) 419 #define RT5670_DAC_R1_STO_L_VOL_SFT 8 420 #define RT5670_M_DAC_R1 (0x1 << 6) 421 #define RT5670_M_DAC_R1_SFT 6 422 #define RT5670_DAC_R1_STO_R_VOL_MASK (0x1 << 5) 423 #define RT5670_DAC_R1_STO_R_VOL_SFT 5 424 #define RT5670_M_DAC_R2 (0x1 << 4) 425 #define RT5670_M_DAC_R2_SFT 4 426 #define RT5670_DAC_R2_STO_R_VOL_MASK (0x1 << 3) 427 #define RT5670_DAC_R2_STO_R_VOL_SFT 3 428 #define RT5670_M_DAC_L1_STO_R (0x1 << 1) 429 #define RT5670_M_DAC_L1_STO_R_SFT 1 430 #define RT5670_DAC_L1_STO_R_VOL_MASK (0x1) 431 #define RT5670_DAC_L1_STO_R_VOL_SFT 0 432 433 /* Mono DAC Mixer Control (0x2b) */ 434 #define RT5670_M_DAC_L1_MONO_L (0x1 << 14) 435 #define RT5670_M_DAC_L1_MONO_L_SFT 14 436 #define RT5670_DAC_L1_MONO_L_VOL_MASK (0x1 << 13) 437 #define RT5670_DAC_L1_MONO_L_VOL_SFT 13 438 #define RT5670_M_DAC_L2_MONO_L (0x1 << 12) 439 #define RT5670_M_DAC_L2_MONO_L_SFT 12 440 #define RT5670_DAC_L2_MONO_L_VOL_MASK (0x1 << 11) 441 #define RT5670_DAC_L2_MONO_L_VOL_SFT 11 442 #define RT5670_M_DAC_R2_MONO_L (0x1 << 10) 443 #define RT5670_M_DAC_R2_MONO_L_SFT 10 444 #define RT5670_DAC_R2_MONO_L_VOL_MASK (0x1 << 9) 445 #define RT5670_DAC_R2_MONO_L_VOL_SFT 9 446 #define RT5670_M_DAC_R1_MONO_R (0x1 << 6) 447 #define RT5670_M_DAC_R1_MONO_R_SFT 6 448 #define RT5670_DAC_R1_MONO_R_VOL_MASK (0x1 << 5) 449 #define RT5670_DAC_R1_MONO_R_VOL_SFT 5 450 #define RT5670_M_DAC_R2_MONO_R (0x1 << 4) 451 #define RT5670_M_DAC_R2_MONO_R_SFT 4 452 #define RT5670_DAC_R2_MONO_R_VOL_MASK (0x1 << 3) 453 #define RT5670_DAC_R2_MONO_R_VOL_SFT 3 454 #define RT5670_M_DAC_L2_MONO_R (0x1 << 2) 455 #define RT5670_M_DAC_L2_MONO_R_SFT 2 456 #define RT5670_DAC_L2_MONO_R_VOL_MASK (0x1 << 1) 457 #define RT5670_DAC_L2_MONO_R_VOL_SFT 1 458 459 /* Digital Mixer Control (0x2c) */ 460 #define RT5670_M_STO_L_DAC_L (0x1 << 15) 461 #define RT5670_M_STO_L_DAC_L_SFT 15 462 #define RT5670_STO_L_DAC_L_VOL_MASK (0x1 << 14) 463 #define RT5670_STO_L_DAC_L_VOL_SFT 14 464 #define RT5670_M_DAC_L2_DAC_L (0x1 << 13) 465 #define RT5670_M_DAC_L2_DAC_L_SFT 13 466 #define RT5670_DAC_L2_DAC_L_VOL_MASK (0x1 << 12) 467 #define RT5670_DAC_L2_DAC_L_VOL_SFT 12 468 #define RT5670_M_STO_R_DAC_R (0x1 << 11) 469 #define RT5670_M_STO_R_DAC_R_SFT 11 470 #define RT5670_STO_R_DAC_R_VOL_MASK (0x1 << 10) 471 #define RT5670_STO_R_DAC_R_VOL_SFT 10 472 #define RT5670_M_DAC_R2_DAC_R (0x1 << 9) 473 #define RT5670_M_DAC_R2_DAC_R_SFT 9 474 #define RT5670_DAC_R2_DAC_R_VOL_MASK (0x1 << 8) 475 #define RT5670_DAC_R2_DAC_R_VOL_SFT 8 476 #define RT5670_M_DAC_R2_DAC_L (0x1 << 7) 477 #define RT5670_M_DAC_R2_DAC_L_SFT 7 478 #define RT5670_DAC_R2_DAC_L_VOL_MASK (0x1 << 6) 479 #define RT5670_DAC_R2_DAC_L_VOL_SFT 6 480 #define RT5670_M_DAC_L2_DAC_R (0x1 << 5) 481 #define RT5670_M_DAC_L2_DAC_R_SFT 5 482 #define RT5670_DAC_L2_DAC_R_VOL_MASK (0x1 << 4) 483 #define RT5670_DAC_L2_DAC_R_VOL_SFT 4 484 485 /* DSP Path Control 1 (0x2d) */ 486 #define RT5670_RXDP_SEL_MASK (0x7 << 13) 487 #define RT5670_RXDP_SEL_SFT 13 488 #define RT5670_RXDP_SRC_MASK (0x3 << 11) 489 #define RT5670_RXDP_SRC_SFT 11 490 #define RT5670_RXDP_SRC_NOR (0x0 << 11) 491 #define RT5670_RXDP_SRC_DIV2 (0x1 << 11) 492 #define RT5670_RXDP_SRC_DIV3 (0x2 << 11) 493 #define RT5670_TXDP_SRC_MASK (0x3 << 4) 494 #define RT5670_TXDP_SRC_SFT 4 495 #define RT5670_TXDP_SRC_NOR (0x0 << 4) 496 #define RT5670_TXDP_SRC_DIV2 (0x1 << 4) 497 #define RT5670_TXDP_SRC_DIV3 (0x2 << 4) 498 #define RT5670_TXDP_SLOT_SEL_MASK (0x3 << 2) 499 #define RT5670_TXDP_SLOT_SEL_SFT 2 500 #define RT5670_DSP_UL_SEL (0x1 << 1) 501 #define RT5670_DSP_UL_SFT 1 502 #define RT5670_DSP_DL_SEL 0x1 503 #define RT5670_DSP_DL_SFT 0 504 505 /* DSP Path Control 2 (0x2e) */ 506 #define RT5670_TXDP_L_VOL_MASK (0x7f << 8) 507 #define RT5670_TXDP_L_VOL_SFT 8 508 #define RT5670_TXDP_R_VOL_MASK (0x7f) 509 #define RT5670_TXDP_R_VOL_SFT 0 510 511 /* Digital Interface Data Control (0x2f) */ 512 #define RT5670_IF1_ADC2_IN_SEL (0x1 << 15) 513 #define RT5670_IF1_ADC2_IN_SFT 15 514 #define RT5670_IF2_ADC_IN_MASK (0x7 << 12) 515 #define RT5670_IF2_ADC_IN_SFT 12 516 #define RT5670_IF2_DAC_SEL_MASK (0x3 << 10) 517 #define RT5670_IF2_DAC_SEL_SFT 10 518 #define RT5670_IF2_ADC_SEL_MASK (0x3 << 8) 519 #define RT5670_IF2_ADC_SEL_SFT 8 520 521 /* Digital Interface Data Control (0x30) */ 522 #define RT5670_IF4_ADC_IN_MASK (0x3 << 4) 523 #define RT5670_IF4_ADC_IN_SFT 4 524 525 /* PDM Output Control (0x31) */ 526 #define RT5670_PDM1_L_MASK (0x1 << 15) 527 #define RT5670_PDM1_L_SFT 15 528 #define RT5670_M_PDM1_L (0x1 << 14) 529 #define RT5670_M_PDM1_L_SFT 14 530 #define RT5670_PDM1_R_MASK (0x1 << 13) 531 #define RT5670_PDM1_R_SFT 13 532 #define RT5670_M_PDM1_R (0x1 << 12) 533 #define RT5670_M_PDM1_R_SFT 12 534 #define RT5670_PDM2_L_MASK (0x1 << 11) 535 #define RT5670_PDM2_L_SFT 11 536 #define RT5670_M_PDM2_L (0x1 << 10) 537 #define RT5670_M_PDM2_L_SFT 10 538 #define RT5670_PDM2_R_MASK (0x1 << 9) 539 #define RT5670_PDM2_R_SFT 9 540 #define RT5670_M_PDM2_R (0x1 << 8) 541 #define RT5670_M_PDM2_R_SFT 8 542 #define RT5670_PDM2_BUSY (0x1 << 7) 543 #define RT5670_PDM1_BUSY (0x1 << 6) 544 #define RT5670_PDM_PATTERN (0x1 << 5) 545 #define RT5670_PDM_GAIN (0x1 << 4) 546 #define RT5670_PDM_DIV_MASK (0x3) 547 548 /* REC Left Mixer Control 1 (0x3b) */ 549 #define RT5670_G_HP_L_RM_L_MASK (0x7 << 13) 550 #define RT5670_G_HP_L_RM_L_SFT 13 551 #define RT5670_G_IN_L_RM_L_MASK (0x7 << 10) 552 #define RT5670_G_IN_L_RM_L_SFT 10 553 #define RT5670_G_BST4_RM_L_MASK (0x7 << 7) 554 #define RT5670_G_BST4_RM_L_SFT 7 555 #define RT5670_G_BST3_RM_L_MASK (0x7 << 4) 556 #define RT5670_G_BST3_RM_L_SFT 4 557 #define RT5670_G_BST2_RM_L_MASK (0x7 << 1) 558 #define RT5670_G_BST2_RM_L_SFT 1 559 560 /* REC Left Mixer Control 2 (0x3c) */ 561 #define RT5670_G_BST1_RM_L_MASK (0x7 << 13) 562 #define RT5670_G_BST1_RM_L_SFT 13 563 #define RT5670_M_IN_L_RM_L (0x1 << 5) 564 #define RT5670_M_IN_L_RM_L_SFT 5 565 #define RT5670_M_BST2_RM_L (0x1 << 3) 566 #define RT5670_M_BST2_RM_L_SFT 3 567 #define RT5670_M_BST1_RM_L (0x1 << 1) 568 #define RT5670_M_BST1_RM_L_SFT 1 569 570 /* REC Right Mixer Control 1 (0x3d) */ 571 #define RT5670_G_HP_R_RM_R_MASK (0x7 << 13) 572 #define RT5670_G_HP_R_RM_R_SFT 13 573 #define RT5670_G_IN_R_RM_R_MASK (0x7 << 10) 574 #define RT5670_G_IN_R_RM_R_SFT 10 575 #define RT5670_G_BST4_RM_R_MASK (0x7 << 7) 576 #define RT5670_G_BST4_RM_R_SFT 7 577 #define RT5670_G_BST3_RM_R_MASK (0x7 << 4) 578 #define RT5670_G_BST3_RM_R_SFT 4 579 #define RT5670_G_BST2_RM_R_MASK (0x7 << 1) 580 #define RT5670_G_BST2_RM_R_SFT 1 581 582 /* REC Right Mixer Control 2 (0x3e) */ 583 #define RT5670_G_BST1_RM_R_MASK (0x7 << 13) 584 #define RT5670_G_BST1_RM_R_SFT 13 585 #define RT5670_M_IN_R_RM_R (0x1 << 5) 586 #define RT5670_M_IN_R_RM_R_SFT 5 587 #define RT5670_M_BST2_RM_R (0x1 << 3) 588 #define RT5670_M_BST2_RM_R_SFT 3 589 #define RT5670_M_BST1_RM_R (0x1 << 1) 590 #define RT5670_M_BST1_RM_R_SFT 1 591 592 /* HPMIX Control (0x45) */ 593 #define RT5670_M_DAC2_HM (0x1 << 15) 594 #define RT5670_M_DAC2_HM_SFT 15 595 #define RT5670_M_HPVOL_HM (0x1 << 14) 596 #define RT5670_M_HPVOL_HM_SFT 14 597 #define RT5670_M_DAC1_HM (0x1 << 13) 598 #define RT5670_M_DAC1_HM_SFT 13 599 #define RT5670_G_HPOMIX_MASK (0x1 << 12) 600 #define RT5670_G_HPOMIX_SFT 12 601 #define RT5670_M_INR1_HMR (0x1 << 3) 602 #define RT5670_M_INR1_HMR_SFT 3 603 #define RT5670_M_DACR1_HMR (0x1 << 2) 604 #define RT5670_M_DACR1_HMR_SFT 2 605 #define RT5670_M_INL1_HML (0x1 << 1) 606 #define RT5670_M_INL1_HML_SFT 1 607 #define RT5670_M_DACL1_HML (0x1) 608 #define RT5670_M_DACL1_HML_SFT 0 609 610 /* Mono Output Mixer Control (0x4c) */ 611 #define RT5670_M_DAC_R2_MA (0x1 << 15) 612 #define RT5670_M_DAC_R2_MA_SFT 15 613 #define RT5670_M_DAC_L2_MA (0x1 << 14) 614 #define RT5670_M_DAC_L2_MA_SFT 14 615 #define RT5670_M_OV_R_MM (0x1 << 13) 616 #define RT5670_M_OV_R_MM_SFT 13 617 #define RT5670_M_OV_L_MM (0x1 << 12) 618 #define RT5670_M_OV_L_MM_SFT 12 619 #define RT5670_G_MONOMIX_MASK (0x1 << 10) 620 #define RT5670_G_MONOMIX_SFT 10 621 #define RT5670_M_DAC_R2_MM (0x1 << 9) 622 #define RT5670_M_DAC_R2_MM_SFT 9 623 #define RT5670_M_DAC_L2_MM (0x1 << 8) 624 #define RT5670_M_DAC_L2_MM_SFT 8 625 #define RT5670_M_BST4_MM (0x1 << 7) 626 #define RT5670_M_BST4_MM_SFT 7 627 628 /* Output Left Mixer Control 1 (0x4d) */ 629 #define RT5670_G_BST3_OM_L_MASK (0x7 << 13) 630 #define RT5670_G_BST3_OM_L_SFT 13 631 #define RT5670_G_BST2_OM_L_MASK (0x7 << 10) 632 #define RT5670_G_BST2_OM_L_SFT 10 633 #define RT5670_G_BST1_OM_L_MASK (0x7 << 7) 634 #define RT5670_G_BST1_OM_L_SFT 7 635 #define RT5670_G_IN_L_OM_L_MASK (0x7 << 4) 636 #define RT5670_G_IN_L_OM_L_SFT 4 637 #define RT5670_G_RM_L_OM_L_MASK (0x7 << 1) 638 #define RT5670_G_RM_L_OM_L_SFT 1 639 640 /* Output Left Mixer Control 2 (0x4e) */ 641 #define RT5670_G_DAC_R2_OM_L_MASK (0x7 << 13) 642 #define RT5670_G_DAC_R2_OM_L_SFT 13 643 #define RT5670_G_DAC_L2_OM_L_MASK (0x7 << 10) 644 #define RT5670_G_DAC_L2_OM_L_SFT 10 645 #define RT5670_G_DAC_L1_OM_L_MASK (0x7 << 7) 646 #define RT5670_G_DAC_L1_OM_L_SFT 7 647 648 /* Output Left Mixer Control 3 (0x4f) */ 649 #define RT5670_M_BST1_OM_L (0x1 << 5) 650 #define RT5670_M_BST1_OM_L_SFT 5 651 #define RT5670_M_IN_L_OM_L (0x1 << 4) 652 #define RT5670_M_IN_L_OM_L_SFT 4 653 #define RT5670_M_DAC_L2_OM_L (0x1 << 1) 654 #define RT5670_M_DAC_L2_OM_L_SFT 1 655 #define RT5670_M_DAC_L1_OM_L (0x1) 656 #define RT5670_M_DAC_L1_OM_L_SFT 0 657 658 /* Output Right Mixer Control 1 (0x50) */ 659 #define RT5670_G_BST4_OM_R_MASK (0x7 << 13) 660 #define RT5670_G_BST4_OM_R_SFT 13 661 #define RT5670_G_BST2_OM_R_MASK (0x7 << 10) 662 #define RT5670_G_BST2_OM_R_SFT 10 663 #define RT5670_G_BST1_OM_R_MASK (0x7 << 7) 664 #define RT5670_G_BST1_OM_R_SFT 7 665 #define RT5670_G_IN_R_OM_R_MASK (0x7 << 4) 666 #define RT5670_G_IN_R_OM_R_SFT 4 667 #define RT5670_G_RM_R_OM_R_MASK (0x7 << 1) 668 #define RT5670_G_RM_R_OM_R_SFT 1 669 670 /* Output Right Mixer Control 2 (0x51) */ 671 #define RT5670_G_DAC_L2_OM_R_MASK (0x7 << 13) 672 #define RT5670_G_DAC_L2_OM_R_SFT 13 673 #define RT5670_G_DAC_R2_OM_R_MASK (0x7 << 10) 674 #define RT5670_G_DAC_R2_OM_R_SFT 10 675 #define RT5670_G_DAC_R1_OM_R_MASK (0x7 << 7) 676 #define RT5670_G_DAC_R1_OM_R_SFT 7 677 678 /* Output Right Mixer Control 3 (0x52) */ 679 #define RT5670_M_BST2_OM_R (0x1 << 6) 680 #define RT5670_M_BST2_OM_R_SFT 6 681 #define RT5670_M_IN_R_OM_R (0x1 << 4) 682 #define RT5670_M_IN_R_OM_R_SFT 4 683 #define RT5670_M_DAC_R2_OM_R (0x1 << 1) 684 #define RT5670_M_DAC_R2_OM_R_SFT 1 685 #define RT5670_M_DAC_R1_OM_R (0x1) 686 #define RT5670_M_DAC_R1_OM_R_SFT 0 687 688 /* LOUT Mixer Control (0x53) */ 689 #define RT5670_M_DAC_L1_LM (0x1 << 15) 690 #define RT5670_M_DAC_L1_LM_SFT 15 691 #define RT5670_M_DAC_R1_LM (0x1 << 14) 692 #define RT5670_M_DAC_R1_LM_SFT 14 693 #define RT5670_M_OV_L_LM (0x1 << 13) 694 #define RT5670_M_OV_L_LM_SFT 13 695 #define RT5670_M_OV_R_LM (0x1 << 12) 696 #define RT5670_M_OV_R_LM_SFT 12 697 #define RT5670_G_LOUTMIX_MASK (0x1 << 11) 698 #define RT5670_G_LOUTMIX_SFT 11 699 700 /* Power Management for Digital 1 (0x61) */ 701 #define RT5670_PWR_I2S1 (0x1 << 15) 702 #define RT5670_PWR_I2S1_BIT 15 703 #define RT5670_PWR_I2S2 (0x1 << 14) 704 #define RT5670_PWR_I2S2_BIT 14 705 #define RT5670_PWR_DAC_L1 (0x1 << 12) 706 #define RT5670_PWR_DAC_L1_BIT 12 707 #define RT5670_PWR_DAC_R1 (0x1 << 11) 708 #define RT5670_PWR_DAC_R1_BIT 11 709 #define RT5670_PWR_DAC_L2 (0x1 << 7) 710 #define RT5670_PWR_DAC_L2_BIT 7 711 #define RT5670_PWR_DAC_R2 (0x1 << 6) 712 #define RT5670_PWR_DAC_R2_BIT 6 713 #define RT5670_PWR_ADC_L (0x1 << 2) 714 #define RT5670_PWR_ADC_L_BIT 2 715 #define RT5670_PWR_ADC_R (0x1 << 1) 716 #define RT5670_PWR_ADC_R_BIT 1 717 #define RT5670_PWR_CLS_D (0x1) 718 #define RT5670_PWR_CLS_D_BIT 0 719 720 /* Power Management for Digital 2 (0x62) */ 721 #define RT5670_PWR_ADC_S1F (0x1 << 15) 722 #define RT5670_PWR_ADC_S1F_BIT 15 723 #define RT5670_PWR_ADC_MF_L (0x1 << 14) 724 #define RT5670_PWR_ADC_MF_L_BIT 14 725 #define RT5670_PWR_ADC_MF_R (0x1 << 13) 726 #define RT5670_PWR_ADC_MF_R_BIT 13 727 #define RT5670_PWR_I2S_DSP (0x1 << 12) 728 #define RT5670_PWR_I2S_DSP_BIT 12 729 #define RT5670_PWR_DAC_S1F (0x1 << 11) 730 #define RT5670_PWR_DAC_S1F_BIT 11 731 #define RT5670_PWR_DAC_MF_L (0x1 << 10) 732 #define RT5670_PWR_DAC_MF_L_BIT 10 733 #define RT5670_PWR_DAC_MF_R (0x1 << 9) 734 #define RT5670_PWR_DAC_MF_R_BIT 9 735 #define RT5670_PWR_ADC_S2F (0x1 << 8) 736 #define RT5670_PWR_ADC_S2F_BIT 8 737 #define RT5670_PWR_PDM1 (0x1 << 7) 738 #define RT5670_PWR_PDM1_BIT 7 739 #define RT5670_PWR_PDM2 (0x1 << 6) 740 #define RT5670_PWR_PDM2_BIT 6 741 742 /* Power Management for Analog 1 (0x63) */ 743 #define RT5670_PWR_VREF1 (0x1 << 15) 744 #define RT5670_PWR_VREF1_BIT 15 745 #define RT5670_PWR_FV1 (0x1 << 14) 746 #define RT5670_PWR_FV1_BIT 14 747 #define RT5670_PWR_MB (0x1 << 13) 748 #define RT5670_PWR_MB_BIT 13 749 #define RT5670_PWR_LM (0x1 << 12) 750 #define RT5670_PWR_LM_BIT 12 751 #define RT5670_PWR_BG (0x1 << 11) 752 #define RT5670_PWR_BG_BIT 11 753 #define RT5670_PWR_HP_L (0x1 << 7) 754 #define RT5670_PWR_HP_L_BIT 7 755 #define RT5670_PWR_HP_R (0x1 << 6) 756 #define RT5670_PWR_HP_R_BIT 6 757 #define RT5670_PWR_HA (0x1 << 5) 758 #define RT5670_PWR_HA_BIT 5 759 #define RT5670_PWR_VREF2 (0x1 << 4) 760 #define RT5670_PWR_VREF2_BIT 4 761 #define RT5670_PWR_FV2 (0x1 << 3) 762 #define RT5670_PWR_FV2_BIT 3 763 #define RT5670_LDO_SEL_MASK (0x3) 764 #define RT5670_LDO_SEL_SFT 0 765 766 /* Power Management for Analog 2 (0x64) */ 767 #define RT5670_PWR_BST1 (0x1 << 15) 768 #define RT5670_PWR_BST1_BIT 15 769 #define RT5670_PWR_BST2 (0x1 << 13) 770 #define RT5670_PWR_BST2_BIT 13 771 #define RT5670_PWR_MB1 (0x1 << 11) 772 #define RT5670_PWR_MB1_BIT 11 773 #define RT5670_PWR_MB2 (0x1 << 10) 774 #define RT5670_PWR_MB2_BIT 10 775 #define RT5670_PWR_PLL (0x1 << 9) 776 #define RT5670_PWR_PLL_BIT 9 777 #define RT5670_PWR_BST1_P (0x1 << 6) 778 #define RT5670_PWR_BST1_P_BIT 6 779 #define RT5670_PWR_BST2_P (0x1 << 4) 780 #define RT5670_PWR_BST2_P_BIT 4 781 #define RT5670_PWR_JD1 (0x1 << 2) 782 #define RT5670_PWR_JD1_BIT 2 783 #define RT5670_PWR_JD (0x1 << 1) 784 #define RT5670_PWR_JD_BIT 1 785 786 /* Power Management for Mixer (0x65) */ 787 #define RT5670_PWR_OM_L (0x1 << 15) 788 #define RT5670_PWR_OM_L_BIT 15 789 #define RT5670_PWR_OM_R (0x1 << 14) 790 #define RT5670_PWR_OM_R_BIT 14 791 #define RT5670_PWR_RM_L (0x1 << 11) 792 #define RT5670_PWR_RM_L_BIT 11 793 #define RT5670_PWR_RM_R (0x1 << 10) 794 #define RT5670_PWR_RM_R_BIT 10 795 796 /* Power Management for Volume (0x66) */ 797 #define RT5670_PWR_HV_L (0x1 << 11) 798 #define RT5670_PWR_HV_L_BIT 11 799 #define RT5670_PWR_HV_R (0x1 << 10) 800 #define RT5670_PWR_HV_R_BIT 10 801 #define RT5670_PWR_IN_L (0x1 << 9) 802 #define RT5670_PWR_IN_L_BIT 9 803 #define RT5670_PWR_IN_R (0x1 << 8) 804 #define RT5670_PWR_IN_R_BIT 8 805 #define RT5670_PWR_MIC_DET (0x1 << 5) 806 #define RT5670_PWR_MIC_DET_BIT 5 807 808 /* I2S1/2/3 Audio Serial Data Port Control (0x70 0x71 0x72) */ 809 #define RT5670_I2S_MS_MASK (0x1 << 15) 810 #define RT5670_I2S_MS_SFT 15 811 #define RT5670_I2S_MS_M (0x0 << 15) 812 #define RT5670_I2S_MS_S (0x1 << 15) 813 #define RT5670_I2S_IF_MASK (0x7 << 12) 814 #define RT5670_I2S_IF_SFT 12 815 #define RT5670_I2S_O_CP_MASK (0x3 << 10) 816 #define RT5670_I2S_O_CP_SFT 10 817 #define RT5670_I2S_O_CP_OFF (0x0 << 10) 818 #define RT5670_I2S_O_CP_U_LAW (0x1 << 10) 819 #define RT5670_I2S_O_CP_A_LAW (0x2 << 10) 820 #define RT5670_I2S_I_CP_MASK (0x3 << 8) 821 #define RT5670_I2S_I_CP_SFT 8 822 #define RT5670_I2S_I_CP_OFF (0x0 << 8) 823 #define RT5670_I2S_I_CP_U_LAW (0x1 << 8) 824 #define RT5670_I2S_I_CP_A_LAW (0x2 << 8) 825 #define RT5670_I2S_BP_MASK (0x1 << 7) 826 #define RT5670_I2S_BP_SFT 7 827 #define RT5670_I2S_BP_NOR (0x0 << 7) 828 #define RT5670_I2S_BP_INV (0x1 << 7) 829 #define RT5670_I2S_DL_MASK (0x3 << 2) 830 #define RT5670_I2S_DL_SFT 2 831 #define RT5670_I2S_DL_16 (0x0 << 2) 832 #define RT5670_I2S_DL_20 (0x1 << 2) 833 #define RT5670_I2S_DL_24 (0x2 << 2) 834 #define RT5670_I2S_DL_8 (0x3 << 2) 835 #define RT5670_I2S_DF_MASK (0x3) 836 #define RT5670_I2S_DF_SFT 0 837 #define RT5670_I2S_DF_I2S (0x0) 838 #define RT5670_I2S_DF_LEFT (0x1) 839 #define RT5670_I2S_DF_PCM_A (0x2) 840 #define RT5670_I2S_DF_PCM_B (0x3) 841 842 /* I2S2 Audio Serial Data Port Control (0x71) */ 843 #define RT5670_I2S2_SDI_MASK (0x1 << 6) 844 #define RT5670_I2S2_SDI_SFT 6 845 #define RT5670_I2S2_SDI_I2S1 (0x0 << 6) 846 #define RT5670_I2S2_SDI_I2S2 (0x1 << 6) 847 848 /* ADC/DAC Clock Control 1 (0x73) */ 849 #define RT5670_I2S_BCLK_MS1_MASK (0x1 << 15) 850 #define RT5670_I2S_BCLK_MS1_SFT 15 851 #define RT5670_I2S_BCLK_MS1_32 (0x0 << 15) 852 #define RT5670_I2S_BCLK_MS1_64 (0x1 << 15) 853 #define RT5670_I2S_PD1_MASK (0x7 << 12) 854 #define RT5670_I2S_PD1_SFT 12 855 #define RT5670_I2S_PD1_1 (0x0 << 12) 856 #define RT5670_I2S_PD1_2 (0x1 << 12) 857 #define RT5670_I2S_PD1_3 (0x2 << 12) 858 #define RT5670_I2S_PD1_4 (0x3 << 12) 859 #define RT5670_I2S_PD1_6 (0x4 << 12) 860 #define RT5670_I2S_PD1_8 (0x5 << 12) 861 #define RT5670_I2S_PD1_12 (0x6 << 12) 862 #define RT5670_I2S_PD1_16 (0x7 << 12) 863 #define RT5670_I2S_BCLK_MS2_MASK (0x1 << 11) 864 #define RT5670_I2S_BCLK_MS2_SFT 11 865 #define RT5670_I2S_BCLK_MS2_32 (0x0 << 11) 866 #define RT5670_I2S_BCLK_MS2_64 (0x1 << 11) 867 #define RT5670_I2S_PD2_MASK (0x7 << 8) 868 #define RT5670_I2S_PD2_SFT 8 869 #define RT5670_I2S_PD2_1 (0x0 << 8) 870 #define RT5670_I2S_PD2_2 (0x1 << 8) 871 #define RT5670_I2S_PD2_3 (0x2 << 8) 872 #define RT5670_I2S_PD2_4 (0x3 << 8) 873 #define RT5670_I2S_PD2_6 (0x4 << 8) 874 #define RT5670_I2S_PD2_8 (0x5 << 8) 875 #define RT5670_I2S_PD2_12 (0x6 << 8) 876 #define RT5670_I2S_PD2_16 (0x7 << 8) 877 #define RT5670_I2S_BCLK_MS3_MASK (0x1 << 7) 878 #define RT5670_I2S_BCLK_MS3_SFT 7 879 #define RT5670_I2S_BCLK_MS3_32 (0x0 << 7) 880 #define RT5670_I2S_BCLK_MS3_64 (0x1 << 7) 881 #define RT5670_I2S_PD3_MASK (0x7 << 4) 882 #define RT5670_I2S_PD3_SFT 4 883 #define RT5670_I2S_PD3_1 (0x0 << 4) 884 #define RT5670_I2S_PD3_2 (0x1 << 4) 885 #define RT5670_I2S_PD3_3 (0x2 << 4) 886 #define RT5670_I2S_PD3_4 (0x3 << 4) 887 #define RT5670_I2S_PD3_6 (0x4 << 4) 888 #define RT5670_I2S_PD3_8 (0x5 << 4) 889 #define RT5670_I2S_PD3_12 (0x6 << 4) 890 #define RT5670_I2S_PD3_16 (0x7 << 4) 891 #define RT5670_DAC_OSR_MASK (0x3 << 2) 892 #define RT5670_DAC_OSR_SFT 2 893 #define RT5670_DAC_OSR_128 (0x0 << 2) 894 #define RT5670_DAC_OSR_64 (0x1 << 2) 895 #define RT5670_DAC_OSR_32 (0x2 << 2) 896 #define RT5670_DAC_OSR_16 (0x3 << 2) 897 #define RT5670_ADC_OSR_MASK (0x3) 898 #define RT5670_ADC_OSR_SFT 0 899 #define RT5670_ADC_OSR_128 (0x0) 900 #define RT5670_ADC_OSR_64 (0x1) 901 #define RT5670_ADC_OSR_32 (0x2) 902 #define RT5670_ADC_OSR_16 (0x3) 903 904 /* ADC/DAC Clock Control 2 (0x74) */ 905 #define RT5670_DAC_L_OSR_MASK (0x3 << 14) 906 #define RT5670_DAC_L_OSR_SFT 14 907 #define RT5670_DAC_L_OSR_128 (0x0 << 14) 908 #define RT5670_DAC_L_OSR_64 (0x1 << 14) 909 #define RT5670_DAC_L_OSR_32 (0x2 << 14) 910 #define RT5670_DAC_L_OSR_16 (0x3 << 14) 911 #define RT5670_ADC_R_OSR_MASK (0x3 << 12) 912 #define RT5670_ADC_R_OSR_SFT 12 913 #define RT5670_ADC_R_OSR_128 (0x0 << 12) 914 #define RT5670_ADC_R_OSR_64 (0x1 << 12) 915 #define RT5670_ADC_R_OSR_32 (0x2 << 12) 916 #define RT5670_ADC_R_OSR_16 (0x3 << 12) 917 #define RT5670_DAHPF_EN (0x1 << 11) 918 #define RT5670_DAHPF_EN_SFT 11 919 #define RT5670_ADHPF_EN (0x1 << 10) 920 #define RT5670_ADHPF_EN_SFT 10 921 922 /* Digital Microphone Control (0x75) */ 923 #define RT5670_DMIC_1_EN_MASK (0x1 << 15) 924 #define RT5670_DMIC_1_EN_SFT 15 925 #define RT5670_DMIC_1_DIS (0x0 << 15) 926 #define RT5670_DMIC_1_EN (0x1 << 15) 927 #define RT5670_DMIC_2_EN_MASK (0x1 << 14) 928 #define RT5670_DMIC_2_EN_SFT 14 929 #define RT5670_DMIC_2_DIS (0x0 << 14) 930 #define RT5670_DMIC_2_EN (0x1 << 14) 931 #define RT5670_DMIC_1L_LH_MASK (0x1 << 13) 932 #define RT5670_DMIC_1L_LH_SFT 13 933 #define RT5670_DMIC_1L_LH_FALLING (0x0 << 13) 934 #define RT5670_DMIC_1L_LH_RISING (0x1 << 13) 935 #define RT5670_DMIC_1R_LH_MASK (0x1 << 12) 936 #define RT5670_DMIC_1R_LH_SFT 12 937 #define RT5670_DMIC_1R_LH_FALLING (0x0 << 12) 938 #define RT5670_DMIC_1R_LH_RISING (0x1 << 12) 939 #define RT5670_DMIC_2_DP_MASK (0x1 << 10) 940 #define RT5670_DMIC_2_DP_SFT 10 941 #define RT5670_DMIC_2_DP_GPIO8 (0x0 << 10) 942 #define RT5670_DMIC_2_DP_IN3N (0x1 << 10) 943 #define RT5670_DMIC_2L_LH_MASK (0x1 << 9) 944 #define RT5670_DMIC_2L_LH_SFT 9 945 #define RT5670_DMIC_2L_LH_FALLING (0x0 << 9) 946 #define RT5670_DMIC_2L_LH_RISING (0x1 << 9) 947 #define RT5670_DMIC_2R_LH_MASK (0x1 << 8) 948 #define RT5670_DMIC_2R_LH_SFT 8 949 #define RT5670_DMIC_2R_LH_FALLING (0x0 << 8) 950 #define RT5670_DMIC_2R_LH_RISING (0x1 << 8) 951 #define RT5670_DMIC_CLK_MASK (0x7 << 5) 952 #define RT5670_DMIC_CLK_SFT 5 953 #define RT5670_DMIC_3_EN_MASK (0x1 << 4) 954 #define RT5670_DMIC_3_EN_SFT 4 955 #define RT5670_DMIC_3_DIS (0x0 << 4) 956 #define RT5670_DMIC_3_EN (0x1 << 4) 957 #define RT5670_DMIC_1_DP_MASK (0x3 << 0) 958 #define RT5670_DMIC_1_DP_SFT 0 959 #define RT5670_DMIC_1_DP_GPIO6 (0x0 << 0) 960 #define RT5670_DMIC_1_DP_IN2P (0x1 << 0) 961 #define RT5670_DMIC_1_DP_GPIO7 (0x2 << 0) 962 963 /* Digital Microphone Control2 (0x76) */ 964 #define RT5670_DMIC_3_DP_MASK (0x3 << 6) 965 #define RT5670_DMIC_3_DP_SFT 6 966 #define RT5670_DMIC_3_DP_GPIO9 (0x0 << 6) 967 #define RT5670_DMIC_3_DP_GPIO10 (0x1 << 6) 968 #define RT5670_DMIC_3_DP_GPIO5 (0x2 << 6) 969 970 /* Global Clock Control (0x80) */ 971 #define RT5670_SCLK_SRC_MASK (0x3 << 14) 972 #define RT5670_SCLK_SRC_SFT 14 973 #define RT5670_SCLK_SRC_MCLK (0x0 << 14) 974 #define RT5670_SCLK_SRC_PLL1 (0x1 << 14) 975 #define RT5670_SCLK_SRC_RCCLK (0x2 << 14) /* 15MHz */ 976 #define RT5670_PLL1_SRC_MASK (0x3 << 12) 977 #define RT5670_PLL1_SRC_SFT 12 978 #define RT5670_PLL1_SRC_MCLK (0x0 << 12) 979 #define RT5670_PLL1_SRC_BCLK1 (0x1 << 12) 980 #define RT5670_PLL1_SRC_BCLK2 (0x2 << 12) 981 #define RT5670_PLL1_SRC_BCLK3 (0x3 << 12) 982 #define RT5670_PLL1_PD_MASK (0x1 << 3) 983 #define RT5670_PLL1_PD_SFT 3 984 #define RT5670_PLL1_PD_1 (0x0 << 3) 985 #define RT5670_PLL1_PD_2 (0x1 << 3) 986 987 #define RT5670_PLL_INP_MAX 40000000 988 #define RT5670_PLL_INP_MIN 256000 989 /* PLL M/N/K Code Control 1 (0x81) */ 990 #define RT5670_PLL_N_MAX 0x1ff 991 #define RT5670_PLL_N_MASK (RT5670_PLL_N_MAX << 7) 992 #define RT5670_PLL_N_SFT 7 993 #define RT5670_PLL_K_MAX 0x1f 994 #define RT5670_PLL_K_MASK (RT5670_PLL_K_MAX) 995 #define RT5670_PLL_K_SFT 0 996 997 /* PLL M/N/K Code Control 2 (0x82) */ 998 #define RT5670_PLL_M_MAX 0xf 999 #define RT5670_PLL_M_MASK (RT5670_PLL_M_MAX << 12) 1000 #define RT5670_PLL_M_SFT 12 1001 #define RT5670_PLL_M_BP (0x1 << 11) 1002 #define RT5670_PLL_M_BP_SFT 11 1003 1004 /* ASRC Control 1 (0x83) */ 1005 #define RT5670_STO_T_MASK (0x1 << 15) 1006 #define RT5670_STO_T_SFT 15 1007 #define RT5670_STO_T_SCLK (0x0 << 15) 1008 #define RT5670_STO_T_LRCK1 (0x1 << 15) 1009 #define RT5670_M1_T_MASK (0x1 << 14) 1010 #define RT5670_M1_T_SFT 14 1011 #define RT5670_M1_T_I2S2 (0x0 << 14) 1012 #define RT5670_M1_T_I2S2_D3 (0x1 << 14) 1013 #define RT5670_I2S2_F_MASK (0x1 << 12) 1014 #define RT5670_I2S2_F_SFT 12 1015 #define RT5670_I2S2_F_I2S2_D2 (0x0 << 12) 1016 #define RT5670_I2S2_F_I2S1_TCLK (0x1 << 12) 1017 #define RT5670_DMIC_1_M_MASK (0x1 << 9) 1018 #define RT5670_DMIC_1_M_SFT 9 1019 #define RT5670_DMIC_1_M_NOR (0x0 << 9) 1020 #define RT5670_DMIC_1_M_ASYN (0x1 << 9) 1021 #define RT5670_DMIC_2_M_MASK (0x1 << 8) 1022 #define RT5670_DMIC_2_M_SFT 8 1023 #define RT5670_DMIC_2_M_NOR (0x0 << 8) 1024 #define RT5670_DMIC_2_M_ASYN (0x1 << 8) 1025 1026 /* ASRC Control 2 (0x84) */ 1027 #define RT5670_MDA_L_M_MASK (0x1 << 15) 1028 #define RT5670_MDA_L_M_SFT 15 1029 #define RT5670_MDA_L_M_NOR (0x0 << 15) 1030 #define RT5670_MDA_L_M_ASYN (0x1 << 15) 1031 #define RT5670_MDA_R_M_MASK (0x1 << 14) 1032 #define RT5670_MDA_R_M_SFT 14 1033 #define RT5670_MDA_R_M_NOR (0x0 << 14) 1034 #define RT5670_MDA_R_M_ASYN (0x1 << 14) 1035 #define RT5670_MAD_L_M_MASK (0x1 << 13) 1036 #define RT5670_MAD_L_M_SFT 13 1037 #define RT5670_MAD_L_M_NOR (0x0 << 13) 1038 #define RT5670_MAD_L_M_ASYN (0x1 << 13) 1039 #define RT5670_MAD_R_M_MASK (0x1 << 12) 1040 #define RT5670_MAD_R_M_SFT 12 1041 #define RT5670_MAD_R_M_NOR (0x0 << 12) 1042 #define RT5670_MAD_R_M_ASYN (0x1 << 12) 1043 #define RT5670_ADC_M_MASK (0x1 << 11) 1044 #define RT5670_ADC_M_SFT 11 1045 #define RT5670_ADC_M_NOR (0x0 << 11) 1046 #define RT5670_ADC_M_ASYN (0x1 << 11) 1047 #define RT5670_STO_DAC_M_MASK (0x1 << 5) 1048 #define RT5670_STO_DAC_M_SFT 5 1049 #define RT5670_STO_DAC_M_NOR (0x0 << 5) 1050 #define RT5670_STO_DAC_M_ASYN (0x1 << 5) 1051 #define RT5670_I2S1_R_D_MASK (0x1 << 4) 1052 #define RT5670_I2S1_R_D_SFT 4 1053 #define RT5670_I2S1_R_D_DIS (0x0 << 4) 1054 #define RT5670_I2S1_R_D_EN (0x1 << 4) 1055 #define RT5670_I2S2_R_D_MASK (0x1 << 3) 1056 #define RT5670_I2S2_R_D_SFT 3 1057 #define RT5670_I2S2_R_D_DIS (0x0 << 3) 1058 #define RT5670_I2S2_R_D_EN (0x1 << 3) 1059 #define RT5670_PRE_SCLK_MASK (0x3) 1060 #define RT5670_PRE_SCLK_SFT 0 1061 #define RT5670_PRE_SCLK_512 (0x0) 1062 #define RT5670_PRE_SCLK_1024 (0x1) 1063 #define RT5670_PRE_SCLK_2048 (0x2) 1064 1065 /* ASRC Control 3 (0x85) */ 1066 #define RT5670_I2S1_RATE_MASK (0xf << 12) 1067 #define RT5670_I2S1_RATE_SFT 12 1068 #define RT5670_I2S2_RATE_MASK (0xf << 8) 1069 #define RT5670_I2S2_RATE_SFT 8 1070 1071 /* ASRC Control 4 (0x89) */ 1072 #define RT5670_I2S1_PD_MASK (0x7 << 12) 1073 #define RT5670_I2S1_PD_SFT 12 1074 #define RT5670_I2S2_PD_MASK (0x7 << 8) 1075 #define RT5670_I2S2_PD_SFT 8 1076 1077 /* HPOUT Over Current Detection (0x8b) */ 1078 #define RT5670_HP_OVCD_MASK (0x1 << 10) 1079 #define RT5670_HP_OVCD_SFT 10 1080 #define RT5670_HP_OVCD_DIS (0x0 << 10) 1081 #define RT5670_HP_OVCD_EN (0x1 << 10) 1082 #define RT5670_HP_OC_TH_MASK (0x3 << 8) 1083 #define RT5670_HP_OC_TH_SFT 8 1084 #define RT5670_HP_OC_TH_90 (0x0 << 8) 1085 #define RT5670_HP_OC_TH_105 (0x1 << 8) 1086 #define RT5670_HP_OC_TH_120 (0x2 << 8) 1087 #define RT5670_HP_OC_TH_135 (0x3 << 8) 1088 1089 /* Class D Over Current Control (0x8c) */ 1090 #define RT5670_CLSD_OC_MASK (0x1 << 9) 1091 #define RT5670_CLSD_OC_SFT 9 1092 #define RT5670_CLSD_OC_PU (0x0 << 9) 1093 #define RT5670_CLSD_OC_PD (0x1 << 9) 1094 #define RT5670_AUTO_PD_MASK (0x1 << 8) 1095 #define RT5670_AUTO_PD_SFT 8 1096 #define RT5670_AUTO_PD_DIS (0x0 << 8) 1097 #define RT5670_AUTO_PD_EN (0x1 << 8) 1098 #define RT5670_CLSD_OC_TH_MASK (0x3f) 1099 #define RT5670_CLSD_OC_TH_SFT 0 1100 1101 /* Class D Output Control (0x8d) */ 1102 #define RT5670_CLSD_RATIO_MASK (0xf << 12) 1103 #define RT5670_CLSD_RATIO_SFT 12 1104 #define RT5670_CLSD_OM_MASK (0x1 << 11) 1105 #define RT5670_CLSD_OM_SFT 11 1106 #define RT5670_CLSD_OM_MONO (0x0 << 11) 1107 #define RT5670_CLSD_OM_STO (0x1 << 11) 1108 #define RT5670_CLSD_SCH_MASK (0x1 << 10) 1109 #define RT5670_CLSD_SCH_SFT 10 1110 #define RT5670_CLSD_SCH_L (0x0 << 10) 1111 #define RT5670_CLSD_SCH_S (0x1 << 10) 1112 1113 /* Depop Mode Control 1 (0x8e) */ 1114 #define RT5670_SMT_TRIG_MASK (0x1 << 15) 1115 #define RT5670_SMT_TRIG_SFT 15 1116 #define RT5670_SMT_TRIG_DIS (0x0 << 15) 1117 #define RT5670_SMT_TRIG_EN (0x1 << 15) 1118 #define RT5670_HP_L_SMT_MASK (0x1 << 9) 1119 #define RT5670_HP_L_SMT_SFT 9 1120 #define RT5670_HP_L_SMT_DIS (0x0 << 9) 1121 #define RT5670_HP_L_SMT_EN (0x1 << 9) 1122 #define RT5670_HP_R_SMT_MASK (0x1 << 8) 1123 #define RT5670_HP_R_SMT_SFT 8 1124 #define RT5670_HP_R_SMT_DIS (0x0 << 8) 1125 #define RT5670_HP_R_SMT_EN (0x1 << 8) 1126 #define RT5670_HP_CD_PD_MASK (0x1 << 7) 1127 #define RT5670_HP_CD_PD_SFT 7 1128 #define RT5670_HP_CD_PD_DIS (0x0 << 7) 1129 #define RT5670_HP_CD_PD_EN (0x1 << 7) 1130 #define RT5670_RSTN_MASK (0x1 << 6) 1131 #define RT5670_RSTN_SFT 6 1132 #define RT5670_RSTN_DIS (0x0 << 6) 1133 #define RT5670_RSTN_EN (0x1 << 6) 1134 #define RT5670_RSTP_MASK (0x1 << 5) 1135 #define RT5670_RSTP_SFT 5 1136 #define RT5670_RSTP_DIS (0x0 << 5) 1137 #define RT5670_RSTP_EN (0x1 << 5) 1138 #define RT5670_HP_CO_MASK (0x1 << 4) 1139 #define RT5670_HP_CO_SFT 4 1140 #define RT5670_HP_CO_DIS (0x0 << 4) 1141 #define RT5670_HP_CO_EN (0x1 << 4) 1142 #define RT5670_HP_CP_MASK (0x1 << 3) 1143 #define RT5670_HP_CP_SFT 3 1144 #define RT5670_HP_CP_PD (0x0 << 3) 1145 #define RT5670_HP_CP_PU (0x1 << 3) 1146 #define RT5670_HP_SG_MASK (0x1 << 2) 1147 #define RT5670_HP_SG_SFT 2 1148 #define RT5670_HP_SG_DIS (0x0 << 2) 1149 #define RT5670_HP_SG_EN (0x1 << 2) 1150 #define RT5670_HP_DP_MASK (0x1 << 1) 1151 #define RT5670_HP_DP_SFT 1 1152 #define RT5670_HP_DP_PD (0x0 << 1) 1153 #define RT5670_HP_DP_PU (0x1 << 1) 1154 #define RT5670_HP_CB_MASK (0x1) 1155 #define RT5670_HP_CB_SFT 0 1156 #define RT5670_HP_CB_PD (0x0) 1157 #define RT5670_HP_CB_PU (0x1) 1158 1159 /* Depop Mode Control 2 (0x8f) */ 1160 #define RT5670_DEPOP_MASK (0x1 << 13) 1161 #define RT5670_DEPOP_SFT 13 1162 #define RT5670_DEPOP_AUTO (0x0 << 13) 1163 #define RT5670_DEPOP_MAN (0x1 << 13) 1164 #define RT5670_RAMP_MASK (0x1 << 12) 1165 #define RT5670_RAMP_SFT 12 1166 #define RT5670_RAMP_DIS (0x0 << 12) 1167 #define RT5670_RAMP_EN (0x1 << 12) 1168 #define RT5670_BPS_MASK (0x1 << 11) 1169 #define RT5670_BPS_SFT 11 1170 #define RT5670_BPS_DIS (0x0 << 11) 1171 #define RT5670_BPS_EN (0x1 << 11) 1172 #define RT5670_FAST_UPDN_MASK (0x1 << 10) 1173 #define RT5670_FAST_UPDN_SFT 10 1174 #define RT5670_FAST_UPDN_DIS (0x0 << 10) 1175 #define RT5670_FAST_UPDN_EN (0x1 << 10) 1176 #define RT5670_MRES_MASK (0x3 << 8) 1177 #define RT5670_MRES_SFT 8 1178 #define RT5670_MRES_15MO (0x0 << 8) 1179 #define RT5670_MRES_25MO (0x1 << 8) 1180 #define RT5670_MRES_35MO (0x2 << 8) 1181 #define RT5670_MRES_45MO (0x3 << 8) 1182 #define RT5670_VLO_MASK (0x1 << 7) 1183 #define RT5670_VLO_SFT 7 1184 #define RT5670_VLO_3V (0x0 << 7) 1185 #define RT5670_VLO_32V (0x1 << 7) 1186 #define RT5670_DIG_DP_MASK (0x1 << 6) 1187 #define RT5670_DIG_DP_SFT 6 1188 #define RT5670_DIG_DP_DIS (0x0 << 6) 1189 #define RT5670_DIG_DP_EN (0x1 << 6) 1190 #define RT5670_DP_TH_MASK (0x3 << 4) 1191 #define RT5670_DP_TH_SFT 4 1192 1193 /* Depop Mode Control 3 (0x90) */ 1194 #define RT5670_CP_SYS_MASK (0x7 << 12) 1195 #define RT5670_CP_SYS_SFT 12 1196 #define RT5670_CP_FQ1_MASK (0x7 << 8) 1197 #define RT5670_CP_FQ1_SFT 8 1198 #define RT5670_CP_FQ2_MASK (0x7 << 4) 1199 #define RT5670_CP_FQ2_SFT 4 1200 #define RT5670_CP_FQ3_MASK (0x7) 1201 #define RT5670_CP_FQ3_SFT 0 1202 #define RT5670_CP_FQ_1_5_KHZ 0 1203 #define RT5670_CP_FQ_3_KHZ 1 1204 #define RT5670_CP_FQ_6_KHZ 2 1205 #define RT5670_CP_FQ_12_KHZ 3 1206 #define RT5670_CP_FQ_24_KHZ 4 1207 #define RT5670_CP_FQ_48_KHZ 5 1208 #define RT5670_CP_FQ_96_KHZ 6 1209 #define RT5670_CP_FQ_192_KHZ 7 1210 1211 /* HPOUT charge pump (0x91) */ 1212 #define RT5670_OSW_L_MASK (0x1 << 11) 1213 #define RT5670_OSW_L_SFT 11 1214 #define RT5670_OSW_L_DIS (0x0 << 11) 1215 #define RT5670_OSW_L_EN (0x1 << 11) 1216 #define RT5670_OSW_R_MASK (0x1 << 10) 1217 #define RT5670_OSW_R_SFT 10 1218 #define RT5670_OSW_R_DIS (0x0 << 10) 1219 #define RT5670_OSW_R_EN (0x1 << 10) 1220 #define RT5670_PM_HP_MASK (0x3 << 8) 1221 #define RT5670_PM_HP_SFT 8 1222 #define RT5670_PM_HP_LV (0x0 << 8) 1223 #define RT5670_PM_HP_MV (0x1 << 8) 1224 #define RT5670_PM_HP_HV (0x2 << 8) 1225 #define RT5670_IB_HP_MASK (0x3 << 6) 1226 #define RT5670_IB_HP_SFT 6 1227 #define RT5670_IB_HP_125IL (0x0 << 6) 1228 #define RT5670_IB_HP_25IL (0x1 << 6) 1229 #define RT5670_IB_HP_5IL (0x2 << 6) 1230 #define RT5670_IB_HP_1IL (0x3 << 6) 1231 1232 /* PV detection and SPK gain control (0x92) */ 1233 #define RT5670_PVDD_DET_MASK (0x1 << 15) 1234 #define RT5670_PVDD_DET_SFT 15 1235 #define RT5670_PVDD_DET_DIS (0x0 << 15) 1236 #define RT5670_PVDD_DET_EN (0x1 << 15) 1237 #define RT5670_SPK_AG_MASK (0x1 << 14) 1238 #define RT5670_SPK_AG_SFT 14 1239 #define RT5670_SPK_AG_DIS (0x0 << 14) 1240 #define RT5670_SPK_AG_EN (0x1 << 14) 1241 1242 /* Micbias Control (0x93) */ 1243 #define RT5670_MIC1_BS_MASK (0x1 << 15) 1244 #define RT5670_MIC1_BS_SFT 15 1245 #define RT5670_MIC1_BS_9AV (0x0 << 15) 1246 #define RT5670_MIC1_BS_75AV (0x1 << 15) 1247 #define RT5670_MIC2_BS_MASK (0x1 << 14) 1248 #define RT5670_MIC2_BS_SFT 14 1249 #define RT5670_MIC2_BS_9AV (0x0 << 14) 1250 #define RT5670_MIC2_BS_75AV (0x1 << 14) 1251 #define RT5670_MIC1_CLK_MASK (0x1 << 13) 1252 #define RT5670_MIC1_CLK_SFT 13 1253 #define RT5670_MIC1_CLK_DIS (0x0 << 13) 1254 #define RT5670_MIC1_CLK_EN (0x1 << 13) 1255 #define RT5670_MIC2_CLK_MASK (0x1 << 12) 1256 #define RT5670_MIC2_CLK_SFT 12 1257 #define RT5670_MIC2_CLK_DIS (0x0 << 12) 1258 #define RT5670_MIC2_CLK_EN (0x1 << 12) 1259 #define RT5670_MIC1_OVCD_MASK (0x1 << 11) 1260 #define RT5670_MIC1_OVCD_SFT 11 1261 #define RT5670_MIC1_OVCD_DIS (0x0 << 11) 1262 #define RT5670_MIC1_OVCD_EN (0x1 << 11) 1263 #define RT5670_MIC1_OVTH_MASK (0x3 << 9) 1264 #define RT5670_MIC1_OVTH_SFT 9 1265 #define RT5670_MIC1_OVTH_600UA (0x0 << 9) 1266 #define RT5670_MIC1_OVTH_1500UA (0x1 << 9) 1267 #define RT5670_MIC1_OVTH_2000UA (0x2 << 9) 1268 #define RT5670_MIC2_OVCD_MASK (0x1 << 8) 1269 #define RT5670_MIC2_OVCD_SFT 8 1270 #define RT5670_MIC2_OVCD_DIS (0x0 << 8) 1271 #define RT5670_MIC2_OVCD_EN (0x1 << 8) 1272 #define RT5670_MIC2_OVTH_MASK (0x3 << 6) 1273 #define RT5670_MIC2_OVTH_SFT 6 1274 #define RT5670_MIC2_OVTH_600UA (0x0 << 6) 1275 #define RT5670_MIC2_OVTH_1500UA (0x1 << 6) 1276 #define RT5670_MIC2_OVTH_2000UA (0x2 << 6) 1277 #define RT5670_PWR_MB_MASK (0x1 << 5) 1278 #define RT5670_PWR_MB_SFT 5 1279 #define RT5670_PWR_MB_PD (0x0 << 5) 1280 #define RT5670_PWR_MB_PU (0x1 << 5) 1281 #define RT5670_PWR_CLK25M_MASK (0x1 << 4) 1282 #define RT5670_PWR_CLK25M_SFT 4 1283 #define RT5670_PWR_CLK25M_PD (0x0 << 4) 1284 #define RT5670_PWR_CLK25M_PU (0x1 << 4) 1285 1286 /* Analog JD Control 1 (0x94) */ 1287 #define RT5670_JD1_MODE_MASK (0x3 << 0) 1288 #define RT5670_JD1_MODE_0 (0x0 << 0) 1289 #define RT5670_JD1_MODE_1 (0x1 << 0) 1290 #define RT5670_JD1_MODE_2 (0x2 << 0) 1291 1292 /* VAD Control 4 (0x9d) */ 1293 #define RT5670_VAD_SEL_MASK (0x3 << 8) 1294 #define RT5670_VAD_SEL_SFT 8 1295 1296 /* EQ Control 1 (0xb0) */ 1297 #define RT5670_EQ_SRC_MASK (0x1 << 15) 1298 #define RT5670_EQ_SRC_SFT 15 1299 #define RT5670_EQ_SRC_DAC (0x0 << 15) 1300 #define RT5670_EQ_SRC_ADC (0x1 << 15) 1301 #define RT5670_EQ_UPD (0x1 << 14) 1302 #define RT5670_EQ_UPD_BIT 14 1303 #define RT5670_EQ_CD_MASK (0x1 << 13) 1304 #define RT5670_EQ_CD_SFT 13 1305 #define RT5670_EQ_CD_DIS (0x0 << 13) 1306 #define RT5670_EQ_CD_EN (0x1 << 13) 1307 #define RT5670_EQ_DITH_MASK (0x3 << 8) 1308 #define RT5670_EQ_DITH_SFT 8 1309 #define RT5670_EQ_DITH_NOR (0x0 << 8) 1310 #define RT5670_EQ_DITH_LSB (0x1 << 8) 1311 #define RT5670_EQ_DITH_LSB_1 (0x2 << 8) 1312 #define RT5670_EQ_DITH_LSB_2 (0x3 << 8) 1313 1314 /* EQ Control 2 (0xb1) */ 1315 #define RT5670_EQ_HPF1_M_MASK (0x1 << 8) 1316 #define RT5670_EQ_HPF1_M_SFT 8 1317 #define RT5670_EQ_HPF1_M_HI (0x0 << 8) 1318 #define RT5670_EQ_HPF1_M_1ST (0x1 << 8) 1319 #define RT5670_EQ_LPF1_M_MASK (0x1 << 7) 1320 #define RT5670_EQ_LPF1_M_SFT 7 1321 #define RT5670_EQ_LPF1_M_LO (0x0 << 7) 1322 #define RT5670_EQ_LPF1_M_1ST (0x1 << 7) 1323 #define RT5670_EQ_HPF2_MASK (0x1 << 6) 1324 #define RT5670_EQ_HPF2_SFT 6 1325 #define RT5670_EQ_HPF2_DIS (0x0 << 6) 1326 #define RT5670_EQ_HPF2_EN (0x1 << 6) 1327 #define RT5670_EQ_HPF1_MASK (0x1 << 5) 1328 #define RT5670_EQ_HPF1_SFT 5 1329 #define RT5670_EQ_HPF1_DIS (0x0 << 5) 1330 #define RT5670_EQ_HPF1_EN (0x1 << 5) 1331 #define RT5670_EQ_BPF4_MASK (0x1 << 4) 1332 #define RT5670_EQ_BPF4_SFT 4 1333 #define RT5670_EQ_BPF4_DIS (0x0 << 4) 1334 #define RT5670_EQ_BPF4_EN (0x1 << 4) 1335 #define RT5670_EQ_BPF3_MASK (0x1 << 3) 1336 #define RT5670_EQ_BPF3_SFT 3 1337 #define RT5670_EQ_BPF3_DIS (0x0 << 3) 1338 #define RT5670_EQ_BPF3_EN (0x1 << 3) 1339 #define RT5670_EQ_BPF2_MASK (0x1 << 2) 1340 #define RT5670_EQ_BPF2_SFT 2 1341 #define RT5670_EQ_BPF2_DIS (0x0 << 2) 1342 #define RT5670_EQ_BPF2_EN (0x1 << 2) 1343 #define RT5670_EQ_BPF1_MASK (0x1 << 1) 1344 #define RT5670_EQ_BPF1_SFT 1 1345 #define RT5670_EQ_BPF1_DIS (0x0 << 1) 1346 #define RT5670_EQ_BPF1_EN (0x1 << 1) 1347 #define RT5670_EQ_LPF_MASK (0x1) 1348 #define RT5670_EQ_LPF_SFT 0 1349 #define RT5670_EQ_LPF_DIS (0x0) 1350 #define RT5670_EQ_LPF_EN (0x1) 1351 #define RT5670_EQ_CTRL_MASK (0x7f) 1352 1353 /* Memory Test (0xb2) */ 1354 #define RT5670_MT_MASK (0x1 << 15) 1355 #define RT5670_MT_SFT 15 1356 #define RT5670_MT_DIS (0x0 << 15) 1357 #define RT5670_MT_EN (0x1 << 15) 1358 1359 /* DRC/AGC Control 1 (0xb4) */ 1360 #define RT5670_DRC_AGC_P_MASK (0x1 << 15) 1361 #define RT5670_DRC_AGC_P_SFT 15 1362 #define RT5670_DRC_AGC_P_DAC (0x0 << 15) 1363 #define RT5670_DRC_AGC_P_ADC (0x1 << 15) 1364 #define RT5670_DRC_AGC_MASK (0x1 << 14) 1365 #define RT5670_DRC_AGC_SFT 14 1366 #define RT5670_DRC_AGC_DIS (0x0 << 14) 1367 #define RT5670_DRC_AGC_EN (0x1 << 14) 1368 #define RT5670_DRC_AGC_UPD (0x1 << 13) 1369 #define RT5670_DRC_AGC_UPD_BIT 13 1370 #define RT5670_DRC_AGC_AR_MASK (0x1f << 8) 1371 #define RT5670_DRC_AGC_AR_SFT 8 1372 #define RT5670_DRC_AGC_R_MASK (0x7 << 5) 1373 #define RT5670_DRC_AGC_R_SFT 5 1374 #define RT5670_DRC_AGC_R_48K (0x1 << 5) 1375 #define RT5670_DRC_AGC_R_96K (0x2 << 5) 1376 #define RT5670_DRC_AGC_R_192K (0x3 << 5) 1377 #define RT5670_DRC_AGC_R_441K (0x5 << 5) 1378 #define RT5670_DRC_AGC_R_882K (0x6 << 5) 1379 #define RT5670_DRC_AGC_R_1764K (0x7 << 5) 1380 #define RT5670_DRC_AGC_RC_MASK (0x1f) 1381 #define RT5670_DRC_AGC_RC_SFT 0 1382 1383 /* DRC/AGC Control 2 (0xb5) */ 1384 #define RT5670_DRC_AGC_POB_MASK (0x3f << 8) 1385 #define RT5670_DRC_AGC_POB_SFT 8 1386 #define RT5670_DRC_AGC_CP_MASK (0x1 << 7) 1387 #define RT5670_DRC_AGC_CP_SFT 7 1388 #define RT5670_DRC_AGC_CP_DIS (0x0 << 7) 1389 #define RT5670_DRC_AGC_CP_EN (0x1 << 7) 1390 #define RT5670_DRC_AGC_CPR_MASK (0x3 << 5) 1391 #define RT5670_DRC_AGC_CPR_SFT 5 1392 #define RT5670_DRC_AGC_CPR_1_1 (0x0 << 5) 1393 #define RT5670_DRC_AGC_CPR_1_2 (0x1 << 5) 1394 #define RT5670_DRC_AGC_CPR_1_3 (0x2 << 5) 1395 #define RT5670_DRC_AGC_CPR_1_4 (0x3 << 5) 1396 #define RT5670_DRC_AGC_PRB_MASK (0x1f) 1397 #define RT5670_DRC_AGC_PRB_SFT 0 1398 1399 /* DRC/AGC Control 3 (0xb6) */ 1400 #define RT5670_DRC_AGC_NGB_MASK (0xf << 12) 1401 #define RT5670_DRC_AGC_NGB_SFT 12 1402 #define RT5670_DRC_AGC_TAR_MASK (0x1f << 7) 1403 #define RT5670_DRC_AGC_TAR_SFT 7 1404 #define RT5670_DRC_AGC_NG_MASK (0x1 << 6) 1405 #define RT5670_DRC_AGC_NG_SFT 6 1406 #define RT5670_DRC_AGC_NG_DIS (0x0 << 6) 1407 #define RT5670_DRC_AGC_NG_EN (0x1 << 6) 1408 #define RT5670_DRC_AGC_NGH_MASK (0x1 << 5) 1409 #define RT5670_DRC_AGC_NGH_SFT 5 1410 #define RT5670_DRC_AGC_NGH_DIS (0x0 << 5) 1411 #define RT5670_DRC_AGC_NGH_EN (0x1 << 5) 1412 #define RT5670_DRC_AGC_NGT_MASK (0x1f) 1413 #define RT5670_DRC_AGC_NGT_SFT 0 1414 1415 /* Jack Detect Control (0xbb) */ 1416 #define RT5670_JD_MASK (0x7 << 13) 1417 #define RT5670_JD_SFT 13 1418 #define RT5670_JD_DIS (0x0 << 13) 1419 #define RT5670_JD_GPIO1 (0x1 << 13) 1420 #define RT5670_JD_JD1_IN4P (0x2 << 13) 1421 #define RT5670_JD_JD2_IN4N (0x3 << 13) 1422 #define RT5670_JD_GPIO2 (0x4 << 13) 1423 #define RT5670_JD_GPIO3 (0x5 << 13) 1424 #define RT5670_JD_GPIO4 (0x6 << 13) 1425 #define RT5670_JD_HP_MASK (0x1 << 11) 1426 #define RT5670_JD_HP_SFT 11 1427 #define RT5670_JD_HP_DIS (0x0 << 11) 1428 #define RT5670_JD_HP_EN (0x1 << 11) 1429 #define RT5670_JD_HP_TRG_MASK (0x1 << 10) 1430 #define RT5670_JD_HP_TRG_SFT 10 1431 #define RT5670_JD_HP_TRG_LO (0x0 << 10) 1432 #define RT5670_JD_HP_TRG_HI (0x1 << 10) 1433 #define RT5670_JD_SPL_MASK (0x1 << 9) 1434 #define RT5670_JD_SPL_SFT 9 1435 #define RT5670_JD_SPL_DIS (0x0 << 9) 1436 #define RT5670_JD_SPL_EN (0x1 << 9) 1437 #define RT5670_JD_SPL_TRG_MASK (0x1 << 8) 1438 #define RT5670_JD_SPL_TRG_SFT 8 1439 #define RT5670_JD_SPL_TRG_LO (0x0 << 8) 1440 #define RT5670_JD_SPL_TRG_HI (0x1 << 8) 1441 #define RT5670_JD_SPR_MASK (0x1 << 7) 1442 #define RT5670_JD_SPR_SFT 7 1443 #define RT5670_JD_SPR_DIS (0x0 << 7) 1444 #define RT5670_JD_SPR_EN (0x1 << 7) 1445 #define RT5670_JD_SPR_TRG_MASK (0x1 << 6) 1446 #define RT5670_JD_SPR_TRG_SFT 6 1447 #define RT5670_JD_SPR_TRG_LO (0x0 << 6) 1448 #define RT5670_JD_SPR_TRG_HI (0x1 << 6) 1449 #define RT5670_JD_MO_MASK (0x1 << 5) 1450 #define RT5670_JD_MO_SFT 5 1451 #define RT5670_JD_MO_DIS (0x0 << 5) 1452 #define RT5670_JD_MO_EN (0x1 << 5) 1453 #define RT5670_JD_MO_TRG_MASK (0x1 << 4) 1454 #define RT5670_JD_MO_TRG_SFT 4 1455 #define RT5670_JD_MO_TRG_LO (0x0 << 4) 1456 #define RT5670_JD_MO_TRG_HI (0x1 << 4) 1457 #define RT5670_JD_LO_MASK (0x1 << 3) 1458 #define RT5670_JD_LO_SFT 3 1459 #define RT5670_JD_LO_DIS (0x0 << 3) 1460 #define RT5670_JD_LO_EN (0x1 << 3) 1461 #define RT5670_JD_LO_TRG_MASK (0x1 << 2) 1462 #define RT5670_JD_LO_TRG_SFT 2 1463 #define RT5670_JD_LO_TRG_LO (0x0 << 2) 1464 #define RT5670_JD_LO_TRG_HI (0x1 << 2) 1465 #define RT5670_JD1_IN4P_MASK (0x1 << 1) 1466 #define RT5670_JD1_IN4P_SFT 1 1467 #define RT5670_JD1_IN4P_DIS (0x0 << 1) 1468 #define RT5670_JD1_IN4P_EN (0x1 << 1) 1469 #define RT5670_JD2_IN4N_MASK (0x1) 1470 #define RT5670_JD2_IN4N_SFT 0 1471 #define RT5670_JD2_IN4N_DIS (0x0) 1472 #define RT5670_JD2_IN4N_EN (0x1) 1473 1474 /* IRQ Control 1 (0xbd) */ 1475 #define RT5670_IRQ_JD_MASK (0x1 << 15) 1476 #define RT5670_IRQ_JD_SFT 15 1477 #define RT5670_IRQ_JD_BP (0x0 << 15) 1478 #define RT5670_IRQ_JD_NOR (0x1 << 15) 1479 #define RT5670_IRQ_OT_MASK (0x1 << 14) 1480 #define RT5670_IRQ_OT_SFT 14 1481 #define RT5670_IRQ_OT_BP (0x0 << 14) 1482 #define RT5670_IRQ_OT_NOR (0x1 << 14) 1483 #define RT5670_JD_STKY_MASK (0x1 << 13) 1484 #define RT5670_JD_STKY_SFT 13 1485 #define RT5670_JD_STKY_DIS (0x0 << 13) 1486 #define RT5670_JD_STKY_EN (0x1 << 13) 1487 #define RT5670_OT_STKY_MASK (0x1 << 12) 1488 #define RT5670_OT_STKY_SFT 12 1489 #define RT5670_OT_STKY_DIS (0x0 << 12) 1490 #define RT5670_OT_STKY_EN (0x1 << 12) 1491 #define RT5670_JD_P_MASK (0x1 << 11) 1492 #define RT5670_JD_P_SFT 11 1493 #define RT5670_JD_P_NOR (0x0 << 11) 1494 #define RT5670_JD_P_INV (0x1 << 11) 1495 #define RT5670_OT_P_MASK (0x1 << 10) 1496 #define RT5670_OT_P_SFT 10 1497 #define RT5670_OT_P_NOR (0x0 << 10) 1498 #define RT5670_OT_P_INV (0x1 << 10) 1499 #define RT5670_JD1_1_EN_MASK (0x1 << 9) 1500 #define RT5670_JD1_1_EN_SFT 9 1501 #define RT5670_JD1_1_DIS (0x0 << 9) 1502 #define RT5670_JD1_1_EN (0x1 << 9) 1503 1504 /* IRQ Control 2 (0xbe) */ 1505 #define RT5670_IRQ_MB1_OC_MASK (0x1 << 15) 1506 #define RT5670_IRQ_MB1_OC_SFT 15 1507 #define RT5670_IRQ_MB1_OC_BP (0x0 << 15) 1508 #define RT5670_IRQ_MB1_OC_NOR (0x1 << 15) 1509 #define RT5670_IRQ_MB2_OC_MASK (0x1 << 14) 1510 #define RT5670_IRQ_MB2_OC_SFT 14 1511 #define RT5670_IRQ_MB2_OC_BP (0x0 << 14) 1512 #define RT5670_IRQ_MB2_OC_NOR (0x1 << 14) 1513 #define RT5670_MB1_OC_STKY_MASK (0x1 << 11) 1514 #define RT5670_MB1_OC_STKY_SFT 11 1515 #define RT5670_MB1_OC_STKY_DIS (0x0 << 11) 1516 #define RT5670_MB1_OC_STKY_EN (0x1 << 11) 1517 #define RT5670_MB2_OC_STKY_MASK (0x1 << 10) 1518 #define RT5670_MB2_OC_STKY_SFT 10 1519 #define RT5670_MB2_OC_STKY_DIS (0x0 << 10) 1520 #define RT5670_MB2_OC_STKY_EN (0x1 << 10) 1521 #define RT5670_MB1_OC_P_MASK (0x1 << 7) 1522 #define RT5670_MB1_OC_P_SFT 7 1523 #define RT5670_MB1_OC_P_NOR (0x0 << 7) 1524 #define RT5670_MB1_OC_P_INV (0x1 << 7) 1525 #define RT5670_MB2_OC_P_MASK (0x1 << 6) 1526 #define RT5670_MB2_OC_P_SFT 6 1527 #define RT5670_MB2_OC_P_NOR (0x0 << 6) 1528 #define RT5670_MB2_OC_P_INV (0x1 << 6) 1529 #define RT5670_MB1_OC_CLR (0x1 << 3) 1530 #define RT5670_MB1_OC_CLR_SFT 3 1531 #define RT5670_MB2_OC_CLR (0x1 << 2) 1532 #define RT5670_MB2_OC_CLR_SFT 2 1533 1534 /* GPIO Control 1 (0xc0) */ 1535 #define RT5670_GP1_PIN_MASK (0x1 << 15) 1536 #define RT5670_GP1_PIN_SFT 15 1537 #define RT5670_GP1_PIN_GPIO1 (0x0 << 15) 1538 #define RT5670_GP1_PIN_IRQ (0x1 << 15) 1539 #define RT5670_GP2_PIN_MASK (0x1 << 14) 1540 #define RT5670_GP2_PIN_SFT 14 1541 #define RT5670_GP2_PIN_GPIO2 (0x0 << 14) 1542 #define RT5670_GP2_PIN_DMIC1_SCL (0x1 << 14) 1543 #define RT5670_GP3_PIN_MASK (0x3 << 12) 1544 #define RT5670_GP3_PIN_SFT 12 1545 #define RT5670_GP3_PIN_GPIO3 (0x0 << 12) 1546 #define RT5670_GP3_PIN_DMIC1_SDA (0x1 << 12) 1547 #define RT5670_GP3_PIN_IRQ (0x2 << 12) 1548 #define RT5670_GP4_PIN_MASK (0x1 << 11) 1549 #define RT5670_GP4_PIN_SFT 11 1550 #define RT5670_GP4_PIN_GPIO4 (0x0 << 11) 1551 #define RT5670_GP4_PIN_DMIC2_SDA (0x1 << 11) 1552 #define RT5670_DP_SIG_MASK (0x1 << 10) 1553 #define RT5670_DP_SIG_SFT 10 1554 #define RT5670_DP_SIG_TEST (0x0 << 10) 1555 #define RT5670_DP_SIG_AP (0x1 << 10) 1556 #define RT5670_GPIO_M_MASK (0x1 << 9) 1557 #define RT5670_GPIO_M_SFT 9 1558 #define RT5670_GPIO_M_FLT (0x0 << 9) 1559 #define RT5670_GPIO_M_PH (0x1 << 9) 1560 #define RT5670_I2S2_PIN_MASK (0x1 << 8) 1561 #define RT5670_I2S2_PIN_SFT 8 1562 #define RT5670_I2S2_PIN_I2S (0x0 << 8) 1563 #define RT5670_I2S2_PIN_GPIO (0x1 << 8) 1564 #define RT5670_GP5_PIN_MASK (0x1 << 7) 1565 #define RT5670_GP5_PIN_SFT 7 1566 #define RT5670_GP5_PIN_GPIO5 (0x0 << 7) 1567 #define RT5670_GP5_PIN_DMIC3_SDA (0x1 << 7) 1568 #define RT5670_GP6_PIN_MASK (0x1 << 6) 1569 #define RT5670_GP6_PIN_SFT 6 1570 #define RT5670_GP6_PIN_GPIO6 (0x0 << 6) 1571 #define RT5670_GP6_PIN_DMIC1_SDA (0x1 << 6) 1572 #define RT5670_GP7_PIN_MASK (0x3 << 4) 1573 #define RT5670_GP7_PIN_SFT 4 1574 #define RT5670_GP7_PIN_GPIO7 (0x0 << 4) 1575 #define RT5670_GP7_PIN_DMIC1_SDA (0x1 << 4) 1576 #define RT5670_GP7_PIN_PDM_SCL2 (0x2 << 4) 1577 #define RT5670_GP8_PIN_MASK (0x1 << 3) 1578 #define RT5670_GP8_PIN_SFT 3 1579 #define RT5670_GP8_PIN_GPIO8 (0x0 << 3) 1580 #define RT5670_GP8_PIN_DMIC2_SDA (0x1 << 3) 1581 #define RT5670_GP9_PIN_MASK (0x1 << 2) 1582 #define RT5670_GP9_PIN_SFT 2 1583 #define RT5670_GP9_PIN_GPIO9 (0x0 << 2) 1584 #define RT5670_GP9_PIN_DMIC3_SDA (0x1 << 2) 1585 #define RT5670_GP10_PIN_MASK (0x3) 1586 #define RT5670_GP10_PIN_SFT 0 1587 #define RT5670_GP10_PIN_GPIO9 (0x0) 1588 #define RT5670_GP10_PIN_DMIC3_SDA (0x1) 1589 #define RT5670_GP10_PIN_PDM_ADT2 (0x2) 1590 1591 /* GPIO Control 2 (0xc1) */ 1592 #define RT5670_GP4_PF_MASK (0x1 << 11) 1593 #define RT5670_GP4_PF_SFT 11 1594 #define RT5670_GP4_PF_IN (0x0 << 11) 1595 #define RT5670_GP4_PF_OUT (0x1 << 11) 1596 #define RT5670_GP4_OUT_MASK (0x1 << 10) 1597 #define RT5670_GP4_OUT_SFT 10 1598 #define RT5670_GP4_OUT_LO (0x0 << 10) 1599 #define RT5670_GP4_OUT_HI (0x1 << 10) 1600 #define RT5670_GP4_P_MASK (0x1 << 9) 1601 #define RT5670_GP4_P_SFT 9 1602 #define RT5670_GP4_P_NOR (0x0 << 9) 1603 #define RT5670_GP4_P_INV (0x1 << 9) 1604 #define RT5670_GP3_PF_MASK (0x1 << 8) 1605 #define RT5670_GP3_PF_SFT 8 1606 #define RT5670_GP3_PF_IN (0x0 << 8) 1607 #define RT5670_GP3_PF_OUT (0x1 << 8) 1608 #define RT5670_GP3_OUT_MASK (0x1 << 7) 1609 #define RT5670_GP3_OUT_SFT 7 1610 #define RT5670_GP3_OUT_LO (0x0 << 7) 1611 #define RT5670_GP3_OUT_HI (0x1 << 7) 1612 #define RT5670_GP3_P_MASK (0x1 << 6) 1613 #define RT5670_GP3_P_SFT 6 1614 #define RT5670_GP3_P_NOR (0x0 << 6) 1615 #define RT5670_GP3_P_INV (0x1 << 6) 1616 #define RT5670_GP2_PF_MASK (0x1 << 5) 1617 #define RT5670_GP2_PF_SFT 5 1618 #define RT5670_GP2_PF_IN (0x0 << 5) 1619 #define RT5670_GP2_PF_OUT (0x1 << 5) 1620 #define RT5670_GP2_OUT_MASK (0x1 << 4) 1621 #define RT5670_GP2_OUT_SFT 4 1622 #define RT5670_GP2_OUT_LO (0x0 << 4) 1623 #define RT5670_GP2_OUT_HI (0x1 << 4) 1624 #define RT5670_GP2_P_MASK (0x1 << 3) 1625 #define RT5670_GP2_P_SFT 3 1626 #define RT5670_GP2_P_NOR (0x0 << 3) 1627 #define RT5670_GP2_P_INV (0x1 << 3) 1628 #define RT5670_GP1_PF_MASK (0x1 << 2) 1629 #define RT5670_GP1_PF_SFT 2 1630 #define RT5670_GP1_PF_IN (0x0 << 2) 1631 #define RT5670_GP1_PF_OUT (0x1 << 2) 1632 #define RT5670_GP1_OUT_MASK (0x1 << 1) 1633 #define RT5670_GP1_OUT_SFT 1 1634 #define RT5670_GP1_OUT_LO (0x0 << 1) 1635 #define RT5670_GP1_OUT_HI (0x1 << 1) 1636 #define RT5670_GP1_P_MASK (0x1) 1637 #define RT5670_GP1_P_SFT 0 1638 #define RT5670_GP1_P_NOR (0x0) 1639 #define RT5670_GP1_P_INV (0x1) 1640 1641 /* Scramble Function (0xcd) */ 1642 #define RT5670_SCB_KEY_MASK (0xff) 1643 #define RT5670_SCB_KEY_SFT 0 1644 1645 /* Scramble Control (0xce) */ 1646 #define RT5670_SCB_SWAP_MASK (0x1 << 15) 1647 #define RT5670_SCB_SWAP_SFT 15 1648 #define RT5670_SCB_SWAP_DIS (0x0 << 15) 1649 #define RT5670_SCB_SWAP_EN (0x1 << 15) 1650 #define RT5670_SCB_MASK (0x1 << 14) 1651 #define RT5670_SCB_SFT 14 1652 #define RT5670_SCB_DIS (0x0 << 14) 1653 #define RT5670_SCB_EN (0x1 << 14) 1654 1655 /* Baseback Control (0xcf) */ 1656 #define RT5670_BB_MASK (0x1 << 15) 1657 #define RT5670_BB_SFT 15 1658 #define RT5670_BB_DIS (0x0 << 15) 1659 #define RT5670_BB_EN (0x1 << 15) 1660 #define RT5670_BB_CT_MASK (0x7 << 12) 1661 #define RT5670_BB_CT_SFT 12 1662 #define RT5670_BB_CT_A (0x0 << 12) 1663 #define RT5670_BB_CT_B (0x1 << 12) 1664 #define RT5670_BB_CT_C (0x2 << 12) 1665 #define RT5670_BB_CT_D (0x3 << 12) 1666 #define RT5670_M_BB_L_MASK (0x1 << 9) 1667 #define RT5670_M_BB_L_SFT 9 1668 #define RT5670_M_BB_R_MASK (0x1 << 8) 1669 #define RT5670_M_BB_R_SFT 8 1670 #define RT5670_M_BB_HPF_L_MASK (0x1 << 7) 1671 #define RT5670_M_BB_HPF_L_SFT 7 1672 #define RT5670_M_BB_HPF_R_MASK (0x1 << 6) 1673 #define RT5670_M_BB_HPF_R_SFT 6 1674 #define RT5670_G_BB_BST_MASK (0x3f) 1675 #define RT5670_G_BB_BST_SFT 0 1676 1677 /* MP3 Plus Control 1 (0xd0) */ 1678 #define RT5670_M_MP3_L_MASK (0x1 << 15) 1679 #define RT5670_M_MP3_L_SFT 15 1680 #define RT5670_M_MP3_R_MASK (0x1 << 14) 1681 #define RT5670_M_MP3_R_SFT 14 1682 #define RT5670_M_MP3_MASK (0x1 << 13) 1683 #define RT5670_M_MP3_SFT 13 1684 #define RT5670_M_MP3_DIS (0x0 << 13) 1685 #define RT5670_M_MP3_EN (0x1 << 13) 1686 #define RT5670_EG_MP3_MASK (0x1f << 8) 1687 #define RT5670_EG_MP3_SFT 8 1688 #define RT5670_MP3_HLP_MASK (0x1 << 7) 1689 #define RT5670_MP3_HLP_SFT 7 1690 #define RT5670_MP3_HLP_DIS (0x0 << 7) 1691 #define RT5670_MP3_HLP_EN (0x1 << 7) 1692 #define RT5670_M_MP3_ORG_L_MASK (0x1 << 6) 1693 #define RT5670_M_MP3_ORG_L_SFT 6 1694 #define RT5670_M_MP3_ORG_R_MASK (0x1 << 5) 1695 #define RT5670_M_MP3_ORG_R_SFT 5 1696 1697 /* MP3 Plus Control 2 (0xd1) */ 1698 #define RT5670_MP3_WT_MASK (0x1 << 13) 1699 #define RT5670_MP3_WT_SFT 13 1700 #define RT5670_MP3_WT_1_4 (0x0 << 13) 1701 #define RT5670_MP3_WT_1_2 (0x1 << 13) 1702 #define RT5670_OG_MP3_MASK (0x1f << 8) 1703 #define RT5670_OG_MP3_SFT 8 1704 #define RT5670_HG_MP3_MASK (0x3f) 1705 #define RT5670_HG_MP3_SFT 0 1706 1707 /* 3D HP Control 1 (0xd2) */ 1708 #define RT5670_3D_CF_MASK (0x1 << 15) 1709 #define RT5670_3D_CF_SFT 15 1710 #define RT5670_3D_CF_DIS (0x0 << 15) 1711 #define RT5670_3D_CF_EN (0x1 << 15) 1712 #define RT5670_3D_HP_MASK (0x1 << 14) 1713 #define RT5670_3D_HP_SFT 14 1714 #define RT5670_3D_HP_DIS (0x0 << 14) 1715 #define RT5670_3D_HP_EN (0x1 << 14) 1716 #define RT5670_3D_BT_MASK (0x1 << 13) 1717 #define RT5670_3D_BT_SFT 13 1718 #define RT5670_3D_BT_DIS (0x0 << 13) 1719 #define RT5670_3D_BT_EN (0x1 << 13) 1720 #define RT5670_3D_1F_MIX_MASK (0x3 << 11) 1721 #define RT5670_3D_1F_MIX_SFT 11 1722 #define RT5670_3D_HP_M_MASK (0x1 << 10) 1723 #define RT5670_3D_HP_M_SFT 10 1724 #define RT5670_3D_HP_M_SUR (0x0 << 10) 1725 #define RT5670_3D_HP_M_FRO (0x1 << 10) 1726 #define RT5670_M_3D_HRTF_MASK (0x1 << 9) 1727 #define RT5670_M_3D_HRTF_SFT 9 1728 #define RT5670_M_3D_D2H_MASK (0x1 << 8) 1729 #define RT5670_M_3D_D2H_SFT 8 1730 #define RT5670_M_3D_D2R_MASK (0x1 << 7) 1731 #define RT5670_M_3D_D2R_SFT 7 1732 #define RT5670_M_3D_REVB_MASK (0x1 << 6) 1733 #define RT5670_M_3D_REVB_SFT 6 1734 1735 /* Adjustable high pass filter control 1 (0xd3) */ 1736 #define RT5670_2ND_HPF_MASK (0x1 << 15) 1737 #define RT5670_2ND_HPF_SFT 15 1738 #define RT5670_2ND_HPF_DIS (0x0 << 15) 1739 #define RT5670_2ND_HPF_EN (0x1 << 15) 1740 #define RT5670_HPF_CF_L_MASK (0x7 << 12) 1741 #define RT5670_HPF_CF_L_SFT 12 1742 #define RT5670_1ST_HPF_MASK (0x1 << 11) 1743 #define RT5670_1ST_HPF_SFT 11 1744 #define RT5670_1ST_HPF_DIS (0x0 << 11) 1745 #define RT5670_1ST_HPF_EN (0x1 << 11) 1746 #define RT5670_HPF_CF_R_MASK (0x7 << 8) 1747 #define RT5670_HPF_CF_R_SFT 8 1748 #define RT5670_ZD_T_MASK (0x3 << 6) 1749 #define RT5670_ZD_T_SFT 6 1750 #define RT5670_ZD_F_MASK (0x3 << 4) 1751 #define RT5670_ZD_F_SFT 4 1752 #define RT5670_ZD_F_IM (0x0 << 4) 1753 #define RT5670_ZD_F_ZC_IM (0x1 << 4) 1754 #define RT5670_ZD_F_ZC_IOD (0x2 << 4) 1755 #define RT5670_ZD_F_UN (0x3 << 4) 1756 1757 /* HP calibration control and Amp detection (0xd6) */ 1758 #define RT5670_SI_DAC_MASK (0x1 << 11) 1759 #define RT5670_SI_DAC_SFT 11 1760 #define RT5670_SI_DAC_AUTO (0x0 << 11) 1761 #define RT5670_SI_DAC_TEST (0x1 << 11) 1762 #define RT5670_DC_CAL_M_MASK (0x1 << 10) 1763 #define RT5670_DC_CAL_M_SFT 10 1764 #define RT5670_DC_CAL_M_CAL (0x0 << 10) 1765 #define RT5670_DC_CAL_M_NOR (0x1 << 10) 1766 #define RT5670_DC_CAL_MASK (0x1 << 9) 1767 #define RT5670_DC_CAL_SFT 9 1768 #define RT5670_DC_CAL_DIS (0x0 << 9) 1769 #define RT5670_DC_CAL_EN (0x1 << 9) 1770 #define RT5670_HPD_RCV_MASK (0x7 << 6) 1771 #define RT5670_HPD_RCV_SFT 6 1772 #define RT5670_HPD_PS_MASK (0x1 << 5) 1773 #define RT5670_HPD_PS_SFT 5 1774 #define RT5670_HPD_PS_DIS (0x0 << 5) 1775 #define RT5670_HPD_PS_EN (0x1 << 5) 1776 #define RT5670_CAL_M_MASK (0x1 << 4) 1777 #define RT5670_CAL_M_SFT 4 1778 #define RT5670_CAL_M_DEP (0x0 << 4) 1779 #define RT5670_CAL_M_CAL (0x1 << 4) 1780 #define RT5670_CAL_MASK (0x1 << 3) 1781 #define RT5670_CAL_SFT 3 1782 #define RT5670_CAL_DIS (0x0 << 3) 1783 #define RT5670_CAL_EN (0x1 << 3) 1784 #define RT5670_CAL_TEST_MASK (0x1 << 2) 1785 #define RT5670_CAL_TEST_SFT 2 1786 #define RT5670_CAL_TEST_DIS (0x0 << 2) 1787 #define RT5670_CAL_TEST_EN (0x1 << 2) 1788 #define RT5670_CAL_P_MASK (0x3) 1789 #define RT5670_CAL_P_SFT 0 1790 #define RT5670_CAL_P_NONE (0x0) 1791 #define RT5670_CAL_P_CAL (0x1) 1792 #define RT5670_CAL_P_DAC_CAL (0x2) 1793 1794 /* Soft volume and zero cross control 1 (0xd9) */ 1795 #define RT5670_SV_MASK (0x1 << 15) 1796 #define RT5670_SV_SFT 15 1797 #define RT5670_SV_DIS (0x0 << 15) 1798 #define RT5670_SV_EN (0x1 << 15) 1799 #define RT5670_SPO_SV_MASK (0x1 << 14) 1800 #define RT5670_SPO_SV_SFT 14 1801 #define RT5670_SPO_SV_DIS (0x0 << 14) 1802 #define RT5670_SPO_SV_EN (0x1 << 14) 1803 #define RT5670_OUT_SV_MASK (0x1 << 13) 1804 #define RT5670_OUT_SV_SFT 13 1805 #define RT5670_OUT_SV_DIS (0x0 << 13) 1806 #define RT5670_OUT_SV_EN (0x1 << 13) 1807 #define RT5670_HP_SV_MASK (0x1 << 12) 1808 #define RT5670_HP_SV_SFT 12 1809 #define RT5670_HP_SV_DIS (0x0 << 12) 1810 #define RT5670_HP_SV_EN (0x1 << 12) 1811 #define RT5670_ZCD_DIG_MASK (0x1 << 11) 1812 #define RT5670_ZCD_DIG_SFT 11 1813 #define RT5670_ZCD_DIG_DIS (0x0 << 11) 1814 #define RT5670_ZCD_DIG_EN (0x1 << 11) 1815 #define RT5670_ZCD_MASK (0x1 << 10) 1816 #define RT5670_ZCD_SFT 10 1817 #define RT5670_ZCD_PD (0x0 << 10) 1818 #define RT5670_ZCD_PU (0x1 << 10) 1819 #define RT5670_M_ZCD_MASK (0x3f << 4) 1820 #define RT5670_M_ZCD_SFT 4 1821 #define RT5670_M_ZCD_RM_L (0x1 << 9) 1822 #define RT5670_M_ZCD_RM_R (0x1 << 8) 1823 #define RT5670_M_ZCD_SM_L (0x1 << 7) 1824 #define RT5670_M_ZCD_SM_R (0x1 << 6) 1825 #define RT5670_M_ZCD_OM_L (0x1 << 5) 1826 #define RT5670_M_ZCD_OM_R (0x1 << 4) 1827 #define RT5670_SV_DLY_MASK (0xf) 1828 #define RT5670_SV_DLY_SFT 0 1829 1830 /* Soft volume and zero cross control 2 (0xda) */ 1831 #define RT5670_ZCD_HP_MASK (0x1 << 15) 1832 #define RT5670_ZCD_HP_SFT 15 1833 #define RT5670_ZCD_HP_DIS (0x0 << 15) 1834 #define RT5670_ZCD_HP_EN (0x1 << 15) 1835 1836 1837 /* Codec Private Register definition */ 1838 /* 3D Speaker Control (0x63) */ 1839 #define RT5670_3D_SPK_MASK (0x1 << 15) 1840 #define RT5670_3D_SPK_SFT 15 1841 #define RT5670_3D_SPK_DIS (0x0 << 15) 1842 #define RT5670_3D_SPK_EN (0x1 << 15) 1843 #define RT5670_3D_SPK_M_MASK (0x3 << 13) 1844 #define RT5670_3D_SPK_M_SFT 13 1845 #define RT5670_3D_SPK_CG_MASK (0x1f << 8) 1846 #define RT5670_3D_SPK_CG_SFT 8 1847 #define RT5670_3D_SPK_SG_MASK (0x1f) 1848 #define RT5670_3D_SPK_SG_SFT 0 1849 1850 /* Wind Noise Detection Control 1 (0x6c) */ 1851 #define RT5670_WND_MASK (0x1 << 15) 1852 #define RT5670_WND_SFT 15 1853 #define RT5670_WND_DIS (0x0 << 15) 1854 #define RT5670_WND_EN (0x1 << 15) 1855 1856 /* Wind Noise Detection Control 2 (0x6d) */ 1857 #define RT5670_WND_FC_NW_MASK (0x3f << 10) 1858 #define RT5670_WND_FC_NW_SFT 10 1859 #define RT5670_WND_FC_WK_MASK (0x3f << 4) 1860 #define RT5670_WND_FC_WK_SFT 4 1861 1862 /* Wind Noise Detection Control 3 (0x6e) */ 1863 #define RT5670_HPF_FC_MASK (0x3f << 6) 1864 #define RT5670_HPF_FC_SFT 6 1865 #define RT5670_WND_FC_ST_MASK (0x3f) 1866 #define RT5670_WND_FC_ST_SFT 0 1867 1868 /* Wind Noise Detection Control 4 (0x6f) */ 1869 #define RT5670_WND_TH_LO_MASK (0x3ff) 1870 #define RT5670_WND_TH_LO_SFT 0 1871 1872 /* Wind Noise Detection Control 5 (0x70) */ 1873 #define RT5670_WND_TH_HI_MASK (0x3ff) 1874 #define RT5670_WND_TH_HI_SFT 0 1875 1876 /* Wind Noise Detection Control 8 (0x73) */ 1877 #define RT5670_WND_WIND_MASK (0x1 << 13) /* Read-Only */ 1878 #define RT5670_WND_WIND_SFT 13 1879 #define RT5670_WND_STRONG_MASK (0x1 << 12) /* Read-Only */ 1880 #define RT5670_WND_STRONG_SFT 12 1881 enum { 1882 RT5670_NO_WIND, 1883 RT5670_BREEZE, 1884 RT5670_STORM, 1885 }; 1886 1887 /* Dipole Speaker Interface (0x75) */ 1888 #define RT5670_DP_ATT_MASK (0x3 << 14) 1889 #define RT5670_DP_ATT_SFT 14 1890 #define RT5670_DP_SPK_MASK (0x1 << 10) 1891 #define RT5670_DP_SPK_SFT 10 1892 #define RT5670_DP_SPK_DIS (0x0 << 10) 1893 #define RT5670_DP_SPK_EN (0x1 << 10) 1894 1895 /* EQ Pre Volume Control (0xb3) */ 1896 #define RT5670_EQ_PRE_VOL_MASK (0xffff) 1897 #define RT5670_EQ_PRE_VOL_SFT 0 1898 1899 /* EQ Post Volume Control (0xb4) */ 1900 #define RT5670_EQ_PST_VOL_MASK (0xffff) 1901 #define RT5670_EQ_PST_VOL_SFT 0 1902 1903 /* Jack Detect Control 3 (0xf8) */ 1904 #define RT5670_CMP_MIC_IN_DET_MASK (0x7 << 12) 1905 #define RT5670_JD_CBJ_EN (0x1 << 7) 1906 #define RT5670_JD_CBJ_POL (0x1 << 6) 1907 #define RT5670_JD_TRI_CBJ_SEL_MASK (0x7 << 3) 1908 #define RT5670_JD_TRI_CBJ_SEL_SFT (3) 1909 #define RT5670_JD_CBJ_GPIO_JD1 (0x0 << 3) 1910 #define RT5670_JD_CBJ_JD1_1 (0x1 << 3) 1911 #define RT5670_JD_CBJ_JD1_2 (0x2 << 3) 1912 #define RT5670_JD_CBJ_JD2 (0x3 << 3) 1913 #define RT5670_JD_CBJ_JD3 (0x4 << 3) 1914 #define RT5670_JD_CBJ_GPIO_JD2 (0x5 << 3) 1915 #define RT5670_JD_CBJ_MX0B_12 (0x6 << 3) 1916 #define RT5670_JD_TRI_HPO_SEL_MASK (0x7 << 3) 1917 #define RT5670_JD_TRI_HPO_SEL_SFT (0) 1918 #define RT5670_JD_HPO_GPIO_JD1 (0x0) 1919 #define RT5670_JD_HPO_JD1_1 (0x1) 1920 #define RT5670_JD_HPO_JD1_2 (0x2) 1921 #define RT5670_JD_HPO_JD2 (0x3) 1922 #define RT5670_JD_HPO_JD3 (0x4) 1923 #define RT5670_JD_HPO_GPIO_JD2 (0x5) 1924 #define RT5670_JD_HPO_MX0B_12 (0x6) 1925 1926 /* Digital Misc Control (0xfa) */ 1927 #define RT5670_RST_DSP (0x1 << 13) 1928 #define RT5670_IF1_ADC1_IN1_SEL (0x1 << 12) 1929 #define RT5670_IF1_ADC1_IN1_SFT 12 1930 #define RT5670_IF1_ADC1_IN2_SEL (0x1 << 11) 1931 #define RT5670_IF1_ADC1_IN2_SFT 11 1932 #define RT5670_IF1_ADC2_IN1_SEL (0x1 << 10) 1933 #define RT5670_IF1_ADC2_IN1_SFT 10 1934 1935 /* General Control2 (0xfb) */ 1936 #define RT5670_RXDC_SRC_MASK (0x1 << 7) 1937 #define RT5670_RXDC_SRC_STO (0x0 << 7) 1938 #define RT5670_RXDC_SRC_MONO (0x1 << 7) 1939 #define RT5670_RXDC_SRC_SFT (7) 1940 #define RT5670_RXDP2_SEL_MASK (0x1 << 3) 1941 #define RT5670_RXDP2_SEL_IF2 (0x0 << 3) 1942 #define RT5670_RXDP2_SEL_ADC (0x1 << 3) 1943 #define RT5670_RXDP2_SEL_SFT (3) 1944 1945 /* System Clock Source */ 1946 enum { 1947 RT5670_SCLK_S_MCLK, 1948 RT5670_SCLK_S_PLL1, 1949 RT5670_SCLK_S_RCCLK, 1950 }; 1951 1952 /* PLL1 Source */ 1953 enum { 1954 RT5670_PLL1_S_MCLK, 1955 RT5670_PLL1_S_BCLK1, 1956 RT5670_PLL1_S_BCLK2, 1957 RT5670_PLL1_S_BCLK3, 1958 RT5670_PLL1_S_BCLK4, 1959 }; 1960 1961 enum { 1962 RT5670_AIF1, 1963 RT5670_AIF2, 1964 RT5670_AIF3, 1965 RT5670_AIF4, 1966 RT5670_AIFS, 1967 }; 1968 1969 enum { 1970 RT5670_DMIC_DATA_GPIO6, 1971 RT5670_DMIC_DATA_IN2P, 1972 RT5670_DMIC_DATA_GPIO7, 1973 }; 1974 1975 enum { 1976 RT5670_DMIC_DATA_GPIO8, 1977 RT5670_DMIC_DATA_IN3N, 1978 }; 1979 1980 enum { 1981 RT5670_DMIC_DATA_GPIO9, 1982 RT5670_DMIC_DATA_GPIO10, 1983 RT5670_DMIC_DATA_GPIO5, 1984 }; 1985 1986 struct rt5670_priv { 1987 struct snd_soc_codec *codec; 1988 struct rt5670_platform_data pdata; 1989 struct regmap *regmap; 1990 1991 int sysclk; 1992 int sysclk_src; 1993 int lrck[RT5670_AIFS]; 1994 int bclk[RT5670_AIFS]; 1995 int master[RT5670_AIFS]; 1996 1997 int pll_src; 1998 int pll_in; 1999 int pll_out; 2000 2001 int dsp_sw; /* expected parameter setting */ 2002 int dsp_rate; 2003 int jack_type; 2004 }; 2005 2006 #endif /* __RT5670_H__ */ 2007