1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * rt5668.c -- RT5668B ALSA SoC audio component driver 4 * 5 * Copyright 2018 Realtek Semiconductor Corp. 6 * Author: Bard Liao <bardliao@realtek.com> 7 */ 8 9 #include <linux/module.h> 10 #include <linux/moduleparam.h> 11 #include <linux/init.h> 12 #include <linux/delay.h> 13 #include <linux/pm.h> 14 #include <linux/i2c.h> 15 #include <linux/platform_device.h> 16 #include <linux/spi/spi.h> 17 #include <linux/acpi.h> 18 #include <linux/gpio.h> 19 #include <linux/of_gpio.h> 20 #include <linux/regulator/consumer.h> 21 #include <linux/mutex.h> 22 #include <sound/core.h> 23 #include <sound/pcm.h> 24 #include <sound/pcm_params.h> 25 #include <sound/jack.h> 26 #include <sound/soc.h> 27 #include <sound/soc-dapm.h> 28 #include <sound/initval.h> 29 #include <sound/tlv.h> 30 #include <sound/rt5668.h> 31 32 #include "rl6231.h" 33 #include "rt5668.h" 34 35 #define RT5668_NUM_SUPPLIES 3 36 37 static const char *rt5668_supply_names[RT5668_NUM_SUPPLIES] = { 38 "AVDD", 39 "MICVDD", 40 "VBAT", 41 }; 42 43 struct rt5668_priv { 44 struct snd_soc_component *component; 45 struct rt5668_platform_data pdata; 46 struct regmap *regmap; 47 struct snd_soc_jack *hs_jack; 48 struct regulator_bulk_data supplies[RT5668_NUM_SUPPLIES]; 49 struct delayed_work jack_detect_work; 50 struct delayed_work jd_check_work; 51 struct mutex calibrate_mutex; 52 53 int sysclk; 54 int sysclk_src; 55 int lrck[RT5668_AIFS]; 56 int bclk[RT5668_AIFS]; 57 int master[RT5668_AIFS]; 58 59 int pll_src; 60 int pll_in; 61 int pll_out; 62 63 int jack_type; 64 }; 65 66 static const struct reg_default rt5668_reg[] = { 67 {0x0002, 0x8080}, 68 {0x0003, 0x8000}, 69 {0x0005, 0x0000}, 70 {0x0006, 0x0000}, 71 {0x0008, 0x800f}, 72 {0x000b, 0x0000}, 73 {0x0010, 0x4040}, 74 {0x0011, 0x0000}, 75 {0x0012, 0x1404}, 76 {0x0013, 0x1000}, 77 {0x0014, 0xa00a}, 78 {0x0015, 0x0404}, 79 {0x0016, 0x0404}, 80 {0x0019, 0xafaf}, 81 {0x001c, 0x2f2f}, 82 {0x001f, 0x0000}, 83 {0x0022, 0x5757}, 84 {0x0023, 0x0039}, 85 {0x0024, 0x000b}, 86 {0x0026, 0xc0c4}, 87 {0x0029, 0x8080}, 88 {0x002a, 0xa0a0}, 89 {0x002b, 0x0300}, 90 {0x0030, 0x0000}, 91 {0x003c, 0x0080}, 92 {0x0044, 0x0c0c}, 93 {0x0049, 0x0000}, 94 {0x0061, 0x0000}, 95 {0x0062, 0x0000}, 96 {0x0063, 0x003f}, 97 {0x0064, 0x0000}, 98 {0x0065, 0x0000}, 99 {0x0066, 0x0030}, 100 {0x0067, 0x0000}, 101 {0x006b, 0x0000}, 102 {0x006c, 0x0000}, 103 {0x006d, 0x2200}, 104 {0x006e, 0x0a10}, 105 {0x0070, 0x8000}, 106 {0x0071, 0x8000}, 107 {0x0073, 0x0000}, 108 {0x0074, 0x0000}, 109 {0x0075, 0x0002}, 110 {0x0076, 0x0001}, 111 {0x0079, 0x0000}, 112 {0x007a, 0x0000}, 113 {0x007b, 0x0000}, 114 {0x007c, 0x0100}, 115 {0x007e, 0x0000}, 116 {0x0080, 0x0000}, 117 {0x0081, 0x0000}, 118 {0x0082, 0x0000}, 119 {0x0083, 0x0000}, 120 {0x0084, 0x0000}, 121 {0x0085, 0x0000}, 122 {0x0086, 0x0005}, 123 {0x0087, 0x0000}, 124 {0x0088, 0x0000}, 125 {0x008c, 0x0003}, 126 {0x008d, 0x0000}, 127 {0x008e, 0x0060}, 128 {0x008f, 0x1000}, 129 {0x0091, 0x0c26}, 130 {0x0092, 0x0073}, 131 {0x0093, 0x0000}, 132 {0x0094, 0x0080}, 133 {0x0098, 0x0000}, 134 {0x009a, 0x0000}, 135 {0x009b, 0x0000}, 136 {0x009c, 0x0000}, 137 {0x009d, 0x0000}, 138 {0x009e, 0x100c}, 139 {0x009f, 0x0000}, 140 {0x00a0, 0x0000}, 141 {0x00a3, 0x0002}, 142 {0x00a4, 0x0001}, 143 {0x00ae, 0x2040}, 144 {0x00af, 0x0000}, 145 {0x00b6, 0x0000}, 146 {0x00b7, 0x0000}, 147 {0x00b8, 0x0000}, 148 {0x00b9, 0x0002}, 149 {0x00be, 0x0000}, 150 {0x00c0, 0x0160}, 151 {0x00c1, 0x82a0}, 152 {0x00c2, 0x0000}, 153 {0x00d0, 0x0000}, 154 {0x00d1, 0x2244}, 155 {0x00d2, 0x3300}, 156 {0x00d3, 0x2200}, 157 {0x00d4, 0x0000}, 158 {0x00d9, 0x0009}, 159 {0x00da, 0x0000}, 160 {0x00db, 0x0000}, 161 {0x00dc, 0x00c0}, 162 {0x00dd, 0x2220}, 163 {0x00de, 0x3131}, 164 {0x00df, 0x3131}, 165 {0x00e0, 0x3131}, 166 {0x00e2, 0x0000}, 167 {0x00e3, 0x4000}, 168 {0x00e4, 0x0aa0}, 169 {0x00e5, 0x3131}, 170 {0x00e6, 0x3131}, 171 {0x00e7, 0x3131}, 172 {0x00e8, 0x3131}, 173 {0x00ea, 0xb320}, 174 {0x00eb, 0x0000}, 175 {0x00f0, 0x0000}, 176 {0x00f1, 0x00d0}, 177 {0x00f2, 0x00d0}, 178 {0x00f6, 0x0000}, 179 {0x00fa, 0x0000}, 180 {0x00fb, 0x0000}, 181 {0x00fc, 0x0000}, 182 {0x00fd, 0x0000}, 183 {0x00fe, 0x10ec}, 184 {0x00ff, 0x6530}, 185 {0x0100, 0xa0a0}, 186 {0x010b, 0x0000}, 187 {0x010c, 0xae00}, 188 {0x010d, 0xaaa0}, 189 {0x010e, 0x8aa2}, 190 {0x010f, 0x02a2}, 191 {0x0110, 0xc000}, 192 {0x0111, 0x04a2}, 193 {0x0112, 0x2800}, 194 {0x0113, 0x0000}, 195 {0x0117, 0x0100}, 196 {0x0125, 0x0410}, 197 {0x0132, 0x6026}, 198 {0x0136, 0x5555}, 199 {0x0138, 0x3700}, 200 {0x013a, 0x2000}, 201 {0x013b, 0x2000}, 202 {0x013c, 0x2005}, 203 {0x013f, 0x0000}, 204 {0x0142, 0x0000}, 205 {0x0145, 0x0002}, 206 {0x0146, 0x0000}, 207 {0x0147, 0x0000}, 208 {0x0148, 0x0000}, 209 {0x0149, 0x0000}, 210 {0x0150, 0x79a1}, 211 {0x0151, 0x0000}, 212 {0x0160, 0x4ec0}, 213 {0x0161, 0x0080}, 214 {0x0162, 0x0200}, 215 {0x0163, 0x0800}, 216 {0x0164, 0x0000}, 217 {0x0165, 0x0000}, 218 {0x0166, 0x0000}, 219 {0x0167, 0x000f}, 220 {0x0168, 0x000f}, 221 {0x0169, 0x0021}, 222 {0x0190, 0x413d}, 223 {0x0194, 0x0000}, 224 {0x0195, 0x0000}, 225 {0x0197, 0x0022}, 226 {0x0198, 0x0000}, 227 {0x0199, 0x0000}, 228 {0x01af, 0x0000}, 229 {0x01b0, 0x0400}, 230 {0x01b1, 0x0000}, 231 {0x01b2, 0x0000}, 232 {0x01b3, 0x0000}, 233 {0x01b4, 0x0000}, 234 {0x01b5, 0x0000}, 235 {0x01b6, 0x01c3}, 236 {0x01b7, 0x02a0}, 237 {0x01b8, 0x03e9}, 238 {0x01b9, 0x1389}, 239 {0x01ba, 0xc351}, 240 {0x01bb, 0x0009}, 241 {0x01bc, 0x0018}, 242 {0x01bd, 0x002a}, 243 {0x01be, 0x004c}, 244 {0x01bf, 0x0097}, 245 {0x01c0, 0x433d}, 246 {0x01c1, 0x2800}, 247 {0x01c2, 0x0000}, 248 {0x01c3, 0x0000}, 249 {0x01c4, 0x0000}, 250 {0x01c5, 0x0000}, 251 {0x01c6, 0x0000}, 252 {0x01c7, 0x0000}, 253 {0x01c8, 0x40af}, 254 {0x01c9, 0x0702}, 255 {0x01ca, 0x0000}, 256 {0x01cb, 0x0000}, 257 {0x01cc, 0x5757}, 258 {0x01cd, 0x5757}, 259 {0x01ce, 0x5757}, 260 {0x01cf, 0x5757}, 261 {0x01d0, 0x5757}, 262 {0x01d1, 0x5757}, 263 {0x01d2, 0x5757}, 264 {0x01d3, 0x5757}, 265 {0x01d4, 0x5757}, 266 {0x01d5, 0x5757}, 267 {0x01d6, 0x0000}, 268 {0x01d7, 0x0008}, 269 {0x01d8, 0x0029}, 270 {0x01d9, 0x3333}, 271 {0x01da, 0x0000}, 272 {0x01db, 0x0004}, 273 {0x01dc, 0x0000}, 274 {0x01de, 0x7c00}, 275 {0x01df, 0x0320}, 276 {0x01e0, 0x06a1}, 277 {0x01e1, 0x0000}, 278 {0x01e2, 0x0000}, 279 {0x01e3, 0x0000}, 280 {0x01e4, 0x0000}, 281 {0x01e6, 0x0001}, 282 {0x01e7, 0x0000}, 283 {0x01e8, 0x0000}, 284 {0x01ea, 0x0000}, 285 {0x01eb, 0x0000}, 286 {0x01ec, 0x0000}, 287 {0x01ed, 0x0000}, 288 {0x01ee, 0x0000}, 289 {0x01ef, 0x0000}, 290 {0x01f0, 0x0000}, 291 {0x01f1, 0x0000}, 292 {0x01f2, 0x0000}, 293 {0x01f3, 0x0000}, 294 {0x01f4, 0x0000}, 295 {0x0210, 0x6297}, 296 {0x0211, 0xa005}, 297 {0x0212, 0x824c}, 298 {0x0213, 0xf7ff}, 299 {0x0214, 0xf24c}, 300 {0x0215, 0x0102}, 301 {0x0216, 0x00a3}, 302 {0x0217, 0x0048}, 303 {0x0218, 0xa2c0}, 304 {0x0219, 0x0400}, 305 {0x021a, 0x00c8}, 306 {0x021b, 0x00c0}, 307 {0x021c, 0x0000}, 308 {0x0250, 0x4500}, 309 {0x0251, 0x40b3}, 310 {0x0252, 0x0000}, 311 {0x0253, 0x0000}, 312 {0x0254, 0x0000}, 313 {0x0255, 0x0000}, 314 {0x0256, 0x0000}, 315 {0x0257, 0x0000}, 316 {0x0258, 0x0000}, 317 {0x0259, 0x0000}, 318 {0x025a, 0x0005}, 319 {0x0270, 0x0000}, 320 {0x02ff, 0x0110}, 321 {0x0300, 0x001f}, 322 {0x0301, 0x032c}, 323 {0x0302, 0x5f21}, 324 {0x0303, 0x4000}, 325 {0x0304, 0x4000}, 326 {0x0305, 0x06d5}, 327 {0x0306, 0x8000}, 328 {0x0307, 0x0700}, 329 {0x0310, 0x4560}, 330 {0x0311, 0xa4a8}, 331 {0x0312, 0x7418}, 332 {0x0313, 0x0000}, 333 {0x0314, 0x0006}, 334 {0x0315, 0xffff}, 335 {0x0316, 0xc400}, 336 {0x0317, 0x0000}, 337 {0x03c0, 0x7e00}, 338 {0x03c1, 0x8000}, 339 {0x03c2, 0x8000}, 340 {0x03c3, 0x8000}, 341 {0x03c4, 0x8000}, 342 {0x03c5, 0x8000}, 343 {0x03c6, 0x8000}, 344 {0x03c7, 0x8000}, 345 {0x03c8, 0x8000}, 346 {0x03c9, 0x8000}, 347 {0x03ca, 0x8000}, 348 {0x03cb, 0x8000}, 349 {0x03cc, 0x8000}, 350 {0x03d0, 0x0000}, 351 {0x03d1, 0x0000}, 352 {0x03d2, 0x0000}, 353 {0x03d3, 0x0000}, 354 {0x03d4, 0x2000}, 355 {0x03d5, 0x2000}, 356 {0x03d6, 0x0000}, 357 {0x03d7, 0x0000}, 358 {0x03d8, 0x2000}, 359 {0x03d9, 0x2000}, 360 {0x03da, 0x2000}, 361 {0x03db, 0x2000}, 362 {0x03dc, 0x0000}, 363 {0x03dd, 0x0000}, 364 {0x03de, 0x0000}, 365 {0x03df, 0x2000}, 366 {0x03e0, 0x0000}, 367 {0x03e1, 0x0000}, 368 {0x03e2, 0x0000}, 369 {0x03e3, 0x0000}, 370 {0x03e4, 0x0000}, 371 {0x03e5, 0x0000}, 372 {0x03e6, 0x0000}, 373 {0x03e7, 0x0000}, 374 {0x03e8, 0x0000}, 375 {0x03e9, 0x0000}, 376 {0x03ea, 0x0000}, 377 {0x03eb, 0x0000}, 378 {0x03ec, 0x0000}, 379 {0x03ed, 0x0000}, 380 {0x03ee, 0x0000}, 381 {0x03ef, 0x0000}, 382 {0x03f0, 0x0800}, 383 {0x03f1, 0x0800}, 384 {0x03f2, 0x0800}, 385 {0x03f3, 0x0800}, 386 }; 387 388 static bool rt5668_volatile_register(struct device *dev, unsigned int reg) 389 { 390 switch (reg) { 391 case RT5668_RESET: 392 case RT5668_CBJ_CTRL_2: 393 case RT5668_INT_ST_1: 394 case RT5668_4BTN_IL_CMD_1: 395 case RT5668_AJD1_CTRL: 396 case RT5668_HP_CALIB_CTRL_1: 397 case RT5668_DEVICE_ID: 398 case RT5668_I2C_MODE: 399 case RT5668_HP_CALIB_CTRL_10: 400 case RT5668_EFUSE_CTRL_2: 401 case RT5668_JD_TOP_VC_VTRL: 402 case RT5668_HP_IMP_SENS_CTRL_19: 403 case RT5668_IL_CMD_1: 404 case RT5668_SAR_IL_CMD_2: 405 case RT5668_SAR_IL_CMD_4: 406 case RT5668_SAR_IL_CMD_10: 407 case RT5668_SAR_IL_CMD_11: 408 case RT5668_EFUSE_CTRL_6...RT5668_EFUSE_CTRL_11: 409 case RT5668_HP_CALIB_STA_1...RT5668_HP_CALIB_STA_11: 410 return true; 411 default: 412 return false; 413 } 414 } 415 416 static bool rt5668_readable_register(struct device *dev, unsigned int reg) 417 { 418 switch (reg) { 419 case RT5668_RESET: 420 case RT5668_VERSION_ID: 421 case RT5668_VENDOR_ID: 422 case RT5668_DEVICE_ID: 423 case RT5668_HP_CTRL_1: 424 case RT5668_HP_CTRL_2: 425 case RT5668_HPL_GAIN: 426 case RT5668_HPR_GAIN: 427 case RT5668_I2C_CTRL: 428 case RT5668_CBJ_BST_CTRL: 429 case RT5668_CBJ_CTRL_1: 430 case RT5668_CBJ_CTRL_2: 431 case RT5668_CBJ_CTRL_3: 432 case RT5668_CBJ_CTRL_4: 433 case RT5668_CBJ_CTRL_5: 434 case RT5668_CBJ_CTRL_6: 435 case RT5668_CBJ_CTRL_7: 436 case RT5668_DAC1_DIG_VOL: 437 case RT5668_STO1_ADC_DIG_VOL: 438 case RT5668_STO1_ADC_BOOST: 439 case RT5668_HP_IMP_GAIN_1: 440 case RT5668_HP_IMP_GAIN_2: 441 case RT5668_SIDETONE_CTRL: 442 case RT5668_STO1_ADC_MIXER: 443 case RT5668_AD_DA_MIXER: 444 case RT5668_STO1_DAC_MIXER: 445 case RT5668_A_DAC1_MUX: 446 case RT5668_DIG_INF2_DATA: 447 case RT5668_REC_MIXER: 448 case RT5668_CAL_REC: 449 case RT5668_ALC_BACK_GAIN: 450 case RT5668_PWR_DIG_1: 451 case RT5668_PWR_DIG_2: 452 case RT5668_PWR_ANLG_1: 453 case RT5668_PWR_ANLG_2: 454 case RT5668_PWR_ANLG_3: 455 case RT5668_PWR_MIXER: 456 case RT5668_PWR_VOL: 457 case RT5668_CLK_DET: 458 case RT5668_RESET_LPF_CTRL: 459 case RT5668_RESET_HPF_CTRL: 460 case RT5668_DMIC_CTRL_1: 461 case RT5668_I2S1_SDP: 462 case RT5668_I2S2_SDP: 463 case RT5668_ADDA_CLK_1: 464 case RT5668_ADDA_CLK_2: 465 case RT5668_I2S1_F_DIV_CTRL_1: 466 case RT5668_I2S1_F_DIV_CTRL_2: 467 case RT5668_TDM_CTRL: 468 case RT5668_TDM_ADDA_CTRL_1: 469 case RT5668_TDM_ADDA_CTRL_2: 470 case RT5668_DATA_SEL_CTRL_1: 471 case RT5668_TDM_TCON_CTRL: 472 case RT5668_GLB_CLK: 473 case RT5668_PLL_CTRL_1: 474 case RT5668_PLL_CTRL_2: 475 case RT5668_PLL_TRACK_1: 476 case RT5668_PLL_TRACK_2: 477 case RT5668_PLL_TRACK_3: 478 case RT5668_PLL_TRACK_4: 479 case RT5668_PLL_TRACK_5: 480 case RT5668_PLL_TRACK_6: 481 case RT5668_PLL_TRACK_11: 482 case RT5668_SDW_REF_CLK: 483 case RT5668_DEPOP_1: 484 case RT5668_DEPOP_2: 485 case RT5668_HP_CHARGE_PUMP_1: 486 case RT5668_HP_CHARGE_PUMP_2: 487 case RT5668_MICBIAS_1: 488 case RT5668_MICBIAS_2: 489 case RT5668_PLL_TRACK_12: 490 case RT5668_PLL_TRACK_14: 491 case RT5668_PLL2_CTRL_1: 492 case RT5668_PLL2_CTRL_2: 493 case RT5668_PLL2_CTRL_3: 494 case RT5668_PLL2_CTRL_4: 495 case RT5668_RC_CLK_CTRL: 496 case RT5668_I2S_M_CLK_CTRL_1: 497 case RT5668_I2S2_F_DIV_CTRL_1: 498 case RT5668_I2S2_F_DIV_CTRL_2: 499 case RT5668_EQ_CTRL_1: 500 case RT5668_EQ_CTRL_2: 501 case RT5668_IRQ_CTRL_1: 502 case RT5668_IRQ_CTRL_2: 503 case RT5668_IRQ_CTRL_3: 504 case RT5668_IRQ_CTRL_4: 505 case RT5668_INT_ST_1: 506 case RT5668_GPIO_CTRL_1: 507 case RT5668_GPIO_CTRL_2: 508 case RT5668_GPIO_CTRL_3: 509 case RT5668_HP_AMP_DET_CTRL_1: 510 case RT5668_HP_AMP_DET_CTRL_2: 511 case RT5668_MID_HP_AMP_DET: 512 case RT5668_LOW_HP_AMP_DET: 513 case RT5668_DELAY_BUF_CTRL: 514 case RT5668_SV_ZCD_1: 515 case RT5668_SV_ZCD_2: 516 case RT5668_IL_CMD_1: 517 case RT5668_IL_CMD_2: 518 case RT5668_IL_CMD_3: 519 case RT5668_IL_CMD_4: 520 case RT5668_IL_CMD_5: 521 case RT5668_IL_CMD_6: 522 case RT5668_4BTN_IL_CMD_1: 523 case RT5668_4BTN_IL_CMD_2: 524 case RT5668_4BTN_IL_CMD_3: 525 case RT5668_4BTN_IL_CMD_4: 526 case RT5668_4BTN_IL_CMD_5: 527 case RT5668_4BTN_IL_CMD_6: 528 case RT5668_4BTN_IL_CMD_7: 529 case RT5668_ADC_STO1_HP_CTRL_1: 530 case RT5668_ADC_STO1_HP_CTRL_2: 531 case RT5668_AJD1_CTRL: 532 case RT5668_JD1_THD: 533 case RT5668_JD2_THD: 534 case RT5668_JD_CTRL_1: 535 case RT5668_DUMMY_1: 536 case RT5668_DUMMY_2: 537 case RT5668_DUMMY_3: 538 case RT5668_DAC_ADC_DIG_VOL1: 539 case RT5668_BIAS_CUR_CTRL_2: 540 case RT5668_BIAS_CUR_CTRL_3: 541 case RT5668_BIAS_CUR_CTRL_4: 542 case RT5668_BIAS_CUR_CTRL_5: 543 case RT5668_BIAS_CUR_CTRL_6: 544 case RT5668_BIAS_CUR_CTRL_7: 545 case RT5668_BIAS_CUR_CTRL_8: 546 case RT5668_BIAS_CUR_CTRL_9: 547 case RT5668_BIAS_CUR_CTRL_10: 548 case RT5668_VREF_REC_OP_FB_CAP_CTRL: 549 case RT5668_CHARGE_PUMP_1: 550 case RT5668_DIG_IN_CTRL_1: 551 case RT5668_PAD_DRIVING_CTRL: 552 case RT5668_SOFT_RAMP_DEPOP: 553 case RT5668_CHOP_DAC: 554 case RT5668_CHOP_ADC: 555 case RT5668_CALIB_ADC_CTRL: 556 case RT5668_VOL_TEST: 557 case RT5668_SPKVDD_DET_STA: 558 case RT5668_TEST_MODE_CTRL_1: 559 case RT5668_TEST_MODE_CTRL_2: 560 case RT5668_TEST_MODE_CTRL_3: 561 case RT5668_TEST_MODE_CTRL_4: 562 case RT5668_TEST_MODE_CTRL_5: 563 case RT5668_PLL1_INTERNAL: 564 case RT5668_PLL2_INTERNAL: 565 case RT5668_STO_NG2_CTRL_1: 566 case RT5668_STO_NG2_CTRL_2: 567 case RT5668_STO_NG2_CTRL_3: 568 case RT5668_STO_NG2_CTRL_4: 569 case RT5668_STO_NG2_CTRL_5: 570 case RT5668_STO_NG2_CTRL_6: 571 case RT5668_STO_NG2_CTRL_7: 572 case RT5668_STO_NG2_CTRL_8: 573 case RT5668_STO_NG2_CTRL_9: 574 case RT5668_STO_NG2_CTRL_10: 575 case RT5668_STO1_DAC_SIL_DET: 576 case RT5668_SIL_PSV_CTRL1: 577 case RT5668_SIL_PSV_CTRL2: 578 case RT5668_SIL_PSV_CTRL3: 579 case RT5668_SIL_PSV_CTRL4: 580 case RT5668_SIL_PSV_CTRL5: 581 case RT5668_HP_IMP_SENS_CTRL_01: 582 case RT5668_HP_IMP_SENS_CTRL_02: 583 case RT5668_HP_IMP_SENS_CTRL_03: 584 case RT5668_HP_IMP_SENS_CTRL_04: 585 case RT5668_HP_IMP_SENS_CTRL_05: 586 case RT5668_HP_IMP_SENS_CTRL_06: 587 case RT5668_HP_IMP_SENS_CTRL_07: 588 case RT5668_HP_IMP_SENS_CTRL_08: 589 case RT5668_HP_IMP_SENS_CTRL_09: 590 case RT5668_HP_IMP_SENS_CTRL_10: 591 case RT5668_HP_IMP_SENS_CTRL_11: 592 case RT5668_HP_IMP_SENS_CTRL_12: 593 case RT5668_HP_IMP_SENS_CTRL_13: 594 case RT5668_HP_IMP_SENS_CTRL_14: 595 case RT5668_HP_IMP_SENS_CTRL_15: 596 case RT5668_HP_IMP_SENS_CTRL_16: 597 case RT5668_HP_IMP_SENS_CTRL_17: 598 case RT5668_HP_IMP_SENS_CTRL_18: 599 case RT5668_HP_IMP_SENS_CTRL_19: 600 case RT5668_HP_IMP_SENS_CTRL_20: 601 case RT5668_HP_IMP_SENS_CTRL_21: 602 case RT5668_HP_IMP_SENS_CTRL_22: 603 case RT5668_HP_IMP_SENS_CTRL_23: 604 case RT5668_HP_IMP_SENS_CTRL_24: 605 case RT5668_HP_IMP_SENS_CTRL_25: 606 case RT5668_HP_IMP_SENS_CTRL_26: 607 case RT5668_HP_IMP_SENS_CTRL_27: 608 case RT5668_HP_IMP_SENS_CTRL_28: 609 case RT5668_HP_IMP_SENS_CTRL_29: 610 case RT5668_HP_IMP_SENS_CTRL_30: 611 case RT5668_HP_IMP_SENS_CTRL_31: 612 case RT5668_HP_IMP_SENS_CTRL_32: 613 case RT5668_HP_IMP_SENS_CTRL_33: 614 case RT5668_HP_IMP_SENS_CTRL_34: 615 case RT5668_HP_IMP_SENS_CTRL_35: 616 case RT5668_HP_IMP_SENS_CTRL_36: 617 case RT5668_HP_IMP_SENS_CTRL_37: 618 case RT5668_HP_IMP_SENS_CTRL_38: 619 case RT5668_HP_IMP_SENS_CTRL_39: 620 case RT5668_HP_IMP_SENS_CTRL_40: 621 case RT5668_HP_IMP_SENS_CTRL_41: 622 case RT5668_HP_IMP_SENS_CTRL_42: 623 case RT5668_HP_IMP_SENS_CTRL_43: 624 case RT5668_HP_LOGIC_CTRL_1: 625 case RT5668_HP_LOGIC_CTRL_2: 626 case RT5668_HP_LOGIC_CTRL_3: 627 case RT5668_HP_CALIB_CTRL_1: 628 case RT5668_HP_CALIB_CTRL_2: 629 case RT5668_HP_CALIB_CTRL_3: 630 case RT5668_HP_CALIB_CTRL_4: 631 case RT5668_HP_CALIB_CTRL_5: 632 case RT5668_HP_CALIB_CTRL_6: 633 case RT5668_HP_CALIB_CTRL_7: 634 case RT5668_HP_CALIB_CTRL_9: 635 case RT5668_HP_CALIB_CTRL_10: 636 case RT5668_HP_CALIB_CTRL_11: 637 case RT5668_HP_CALIB_STA_1: 638 case RT5668_HP_CALIB_STA_2: 639 case RT5668_HP_CALIB_STA_3: 640 case RT5668_HP_CALIB_STA_4: 641 case RT5668_HP_CALIB_STA_5: 642 case RT5668_HP_CALIB_STA_6: 643 case RT5668_HP_CALIB_STA_7: 644 case RT5668_HP_CALIB_STA_8: 645 case RT5668_HP_CALIB_STA_9: 646 case RT5668_HP_CALIB_STA_10: 647 case RT5668_HP_CALIB_STA_11: 648 case RT5668_SAR_IL_CMD_1: 649 case RT5668_SAR_IL_CMD_2: 650 case RT5668_SAR_IL_CMD_3: 651 case RT5668_SAR_IL_CMD_4: 652 case RT5668_SAR_IL_CMD_5: 653 case RT5668_SAR_IL_CMD_6: 654 case RT5668_SAR_IL_CMD_7: 655 case RT5668_SAR_IL_CMD_8: 656 case RT5668_SAR_IL_CMD_9: 657 case RT5668_SAR_IL_CMD_10: 658 case RT5668_SAR_IL_CMD_11: 659 case RT5668_SAR_IL_CMD_12: 660 case RT5668_SAR_IL_CMD_13: 661 case RT5668_EFUSE_CTRL_1: 662 case RT5668_EFUSE_CTRL_2: 663 case RT5668_EFUSE_CTRL_3: 664 case RT5668_EFUSE_CTRL_4: 665 case RT5668_EFUSE_CTRL_5: 666 case RT5668_EFUSE_CTRL_6: 667 case RT5668_EFUSE_CTRL_7: 668 case RT5668_EFUSE_CTRL_8: 669 case RT5668_EFUSE_CTRL_9: 670 case RT5668_EFUSE_CTRL_10: 671 case RT5668_EFUSE_CTRL_11: 672 case RT5668_JD_TOP_VC_VTRL: 673 case RT5668_DRC1_CTRL_0: 674 case RT5668_DRC1_CTRL_1: 675 case RT5668_DRC1_CTRL_2: 676 case RT5668_DRC1_CTRL_3: 677 case RT5668_DRC1_CTRL_4: 678 case RT5668_DRC1_CTRL_5: 679 case RT5668_DRC1_CTRL_6: 680 case RT5668_DRC1_HARD_LMT_CTRL_1: 681 case RT5668_DRC1_HARD_LMT_CTRL_2: 682 case RT5668_DRC1_PRIV_1: 683 case RT5668_DRC1_PRIV_2: 684 case RT5668_DRC1_PRIV_3: 685 case RT5668_DRC1_PRIV_4: 686 case RT5668_DRC1_PRIV_5: 687 case RT5668_DRC1_PRIV_6: 688 case RT5668_DRC1_PRIV_7: 689 case RT5668_DRC1_PRIV_8: 690 case RT5668_EQ_AUTO_RCV_CTRL1: 691 case RT5668_EQ_AUTO_RCV_CTRL2: 692 case RT5668_EQ_AUTO_RCV_CTRL3: 693 case RT5668_EQ_AUTO_RCV_CTRL4: 694 case RT5668_EQ_AUTO_RCV_CTRL5: 695 case RT5668_EQ_AUTO_RCV_CTRL6: 696 case RT5668_EQ_AUTO_RCV_CTRL7: 697 case RT5668_EQ_AUTO_RCV_CTRL8: 698 case RT5668_EQ_AUTO_RCV_CTRL9: 699 case RT5668_EQ_AUTO_RCV_CTRL10: 700 case RT5668_EQ_AUTO_RCV_CTRL11: 701 case RT5668_EQ_AUTO_RCV_CTRL12: 702 case RT5668_EQ_AUTO_RCV_CTRL13: 703 case RT5668_ADC_L_EQ_LPF1_A1: 704 case RT5668_R_EQ_LPF1_A1: 705 case RT5668_L_EQ_LPF1_H0: 706 case RT5668_R_EQ_LPF1_H0: 707 case RT5668_L_EQ_BPF1_A1: 708 case RT5668_R_EQ_BPF1_A1: 709 case RT5668_L_EQ_BPF1_A2: 710 case RT5668_R_EQ_BPF1_A2: 711 case RT5668_L_EQ_BPF1_H0: 712 case RT5668_R_EQ_BPF1_H0: 713 case RT5668_L_EQ_BPF2_A1: 714 case RT5668_R_EQ_BPF2_A1: 715 case RT5668_L_EQ_BPF2_A2: 716 case RT5668_R_EQ_BPF2_A2: 717 case RT5668_L_EQ_BPF2_H0: 718 case RT5668_R_EQ_BPF2_H0: 719 case RT5668_L_EQ_BPF3_A1: 720 case RT5668_R_EQ_BPF3_A1: 721 case RT5668_L_EQ_BPF3_A2: 722 case RT5668_R_EQ_BPF3_A2: 723 case RT5668_L_EQ_BPF3_H0: 724 case RT5668_R_EQ_BPF3_H0: 725 case RT5668_L_EQ_BPF4_A1: 726 case RT5668_R_EQ_BPF4_A1: 727 case RT5668_L_EQ_BPF4_A2: 728 case RT5668_R_EQ_BPF4_A2: 729 case RT5668_L_EQ_BPF4_H0: 730 case RT5668_R_EQ_BPF4_H0: 731 case RT5668_L_EQ_HPF1_A1: 732 case RT5668_R_EQ_HPF1_A1: 733 case RT5668_L_EQ_HPF1_H0: 734 case RT5668_R_EQ_HPF1_H0: 735 case RT5668_L_EQ_PRE_VOL: 736 case RT5668_R_EQ_PRE_VOL: 737 case RT5668_L_EQ_POST_VOL: 738 case RT5668_R_EQ_POST_VOL: 739 case RT5668_I2C_MODE: 740 return true; 741 default: 742 return false; 743 } 744 } 745 746 static const DECLARE_TLV_DB_SCALE(hp_vol_tlv, -2250, 150, 0); 747 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -65625, 375, 0); 748 static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -17625, 375, 0); 749 static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0); 750 751 /* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */ 752 static const DECLARE_TLV_DB_RANGE(bst_tlv, 753 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0), 754 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0), 755 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0), 756 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0), 757 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0), 758 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0), 759 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0) 760 ); 761 762 /* Interface data select */ 763 static const char * const rt5668_data_select[] = { 764 "L/R", "R/L", "L/L", "R/R" 765 }; 766 767 static SOC_ENUM_SINGLE_DECL(rt5668_if2_adc_enum, 768 RT5668_DIG_INF2_DATA, RT5668_IF2_ADC_SEL_SFT, rt5668_data_select); 769 770 static SOC_ENUM_SINGLE_DECL(rt5668_if1_01_adc_enum, 771 RT5668_TDM_ADDA_CTRL_1, RT5668_IF1_ADC1_SEL_SFT, rt5668_data_select); 772 773 static SOC_ENUM_SINGLE_DECL(rt5668_if1_23_adc_enum, 774 RT5668_TDM_ADDA_CTRL_1, RT5668_IF1_ADC2_SEL_SFT, rt5668_data_select); 775 776 static SOC_ENUM_SINGLE_DECL(rt5668_if1_45_adc_enum, 777 RT5668_TDM_ADDA_CTRL_1, RT5668_IF1_ADC3_SEL_SFT, rt5668_data_select); 778 779 static SOC_ENUM_SINGLE_DECL(rt5668_if1_67_adc_enum, 780 RT5668_TDM_ADDA_CTRL_1, RT5668_IF1_ADC4_SEL_SFT, rt5668_data_select); 781 782 static const struct snd_kcontrol_new rt5668_if2_adc_swap_mux = 783 SOC_DAPM_ENUM("IF2 ADC Swap Mux", rt5668_if2_adc_enum); 784 785 static const struct snd_kcontrol_new rt5668_if1_01_adc_swap_mux = 786 SOC_DAPM_ENUM("IF1 01 ADC Swap Mux", rt5668_if1_01_adc_enum); 787 788 static const struct snd_kcontrol_new rt5668_if1_23_adc_swap_mux = 789 SOC_DAPM_ENUM("IF1 23 ADC Swap Mux", rt5668_if1_23_adc_enum); 790 791 static const struct snd_kcontrol_new rt5668_if1_45_adc_swap_mux = 792 SOC_DAPM_ENUM("IF1 45 ADC Swap Mux", rt5668_if1_45_adc_enum); 793 794 static const struct snd_kcontrol_new rt5668_if1_67_adc_swap_mux = 795 SOC_DAPM_ENUM("IF1 67 ADC Swap Mux", rt5668_if1_67_adc_enum); 796 797 static void rt5668_reset(struct regmap *regmap) 798 { 799 regmap_write(regmap, RT5668_RESET, 0); 800 regmap_write(regmap, RT5668_I2C_MODE, 1); 801 } 802 /** 803 * rt5668_sel_asrc_clk_src - select ASRC clock source for a set of filters 804 * @component: SoC audio component device. 805 * @filter_mask: mask of filters. 806 * @clk_src: clock source 807 * 808 * The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5668 can 809 * only support standard 32fs or 64fs i2s format, ASRC should be enabled to 810 * support special i2s clock format such as Intel's 100fs(100 * sampling rate). 811 * ASRC function will track i2s clock and generate a corresponding system clock 812 * for codec. This function provides an API to select the clock source for a 813 * set of filters specified by the mask. And the component driver will turn on 814 * ASRC for these filters if ASRC is selected as their clock source. 815 */ 816 int rt5668_sel_asrc_clk_src(struct snd_soc_component *component, 817 unsigned int filter_mask, unsigned int clk_src) 818 { 819 820 switch (clk_src) { 821 case RT5668_CLK_SEL_SYS: 822 case RT5668_CLK_SEL_I2S1_ASRC: 823 case RT5668_CLK_SEL_I2S2_ASRC: 824 break; 825 826 default: 827 return -EINVAL; 828 } 829 830 if (filter_mask & RT5668_DA_STEREO1_FILTER) { 831 snd_soc_component_update_bits(component, RT5668_PLL_TRACK_2, 832 RT5668_FILTER_CLK_SEL_MASK, 833 clk_src << RT5668_FILTER_CLK_SEL_SFT); 834 } 835 836 if (filter_mask & RT5668_AD_STEREO1_FILTER) { 837 snd_soc_component_update_bits(component, RT5668_PLL_TRACK_3, 838 RT5668_FILTER_CLK_SEL_MASK, 839 clk_src << RT5668_FILTER_CLK_SEL_SFT); 840 } 841 842 return 0; 843 } 844 EXPORT_SYMBOL_GPL(rt5668_sel_asrc_clk_src); 845 846 static int rt5668_button_detect(struct snd_soc_component *component) 847 { 848 int btn_type, val; 849 850 val = snd_soc_component_read(component, RT5668_4BTN_IL_CMD_1); 851 btn_type = val & 0xfff0; 852 snd_soc_component_write(component, RT5668_4BTN_IL_CMD_1, val); 853 pr_debug("%s btn_type=%x\n", __func__, btn_type); 854 855 return btn_type; 856 } 857 858 static void rt5668_enable_push_button_irq(struct snd_soc_component *component, 859 bool enable) 860 { 861 if (enable) { 862 snd_soc_component_update_bits(component, RT5668_SAR_IL_CMD_1, 863 RT5668_SAR_BUTT_DET_MASK, RT5668_SAR_BUTT_DET_EN); 864 snd_soc_component_update_bits(component, RT5668_SAR_IL_CMD_13, 865 RT5668_SAR_SOUR_MASK, RT5668_SAR_SOUR_BTN); 866 snd_soc_component_write(component, RT5668_IL_CMD_1, 0x0040); 867 snd_soc_component_update_bits(component, RT5668_4BTN_IL_CMD_2, 868 RT5668_4BTN_IL_MASK | RT5668_4BTN_IL_RST_MASK, 869 RT5668_4BTN_IL_EN | RT5668_4BTN_IL_NOR); 870 snd_soc_component_update_bits(component, RT5668_IRQ_CTRL_3, 871 RT5668_IL_IRQ_MASK, RT5668_IL_IRQ_EN); 872 } else { 873 snd_soc_component_update_bits(component, RT5668_IRQ_CTRL_3, 874 RT5668_IL_IRQ_MASK, RT5668_IL_IRQ_DIS); 875 snd_soc_component_update_bits(component, RT5668_SAR_IL_CMD_1, 876 RT5668_SAR_BUTT_DET_MASK, RT5668_SAR_BUTT_DET_DIS); 877 snd_soc_component_update_bits(component, RT5668_4BTN_IL_CMD_2, 878 RT5668_4BTN_IL_MASK, RT5668_4BTN_IL_DIS); 879 snd_soc_component_update_bits(component, RT5668_4BTN_IL_CMD_2, 880 RT5668_4BTN_IL_RST_MASK, RT5668_4BTN_IL_RST); 881 snd_soc_component_update_bits(component, RT5668_SAR_IL_CMD_13, 882 RT5668_SAR_SOUR_MASK, RT5668_SAR_SOUR_TYPE); 883 } 884 } 885 886 /** 887 * rt5668_headset_detect - Detect headset. 888 * @component: SoC audio component device. 889 * @jack_insert: Jack insert or not. 890 * 891 * Detect whether is headset or not when jack inserted. 892 * 893 * Returns detect status. 894 */ 895 static int rt5668_headset_detect(struct snd_soc_component *component, 896 int jack_insert) 897 { 898 struct rt5668_priv *rt5668 = snd_soc_component_get_drvdata(component); 899 struct snd_soc_dapm_context *dapm = 900 snd_soc_component_get_dapm(component); 901 unsigned int val, count; 902 903 if (jack_insert) { 904 snd_soc_dapm_force_enable_pin(dapm, "CBJ Power"); 905 snd_soc_dapm_sync(dapm); 906 snd_soc_component_update_bits(component, RT5668_CBJ_CTRL_1, 907 RT5668_TRIG_JD_MASK, RT5668_TRIG_JD_HIGH); 908 909 count = 0; 910 val = snd_soc_component_read(component, RT5668_CBJ_CTRL_2) 911 & RT5668_JACK_TYPE_MASK; 912 while (val == 0 && count < 50) { 913 usleep_range(10000, 15000); 914 val = snd_soc_component_read(component, 915 RT5668_CBJ_CTRL_2) & RT5668_JACK_TYPE_MASK; 916 count++; 917 } 918 919 switch (val) { 920 case 0x1: 921 case 0x2: 922 rt5668->jack_type = SND_JACK_HEADSET; 923 rt5668_enable_push_button_irq(component, true); 924 break; 925 default: 926 rt5668->jack_type = SND_JACK_HEADPHONE; 927 } 928 929 } else { 930 rt5668_enable_push_button_irq(component, false); 931 snd_soc_component_update_bits(component, RT5668_CBJ_CTRL_1, 932 RT5668_TRIG_JD_MASK, RT5668_TRIG_JD_LOW); 933 snd_soc_dapm_disable_pin(dapm, "CBJ Power"); 934 snd_soc_dapm_sync(dapm); 935 936 rt5668->jack_type = 0; 937 } 938 939 dev_dbg(component->dev, "jack_type = %d\n", rt5668->jack_type); 940 return rt5668->jack_type; 941 } 942 943 static irqreturn_t rt5668_irq(int irq, void *data) 944 { 945 struct rt5668_priv *rt5668 = data; 946 947 mod_delayed_work(system_power_efficient_wq, 948 &rt5668->jack_detect_work, msecs_to_jiffies(250)); 949 950 return IRQ_HANDLED; 951 } 952 953 static void rt5668_jd_check_handler(struct work_struct *work) 954 { 955 struct rt5668_priv *rt5668 = container_of(work, struct rt5668_priv, 956 jd_check_work.work); 957 958 if (snd_soc_component_read(rt5668->component, RT5668_AJD1_CTRL) 959 & RT5668_JDH_RS_MASK) { 960 /* jack out */ 961 rt5668->jack_type = rt5668_headset_detect(rt5668->component, 0); 962 963 snd_soc_jack_report(rt5668->hs_jack, rt5668->jack_type, 964 SND_JACK_HEADSET | 965 SND_JACK_BTN_0 | SND_JACK_BTN_1 | 966 SND_JACK_BTN_2 | SND_JACK_BTN_3); 967 } else { 968 schedule_delayed_work(&rt5668->jd_check_work, 500); 969 } 970 } 971 972 static int rt5668_set_jack_detect(struct snd_soc_component *component, 973 struct snd_soc_jack *hs_jack, void *data) 974 { 975 struct rt5668_priv *rt5668 = snd_soc_component_get_drvdata(component); 976 977 switch (rt5668->pdata.jd_src) { 978 case RT5668_JD1: 979 snd_soc_component_update_bits(component, RT5668_CBJ_CTRL_2, 980 RT5668_EXT_JD_SRC, RT5668_EXT_JD_SRC_MANUAL); 981 snd_soc_component_write(component, RT5668_CBJ_CTRL_1, 0xd002); 982 snd_soc_component_update_bits(component, RT5668_CBJ_CTRL_3, 983 RT5668_CBJ_IN_BUF_EN, RT5668_CBJ_IN_BUF_EN); 984 snd_soc_component_update_bits(component, RT5668_SAR_IL_CMD_1, 985 RT5668_SAR_POW_MASK, RT5668_SAR_POW_EN); 986 regmap_update_bits(rt5668->regmap, RT5668_GPIO_CTRL_1, 987 RT5668_GP1_PIN_MASK, RT5668_GP1_PIN_IRQ); 988 regmap_update_bits(rt5668->regmap, RT5668_RC_CLK_CTRL, 989 RT5668_POW_IRQ | RT5668_POW_JDH | 990 RT5668_POW_ANA, RT5668_POW_IRQ | 991 RT5668_POW_JDH | RT5668_POW_ANA); 992 regmap_update_bits(rt5668->regmap, RT5668_PWR_ANLG_2, 993 RT5668_PWR_JDH | RT5668_PWR_JDL, 994 RT5668_PWR_JDH | RT5668_PWR_JDL); 995 regmap_update_bits(rt5668->regmap, RT5668_IRQ_CTRL_2, 996 RT5668_JD1_EN_MASK | RT5668_JD1_POL_MASK, 997 RT5668_JD1_EN | RT5668_JD1_POL_NOR); 998 mod_delayed_work(system_power_efficient_wq, 999 &rt5668->jack_detect_work, msecs_to_jiffies(250)); 1000 break; 1001 1002 case RT5668_JD_NULL: 1003 regmap_update_bits(rt5668->regmap, RT5668_IRQ_CTRL_2, 1004 RT5668_JD1_EN_MASK, RT5668_JD1_DIS); 1005 regmap_update_bits(rt5668->regmap, RT5668_RC_CLK_CTRL, 1006 RT5668_POW_JDH | RT5668_POW_JDL, 0); 1007 break; 1008 1009 default: 1010 dev_warn(component->dev, "Wrong JD source\n"); 1011 break; 1012 } 1013 1014 rt5668->hs_jack = hs_jack; 1015 1016 return 0; 1017 } 1018 1019 static void rt5668_jack_detect_handler(struct work_struct *work) 1020 { 1021 struct rt5668_priv *rt5668 = 1022 container_of(work, struct rt5668_priv, jack_detect_work.work); 1023 int val, btn_type; 1024 1025 if (!rt5668->component || 1026 !snd_soc_card_is_instantiated(rt5668->component->card)) { 1027 /* card not yet ready, try later */ 1028 mod_delayed_work(system_power_efficient_wq, 1029 &rt5668->jack_detect_work, msecs_to_jiffies(15)); 1030 return; 1031 } 1032 1033 mutex_lock(&rt5668->calibrate_mutex); 1034 1035 val = snd_soc_component_read(rt5668->component, RT5668_AJD1_CTRL) 1036 & RT5668_JDH_RS_MASK; 1037 if (!val) { 1038 /* jack in */ 1039 if (rt5668->jack_type == 0) { 1040 /* jack was out, report jack type */ 1041 rt5668->jack_type = 1042 rt5668_headset_detect(rt5668->component, 1); 1043 } else { 1044 /* jack is already in, report button event */ 1045 rt5668->jack_type = SND_JACK_HEADSET; 1046 btn_type = rt5668_button_detect(rt5668->component); 1047 /** 1048 * rt5668 can report three kinds of button behavior, 1049 * one click, double click and hold. However, 1050 * currently we will report button pressed/released 1051 * event. So all the three button behaviors are 1052 * treated as button pressed. 1053 */ 1054 switch (btn_type) { 1055 case 0x8000: 1056 case 0x4000: 1057 case 0x2000: 1058 rt5668->jack_type |= SND_JACK_BTN_0; 1059 break; 1060 case 0x1000: 1061 case 0x0800: 1062 case 0x0400: 1063 rt5668->jack_type |= SND_JACK_BTN_1; 1064 break; 1065 case 0x0200: 1066 case 0x0100: 1067 case 0x0080: 1068 rt5668->jack_type |= SND_JACK_BTN_2; 1069 break; 1070 case 0x0040: 1071 case 0x0020: 1072 case 0x0010: 1073 rt5668->jack_type |= SND_JACK_BTN_3; 1074 break; 1075 case 0x0000: /* unpressed */ 1076 break; 1077 default: 1078 btn_type = 0; 1079 dev_err(rt5668->component->dev, 1080 "Unexpected button code 0x%04x\n", 1081 btn_type); 1082 break; 1083 } 1084 } 1085 } else { 1086 /* jack out */ 1087 rt5668->jack_type = rt5668_headset_detect(rt5668->component, 0); 1088 } 1089 1090 snd_soc_jack_report(rt5668->hs_jack, rt5668->jack_type, 1091 SND_JACK_HEADSET | 1092 SND_JACK_BTN_0 | SND_JACK_BTN_1 | 1093 SND_JACK_BTN_2 | SND_JACK_BTN_3); 1094 1095 if (rt5668->jack_type & (SND_JACK_BTN_0 | SND_JACK_BTN_1 | 1096 SND_JACK_BTN_2 | SND_JACK_BTN_3)) 1097 schedule_delayed_work(&rt5668->jd_check_work, 0); 1098 else 1099 cancel_delayed_work_sync(&rt5668->jd_check_work); 1100 1101 mutex_unlock(&rt5668->calibrate_mutex); 1102 } 1103 1104 static const struct snd_kcontrol_new rt5668_snd_controls[] = { 1105 /* Headphone Output Volume */ 1106 SOC_DOUBLE_R_TLV("Headphone Playback Volume", RT5668_HPL_GAIN, 1107 RT5668_HPR_GAIN, RT5668_G_HP_SFT, 15, 1, hp_vol_tlv), 1108 1109 /* DAC Digital Volume */ 1110 SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5668_DAC1_DIG_VOL, 1111 RT5668_L_VOL_SFT, RT5668_R_VOL_SFT, 175, 0, dac_vol_tlv), 1112 1113 /* IN Boost Volume */ 1114 SOC_SINGLE_TLV("CBJ Boost Volume", RT5668_CBJ_BST_CTRL, 1115 RT5668_BST_CBJ_SFT, 8, 0, bst_tlv), 1116 1117 /* ADC Digital Volume Control */ 1118 SOC_DOUBLE("STO1 ADC Capture Switch", RT5668_STO1_ADC_DIG_VOL, 1119 RT5668_L_MUTE_SFT, RT5668_R_MUTE_SFT, 1, 1), 1120 SOC_DOUBLE_TLV("STO1 ADC Capture Volume", RT5668_STO1_ADC_DIG_VOL, 1121 RT5668_L_VOL_SFT, RT5668_R_VOL_SFT, 127, 0, adc_vol_tlv), 1122 1123 /* ADC Boost Volume Control */ 1124 SOC_DOUBLE_TLV("STO1 ADC Boost Gain Volume", RT5668_STO1_ADC_BOOST, 1125 RT5668_STO1_ADC_L_BST_SFT, RT5668_STO1_ADC_R_BST_SFT, 1126 3, 0, adc_bst_tlv), 1127 }; 1128 1129 1130 static int rt5668_div_sel(struct rt5668_priv *rt5668, 1131 int target, const int div[], int size) 1132 { 1133 int i; 1134 1135 if (rt5668->sysclk < target) { 1136 pr_err("sysclk rate %d is too low\n", 1137 rt5668->sysclk); 1138 return 0; 1139 } 1140 1141 for (i = 0; i < size - 1; i++) { 1142 pr_info("div[%d]=%d\n", i, div[i]); 1143 if (target * div[i] == rt5668->sysclk) 1144 return i; 1145 if (target * div[i + 1] > rt5668->sysclk) { 1146 pr_err("can't find div for sysclk %d\n", 1147 rt5668->sysclk); 1148 return i; 1149 } 1150 } 1151 1152 if (target * div[i] < rt5668->sysclk) 1153 pr_err("sysclk rate %d is too high\n", 1154 rt5668->sysclk); 1155 1156 return size - 1; 1157 1158 } 1159 1160 /** 1161 * set_dmic_clk - Set parameter of dmic. 1162 * 1163 * @w: DAPM widget. 1164 * @kcontrol: The kcontrol of this widget. 1165 * @event: Event id. 1166 * 1167 * Choose dmic clock between 1MHz and 3MHz. 1168 * It is better for clock to approximate 3MHz. 1169 */ 1170 static int set_dmic_clk(struct snd_soc_dapm_widget *w, 1171 struct snd_kcontrol *kcontrol, int event) 1172 { 1173 struct snd_soc_component *component = 1174 snd_soc_dapm_to_component(w->dapm); 1175 struct rt5668_priv *rt5668 = snd_soc_component_get_drvdata(component); 1176 int idx; 1177 static const int div[] = {2, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, 128}; 1178 1179 idx = rt5668_div_sel(rt5668, 1500000, div, ARRAY_SIZE(div)); 1180 1181 snd_soc_component_update_bits(component, RT5668_DMIC_CTRL_1, 1182 RT5668_DMIC_CLK_MASK, idx << RT5668_DMIC_CLK_SFT); 1183 1184 return 0; 1185 } 1186 1187 static int set_filter_clk(struct snd_soc_dapm_widget *w, 1188 struct snd_kcontrol *kcontrol, int event) 1189 { 1190 struct snd_soc_component *component = 1191 snd_soc_dapm_to_component(w->dapm); 1192 struct rt5668_priv *rt5668 = snd_soc_component_get_drvdata(component); 1193 int ref, val, reg, idx; 1194 static const int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32, 48}; 1195 1196 val = snd_soc_component_read(component, RT5668_GPIO_CTRL_1) & 1197 RT5668_GP4_PIN_MASK; 1198 if (w->shift == RT5668_PWR_ADC_S1F_BIT && 1199 val == RT5668_GP4_PIN_ADCDAT2) 1200 ref = 256 * rt5668->lrck[RT5668_AIF2]; 1201 else 1202 ref = 256 * rt5668->lrck[RT5668_AIF1]; 1203 1204 idx = rt5668_div_sel(rt5668, ref, div, ARRAY_SIZE(div)); 1205 1206 if (w->shift == RT5668_PWR_ADC_S1F_BIT) 1207 reg = RT5668_PLL_TRACK_3; 1208 else 1209 reg = RT5668_PLL_TRACK_2; 1210 1211 snd_soc_component_update_bits(component, reg, 1212 RT5668_FILTER_CLK_SEL_MASK, idx << RT5668_FILTER_CLK_SEL_SFT); 1213 1214 return 0; 1215 } 1216 1217 static int is_sys_clk_from_pll1(struct snd_soc_dapm_widget *w, 1218 struct snd_soc_dapm_widget *sink) 1219 { 1220 unsigned int val; 1221 struct snd_soc_component *component = 1222 snd_soc_dapm_to_component(w->dapm); 1223 1224 val = snd_soc_component_read(component, RT5668_GLB_CLK); 1225 val &= RT5668_SCLK_SRC_MASK; 1226 if (val == RT5668_SCLK_SRC_PLL1) 1227 return 1; 1228 else 1229 return 0; 1230 } 1231 1232 static int is_using_asrc(struct snd_soc_dapm_widget *w, 1233 struct snd_soc_dapm_widget *sink) 1234 { 1235 unsigned int reg, shift, val; 1236 struct snd_soc_component *component = 1237 snd_soc_dapm_to_component(w->dapm); 1238 1239 switch (w->shift) { 1240 case RT5668_ADC_STO1_ASRC_SFT: 1241 reg = RT5668_PLL_TRACK_3; 1242 shift = RT5668_FILTER_CLK_SEL_SFT; 1243 break; 1244 case RT5668_DAC_STO1_ASRC_SFT: 1245 reg = RT5668_PLL_TRACK_2; 1246 shift = RT5668_FILTER_CLK_SEL_SFT; 1247 break; 1248 default: 1249 return 0; 1250 } 1251 1252 val = (snd_soc_component_read(component, reg) >> shift) & 0xf; 1253 switch (val) { 1254 case RT5668_CLK_SEL_I2S1_ASRC: 1255 case RT5668_CLK_SEL_I2S2_ASRC: 1256 return 1; 1257 default: 1258 return 0; 1259 } 1260 1261 } 1262 1263 /* Digital Mixer */ 1264 static const struct snd_kcontrol_new rt5668_sto1_adc_l_mix[] = { 1265 SOC_DAPM_SINGLE("ADC1 Switch", RT5668_STO1_ADC_MIXER, 1266 RT5668_M_STO1_ADC_L1_SFT, 1, 1), 1267 SOC_DAPM_SINGLE("ADC2 Switch", RT5668_STO1_ADC_MIXER, 1268 RT5668_M_STO1_ADC_L2_SFT, 1, 1), 1269 }; 1270 1271 static const struct snd_kcontrol_new rt5668_sto1_adc_r_mix[] = { 1272 SOC_DAPM_SINGLE("ADC1 Switch", RT5668_STO1_ADC_MIXER, 1273 RT5668_M_STO1_ADC_R1_SFT, 1, 1), 1274 SOC_DAPM_SINGLE("ADC2 Switch", RT5668_STO1_ADC_MIXER, 1275 RT5668_M_STO1_ADC_R2_SFT, 1, 1), 1276 }; 1277 1278 static const struct snd_kcontrol_new rt5668_dac_l_mix[] = { 1279 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5668_AD_DA_MIXER, 1280 RT5668_M_ADCMIX_L_SFT, 1, 1), 1281 SOC_DAPM_SINGLE("DAC1 Switch", RT5668_AD_DA_MIXER, 1282 RT5668_M_DAC1_L_SFT, 1, 1), 1283 }; 1284 1285 static const struct snd_kcontrol_new rt5668_dac_r_mix[] = { 1286 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5668_AD_DA_MIXER, 1287 RT5668_M_ADCMIX_R_SFT, 1, 1), 1288 SOC_DAPM_SINGLE("DAC1 Switch", RT5668_AD_DA_MIXER, 1289 RT5668_M_DAC1_R_SFT, 1, 1), 1290 }; 1291 1292 static const struct snd_kcontrol_new rt5668_sto1_dac_l_mix[] = { 1293 SOC_DAPM_SINGLE("DAC L1 Switch", RT5668_STO1_DAC_MIXER, 1294 RT5668_M_DAC_L1_STO_L_SFT, 1, 1), 1295 SOC_DAPM_SINGLE("DAC R1 Switch", RT5668_STO1_DAC_MIXER, 1296 RT5668_M_DAC_R1_STO_L_SFT, 1, 1), 1297 }; 1298 1299 static const struct snd_kcontrol_new rt5668_sto1_dac_r_mix[] = { 1300 SOC_DAPM_SINGLE("DAC L1 Switch", RT5668_STO1_DAC_MIXER, 1301 RT5668_M_DAC_L1_STO_R_SFT, 1, 1), 1302 SOC_DAPM_SINGLE("DAC R1 Switch", RT5668_STO1_DAC_MIXER, 1303 RT5668_M_DAC_R1_STO_R_SFT, 1, 1), 1304 }; 1305 1306 /* Analog Input Mixer */ 1307 static const struct snd_kcontrol_new rt5668_rec1_l_mix[] = { 1308 SOC_DAPM_SINGLE("CBJ Switch", RT5668_REC_MIXER, 1309 RT5668_M_CBJ_RM1_L_SFT, 1, 1), 1310 }; 1311 1312 /* STO1 ADC1 Source */ 1313 /* MX-26 [13] [5] */ 1314 static const char * const rt5668_sto1_adc1_src[] = { 1315 "DAC MIX", "ADC" 1316 }; 1317 1318 static SOC_ENUM_SINGLE_DECL( 1319 rt5668_sto1_adc1l_enum, RT5668_STO1_ADC_MIXER, 1320 RT5668_STO1_ADC1L_SRC_SFT, rt5668_sto1_adc1_src); 1321 1322 static const struct snd_kcontrol_new rt5668_sto1_adc1l_mux = 1323 SOC_DAPM_ENUM("Stereo1 ADC1L Source", rt5668_sto1_adc1l_enum); 1324 1325 static SOC_ENUM_SINGLE_DECL( 1326 rt5668_sto1_adc1r_enum, RT5668_STO1_ADC_MIXER, 1327 RT5668_STO1_ADC1R_SRC_SFT, rt5668_sto1_adc1_src); 1328 1329 static const struct snd_kcontrol_new rt5668_sto1_adc1r_mux = 1330 SOC_DAPM_ENUM("Stereo1 ADC1L Source", rt5668_sto1_adc1r_enum); 1331 1332 /* STO1 ADC Source */ 1333 /* MX-26 [11:10] [3:2] */ 1334 static const char * const rt5668_sto1_adc_src[] = { 1335 "ADC1 L", "ADC1 R" 1336 }; 1337 1338 static SOC_ENUM_SINGLE_DECL( 1339 rt5668_sto1_adcl_enum, RT5668_STO1_ADC_MIXER, 1340 RT5668_STO1_ADCL_SRC_SFT, rt5668_sto1_adc_src); 1341 1342 static const struct snd_kcontrol_new rt5668_sto1_adcl_mux = 1343 SOC_DAPM_ENUM("Stereo1 ADCL Source", rt5668_sto1_adcl_enum); 1344 1345 static SOC_ENUM_SINGLE_DECL( 1346 rt5668_sto1_adcr_enum, RT5668_STO1_ADC_MIXER, 1347 RT5668_STO1_ADCR_SRC_SFT, rt5668_sto1_adc_src); 1348 1349 static const struct snd_kcontrol_new rt5668_sto1_adcr_mux = 1350 SOC_DAPM_ENUM("Stereo1 ADCR Source", rt5668_sto1_adcr_enum); 1351 1352 /* STO1 ADC2 Source */ 1353 /* MX-26 [12] [4] */ 1354 static const char * const rt5668_sto1_adc2_src[] = { 1355 "DAC MIX", "DMIC" 1356 }; 1357 1358 static SOC_ENUM_SINGLE_DECL( 1359 rt5668_sto1_adc2l_enum, RT5668_STO1_ADC_MIXER, 1360 RT5668_STO1_ADC2L_SRC_SFT, rt5668_sto1_adc2_src); 1361 1362 static const struct snd_kcontrol_new rt5668_sto1_adc2l_mux = 1363 SOC_DAPM_ENUM("Stereo1 ADC2L Source", rt5668_sto1_adc2l_enum); 1364 1365 static SOC_ENUM_SINGLE_DECL( 1366 rt5668_sto1_adc2r_enum, RT5668_STO1_ADC_MIXER, 1367 RT5668_STO1_ADC2R_SRC_SFT, rt5668_sto1_adc2_src); 1368 1369 static const struct snd_kcontrol_new rt5668_sto1_adc2r_mux = 1370 SOC_DAPM_ENUM("Stereo1 ADC2R Source", rt5668_sto1_adc2r_enum); 1371 1372 /* MX-79 [6:4] I2S1 ADC data location */ 1373 static const unsigned int rt5668_if1_adc_slot_values[] = { 1374 0, 1375 2, 1376 4, 1377 6, 1378 }; 1379 1380 static const char * const rt5668_if1_adc_slot_src[] = { 1381 "Slot 0", "Slot 2", "Slot 4", "Slot 6" 1382 }; 1383 1384 static SOC_VALUE_ENUM_SINGLE_DECL(rt5668_if1_adc_slot_enum, 1385 RT5668_TDM_CTRL, RT5668_TDM_ADC_LCA_SFT, RT5668_TDM_ADC_LCA_MASK, 1386 rt5668_if1_adc_slot_src, rt5668_if1_adc_slot_values); 1387 1388 static const struct snd_kcontrol_new rt5668_if1_adc_slot_mux = 1389 SOC_DAPM_ENUM("IF1 ADC Slot location", rt5668_if1_adc_slot_enum); 1390 1391 /* Analog DAC L1 Source, Analog DAC R1 Source*/ 1392 /* MX-2B [4], MX-2B [0]*/ 1393 static const char * const rt5668_alg_dac1_src[] = { 1394 "Stereo1 DAC Mixer", "DAC1" 1395 }; 1396 1397 static SOC_ENUM_SINGLE_DECL( 1398 rt5668_alg_dac_l1_enum, RT5668_A_DAC1_MUX, 1399 RT5668_A_DACL1_SFT, rt5668_alg_dac1_src); 1400 1401 static const struct snd_kcontrol_new rt5668_alg_dac_l1_mux = 1402 SOC_DAPM_ENUM("Analog DAC L1 Source", rt5668_alg_dac_l1_enum); 1403 1404 static SOC_ENUM_SINGLE_DECL( 1405 rt5668_alg_dac_r1_enum, RT5668_A_DAC1_MUX, 1406 RT5668_A_DACR1_SFT, rt5668_alg_dac1_src); 1407 1408 static const struct snd_kcontrol_new rt5668_alg_dac_r1_mux = 1409 SOC_DAPM_ENUM("Analog DAC R1 Source", rt5668_alg_dac_r1_enum); 1410 1411 /* Out Switch */ 1412 static const struct snd_kcontrol_new hpol_switch = 1413 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5668_HP_CTRL_1, 1414 RT5668_L_MUTE_SFT, 1, 1); 1415 static const struct snd_kcontrol_new hpor_switch = 1416 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5668_HP_CTRL_1, 1417 RT5668_R_MUTE_SFT, 1, 1); 1418 1419 static int rt5668_hp_event(struct snd_soc_dapm_widget *w, 1420 struct snd_kcontrol *kcontrol, int event) 1421 { 1422 struct snd_soc_component *component = 1423 snd_soc_dapm_to_component(w->dapm); 1424 1425 switch (event) { 1426 case SND_SOC_DAPM_PRE_PMU: 1427 snd_soc_component_write(component, 1428 RT5668_HP_LOGIC_CTRL_2, 0x0012); 1429 snd_soc_component_write(component, 1430 RT5668_HP_CTRL_2, 0x6000); 1431 snd_soc_component_update_bits(component, RT5668_STO_NG2_CTRL_1, 1432 RT5668_NG2_EN_MASK, RT5668_NG2_EN); 1433 snd_soc_component_update_bits(component, 1434 RT5668_DEPOP_1, 0x60, 0x60); 1435 break; 1436 1437 case SND_SOC_DAPM_POST_PMD: 1438 snd_soc_component_update_bits(component, 1439 RT5668_DEPOP_1, 0x60, 0x0); 1440 snd_soc_component_write(component, 1441 RT5668_HP_CTRL_2, 0x0000); 1442 break; 1443 1444 default: 1445 return 0; 1446 } 1447 1448 return 0; 1449 1450 } 1451 1452 static int set_dmic_power(struct snd_soc_dapm_widget *w, 1453 struct snd_kcontrol *kcontrol, int event) 1454 { 1455 switch (event) { 1456 case SND_SOC_DAPM_POST_PMU: 1457 /*Add delay to avoid pop noise*/ 1458 msleep(150); 1459 break; 1460 1461 default: 1462 return 0; 1463 } 1464 1465 return 0; 1466 } 1467 1468 static int rt5655_set_verf(struct snd_soc_dapm_widget *w, 1469 struct snd_kcontrol *kcontrol, int event) 1470 { 1471 struct snd_soc_component *component = 1472 snd_soc_dapm_to_component(w->dapm); 1473 1474 switch (event) { 1475 case SND_SOC_DAPM_PRE_PMU: 1476 switch (w->shift) { 1477 case RT5668_PWR_VREF1_BIT: 1478 snd_soc_component_update_bits(component, 1479 RT5668_PWR_ANLG_1, RT5668_PWR_FV1, 0); 1480 break; 1481 1482 case RT5668_PWR_VREF2_BIT: 1483 snd_soc_component_update_bits(component, 1484 RT5668_PWR_ANLG_1, RT5668_PWR_FV2, 0); 1485 break; 1486 1487 default: 1488 break; 1489 } 1490 break; 1491 1492 case SND_SOC_DAPM_POST_PMU: 1493 usleep_range(15000, 20000); 1494 switch (w->shift) { 1495 case RT5668_PWR_VREF1_BIT: 1496 snd_soc_component_update_bits(component, 1497 RT5668_PWR_ANLG_1, RT5668_PWR_FV1, 1498 RT5668_PWR_FV1); 1499 break; 1500 1501 case RT5668_PWR_VREF2_BIT: 1502 snd_soc_component_update_bits(component, 1503 RT5668_PWR_ANLG_1, RT5668_PWR_FV2, 1504 RT5668_PWR_FV2); 1505 break; 1506 1507 default: 1508 break; 1509 } 1510 break; 1511 1512 default: 1513 return 0; 1514 } 1515 1516 return 0; 1517 } 1518 1519 static const unsigned int rt5668_adcdat_pin_values[] = { 1520 1, 1521 3, 1522 }; 1523 1524 static const char * const rt5668_adcdat_pin_select[] = { 1525 "ADCDAT1", 1526 "ADCDAT2", 1527 }; 1528 1529 static SOC_VALUE_ENUM_SINGLE_DECL(rt5668_adcdat_pin_enum, 1530 RT5668_GPIO_CTRL_1, RT5668_GP4_PIN_SFT, RT5668_GP4_PIN_MASK, 1531 rt5668_adcdat_pin_select, rt5668_adcdat_pin_values); 1532 1533 static const struct snd_kcontrol_new rt5668_adcdat_pin_ctrl = 1534 SOC_DAPM_ENUM("ADCDAT", rt5668_adcdat_pin_enum); 1535 1536 static const struct snd_soc_dapm_widget rt5668_dapm_widgets[] = { 1537 SND_SOC_DAPM_SUPPLY("LDO2", RT5668_PWR_ANLG_3, RT5668_PWR_LDO2_BIT, 1538 0, NULL, 0), 1539 SND_SOC_DAPM_SUPPLY("PLL1", RT5668_PWR_ANLG_3, RT5668_PWR_PLL_BIT, 1540 0, NULL, 0), 1541 SND_SOC_DAPM_SUPPLY("PLL2B", RT5668_PWR_ANLG_3, RT5668_PWR_PLL2B_BIT, 1542 0, NULL, 0), 1543 SND_SOC_DAPM_SUPPLY("PLL2F", RT5668_PWR_ANLG_3, RT5668_PWR_PLL2F_BIT, 1544 0, NULL, 0), 1545 SND_SOC_DAPM_SUPPLY("Vref1", RT5668_PWR_ANLG_1, RT5668_PWR_VREF1_BIT, 0, 1546 rt5655_set_verf, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), 1547 SND_SOC_DAPM_SUPPLY("Vref2", RT5668_PWR_ANLG_1, RT5668_PWR_VREF2_BIT, 0, 1548 rt5655_set_verf, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), 1549 1550 /* ASRC */ 1551 SND_SOC_DAPM_SUPPLY_S("DAC STO1 ASRC", 1, RT5668_PLL_TRACK_1, 1552 RT5668_DAC_STO1_ASRC_SFT, 0, NULL, 0), 1553 SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5668_PLL_TRACK_1, 1554 RT5668_ADC_STO1_ASRC_SFT, 0, NULL, 0), 1555 SND_SOC_DAPM_SUPPLY_S("AD ASRC", 1, RT5668_PLL_TRACK_1, 1556 RT5668_AD_ASRC_SFT, 0, NULL, 0), 1557 SND_SOC_DAPM_SUPPLY_S("DA ASRC", 1, RT5668_PLL_TRACK_1, 1558 RT5668_DA_ASRC_SFT, 0, NULL, 0), 1559 SND_SOC_DAPM_SUPPLY_S("DMIC ASRC", 1, RT5668_PLL_TRACK_1, 1560 RT5668_DMIC_ASRC_SFT, 0, NULL, 0), 1561 1562 /* Input Side */ 1563 SND_SOC_DAPM_SUPPLY("MICBIAS1", RT5668_PWR_ANLG_2, RT5668_PWR_MB1_BIT, 1564 0, NULL, 0), 1565 SND_SOC_DAPM_SUPPLY("MICBIAS2", RT5668_PWR_ANLG_2, RT5668_PWR_MB2_BIT, 1566 0, NULL, 0), 1567 1568 /* Input Lines */ 1569 SND_SOC_DAPM_INPUT("DMIC L1"), 1570 SND_SOC_DAPM_INPUT("DMIC R1"), 1571 1572 SND_SOC_DAPM_INPUT("IN1P"), 1573 1574 SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0, 1575 set_dmic_clk, SND_SOC_DAPM_PRE_PMU), 1576 SND_SOC_DAPM_SUPPLY("DMIC1 Power", RT5668_DMIC_CTRL_1, 1577 RT5668_DMIC_1_EN_SFT, 0, set_dmic_power, SND_SOC_DAPM_POST_PMU), 1578 1579 /* Boost */ 1580 SND_SOC_DAPM_PGA("BST1 CBJ", SND_SOC_NOPM, 1581 0, 0, NULL, 0), 1582 1583 SND_SOC_DAPM_SUPPLY("CBJ Power", RT5668_PWR_ANLG_3, 1584 RT5668_PWR_CBJ_BIT, 0, NULL, 0), 1585 1586 /* REC Mixer */ 1587 SND_SOC_DAPM_MIXER("RECMIX1L", SND_SOC_NOPM, 0, 0, rt5668_rec1_l_mix, 1588 ARRAY_SIZE(rt5668_rec1_l_mix)), 1589 SND_SOC_DAPM_SUPPLY("RECMIX1L Power", RT5668_PWR_ANLG_2, 1590 RT5668_PWR_RM1_L_BIT, 0, NULL, 0), 1591 1592 /* ADCs */ 1593 SND_SOC_DAPM_ADC("ADC1 L", NULL, SND_SOC_NOPM, 0, 0), 1594 SND_SOC_DAPM_ADC("ADC1 R", NULL, SND_SOC_NOPM, 0, 0), 1595 1596 SND_SOC_DAPM_SUPPLY("ADC1 L Power", RT5668_PWR_DIG_1, 1597 RT5668_PWR_ADC_L1_BIT, 0, NULL, 0), 1598 SND_SOC_DAPM_SUPPLY("ADC1 R Power", RT5668_PWR_DIG_1, 1599 RT5668_PWR_ADC_R1_BIT, 0, NULL, 0), 1600 SND_SOC_DAPM_SUPPLY("ADC1 clock", RT5668_CHOP_ADC, 1601 RT5668_CKGEN_ADC1_SFT, 0, NULL, 0), 1602 1603 /* ADC Mux */ 1604 SND_SOC_DAPM_MUX("Stereo1 ADC L1 Mux", SND_SOC_NOPM, 0, 0, 1605 &rt5668_sto1_adc1l_mux), 1606 SND_SOC_DAPM_MUX("Stereo1 ADC R1 Mux", SND_SOC_NOPM, 0, 0, 1607 &rt5668_sto1_adc1r_mux), 1608 SND_SOC_DAPM_MUX("Stereo1 ADC L2 Mux", SND_SOC_NOPM, 0, 0, 1609 &rt5668_sto1_adc2l_mux), 1610 SND_SOC_DAPM_MUX("Stereo1 ADC R2 Mux", SND_SOC_NOPM, 0, 0, 1611 &rt5668_sto1_adc2r_mux), 1612 SND_SOC_DAPM_MUX("Stereo1 ADC L Mux", SND_SOC_NOPM, 0, 0, 1613 &rt5668_sto1_adcl_mux), 1614 SND_SOC_DAPM_MUX("Stereo1 ADC R Mux", SND_SOC_NOPM, 0, 0, 1615 &rt5668_sto1_adcr_mux), 1616 SND_SOC_DAPM_MUX("IF1_ADC Mux", SND_SOC_NOPM, 0, 0, 1617 &rt5668_if1_adc_slot_mux), 1618 1619 /* ADC Mixer */ 1620 SND_SOC_DAPM_SUPPLY("ADC Stereo1 Filter", RT5668_PWR_DIG_2, 1621 RT5668_PWR_ADC_S1F_BIT, 0, set_filter_clk, 1622 SND_SOC_DAPM_PRE_PMU), 1623 SND_SOC_DAPM_MIXER("Stereo1 ADC MIXL", RT5668_STO1_ADC_DIG_VOL, 1624 RT5668_L_MUTE_SFT, 1, rt5668_sto1_adc_l_mix, 1625 ARRAY_SIZE(rt5668_sto1_adc_l_mix)), 1626 SND_SOC_DAPM_MIXER("Stereo1 ADC MIXR", RT5668_STO1_ADC_DIG_VOL, 1627 RT5668_R_MUTE_SFT, 1, rt5668_sto1_adc_r_mix, 1628 ARRAY_SIZE(rt5668_sto1_adc_r_mix)), 1629 1630 /* ADC PGA */ 1631 SND_SOC_DAPM_PGA("Stereo1 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 1632 1633 /* Digital Interface */ 1634 SND_SOC_DAPM_SUPPLY("I2S1", RT5668_PWR_DIG_1, RT5668_PWR_I2S1_BIT, 1635 0, NULL, 0), 1636 SND_SOC_DAPM_SUPPLY("I2S2", RT5668_PWR_DIG_1, RT5668_PWR_I2S2_BIT, 1637 0, NULL, 0), 1638 SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0), 1639 SND_SOC_DAPM_PGA("IF1 DAC1 L", SND_SOC_NOPM, 0, 0, NULL, 0), 1640 SND_SOC_DAPM_PGA("IF1 DAC1 R", SND_SOC_NOPM, 0, 0, NULL, 0), 1641 1642 /* Digital Interface Select */ 1643 SND_SOC_DAPM_MUX("IF1 01 ADC Swap Mux", SND_SOC_NOPM, 0, 0, 1644 &rt5668_if1_01_adc_swap_mux), 1645 SND_SOC_DAPM_MUX("IF1 23 ADC Swap Mux", SND_SOC_NOPM, 0, 0, 1646 &rt5668_if1_23_adc_swap_mux), 1647 SND_SOC_DAPM_MUX("IF1 45 ADC Swap Mux", SND_SOC_NOPM, 0, 0, 1648 &rt5668_if1_45_adc_swap_mux), 1649 SND_SOC_DAPM_MUX("IF1 67 ADC Swap Mux", SND_SOC_NOPM, 0, 0, 1650 &rt5668_if1_67_adc_swap_mux), 1651 SND_SOC_DAPM_MUX("IF2 ADC Swap Mux", SND_SOC_NOPM, 0, 0, 1652 &rt5668_if2_adc_swap_mux), 1653 1654 SND_SOC_DAPM_MUX("ADCDAT Mux", SND_SOC_NOPM, 0, 0, 1655 &rt5668_adcdat_pin_ctrl), 1656 1657 /* Audio Interface */ 1658 SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, 1659 RT5668_I2S1_SDP, RT5668_SEL_ADCDAT_SFT, 1), 1660 SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, 1661 RT5668_I2S2_SDP, RT5668_I2S2_PIN_CFG_SFT, 1), 1662 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0), 1663 1664 /* Output Side */ 1665 /* DAC mixer before sound effect */ 1666 SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0, 1667 rt5668_dac_l_mix, ARRAY_SIZE(rt5668_dac_l_mix)), 1668 SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0, 1669 rt5668_dac_r_mix, ARRAY_SIZE(rt5668_dac_r_mix)), 1670 1671 /* DAC channel Mux */ 1672 SND_SOC_DAPM_MUX("DAC L1 Source", SND_SOC_NOPM, 0, 0, 1673 &rt5668_alg_dac_l1_mux), 1674 SND_SOC_DAPM_MUX("DAC R1 Source", SND_SOC_NOPM, 0, 0, 1675 &rt5668_alg_dac_r1_mux), 1676 1677 /* DAC Mixer */ 1678 SND_SOC_DAPM_SUPPLY("DAC Stereo1 Filter", RT5668_PWR_DIG_2, 1679 RT5668_PWR_DAC_S1F_BIT, 0, set_filter_clk, 1680 SND_SOC_DAPM_PRE_PMU), 1681 SND_SOC_DAPM_MIXER("Stereo1 DAC MIXL", SND_SOC_NOPM, 0, 0, 1682 rt5668_sto1_dac_l_mix, ARRAY_SIZE(rt5668_sto1_dac_l_mix)), 1683 SND_SOC_DAPM_MIXER("Stereo1 DAC MIXR", SND_SOC_NOPM, 0, 0, 1684 rt5668_sto1_dac_r_mix, ARRAY_SIZE(rt5668_sto1_dac_r_mix)), 1685 1686 /* DACs */ 1687 SND_SOC_DAPM_DAC("DAC L1", NULL, RT5668_PWR_DIG_1, 1688 RT5668_PWR_DAC_L1_BIT, 0), 1689 SND_SOC_DAPM_DAC("DAC R1", NULL, RT5668_PWR_DIG_1, 1690 RT5668_PWR_DAC_R1_BIT, 0), 1691 SND_SOC_DAPM_SUPPLY_S("DAC 1 Clock", 3, RT5668_CHOP_DAC, 1692 RT5668_CKGEN_DAC1_SFT, 0, NULL, 0), 1693 1694 /* HPO */ 1695 SND_SOC_DAPM_PGA_S("HP Amp", 1, SND_SOC_NOPM, 0, 0, rt5668_hp_event, 1696 SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_PRE_PMU), 1697 1698 SND_SOC_DAPM_SUPPLY("HP Amp L", RT5668_PWR_ANLG_1, 1699 RT5668_PWR_HA_L_BIT, 0, NULL, 0), 1700 SND_SOC_DAPM_SUPPLY("HP Amp R", RT5668_PWR_ANLG_1, 1701 RT5668_PWR_HA_R_BIT, 0, NULL, 0), 1702 SND_SOC_DAPM_SUPPLY_S("Charge Pump", 1, RT5668_DEPOP_1, 1703 RT5668_PUMP_EN_SFT, 0, NULL, 0), 1704 SND_SOC_DAPM_SUPPLY_S("Capless", 2, RT5668_DEPOP_1, 1705 RT5668_CAPLESS_EN_SFT, 0, NULL, 0), 1706 1707 SND_SOC_DAPM_SWITCH("HPOL Playback", SND_SOC_NOPM, 0, 0, 1708 &hpol_switch), 1709 SND_SOC_DAPM_SWITCH("HPOR Playback", SND_SOC_NOPM, 0, 0, 1710 &hpor_switch), 1711 1712 /* CLK DET */ 1713 SND_SOC_DAPM_SUPPLY("CLKDET SYS", RT5668_CLK_DET, 1714 RT5668_SYS_CLK_DET_SFT, 0, NULL, 0), 1715 SND_SOC_DAPM_SUPPLY("CLKDET PLL1", RT5668_CLK_DET, 1716 RT5668_PLL1_CLK_DET_SFT, 0, NULL, 0), 1717 SND_SOC_DAPM_SUPPLY("CLKDET PLL2", RT5668_CLK_DET, 1718 RT5668_PLL2_CLK_DET_SFT, 0, NULL, 0), 1719 SND_SOC_DAPM_SUPPLY("CLKDET", RT5668_CLK_DET, 1720 RT5668_POW_CLK_DET_SFT, 0, NULL, 0), 1721 1722 /* Output Lines */ 1723 SND_SOC_DAPM_OUTPUT("HPOL"), 1724 SND_SOC_DAPM_OUTPUT("HPOR"), 1725 1726 }; 1727 1728 static const struct snd_soc_dapm_route rt5668_dapm_routes[] = { 1729 /*PLL*/ 1730 {"ADC Stereo1 Filter", NULL, "PLL1", is_sys_clk_from_pll1}, 1731 {"DAC Stereo1 Filter", NULL, "PLL1", is_sys_clk_from_pll1}, 1732 1733 /*ASRC*/ 1734 {"ADC Stereo1 Filter", NULL, "ADC STO1 ASRC", is_using_asrc}, 1735 {"DAC Stereo1 Filter", NULL, "DAC STO1 ASRC", is_using_asrc}, 1736 {"ADC STO1 ASRC", NULL, "AD ASRC"}, 1737 {"DAC STO1 ASRC", NULL, "DA ASRC"}, 1738 1739 /*Vref*/ 1740 {"MICBIAS1", NULL, "Vref1"}, 1741 {"MICBIAS1", NULL, "Vref2"}, 1742 {"MICBIAS2", NULL, "Vref1"}, 1743 {"MICBIAS2", NULL, "Vref2"}, 1744 1745 {"CLKDET SYS", NULL, "CLKDET"}, 1746 1747 {"IN1P", NULL, "LDO2"}, 1748 1749 {"BST1 CBJ", NULL, "IN1P"}, 1750 {"BST1 CBJ", NULL, "CBJ Power"}, 1751 {"CBJ Power", NULL, "Vref2"}, 1752 1753 {"RECMIX1L", "CBJ Switch", "BST1 CBJ"}, 1754 {"RECMIX1L", NULL, "RECMIX1L Power"}, 1755 1756 {"ADC1 L", NULL, "RECMIX1L"}, 1757 {"ADC1 L", NULL, "ADC1 L Power"}, 1758 {"ADC1 L", NULL, "ADC1 clock"}, 1759 1760 {"DMIC L1", NULL, "DMIC CLK"}, 1761 {"DMIC L1", NULL, "DMIC1 Power"}, 1762 {"DMIC R1", NULL, "DMIC CLK"}, 1763 {"DMIC R1", NULL, "DMIC1 Power"}, 1764 {"DMIC CLK", NULL, "DMIC ASRC"}, 1765 1766 {"Stereo1 ADC L Mux", "ADC1 L", "ADC1 L"}, 1767 {"Stereo1 ADC L Mux", "ADC1 R", "ADC1 R"}, 1768 {"Stereo1 ADC R Mux", "ADC1 L", "ADC1 L"}, 1769 {"Stereo1 ADC R Mux", "ADC1 R", "ADC1 R"}, 1770 1771 {"Stereo1 ADC L1 Mux", "ADC", "Stereo1 ADC L Mux"}, 1772 {"Stereo1 ADC L1 Mux", "DAC MIX", "Stereo1 DAC MIXL"}, 1773 {"Stereo1 ADC L2 Mux", "DMIC", "DMIC L1"}, 1774 {"Stereo1 ADC L2 Mux", "DAC MIX", "Stereo1 DAC MIXL"}, 1775 1776 {"Stereo1 ADC R1 Mux", "ADC", "Stereo1 ADC R Mux"}, 1777 {"Stereo1 ADC R1 Mux", "DAC MIX", "Stereo1 DAC MIXR"}, 1778 {"Stereo1 ADC R2 Mux", "DMIC", "DMIC R1"}, 1779 {"Stereo1 ADC R2 Mux", "DAC MIX", "Stereo1 DAC MIXR"}, 1780 1781 {"Stereo1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC L1 Mux"}, 1782 {"Stereo1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC L2 Mux"}, 1783 {"Stereo1 ADC MIXL", NULL, "ADC Stereo1 Filter"}, 1784 1785 {"Stereo1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC R1 Mux"}, 1786 {"Stereo1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC R2 Mux"}, 1787 {"Stereo1 ADC MIXR", NULL, "ADC Stereo1 Filter"}, 1788 1789 {"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXL"}, 1790 {"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXR"}, 1791 1792 {"IF1 01 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"}, 1793 {"IF1 01 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"}, 1794 {"IF1 01 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"}, 1795 {"IF1 01 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"}, 1796 {"IF1 23 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"}, 1797 {"IF1 23 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"}, 1798 {"IF1 23 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"}, 1799 {"IF1 23 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"}, 1800 {"IF1 45 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"}, 1801 {"IF1 45 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"}, 1802 {"IF1 45 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"}, 1803 {"IF1 45 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"}, 1804 {"IF1 67 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"}, 1805 {"IF1 67 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"}, 1806 {"IF1 67 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"}, 1807 {"IF1 67 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"}, 1808 1809 {"IF1_ADC Mux", "Slot 0", "IF1 01 ADC Swap Mux"}, 1810 {"IF1_ADC Mux", "Slot 2", "IF1 23 ADC Swap Mux"}, 1811 {"IF1_ADC Mux", "Slot 4", "IF1 45 ADC Swap Mux"}, 1812 {"IF1_ADC Mux", "Slot 6", "IF1 67 ADC Swap Mux"}, 1813 {"IF1_ADC Mux", NULL, "I2S1"}, 1814 {"ADCDAT Mux", "ADCDAT1", "IF1_ADC Mux"}, 1815 {"AIF1TX", NULL, "ADCDAT Mux"}, 1816 {"IF2 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"}, 1817 {"IF2 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"}, 1818 {"IF2 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"}, 1819 {"IF2 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"}, 1820 {"ADCDAT Mux", "ADCDAT2", "IF2 ADC Swap Mux"}, 1821 {"AIF2TX", NULL, "ADCDAT Mux"}, 1822 1823 {"IF1 DAC1 L", NULL, "AIF1RX"}, 1824 {"IF1 DAC1 L", NULL, "I2S1"}, 1825 {"IF1 DAC1 L", NULL, "DAC Stereo1 Filter"}, 1826 {"IF1 DAC1 R", NULL, "AIF1RX"}, 1827 {"IF1 DAC1 R", NULL, "I2S1"}, 1828 {"IF1 DAC1 R", NULL, "DAC Stereo1 Filter"}, 1829 1830 {"DAC1 MIXL", "Stereo ADC Switch", "Stereo1 ADC MIXL"}, 1831 {"DAC1 MIXL", "DAC1 Switch", "IF1 DAC1 L"}, 1832 {"DAC1 MIXR", "Stereo ADC Switch", "Stereo1 ADC MIXR"}, 1833 {"DAC1 MIXR", "DAC1 Switch", "IF1 DAC1 R"}, 1834 1835 {"Stereo1 DAC MIXL", "DAC L1 Switch", "DAC1 MIXL"}, 1836 {"Stereo1 DAC MIXL", "DAC R1 Switch", "DAC1 MIXR"}, 1837 1838 {"Stereo1 DAC MIXR", "DAC R1 Switch", "DAC1 MIXR"}, 1839 {"Stereo1 DAC MIXR", "DAC L1 Switch", "DAC1 MIXL"}, 1840 1841 {"DAC L1 Source", "DAC1", "DAC1 MIXL"}, 1842 {"DAC L1 Source", "Stereo1 DAC Mixer", "Stereo1 DAC MIXL"}, 1843 {"DAC R1 Source", "DAC1", "DAC1 MIXR"}, 1844 {"DAC R1 Source", "Stereo1 DAC Mixer", "Stereo1 DAC MIXR"}, 1845 1846 {"DAC L1", NULL, "DAC L1 Source"}, 1847 {"DAC R1", NULL, "DAC R1 Source"}, 1848 1849 {"DAC L1", NULL, "DAC 1 Clock"}, 1850 {"DAC R1", NULL, "DAC 1 Clock"}, 1851 1852 {"HP Amp", NULL, "DAC L1"}, 1853 {"HP Amp", NULL, "DAC R1"}, 1854 {"HP Amp", NULL, "HP Amp L"}, 1855 {"HP Amp", NULL, "HP Amp R"}, 1856 {"HP Amp", NULL, "Capless"}, 1857 {"HP Amp", NULL, "Charge Pump"}, 1858 {"HP Amp", NULL, "CLKDET SYS"}, 1859 {"HP Amp", NULL, "CBJ Power"}, 1860 {"HP Amp", NULL, "Vref2"}, 1861 {"HPOL Playback", "Switch", "HP Amp"}, 1862 {"HPOR Playback", "Switch", "HP Amp"}, 1863 {"HPOL", NULL, "HPOL Playback"}, 1864 {"HPOR", NULL, "HPOR Playback"}, 1865 }; 1866 1867 static int rt5668_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask, 1868 unsigned int rx_mask, int slots, int slot_width) 1869 { 1870 struct snd_soc_component *component = dai->component; 1871 unsigned int val = 0; 1872 1873 switch (slots) { 1874 case 4: 1875 val |= RT5668_TDM_TX_CH_4; 1876 val |= RT5668_TDM_RX_CH_4; 1877 break; 1878 case 6: 1879 val |= RT5668_TDM_TX_CH_6; 1880 val |= RT5668_TDM_RX_CH_6; 1881 break; 1882 case 8: 1883 val |= RT5668_TDM_TX_CH_8; 1884 val |= RT5668_TDM_RX_CH_8; 1885 break; 1886 case 2: 1887 break; 1888 default: 1889 return -EINVAL; 1890 } 1891 1892 snd_soc_component_update_bits(component, RT5668_TDM_CTRL, 1893 RT5668_TDM_TX_CH_MASK | RT5668_TDM_RX_CH_MASK, val); 1894 1895 switch (slot_width) { 1896 case 16: 1897 val = RT5668_TDM_CL_16; 1898 break; 1899 case 20: 1900 val = RT5668_TDM_CL_20; 1901 break; 1902 case 24: 1903 val = RT5668_TDM_CL_24; 1904 break; 1905 case 32: 1906 val = RT5668_TDM_CL_32; 1907 break; 1908 default: 1909 return -EINVAL; 1910 } 1911 1912 snd_soc_component_update_bits(component, RT5668_TDM_TCON_CTRL, 1913 RT5668_TDM_CL_MASK, val); 1914 1915 return 0; 1916 } 1917 1918 1919 static int rt5668_hw_params(struct snd_pcm_substream *substream, 1920 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) 1921 { 1922 struct snd_soc_component *component = dai->component; 1923 struct rt5668_priv *rt5668 = snd_soc_component_get_drvdata(component); 1924 unsigned int len_1 = 0, len_2 = 0; 1925 int pre_div, frame_size; 1926 1927 rt5668->lrck[dai->id] = params_rate(params); 1928 pre_div = rl6231_get_clk_info(rt5668->sysclk, rt5668->lrck[dai->id]); 1929 1930 frame_size = snd_soc_params_to_frame_size(params); 1931 if (frame_size < 0) { 1932 dev_err(component->dev, "Unsupported frame size: %d\n", 1933 frame_size); 1934 return -EINVAL; 1935 } 1936 1937 dev_dbg(dai->dev, "lrck is %dHz and pre_div is %d for iis %d\n", 1938 rt5668->lrck[dai->id], pre_div, dai->id); 1939 1940 switch (params_width(params)) { 1941 case 16: 1942 break; 1943 case 20: 1944 len_1 |= RT5668_I2S1_DL_20; 1945 len_2 |= RT5668_I2S2_DL_20; 1946 break; 1947 case 24: 1948 len_1 |= RT5668_I2S1_DL_24; 1949 len_2 |= RT5668_I2S2_DL_24; 1950 break; 1951 case 32: 1952 len_1 |= RT5668_I2S1_DL_32; 1953 len_2 |= RT5668_I2S2_DL_24; 1954 break; 1955 case 8: 1956 len_1 |= RT5668_I2S2_DL_8; 1957 len_2 |= RT5668_I2S2_DL_8; 1958 break; 1959 default: 1960 return -EINVAL; 1961 } 1962 1963 switch (dai->id) { 1964 case RT5668_AIF1: 1965 snd_soc_component_update_bits(component, RT5668_I2S1_SDP, 1966 RT5668_I2S1_DL_MASK, len_1); 1967 if (rt5668->master[RT5668_AIF1]) { 1968 snd_soc_component_update_bits(component, 1969 RT5668_ADDA_CLK_1, RT5668_I2S_M_DIV_MASK, 1970 pre_div << RT5668_I2S_M_DIV_SFT); 1971 } 1972 if (params_channels(params) == 1) /* mono mode */ 1973 snd_soc_component_update_bits(component, 1974 RT5668_I2S1_SDP, RT5668_I2S1_MONO_MASK, 1975 RT5668_I2S1_MONO_EN); 1976 else 1977 snd_soc_component_update_bits(component, 1978 RT5668_I2S1_SDP, RT5668_I2S1_MONO_MASK, 1979 RT5668_I2S1_MONO_DIS); 1980 break; 1981 case RT5668_AIF2: 1982 snd_soc_component_update_bits(component, RT5668_I2S2_SDP, 1983 RT5668_I2S2_DL_MASK, len_2); 1984 if (rt5668->master[RT5668_AIF2]) { 1985 snd_soc_component_update_bits(component, 1986 RT5668_I2S_M_CLK_CTRL_1, RT5668_I2S2_M_PD_MASK, 1987 pre_div << RT5668_I2S2_M_PD_SFT); 1988 } 1989 if (params_channels(params) == 1) /* mono mode */ 1990 snd_soc_component_update_bits(component, 1991 RT5668_I2S2_SDP, RT5668_I2S2_MONO_MASK, 1992 RT5668_I2S2_MONO_EN); 1993 else 1994 snd_soc_component_update_bits(component, 1995 RT5668_I2S2_SDP, RT5668_I2S2_MONO_MASK, 1996 RT5668_I2S2_MONO_DIS); 1997 break; 1998 default: 1999 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id); 2000 return -EINVAL; 2001 } 2002 2003 return 0; 2004 } 2005 2006 static int rt5668_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) 2007 { 2008 struct snd_soc_component *component = dai->component; 2009 struct rt5668_priv *rt5668 = snd_soc_component_get_drvdata(component); 2010 unsigned int reg_val = 0, tdm_ctrl = 0; 2011 2012 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 2013 case SND_SOC_DAIFMT_CBM_CFM: 2014 rt5668->master[dai->id] = 1; 2015 break; 2016 case SND_SOC_DAIFMT_CBS_CFS: 2017 rt5668->master[dai->id] = 0; 2018 break; 2019 default: 2020 return -EINVAL; 2021 } 2022 2023 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 2024 case SND_SOC_DAIFMT_NB_NF: 2025 break; 2026 case SND_SOC_DAIFMT_IB_NF: 2027 reg_val |= RT5668_I2S_BP_INV; 2028 tdm_ctrl |= RT5668_TDM_S_BP_INV; 2029 break; 2030 case SND_SOC_DAIFMT_NB_IF: 2031 if (dai->id == RT5668_AIF1) 2032 tdm_ctrl |= RT5668_TDM_S_LP_INV | RT5668_TDM_M_BP_INV; 2033 else 2034 return -EINVAL; 2035 break; 2036 case SND_SOC_DAIFMT_IB_IF: 2037 if (dai->id == RT5668_AIF1) 2038 tdm_ctrl |= RT5668_TDM_S_BP_INV | RT5668_TDM_S_LP_INV | 2039 RT5668_TDM_M_BP_INV | RT5668_TDM_M_LP_INV; 2040 else 2041 return -EINVAL; 2042 break; 2043 default: 2044 return -EINVAL; 2045 } 2046 2047 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 2048 case SND_SOC_DAIFMT_I2S: 2049 break; 2050 case SND_SOC_DAIFMT_LEFT_J: 2051 reg_val |= RT5668_I2S_DF_LEFT; 2052 tdm_ctrl |= RT5668_TDM_DF_LEFT; 2053 break; 2054 case SND_SOC_DAIFMT_DSP_A: 2055 reg_val |= RT5668_I2S_DF_PCM_A; 2056 tdm_ctrl |= RT5668_TDM_DF_PCM_A; 2057 break; 2058 case SND_SOC_DAIFMT_DSP_B: 2059 reg_val |= RT5668_I2S_DF_PCM_B; 2060 tdm_ctrl |= RT5668_TDM_DF_PCM_B; 2061 break; 2062 default: 2063 return -EINVAL; 2064 } 2065 2066 switch (dai->id) { 2067 case RT5668_AIF1: 2068 snd_soc_component_update_bits(component, RT5668_I2S1_SDP, 2069 RT5668_I2S_DF_MASK, reg_val); 2070 snd_soc_component_update_bits(component, RT5668_TDM_TCON_CTRL, 2071 RT5668_TDM_MS_MASK | RT5668_TDM_S_BP_MASK | 2072 RT5668_TDM_DF_MASK | RT5668_TDM_M_BP_MASK | 2073 RT5668_TDM_M_LP_MASK | RT5668_TDM_S_LP_MASK, 2074 tdm_ctrl | rt5668->master[dai->id]); 2075 break; 2076 case RT5668_AIF2: 2077 if (rt5668->master[dai->id] == 0) 2078 reg_val |= RT5668_I2S2_MS_S; 2079 snd_soc_component_update_bits(component, RT5668_I2S2_SDP, 2080 RT5668_I2S2_MS_MASK | RT5668_I2S_BP_MASK | 2081 RT5668_I2S_DF_MASK, reg_val); 2082 break; 2083 default: 2084 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id); 2085 return -EINVAL; 2086 } 2087 return 0; 2088 } 2089 2090 static int rt5668_set_component_sysclk(struct snd_soc_component *component, 2091 int clk_id, int source, unsigned int freq, int dir) 2092 { 2093 struct rt5668_priv *rt5668 = snd_soc_component_get_drvdata(component); 2094 unsigned int reg_val = 0, src = 0; 2095 2096 if (freq == rt5668->sysclk && clk_id == rt5668->sysclk_src) 2097 return 0; 2098 2099 switch (clk_id) { 2100 case RT5668_SCLK_S_MCLK: 2101 reg_val |= RT5668_SCLK_SRC_MCLK; 2102 src = RT5668_CLK_SRC_MCLK; 2103 break; 2104 case RT5668_SCLK_S_PLL1: 2105 reg_val |= RT5668_SCLK_SRC_PLL1; 2106 src = RT5668_CLK_SRC_PLL1; 2107 break; 2108 case RT5668_SCLK_S_PLL2: 2109 reg_val |= RT5668_SCLK_SRC_PLL2; 2110 src = RT5668_CLK_SRC_PLL2; 2111 break; 2112 case RT5668_SCLK_S_RCCLK: 2113 reg_val |= RT5668_SCLK_SRC_RCCLK; 2114 src = RT5668_CLK_SRC_RCCLK; 2115 break; 2116 default: 2117 dev_err(component->dev, "Invalid clock id (%d)\n", clk_id); 2118 return -EINVAL; 2119 } 2120 snd_soc_component_update_bits(component, RT5668_GLB_CLK, 2121 RT5668_SCLK_SRC_MASK, reg_val); 2122 2123 if (rt5668->master[RT5668_AIF2]) { 2124 snd_soc_component_update_bits(component, 2125 RT5668_I2S_M_CLK_CTRL_1, RT5668_I2S2_SRC_MASK, 2126 src << RT5668_I2S2_SRC_SFT); 2127 } 2128 2129 rt5668->sysclk = freq; 2130 rt5668->sysclk_src = clk_id; 2131 2132 dev_dbg(component->dev, "Sysclk is %dHz and clock id is %d\n", 2133 freq, clk_id); 2134 2135 return 0; 2136 } 2137 2138 static int rt5668_set_component_pll(struct snd_soc_component *component, 2139 int pll_id, int source, unsigned int freq_in, 2140 unsigned int freq_out) 2141 { 2142 struct rt5668_priv *rt5668 = snd_soc_component_get_drvdata(component); 2143 struct rl6231_pll_code pll_code; 2144 int ret; 2145 2146 if (source == rt5668->pll_src && freq_in == rt5668->pll_in && 2147 freq_out == rt5668->pll_out) 2148 return 0; 2149 2150 if (!freq_in || !freq_out) { 2151 dev_dbg(component->dev, "PLL disabled\n"); 2152 2153 rt5668->pll_in = 0; 2154 rt5668->pll_out = 0; 2155 snd_soc_component_update_bits(component, RT5668_GLB_CLK, 2156 RT5668_SCLK_SRC_MASK, RT5668_SCLK_SRC_MCLK); 2157 return 0; 2158 } 2159 2160 switch (source) { 2161 case RT5668_PLL1_S_MCLK: 2162 snd_soc_component_update_bits(component, RT5668_GLB_CLK, 2163 RT5668_PLL1_SRC_MASK, RT5668_PLL1_SRC_MCLK); 2164 break; 2165 case RT5668_PLL1_S_BCLK1: 2166 snd_soc_component_update_bits(component, RT5668_GLB_CLK, 2167 RT5668_PLL1_SRC_MASK, RT5668_PLL1_SRC_BCLK1); 2168 break; 2169 default: 2170 dev_err(component->dev, "Unknown PLL Source %d\n", source); 2171 return -EINVAL; 2172 } 2173 2174 ret = rl6231_pll_calc(freq_in, freq_out, &pll_code); 2175 if (ret < 0) { 2176 dev_err(component->dev, "Unsupported input clock %d\n", freq_in); 2177 return ret; 2178 } 2179 2180 dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n", 2181 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code), 2182 pll_code.n_code, pll_code.k_code); 2183 2184 snd_soc_component_write(component, RT5668_PLL_CTRL_1, 2185 pll_code.n_code << RT5668_PLL_N_SFT | pll_code.k_code); 2186 snd_soc_component_write(component, RT5668_PLL_CTRL_2, 2187 ((pll_code.m_bp ? 0 : pll_code.m_code) << RT5668_PLL_M_SFT) | 2188 (pll_code.m_bp << RT5668_PLL_M_BP_SFT)); 2189 2190 rt5668->pll_in = freq_in; 2191 rt5668->pll_out = freq_out; 2192 rt5668->pll_src = source; 2193 2194 return 0; 2195 } 2196 2197 static int rt5668_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio) 2198 { 2199 struct snd_soc_component *component = dai->component; 2200 struct rt5668_priv *rt5668 = snd_soc_component_get_drvdata(component); 2201 2202 rt5668->bclk[dai->id] = ratio; 2203 2204 switch (ratio) { 2205 case 64: 2206 snd_soc_component_update_bits(component, RT5668_ADDA_CLK_2, 2207 RT5668_I2S2_BCLK_MS2_MASK, 2208 RT5668_I2S2_BCLK_MS2_64); 2209 break; 2210 case 32: 2211 snd_soc_component_update_bits(component, RT5668_ADDA_CLK_2, 2212 RT5668_I2S2_BCLK_MS2_MASK, 2213 RT5668_I2S2_BCLK_MS2_32); 2214 break; 2215 default: 2216 dev_err(dai->dev, "Invalid bclk ratio %d\n", ratio); 2217 return -EINVAL; 2218 } 2219 2220 return 0; 2221 } 2222 2223 static int rt5668_set_bias_level(struct snd_soc_component *component, 2224 enum snd_soc_bias_level level) 2225 { 2226 struct rt5668_priv *rt5668 = snd_soc_component_get_drvdata(component); 2227 2228 switch (level) { 2229 case SND_SOC_BIAS_PREPARE: 2230 regmap_update_bits(rt5668->regmap, RT5668_PWR_ANLG_1, 2231 RT5668_PWR_MB | RT5668_PWR_BG, 2232 RT5668_PWR_MB | RT5668_PWR_BG); 2233 regmap_update_bits(rt5668->regmap, RT5668_PWR_DIG_1, 2234 RT5668_DIG_GATE_CTRL | RT5668_PWR_LDO, 2235 RT5668_DIG_GATE_CTRL | RT5668_PWR_LDO); 2236 break; 2237 2238 case SND_SOC_BIAS_STANDBY: 2239 regmap_update_bits(rt5668->regmap, RT5668_PWR_ANLG_1, 2240 RT5668_PWR_MB, RT5668_PWR_MB); 2241 regmap_update_bits(rt5668->regmap, RT5668_PWR_DIG_1, 2242 RT5668_DIG_GATE_CTRL, RT5668_DIG_GATE_CTRL); 2243 break; 2244 case SND_SOC_BIAS_OFF: 2245 regmap_update_bits(rt5668->regmap, RT5668_PWR_DIG_1, 2246 RT5668_DIG_GATE_CTRL | RT5668_PWR_LDO, 0); 2247 regmap_update_bits(rt5668->regmap, RT5668_PWR_ANLG_1, 2248 RT5668_PWR_MB | RT5668_PWR_BG, 0); 2249 break; 2250 2251 default: 2252 break; 2253 } 2254 2255 return 0; 2256 } 2257 2258 static int rt5668_probe(struct snd_soc_component *component) 2259 { 2260 struct rt5668_priv *rt5668 = snd_soc_component_get_drvdata(component); 2261 2262 rt5668->component = component; 2263 2264 return 0; 2265 } 2266 2267 static void rt5668_remove(struct snd_soc_component *component) 2268 { 2269 struct rt5668_priv *rt5668 = snd_soc_component_get_drvdata(component); 2270 2271 rt5668_reset(rt5668->regmap); 2272 } 2273 2274 #ifdef CONFIG_PM 2275 static int rt5668_suspend(struct snd_soc_component *component) 2276 { 2277 struct rt5668_priv *rt5668 = snd_soc_component_get_drvdata(component); 2278 2279 regcache_cache_only(rt5668->regmap, true); 2280 regcache_mark_dirty(rt5668->regmap); 2281 return 0; 2282 } 2283 2284 static int rt5668_resume(struct snd_soc_component *component) 2285 { 2286 struct rt5668_priv *rt5668 = snd_soc_component_get_drvdata(component); 2287 2288 regcache_cache_only(rt5668->regmap, false); 2289 regcache_sync(rt5668->regmap); 2290 2291 return 0; 2292 } 2293 #else 2294 #define rt5668_suspend NULL 2295 #define rt5668_resume NULL 2296 #endif 2297 2298 #define RT5668_STEREO_RATES SNDRV_PCM_RATE_8000_192000 2299 #define RT5668_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ 2300 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8) 2301 2302 static const struct snd_soc_dai_ops rt5668_aif1_dai_ops = { 2303 .hw_params = rt5668_hw_params, 2304 .set_fmt = rt5668_set_dai_fmt, 2305 .set_tdm_slot = rt5668_set_tdm_slot, 2306 }; 2307 2308 static const struct snd_soc_dai_ops rt5668_aif2_dai_ops = { 2309 .hw_params = rt5668_hw_params, 2310 .set_fmt = rt5668_set_dai_fmt, 2311 .set_bclk_ratio = rt5668_set_bclk_ratio, 2312 }; 2313 2314 static struct snd_soc_dai_driver rt5668_dai[] = { 2315 { 2316 .name = "rt5668-aif1", 2317 .id = RT5668_AIF1, 2318 .playback = { 2319 .stream_name = "AIF1 Playback", 2320 .channels_min = 1, 2321 .channels_max = 2, 2322 .rates = RT5668_STEREO_RATES, 2323 .formats = RT5668_FORMATS, 2324 }, 2325 .capture = { 2326 .stream_name = "AIF1 Capture", 2327 .channels_min = 1, 2328 .channels_max = 2, 2329 .rates = RT5668_STEREO_RATES, 2330 .formats = RT5668_FORMATS, 2331 }, 2332 .ops = &rt5668_aif1_dai_ops, 2333 }, 2334 { 2335 .name = "rt5668-aif2", 2336 .id = RT5668_AIF2, 2337 .capture = { 2338 .stream_name = "AIF2 Capture", 2339 .channels_min = 1, 2340 .channels_max = 2, 2341 .rates = RT5668_STEREO_RATES, 2342 .formats = RT5668_FORMATS, 2343 }, 2344 .ops = &rt5668_aif2_dai_ops, 2345 }, 2346 }; 2347 2348 static const struct snd_soc_component_driver soc_component_dev_rt5668 = { 2349 .probe = rt5668_probe, 2350 .remove = rt5668_remove, 2351 .suspend = rt5668_suspend, 2352 .resume = rt5668_resume, 2353 .set_bias_level = rt5668_set_bias_level, 2354 .controls = rt5668_snd_controls, 2355 .num_controls = ARRAY_SIZE(rt5668_snd_controls), 2356 .dapm_widgets = rt5668_dapm_widgets, 2357 .num_dapm_widgets = ARRAY_SIZE(rt5668_dapm_widgets), 2358 .dapm_routes = rt5668_dapm_routes, 2359 .num_dapm_routes = ARRAY_SIZE(rt5668_dapm_routes), 2360 .set_sysclk = rt5668_set_component_sysclk, 2361 .set_pll = rt5668_set_component_pll, 2362 .set_jack = rt5668_set_jack_detect, 2363 .use_pmdown_time = 1, 2364 .endianness = 1, 2365 }; 2366 2367 static const struct regmap_config rt5668_regmap = { 2368 .reg_bits = 16, 2369 .val_bits = 16, 2370 .max_register = RT5668_I2C_MODE, 2371 .volatile_reg = rt5668_volatile_register, 2372 .readable_reg = rt5668_readable_register, 2373 .cache_type = REGCACHE_RBTREE, 2374 .reg_defaults = rt5668_reg, 2375 .num_reg_defaults = ARRAY_SIZE(rt5668_reg), 2376 .use_single_read = true, 2377 .use_single_write = true, 2378 }; 2379 2380 static const struct i2c_device_id rt5668_i2c_id[] = { 2381 {"rt5668b", 0}, 2382 {} 2383 }; 2384 MODULE_DEVICE_TABLE(i2c, rt5668_i2c_id); 2385 2386 static int rt5668_parse_dt(struct rt5668_priv *rt5668, struct device *dev) 2387 { 2388 2389 of_property_read_u32(dev->of_node, "realtek,dmic1-data-pin", 2390 &rt5668->pdata.dmic1_data_pin); 2391 of_property_read_u32(dev->of_node, "realtek,dmic1-clk-pin", 2392 &rt5668->pdata.dmic1_clk_pin); 2393 of_property_read_u32(dev->of_node, "realtek,jd-src", 2394 &rt5668->pdata.jd_src); 2395 2396 rt5668->pdata.ldo1_en = of_get_named_gpio(dev->of_node, 2397 "realtek,ldo1-en-gpios", 0); 2398 2399 return 0; 2400 } 2401 2402 static void rt5668_calibrate(struct rt5668_priv *rt5668) 2403 { 2404 int value, count; 2405 2406 mutex_lock(&rt5668->calibrate_mutex); 2407 2408 rt5668_reset(rt5668->regmap); 2409 regmap_write(rt5668->regmap, RT5668_PWR_ANLG_1, 0xa2bf); 2410 usleep_range(15000, 20000); 2411 regmap_write(rt5668->regmap, RT5668_PWR_ANLG_1, 0xf2bf); 2412 regmap_write(rt5668->regmap, RT5668_MICBIAS_2, 0x0380); 2413 regmap_write(rt5668->regmap, RT5668_PWR_DIG_1, 0x8001); 2414 regmap_write(rt5668->regmap, RT5668_TEST_MODE_CTRL_1, 0x0000); 2415 regmap_write(rt5668->regmap, RT5668_STO1_DAC_MIXER, 0x2080); 2416 regmap_write(rt5668->regmap, RT5668_STO1_ADC_MIXER, 0x4040); 2417 regmap_write(rt5668->regmap, RT5668_DEPOP_1, 0x0069); 2418 regmap_write(rt5668->regmap, RT5668_CHOP_DAC, 0x3000); 2419 regmap_write(rt5668->regmap, RT5668_HP_CTRL_2, 0x6000); 2420 regmap_write(rt5668->regmap, RT5668_HP_CHARGE_PUMP_1, 0x0f26); 2421 regmap_write(rt5668->regmap, RT5668_CALIB_ADC_CTRL, 0x7f05); 2422 regmap_write(rt5668->regmap, RT5668_STO1_ADC_MIXER, 0x686c); 2423 regmap_write(rt5668->regmap, RT5668_CAL_REC, 0x0d0d); 2424 regmap_write(rt5668->regmap, RT5668_HP_CALIB_CTRL_9, 0x000f); 2425 regmap_write(rt5668->regmap, RT5668_PWR_DIG_1, 0x8d01); 2426 regmap_write(rt5668->regmap, RT5668_HP_CALIB_CTRL_2, 0x0321); 2427 regmap_write(rt5668->regmap, RT5668_HP_LOGIC_CTRL_2, 0x0004); 2428 regmap_write(rt5668->regmap, RT5668_HP_CALIB_CTRL_1, 0x7c00); 2429 regmap_write(rt5668->regmap, RT5668_HP_CALIB_CTRL_3, 0x06a1); 2430 regmap_write(rt5668->regmap, RT5668_A_DAC1_MUX, 0x0311); 2431 regmap_write(rt5668->regmap, RT5668_RESET_HPF_CTRL, 0x0000); 2432 regmap_write(rt5668->regmap, RT5668_ADC_STO1_HP_CTRL_1, 0x3320); 2433 2434 regmap_write(rt5668->regmap, RT5668_HP_CALIB_CTRL_1, 0xfc00); 2435 2436 for (count = 0; count < 60; count++) { 2437 regmap_read(rt5668->regmap, RT5668_HP_CALIB_STA_1, &value); 2438 if (!(value & 0x8000)) 2439 break; 2440 2441 usleep_range(10000, 10005); 2442 } 2443 2444 if (count >= 60) 2445 pr_err("HP Calibration Failure\n"); 2446 2447 /* restore settings */ 2448 regmap_write(rt5668->regmap, RT5668_STO1_ADC_MIXER, 0xc0c4); 2449 regmap_write(rt5668->regmap, RT5668_PWR_DIG_1, 0x0000); 2450 2451 mutex_unlock(&rt5668->calibrate_mutex); 2452 2453 } 2454 2455 static int rt5668_i2c_probe(struct i2c_client *i2c) 2456 { 2457 struct rt5668_platform_data *pdata = dev_get_platdata(&i2c->dev); 2458 struct rt5668_priv *rt5668; 2459 int i, ret; 2460 unsigned int val; 2461 2462 rt5668 = devm_kzalloc(&i2c->dev, sizeof(struct rt5668_priv), 2463 GFP_KERNEL); 2464 2465 if (rt5668 == NULL) 2466 return -ENOMEM; 2467 2468 i2c_set_clientdata(i2c, rt5668); 2469 2470 if (pdata) 2471 rt5668->pdata = *pdata; 2472 else 2473 rt5668_parse_dt(rt5668, &i2c->dev); 2474 2475 rt5668->regmap = devm_regmap_init_i2c(i2c, &rt5668_regmap); 2476 if (IS_ERR(rt5668->regmap)) { 2477 ret = PTR_ERR(rt5668->regmap); 2478 dev_err(&i2c->dev, "Failed to allocate register map: %d\n", 2479 ret); 2480 return ret; 2481 } 2482 2483 for (i = 0; i < ARRAY_SIZE(rt5668->supplies); i++) 2484 rt5668->supplies[i].supply = rt5668_supply_names[i]; 2485 2486 ret = devm_regulator_bulk_get(&i2c->dev, ARRAY_SIZE(rt5668->supplies), 2487 rt5668->supplies); 2488 if (ret != 0) { 2489 dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret); 2490 return ret; 2491 } 2492 2493 ret = regulator_bulk_enable(ARRAY_SIZE(rt5668->supplies), 2494 rt5668->supplies); 2495 if (ret != 0) { 2496 dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret); 2497 return ret; 2498 } 2499 2500 if (gpio_is_valid(rt5668->pdata.ldo1_en)) { 2501 if (devm_gpio_request_one(&i2c->dev, rt5668->pdata.ldo1_en, 2502 GPIOF_OUT_INIT_HIGH, "rt5668")) 2503 dev_err(&i2c->dev, "Fail gpio_request gpio_ldo\n"); 2504 } 2505 2506 /* Sleep for 300 ms miniumum */ 2507 usleep_range(300000, 350000); 2508 2509 regmap_write(rt5668->regmap, RT5668_I2C_MODE, 0x1); 2510 usleep_range(10000, 15000); 2511 2512 regmap_read(rt5668->regmap, RT5668_DEVICE_ID, &val); 2513 if (val != DEVICE_ID) { 2514 pr_err("Device with ID register %x is not rt5668\n", val); 2515 return -ENODEV; 2516 } 2517 2518 rt5668_reset(rt5668->regmap); 2519 2520 rt5668_calibrate(rt5668); 2521 2522 regmap_write(rt5668->regmap, RT5668_DEPOP_1, 0x0000); 2523 2524 /* DMIC pin*/ 2525 if (rt5668->pdata.dmic1_data_pin != RT5668_DMIC1_NULL) { 2526 switch (rt5668->pdata.dmic1_data_pin) { 2527 case RT5668_DMIC1_DATA_GPIO2: /* share with LRCK2 */ 2528 regmap_update_bits(rt5668->regmap, RT5668_DMIC_CTRL_1, 2529 RT5668_DMIC_1_DP_MASK, RT5668_DMIC_1_DP_GPIO2); 2530 regmap_update_bits(rt5668->regmap, RT5668_GPIO_CTRL_1, 2531 RT5668_GP2_PIN_MASK, RT5668_GP2_PIN_DMIC_SDA); 2532 break; 2533 2534 case RT5668_DMIC1_DATA_GPIO5: /* share with DACDAT1 */ 2535 regmap_update_bits(rt5668->regmap, RT5668_DMIC_CTRL_1, 2536 RT5668_DMIC_1_DP_MASK, RT5668_DMIC_1_DP_GPIO5); 2537 regmap_update_bits(rt5668->regmap, RT5668_GPIO_CTRL_1, 2538 RT5668_GP5_PIN_MASK, RT5668_GP5_PIN_DMIC_SDA); 2539 break; 2540 2541 default: 2542 dev_dbg(&i2c->dev, "invalid DMIC_DAT pin\n"); 2543 break; 2544 } 2545 2546 switch (rt5668->pdata.dmic1_clk_pin) { 2547 case RT5668_DMIC1_CLK_GPIO1: /* share with IRQ */ 2548 regmap_update_bits(rt5668->regmap, RT5668_GPIO_CTRL_1, 2549 RT5668_GP1_PIN_MASK, RT5668_GP1_PIN_DMIC_CLK); 2550 break; 2551 2552 case RT5668_DMIC1_CLK_GPIO3: /* share with BCLK2 */ 2553 regmap_update_bits(rt5668->regmap, RT5668_GPIO_CTRL_1, 2554 RT5668_GP3_PIN_MASK, RT5668_GP3_PIN_DMIC_CLK); 2555 break; 2556 2557 default: 2558 dev_dbg(&i2c->dev, "invalid DMIC_CLK pin\n"); 2559 break; 2560 } 2561 } 2562 2563 regmap_update_bits(rt5668->regmap, RT5668_PWR_ANLG_1, 2564 RT5668_LDO1_DVO_MASK | RT5668_HP_DRIVER_MASK, 2565 RT5668_LDO1_DVO_14 | RT5668_HP_DRIVER_5X); 2566 regmap_write(rt5668->regmap, RT5668_MICBIAS_2, 0x0380); 2567 regmap_update_bits(rt5668->regmap, RT5668_GPIO_CTRL_1, 2568 RT5668_GP4_PIN_MASK | RT5668_GP5_PIN_MASK, 2569 RT5668_GP4_PIN_ADCDAT1 | RT5668_GP5_PIN_DACDAT1); 2570 regmap_write(rt5668->regmap, RT5668_TEST_MODE_CTRL_1, 0x0000); 2571 2572 INIT_DELAYED_WORK(&rt5668->jack_detect_work, 2573 rt5668_jack_detect_handler); 2574 INIT_DELAYED_WORK(&rt5668->jd_check_work, 2575 rt5668_jd_check_handler); 2576 2577 mutex_init(&rt5668->calibrate_mutex); 2578 2579 if (i2c->irq) { 2580 ret = devm_request_threaded_irq(&i2c->dev, i2c->irq, NULL, 2581 rt5668_irq, IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING 2582 | IRQF_ONESHOT, "rt5668", rt5668); 2583 if (ret) 2584 dev_err(&i2c->dev, "Failed to reguest IRQ: %d\n", ret); 2585 2586 } 2587 2588 return devm_snd_soc_register_component(&i2c->dev, &soc_component_dev_rt5668, 2589 rt5668_dai, ARRAY_SIZE(rt5668_dai)); 2590 } 2591 2592 static void rt5668_i2c_shutdown(struct i2c_client *client) 2593 { 2594 struct rt5668_priv *rt5668 = i2c_get_clientdata(client); 2595 2596 rt5668_reset(rt5668->regmap); 2597 } 2598 2599 #ifdef CONFIG_OF 2600 static const struct of_device_id rt5668_of_match[] = { 2601 {.compatible = "realtek,rt5668b"}, 2602 {}, 2603 }; 2604 MODULE_DEVICE_TABLE(of, rt5668_of_match); 2605 #endif 2606 2607 #ifdef CONFIG_ACPI 2608 static const struct acpi_device_id rt5668_acpi_match[] = { 2609 {"10EC5668", 0,}, 2610 {}, 2611 }; 2612 MODULE_DEVICE_TABLE(acpi, rt5668_acpi_match); 2613 #endif 2614 2615 static struct i2c_driver rt5668_i2c_driver = { 2616 .driver = { 2617 .name = "rt5668b", 2618 .of_match_table = of_match_ptr(rt5668_of_match), 2619 .acpi_match_table = ACPI_PTR(rt5668_acpi_match), 2620 }, 2621 .probe_new = rt5668_i2c_probe, 2622 .shutdown = rt5668_i2c_shutdown, 2623 .id_table = rt5668_i2c_id, 2624 }; 2625 module_i2c_driver(rt5668_i2c_driver); 2626 2627 MODULE_DESCRIPTION("ASoC RT5668B driver"); 2628 MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>"); 2629 MODULE_LICENSE("GPL v2"); 2630