1 /* 2 * rt5663.c -- RT5663 ALSA SoC audio codec driver 3 * 4 * Copyright 2016 Realtek Semiconductor Corp. 5 * Author: Jack Yu <jack.yu@realtek.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11 #include <linux/module.h> 12 #include <linux/moduleparam.h> 13 #include <linux/init.h> 14 #include <linux/delay.h> 15 #include <linux/pm.h> 16 #include <linux/i2c.h> 17 #include <linux/platform_device.h> 18 #include <linux/spi/spi.h> 19 #include <linux/acpi.h> 20 #include <linux/workqueue.h> 21 #include <sound/core.h> 22 #include <sound/pcm.h> 23 #include <sound/pcm_params.h> 24 #include <sound/jack.h> 25 #include <sound/soc.h> 26 #include <sound/soc-dapm.h> 27 #include <sound/initval.h> 28 #include <sound/tlv.h> 29 30 #include "rt5663.h" 31 #include "rl6231.h" 32 33 #define RT5663_DEVICE_ID_2 0x6451 34 #define RT5663_DEVICE_ID_1 0x6406 35 36 enum { 37 CODEC_VER_1, 38 CODEC_VER_0, 39 }; 40 41 struct impedance_mapping_table { 42 unsigned int imp_min; 43 unsigned int imp_max; 44 unsigned int vol; 45 unsigned int dc_offset_l_manual; 46 unsigned int dc_offset_r_manual; 47 unsigned int dc_offset_l_manual_mic; 48 unsigned int dc_offset_r_manual_mic; 49 }; 50 51 struct rt5663_priv { 52 struct snd_soc_component *component; 53 struct rt5663_platform_data pdata; 54 struct regmap *regmap; 55 struct delayed_work jack_detect_work, jd_unplug_work; 56 struct snd_soc_jack *hs_jack; 57 struct timer_list btn_check_timer; 58 struct impedance_mapping_table *imp_table; 59 60 int codec_ver; 61 int sysclk; 62 int sysclk_src; 63 int lrck; 64 65 int pll_src; 66 int pll_in; 67 int pll_out; 68 69 int jack_type; 70 }; 71 72 static const struct reg_sequence rt5663_patch_list[] = { 73 { 0x002a, 0x8020 }, 74 { 0x0086, 0x0028 }, 75 { 0x0117, 0x0f28 }, 76 { 0x02fb, 0x8089 }, 77 }; 78 79 static const struct reg_default rt5663_v2_reg[] = { 80 { 0x0000, 0x0000 }, 81 { 0x0001, 0xc8c8 }, 82 { 0x0002, 0x8080 }, 83 { 0x0003, 0x8000 }, 84 { 0x0004, 0xc80a }, 85 { 0x0005, 0x0000 }, 86 { 0x0006, 0x0000 }, 87 { 0x0007, 0x0000 }, 88 { 0x000a, 0x0000 }, 89 { 0x000b, 0x0000 }, 90 { 0x000c, 0x0000 }, 91 { 0x000d, 0x0000 }, 92 { 0x000f, 0x0808 }, 93 { 0x0010, 0x4000 }, 94 { 0x0011, 0x0000 }, 95 { 0x0012, 0x1404 }, 96 { 0x0013, 0x1000 }, 97 { 0x0014, 0xa00a }, 98 { 0x0015, 0x0404 }, 99 { 0x0016, 0x0404 }, 100 { 0x0017, 0x0011 }, 101 { 0x0018, 0xafaf }, 102 { 0x0019, 0xafaf }, 103 { 0x001a, 0xafaf }, 104 { 0x001b, 0x0011 }, 105 { 0x001c, 0x2f2f }, 106 { 0x001d, 0x2f2f }, 107 { 0x001e, 0x2f2f }, 108 { 0x001f, 0x0000 }, 109 { 0x0020, 0x0000 }, 110 { 0x0021, 0x0000 }, 111 { 0x0022, 0x5757 }, 112 { 0x0023, 0x0039 }, 113 { 0x0024, 0x000b }, 114 { 0x0026, 0xc0c0 }, 115 { 0x0027, 0xc0c0 }, 116 { 0x0028, 0xc0c0 }, 117 { 0x0029, 0x8080 }, 118 { 0x002a, 0xaaaa }, 119 { 0x002b, 0xaaaa }, 120 { 0x002c, 0xaba8 }, 121 { 0x002d, 0x0000 }, 122 { 0x002e, 0x0000 }, 123 { 0x002f, 0x0000 }, 124 { 0x0030, 0x0000 }, 125 { 0x0031, 0x5000 }, 126 { 0x0032, 0x0000 }, 127 { 0x0033, 0x0000 }, 128 { 0x0034, 0x0000 }, 129 { 0x0035, 0x0000 }, 130 { 0x003a, 0x0000 }, 131 { 0x003b, 0x0000 }, 132 { 0x003c, 0x00ff }, 133 { 0x003d, 0x0000 }, 134 { 0x003e, 0x00ff }, 135 { 0x003f, 0x0000 }, 136 { 0x0040, 0x0000 }, 137 { 0x0041, 0x00ff }, 138 { 0x0042, 0x0000 }, 139 { 0x0043, 0x00ff }, 140 { 0x0044, 0x0c0c }, 141 { 0x0049, 0xc00b }, 142 { 0x004a, 0x0000 }, 143 { 0x004b, 0x031f }, 144 { 0x004d, 0x0000 }, 145 { 0x004e, 0x001f }, 146 { 0x004f, 0x0000 }, 147 { 0x0050, 0x001f }, 148 { 0x0052, 0xf000 }, 149 { 0x0061, 0x0000 }, 150 { 0x0062, 0x0000 }, 151 { 0x0063, 0x003e }, 152 { 0x0064, 0x0000 }, 153 { 0x0065, 0x0000 }, 154 { 0x0066, 0x003f }, 155 { 0x0067, 0x0000 }, 156 { 0x006b, 0x0000 }, 157 { 0x006d, 0xff00 }, 158 { 0x006e, 0x2808 }, 159 { 0x006f, 0x000a }, 160 { 0x0070, 0x8000 }, 161 { 0x0071, 0x8000 }, 162 { 0x0072, 0x8000 }, 163 { 0x0073, 0x7000 }, 164 { 0x0074, 0x7770 }, 165 { 0x0075, 0x0002 }, 166 { 0x0076, 0x0001 }, 167 { 0x0078, 0x00f0 }, 168 { 0x0079, 0x0000 }, 169 { 0x007a, 0x0000 }, 170 { 0x007b, 0x0000 }, 171 { 0x007c, 0x0000 }, 172 { 0x007d, 0x0123 }, 173 { 0x007e, 0x4500 }, 174 { 0x007f, 0x8003 }, 175 { 0x0080, 0x0000 }, 176 { 0x0081, 0x0000 }, 177 { 0x0082, 0x0000 }, 178 { 0x0083, 0x0000 }, 179 { 0x0084, 0x0000 }, 180 { 0x0085, 0x0000 }, 181 { 0x0086, 0x0008 }, 182 { 0x0087, 0x0000 }, 183 { 0x0088, 0x0000 }, 184 { 0x0089, 0x0000 }, 185 { 0x008a, 0x0000 }, 186 { 0x008b, 0x0000 }, 187 { 0x008c, 0x0003 }, 188 { 0x008e, 0x0060 }, 189 { 0x008f, 0x1000 }, 190 { 0x0091, 0x0c26 }, 191 { 0x0092, 0x0073 }, 192 { 0x0093, 0x0000 }, 193 { 0x0094, 0x0080 }, 194 { 0x0098, 0x0000 }, 195 { 0x0099, 0x0000 }, 196 { 0x009a, 0x0007 }, 197 { 0x009f, 0x0000 }, 198 { 0x00a0, 0x0000 }, 199 { 0x00a1, 0x0002 }, 200 { 0x00a2, 0x0001 }, 201 { 0x00a3, 0x0002 }, 202 { 0x00a4, 0x0001 }, 203 { 0x00ae, 0x2040 }, 204 { 0x00af, 0x0000 }, 205 { 0x00b6, 0x0000 }, 206 { 0x00b7, 0x0000 }, 207 { 0x00b8, 0x0000 }, 208 { 0x00b9, 0x0000 }, 209 { 0x00ba, 0x0002 }, 210 { 0x00bb, 0x0000 }, 211 { 0x00be, 0x0000 }, 212 { 0x00c0, 0x0000 }, 213 { 0x00c1, 0x0aaa }, 214 { 0x00c2, 0xaa80 }, 215 { 0x00c3, 0x0003 }, 216 { 0x00c4, 0x0000 }, 217 { 0x00d0, 0x0000 }, 218 { 0x00d1, 0x2244 }, 219 { 0x00d2, 0x0000 }, 220 { 0x00d3, 0x3300 }, 221 { 0x00d4, 0x2200 }, 222 { 0x00d9, 0x0809 }, 223 { 0x00da, 0x0000 }, 224 { 0x00db, 0x0008 }, 225 { 0x00dc, 0x00c0 }, 226 { 0x00dd, 0x6724 }, 227 { 0x00de, 0x3131 }, 228 { 0x00df, 0x0008 }, 229 { 0x00e0, 0x4000 }, 230 { 0x00e1, 0x3131 }, 231 { 0x00e2, 0x600c }, 232 { 0x00ea, 0xb320 }, 233 { 0x00eb, 0x0000 }, 234 { 0x00ec, 0xb300 }, 235 { 0x00ed, 0x0000 }, 236 { 0x00ee, 0xb320 }, 237 { 0x00ef, 0x0000 }, 238 { 0x00f0, 0x0201 }, 239 { 0x00f1, 0x0ddd }, 240 { 0x00f2, 0x0ddd }, 241 { 0x00f6, 0x0000 }, 242 { 0x00f7, 0x0000 }, 243 { 0x00f8, 0x0000 }, 244 { 0x00fa, 0x0000 }, 245 { 0x00fb, 0x0000 }, 246 { 0x00fc, 0x0000 }, 247 { 0x00fd, 0x0000 }, 248 { 0x00fe, 0x10ec }, 249 { 0x00ff, 0x6451 }, 250 { 0x0100, 0xaaaa }, 251 { 0x0101, 0x000a }, 252 { 0x010a, 0xaaaa }, 253 { 0x010b, 0xa0a0 }, 254 { 0x010c, 0xaeae }, 255 { 0x010d, 0xaaaa }, 256 { 0x010e, 0xaaaa }, 257 { 0x010f, 0xaaaa }, 258 { 0x0110, 0xe002 }, 259 { 0x0111, 0xa602 }, 260 { 0x0112, 0xaaaa }, 261 { 0x0113, 0x2000 }, 262 { 0x0117, 0x0f00 }, 263 { 0x0125, 0x0420 }, 264 { 0x0132, 0x0000 }, 265 { 0x0133, 0x0000 }, 266 { 0x0136, 0x5555 }, 267 { 0x0137, 0x5540 }, 268 { 0x0138, 0x3700 }, 269 { 0x0139, 0x79a1 }, 270 { 0x013a, 0x2020 }, 271 { 0x013b, 0x2020 }, 272 { 0x013c, 0x2005 }, 273 { 0x013f, 0x0000 }, 274 { 0x0145, 0x0002 }, 275 { 0x0146, 0x0000 }, 276 { 0x0147, 0x0000 }, 277 { 0x0148, 0x0000 }, 278 { 0x0160, 0x4ec0 }, 279 { 0x0161, 0x0080 }, 280 { 0x0162, 0x0200 }, 281 { 0x0163, 0x0800 }, 282 { 0x0164, 0x0000 }, 283 { 0x0165, 0x0000 }, 284 { 0x0166, 0x0000 }, 285 { 0x0167, 0x000f }, 286 { 0x0168, 0x000f }, 287 { 0x0170, 0x4e80 }, 288 { 0x0171, 0x0080 }, 289 { 0x0172, 0x0200 }, 290 { 0x0173, 0x0800 }, 291 { 0x0174, 0x00ff }, 292 { 0x0175, 0x0000 }, 293 { 0x0190, 0x4131 }, 294 { 0x0191, 0x4131 }, 295 { 0x0192, 0x4131 }, 296 { 0x0193, 0x4131 }, 297 { 0x0194, 0x0000 }, 298 { 0x0195, 0x0000 }, 299 { 0x0196, 0x0000 }, 300 { 0x0197, 0x0000 }, 301 { 0x0198, 0x0000 }, 302 { 0x0199, 0x0000 }, 303 { 0x01a0, 0x1e64 }, 304 { 0x01a1, 0x06a3 }, 305 { 0x01a2, 0x0000 }, 306 { 0x01a3, 0x0000 }, 307 { 0x01a4, 0x0000 }, 308 { 0x01a5, 0x0000 }, 309 { 0x01a6, 0x0000 }, 310 { 0x01a7, 0x0000 }, 311 { 0x01a8, 0x0000 }, 312 { 0x01a9, 0x0000 }, 313 { 0x01aa, 0x0000 }, 314 { 0x01ab, 0x0000 }, 315 { 0x01b5, 0x0000 }, 316 { 0x01b6, 0x01c3 }, 317 { 0x01b7, 0x02a0 }, 318 { 0x01b8, 0x03e9 }, 319 { 0x01b9, 0x1389 }, 320 { 0x01ba, 0xc351 }, 321 { 0x01bb, 0x0009 }, 322 { 0x01bc, 0x0018 }, 323 { 0x01bd, 0x002a }, 324 { 0x01be, 0x004c }, 325 { 0x01bf, 0x0097 }, 326 { 0x01c0, 0x433d }, 327 { 0x01c1, 0x0000 }, 328 { 0x01c2, 0x0000 }, 329 { 0x01c3, 0x0000 }, 330 { 0x01c4, 0x0000 }, 331 { 0x01c5, 0x0000 }, 332 { 0x01c6, 0x0000 }, 333 { 0x01c7, 0x0000 }, 334 { 0x01c8, 0x40af }, 335 { 0x01c9, 0x0702 }, 336 { 0x01ca, 0x0000 }, 337 { 0x01cb, 0x0000 }, 338 { 0x01cc, 0x5757 }, 339 { 0x01cd, 0x5757 }, 340 { 0x01ce, 0x5757 }, 341 { 0x01cf, 0x5757 }, 342 { 0x01d0, 0x5757 }, 343 { 0x01d1, 0x5757 }, 344 { 0x01d2, 0x5757 }, 345 { 0x01d3, 0x5757 }, 346 { 0x01d4, 0x5757 }, 347 { 0x01d5, 0x5757 }, 348 { 0x01d6, 0x003c }, 349 { 0x01da, 0x0000 }, 350 { 0x01db, 0x0000 }, 351 { 0x01dc, 0x0000 }, 352 { 0x01de, 0x7c00 }, 353 { 0x01df, 0x0320 }, 354 { 0x01e0, 0x06a1 }, 355 { 0x01e1, 0x0000 }, 356 { 0x01e2, 0x0000 }, 357 { 0x01e3, 0x0000 }, 358 { 0x01e4, 0x0000 }, 359 { 0x01e5, 0x0000 }, 360 { 0x01e6, 0x0001 }, 361 { 0x01e7, 0x0000 }, 362 { 0x01e8, 0x0000 }, 363 { 0x01ea, 0x0000 }, 364 { 0x01eb, 0x0000 }, 365 { 0x01ec, 0x0000 }, 366 { 0x01ed, 0x0000 }, 367 { 0x01ee, 0x0000 }, 368 { 0x01ef, 0x0000 }, 369 { 0x01f0, 0x0000 }, 370 { 0x01f1, 0x0000 }, 371 { 0x01f2, 0x0000 }, 372 { 0x01f3, 0x0000 }, 373 { 0x01f4, 0x0000 }, 374 { 0x0200, 0x0000 }, 375 { 0x0201, 0x0000 }, 376 { 0x0202, 0x0000 }, 377 { 0x0203, 0x0000 }, 378 { 0x0204, 0x0000 }, 379 { 0x0205, 0x0000 }, 380 { 0x0206, 0x0000 }, 381 { 0x0207, 0x0000 }, 382 { 0x0208, 0x0000 }, 383 { 0x0210, 0x60b1 }, 384 { 0x0211, 0xa000 }, 385 { 0x0212, 0x024c }, 386 { 0x0213, 0xf7ff }, 387 { 0x0214, 0x024c }, 388 { 0x0215, 0x0102 }, 389 { 0x0216, 0x00a3 }, 390 { 0x0217, 0x0048 }, 391 { 0x0218, 0x92c0 }, 392 { 0x0219, 0x0000 }, 393 { 0x021a, 0x00c8 }, 394 { 0x021b, 0x0020 }, 395 { 0x02fa, 0x0000 }, 396 { 0x02fb, 0x0000 }, 397 { 0x02fc, 0x0000 }, 398 { 0x02ff, 0x0110 }, 399 { 0x0300, 0x001f }, 400 { 0x0301, 0x032c }, 401 { 0x0302, 0x5f21 }, 402 { 0x0303, 0x4000 }, 403 { 0x0304, 0x4000 }, 404 { 0x0305, 0x06d5 }, 405 { 0x0306, 0x8000 }, 406 { 0x0307, 0x0700 }, 407 { 0x0310, 0x4560 }, 408 { 0x0311, 0xa4a8 }, 409 { 0x0312, 0x7418 }, 410 { 0x0313, 0x0000 }, 411 { 0x0314, 0x0006 }, 412 { 0x0315, 0xffff }, 413 { 0x0316, 0xc400 }, 414 { 0x0317, 0x0000 }, 415 { 0x0330, 0x00a6 }, 416 { 0x0331, 0x04c3 }, 417 { 0x0332, 0x27c8 }, 418 { 0x0333, 0xbf50 }, 419 { 0x0334, 0x0045 }, 420 { 0x0335, 0x0007 }, 421 { 0x0336, 0x7418 }, 422 { 0x0337, 0x0501 }, 423 { 0x0338, 0x0000 }, 424 { 0x0339, 0x0010 }, 425 { 0x033a, 0x1010 }, 426 { 0x03c0, 0x7e00 }, 427 { 0x03c1, 0x8000 }, 428 { 0x03c2, 0x8000 }, 429 { 0x03c3, 0x8000 }, 430 { 0x03c4, 0x8000 }, 431 { 0x03c5, 0x8000 }, 432 { 0x03c6, 0x8000 }, 433 { 0x03c7, 0x8000 }, 434 { 0x03c8, 0x8000 }, 435 { 0x03c9, 0x8000 }, 436 { 0x03ca, 0x8000 }, 437 { 0x03cb, 0x8000 }, 438 { 0x03cc, 0x8000 }, 439 { 0x03d0, 0x0000 }, 440 { 0x03d1, 0x0000 }, 441 { 0x03d2, 0x0000 }, 442 { 0x03d3, 0x0000 }, 443 { 0x03d4, 0x2000 }, 444 { 0x03d5, 0x2000 }, 445 { 0x03d6, 0x0000 }, 446 { 0x03d7, 0x0000 }, 447 { 0x03d8, 0x2000 }, 448 { 0x03d9, 0x2000 }, 449 { 0x03da, 0x2000 }, 450 { 0x03db, 0x2000 }, 451 { 0x03dc, 0x0000 }, 452 { 0x03dd, 0x0000 }, 453 { 0x03de, 0x0000 }, 454 { 0x03df, 0x2000 }, 455 { 0x03e0, 0x0000 }, 456 { 0x03e1, 0x0000 }, 457 { 0x03e2, 0x0000 }, 458 { 0x03e3, 0x0000 }, 459 { 0x03e4, 0x0000 }, 460 { 0x03e5, 0x0000 }, 461 { 0x03e6, 0x0000 }, 462 { 0x03e7, 0x0000 }, 463 { 0x03e8, 0x0000 }, 464 { 0x03e9, 0x0000 }, 465 { 0x03ea, 0x0000 }, 466 { 0x03eb, 0x0000 }, 467 { 0x03ec, 0x0000 }, 468 { 0x03ed, 0x0000 }, 469 { 0x03ee, 0x0000 }, 470 { 0x03ef, 0x0000 }, 471 { 0x03f0, 0x0800 }, 472 { 0x03f1, 0x0800 }, 473 { 0x03f2, 0x0800 }, 474 { 0x03f3, 0x0800 }, 475 { 0x03fe, 0x0000 }, 476 { 0x03ff, 0x0000 }, 477 { 0x07f0, 0x0000 }, 478 { 0x07fa, 0x0000 }, 479 }; 480 481 static const struct reg_default rt5663_reg[] = { 482 { 0x0000, 0x0000 }, 483 { 0x0002, 0x0008 }, 484 { 0x0005, 0x1000 }, 485 { 0x0006, 0x1000 }, 486 { 0x000a, 0x0000 }, 487 { 0x0010, 0x000f }, 488 { 0x0015, 0x42f1 }, 489 { 0x0016, 0x0000 }, 490 { 0x0018, 0x000b }, 491 { 0x0019, 0xafaf }, 492 { 0x001c, 0x2f2f }, 493 { 0x001f, 0x0000 }, 494 { 0x0022, 0x5757 }, 495 { 0x0023, 0x0039 }, 496 { 0x0026, 0xc0c0 }, 497 { 0x0029, 0x8080 }, 498 { 0x002a, 0x8020 }, 499 { 0x002c, 0x000c }, 500 { 0x002d, 0x0000 }, 501 { 0x0040, 0x0808 }, 502 { 0x0061, 0x0000 }, 503 { 0x0062, 0x0000 }, 504 { 0x0063, 0x003e }, 505 { 0x0064, 0x0000 }, 506 { 0x0065, 0x0000 }, 507 { 0x0066, 0x0000 }, 508 { 0x006b, 0x0000 }, 509 { 0x006e, 0x0000 }, 510 { 0x006f, 0x0000 }, 511 { 0x0070, 0x8020 }, 512 { 0x0073, 0x1000 }, 513 { 0x0074, 0xe400 }, 514 { 0x0075, 0x0002 }, 515 { 0x0076, 0x0001 }, 516 { 0x0077, 0x00f0 }, 517 { 0x0078, 0x0000 }, 518 { 0x0079, 0x0000 }, 519 { 0x007a, 0x0123 }, 520 { 0x007b, 0x8003 }, 521 { 0x0080, 0x0000 }, 522 { 0x0081, 0x0000 }, 523 { 0x0082, 0x0000 }, 524 { 0x0083, 0x0000 }, 525 { 0x0084, 0x0000 }, 526 { 0x0086, 0x0028 }, 527 { 0x0087, 0x0000 }, 528 { 0x008a, 0x0000 }, 529 { 0x008b, 0x0000 }, 530 { 0x008c, 0x0003 }, 531 { 0x008e, 0x0008 }, 532 { 0x008f, 0x1000 }, 533 { 0x0090, 0x0646 }, 534 { 0x0091, 0x0e3e }, 535 { 0x0092, 0x1071 }, 536 { 0x0093, 0x0000 }, 537 { 0x0094, 0x0080 }, 538 { 0x0097, 0x0000 }, 539 { 0x0098, 0x0000 }, 540 { 0x009a, 0x0000 }, 541 { 0x009f, 0x0000 }, 542 { 0x00ae, 0x6000 }, 543 { 0x00af, 0x0000 }, 544 { 0x00b6, 0x0000 }, 545 { 0x00b7, 0x0000 }, 546 { 0x00b8, 0x0000 }, 547 { 0x00ba, 0x0000 }, 548 { 0x00bb, 0x0000 }, 549 { 0x00be, 0x0000 }, 550 { 0x00bf, 0x0000 }, 551 { 0x00c0, 0x0000 }, 552 { 0x00c1, 0x0000 }, 553 { 0x00c5, 0x0000 }, 554 { 0x00cb, 0xa02f }, 555 { 0x00cc, 0x0000 }, 556 { 0x00cd, 0x0e02 }, 557 { 0x00d9, 0x08f9 }, 558 { 0x00db, 0x0008 }, 559 { 0x00dc, 0x00c0 }, 560 { 0x00dd, 0x6729 }, 561 { 0x00de, 0x3131 }, 562 { 0x00df, 0x0008 }, 563 { 0x00e0, 0x4000 }, 564 { 0x00e1, 0x3131 }, 565 { 0x00e2, 0x0043 }, 566 { 0x00e4, 0x400b }, 567 { 0x00e5, 0x8031 }, 568 { 0x00e6, 0x3080 }, 569 { 0x00e7, 0x4100 }, 570 { 0x00e8, 0x1400 }, 571 { 0x00e9, 0xe00a }, 572 { 0x00ea, 0x0404 }, 573 { 0x00eb, 0x0404 }, 574 { 0x00ec, 0xb320 }, 575 { 0x00ed, 0x0000 }, 576 { 0x00f4, 0x0000 }, 577 { 0x00f6, 0x0000 }, 578 { 0x00f8, 0x0000 }, 579 { 0x00fa, 0x8000 }, 580 { 0x00fd, 0x0001 }, 581 { 0x00fe, 0x10ec }, 582 { 0x00ff, 0x6406 }, 583 { 0x0100, 0xa0a0 }, 584 { 0x0108, 0x4444 }, 585 { 0x0109, 0x4444 }, 586 { 0x010a, 0xaaaa }, 587 { 0x010b, 0x00a0 }, 588 { 0x010c, 0x8aaa }, 589 { 0x010d, 0xaaaa }, 590 { 0x010e, 0x2aaa }, 591 { 0x010f, 0x002a }, 592 { 0x0110, 0xa0a4 }, 593 { 0x0111, 0x4602 }, 594 { 0x0112, 0x0101 }, 595 { 0x0113, 0x2000 }, 596 { 0x0114, 0x0000 }, 597 { 0x0116, 0x0000 }, 598 { 0x0117, 0x0f28 }, 599 { 0x0118, 0x0006 }, 600 { 0x0125, 0x2424 }, 601 { 0x0126, 0x5550 }, 602 { 0x0127, 0x0400 }, 603 { 0x0128, 0x7711 }, 604 { 0x0132, 0x0004 }, 605 { 0x0137, 0x5441 }, 606 { 0x0139, 0x79a1 }, 607 { 0x013a, 0x30c0 }, 608 { 0x013b, 0x2000 }, 609 { 0x013c, 0x2005 }, 610 { 0x013d, 0x30c0 }, 611 { 0x013e, 0x0000 }, 612 { 0x0140, 0x3700 }, 613 { 0x0141, 0x1f00 }, 614 { 0x0144, 0x0000 }, 615 { 0x0145, 0x0002 }, 616 { 0x0146, 0x0000 }, 617 { 0x0160, 0x0e80 }, 618 { 0x0161, 0x0080 }, 619 { 0x0162, 0x0200 }, 620 { 0x0163, 0x0800 }, 621 { 0x0164, 0x0000 }, 622 { 0x0165, 0x0000 }, 623 { 0x0166, 0x0000 }, 624 { 0x0167, 0x1417 }, 625 { 0x0168, 0x0017 }, 626 { 0x0169, 0x0017 }, 627 { 0x0180, 0x2000 }, 628 { 0x0181, 0x0000 }, 629 { 0x0182, 0x0000 }, 630 { 0x0183, 0x2000 }, 631 { 0x0184, 0x0000 }, 632 { 0x0185, 0x0000 }, 633 { 0x01b0, 0x4b30 }, 634 { 0x01b1, 0x0000 }, 635 { 0x01b2, 0xd870 }, 636 { 0x01b3, 0x0000 }, 637 { 0x01b4, 0x0030 }, 638 { 0x01b5, 0x5757 }, 639 { 0x01b6, 0x5757 }, 640 { 0x01b7, 0x5757 }, 641 { 0x01b8, 0x5757 }, 642 { 0x01c0, 0x433d }, 643 { 0x01c1, 0x0540 }, 644 { 0x01c2, 0x0000 }, 645 { 0x01c3, 0x0000 }, 646 { 0x01c4, 0x0000 }, 647 { 0x01c5, 0x0009 }, 648 { 0x01c6, 0x0018 }, 649 { 0x01c7, 0x002a }, 650 { 0x01c8, 0x004c }, 651 { 0x01c9, 0x0097 }, 652 { 0x01ca, 0x01c3 }, 653 { 0x01cb, 0x03e9 }, 654 { 0x01cc, 0x1389 }, 655 { 0x01cd, 0xc351 }, 656 { 0x01ce, 0x0000 }, 657 { 0x01cf, 0x0000 }, 658 { 0x01d0, 0x0000 }, 659 { 0x01d1, 0x0000 }, 660 { 0x01d2, 0x0000 }, 661 { 0x01d3, 0x003c }, 662 { 0x01d4, 0x5757 }, 663 { 0x01d5, 0x5757 }, 664 { 0x01d6, 0x5757 }, 665 { 0x01d7, 0x5757 }, 666 { 0x01d8, 0x5757 }, 667 { 0x01d9, 0x5757 }, 668 { 0x01da, 0x0000 }, 669 { 0x01db, 0x0000 }, 670 { 0x01dd, 0x0009 }, 671 { 0x01de, 0x7f00 }, 672 { 0x01df, 0x00c8 }, 673 { 0x01e0, 0x0691 }, 674 { 0x01e1, 0x0000 }, 675 { 0x01e2, 0x0000 }, 676 { 0x01e3, 0x0000 }, 677 { 0x01e4, 0x0000 }, 678 { 0x01e5, 0x0040 }, 679 { 0x01e6, 0x0000 }, 680 { 0x01e7, 0x0000 }, 681 { 0x01e8, 0x0000 }, 682 { 0x01ea, 0x0000 }, 683 { 0x01eb, 0x0000 }, 684 { 0x01ec, 0x0000 }, 685 { 0x01ed, 0x0000 }, 686 { 0x01ee, 0x0000 }, 687 { 0x01ef, 0x0000 }, 688 { 0x01f0, 0x0000 }, 689 { 0x01f1, 0x0000 }, 690 { 0x01f2, 0x0000 }, 691 { 0x0200, 0x0000 }, 692 { 0x0201, 0x2244 }, 693 { 0x0202, 0xaaaa }, 694 { 0x0250, 0x8010 }, 695 { 0x0251, 0x0000 }, 696 { 0x0252, 0x028a }, 697 { 0x02fa, 0x0000 }, 698 { 0x02fb, 0x8089 }, 699 { 0x02fc, 0x0300 }, 700 { 0x0300, 0x0000 }, 701 { 0x03d0, 0x0000 }, 702 { 0x03d1, 0x0000 }, 703 { 0x03d2, 0x0000 }, 704 { 0x03d3, 0x0000 }, 705 { 0x03d4, 0x2000 }, 706 { 0x03d5, 0x2000 }, 707 { 0x03d6, 0x0000 }, 708 { 0x03d7, 0x0000 }, 709 { 0x03d8, 0x2000 }, 710 { 0x03d9, 0x2000 }, 711 { 0x03da, 0x2000 }, 712 { 0x03db, 0x2000 }, 713 { 0x03dc, 0x0000 }, 714 { 0x03dd, 0x0000 }, 715 { 0x03de, 0x0000 }, 716 { 0x03df, 0x2000 }, 717 { 0x03e0, 0x0000 }, 718 { 0x03e1, 0x0000 }, 719 { 0x03e2, 0x0000 }, 720 { 0x03e3, 0x0000 }, 721 { 0x03e4, 0x0000 }, 722 { 0x03e5, 0x0000 }, 723 { 0x03e6, 0x0000 }, 724 { 0x03e7, 0x0000 }, 725 { 0x03e8, 0x0000 }, 726 { 0x03e9, 0x0000 }, 727 { 0x03ea, 0x0000 }, 728 { 0x03eb, 0x0000 }, 729 { 0x03ec, 0x0000 }, 730 { 0x03ed, 0x0000 }, 731 { 0x03ee, 0x0000 }, 732 { 0x03ef, 0x0000 }, 733 { 0x03f0, 0x0800 }, 734 { 0x03f1, 0x0800 }, 735 { 0x03f2, 0x0800 }, 736 { 0x03f3, 0x0800 }, 737 }; 738 739 static bool rt5663_volatile_register(struct device *dev, unsigned int reg) 740 { 741 switch (reg) { 742 case RT5663_RESET: 743 case RT5663_SIL_DET_CTL: 744 case RT5663_HP_IMP_GAIN_2: 745 case RT5663_AD_DA_MIXER: 746 case RT5663_FRAC_DIV_2: 747 case RT5663_MICBIAS_1: 748 case RT5663_ASRC_11_2: 749 case RT5663_ADC_EQ_1: 750 case RT5663_INT_ST_1: 751 case RT5663_INT_ST_2: 752 case RT5663_GPIO_STA1: 753 case RT5663_SIN_GEN_1: 754 case RT5663_IL_CMD_1: 755 case RT5663_IL_CMD_5: 756 case RT5663_IL_CMD_PWRSAV1: 757 case RT5663_EM_JACK_TYPE_1: 758 case RT5663_EM_JACK_TYPE_2: 759 case RT5663_EM_JACK_TYPE_3: 760 case RT5663_JD_CTRL2: 761 case RT5663_VENDOR_ID: 762 case RT5663_VENDOR_ID_1: 763 case RT5663_VENDOR_ID_2: 764 case RT5663_PLL_INT_REG: 765 case RT5663_SOFT_RAMP: 766 case RT5663_STO_DRE_1: 767 case RT5663_STO_DRE_5: 768 case RT5663_STO_DRE_6: 769 case RT5663_STO_DRE_7: 770 case RT5663_MIC_DECRO_1: 771 case RT5663_MIC_DECRO_4: 772 case RT5663_HP_IMP_SEN_1: 773 case RT5663_HP_IMP_SEN_3: 774 case RT5663_HP_IMP_SEN_4: 775 case RT5663_HP_IMP_SEN_5: 776 case RT5663_HP_CALIB_1_1: 777 case RT5663_HP_CALIB_9: 778 case RT5663_HP_CALIB_ST1: 779 case RT5663_HP_CALIB_ST2: 780 case RT5663_HP_CALIB_ST3: 781 case RT5663_HP_CALIB_ST4: 782 case RT5663_HP_CALIB_ST5: 783 case RT5663_HP_CALIB_ST6: 784 case RT5663_HP_CALIB_ST7: 785 case RT5663_HP_CALIB_ST8: 786 case RT5663_HP_CALIB_ST9: 787 case RT5663_ANA_JD: 788 return true; 789 default: 790 return false; 791 } 792 } 793 794 static bool rt5663_readable_register(struct device *dev, unsigned int reg) 795 { 796 switch (reg) { 797 case RT5663_RESET: 798 case RT5663_HP_OUT_EN: 799 case RT5663_HP_LCH_DRE: 800 case RT5663_HP_RCH_DRE: 801 case RT5663_CALIB_BST: 802 case RT5663_RECMIX: 803 case RT5663_SIL_DET_CTL: 804 case RT5663_PWR_SAV_SILDET: 805 case RT5663_SIDETONE_CTL: 806 case RT5663_STO1_DAC_DIG_VOL: 807 case RT5663_STO1_ADC_DIG_VOL: 808 case RT5663_STO1_BOOST: 809 case RT5663_HP_IMP_GAIN_1: 810 case RT5663_HP_IMP_GAIN_2: 811 case RT5663_STO1_ADC_MIXER: 812 case RT5663_AD_DA_MIXER: 813 case RT5663_STO_DAC_MIXER: 814 case RT5663_DIG_SIDE_MIXER: 815 case RT5663_BYPASS_STO_DAC: 816 case RT5663_CALIB_REC_MIX: 817 case RT5663_PWR_DIG_1: 818 case RT5663_PWR_DIG_2: 819 case RT5663_PWR_ANLG_1: 820 case RT5663_PWR_ANLG_2: 821 case RT5663_PWR_ANLG_3: 822 case RT5663_PWR_MIXER: 823 case RT5663_SIG_CLK_DET: 824 case RT5663_PRE_DIV_GATING_1: 825 case RT5663_PRE_DIV_GATING_2: 826 case RT5663_I2S1_SDP: 827 case RT5663_ADDA_CLK_1: 828 case RT5663_ADDA_RST: 829 case RT5663_FRAC_DIV_1: 830 case RT5663_FRAC_DIV_2: 831 case RT5663_TDM_1: 832 case RT5663_TDM_2: 833 case RT5663_TDM_3: 834 case RT5663_TDM_4: 835 case RT5663_TDM_5: 836 case RT5663_GLB_CLK: 837 case RT5663_PLL_1: 838 case RT5663_PLL_2: 839 case RT5663_ASRC_1: 840 case RT5663_ASRC_2: 841 case RT5663_ASRC_4: 842 case RT5663_DUMMY_REG: 843 case RT5663_ASRC_8: 844 case RT5663_ASRC_9: 845 case RT5663_ASRC_11: 846 case RT5663_DEPOP_1: 847 case RT5663_DEPOP_2: 848 case RT5663_DEPOP_3: 849 case RT5663_HP_CHARGE_PUMP_1: 850 case RT5663_HP_CHARGE_PUMP_2: 851 case RT5663_MICBIAS_1: 852 case RT5663_RC_CLK: 853 case RT5663_ASRC_11_2: 854 case RT5663_DUMMY_REG_2: 855 case RT5663_REC_PATH_GAIN: 856 case RT5663_AUTO_1MRC_CLK: 857 case RT5663_ADC_EQ_1: 858 case RT5663_ADC_EQ_2: 859 case RT5663_IRQ_1: 860 case RT5663_IRQ_2: 861 case RT5663_IRQ_3: 862 case RT5663_IRQ_4: 863 case RT5663_IRQ_5: 864 case RT5663_INT_ST_1: 865 case RT5663_INT_ST_2: 866 case RT5663_GPIO_1: 867 case RT5663_GPIO_2: 868 case RT5663_GPIO_STA1: 869 case RT5663_SIN_GEN_1: 870 case RT5663_SIN_GEN_2: 871 case RT5663_SIN_GEN_3: 872 case RT5663_SOF_VOL_ZC1: 873 case RT5663_IL_CMD_1: 874 case RT5663_IL_CMD_2: 875 case RT5663_IL_CMD_3: 876 case RT5663_IL_CMD_4: 877 case RT5663_IL_CMD_5: 878 case RT5663_IL_CMD_6: 879 case RT5663_IL_CMD_7: 880 case RT5663_IL_CMD_8: 881 case RT5663_IL_CMD_PWRSAV1: 882 case RT5663_IL_CMD_PWRSAV2: 883 case RT5663_EM_JACK_TYPE_1: 884 case RT5663_EM_JACK_TYPE_2: 885 case RT5663_EM_JACK_TYPE_3: 886 case RT5663_EM_JACK_TYPE_4: 887 case RT5663_EM_JACK_TYPE_5: 888 case RT5663_EM_JACK_TYPE_6: 889 case RT5663_STO1_HPF_ADJ1: 890 case RT5663_STO1_HPF_ADJ2: 891 case RT5663_FAST_OFF_MICBIAS: 892 case RT5663_JD_CTRL1: 893 case RT5663_JD_CTRL2: 894 case RT5663_DIG_MISC: 895 case RT5663_VENDOR_ID: 896 case RT5663_VENDOR_ID_1: 897 case RT5663_VENDOR_ID_2: 898 case RT5663_DIG_VOL_ZCD: 899 case RT5663_ANA_BIAS_CUR_1: 900 case RT5663_ANA_BIAS_CUR_2: 901 case RT5663_ANA_BIAS_CUR_3: 902 case RT5663_ANA_BIAS_CUR_4: 903 case RT5663_ANA_BIAS_CUR_5: 904 case RT5663_ANA_BIAS_CUR_6: 905 case RT5663_BIAS_CUR_5: 906 case RT5663_BIAS_CUR_6: 907 case RT5663_BIAS_CUR_7: 908 case RT5663_BIAS_CUR_8: 909 case RT5663_DACREF_LDO: 910 case RT5663_DUMMY_REG_3: 911 case RT5663_BIAS_CUR_9: 912 case RT5663_DUMMY_REG_4: 913 case RT5663_VREFADJ_OP: 914 case RT5663_VREF_RECMIX: 915 case RT5663_CHARGE_PUMP_1: 916 case RT5663_CHARGE_PUMP_1_2: 917 case RT5663_CHARGE_PUMP_1_3: 918 case RT5663_CHARGE_PUMP_2: 919 case RT5663_DIG_IN_PIN1: 920 case RT5663_PAD_DRV_CTL: 921 case RT5663_PLL_INT_REG: 922 case RT5663_CHOP_DAC_L: 923 case RT5663_CHOP_ADC: 924 case RT5663_CALIB_ADC: 925 case RT5663_CHOP_DAC_R: 926 case RT5663_DUMMY_CTL_DACLR: 927 case RT5663_DUMMY_REG_5: 928 case RT5663_SOFT_RAMP: 929 case RT5663_TEST_MODE_1: 930 case RT5663_TEST_MODE_2: 931 case RT5663_TEST_MODE_3: 932 case RT5663_STO_DRE_1: 933 case RT5663_STO_DRE_2: 934 case RT5663_STO_DRE_3: 935 case RT5663_STO_DRE_4: 936 case RT5663_STO_DRE_5: 937 case RT5663_STO_DRE_6: 938 case RT5663_STO_DRE_7: 939 case RT5663_STO_DRE_8: 940 case RT5663_STO_DRE_9: 941 case RT5663_STO_DRE_10: 942 case RT5663_MIC_DECRO_1: 943 case RT5663_MIC_DECRO_2: 944 case RT5663_MIC_DECRO_3: 945 case RT5663_MIC_DECRO_4: 946 case RT5663_MIC_DECRO_5: 947 case RT5663_MIC_DECRO_6: 948 case RT5663_HP_DECRO_1: 949 case RT5663_HP_DECRO_2: 950 case RT5663_HP_DECRO_3: 951 case RT5663_HP_DECRO_4: 952 case RT5663_HP_DECOUP: 953 case RT5663_HP_IMP_SEN_MAP8: 954 case RT5663_HP_IMP_SEN_MAP9: 955 case RT5663_HP_IMP_SEN_MAP10: 956 case RT5663_HP_IMP_SEN_MAP11: 957 case RT5663_HP_IMP_SEN_1: 958 case RT5663_HP_IMP_SEN_2: 959 case RT5663_HP_IMP_SEN_3: 960 case RT5663_HP_IMP_SEN_4: 961 case RT5663_HP_IMP_SEN_5: 962 case RT5663_HP_IMP_SEN_6: 963 case RT5663_HP_IMP_SEN_7: 964 case RT5663_HP_IMP_SEN_8: 965 case RT5663_HP_IMP_SEN_9: 966 case RT5663_HP_IMP_SEN_10: 967 case RT5663_HP_IMP_SEN_11: 968 case RT5663_HP_IMP_SEN_12: 969 case RT5663_HP_IMP_SEN_13: 970 case RT5663_HP_IMP_SEN_14: 971 case RT5663_HP_IMP_SEN_15: 972 case RT5663_HP_IMP_SEN_16: 973 case RT5663_HP_IMP_SEN_17: 974 case RT5663_HP_IMP_SEN_18: 975 case RT5663_HP_IMP_SEN_19: 976 case RT5663_HP_IMPSEN_DIG5: 977 case RT5663_HP_IMPSEN_MAP1: 978 case RT5663_HP_IMPSEN_MAP2: 979 case RT5663_HP_IMPSEN_MAP3: 980 case RT5663_HP_IMPSEN_MAP4: 981 case RT5663_HP_IMPSEN_MAP5: 982 case RT5663_HP_IMPSEN_MAP7: 983 case RT5663_HP_LOGIC_1: 984 case RT5663_HP_LOGIC_2: 985 case RT5663_HP_CALIB_1: 986 case RT5663_HP_CALIB_1_1: 987 case RT5663_HP_CALIB_2: 988 case RT5663_HP_CALIB_3: 989 case RT5663_HP_CALIB_4: 990 case RT5663_HP_CALIB_5: 991 case RT5663_HP_CALIB_5_1: 992 case RT5663_HP_CALIB_6: 993 case RT5663_HP_CALIB_7: 994 case RT5663_HP_CALIB_9: 995 case RT5663_HP_CALIB_10: 996 case RT5663_HP_CALIB_11: 997 case RT5663_HP_CALIB_ST1: 998 case RT5663_HP_CALIB_ST2: 999 case RT5663_HP_CALIB_ST3: 1000 case RT5663_HP_CALIB_ST4: 1001 case RT5663_HP_CALIB_ST5: 1002 case RT5663_HP_CALIB_ST6: 1003 case RT5663_HP_CALIB_ST7: 1004 case RT5663_HP_CALIB_ST8: 1005 case RT5663_HP_CALIB_ST9: 1006 case RT5663_HP_AMP_DET: 1007 case RT5663_DUMMY_REG_6: 1008 case RT5663_HP_BIAS: 1009 case RT5663_CBJ_1: 1010 case RT5663_CBJ_2: 1011 case RT5663_CBJ_3: 1012 case RT5663_DUMMY_1: 1013 case RT5663_DUMMY_2: 1014 case RT5663_DUMMY_3: 1015 case RT5663_ANA_JD: 1016 case RT5663_ADC_LCH_LPF1_A1: 1017 case RT5663_ADC_RCH_LPF1_A1: 1018 case RT5663_ADC_LCH_LPF1_H0: 1019 case RT5663_ADC_RCH_LPF1_H0: 1020 case RT5663_ADC_LCH_BPF1_A1: 1021 case RT5663_ADC_RCH_BPF1_A1: 1022 case RT5663_ADC_LCH_BPF1_A2: 1023 case RT5663_ADC_RCH_BPF1_A2: 1024 case RT5663_ADC_LCH_BPF1_H0: 1025 case RT5663_ADC_RCH_BPF1_H0: 1026 case RT5663_ADC_LCH_BPF2_A1: 1027 case RT5663_ADC_RCH_BPF2_A1: 1028 case RT5663_ADC_LCH_BPF2_A2: 1029 case RT5663_ADC_RCH_BPF2_A2: 1030 case RT5663_ADC_LCH_BPF2_H0: 1031 case RT5663_ADC_RCH_BPF2_H0: 1032 case RT5663_ADC_LCH_BPF3_A1: 1033 case RT5663_ADC_RCH_BPF3_A1: 1034 case RT5663_ADC_LCH_BPF3_A2: 1035 case RT5663_ADC_RCH_BPF3_A2: 1036 case RT5663_ADC_LCH_BPF3_H0: 1037 case RT5663_ADC_RCH_BPF3_H0: 1038 case RT5663_ADC_LCH_BPF4_A1: 1039 case RT5663_ADC_RCH_BPF4_A1: 1040 case RT5663_ADC_LCH_BPF4_A2: 1041 case RT5663_ADC_RCH_BPF4_A2: 1042 case RT5663_ADC_LCH_BPF4_H0: 1043 case RT5663_ADC_RCH_BPF4_H0: 1044 case RT5663_ADC_LCH_HPF1_A1: 1045 case RT5663_ADC_RCH_HPF1_A1: 1046 case RT5663_ADC_LCH_HPF1_H0: 1047 case RT5663_ADC_RCH_HPF1_H0: 1048 case RT5663_ADC_EQ_PRE_VOL_L: 1049 case RT5663_ADC_EQ_PRE_VOL_R: 1050 case RT5663_ADC_EQ_POST_VOL_L: 1051 case RT5663_ADC_EQ_POST_VOL_R: 1052 return true; 1053 default: 1054 return false; 1055 } 1056 } 1057 1058 static bool rt5663_v2_volatile_register(struct device *dev, unsigned int reg) 1059 { 1060 switch (reg) { 1061 case RT5663_RESET: 1062 case RT5663_CBJ_TYPE_2: 1063 case RT5663_PDM_OUT_CTL: 1064 case RT5663_PDM_I2C_DATA_CTL1: 1065 case RT5663_PDM_I2C_DATA_CTL4: 1066 case RT5663_ALC_BK_GAIN: 1067 case RT5663_PLL_2: 1068 case RT5663_MICBIAS_1: 1069 case RT5663_ADC_EQ_1: 1070 case RT5663_INT_ST_1: 1071 case RT5663_GPIO_STA2: 1072 case RT5663_IL_CMD_1: 1073 case RT5663_IL_CMD_5: 1074 case RT5663_A_JD_CTRL: 1075 case RT5663_JD_CTRL2: 1076 case RT5663_VENDOR_ID: 1077 case RT5663_VENDOR_ID_1: 1078 case RT5663_VENDOR_ID_2: 1079 case RT5663_STO_DRE_1: 1080 case RT5663_STO_DRE_5: 1081 case RT5663_STO_DRE_6: 1082 case RT5663_STO_DRE_7: 1083 case RT5663_MONO_DYNA_6: 1084 case RT5663_STO1_SIL_DET: 1085 case RT5663_MONOL_SIL_DET: 1086 case RT5663_MONOR_SIL_DET: 1087 case RT5663_STO2_DAC_SIL: 1088 case RT5663_MONO_AMP_CAL_ST1: 1089 case RT5663_MONO_AMP_CAL_ST2: 1090 case RT5663_MONO_AMP_CAL_ST3: 1091 case RT5663_MONO_AMP_CAL_ST4: 1092 case RT5663_HP_IMP_SEN_2: 1093 case RT5663_HP_IMP_SEN_3: 1094 case RT5663_HP_IMP_SEN_4: 1095 case RT5663_HP_IMP_SEN_10: 1096 case RT5663_HP_CALIB_1: 1097 case RT5663_HP_CALIB_10: 1098 case RT5663_HP_CALIB_ST1: 1099 case RT5663_HP_CALIB_ST4: 1100 case RT5663_HP_CALIB_ST5: 1101 case RT5663_HP_CALIB_ST6: 1102 case RT5663_HP_CALIB_ST7: 1103 case RT5663_HP_CALIB_ST8: 1104 case RT5663_HP_CALIB_ST9: 1105 case RT5663_HP_CALIB_ST10: 1106 case RT5663_HP_CALIB_ST11: 1107 return true; 1108 default: 1109 return false; 1110 } 1111 } 1112 1113 static bool rt5663_v2_readable_register(struct device *dev, unsigned int reg) 1114 { 1115 switch (reg) { 1116 case RT5663_LOUT_CTRL: 1117 case RT5663_HP_AMP_2: 1118 case RT5663_MONO_OUT: 1119 case RT5663_MONO_GAIN: 1120 case RT5663_AEC_BST: 1121 case RT5663_IN1_IN2: 1122 case RT5663_IN3_IN4: 1123 case RT5663_INL1_INR1: 1124 case RT5663_CBJ_TYPE_2: 1125 case RT5663_CBJ_TYPE_3: 1126 case RT5663_CBJ_TYPE_4: 1127 case RT5663_CBJ_TYPE_5: 1128 case RT5663_CBJ_TYPE_8: 1129 case RT5663_DAC3_DIG_VOL: 1130 case RT5663_DAC3_CTRL: 1131 case RT5663_MONO_ADC_DIG_VOL: 1132 case RT5663_STO2_ADC_DIG_VOL: 1133 case RT5663_MONO_ADC_BST_GAIN: 1134 case RT5663_STO2_ADC_BST_GAIN: 1135 case RT5663_SIDETONE_CTRL: 1136 case RT5663_MONO1_ADC_MIXER: 1137 case RT5663_STO2_ADC_MIXER: 1138 case RT5663_MONO_DAC_MIXER: 1139 case RT5663_DAC2_SRC_CTRL: 1140 case RT5663_IF_3_4_DATA_CTL: 1141 case RT5663_IF_5_DATA_CTL: 1142 case RT5663_PDM_OUT_CTL: 1143 case RT5663_PDM_I2C_DATA_CTL1: 1144 case RT5663_PDM_I2C_DATA_CTL2: 1145 case RT5663_PDM_I2C_DATA_CTL3: 1146 case RT5663_PDM_I2C_DATA_CTL4: 1147 case RT5663_RECMIX1_NEW: 1148 case RT5663_RECMIX1L_0: 1149 case RT5663_RECMIX1L: 1150 case RT5663_RECMIX1R_0: 1151 case RT5663_RECMIX1R: 1152 case RT5663_RECMIX2_NEW: 1153 case RT5663_RECMIX2_L_2: 1154 case RT5663_RECMIX2_R: 1155 case RT5663_RECMIX2_R_2: 1156 case RT5663_CALIB_REC_LR: 1157 case RT5663_ALC_BK_GAIN: 1158 case RT5663_MONOMIX_GAIN: 1159 case RT5663_MONOMIX_IN_GAIN: 1160 case RT5663_OUT_MIXL_GAIN: 1161 case RT5663_OUT_LMIX_IN_GAIN: 1162 case RT5663_OUT_RMIX_IN_GAIN: 1163 case RT5663_OUT_RMIX_IN_GAIN1: 1164 case RT5663_LOUT_MIXER_CTRL: 1165 case RT5663_PWR_VOL: 1166 case RT5663_ADCDAC_RST: 1167 case RT5663_I2S34_SDP: 1168 case RT5663_I2S5_SDP: 1169 case RT5663_TDM_6: 1170 case RT5663_TDM_7: 1171 case RT5663_TDM_8: 1172 case RT5663_TDM_9: 1173 case RT5663_ASRC_3: 1174 case RT5663_ASRC_6: 1175 case RT5663_ASRC_7: 1176 case RT5663_PLL_TRK_13: 1177 case RT5663_I2S_M_CLK_CTL: 1178 case RT5663_FDIV_I2S34_M_CLK: 1179 case RT5663_FDIV_I2S34_M_CLK2: 1180 case RT5663_FDIV_I2S5_M_CLK: 1181 case RT5663_FDIV_I2S5_M_CLK2: 1182 case RT5663_V2_IRQ_4: 1183 case RT5663_GPIO_3: 1184 case RT5663_GPIO_4: 1185 case RT5663_GPIO_STA2: 1186 case RT5663_HP_AMP_DET1: 1187 case RT5663_HP_AMP_DET2: 1188 case RT5663_HP_AMP_DET3: 1189 case RT5663_MID_BD_HP_AMP: 1190 case RT5663_LOW_BD_HP_AMP: 1191 case RT5663_SOF_VOL_ZC2: 1192 case RT5663_ADC_STO2_ADJ1: 1193 case RT5663_ADC_STO2_ADJ2: 1194 case RT5663_A_JD_CTRL: 1195 case RT5663_JD1_TRES_CTRL: 1196 case RT5663_JD2_TRES_CTRL: 1197 case RT5663_V2_JD_CTRL2: 1198 case RT5663_DUM_REG_2: 1199 case RT5663_DUM_REG_3: 1200 case RT5663_VENDOR_ID: 1201 case RT5663_VENDOR_ID_1: 1202 case RT5663_VENDOR_ID_2: 1203 case RT5663_DACADC_DIG_VOL2: 1204 case RT5663_DIG_IN_PIN2: 1205 case RT5663_PAD_DRV_CTL1: 1206 case RT5663_SOF_RAM_DEPOP: 1207 case RT5663_VOL_TEST: 1208 case RT5663_TEST_MODE_4: 1209 case RT5663_TEST_MODE_5: 1210 case RT5663_STO_DRE_9: 1211 case RT5663_MONO_DYNA_1: 1212 case RT5663_MONO_DYNA_2: 1213 case RT5663_MONO_DYNA_3: 1214 case RT5663_MONO_DYNA_4: 1215 case RT5663_MONO_DYNA_5: 1216 case RT5663_MONO_DYNA_6: 1217 case RT5663_STO1_SIL_DET: 1218 case RT5663_MONOL_SIL_DET: 1219 case RT5663_MONOR_SIL_DET: 1220 case RT5663_STO2_DAC_SIL: 1221 case RT5663_PWR_SAV_CTL1: 1222 case RT5663_PWR_SAV_CTL2: 1223 case RT5663_PWR_SAV_CTL3: 1224 case RT5663_PWR_SAV_CTL4: 1225 case RT5663_PWR_SAV_CTL5: 1226 case RT5663_PWR_SAV_CTL6: 1227 case RT5663_MONO_AMP_CAL1: 1228 case RT5663_MONO_AMP_CAL2: 1229 case RT5663_MONO_AMP_CAL3: 1230 case RT5663_MONO_AMP_CAL4: 1231 case RT5663_MONO_AMP_CAL5: 1232 case RT5663_MONO_AMP_CAL6: 1233 case RT5663_MONO_AMP_CAL7: 1234 case RT5663_MONO_AMP_CAL_ST1: 1235 case RT5663_MONO_AMP_CAL_ST2: 1236 case RT5663_MONO_AMP_CAL_ST3: 1237 case RT5663_MONO_AMP_CAL_ST4: 1238 case RT5663_MONO_AMP_CAL_ST5: 1239 case RT5663_V2_HP_IMP_SEN_13: 1240 case RT5663_V2_HP_IMP_SEN_14: 1241 case RT5663_V2_HP_IMP_SEN_6: 1242 case RT5663_V2_HP_IMP_SEN_7: 1243 case RT5663_V2_HP_IMP_SEN_8: 1244 case RT5663_V2_HP_IMP_SEN_9: 1245 case RT5663_V2_HP_IMP_SEN_10: 1246 case RT5663_HP_LOGIC_3: 1247 case RT5663_HP_CALIB_ST10: 1248 case RT5663_HP_CALIB_ST11: 1249 case RT5663_PRO_REG_TBL_4: 1250 case RT5663_PRO_REG_TBL_5: 1251 case RT5663_PRO_REG_TBL_6: 1252 case RT5663_PRO_REG_TBL_7: 1253 case RT5663_PRO_REG_TBL_8: 1254 case RT5663_PRO_REG_TBL_9: 1255 case RT5663_SAR_ADC_INL_1: 1256 case RT5663_SAR_ADC_INL_2: 1257 case RT5663_SAR_ADC_INL_3: 1258 case RT5663_SAR_ADC_INL_4: 1259 case RT5663_SAR_ADC_INL_5: 1260 case RT5663_SAR_ADC_INL_6: 1261 case RT5663_SAR_ADC_INL_7: 1262 case RT5663_SAR_ADC_INL_8: 1263 case RT5663_SAR_ADC_INL_9: 1264 case RT5663_SAR_ADC_INL_10: 1265 case RT5663_SAR_ADC_INL_11: 1266 case RT5663_SAR_ADC_INL_12: 1267 case RT5663_DRC_CTRL_1: 1268 case RT5663_DRC1_CTRL_2: 1269 case RT5663_DRC1_CTRL_3: 1270 case RT5663_DRC1_CTRL_4: 1271 case RT5663_DRC1_CTRL_5: 1272 case RT5663_DRC1_CTRL_6: 1273 case RT5663_DRC1_HD_CTRL_1: 1274 case RT5663_DRC1_HD_CTRL_2: 1275 case RT5663_DRC1_PRI_REG_1: 1276 case RT5663_DRC1_PRI_REG_2: 1277 case RT5663_DRC1_PRI_REG_3: 1278 case RT5663_DRC1_PRI_REG_4: 1279 case RT5663_DRC1_PRI_REG_5: 1280 case RT5663_DRC1_PRI_REG_6: 1281 case RT5663_DRC1_PRI_REG_7: 1282 case RT5663_DRC1_PRI_REG_8: 1283 case RT5663_ALC_PGA_CTL_1: 1284 case RT5663_ALC_PGA_CTL_2: 1285 case RT5663_ALC_PGA_CTL_3: 1286 case RT5663_ALC_PGA_CTL_4: 1287 case RT5663_ALC_PGA_CTL_5: 1288 case RT5663_ALC_PGA_CTL_6: 1289 case RT5663_ALC_PGA_CTL_7: 1290 case RT5663_ALC_PGA_CTL_8: 1291 case RT5663_ALC_PGA_REG_1: 1292 case RT5663_ALC_PGA_REG_2: 1293 case RT5663_ALC_PGA_REG_3: 1294 case RT5663_ADC_EQ_RECOV_1: 1295 case RT5663_ADC_EQ_RECOV_2: 1296 case RT5663_ADC_EQ_RECOV_3: 1297 case RT5663_ADC_EQ_RECOV_4: 1298 case RT5663_ADC_EQ_RECOV_5: 1299 case RT5663_ADC_EQ_RECOV_6: 1300 case RT5663_ADC_EQ_RECOV_7: 1301 case RT5663_ADC_EQ_RECOV_8: 1302 case RT5663_ADC_EQ_RECOV_9: 1303 case RT5663_ADC_EQ_RECOV_10: 1304 case RT5663_ADC_EQ_RECOV_11: 1305 case RT5663_ADC_EQ_RECOV_12: 1306 case RT5663_ADC_EQ_RECOV_13: 1307 case RT5663_VID_HIDDEN: 1308 case RT5663_VID_CUSTOMER: 1309 case RT5663_SCAN_MODE: 1310 case RT5663_I2C_BYPA: 1311 return true; 1312 case RT5663_TDM_1: 1313 case RT5663_DEPOP_3: 1314 case RT5663_ASRC_11_2: 1315 case RT5663_INT_ST_2: 1316 case RT5663_GPIO_STA1: 1317 case RT5663_SIN_GEN_1: 1318 case RT5663_SIN_GEN_2: 1319 case RT5663_SIN_GEN_3: 1320 case RT5663_IL_CMD_PWRSAV1: 1321 case RT5663_IL_CMD_PWRSAV2: 1322 case RT5663_EM_JACK_TYPE_1: 1323 case RT5663_EM_JACK_TYPE_2: 1324 case RT5663_EM_JACK_TYPE_3: 1325 case RT5663_EM_JACK_TYPE_4: 1326 case RT5663_FAST_OFF_MICBIAS: 1327 case RT5663_ANA_BIAS_CUR_1: 1328 case RT5663_ANA_BIAS_CUR_2: 1329 case RT5663_BIAS_CUR_9: 1330 case RT5663_DUMMY_REG_4: 1331 case RT5663_VREF_RECMIX: 1332 case RT5663_CHARGE_PUMP_1_2: 1333 case RT5663_CHARGE_PUMP_1_3: 1334 case RT5663_CHARGE_PUMP_2: 1335 case RT5663_CHOP_DAC_R: 1336 case RT5663_DUMMY_CTL_DACLR: 1337 case RT5663_DUMMY_REG_5: 1338 case RT5663_SOFT_RAMP: 1339 case RT5663_TEST_MODE_1: 1340 case RT5663_STO_DRE_10: 1341 case RT5663_MIC_DECRO_1: 1342 case RT5663_MIC_DECRO_2: 1343 case RT5663_MIC_DECRO_3: 1344 case RT5663_MIC_DECRO_4: 1345 case RT5663_MIC_DECRO_5: 1346 case RT5663_MIC_DECRO_6: 1347 case RT5663_HP_DECRO_1: 1348 case RT5663_HP_DECRO_2: 1349 case RT5663_HP_DECRO_3: 1350 case RT5663_HP_DECRO_4: 1351 case RT5663_HP_DECOUP: 1352 case RT5663_HP_IMPSEN_MAP4: 1353 case RT5663_HP_IMPSEN_MAP5: 1354 case RT5663_HP_IMPSEN_MAP7: 1355 case RT5663_HP_CALIB_1: 1356 case RT5663_CBJ_1: 1357 case RT5663_CBJ_2: 1358 case RT5663_CBJ_3: 1359 return false; 1360 default: 1361 return rt5663_readable_register(dev, reg); 1362 } 1363 } 1364 1365 static const DECLARE_TLV_DB_SCALE(rt5663_hp_vol_tlv, -2400, 150, 0); 1366 static const DECLARE_TLV_DB_SCALE(rt5663_v2_hp_vol_tlv, -2250, 150, 0); 1367 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6525, 75, 0); 1368 static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0); 1369 1370 /* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */ 1371 static const DECLARE_TLV_DB_RANGE(in_bst_tlv, 1372 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0), 1373 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0), 1374 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0), 1375 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0), 1376 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0), 1377 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0), 1378 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0) 1379 ); 1380 1381 /* Interface data select */ 1382 static const char * const rt5663_if1_adc_data_select[] = { 1383 "L/R", "R/L", "L/L", "R/R" 1384 }; 1385 1386 static SOC_ENUM_SINGLE_DECL(rt5663_if1_adc_enum, RT5663_TDM_2, 1387 RT5663_DATA_SWAP_ADCDAT1_SHIFT, rt5663_if1_adc_data_select); 1388 1389 static void rt5663_enable_push_button_irq(struct snd_soc_component *component, 1390 bool enable) 1391 { 1392 struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component); 1393 1394 if (enable) { 1395 snd_soc_component_update_bits(component, RT5663_IL_CMD_6, 1396 RT5663_EN_4BTN_INL_MASK, RT5663_EN_4BTN_INL_EN); 1397 /* reset in-line command */ 1398 snd_soc_component_update_bits(component, RT5663_IL_CMD_6, 1399 RT5663_RESET_4BTN_INL_MASK, 1400 RT5663_RESET_4BTN_INL_RESET); 1401 snd_soc_component_update_bits(component, RT5663_IL_CMD_6, 1402 RT5663_RESET_4BTN_INL_MASK, 1403 RT5663_RESET_4BTN_INL_NOR); 1404 switch (rt5663->codec_ver) { 1405 case CODEC_VER_1: 1406 snd_soc_component_update_bits(component, RT5663_IRQ_3, 1407 RT5663_V2_EN_IRQ_INLINE_MASK, 1408 RT5663_V2_EN_IRQ_INLINE_NOR); 1409 break; 1410 case CODEC_VER_0: 1411 snd_soc_component_update_bits(component, RT5663_IRQ_2, 1412 RT5663_EN_IRQ_INLINE_MASK, 1413 RT5663_EN_IRQ_INLINE_NOR); 1414 break; 1415 default: 1416 dev_err(component->dev, "Unknown CODEC Version\n"); 1417 } 1418 } else { 1419 switch (rt5663->codec_ver) { 1420 case CODEC_VER_1: 1421 snd_soc_component_update_bits(component, RT5663_IRQ_3, 1422 RT5663_V2_EN_IRQ_INLINE_MASK, 1423 RT5663_V2_EN_IRQ_INLINE_BYP); 1424 break; 1425 case CODEC_VER_0: 1426 snd_soc_component_update_bits(component, RT5663_IRQ_2, 1427 RT5663_EN_IRQ_INLINE_MASK, 1428 RT5663_EN_IRQ_INLINE_BYP); 1429 break; 1430 default: 1431 dev_err(component->dev, "Unknown CODEC Version\n"); 1432 } 1433 snd_soc_component_update_bits(component, RT5663_IL_CMD_6, 1434 RT5663_EN_4BTN_INL_MASK, RT5663_EN_4BTN_INL_DIS); 1435 /* reset in-line command */ 1436 snd_soc_component_update_bits(component, RT5663_IL_CMD_6, 1437 RT5663_RESET_4BTN_INL_MASK, 1438 RT5663_RESET_4BTN_INL_RESET); 1439 snd_soc_component_update_bits(component, RT5663_IL_CMD_6, 1440 RT5663_RESET_4BTN_INL_MASK, 1441 RT5663_RESET_4BTN_INL_NOR); 1442 } 1443 } 1444 1445 /** 1446 * rt5663_v2_jack_detect - Detect headset. 1447 * @component: SoC audio component device. 1448 * @jack_insert: Jack insert or not. 1449 * 1450 * Detect whether is headset or not when jack inserted. 1451 * 1452 * Returns detect status. 1453 */ 1454 1455 static int rt5663_v2_jack_detect(struct snd_soc_component *component, int jack_insert) 1456 { 1457 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); 1458 struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component); 1459 int val, i = 0, sleep_time[5] = {300, 150, 100, 50, 30}; 1460 1461 dev_dbg(component->dev, "%s jack_insert:%d\n", __func__, jack_insert); 1462 if (jack_insert) { 1463 snd_soc_component_write(component, RT5663_CBJ_TYPE_2, 0x8040); 1464 snd_soc_component_write(component, RT5663_CBJ_TYPE_3, 0x1484); 1465 1466 snd_soc_dapm_force_enable_pin(dapm, "MICBIAS1"); 1467 snd_soc_dapm_force_enable_pin(dapm, "MICBIAS2"); 1468 snd_soc_dapm_force_enable_pin(dapm, "Mic Det Power"); 1469 snd_soc_dapm_force_enable_pin(dapm, "CBJ Power"); 1470 snd_soc_dapm_sync(dapm); 1471 snd_soc_component_update_bits(component, RT5663_RC_CLK, 1472 RT5663_DIG_1M_CLK_MASK, RT5663_DIG_1M_CLK_EN); 1473 snd_soc_component_update_bits(component, RT5663_RECMIX, 0x8, 0x8); 1474 1475 while (i < 5) { 1476 msleep(sleep_time[i]); 1477 val = snd_soc_component_read32(component, RT5663_CBJ_TYPE_2) & 0x0003; 1478 if (val == 0x1 || val == 0x2 || val == 0x3) 1479 break; 1480 dev_dbg(component->dev, "%s: MX-0011 val=%x sleep %d\n", 1481 __func__, val, sleep_time[i]); 1482 i++; 1483 } 1484 dev_dbg(component->dev, "%s val = %d\n", __func__, val); 1485 switch (val) { 1486 case 1: 1487 case 2: 1488 rt5663->jack_type = SND_JACK_HEADSET; 1489 rt5663_enable_push_button_irq(component, true); 1490 break; 1491 default: 1492 snd_soc_dapm_disable_pin(dapm, "MICBIAS1"); 1493 snd_soc_dapm_disable_pin(dapm, "MICBIAS2"); 1494 snd_soc_dapm_disable_pin(dapm, "Mic Det Power"); 1495 snd_soc_dapm_disable_pin(dapm, "CBJ Power"); 1496 snd_soc_dapm_sync(dapm); 1497 rt5663->jack_type = SND_JACK_HEADPHONE; 1498 break; 1499 } 1500 } else { 1501 snd_soc_component_update_bits(component, RT5663_RECMIX, 0x8, 0x0); 1502 1503 if (rt5663->jack_type == SND_JACK_HEADSET) { 1504 rt5663_enable_push_button_irq(component, false); 1505 snd_soc_dapm_disable_pin(dapm, "MICBIAS1"); 1506 snd_soc_dapm_disable_pin(dapm, "MICBIAS2"); 1507 snd_soc_dapm_disable_pin(dapm, "Mic Det Power"); 1508 snd_soc_dapm_disable_pin(dapm, "CBJ Power"); 1509 snd_soc_dapm_sync(dapm); 1510 } 1511 rt5663->jack_type = 0; 1512 } 1513 1514 dev_dbg(component->dev, "jack_type = %d\n", rt5663->jack_type); 1515 return rt5663->jack_type; 1516 } 1517 1518 /** 1519 * rt5663_jack_detect - Detect headset. 1520 * @component: SoC audio component device. 1521 * @jack_insert: Jack insert or not. 1522 * 1523 * Detect whether is headset or not when jack inserted. 1524 * 1525 * Returns detect status. 1526 */ 1527 static int rt5663_jack_detect(struct snd_soc_component *component, int jack_insert) 1528 { 1529 struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component); 1530 int val, i = 0; 1531 1532 dev_dbg(component->dev, "%s jack_insert:%d\n", __func__, jack_insert); 1533 1534 if (jack_insert) { 1535 snd_soc_component_update_bits(component, RT5663_DIG_MISC, 1536 RT5663_DIG_GATE_CTRL_MASK, RT5663_DIG_GATE_CTRL_EN); 1537 snd_soc_component_update_bits(component, RT5663_HP_CHARGE_PUMP_1, 1538 RT5663_SI_HP_MASK | RT5663_OSW_HP_L_MASK | 1539 RT5663_OSW_HP_R_MASK, RT5663_SI_HP_EN | 1540 RT5663_OSW_HP_L_DIS | RT5663_OSW_HP_R_DIS); 1541 snd_soc_component_update_bits(component, RT5663_DUMMY_1, 1542 RT5663_EMB_CLK_MASK | RT5663_HPA_CPL_BIAS_MASK | 1543 RT5663_HPA_CPR_BIAS_MASK, RT5663_EMB_CLK_EN | 1544 RT5663_HPA_CPL_BIAS_1 | RT5663_HPA_CPR_BIAS_1); 1545 snd_soc_component_update_bits(component, RT5663_CBJ_1, 1546 RT5663_INBUF_CBJ_BST1_MASK | RT5663_CBJ_SENSE_BST1_MASK, 1547 RT5663_INBUF_CBJ_BST1_ON | RT5663_CBJ_SENSE_BST1_L); 1548 snd_soc_component_update_bits(component, RT5663_IL_CMD_2, 1549 RT5663_PWR_MIC_DET_MASK, RT5663_PWR_MIC_DET_ON); 1550 /* BST1 power on for JD */ 1551 snd_soc_component_update_bits(component, RT5663_PWR_ANLG_2, 1552 RT5663_PWR_BST1_MASK, RT5663_PWR_BST1_ON); 1553 snd_soc_component_update_bits(component, RT5663_EM_JACK_TYPE_1, 1554 RT5663_CBJ_DET_MASK | RT5663_EXT_JD_MASK | 1555 RT5663_POL_EXT_JD_MASK, RT5663_CBJ_DET_EN | 1556 RT5663_EXT_JD_EN | RT5663_POL_EXT_JD_EN); 1557 snd_soc_component_update_bits(component, RT5663_PWR_ANLG_1, 1558 RT5663_PWR_MB_MASK | RT5663_LDO1_DVO_MASK | 1559 RT5663_AMP_HP_MASK, RT5663_PWR_MB | 1560 RT5663_LDO1_DVO_0_9V | RT5663_AMP_HP_3X); 1561 snd_soc_component_update_bits(component, RT5663_PWR_ANLG_1, 1562 RT5663_PWR_VREF1_MASK | RT5663_PWR_VREF2_MASK | 1563 RT5663_PWR_FV1_MASK | RT5663_PWR_FV2_MASK, 1564 RT5663_PWR_VREF1 | RT5663_PWR_VREF2); 1565 msleep(20); 1566 snd_soc_component_update_bits(component, RT5663_PWR_ANLG_1, 1567 RT5663_PWR_FV1_MASK | RT5663_PWR_FV2_MASK, 1568 RT5663_PWR_FV1 | RT5663_PWR_FV2); 1569 snd_soc_component_update_bits(component, RT5663_AUTO_1MRC_CLK, 1570 RT5663_IRQ_POW_SAV_MASK, RT5663_IRQ_POW_SAV_EN); 1571 snd_soc_component_update_bits(component, RT5663_IRQ_1, 1572 RT5663_EN_IRQ_JD1_MASK, RT5663_EN_IRQ_JD1_EN); 1573 snd_soc_component_update_bits(component, RT5663_EM_JACK_TYPE_1, 1574 RT5663_EM_JD_MASK, RT5663_EM_JD_RST); 1575 snd_soc_component_update_bits(component, RT5663_EM_JACK_TYPE_1, 1576 RT5663_EM_JD_MASK, RT5663_EM_JD_NOR); 1577 1578 while (true) { 1579 regmap_read(rt5663->regmap, RT5663_INT_ST_2, &val); 1580 if (!(val & 0x80)) 1581 usleep_range(10000, 10005); 1582 else 1583 break; 1584 1585 if (i > 200) 1586 break; 1587 i++; 1588 } 1589 1590 val = snd_soc_component_read32(component, RT5663_EM_JACK_TYPE_2) & 0x0003; 1591 dev_dbg(component->dev, "%s val = %d\n", __func__, val); 1592 1593 snd_soc_component_update_bits(component, RT5663_HP_CHARGE_PUMP_1, 1594 RT5663_OSW_HP_L_MASK | RT5663_OSW_HP_R_MASK, 1595 RT5663_OSW_HP_L_EN | RT5663_OSW_HP_R_EN); 1596 1597 switch (val) { 1598 case 1: 1599 case 2: 1600 rt5663->jack_type = SND_JACK_HEADSET; 1601 rt5663_enable_push_button_irq(component, true); 1602 1603 if (rt5663->pdata.impedance_sensing_num) 1604 break; 1605 1606 if (rt5663->pdata.dc_offset_l_manual_mic) { 1607 regmap_write(rt5663->regmap, RT5663_MIC_DECRO_2, 1608 rt5663->pdata.dc_offset_l_manual_mic >> 1609 16); 1610 regmap_write(rt5663->regmap, RT5663_MIC_DECRO_3, 1611 rt5663->pdata.dc_offset_l_manual_mic & 1612 0xffff); 1613 } 1614 1615 if (rt5663->pdata.dc_offset_r_manual_mic) { 1616 regmap_write(rt5663->regmap, RT5663_MIC_DECRO_5, 1617 rt5663->pdata.dc_offset_r_manual_mic >> 1618 16); 1619 regmap_write(rt5663->regmap, RT5663_MIC_DECRO_6, 1620 rt5663->pdata.dc_offset_r_manual_mic & 1621 0xffff); 1622 } 1623 break; 1624 default: 1625 rt5663->jack_type = SND_JACK_HEADPHONE; 1626 snd_soc_component_update_bits(component, 1627 RT5663_PWR_ANLG_1, 1628 RT5663_PWR_MB_MASK | RT5663_PWR_VREF1_MASK | 1629 RT5663_PWR_VREF2_MASK, 0); 1630 if (rt5663->pdata.impedance_sensing_num) 1631 break; 1632 1633 if (rt5663->pdata.dc_offset_l_manual) { 1634 regmap_write(rt5663->regmap, RT5663_MIC_DECRO_2, 1635 rt5663->pdata.dc_offset_l_manual >> 16); 1636 regmap_write(rt5663->regmap, RT5663_MIC_DECRO_3, 1637 rt5663->pdata.dc_offset_l_manual & 1638 0xffff); 1639 } 1640 1641 if (rt5663->pdata.dc_offset_r_manual) { 1642 regmap_write(rt5663->regmap, RT5663_MIC_DECRO_5, 1643 rt5663->pdata.dc_offset_r_manual >> 16); 1644 regmap_write(rt5663->regmap, RT5663_MIC_DECRO_6, 1645 rt5663->pdata.dc_offset_r_manual & 1646 0xffff); 1647 } 1648 break; 1649 } 1650 } else { 1651 if (rt5663->jack_type == SND_JACK_HEADSET) 1652 rt5663_enable_push_button_irq(component, false); 1653 rt5663->jack_type = 0; 1654 snd_soc_component_update_bits(component, RT5663_PWR_ANLG_1, 1655 RT5663_PWR_MB_MASK | RT5663_PWR_VREF1_MASK | 1656 RT5663_PWR_VREF2_MASK, 0); 1657 } 1658 1659 dev_dbg(component->dev, "jack_type = %d\n", rt5663->jack_type); 1660 return rt5663->jack_type; 1661 } 1662 1663 static int rt5663_impedance_sensing(struct snd_soc_component *component) 1664 { 1665 struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component); 1666 unsigned int value, i, reg84, reg26, reg2fa, reg91, reg10, reg80; 1667 1668 for (i = 0; i < rt5663->pdata.impedance_sensing_num; i++) { 1669 if (rt5663->imp_table[i].vol == 7) 1670 break; 1671 } 1672 1673 if (rt5663->jack_type == SND_JACK_HEADSET) { 1674 snd_soc_component_write(component, RT5663_MIC_DECRO_2, 1675 rt5663->imp_table[i].dc_offset_l_manual_mic >> 16); 1676 snd_soc_component_write(component, RT5663_MIC_DECRO_3, 1677 rt5663->imp_table[i].dc_offset_l_manual_mic & 0xffff); 1678 snd_soc_component_write(component, RT5663_MIC_DECRO_5, 1679 rt5663->imp_table[i].dc_offset_r_manual_mic >> 16); 1680 snd_soc_component_write(component, RT5663_MIC_DECRO_6, 1681 rt5663->imp_table[i].dc_offset_r_manual_mic & 0xffff); 1682 } else { 1683 snd_soc_component_write(component, RT5663_MIC_DECRO_2, 1684 rt5663->imp_table[i].dc_offset_l_manual >> 16); 1685 snd_soc_component_write(component, RT5663_MIC_DECRO_3, 1686 rt5663->imp_table[i].dc_offset_l_manual & 0xffff); 1687 snd_soc_component_write(component, RT5663_MIC_DECRO_5, 1688 rt5663->imp_table[i].dc_offset_r_manual >> 16); 1689 snd_soc_component_write(component, RT5663_MIC_DECRO_6, 1690 rt5663->imp_table[i].dc_offset_r_manual & 0xffff); 1691 } 1692 1693 reg84 = snd_soc_component_read32(component, RT5663_ASRC_2); 1694 reg26 = snd_soc_component_read32(component, RT5663_STO1_ADC_MIXER); 1695 reg2fa = snd_soc_component_read32(component, RT5663_DUMMY_1); 1696 reg91 = snd_soc_component_read32(component, RT5663_HP_CHARGE_PUMP_1); 1697 reg10 = snd_soc_component_read32(component, RT5663_RECMIX); 1698 reg80 = snd_soc_component_read32(component, RT5663_GLB_CLK); 1699 1700 snd_soc_component_update_bits(component, RT5663_STO_DRE_1, 0x8000, 0); 1701 snd_soc_component_write(component, RT5663_ASRC_2, 0); 1702 snd_soc_component_write(component, RT5663_STO1_ADC_MIXER, 0x4040); 1703 snd_soc_component_update_bits(component, RT5663_PWR_ANLG_1, 1704 RT5663_PWR_VREF1_MASK | RT5663_PWR_VREF2_MASK | 1705 RT5663_PWR_FV1_MASK | RT5663_PWR_FV2_MASK, 1706 RT5663_PWR_VREF1 | RT5663_PWR_VREF2); 1707 usleep_range(10000, 10005); 1708 snd_soc_component_update_bits(component, RT5663_PWR_ANLG_1, 1709 RT5663_PWR_FV1_MASK | RT5663_PWR_FV2_MASK, 1710 RT5663_PWR_FV1 | RT5663_PWR_FV2); 1711 snd_soc_component_update_bits(component, RT5663_GLB_CLK, RT5663_SCLK_SRC_MASK, 1712 RT5663_SCLK_SRC_RCCLK); 1713 snd_soc_component_update_bits(component, RT5663_RC_CLK, RT5663_DIG_25M_CLK_MASK, 1714 RT5663_DIG_25M_CLK_EN); 1715 snd_soc_component_update_bits(component, RT5663_ADDA_CLK_1, RT5663_I2S_PD1_MASK, 0); 1716 snd_soc_component_write(component, RT5663_PRE_DIV_GATING_1, 0xff00); 1717 snd_soc_component_write(component, RT5663_PRE_DIV_GATING_2, 0xfffc); 1718 snd_soc_component_write(component, RT5663_HP_CHARGE_PUMP_1, 0x1232); 1719 snd_soc_component_write(component, RT5663_HP_LOGIC_2, 0x0005); 1720 snd_soc_component_write(component, RT5663_DEPOP_2, 0x3003); 1721 snd_soc_component_update_bits(component, RT5663_DEPOP_1, 0x0030, 0x0030); 1722 snd_soc_component_update_bits(component, RT5663_DEPOP_1, 0x0003, 0x0003); 1723 snd_soc_component_update_bits(component, RT5663_PWR_DIG_2, 1724 RT5663_PWR_ADC_S1F | RT5663_PWR_DAC_S1F, 1725 RT5663_PWR_ADC_S1F | RT5663_PWR_DAC_S1F); 1726 snd_soc_component_update_bits(component, RT5663_PWR_DIG_1, 1727 RT5663_PWR_DAC_L1 | RT5663_PWR_DAC_R1 | 1728 RT5663_PWR_LDO_DACREF_MASK | RT5663_PWR_ADC_L1 | 1729 RT5663_PWR_ADC_R1, 1730 RT5663_PWR_DAC_L1 | RT5663_PWR_DAC_R1 | 1731 RT5663_PWR_LDO_DACREF_ON | RT5663_PWR_ADC_L1 | 1732 RT5663_PWR_ADC_R1); 1733 msleep(40); 1734 snd_soc_component_update_bits(component, RT5663_PWR_ANLG_2, 1735 RT5663_PWR_RECMIX1 | RT5663_PWR_RECMIX2, 1736 RT5663_PWR_RECMIX1 | RT5663_PWR_RECMIX2); 1737 msleep(30); 1738 snd_soc_component_write(component, RT5663_HP_CHARGE_PUMP_2, 0x1371); 1739 snd_soc_component_write(component, RT5663_STO_DAC_MIXER, 0); 1740 snd_soc_component_write(component, RT5663_BYPASS_STO_DAC, 0x000c); 1741 snd_soc_component_write(component, RT5663_HP_BIAS, 0xafaa); 1742 snd_soc_component_write(component, RT5663_CHARGE_PUMP_1, 0x2224); 1743 snd_soc_component_write(component, RT5663_HP_OUT_EN, 0x8088); 1744 snd_soc_component_write(component, RT5663_CHOP_ADC, 0x3000); 1745 snd_soc_component_write(component, RT5663_ADDA_RST, 0xc000); 1746 snd_soc_component_write(component, RT5663_STO1_HPF_ADJ1, 0x3320); 1747 snd_soc_component_write(component, RT5663_HP_CALIB_2, 0x00c9); 1748 snd_soc_component_write(component, RT5663_DUMMY_1, 0x004c); 1749 snd_soc_component_write(component, RT5663_ANA_BIAS_CUR_1, 0x7733); 1750 snd_soc_component_write(component, RT5663_CHARGE_PUMP_2, 0x7777); 1751 snd_soc_component_write(component, RT5663_STO_DRE_9, 0x0007); 1752 snd_soc_component_write(component, RT5663_STO_DRE_10, 0x0007); 1753 snd_soc_component_write(component, RT5663_DUMMY_2, 0x02a4); 1754 snd_soc_component_write(component, RT5663_RECMIX, 0x0005); 1755 snd_soc_component_write(component, RT5663_HP_IMP_SEN_1, 0x4334); 1756 snd_soc_component_update_bits(component, RT5663_IRQ_3, 0x0004, 0x0004); 1757 snd_soc_component_write(component, RT5663_HP_LOGIC_1, 0x2200); 1758 snd_soc_component_update_bits(component, RT5663_DEPOP_1, 0x3000, 0x3000); 1759 snd_soc_component_write(component, RT5663_HP_LOGIC_1, 0x6200); 1760 1761 for (i = 0; i < 100; i++) { 1762 msleep(20); 1763 if (snd_soc_component_read32(component, RT5663_INT_ST_1) & 0x2) 1764 break; 1765 } 1766 1767 value = snd_soc_component_read32(component, RT5663_HP_IMP_SEN_4); 1768 1769 snd_soc_component_update_bits(component, RT5663_DEPOP_1, 0x3000, 0); 1770 snd_soc_component_write(component, RT5663_INT_ST_1, 0); 1771 snd_soc_component_write(component, RT5663_HP_LOGIC_1, 0); 1772 snd_soc_component_update_bits(component, RT5663_RC_CLK, RT5663_DIG_25M_CLK_MASK, 1773 RT5663_DIG_25M_CLK_DIS); 1774 snd_soc_component_write(component, RT5663_GLB_CLK, reg80); 1775 snd_soc_component_write(component, RT5663_RECMIX, reg10); 1776 snd_soc_component_write(component, RT5663_DUMMY_2, 0x00a4); 1777 snd_soc_component_write(component, RT5663_DUMMY_1, reg2fa); 1778 snd_soc_component_write(component, RT5663_HP_CALIB_2, 0x00c8); 1779 snd_soc_component_write(component, RT5663_STO1_HPF_ADJ1, 0xb320); 1780 snd_soc_component_write(component, RT5663_ADDA_RST, 0xe400); 1781 snd_soc_component_write(component, RT5663_CHOP_ADC, 0x2000); 1782 snd_soc_component_write(component, RT5663_HP_OUT_EN, 0x0008); 1783 snd_soc_component_update_bits(component, RT5663_PWR_ANLG_2, 1784 RT5663_PWR_RECMIX1 | RT5663_PWR_RECMIX2, 0); 1785 snd_soc_component_update_bits(component, RT5663_PWR_DIG_1, 1786 RT5663_PWR_DAC_L1 | RT5663_PWR_DAC_R1 | 1787 RT5663_PWR_LDO_DACREF_MASK | RT5663_PWR_ADC_L1 | 1788 RT5663_PWR_ADC_R1, 0); 1789 snd_soc_component_update_bits(component, RT5663_PWR_DIG_2, 1790 RT5663_PWR_ADC_S1F | RT5663_PWR_DAC_S1F, 0); 1791 snd_soc_component_update_bits(component, RT5663_DEPOP_1, 0x0003, 0); 1792 snd_soc_component_update_bits(component, RT5663_DEPOP_1, 0x0030, 0); 1793 snd_soc_component_write(component, RT5663_HP_LOGIC_2, 0); 1794 snd_soc_component_write(component, RT5663_HP_CHARGE_PUMP_1, reg91); 1795 snd_soc_component_update_bits(component, RT5663_PWR_ANLG_1, 1796 RT5663_PWR_VREF1_MASK | RT5663_PWR_VREF2_MASK, 0); 1797 snd_soc_component_write(component, RT5663_STO1_ADC_MIXER, reg26); 1798 snd_soc_component_write(component, RT5663_ASRC_2, reg84); 1799 1800 for (i = 0; i < rt5663->pdata.impedance_sensing_num; i++) { 1801 if (value >= rt5663->imp_table[i].imp_min && 1802 value <= rt5663->imp_table[i].imp_max) 1803 break; 1804 } 1805 1806 snd_soc_component_update_bits(component, RT5663_STO_DRE_9, RT5663_DRE_GAIN_HP_MASK, 1807 rt5663->imp_table[i].vol); 1808 snd_soc_component_update_bits(component, RT5663_STO_DRE_10, RT5663_DRE_GAIN_HP_MASK, 1809 rt5663->imp_table[i].vol); 1810 1811 if (rt5663->jack_type == SND_JACK_HEADSET) { 1812 snd_soc_component_write(component, RT5663_MIC_DECRO_2, 1813 rt5663->imp_table[i].dc_offset_l_manual_mic >> 16); 1814 snd_soc_component_write(component, RT5663_MIC_DECRO_3, 1815 rt5663->imp_table[i].dc_offset_l_manual_mic & 0xffff); 1816 snd_soc_component_write(component, RT5663_MIC_DECRO_5, 1817 rt5663->imp_table[i].dc_offset_r_manual_mic >> 16); 1818 snd_soc_component_write(component, RT5663_MIC_DECRO_6, 1819 rt5663->imp_table[i].dc_offset_r_manual_mic & 0xffff); 1820 } else { 1821 snd_soc_component_write(component, RT5663_MIC_DECRO_2, 1822 rt5663->imp_table[i].dc_offset_l_manual >> 16); 1823 snd_soc_component_write(component, RT5663_MIC_DECRO_3, 1824 rt5663->imp_table[i].dc_offset_l_manual & 0xffff); 1825 snd_soc_component_write(component, RT5663_MIC_DECRO_5, 1826 rt5663->imp_table[i].dc_offset_r_manual >> 16); 1827 snd_soc_component_write(component, RT5663_MIC_DECRO_6, 1828 rt5663->imp_table[i].dc_offset_r_manual & 0xffff); 1829 } 1830 1831 return 0; 1832 } 1833 1834 static int rt5663_button_detect(struct snd_soc_component *component) 1835 { 1836 int btn_type, val; 1837 1838 val = snd_soc_component_read32(component, RT5663_IL_CMD_5); 1839 dev_dbg(component->dev, "%s: val=0x%x\n", __func__, val); 1840 btn_type = val & 0xfff0; 1841 snd_soc_component_write(component, RT5663_IL_CMD_5, val); 1842 1843 return btn_type; 1844 } 1845 1846 static irqreturn_t rt5663_irq(int irq, void *data) 1847 { 1848 struct rt5663_priv *rt5663 = data; 1849 1850 dev_dbg(regmap_get_device(rt5663->regmap), "%s IRQ queue work\n", 1851 __func__); 1852 1853 queue_delayed_work(system_wq, &rt5663->jack_detect_work, 1854 msecs_to_jiffies(250)); 1855 1856 return IRQ_HANDLED; 1857 } 1858 1859 static int rt5663_set_jack_detect(struct snd_soc_component *component, 1860 struct snd_soc_jack *hs_jack, void *data) 1861 { 1862 struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component); 1863 1864 rt5663->hs_jack = hs_jack; 1865 1866 rt5663_irq(0, rt5663); 1867 1868 return 0; 1869 } 1870 1871 static bool rt5663_check_jd_status(struct snd_soc_component *component) 1872 { 1873 struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component); 1874 int val = snd_soc_component_read32(component, RT5663_INT_ST_1); 1875 1876 dev_dbg(component->dev, "%s val=%x\n", __func__, val); 1877 1878 /* JD1 */ 1879 switch (rt5663->codec_ver) { 1880 case CODEC_VER_1: 1881 return !(val & 0x2000); 1882 case CODEC_VER_0: 1883 return !(val & 0x1000); 1884 default: 1885 dev_err(component->dev, "Unknown CODEC Version\n"); 1886 } 1887 1888 return false; 1889 } 1890 1891 static void rt5663_jack_detect_work(struct work_struct *work) 1892 { 1893 struct rt5663_priv *rt5663 = 1894 container_of(work, struct rt5663_priv, jack_detect_work.work); 1895 struct snd_soc_component *component = rt5663->component; 1896 int btn_type, report = 0; 1897 1898 if (!component) 1899 return; 1900 1901 if (rt5663_check_jd_status(component)) { 1902 /* jack in */ 1903 if (rt5663->jack_type == 0) { 1904 /* jack was out, report jack type */ 1905 switch (rt5663->codec_ver) { 1906 case CODEC_VER_1: 1907 report = rt5663_v2_jack_detect( 1908 rt5663->component, 1); 1909 break; 1910 case CODEC_VER_0: 1911 report = rt5663_jack_detect(rt5663->component, 1); 1912 if (rt5663->pdata.impedance_sensing_num) 1913 rt5663_impedance_sensing(rt5663->component); 1914 break; 1915 default: 1916 dev_err(component->dev, "Unknown CODEC Version\n"); 1917 } 1918 1919 /* Delay the jack insert report to avoid pop noise */ 1920 msleep(30); 1921 } else { 1922 /* jack is already in, report button event */ 1923 report = SND_JACK_HEADSET; 1924 btn_type = rt5663_button_detect(rt5663->component); 1925 /** 1926 * rt5663 can report three kinds of button behavior, 1927 * one click, double click and hold. However, 1928 * currently we will report button pressed/released 1929 * event. So all the three button behaviors are 1930 * treated as button pressed. 1931 */ 1932 switch (btn_type) { 1933 case 0x8000: 1934 case 0x4000: 1935 case 0x2000: 1936 report |= SND_JACK_BTN_0; 1937 break; 1938 case 0x1000: 1939 case 0x0800: 1940 case 0x0400: 1941 report |= SND_JACK_BTN_1; 1942 break; 1943 case 0x0200: 1944 case 0x0100: 1945 case 0x0080: 1946 report |= SND_JACK_BTN_2; 1947 break; 1948 case 0x0040: 1949 case 0x0020: 1950 case 0x0010: 1951 report |= SND_JACK_BTN_3; 1952 break; 1953 case 0x0000: /* unpressed */ 1954 break; 1955 default: 1956 btn_type = 0; 1957 dev_err(rt5663->component->dev, 1958 "Unexpected button code 0x%04x\n", 1959 btn_type); 1960 break; 1961 } 1962 /* button release or spurious interrput*/ 1963 if (btn_type == 0) { 1964 report = rt5663->jack_type; 1965 cancel_delayed_work_sync( 1966 &rt5663->jd_unplug_work); 1967 } else { 1968 queue_delayed_work(system_wq, 1969 &rt5663->jd_unplug_work, 1970 msecs_to_jiffies(500)); 1971 } 1972 } 1973 } else { 1974 /* jack out */ 1975 switch (rt5663->codec_ver) { 1976 case CODEC_VER_1: 1977 report = rt5663_v2_jack_detect(rt5663->component, 0); 1978 break; 1979 case CODEC_VER_0: 1980 report = rt5663_jack_detect(rt5663->component, 0); 1981 break; 1982 default: 1983 dev_err(component->dev, "Unknown CODEC Version\n"); 1984 } 1985 } 1986 dev_dbg(component->dev, "%s jack report: 0x%04x\n", __func__, report); 1987 snd_soc_jack_report(rt5663->hs_jack, report, SND_JACK_HEADSET | 1988 SND_JACK_BTN_0 | SND_JACK_BTN_1 | 1989 SND_JACK_BTN_2 | SND_JACK_BTN_3); 1990 } 1991 1992 static void rt5663_jd_unplug_work(struct work_struct *work) 1993 { 1994 struct rt5663_priv *rt5663 = 1995 container_of(work, struct rt5663_priv, jd_unplug_work.work); 1996 struct snd_soc_component *component = rt5663->component; 1997 1998 if (!component) 1999 return; 2000 2001 if (!rt5663_check_jd_status(component)) { 2002 /* jack out */ 2003 switch (rt5663->codec_ver) { 2004 case CODEC_VER_1: 2005 rt5663_v2_jack_detect(rt5663->component, 0); 2006 break; 2007 case CODEC_VER_0: 2008 rt5663_jack_detect(rt5663->component, 0); 2009 break; 2010 default: 2011 dev_err(component->dev, "Unknown CODEC Version\n"); 2012 } 2013 2014 snd_soc_jack_report(rt5663->hs_jack, 0, SND_JACK_HEADSET | 2015 SND_JACK_BTN_0 | SND_JACK_BTN_1 | 2016 SND_JACK_BTN_2 | SND_JACK_BTN_3); 2017 } else { 2018 queue_delayed_work(system_wq, &rt5663->jd_unplug_work, 2019 msecs_to_jiffies(500)); 2020 } 2021 } 2022 2023 static const struct snd_kcontrol_new rt5663_snd_controls[] = { 2024 /* DAC Digital Volume */ 2025 SOC_DOUBLE_TLV("DAC Playback Volume", RT5663_STO1_DAC_DIG_VOL, 2026 RT5663_DAC_L1_VOL_SHIFT + 1, RT5663_DAC_R1_VOL_SHIFT + 1, 2027 87, 0, dac_vol_tlv), 2028 /* ADC Digital Volume Control */ 2029 SOC_DOUBLE("ADC Capture Switch", RT5663_STO1_ADC_DIG_VOL, 2030 RT5663_ADC_L_MUTE_SHIFT, RT5663_ADC_R_MUTE_SHIFT, 1, 1), 2031 SOC_DOUBLE_TLV("ADC Capture Volume", RT5663_STO1_ADC_DIG_VOL, 2032 RT5663_ADC_L_VOL_SHIFT + 1, RT5663_ADC_R_VOL_SHIFT + 1, 2033 63, 0, adc_vol_tlv), 2034 }; 2035 2036 static const struct snd_kcontrol_new rt5663_v2_specific_controls[] = { 2037 /* Headphone Output Volume */ 2038 SOC_DOUBLE_R_TLV("Headphone Playback Volume", RT5663_HP_LCH_DRE, 2039 RT5663_HP_RCH_DRE, RT5663_GAIN_HP_SHIFT, 15, 1, 2040 rt5663_v2_hp_vol_tlv), 2041 /* Mic Boost Volume */ 2042 SOC_SINGLE_TLV("IN1 Capture Volume", RT5663_AEC_BST, 2043 RT5663_GAIN_CBJ_SHIFT, 8, 0, in_bst_tlv), 2044 }; 2045 2046 static const struct snd_kcontrol_new rt5663_specific_controls[] = { 2047 /* Mic Boost Volume*/ 2048 SOC_SINGLE_TLV("IN1 Capture Volume", RT5663_CBJ_2, 2049 RT5663_GAIN_BST1_SHIFT, 8, 0, in_bst_tlv), 2050 /* Data Swap for Slot0/1 in ADCDAT1 */ 2051 SOC_ENUM("IF1 ADC Data Swap", rt5663_if1_adc_enum), 2052 }; 2053 2054 static const struct snd_kcontrol_new rt5663_hpvol_controls[] = { 2055 /* Headphone Output Volume */ 2056 SOC_DOUBLE_R_TLV("Headphone Playback Volume", RT5663_STO_DRE_9, 2057 RT5663_STO_DRE_10, RT5663_DRE_GAIN_HP_SHIFT, 23, 1, 2058 rt5663_hp_vol_tlv), 2059 }; 2060 2061 static int rt5663_is_sys_clk_from_pll(struct snd_soc_dapm_widget *w, 2062 struct snd_soc_dapm_widget *sink) 2063 { 2064 unsigned int val; 2065 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 2066 2067 val = snd_soc_component_read32(component, RT5663_GLB_CLK); 2068 val &= RT5663_SCLK_SRC_MASK; 2069 if (val == RT5663_SCLK_SRC_PLL1) 2070 return 1; 2071 else 2072 return 0; 2073 } 2074 2075 static int rt5663_is_using_asrc(struct snd_soc_dapm_widget *w, 2076 struct snd_soc_dapm_widget *sink) 2077 { 2078 unsigned int reg, shift, val; 2079 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 2080 struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component); 2081 2082 if (rt5663->codec_ver == CODEC_VER_1) { 2083 switch (w->shift) { 2084 case RT5663_ADC_STO1_ASRC_SHIFT: 2085 reg = RT5663_ASRC_3; 2086 shift = RT5663_V2_AD_STO1_TRACK_SHIFT; 2087 break; 2088 case RT5663_DAC_STO1_ASRC_SHIFT: 2089 reg = RT5663_ASRC_2; 2090 shift = RT5663_DA_STO1_TRACK_SHIFT; 2091 break; 2092 default: 2093 return 0; 2094 } 2095 } else { 2096 switch (w->shift) { 2097 case RT5663_ADC_STO1_ASRC_SHIFT: 2098 reg = RT5663_ASRC_2; 2099 shift = RT5663_AD_STO1_TRACK_SHIFT; 2100 break; 2101 case RT5663_DAC_STO1_ASRC_SHIFT: 2102 reg = RT5663_ASRC_2; 2103 shift = RT5663_DA_STO1_TRACK_SHIFT; 2104 break; 2105 default: 2106 return 0; 2107 } 2108 } 2109 2110 val = (snd_soc_component_read32(component, reg) >> shift) & 0x7; 2111 2112 if (val) 2113 return 1; 2114 2115 return 0; 2116 } 2117 2118 static int rt5663_i2s_use_asrc(struct snd_soc_dapm_widget *source, 2119 struct snd_soc_dapm_widget *sink) 2120 { 2121 struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm); 2122 struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component); 2123 int da_asrc_en, ad_asrc_en; 2124 2125 da_asrc_en = (snd_soc_component_read32(component, RT5663_ASRC_2) & 2126 RT5663_DA_STO1_TRACK_MASK) ? 1 : 0; 2127 switch (rt5663->codec_ver) { 2128 case CODEC_VER_1: 2129 ad_asrc_en = (snd_soc_component_read32(component, RT5663_ASRC_3) & 2130 RT5663_V2_AD_STO1_TRACK_MASK) ? 1 : 0; 2131 break; 2132 case CODEC_VER_0: 2133 ad_asrc_en = (snd_soc_component_read32(component, RT5663_ASRC_2) & 2134 RT5663_AD_STO1_TRACK_MASK) ? 1 : 0; 2135 break; 2136 default: 2137 dev_err(component->dev, "Unknown CODEC Version\n"); 2138 return 1; 2139 } 2140 2141 if (da_asrc_en || ad_asrc_en) 2142 if (rt5663->sysclk > rt5663->lrck * 384) 2143 return 1; 2144 2145 dev_err(component->dev, "sysclk < 384 x fs, disable i2s asrc\n"); 2146 2147 return 0; 2148 } 2149 2150 /** 2151 * rt5663_sel_asrc_clk_src - select ASRC clock source for a set of filters 2152 * @component: SoC audio component device. 2153 * @filter_mask: mask of filters. 2154 * @clk_src: clock source 2155 * 2156 * The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5663 can 2157 * only support standard 32fs or 64fs i2s format, ASRC should be enabled to 2158 * support special i2s clock format such as Intel's 100fs(100 * sampling rate). 2159 * ASRC function will track i2s clock and generate a corresponding system clock 2160 * for codec. This function provides an API to select the clock source for a 2161 * set of filters specified by the mask. And the codec driver will turn on ASRC 2162 * for these filters if ASRC is selected as their clock source. 2163 */ 2164 int rt5663_sel_asrc_clk_src(struct snd_soc_component *component, 2165 unsigned int filter_mask, unsigned int clk_src) 2166 { 2167 struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component); 2168 unsigned int asrc2_mask = 0; 2169 unsigned int asrc2_value = 0; 2170 unsigned int asrc3_mask = 0; 2171 unsigned int asrc3_value = 0; 2172 2173 switch (clk_src) { 2174 case RT5663_CLK_SEL_SYS: 2175 case RT5663_CLK_SEL_I2S1_ASRC: 2176 break; 2177 2178 default: 2179 return -EINVAL; 2180 } 2181 2182 if (filter_mask & RT5663_DA_STEREO_FILTER) { 2183 asrc2_mask |= RT5663_DA_STO1_TRACK_MASK; 2184 asrc2_value |= clk_src << RT5663_DA_STO1_TRACK_SHIFT; 2185 } 2186 2187 if (filter_mask & RT5663_AD_STEREO_FILTER) { 2188 switch (rt5663->codec_ver) { 2189 case CODEC_VER_1: 2190 asrc3_mask |= RT5663_V2_AD_STO1_TRACK_MASK; 2191 asrc3_value |= clk_src << RT5663_V2_AD_STO1_TRACK_SHIFT; 2192 break; 2193 case CODEC_VER_0: 2194 asrc2_mask |= RT5663_AD_STO1_TRACK_MASK; 2195 asrc2_value |= clk_src << RT5663_AD_STO1_TRACK_SHIFT; 2196 break; 2197 default: 2198 dev_err(component->dev, "Unknown CODEC Version\n"); 2199 } 2200 } 2201 2202 if (asrc2_mask) 2203 snd_soc_component_update_bits(component, RT5663_ASRC_2, asrc2_mask, 2204 asrc2_value); 2205 2206 if (asrc3_mask) 2207 snd_soc_component_update_bits(component, RT5663_ASRC_3, asrc3_mask, 2208 asrc3_value); 2209 2210 return 0; 2211 } 2212 EXPORT_SYMBOL_GPL(rt5663_sel_asrc_clk_src); 2213 2214 /* Analog Mixer */ 2215 static const struct snd_kcontrol_new rt5663_recmix1l[] = { 2216 SOC_DAPM_SINGLE("BST2 Switch", RT5663_RECMIX1L, 2217 RT5663_RECMIX1L_BST2_SHIFT, 1, 1), 2218 SOC_DAPM_SINGLE("BST1 CBJ Switch", RT5663_RECMIX1L, 2219 RT5663_RECMIX1L_BST1_CBJ_SHIFT, 1, 1), 2220 }; 2221 2222 static const struct snd_kcontrol_new rt5663_recmix1r[] = { 2223 SOC_DAPM_SINGLE("BST2 Switch", RT5663_RECMIX1R, 2224 RT5663_RECMIX1R_BST2_SHIFT, 1, 1), 2225 }; 2226 2227 /* Digital Mixer */ 2228 static const struct snd_kcontrol_new rt5663_sto1_adc_l_mix[] = { 2229 SOC_DAPM_SINGLE("ADC1 Switch", RT5663_STO1_ADC_MIXER, 2230 RT5663_M_STO1_ADC_L1_SHIFT, 1, 1), 2231 SOC_DAPM_SINGLE("ADC2 Switch", RT5663_STO1_ADC_MIXER, 2232 RT5663_M_STO1_ADC_L2_SHIFT, 1, 1), 2233 }; 2234 2235 static const struct snd_kcontrol_new rt5663_sto1_adc_r_mix[] = { 2236 SOC_DAPM_SINGLE("ADC1 Switch", RT5663_STO1_ADC_MIXER, 2237 RT5663_M_STO1_ADC_R1_SHIFT, 1, 1), 2238 SOC_DAPM_SINGLE("ADC2 Switch", RT5663_STO1_ADC_MIXER, 2239 RT5663_M_STO1_ADC_R2_SHIFT, 1, 1), 2240 }; 2241 2242 static const struct snd_kcontrol_new rt5663_adda_l_mix[] = { 2243 SOC_DAPM_SINGLE("ADC L Switch", RT5663_AD_DA_MIXER, 2244 RT5663_M_ADCMIX_L_SHIFT, 1, 1), 2245 SOC_DAPM_SINGLE("DAC L Switch", RT5663_AD_DA_MIXER, 2246 RT5663_M_DAC1_L_SHIFT, 1, 1), 2247 }; 2248 2249 static const struct snd_kcontrol_new rt5663_adda_r_mix[] = { 2250 SOC_DAPM_SINGLE("ADC R Switch", RT5663_AD_DA_MIXER, 2251 RT5663_M_ADCMIX_R_SHIFT, 1, 1), 2252 SOC_DAPM_SINGLE("DAC R Switch", RT5663_AD_DA_MIXER, 2253 RT5663_M_DAC1_R_SHIFT, 1, 1), 2254 }; 2255 2256 static const struct snd_kcontrol_new rt5663_sto1_dac_l_mix[] = { 2257 SOC_DAPM_SINGLE("DAC L Switch", RT5663_STO_DAC_MIXER, 2258 RT5663_M_DAC_L1_STO_L_SHIFT, 1, 1), 2259 }; 2260 2261 static const struct snd_kcontrol_new rt5663_sto1_dac_r_mix[] = { 2262 SOC_DAPM_SINGLE("DAC R Switch", RT5663_STO_DAC_MIXER, 2263 RT5663_M_DAC_R1_STO_R_SHIFT, 1, 1), 2264 }; 2265 2266 /* Out Switch */ 2267 static const struct snd_kcontrol_new rt5663_hpo_switch = 2268 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5663_HP_AMP_2, 2269 RT5663_EN_DAC_HPO_SHIFT, 1, 0); 2270 2271 /* Stereo ADC source */ 2272 static const char * const rt5663_sto1_adc_src[] = { 2273 "ADC L", "ADC R" 2274 }; 2275 2276 static SOC_ENUM_SINGLE_DECL(rt5663_sto1_adcl_enum, RT5663_STO1_ADC_MIXER, 2277 RT5663_STO1_ADC_L_SRC_SHIFT, rt5663_sto1_adc_src); 2278 2279 static const struct snd_kcontrol_new rt5663_sto1_adcl_mux = 2280 SOC_DAPM_ENUM("STO1 ADC L Mux", rt5663_sto1_adcl_enum); 2281 2282 static SOC_ENUM_SINGLE_DECL(rt5663_sto1_adcr_enum, RT5663_STO1_ADC_MIXER, 2283 RT5663_STO1_ADC_R_SRC_SHIFT, rt5663_sto1_adc_src); 2284 2285 static const struct snd_kcontrol_new rt5663_sto1_adcr_mux = 2286 SOC_DAPM_ENUM("STO1 ADC R Mux", rt5663_sto1_adcr_enum); 2287 2288 /* RT5663: Analog DACL1 input source */ 2289 static const char * const rt5663_alg_dacl_src[] = { 2290 "DAC L", "STO DAC MIXL" 2291 }; 2292 2293 static SOC_ENUM_SINGLE_DECL(rt5663_alg_dacl_enum, RT5663_BYPASS_STO_DAC, 2294 RT5663_DACL1_SRC_SHIFT, rt5663_alg_dacl_src); 2295 2296 static const struct snd_kcontrol_new rt5663_alg_dacl_mux = 2297 SOC_DAPM_ENUM("DAC L Mux", rt5663_alg_dacl_enum); 2298 2299 /* RT5663: Analog DACR1 input source */ 2300 static const char * const rt5663_alg_dacr_src[] = { 2301 "DAC R", "STO DAC MIXR" 2302 }; 2303 2304 static SOC_ENUM_SINGLE_DECL(rt5663_alg_dacr_enum, RT5663_BYPASS_STO_DAC, 2305 RT5663_DACR1_SRC_SHIFT, rt5663_alg_dacr_src); 2306 2307 static const struct snd_kcontrol_new rt5663_alg_dacr_mux = 2308 SOC_DAPM_ENUM("DAC R Mux", rt5663_alg_dacr_enum); 2309 2310 static int rt5663_hp_event(struct snd_soc_dapm_widget *w, 2311 struct snd_kcontrol *kcontrol, int event) 2312 { 2313 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 2314 struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component); 2315 2316 switch (event) { 2317 case SND_SOC_DAPM_POST_PMU: 2318 if (rt5663->codec_ver == CODEC_VER_1) { 2319 snd_soc_component_update_bits(component, RT5663_HP_CHARGE_PUMP_1, 2320 RT5663_SEL_PM_HP_SHIFT, RT5663_SEL_PM_HP_HIGH); 2321 snd_soc_component_update_bits(component, RT5663_HP_LOGIC_2, 2322 RT5663_HP_SIG_SRC1_MASK, 2323 RT5663_HP_SIG_SRC1_SILENCE); 2324 } else { 2325 snd_soc_component_update_bits(component, 2326 RT5663_DACREF_LDO, 0x3e0e, 0x3a0a); 2327 snd_soc_component_write(component, RT5663_DEPOP_2, 0x3003); 2328 snd_soc_component_update_bits(component, RT5663_HP_CHARGE_PUMP_1, 2329 RT5663_OVCD_HP_MASK, RT5663_OVCD_HP_DIS); 2330 snd_soc_component_write(component, RT5663_HP_CHARGE_PUMP_2, 0x1371); 2331 snd_soc_component_write(component, RT5663_HP_BIAS, 0xabba); 2332 snd_soc_component_write(component, RT5663_CHARGE_PUMP_1, 0x2224); 2333 snd_soc_component_write(component, RT5663_ANA_BIAS_CUR_1, 0x7766); 2334 snd_soc_component_write(component, RT5663_HP_BIAS, 0xafaa); 2335 snd_soc_component_write(component, RT5663_CHARGE_PUMP_2, 0x7777); 2336 snd_soc_component_update_bits(component, RT5663_STO_DRE_1, 0x8000, 2337 0x8000); 2338 snd_soc_component_update_bits(component, RT5663_DEPOP_1, 0x3000, 2339 0x3000); 2340 } 2341 break; 2342 2343 case SND_SOC_DAPM_PRE_PMD: 2344 if (rt5663->codec_ver == CODEC_VER_1) { 2345 snd_soc_component_update_bits(component, RT5663_HP_LOGIC_2, 2346 RT5663_HP_SIG_SRC1_MASK, 2347 RT5663_HP_SIG_SRC1_REG); 2348 } else { 2349 snd_soc_component_update_bits(component, RT5663_DEPOP_1, 0x3000, 0x0); 2350 snd_soc_component_update_bits(component, RT5663_HP_CHARGE_PUMP_1, 2351 RT5663_OVCD_HP_MASK, RT5663_OVCD_HP_EN); 2352 snd_soc_component_update_bits(component, 2353 RT5663_DACREF_LDO, 0x3e0e, 0); 2354 } 2355 break; 2356 2357 default: 2358 return 0; 2359 } 2360 2361 return 0; 2362 } 2363 2364 static int rt5663_charge_pump_event(struct snd_soc_dapm_widget *w, 2365 struct snd_kcontrol *kcontrol, int event) 2366 { 2367 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 2368 struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component); 2369 2370 switch (event) { 2371 case SND_SOC_DAPM_PRE_PMU: 2372 if (rt5663->codec_ver == CODEC_VER_0) { 2373 snd_soc_component_update_bits(component, RT5663_DEPOP_1, 0x0030, 2374 0x0030); 2375 snd_soc_component_update_bits(component, RT5663_DEPOP_1, 0x0003, 2376 0x0003); 2377 } 2378 break; 2379 2380 case SND_SOC_DAPM_POST_PMD: 2381 if (rt5663->codec_ver == CODEC_VER_0) { 2382 snd_soc_component_update_bits(component, RT5663_DEPOP_1, 0x0003, 0); 2383 snd_soc_component_update_bits(component, RT5663_DEPOP_1, 0x0030, 0); 2384 } 2385 break; 2386 2387 default: 2388 return 0; 2389 } 2390 2391 return 0; 2392 } 2393 2394 static int rt5663_bst2_power(struct snd_soc_dapm_widget *w, 2395 struct snd_kcontrol *kcontrol, int event) 2396 { 2397 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 2398 2399 switch (event) { 2400 case SND_SOC_DAPM_POST_PMU: 2401 snd_soc_component_update_bits(component, RT5663_PWR_ANLG_2, 2402 RT5663_PWR_BST2_MASK | RT5663_PWR_BST2_OP_MASK, 2403 RT5663_PWR_BST2 | RT5663_PWR_BST2_OP); 2404 break; 2405 2406 case SND_SOC_DAPM_PRE_PMD: 2407 snd_soc_component_update_bits(component, RT5663_PWR_ANLG_2, 2408 RT5663_PWR_BST2_MASK | RT5663_PWR_BST2_OP_MASK, 0); 2409 break; 2410 2411 default: 2412 return 0; 2413 } 2414 2415 return 0; 2416 } 2417 2418 static int rt5663_pre_div_power(struct snd_soc_dapm_widget *w, 2419 struct snd_kcontrol *kcontrol, int event) 2420 { 2421 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 2422 2423 switch (event) { 2424 case SND_SOC_DAPM_POST_PMU: 2425 snd_soc_component_write(component, RT5663_PRE_DIV_GATING_1, 0xff00); 2426 snd_soc_component_write(component, RT5663_PRE_DIV_GATING_2, 0xfffc); 2427 break; 2428 2429 case SND_SOC_DAPM_PRE_PMD: 2430 snd_soc_component_write(component, RT5663_PRE_DIV_GATING_1, 0x0000); 2431 snd_soc_component_write(component, RT5663_PRE_DIV_GATING_2, 0x0000); 2432 break; 2433 2434 default: 2435 return 0; 2436 } 2437 2438 return 0; 2439 } 2440 2441 static const struct snd_soc_dapm_widget rt5663_dapm_widgets[] = { 2442 SND_SOC_DAPM_SUPPLY("PLL", RT5663_PWR_ANLG_3, RT5663_PWR_PLL_SHIFT, 0, 2443 NULL, 0), 2444 2445 /* micbias */ 2446 SND_SOC_DAPM_MICBIAS("MICBIAS1", RT5663_PWR_ANLG_2, 2447 RT5663_PWR_MB1_SHIFT, 0), 2448 SND_SOC_DAPM_MICBIAS("MICBIAS2", RT5663_PWR_ANLG_2, 2449 RT5663_PWR_MB2_SHIFT, 0), 2450 2451 /* Input Lines */ 2452 SND_SOC_DAPM_INPUT("IN1P"), 2453 SND_SOC_DAPM_INPUT("IN1N"), 2454 2455 /* REC Mixer Power */ 2456 SND_SOC_DAPM_SUPPLY("RECMIX1L Power", RT5663_PWR_ANLG_2, 2457 RT5663_PWR_RECMIX1_SHIFT, 0, NULL, 0), 2458 2459 /* ADCs */ 2460 SND_SOC_DAPM_ADC("ADC L", NULL, SND_SOC_NOPM, 0, 0), 2461 SND_SOC_DAPM_SUPPLY("ADC L Power", RT5663_PWR_DIG_1, 2462 RT5663_PWR_ADC_L1_SHIFT, 0, NULL, 0), 2463 SND_SOC_DAPM_SUPPLY("ADC Clock", RT5663_CHOP_ADC, 2464 RT5663_CKGEN_ADCC_SHIFT, 0, NULL, 0), 2465 2466 /* ADC Mixer */ 2467 SND_SOC_DAPM_MIXER("STO1 ADC MIXL", SND_SOC_NOPM, 2468 0, 0, rt5663_sto1_adc_l_mix, 2469 ARRAY_SIZE(rt5663_sto1_adc_l_mix)), 2470 2471 /* ADC Filter Power */ 2472 SND_SOC_DAPM_SUPPLY("STO1 ADC Filter", RT5663_PWR_DIG_2, 2473 RT5663_PWR_ADC_S1F_SHIFT, 0, NULL, 0), 2474 2475 /* Digital Interface */ 2476 SND_SOC_DAPM_SUPPLY("I2S", RT5663_PWR_DIG_1, RT5663_PWR_I2S1_SHIFT, 0, 2477 NULL, 0), 2478 SND_SOC_DAPM_PGA("IF DAC", SND_SOC_NOPM, 0, 0, NULL, 0), 2479 SND_SOC_DAPM_PGA("IF1 DAC1 L", SND_SOC_NOPM, 0, 0, NULL, 0), 2480 SND_SOC_DAPM_PGA("IF1 DAC1 R", SND_SOC_NOPM, 0, 0, NULL, 0), 2481 SND_SOC_DAPM_PGA("IF1 ADC1", SND_SOC_NOPM, 0, 0, NULL, 0), 2482 SND_SOC_DAPM_PGA("IF ADC", SND_SOC_NOPM, 0, 0, NULL, 0), 2483 2484 /* Audio Interface */ 2485 SND_SOC_DAPM_AIF_IN("AIFRX", "AIF Playback", 0, SND_SOC_NOPM, 0, 0), 2486 SND_SOC_DAPM_AIF_OUT("AIFTX", "AIF Capture", 0, SND_SOC_NOPM, 0, 0), 2487 2488 /* DAC mixer before sound effect */ 2489 SND_SOC_DAPM_MIXER("ADDA MIXL", SND_SOC_NOPM, 0, 0, rt5663_adda_l_mix, 2490 ARRAY_SIZE(rt5663_adda_l_mix)), 2491 SND_SOC_DAPM_MIXER("ADDA MIXR", SND_SOC_NOPM, 0, 0, rt5663_adda_r_mix, 2492 ARRAY_SIZE(rt5663_adda_r_mix)), 2493 SND_SOC_DAPM_PGA("DAC L1", SND_SOC_NOPM, 0, 0, NULL, 0), 2494 SND_SOC_DAPM_PGA("DAC R1", SND_SOC_NOPM, 0, 0, NULL, 0), 2495 2496 /* DAC Mixer */ 2497 SND_SOC_DAPM_SUPPLY("STO1 DAC Filter", RT5663_PWR_DIG_2, 2498 RT5663_PWR_DAC_S1F_SHIFT, 0, NULL, 0), 2499 SND_SOC_DAPM_MIXER("STO1 DAC MIXL", SND_SOC_NOPM, 0, 0, 2500 rt5663_sto1_dac_l_mix, ARRAY_SIZE(rt5663_sto1_dac_l_mix)), 2501 SND_SOC_DAPM_MIXER("STO1 DAC MIXR", SND_SOC_NOPM, 0, 0, 2502 rt5663_sto1_dac_r_mix, ARRAY_SIZE(rt5663_sto1_dac_r_mix)), 2503 2504 /* DACs */ 2505 SND_SOC_DAPM_SUPPLY("STO1 DAC L Power", RT5663_PWR_DIG_1, 2506 RT5663_PWR_DAC_L1_SHIFT, 0, NULL, 0), 2507 SND_SOC_DAPM_SUPPLY("STO1 DAC R Power", RT5663_PWR_DIG_1, 2508 RT5663_PWR_DAC_R1_SHIFT, 0, NULL, 0), 2509 SND_SOC_DAPM_DAC("DAC L", NULL, SND_SOC_NOPM, 0, 0), 2510 SND_SOC_DAPM_DAC("DAC R", NULL, SND_SOC_NOPM, 0, 0), 2511 2512 /* Headphone*/ 2513 SND_SOC_DAPM_SUPPLY("HP Charge Pump", SND_SOC_NOPM, 0, 0, 2514 rt5663_charge_pump_event, SND_SOC_DAPM_PRE_PMU | 2515 SND_SOC_DAPM_POST_PMD), 2516 SND_SOC_DAPM_PGA_S("HP Amp", 1, SND_SOC_NOPM, 0, 0, rt5663_hp_event, 2517 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU), 2518 2519 /* Output Lines */ 2520 SND_SOC_DAPM_OUTPUT("HPOL"), 2521 SND_SOC_DAPM_OUTPUT("HPOR"), 2522 }; 2523 2524 static const struct snd_soc_dapm_widget rt5663_v2_specific_dapm_widgets[] = { 2525 SND_SOC_DAPM_SUPPLY("LDO2", RT5663_PWR_ANLG_3, 2526 RT5663_PWR_LDO2_SHIFT, 0, NULL, 0), 2527 SND_SOC_DAPM_SUPPLY("Mic Det Power", RT5663_PWR_VOL, 2528 RT5663_V2_PWR_MIC_DET_SHIFT, 0, NULL, 0), 2529 SND_SOC_DAPM_SUPPLY("LDO DAC", RT5663_PWR_DIG_1, 2530 RT5663_PWR_LDO_DACREF_SHIFT, 0, NULL, 0), 2531 2532 /* ASRC */ 2533 SND_SOC_DAPM_SUPPLY("I2S ASRC", RT5663_ASRC_1, 2534 RT5663_I2S1_ASRC_SHIFT, 0, NULL, 0), 2535 SND_SOC_DAPM_SUPPLY("DAC ASRC", RT5663_ASRC_1, 2536 RT5663_DAC_STO1_ASRC_SHIFT, 0, NULL, 0), 2537 SND_SOC_DAPM_SUPPLY("ADC ASRC", RT5663_ASRC_1, 2538 RT5663_ADC_STO1_ASRC_SHIFT, 0, NULL, 0), 2539 2540 /* Input Lines */ 2541 SND_SOC_DAPM_INPUT("IN2P"), 2542 SND_SOC_DAPM_INPUT("IN2N"), 2543 2544 /* Boost */ 2545 SND_SOC_DAPM_PGA("BST1 CBJ", SND_SOC_NOPM, 0, 0, NULL, 0), 2546 SND_SOC_DAPM_SUPPLY("CBJ Power", RT5663_PWR_ANLG_3, 2547 RT5663_PWR_CBJ_SHIFT, 0, NULL, 0), 2548 SND_SOC_DAPM_PGA("BST2", SND_SOC_NOPM, 0, 0, NULL, 0), 2549 SND_SOC_DAPM_SUPPLY("BST2 Power", SND_SOC_NOPM, 0, 0, 2550 rt5663_bst2_power, SND_SOC_DAPM_PRE_PMD | 2551 SND_SOC_DAPM_POST_PMU), 2552 2553 /* REC Mixer */ 2554 SND_SOC_DAPM_MIXER("RECMIX1L", SND_SOC_NOPM, 0, 0, rt5663_recmix1l, 2555 ARRAY_SIZE(rt5663_recmix1l)), 2556 SND_SOC_DAPM_MIXER("RECMIX1R", SND_SOC_NOPM, 0, 0, rt5663_recmix1r, 2557 ARRAY_SIZE(rt5663_recmix1r)), 2558 SND_SOC_DAPM_SUPPLY("RECMIX1R Power", RT5663_PWR_ANLG_2, 2559 RT5663_PWR_RECMIX2_SHIFT, 0, NULL, 0), 2560 2561 /* ADC */ 2562 SND_SOC_DAPM_ADC("ADC R", NULL, SND_SOC_NOPM, 0, 0), 2563 SND_SOC_DAPM_SUPPLY("ADC R Power", RT5663_PWR_DIG_1, 2564 RT5663_PWR_ADC_R1_SHIFT, 0, NULL, 0), 2565 2566 /* ADC Mux */ 2567 SND_SOC_DAPM_PGA("STO1 ADC L1", RT5663_STO1_ADC_MIXER, 2568 RT5663_STO1_ADC_L1_SRC_SHIFT, 0, NULL, 0), 2569 SND_SOC_DAPM_PGA("STO1 ADC R1", RT5663_STO1_ADC_MIXER, 2570 RT5663_STO1_ADC_R1_SRC_SHIFT, 0, NULL, 0), 2571 SND_SOC_DAPM_PGA("STO1 ADC L2", RT5663_STO1_ADC_MIXER, 2572 RT5663_STO1_ADC_L2_SRC_SHIFT, 1, NULL, 0), 2573 SND_SOC_DAPM_PGA("STO1 ADC R2", RT5663_STO1_ADC_MIXER, 2574 RT5663_STO1_ADC_R2_SRC_SHIFT, 1, NULL, 0), 2575 2576 SND_SOC_DAPM_MUX("STO1 ADC L Mux", SND_SOC_NOPM, 0, 0, 2577 &rt5663_sto1_adcl_mux), 2578 SND_SOC_DAPM_MUX("STO1 ADC R Mux", SND_SOC_NOPM, 0, 0, 2579 &rt5663_sto1_adcr_mux), 2580 2581 /* ADC Mix */ 2582 SND_SOC_DAPM_MIXER("STO1 ADC MIXR", SND_SOC_NOPM, 0, 0, 2583 rt5663_sto1_adc_r_mix, ARRAY_SIZE(rt5663_sto1_adc_r_mix)), 2584 2585 /* Analog DAC Clock */ 2586 SND_SOC_DAPM_SUPPLY("DAC Clock", RT5663_CHOP_DAC_L, 2587 RT5663_CKGEN_DAC1_SHIFT, 0, NULL, 0), 2588 2589 /* Headphone out */ 2590 SND_SOC_DAPM_SWITCH("HPO Playback", SND_SOC_NOPM, 0, 0, 2591 &rt5663_hpo_switch), 2592 }; 2593 2594 static const struct snd_soc_dapm_widget rt5663_specific_dapm_widgets[] = { 2595 /* System Clock Pre Divider Gating */ 2596 SND_SOC_DAPM_SUPPLY("Pre Div Power", SND_SOC_NOPM, 0, 0, 2597 rt5663_pre_div_power, SND_SOC_DAPM_POST_PMU | 2598 SND_SOC_DAPM_PRE_PMD), 2599 2600 /* LDO */ 2601 SND_SOC_DAPM_SUPPLY("LDO ADC", RT5663_PWR_DIG_1, 2602 RT5663_PWR_LDO_DACREF_SHIFT, 0, NULL, 0), 2603 2604 /* ASRC */ 2605 SND_SOC_DAPM_SUPPLY("I2S ASRC", RT5663_ASRC_1, 2606 RT5663_I2S1_ASRC_SHIFT, 0, NULL, 0), 2607 SND_SOC_DAPM_SUPPLY("DAC ASRC", RT5663_ASRC_1, 2608 RT5663_DAC_STO1_ASRC_SHIFT, 0, NULL, 0), 2609 SND_SOC_DAPM_SUPPLY("ADC ASRC", RT5663_ASRC_1, 2610 RT5663_ADC_STO1_ASRC_SHIFT, 0, NULL, 0), 2611 2612 /* Boost */ 2613 SND_SOC_DAPM_PGA("BST1", SND_SOC_NOPM, 0, 0, NULL, 0), 2614 2615 /* STO ADC */ 2616 SND_SOC_DAPM_PGA("STO1 ADC L1", SND_SOC_NOPM, 0, 0, NULL, 0), 2617 SND_SOC_DAPM_PGA("STO1 ADC L2", SND_SOC_NOPM, 0, 0, NULL, 0), 2618 2619 /* Analog DAC source */ 2620 SND_SOC_DAPM_MUX("DAC L Mux", SND_SOC_NOPM, 0, 0, &rt5663_alg_dacl_mux), 2621 SND_SOC_DAPM_MUX("DAC R Mux", SND_SOC_NOPM, 0, 0, &rt5663_alg_dacr_mux), 2622 }; 2623 2624 static const struct snd_soc_dapm_route rt5663_dapm_routes[] = { 2625 /* PLL */ 2626 { "I2S", NULL, "PLL", rt5663_is_sys_clk_from_pll }, 2627 2628 /* ASRC */ 2629 { "STO1 ADC Filter", NULL, "ADC ASRC", rt5663_is_using_asrc }, 2630 { "STO1 DAC Filter", NULL, "DAC ASRC", rt5663_is_using_asrc }, 2631 { "I2S", NULL, "I2S ASRC", rt5663_i2s_use_asrc }, 2632 2633 { "ADC L", NULL, "ADC L Power" }, 2634 { "ADC L", NULL, "ADC Clock" }, 2635 2636 { "STO1 ADC L2", NULL, "STO1 DAC MIXL" }, 2637 2638 { "STO1 ADC MIXL", "ADC1 Switch", "STO1 ADC L1" }, 2639 { "STO1 ADC MIXL", "ADC2 Switch", "STO1 ADC L2" }, 2640 { "STO1 ADC MIXL", NULL, "STO1 ADC Filter" }, 2641 2642 { "IF1 ADC1", NULL, "STO1 ADC MIXL" }, 2643 { "IF ADC", NULL, "IF1 ADC1" }, 2644 { "AIFTX", NULL, "IF ADC" }, 2645 { "AIFTX", NULL, "I2S" }, 2646 2647 { "AIFRX", NULL, "I2S" }, 2648 { "IF DAC", NULL, "AIFRX" }, 2649 { "IF1 DAC1 L", NULL, "IF DAC" }, 2650 { "IF1 DAC1 R", NULL, "IF DAC" }, 2651 2652 { "ADDA MIXL", "ADC L Switch", "STO1 ADC MIXL" }, 2653 { "ADDA MIXL", "DAC L Switch", "IF1 DAC1 L" }, 2654 { "ADDA MIXL", NULL, "STO1 DAC Filter" }, 2655 { "ADDA MIXL", NULL, "STO1 DAC L Power" }, 2656 { "ADDA MIXR", "DAC R Switch", "IF1 DAC1 R" }, 2657 { "ADDA MIXR", NULL, "STO1 DAC Filter" }, 2658 { "ADDA MIXR", NULL, "STO1 DAC R Power" }, 2659 2660 { "DAC L1", NULL, "ADDA MIXL" }, 2661 { "DAC R1", NULL, "ADDA MIXR" }, 2662 2663 { "STO1 DAC MIXL", "DAC L Switch", "DAC L1" }, 2664 { "STO1 DAC MIXL", NULL, "STO1 DAC L Power" }, 2665 { "STO1 DAC MIXL", NULL, "STO1 DAC Filter" }, 2666 { "STO1 DAC MIXR", "DAC R Switch", "DAC R1" }, 2667 { "STO1 DAC MIXR", NULL, "STO1 DAC R Power" }, 2668 { "STO1 DAC MIXR", NULL, "STO1 DAC Filter" }, 2669 2670 { "HP Amp", NULL, "HP Charge Pump" }, 2671 { "HP Amp", NULL, "DAC L" }, 2672 { "HP Amp", NULL, "DAC R" }, 2673 }; 2674 2675 static const struct snd_soc_dapm_route rt5663_v2_specific_dapm_routes[] = { 2676 { "MICBIAS1", NULL, "LDO2" }, 2677 { "MICBIAS2", NULL, "LDO2" }, 2678 2679 { "BST1 CBJ", NULL, "IN1P" }, 2680 { "BST1 CBJ", NULL, "IN1N" }, 2681 { "BST1 CBJ", NULL, "CBJ Power" }, 2682 2683 { "BST2", NULL, "IN2P" }, 2684 { "BST2", NULL, "IN2N" }, 2685 { "BST2", NULL, "BST2 Power" }, 2686 2687 { "RECMIX1L", "BST2 Switch", "BST2" }, 2688 { "RECMIX1L", "BST1 CBJ Switch", "BST1 CBJ" }, 2689 { "RECMIX1L", NULL, "RECMIX1L Power" }, 2690 { "RECMIX1R", "BST2 Switch", "BST2" }, 2691 { "RECMIX1R", NULL, "RECMIX1R Power" }, 2692 2693 { "ADC L", NULL, "RECMIX1L" }, 2694 { "ADC R", NULL, "RECMIX1R" }, 2695 { "ADC R", NULL, "ADC R Power" }, 2696 { "ADC R", NULL, "ADC Clock" }, 2697 2698 { "STO1 ADC L Mux", "ADC L", "ADC L" }, 2699 { "STO1 ADC L Mux", "ADC R", "ADC R" }, 2700 { "STO1 ADC L1", NULL, "STO1 ADC L Mux" }, 2701 2702 { "STO1 ADC R Mux", "ADC L", "ADC L" }, 2703 { "STO1 ADC R Mux", "ADC R", "ADC R" }, 2704 { "STO1 ADC R1", NULL, "STO1 ADC R Mux" }, 2705 { "STO1 ADC R2", NULL, "STO1 DAC MIXR" }, 2706 2707 { "STO1 ADC MIXR", "ADC1 Switch", "STO1 ADC R1" }, 2708 { "STO1 ADC MIXR", "ADC2 Switch", "STO1 ADC R2" }, 2709 { "STO1 ADC MIXR", NULL, "STO1 ADC Filter" }, 2710 2711 { "IF1 ADC1", NULL, "STO1 ADC MIXR" }, 2712 2713 { "ADDA MIXR", "ADC R Switch", "STO1 ADC MIXR" }, 2714 2715 { "DAC L", NULL, "STO1 DAC MIXL" }, 2716 { "DAC L", NULL, "LDO DAC" }, 2717 { "DAC L", NULL, "DAC Clock" }, 2718 { "DAC R", NULL, "STO1 DAC MIXR" }, 2719 { "DAC R", NULL, "LDO DAC" }, 2720 { "DAC R", NULL, "DAC Clock" }, 2721 2722 { "HPO Playback", "Switch", "HP Amp" }, 2723 { "HPOL", NULL, "HPO Playback" }, 2724 { "HPOR", NULL, "HPO Playback" }, 2725 }; 2726 2727 static const struct snd_soc_dapm_route rt5663_specific_dapm_routes[] = { 2728 { "I2S", NULL, "Pre Div Power" }, 2729 2730 { "BST1", NULL, "IN1P" }, 2731 { "BST1", NULL, "IN1N" }, 2732 { "BST1", NULL, "RECMIX1L Power" }, 2733 2734 { "ADC L", NULL, "BST1" }, 2735 2736 { "STO1 ADC L1", NULL, "ADC L" }, 2737 2738 { "DAC L Mux", "DAC L", "DAC L1" }, 2739 { "DAC L Mux", "STO DAC MIXL", "STO1 DAC MIXL" }, 2740 { "DAC R Mux", "DAC R", "DAC R1"}, 2741 { "DAC R Mux", "STO DAC MIXR", "STO1 DAC MIXR" }, 2742 2743 { "DAC L", NULL, "DAC L Mux" }, 2744 { "DAC R", NULL, "DAC R Mux" }, 2745 2746 { "HPOL", NULL, "HP Amp" }, 2747 { "HPOR", NULL, "HP Amp" }, 2748 }; 2749 2750 static int rt5663_hw_params(struct snd_pcm_substream *substream, 2751 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) 2752 { 2753 struct snd_soc_component *component = dai->component; 2754 struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component); 2755 unsigned int val_len = 0; 2756 int pre_div; 2757 2758 rt5663->lrck = params_rate(params); 2759 2760 dev_dbg(dai->dev, "bclk is %dHz and sysclk is %dHz\n", 2761 rt5663->lrck, rt5663->sysclk); 2762 2763 pre_div = rl6231_get_clk_info(rt5663->sysclk, rt5663->lrck); 2764 if (pre_div < 0) { 2765 dev_err(component->dev, "Unsupported clock setting %d for DAI %d\n", 2766 rt5663->lrck, dai->id); 2767 return -EINVAL; 2768 } 2769 2770 dev_dbg(dai->dev, "pre_div is %d for iis %d\n", pre_div, dai->id); 2771 2772 switch (params_width(params)) { 2773 case 8: 2774 val_len = RT5663_I2S_DL_8; 2775 break; 2776 case 16: 2777 val_len = RT5663_I2S_DL_16; 2778 break; 2779 case 20: 2780 val_len = RT5663_I2S_DL_20; 2781 break; 2782 case 24: 2783 val_len = RT5663_I2S_DL_24; 2784 break; 2785 default: 2786 return -EINVAL; 2787 } 2788 2789 snd_soc_component_update_bits(component, RT5663_I2S1_SDP, 2790 RT5663_I2S_DL_MASK, val_len); 2791 2792 snd_soc_component_update_bits(component, RT5663_ADDA_CLK_1, 2793 RT5663_I2S_PD1_MASK, pre_div << RT5663_I2S_PD1_SHIFT); 2794 2795 return 0; 2796 } 2797 2798 static int rt5663_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) 2799 { 2800 struct snd_soc_component *component = dai->component; 2801 unsigned int reg_val = 0; 2802 2803 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 2804 case SND_SOC_DAIFMT_CBM_CFM: 2805 break; 2806 case SND_SOC_DAIFMT_CBS_CFS: 2807 reg_val |= RT5663_I2S_MS_S; 2808 break; 2809 default: 2810 return -EINVAL; 2811 } 2812 2813 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 2814 case SND_SOC_DAIFMT_NB_NF: 2815 break; 2816 case SND_SOC_DAIFMT_IB_NF: 2817 reg_val |= RT5663_I2S_BP_INV; 2818 break; 2819 default: 2820 return -EINVAL; 2821 } 2822 2823 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 2824 case SND_SOC_DAIFMT_I2S: 2825 break; 2826 case SND_SOC_DAIFMT_LEFT_J: 2827 reg_val |= RT5663_I2S_DF_LEFT; 2828 break; 2829 case SND_SOC_DAIFMT_DSP_A: 2830 reg_val |= RT5663_I2S_DF_PCM_A; 2831 break; 2832 case SND_SOC_DAIFMT_DSP_B: 2833 reg_val |= RT5663_I2S_DF_PCM_B; 2834 break; 2835 default: 2836 return -EINVAL; 2837 } 2838 2839 snd_soc_component_update_bits(component, RT5663_I2S1_SDP, RT5663_I2S_MS_MASK | 2840 RT5663_I2S_BP_MASK | RT5663_I2S_DF_MASK, reg_val); 2841 2842 return 0; 2843 } 2844 2845 static int rt5663_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id, 2846 unsigned int freq, int dir) 2847 { 2848 struct snd_soc_component *component = dai->component; 2849 struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component); 2850 unsigned int reg_val = 0; 2851 2852 if (freq == rt5663->sysclk && clk_id == rt5663->sysclk_src) 2853 return 0; 2854 2855 switch (clk_id) { 2856 case RT5663_SCLK_S_MCLK: 2857 reg_val |= RT5663_SCLK_SRC_MCLK; 2858 break; 2859 case RT5663_SCLK_S_PLL1: 2860 reg_val |= RT5663_SCLK_SRC_PLL1; 2861 break; 2862 case RT5663_SCLK_S_RCCLK: 2863 reg_val |= RT5663_SCLK_SRC_RCCLK; 2864 break; 2865 default: 2866 dev_err(component->dev, "Invalid clock id (%d)\n", clk_id); 2867 return -EINVAL; 2868 } 2869 snd_soc_component_update_bits(component, RT5663_GLB_CLK, RT5663_SCLK_SRC_MASK, 2870 reg_val); 2871 rt5663->sysclk = freq; 2872 rt5663->sysclk_src = clk_id; 2873 2874 dev_dbg(component->dev, "Sysclk is %dHz and clock id is %d\n", 2875 freq, clk_id); 2876 2877 return 0; 2878 } 2879 2880 static int rt5663_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source, 2881 unsigned int freq_in, unsigned int freq_out) 2882 { 2883 struct snd_soc_component *component = dai->component; 2884 struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component); 2885 struct rl6231_pll_code pll_code; 2886 int ret; 2887 int mask, shift, val; 2888 2889 if (source == rt5663->pll_src && freq_in == rt5663->pll_in && 2890 freq_out == rt5663->pll_out) 2891 return 0; 2892 2893 if (!freq_in || !freq_out) { 2894 dev_dbg(component->dev, "PLL disabled\n"); 2895 2896 rt5663->pll_in = 0; 2897 rt5663->pll_out = 0; 2898 snd_soc_component_update_bits(component, RT5663_GLB_CLK, 2899 RT5663_SCLK_SRC_MASK, RT5663_SCLK_SRC_MCLK); 2900 return 0; 2901 } 2902 2903 switch (rt5663->codec_ver) { 2904 case CODEC_VER_1: 2905 mask = RT5663_V2_PLL1_SRC_MASK; 2906 shift = RT5663_V2_PLL1_SRC_SHIFT; 2907 break; 2908 case CODEC_VER_0: 2909 mask = RT5663_PLL1_SRC_MASK; 2910 shift = RT5663_PLL1_SRC_SHIFT; 2911 break; 2912 default: 2913 dev_err(component->dev, "Unknown CODEC Version\n"); 2914 return -EINVAL; 2915 } 2916 2917 switch (source) { 2918 case RT5663_PLL1_S_MCLK: 2919 val = 0x0; 2920 break; 2921 case RT5663_PLL1_S_BCLK1: 2922 val = 0x1; 2923 break; 2924 default: 2925 dev_err(component->dev, "Unknown PLL source %d\n", source); 2926 return -EINVAL; 2927 } 2928 snd_soc_component_update_bits(component, RT5663_GLB_CLK, mask, (val << shift)); 2929 2930 ret = rl6231_pll_calc(freq_in, freq_out, &pll_code); 2931 if (ret < 0) { 2932 dev_err(component->dev, "Unsupport input clock %d\n", freq_in); 2933 return ret; 2934 } 2935 2936 dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n", pll_code.m_bp, 2937 (pll_code.m_bp ? 0 : pll_code.m_code), pll_code.n_code, 2938 pll_code.k_code); 2939 2940 snd_soc_component_write(component, RT5663_PLL_1, 2941 pll_code.n_code << RT5663_PLL_N_SHIFT | pll_code.k_code); 2942 snd_soc_component_write(component, RT5663_PLL_2, 2943 (pll_code.m_bp ? 0 : pll_code.m_code) << RT5663_PLL_M_SHIFT | 2944 pll_code.m_bp << RT5663_PLL_M_BP_SHIFT); 2945 2946 rt5663->pll_in = freq_in; 2947 rt5663->pll_out = freq_out; 2948 rt5663->pll_src = source; 2949 2950 return 0; 2951 } 2952 2953 static int rt5663_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask, 2954 unsigned int rx_mask, int slots, int slot_width) 2955 { 2956 struct snd_soc_component *component = dai->component; 2957 struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component); 2958 unsigned int val = 0, reg; 2959 2960 if (rx_mask || tx_mask) 2961 val |= RT5663_TDM_MODE_TDM; 2962 2963 switch (slots) { 2964 case 4: 2965 val |= RT5663_TDM_IN_CH_4; 2966 val |= RT5663_TDM_OUT_CH_4; 2967 break; 2968 case 6: 2969 val |= RT5663_TDM_IN_CH_6; 2970 val |= RT5663_TDM_OUT_CH_6; 2971 break; 2972 case 8: 2973 val |= RT5663_TDM_IN_CH_8; 2974 val |= RT5663_TDM_OUT_CH_8; 2975 break; 2976 case 2: 2977 break; 2978 default: 2979 return -EINVAL; 2980 } 2981 2982 switch (slot_width) { 2983 case 20: 2984 val |= RT5663_TDM_IN_LEN_20; 2985 val |= RT5663_TDM_OUT_LEN_20; 2986 break; 2987 case 24: 2988 val |= RT5663_TDM_IN_LEN_24; 2989 val |= RT5663_TDM_OUT_LEN_24; 2990 break; 2991 case 32: 2992 val |= RT5663_TDM_IN_LEN_32; 2993 val |= RT5663_TDM_OUT_LEN_32; 2994 break; 2995 case 16: 2996 break; 2997 default: 2998 return -EINVAL; 2999 } 3000 3001 switch (rt5663->codec_ver) { 3002 case CODEC_VER_1: 3003 reg = RT5663_TDM_2; 3004 break; 3005 case CODEC_VER_0: 3006 reg = RT5663_TDM_1; 3007 break; 3008 default: 3009 dev_err(component->dev, "Unknown CODEC Version\n"); 3010 return -EINVAL; 3011 } 3012 3013 snd_soc_component_update_bits(component, reg, RT5663_TDM_MODE_MASK | 3014 RT5663_TDM_IN_CH_MASK | RT5663_TDM_OUT_CH_MASK | 3015 RT5663_TDM_IN_LEN_MASK | RT5663_TDM_OUT_LEN_MASK, val); 3016 3017 return 0; 3018 } 3019 3020 static int rt5663_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio) 3021 { 3022 struct snd_soc_component *component = dai->component; 3023 struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component); 3024 unsigned int reg; 3025 3026 dev_dbg(component->dev, "%s ratio = %d\n", __func__, ratio); 3027 3028 if (rt5663->codec_ver == CODEC_VER_1) 3029 reg = RT5663_TDM_9; 3030 else 3031 reg = RT5663_TDM_5; 3032 3033 switch (ratio) { 3034 case 32: 3035 snd_soc_component_update_bits(component, reg, 3036 RT5663_TDM_LENGTN_MASK, 3037 RT5663_TDM_LENGTN_16); 3038 break; 3039 case 40: 3040 snd_soc_component_update_bits(component, reg, 3041 RT5663_TDM_LENGTN_MASK, 3042 RT5663_TDM_LENGTN_20); 3043 break; 3044 case 48: 3045 snd_soc_component_update_bits(component, reg, 3046 RT5663_TDM_LENGTN_MASK, 3047 RT5663_TDM_LENGTN_24); 3048 break; 3049 case 64: 3050 snd_soc_component_update_bits(component, reg, 3051 RT5663_TDM_LENGTN_MASK, 3052 RT5663_TDM_LENGTN_32); 3053 break; 3054 default: 3055 dev_err(component->dev, "Invalid ratio!\n"); 3056 return -EINVAL; 3057 } 3058 3059 return 0; 3060 } 3061 3062 static int rt5663_set_bias_level(struct snd_soc_component *component, 3063 enum snd_soc_bias_level level) 3064 { 3065 struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component); 3066 3067 switch (level) { 3068 case SND_SOC_BIAS_ON: 3069 snd_soc_component_update_bits(component, RT5663_PWR_ANLG_1, 3070 RT5663_PWR_FV1_MASK | RT5663_PWR_FV2_MASK, 3071 RT5663_PWR_FV1 | RT5663_PWR_FV2); 3072 break; 3073 3074 case SND_SOC_BIAS_PREPARE: 3075 if (rt5663->codec_ver == CODEC_VER_1) { 3076 snd_soc_component_update_bits(component, RT5663_DIG_MISC, 3077 RT5663_DIG_GATE_CTRL_MASK, 3078 RT5663_DIG_GATE_CTRL_EN); 3079 snd_soc_component_update_bits(component, RT5663_SIG_CLK_DET, 3080 RT5663_EN_ANA_CLK_DET_MASK | 3081 RT5663_PWR_CLK_DET_MASK, 3082 RT5663_EN_ANA_CLK_DET_AUTO | 3083 RT5663_PWR_CLK_DET_EN); 3084 } 3085 break; 3086 3087 case SND_SOC_BIAS_STANDBY: 3088 if (rt5663->codec_ver == CODEC_VER_1) 3089 snd_soc_component_update_bits(component, RT5663_DIG_MISC, 3090 RT5663_DIG_GATE_CTRL_MASK, 3091 RT5663_DIG_GATE_CTRL_DIS); 3092 snd_soc_component_update_bits(component, RT5663_PWR_ANLG_1, 3093 RT5663_PWR_VREF1_MASK | RT5663_PWR_VREF2_MASK | 3094 RT5663_PWR_FV1_MASK | RT5663_PWR_FV2_MASK | 3095 RT5663_PWR_MB_MASK, RT5663_PWR_VREF1 | 3096 RT5663_PWR_VREF2 | RT5663_PWR_MB); 3097 usleep_range(10000, 10005); 3098 if (rt5663->codec_ver == CODEC_VER_1) { 3099 snd_soc_component_update_bits(component, RT5663_SIG_CLK_DET, 3100 RT5663_EN_ANA_CLK_DET_MASK | 3101 RT5663_PWR_CLK_DET_MASK, 3102 RT5663_EN_ANA_CLK_DET_DIS | 3103 RT5663_PWR_CLK_DET_DIS); 3104 } 3105 break; 3106 3107 case SND_SOC_BIAS_OFF: 3108 if (rt5663->jack_type != SND_JACK_HEADSET) 3109 snd_soc_component_update_bits(component, 3110 RT5663_PWR_ANLG_1, 3111 RT5663_PWR_VREF1_MASK | RT5663_PWR_VREF2_MASK | 3112 RT5663_PWR_FV1 | RT5663_PWR_FV2 | 3113 RT5663_PWR_MB_MASK, 0); 3114 else 3115 snd_soc_component_update_bits(component, 3116 RT5663_PWR_ANLG_1, 3117 RT5663_PWR_FV1_MASK | RT5663_PWR_FV2_MASK, 3118 RT5663_PWR_FV1 | RT5663_PWR_FV2); 3119 break; 3120 3121 default: 3122 break; 3123 } 3124 3125 return 0; 3126 } 3127 3128 static int rt5663_probe(struct snd_soc_component *component) 3129 { 3130 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); 3131 struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component); 3132 3133 rt5663->component = component; 3134 3135 switch (rt5663->codec_ver) { 3136 case CODEC_VER_1: 3137 snd_soc_dapm_new_controls(dapm, 3138 rt5663_v2_specific_dapm_widgets, 3139 ARRAY_SIZE(rt5663_v2_specific_dapm_widgets)); 3140 snd_soc_dapm_add_routes(dapm, 3141 rt5663_v2_specific_dapm_routes, 3142 ARRAY_SIZE(rt5663_v2_specific_dapm_routes)); 3143 snd_soc_add_component_controls(component, rt5663_v2_specific_controls, 3144 ARRAY_SIZE(rt5663_v2_specific_controls)); 3145 break; 3146 case CODEC_VER_0: 3147 snd_soc_dapm_new_controls(dapm, 3148 rt5663_specific_dapm_widgets, 3149 ARRAY_SIZE(rt5663_specific_dapm_widgets)); 3150 snd_soc_dapm_add_routes(dapm, 3151 rt5663_specific_dapm_routes, 3152 ARRAY_SIZE(rt5663_specific_dapm_routes)); 3153 snd_soc_add_component_controls(component, rt5663_specific_controls, 3154 ARRAY_SIZE(rt5663_specific_controls)); 3155 3156 if (!rt5663->imp_table) 3157 snd_soc_add_component_controls(component, rt5663_hpvol_controls, 3158 ARRAY_SIZE(rt5663_hpvol_controls)); 3159 break; 3160 } 3161 3162 return 0; 3163 } 3164 3165 static void rt5663_remove(struct snd_soc_component *component) 3166 { 3167 struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component); 3168 3169 regmap_write(rt5663->regmap, RT5663_RESET, 0); 3170 } 3171 3172 #ifdef CONFIG_PM 3173 static int rt5663_suspend(struct snd_soc_component *component) 3174 { 3175 struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component); 3176 3177 regcache_cache_only(rt5663->regmap, true); 3178 regcache_mark_dirty(rt5663->regmap); 3179 3180 return 0; 3181 } 3182 3183 static int rt5663_resume(struct snd_soc_component *component) 3184 { 3185 struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component); 3186 3187 regcache_cache_only(rt5663->regmap, false); 3188 regcache_sync(rt5663->regmap); 3189 3190 rt5663_irq(0, rt5663); 3191 3192 return 0; 3193 } 3194 #else 3195 #define rt5663_suspend NULL 3196 #define rt5663_resume NULL 3197 #endif 3198 3199 #define RT5663_STEREO_RATES SNDRV_PCM_RATE_8000_192000 3200 #define RT5663_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ 3201 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8) 3202 3203 static const struct snd_soc_dai_ops rt5663_aif_dai_ops = { 3204 .hw_params = rt5663_hw_params, 3205 .set_fmt = rt5663_set_dai_fmt, 3206 .set_sysclk = rt5663_set_dai_sysclk, 3207 .set_pll = rt5663_set_dai_pll, 3208 .set_tdm_slot = rt5663_set_tdm_slot, 3209 .set_bclk_ratio = rt5663_set_bclk_ratio, 3210 }; 3211 3212 static struct snd_soc_dai_driver rt5663_dai[] = { 3213 { 3214 .name = "rt5663-aif", 3215 .id = RT5663_AIF, 3216 .playback = { 3217 .stream_name = "AIF Playback", 3218 .channels_min = 1, 3219 .channels_max = 2, 3220 .rates = RT5663_STEREO_RATES, 3221 .formats = RT5663_FORMATS, 3222 }, 3223 .capture = { 3224 .stream_name = "AIF Capture", 3225 .channels_min = 1, 3226 .channels_max = 2, 3227 .rates = RT5663_STEREO_RATES, 3228 .formats = RT5663_FORMATS, 3229 }, 3230 .ops = &rt5663_aif_dai_ops, 3231 }, 3232 }; 3233 3234 static const struct snd_soc_component_driver soc_component_dev_rt5663 = { 3235 .probe = rt5663_probe, 3236 .remove = rt5663_remove, 3237 .suspend = rt5663_suspend, 3238 .resume = rt5663_resume, 3239 .set_bias_level = rt5663_set_bias_level, 3240 .controls = rt5663_snd_controls, 3241 .num_controls = ARRAY_SIZE(rt5663_snd_controls), 3242 .dapm_widgets = rt5663_dapm_widgets, 3243 .num_dapm_widgets = ARRAY_SIZE(rt5663_dapm_widgets), 3244 .dapm_routes = rt5663_dapm_routes, 3245 .num_dapm_routes = ARRAY_SIZE(rt5663_dapm_routes), 3246 .set_jack = rt5663_set_jack_detect, 3247 .use_pmdown_time = 1, 3248 .endianness = 1, 3249 .non_legacy_dai_naming = 1, 3250 }; 3251 3252 static const struct regmap_config rt5663_v2_regmap = { 3253 .reg_bits = 16, 3254 .val_bits = 16, 3255 .use_single_rw = true, 3256 .max_register = 0x07fa, 3257 .volatile_reg = rt5663_v2_volatile_register, 3258 .readable_reg = rt5663_v2_readable_register, 3259 .cache_type = REGCACHE_RBTREE, 3260 .reg_defaults = rt5663_v2_reg, 3261 .num_reg_defaults = ARRAY_SIZE(rt5663_v2_reg), 3262 }; 3263 3264 static const struct regmap_config rt5663_regmap = { 3265 .reg_bits = 16, 3266 .val_bits = 16, 3267 .use_single_rw = true, 3268 .max_register = 0x03f3, 3269 .volatile_reg = rt5663_volatile_register, 3270 .readable_reg = rt5663_readable_register, 3271 .cache_type = REGCACHE_RBTREE, 3272 .reg_defaults = rt5663_reg, 3273 .num_reg_defaults = ARRAY_SIZE(rt5663_reg), 3274 }; 3275 3276 static const struct regmap_config temp_regmap = { 3277 .name = "nocache", 3278 .reg_bits = 16, 3279 .val_bits = 16, 3280 .use_single_rw = true, 3281 .max_register = 0x03f3, 3282 .cache_type = REGCACHE_NONE, 3283 }; 3284 3285 static const struct i2c_device_id rt5663_i2c_id[] = { 3286 { "rt5663", 0 }, 3287 {} 3288 }; 3289 MODULE_DEVICE_TABLE(i2c, rt5663_i2c_id); 3290 3291 #if defined(CONFIG_OF) 3292 static const struct of_device_id rt5663_of_match[] = { 3293 { .compatible = "realtek,rt5663", }, 3294 {}, 3295 }; 3296 MODULE_DEVICE_TABLE(of, rt5663_of_match); 3297 #endif 3298 3299 #ifdef CONFIG_ACPI 3300 static const struct acpi_device_id rt5663_acpi_match[] = { 3301 { "10EC5663", 0}, 3302 {}, 3303 }; 3304 MODULE_DEVICE_TABLE(acpi, rt5663_acpi_match); 3305 #endif 3306 3307 static void rt5663_v2_calibrate(struct rt5663_priv *rt5663) 3308 { 3309 regmap_write(rt5663->regmap, RT5663_BIAS_CUR_8, 0xa402); 3310 regmap_write(rt5663->regmap, RT5663_PWR_DIG_1, 0x0100); 3311 regmap_write(rt5663->regmap, RT5663_RECMIX, 0x4040); 3312 regmap_write(rt5663->regmap, RT5663_DIG_MISC, 0x0001); 3313 regmap_write(rt5663->regmap, RT5663_RC_CLK, 0x0380); 3314 regmap_write(rt5663->regmap, RT5663_GLB_CLK, 0x8000); 3315 regmap_write(rt5663->regmap, RT5663_ADDA_CLK_1, 0x1000); 3316 regmap_write(rt5663->regmap, RT5663_CHOP_DAC_L, 0x3030); 3317 regmap_write(rt5663->regmap, RT5663_CALIB_ADC, 0x3c05); 3318 regmap_write(rt5663->regmap, RT5663_PWR_ANLG_1, 0xa23e); 3319 msleep(40); 3320 regmap_write(rt5663->regmap, RT5663_PWR_ANLG_1, 0xf23e); 3321 regmap_write(rt5663->regmap, RT5663_HP_CALIB_2, 0x0321); 3322 regmap_write(rt5663->regmap, RT5663_HP_CALIB_1, 0xfc00); 3323 msleep(500); 3324 } 3325 3326 static void rt5663_calibrate(struct rt5663_priv *rt5663) 3327 { 3328 int value, count; 3329 3330 regmap_write(rt5663->regmap, RT5663_RESET, 0x0000); 3331 msleep(20); 3332 regmap_write(rt5663->regmap, RT5663_ANA_BIAS_CUR_4, 0x00a1); 3333 regmap_write(rt5663->regmap, RT5663_RC_CLK, 0x0380); 3334 regmap_write(rt5663->regmap, RT5663_GLB_CLK, 0x8000); 3335 regmap_write(rt5663->regmap, RT5663_ADDA_CLK_1, 0x1000); 3336 regmap_write(rt5663->regmap, RT5663_VREF_RECMIX, 0x0032); 3337 regmap_write(rt5663->regmap, RT5663_HP_IMP_SEN_19, 0x000c); 3338 regmap_write(rt5663->regmap, RT5663_DUMMY_1, 0x0324); 3339 regmap_write(rt5663->regmap, RT5663_DIG_MISC, 0x8001); 3340 regmap_write(rt5663->regmap, RT5663_VREFADJ_OP, 0x0f28); 3341 regmap_write(rt5663->regmap, RT5663_PWR_ANLG_1, 0xa23b); 3342 msleep(30); 3343 regmap_write(rt5663->regmap, RT5663_PWR_ANLG_1, 0xf23b); 3344 regmap_write(rt5663->regmap, RT5663_PWR_ANLG_2, 0x8000); 3345 regmap_write(rt5663->regmap, RT5663_PWR_ANLG_3, 0x0008); 3346 regmap_write(rt5663->regmap, RT5663_PRE_DIV_GATING_1, 0xffff); 3347 regmap_write(rt5663->regmap, RT5663_PRE_DIV_GATING_2, 0xffff); 3348 regmap_write(rt5663->regmap, RT5663_CBJ_1, 0x8c10); 3349 regmap_write(rt5663->regmap, RT5663_IL_CMD_2, 0x00c1); 3350 regmap_write(rt5663->regmap, RT5663_EM_JACK_TYPE_1, 0xb880); 3351 regmap_write(rt5663->regmap, RT5663_EM_JACK_TYPE_2, 0x4110); 3352 regmap_write(rt5663->regmap, RT5663_EM_JACK_TYPE_2, 0x4118); 3353 3354 count = 0; 3355 while (true) { 3356 regmap_read(rt5663->regmap, RT5663_INT_ST_2, &value); 3357 if (!(value & 0x80)) 3358 usleep_range(10000, 10005); 3359 else 3360 break; 3361 3362 if (++count > 200) 3363 break; 3364 } 3365 3366 regmap_write(rt5663->regmap, RT5663_HP_IMP_SEN_19, 0x0000); 3367 regmap_write(rt5663->regmap, RT5663_DEPOP_2, 0x3003); 3368 regmap_write(rt5663->regmap, RT5663_DEPOP_1, 0x0038); 3369 regmap_write(rt5663->regmap, RT5663_DEPOP_1, 0x003b); 3370 regmap_write(rt5663->regmap, RT5663_PWR_DIG_2, 0x8400); 3371 regmap_write(rt5663->regmap, RT5663_PWR_DIG_1, 0x8df8); 3372 regmap_write(rt5663->regmap, RT5663_PWR_ANLG_2, 0x8003); 3373 regmap_write(rt5663->regmap, RT5663_PWR_ANLG_3, 0x018c); 3374 regmap_write(rt5663->regmap, RT5663_HP_CHARGE_PUMP_1, 0x1e32); 3375 regmap_write(rt5663->regmap, RT5663_DUMMY_2, 0x8089); 3376 regmap_write(rt5663->regmap, RT5663_DACREF_LDO, 0x3b0b); 3377 msleep(40); 3378 regmap_write(rt5663->regmap, RT5663_STO_DAC_MIXER, 0x0000); 3379 regmap_write(rt5663->regmap, RT5663_BYPASS_STO_DAC, 0x000c); 3380 regmap_write(rt5663->regmap, RT5663_HP_BIAS, 0xafaa); 3381 regmap_write(rt5663->regmap, RT5663_CHARGE_PUMP_1, 0x2224); 3382 regmap_write(rt5663->regmap, RT5663_HP_OUT_EN, 0x8088); 3383 regmap_write(rt5663->regmap, RT5663_STO_DRE_9, 0x0017); 3384 regmap_write(rt5663->regmap, RT5663_STO_DRE_10, 0x0017); 3385 regmap_write(rt5663->regmap, RT5663_STO1_ADC_MIXER, 0x4040); 3386 regmap_write(rt5663->regmap, RT5663_CHOP_ADC, 0x3000); 3387 regmap_write(rt5663->regmap, RT5663_RECMIX, 0x0005); 3388 regmap_write(rt5663->regmap, RT5663_ADDA_RST, 0xc000); 3389 regmap_write(rt5663->regmap, RT5663_STO1_HPF_ADJ1, 0x3320); 3390 regmap_write(rt5663->regmap, RT5663_HP_CALIB_2, 0x00c9); 3391 regmap_write(rt5663->regmap, RT5663_DUMMY_1, 0x004c); 3392 regmap_write(rt5663->regmap, RT5663_ANA_BIAS_CUR_1, 0x1111); 3393 regmap_write(rt5663->regmap, RT5663_BIAS_CUR_8, 0x4402); 3394 regmap_write(rt5663->regmap, RT5663_CHARGE_PUMP_2, 0x3311); 3395 regmap_write(rt5663->regmap, RT5663_HP_CALIB_1, 0x0069); 3396 regmap_write(rt5663->regmap, RT5663_HP_CALIB_3, 0x06ce); 3397 regmap_write(rt5663->regmap, RT5663_HP_CALIB_1_1, 0x6800); 3398 regmap_write(rt5663->regmap, RT5663_CHARGE_PUMP_2, 0x1100); 3399 regmap_write(rt5663->regmap, RT5663_HP_CALIB_7, 0x0057); 3400 regmap_write(rt5663->regmap, RT5663_HP_CALIB_1_1, 0xe800); 3401 3402 count = 0; 3403 while (true) { 3404 regmap_read(rt5663->regmap, RT5663_HP_CALIB_1_1, &value); 3405 if (value & 0x8000) 3406 usleep_range(10000, 10005); 3407 else 3408 break; 3409 3410 if (count > 200) 3411 return; 3412 count++; 3413 } 3414 3415 regmap_write(rt5663->regmap, RT5663_HP_CALIB_1_1, 0x6200); 3416 regmap_write(rt5663->regmap, RT5663_HP_CALIB_7, 0x0059); 3417 regmap_write(rt5663->regmap, RT5663_HP_CALIB_1_1, 0xe200); 3418 3419 count = 0; 3420 while (true) { 3421 regmap_read(rt5663->regmap, RT5663_HP_CALIB_1_1, &value); 3422 if (value & 0x8000) 3423 usleep_range(10000, 10005); 3424 else 3425 break; 3426 3427 if (count > 200) 3428 return; 3429 count++; 3430 } 3431 3432 regmap_write(rt5663->regmap, RT5663_EM_JACK_TYPE_1, 0xb8e0); 3433 usleep_range(10000, 10005); 3434 regmap_write(rt5663->regmap, RT5663_PWR_ANLG_1, 0x003b); 3435 usleep_range(10000, 10005); 3436 regmap_write(rt5663->regmap, RT5663_PWR_DIG_1, 0x0000); 3437 usleep_range(10000, 10005); 3438 regmap_write(rt5663->regmap, RT5663_DEPOP_1, 0x000b); 3439 usleep_range(10000, 10005); 3440 regmap_write(rt5663->regmap, RT5663_DEPOP_1, 0x0008); 3441 usleep_range(10000, 10005); 3442 regmap_write(rt5663->regmap, RT5663_PWR_ANLG_2, 0x0000); 3443 usleep_range(10000, 10005); 3444 } 3445 3446 static int rt5663_parse_dp(struct rt5663_priv *rt5663, struct device *dev) 3447 { 3448 int table_size; 3449 3450 device_property_read_u32(dev, "realtek,dc_offset_l_manual", 3451 &rt5663->pdata.dc_offset_l_manual); 3452 device_property_read_u32(dev, "realtek,dc_offset_r_manual", 3453 &rt5663->pdata.dc_offset_r_manual); 3454 device_property_read_u32(dev, "realtek,dc_offset_l_manual_mic", 3455 &rt5663->pdata.dc_offset_l_manual_mic); 3456 device_property_read_u32(dev, "realtek,dc_offset_r_manual_mic", 3457 &rt5663->pdata.dc_offset_r_manual_mic); 3458 device_property_read_u32(dev, "realtek,impedance_sensing_num", 3459 &rt5663->pdata.impedance_sensing_num); 3460 3461 if (rt5663->pdata.impedance_sensing_num) { 3462 table_size = sizeof(struct impedance_mapping_table) * 3463 rt5663->pdata.impedance_sensing_num; 3464 rt5663->imp_table = devm_kzalloc(dev, table_size, GFP_KERNEL); 3465 device_property_read_u32_array(dev, 3466 "realtek,impedance_sensing_table", 3467 (u32 *)rt5663->imp_table, table_size); 3468 } 3469 3470 return 0; 3471 } 3472 3473 static int rt5663_i2c_probe(struct i2c_client *i2c, 3474 const struct i2c_device_id *id) 3475 { 3476 struct rt5663_platform_data *pdata = dev_get_platdata(&i2c->dev); 3477 struct rt5663_priv *rt5663; 3478 int ret; 3479 unsigned int val; 3480 struct regmap *regmap; 3481 3482 rt5663 = devm_kzalloc(&i2c->dev, sizeof(struct rt5663_priv), 3483 GFP_KERNEL); 3484 3485 if (rt5663 == NULL) 3486 return -ENOMEM; 3487 3488 i2c_set_clientdata(i2c, rt5663); 3489 3490 if (pdata) 3491 rt5663->pdata = *pdata; 3492 else 3493 rt5663_parse_dp(rt5663, &i2c->dev); 3494 3495 regmap = devm_regmap_init_i2c(i2c, &temp_regmap); 3496 if (IS_ERR(regmap)) { 3497 ret = PTR_ERR(regmap); 3498 dev_err(&i2c->dev, "Failed to allocate temp register map: %d\n", 3499 ret); 3500 return ret; 3501 } 3502 3503 ret = regmap_read(regmap, RT5663_VENDOR_ID_2, &val); 3504 if (ret || (val != RT5663_DEVICE_ID_2 && val != RT5663_DEVICE_ID_1)) { 3505 dev_err(&i2c->dev, 3506 "Device with ID register %#x is not rt5663, retry one time.\n", 3507 val); 3508 msleep(100); 3509 regmap_read(regmap, RT5663_VENDOR_ID_2, &val); 3510 } 3511 3512 switch (val) { 3513 case RT5663_DEVICE_ID_2: 3514 rt5663->regmap = devm_regmap_init_i2c(i2c, &rt5663_v2_regmap); 3515 rt5663->codec_ver = CODEC_VER_1; 3516 break; 3517 case RT5663_DEVICE_ID_1: 3518 rt5663->regmap = devm_regmap_init_i2c(i2c, &rt5663_regmap); 3519 rt5663->codec_ver = CODEC_VER_0; 3520 break; 3521 default: 3522 dev_err(&i2c->dev, 3523 "Device with ID register %#x is not rt5663\n", 3524 val); 3525 return -ENODEV; 3526 } 3527 3528 if (IS_ERR(rt5663->regmap)) { 3529 ret = PTR_ERR(rt5663->regmap); 3530 dev_err(&i2c->dev, "Failed to allocate register map: %d\n", 3531 ret); 3532 return ret; 3533 } 3534 3535 /* reset and calibrate */ 3536 regmap_write(rt5663->regmap, RT5663_RESET, 0); 3537 regcache_cache_bypass(rt5663->regmap, true); 3538 switch (rt5663->codec_ver) { 3539 case CODEC_VER_1: 3540 rt5663_v2_calibrate(rt5663); 3541 break; 3542 case CODEC_VER_0: 3543 rt5663_calibrate(rt5663); 3544 break; 3545 default: 3546 dev_err(&i2c->dev, "%s:Unknown codec type\n", __func__); 3547 } 3548 regcache_cache_bypass(rt5663->regmap, false); 3549 regmap_write(rt5663->regmap, RT5663_RESET, 0); 3550 dev_dbg(&i2c->dev, "calibrate done\n"); 3551 3552 switch (rt5663->codec_ver) { 3553 case CODEC_VER_1: 3554 break; 3555 case CODEC_VER_0: 3556 ret = regmap_register_patch(rt5663->regmap, rt5663_patch_list, 3557 ARRAY_SIZE(rt5663_patch_list)); 3558 if (ret != 0) 3559 dev_warn(&i2c->dev, 3560 "Failed to apply regmap patch: %d\n", ret); 3561 break; 3562 default: 3563 dev_err(&i2c->dev, "%s:Unknown codec type\n", __func__); 3564 } 3565 3566 /* GPIO1 as IRQ */ 3567 regmap_update_bits(rt5663->regmap, RT5663_GPIO_1, RT5663_GP1_PIN_MASK, 3568 RT5663_GP1_PIN_IRQ); 3569 /* 4btn inline command debounce */ 3570 regmap_update_bits(rt5663->regmap, RT5663_IL_CMD_5, 3571 RT5663_4BTN_CLK_DEB_MASK, RT5663_4BTN_CLK_DEB_65MS); 3572 3573 switch (rt5663->codec_ver) { 3574 case CODEC_VER_1: 3575 regmap_write(rt5663->regmap, RT5663_BIAS_CUR_8, 0xa402); 3576 /* JD1 */ 3577 regmap_update_bits(rt5663->regmap, RT5663_AUTO_1MRC_CLK, 3578 RT5663_IRQ_POW_SAV_MASK | RT5663_IRQ_POW_SAV_JD1_MASK, 3579 RT5663_IRQ_POW_SAV_EN | RT5663_IRQ_POW_SAV_JD1_EN); 3580 regmap_update_bits(rt5663->regmap, RT5663_PWR_ANLG_2, 3581 RT5663_PWR_JD1_MASK, RT5663_PWR_JD1); 3582 regmap_update_bits(rt5663->regmap, RT5663_IRQ_1, 3583 RT5663_EN_CB_JD_MASK, RT5663_EN_CB_JD_EN); 3584 3585 regmap_update_bits(rt5663->regmap, RT5663_HP_LOGIC_2, 3586 RT5663_HP_SIG_SRC1_MASK, RT5663_HP_SIG_SRC1_REG); 3587 regmap_update_bits(rt5663->regmap, RT5663_RECMIX, 3588 RT5663_VREF_BIAS_MASK | RT5663_CBJ_DET_MASK | 3589 RT5663_DET_TYPE_MASK, RT5663_VREF_BIAS_REG | 3590 RT5663_CBJ_DET_EN | RT5663_DET_TYPE_QFN); 3591 /* Set GPIO4 and GPIO8 as input for combo jack */ 3592 regmap_update_bits(rt5663->regmap, RT5663_GPIO_2, 3593 RT5663_GP4_PIN_CONF_MASK, RT5663_GP4_PIN_CONF_INPUT); 3594 regmap_update_bits(rt5663->regmap, RT5663_GPIO_3, 3595 RT5663_GP8_PIN_CONF_MASK, RT5663_GP8_PIN_CONF_INPUT); 3596 regmap_update_bits(rt5663->regmap, RT5663_PWR_ANLG_1, 3597 RT5663_LDO1_DVO_MASK | RT5663_AMP_HP_MASK, 3598 RT5663_LDO1_DVO_0_9V | RT5663_AMP_HP_3X); 3599 break; 3600 case CODEC_VER_0: 3601 regmap_update_bits(rt5663->regmap, RT5663_DIG_MISC, 3602 RT5663_DIG_GATE_CTRL_MASK, RT5663_DIG_GATE_CTRL_EN); 3603 regmap_update_bits(rt5663->regmap, RT5663_AUTO_1MRC_CLK, 3604 RT5663_IRQ_MANUAL_MASK, RT5663_IRQ_MANUAL_EN); 3605 regmap_update_bits(rt5663->regmap, RT5663_IRQ_1, 3606 RT5663_EN_IRQ_JD1_MASK, RT5663_EN_IRQ_JD1_EN); 3607 regmap_update_bits(rt5663->regmap, RT5663_GPIO_1, 3608 RT5663_GPIO1_TYPE_MASK, RT5663_GPIO1_TYPE_EN); 3609 regmap_write(rt5663->regmap, RT5663_VREF_RECMIX, 0x0032); 3610 regmap_update_bits(rt5663->regmap, RT5663_GPIO_2, 3611 RT5663_GP1_PIN_CONF_MASK | RT5663_SEL_GPIO1_MASK, 3612 RT5663_GP1_PIN_CONF_OUTPUT | RT5663_SEL_GPIO1_EN); 3613 regmap_update_bits(rt5663->regmap, RT5663_RECMIX, 3614 RT5663_RECMIX1_BST1_MASK, RT5663_RECMIX1_BST1_ON); 3615 regmap_update_bits(rt5663->regmap, RT5663_TDM_2, 3616 RT5663_DATA_SWAP_ADCDAT1_MASK, 3617 RT5663_DATA_SWAP_ADCDAT1_LL); 3618 break; 3619 default: 3620 dev_err(&i2c->dev, "%s:Unknown codec type\n", __func__); 3621 } 3622 3623 INIT_DELAYED_WORK(&rt5663->jack_detect_work, rt5663_jack_detect_work); 3624 INIT_DELAYED_WORK(&rt5663->jd_unplug_work, rt5663_jd_unplug_work); 3625 3626 if (i2c->irq) { 3627 ret = request_irq(i2c->irq, rt5663_irq, 3628 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING 3629 | IRQF_ONESHOT, "rt5663", rt5663); 3630 if (ret) 3631 dev_err(&i2c->dev, "%s Failed to reguest IRQ: %d\n", 3632 __func__, ret); 3633 } 3634 3635 ret = devm_snd_soc_register_component(&i2c->dev, 3636 &soc_component_dev_rt5663, 3637 rt5663_dai, ARRAY_SIZE(rt5663_dai)); 3638 3639 if (ret) { 3640 if (i2c->irq) 3641 free_irq(i2c->irq, rt5663); 3642 } 3643 3644 return ret; 3645 } 3646 3647 static int rt5663_i2c_remove(struct i2c_client *i2c) 3648 { 3649 struct rt5663_priv *rt5663 = i2c_get_clientdata(i2c); 3650 3651 if (i2c->irq) 3652 free_irq(i2c->irq, rt5663); 3653 3654 return 0; 3655 } 3656 3657 static void rt5663_i2c_shutdown(struct i2c_client *client) 3658 { 3659 struct rt5663_priv *rt5663 = i2c_get_clientdata(client); 3660 3661 regmap_write(rt5663->regmap, RT5663_RESET, 0); 3662 } 3663 3664 static struct i2c_driver rt5663_i2c_driver = { 3665 .driver = { 3666 .name = "rt5663", 3667 .acpi_match_table = ACPI_PTR(rt5663_acpi_match), 3668 .of_match_table = of_match_ptr(rt5663_of_match), 3669 }, 3670 .probe = rt5663_i2c_probe, 3671 .remove = rt5663_i2c_remove, 3672 .shutdown = rt5663_i2c_shutdown, 3673 .id_table = rt5663_i2c_id, 3674 }; 3675 module_i2c_driver(rt5663_i2c_driver); 3676 3677 MODULE_DESCRIPTION("ASoC RT5663 driver"); 3678 MODULE_AUTHOR("Jack Yu <jack.yu@realtek.com>"); 3679 MODULE_LICENSE("GPL v2"); 3680