xref: /openbmc/linux/sound/soc/codecs/rt5663.c (revision b732539e)
1 /*
2  * rt5663.c  --  RT5663 ALSA SoC audio codec driver
3  *
4  * Copyright 2016 Realtek Semiconductor Corp.
5  * Author: Jack Yu <jack.yu@realtek.com>
6  *
7  * This program is free software; you can redistribute it and/or modify
8  * it under the terms of the GNU General Public License version 2 as
9  * published by the Free Software Foundation.
10  */
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/init.h>
14 #include <linux/delay.h>
15 #include <linux/pm.h>
16 #include <linux/i2c.h>
17 #include <linux/platform_device.h>
18 #include <linux/spi/spi.h>
19 #include <linux/acpi.h>
20 #include <linux/workqueue.h>
21 #include <sound/core.h>
22 #include <sound/pcm.h>
23 #include <sound/pcm_params.h>
24 #include <sound/jack.h>
25 #include <sound/soc.h>
26 #include <sound/soc-dapm.h>
27 #include <sound/initval.h>
28 #include <sound/tlv.h>
29 
30 #include "rt5663.h"
31 #include "rl6231.h"
32 
33 #define RT5663_DEVICE_ID_2 0x6451
34 #define RT5663_DEVICE_ID_1 0x6406
35 
36 enum {
37 	CODEC_VER_1,
38 	CODEC_VER_0,
39 };
40 
41 struct impedance_mapping_table {
42 	unsigned int imp_min;
43 	unsigned int imp_max;
44 	unsigned int vol;
45 	unsigned int dc_offset_l_manual;
46 	unsigned int dc_offset_r_manual;
47 	unsigned int dc_offset_l_manual_mic;
48 	unsigned int dc_offset_r_manual_mic;
49 };
50 
51 struct rt5663_priv {
52 	struct snd_soc_component *component;
53 	struct rt5663_platform_data pdata;
54 	struct regmap *regmap;
55 	struct delayed_work jack_detect_work, jd_unplug_work;
56 	struct snd_soc_jack *hs_jack;
57 	struct timer_list btn_check_timer;
58 	struct impedance_mapping_table *imp_table;
59 
60 	int codec_ver;
61 	int sysclk;
62 	int sysclk_src;
63 	int lrck;
64 
65 	int pll_src;
66 	int pll_in;
67 	int pll_out;
68 
69 	int jack_type;
70 };
71 
72 static const struct reg_sequence rt5663_patch_list[] = {
73 	{ 0x002a, 0x8020 },
74 	{ 0x0086, 0x0028 },
75 };
76 
77 static const struct reg_default rt5663_v2_reg[] = {
78 	{ 0x0000, 0x0000 },
79 	{ 0x0001, 0xc8c8 },
80 	{ 0x0002, 0x8080 },
81 	{ 0x0003, 0x8000 },
82 	{ 0x0004, 0xc80a },
83 	{ 0x0005, 0x0000 },
84 	{ 0x0006, 0x0000 },
85 	{ 0x0007, 0x0000 },
86 	{ 0x000a, 0x0000 },
87 	{ 0x000b, 0x0000 },
88 	{ 0x000c, 0x0000 },
89 	{ 0x000d, 0x0000 },
90 	{ 0x000f, 0x0808 },
91 	{ 0x0010, 0x4000 },
92 	{ 0x0011, 0x0000 },
93 	{ 0x0012, 0x1404 },
94 	{ 0x0013, 0x1000 },
95 	{ 0x0014, 0xa00a },
96 	{ 0x0015, 0x0404 },
97 	{ 0x0016, 0x0404 },
98 	{ 0x0017, 0x0011 },
99 	{ 0x0018, 0xafaf },
100 	{ 0x0019, 0xafaf },
101 	{ 0x001a, 0xafaf },
102 	{ 0x001b, 0x0011 },
103 	{ 0x001c, 0x2f2f },
104 	{ 0x001d, 0x2f2f },
105 	{ 0x001e, 0x2f2f },
106 	{ 0x001f, 0x0000 },
107 	{ 0x0020, 0x0000 },
108 	{ 0x0021, 0x0000 },
109 	{ 0x0022, 0x5757 },
110 	{ 0x0023, 0x0039 },
111 	{ 0x0024, 0x000b },
112 	{ 0x0026, 0xc0c0 },
113 	{ 0x0027, 0xc0c0 },
114 	{ 0x0028, 0xc0c0 },
115 	{ 0x0029, 0x8080 },
116 	{ 0x002a, 0xaaaa },
117 	{ 0x002b, 0xaaaa },
118 	{ 0x002c, 0xaba8 },
119 	{ 0x002d, 0x0000 },
120 	{ 0x002e, 0x0000 },
121 	{ 0x002f, 0x0000 },
122 	{ 0x0030, 0x0000 },
123 	{ 0x0031, 0x5000 },
124 	{ 0x0032, 0x0000 },
125 	{ 0x0033, 0x0000 },
126 	{ 0x0034, 0x0000 },
127 	{ 0x0035, 0x0000 },
128 	{ 0x003a, 0x0000 },
129 	{ 0x003b, 0x0000 },
130 	{ 0x003c, 0x00ff },
131 	{ 0x003d, 0x0000 },
132 	{ 0x003e, 0x00ff },
133 	{ 0x003f, 0x0000 },
134 	{ 0x0040, 0x0000 },
135 	{ 0x0041, 0x00ff },
136 	{ 0x0042, 0x0000 },
137 	{ 0x0043, 0x00ff },
138 	{ 0x0044, 0x0c0c },
139 	{ 0x0049, 0xc00b },
140 	{ 0x004a, 0x0000 },
141 	{ 0x004b, 0x031f },
142 	{ 0x004d, 0x0000 },
143 	{ 0x004e, 0x001f },
144 	{ 0x004f, 0x0000 },
145 	{ 0x0050, 0x001f },
146 	{ 0x0052, 0xf000 },
147 	{ 0x0061, 0x0000 },
148 	{ 0x0062, 0x0000 },
149 	{ 0x0063, 0x003e },
150 	{ 0x0064, 0x0000 },
151 	{ 0x0065, 0x0000 },
152 	{ 0x0066, 0x003f },
153 	{ 0x0067, 0x0000 },
154 	{ 0x006b, 0x0000 },
155 	{ 0x006d, 0xff00 },
156 	{ 0x006e, 0x2808 },
157 	{ 0x006f, 0x000a },
158 	{ 0x0070, 0x8000 },
159 	{ 0x0071, 0x8000 },
160 	{ 0x0072, 0x8000 },
161 	{ 0x0073, 0x7000 },
162 	{ 0x0074, 0x7770 },
163 	{ 0x0075, 0x0002 },
164 	{ 0x0076, 0x0001 },
165 	{ 0x0078, 0x00f0 },
166 	{ 0x0079, 0x0000 },
167 	{ 0x007a, 0x0000 },
168 	{ 0x007b, 0x0000 },
169 	{ 0x007c, 0x0000 },
170 	{ 0x007d, 0x0123 },
171 	{ 0x007e, 0x4500 },
172 	{ 0x007f, 0x8003 },
173 	{ 0x0080, 0x0000 },
174 	{ 0x0081, 0x0000 },
175 	{ 0x0082, 0x0000 },
176 	{ 0x0083, 0x0000 },
177 	{ 0x0084, 0x0000 },
178 	{ 0x0085, 0x0000 },
179 	{ 0x0086, 0x0008 },
180 	{ 0x0087, 0x0000 },
181 	{ 0x0088, 0x0000 },
182 	{ 0x0089, 0x0000 },
183 	{ 0x008a, 0x0000 },
184 	{ 0x008b, 0x0000 },
185 	{ 0x008c, 0x0003 },
186 	{ 0x008e, 0x0060 },
187 	{ 0x008f, 0x1000 },
188 	{ 0x0091, 0x0c26 },
189 	{ 0x0092, 0x0073 },
190 	{ 0x0093, 0x0000 },
191 	{ 0x0094, 0x0080 },
192 	{ 0x0098, 0x0000 },
193 	{ 0x0099, 0x0000 },
194 	{ 0x009a, 0x0007 },
195 	{ 0x009f, 0x0000 },
196 	{ 0x00a0, 0x0000 },
197 	{ 0x00a1, 0x0002 },
198 	{ 0x00a2, 0x0001 },
199 	{ 0x00a3, 0x0002 },
200 	{ 0x00a4, 0x0001 },
201 	{ 0x00ae, 0x2040 },
202 	{ 0x00af, 0x0000 },
203 	{ 0x00b6, 0x0000 },
204 	{ 0x00b7, 0x0000 },
205 	{ 0x00b8, 0x0000 },
206 	{ 0x00b9, 0x0000 },
207 	{ 0x00ba, 0x0002 },
208 	{ 0x00bb, 0x0000 },
209 	{ 0x00be, 0x0000 },
210 	{ 0x00c0, 0x0000 },
211 	{ 0x00c1, 0x0aaa },
212 	{ 0x00c2, 0xaa80 },
213 	{ 0x00c3, 0x0003 },
214 	{ 0x00c4, 0x0000 },
215 	{ 0x00d0, 0x0000 },
216 	{ 0x00d1, 0x2244 },
217 	{ 0x00d2, 0x0000 },
218 	{ 0x00d3, 0x3300 },
219 	{ 0x00d4, 0x2200 },
220 	{ 0x00d9, 0x0809 },
221 	{ 0x00da, 0x0000 },
222 	{ 0x00db, 0x0008 },
223 	{ 0x00dc, 0x00c0 },
224 	{ 0x00dd, 0x6724 },
225 	{ 0x00de, 0x3131 },
226 	{ 0x00df, 0x0008 },
227 	{ 0x00e0, 0x4000 },
228 	{ 0x00e1, 0x3131 },
229 	{ 0x00e2, 0x600c },
230 	{ 0x00ea, 0xb320 },
231 	{ 0x00eb, 0x0000 },
232 	{ 0x00ec, 0xb300 },
233 	{ 0x00ed, 0x0000 },
234 	{ 0x00ee, 0xb320 },
235 	{ 0x00ef, 0x0000 },
236 	{ 0x00f0, 0x0201 },
237 	{ 0x00f1, 0x0ddd },
238 	{ 0x00f2, 0x0ddd },
239 	{ 0x00f6, 0x0000 },
240 	{ 0x00f7, 0x0000 },
241 	{ 0x00f8, 0x0000 },
242 	{ 0x00fa, 0x0000 },
243 	{ 0x00fb, 0x0000 },
244 	{ 0x00fc, 0x0000 },
245 	{ 0x00fd, 0x0000 },
246 	{ 0x00fe, 0x10ec },
247 	{ 0x00ff, 0x6451 },
248 	{ 0x0100, 0xaaaa },
249 	{ 0x0101, 0x000a },
250 	{ 0x010a, 0xaaaa },
251 	{ 0x010b, 0xa0a0 },
252 	{ 0x010c, 0xaeae },
253 	{ 0x010d, 0xaaaa },
254 	{ 0x010e, 0xaaaa },
255 	{ 0x010f, 0xaaaa },
256 	{ 0x0110, 0xe002 },
257 	{ 0x0111, 0xa602 },
258 	{ 0x0112, 0xaaaa },
259 	{ 0x0113, 0x2000 },
260 	{ 0x0117, 0x0f00 },
261 	{ 0x0125, 0x0420 },
262 	{ 0x0132, 0x0000 },
263 	{ 0x0133, 0x0000 },
264 	{ 0x0136, 0x5555 },
265 	{ 0x0137, 0x5540 },
266 	{ 0x0138, 0x3700 },
267 	{ 0x0139, 0x79a1 },
268 	{ 0x013a, 0x2020 },
269 	{ 0x013b, 0x2020 },
270 	{ 0x013c, 0x2005 },
271 	{ 0x013f, 0x0000 },
272 	{ 0x0145, 0x0002 },
273 	{ 0x0146, 0x0000 },
274 	{ 0x0147, 0x0000 },
275 	{ 0x0148, 0x0000 },
276 	{ 0x0160, 0x4ec0 },
277 	{ 0x0161, 0x0080 },
278 	{ 0x0162, 0x0200 },
279 	{ 0x0163, 0x0800 },
280 	{ 0x0164, 0x0000 },
281 	{ 0x0165, 0x0000 },
282 	{ 0x0166, 0x0000 },
283 	{ 0x0167, 0x000f },
284 	{ 0x0168, 0x000f },
285 	{ 0x0170, 0x4e80 },
286 	{ 0x0171, 0x0080 },
287 	{ 0x0172, 0x0200 },
288 	{ 0x0173, 0x0800 },
289 	{ 0x0174, 0x00ff },
290 	{ 0x0175, 0x0000 },
291 	{ 0x0190, 0x4131 },
292 	{ 0x0191, 0x4131 },
293 	{ 0x0192, 0x4131 },
294 	{ 0x0193, 0x4131 },
295 	{ 0x0194, 0x0000 },
296 	{ 0x0195, 0x0000 },
297 	{ 0x0196, 0x0000 },
298 	{ 0x0197, 0x0000 },
299 	{ 0x0198, 0x0000 },
300 	{ 0x0199, 0x0000 },
301 	{ 0x01a0, 0x1e64 },
302 	{ 0x01a1, 0x06a3 },
303 	{ 0x01a2, 0x0000 },
304 	{ 0x01a3, 0x0000 },
305 	{ 0x01a4, 0x0000 },
306 	{ 0x01a5, 0x0000 },
307 	{ 0x01a6, 0x0000 },
308 	{ 0x01a7, 0x0000 },
309 	{ 0x01a8, 0x0000 },
310 	{ 0x01a9, 0x0000 },
311 	{ 0x01aa, 0x0000 },
312 	{ 0x01ab, 0x0000 },
313 	{ 0x01b5, 0x0000 },
314 	{ 0x01b6, 0x01c3 },
315 	{ 0x01b7, 0x02a0 },
316 	{ 0x01b8, 0x03e9 },
317 	{ 0x01b9, 0x1389 },
318 	{ 0x01ba, 0xc351 },
319 	{ 0x01bb, 0x0009 },
320 	{ 0x01bc, 0x0018 },
321 	{ 0x01bd, 0x002a },
322 	{ 0x01be, 0x004c },
323 	{ 0x01bf, 0x0097 },
324 	{ 0x01c0, 0x433d },
325 	{ 0x01c1, 0x0000 },
326 	{ 0x01c2, 0x0000 },
327 	{ 0x01c3, 0x0000 },
328 	{ 0x01c4, 0x0000 },
329 	{ 0x01c5, 0x0000 },
330 	{ 0x01c6, 0x0000 },
331 	{ 0x01c7, 0x0000 },
332 	{ 0x01c8, 0x40af },
333 	{ 0x01c9, 0x0702 },
334 	{ 0x01ca, 0x0000 },
335 	{ 0x01cb, 0x0000 },
336 	{ 0x01cc, 0x5757 },
337 	{ 0x01cd, 0x5757 },
338 	{ 0x01ce, 0x5757 },
339 	{ 0x01cf, 0x5757 },
340 	{ 0x01d0, 0x5757 },
341 	{ 0x01d1, 0x5757 },
342 	{ 0x01d2, 0x5757 },
343 	{ 0x01d3, 0x5757 },
344 	{ 0x01d4, 0x5757 },
345 	{ 0x01d5, 0x5757 },
346 	{ 0x01d6, 0x003c },
347 	{ 0x01da, 0x0000 },
348 	{ 0x01db, 0x0000 },
349 	{ 0x01dc, 0x0000 },
350 	{ 0x01de, 0x7c00 },
351 	{ 0x01df, 0x0320 },
352 	{ 0x01e0, 0x06a1 },
353 	{ 0x01e1, 0x0000 },
354 	{ 0x01e2, 0x0000 },
355 	{ 0x01e3, 0x0000 },
356 	{ 0x01e4, 0x0000 },
357 	{ 0x01e5, 0x0000 },
358 	{ 0x01e6, 0x0001 },
359 	{ 0x01e7, 0x0000 },
360 	{ 0x01e8, 0x0000 },
361 	{ 0x01ea, 0x0000 },
362 	{ 0x01eb, 0x0000 },
363 	{ 0x01ec, 0x0000 },
364 	{ 0x01ed, 0x0000 },
365 	{ 0x01ee, 0x0000 },
366 	{ 0x01ef, 0x0000 },
367 	{ 0x01f0, 0x0000 },
368 	{ 0x01f1, 0x0000 },
369 	{ 0x01f2, 0x0000 },
370 	{ 0x01f3, 0x0000 },
371 	{ 0x01f4, 0x0000 },
372 	{ 0x0200, 0x0000 },
373 	{ 0x0201, 0x0000 },
374 	{ 0x0202, 0x0000 },
375 	{ 0x0203, 0x0000 },
376 	{ 0x0204, 0x0000 },
377 	{ 0x0205, 0x0000 },
378 	{ 0x0206, 0x0000 },
379 	{ 0x0207, 0x0000 },
380 	{ 0x0208, 0x0000 },
381 	{ 0x0210, 0x60b1 },
382 	{ 0x0211, 0xa000 },
383 	{ 0x0212, 0x024c },
384 	{ 0x0213, 0xf7ff },
385 	{ 0x0214, 0x024c },
386 	{ 0x0215, 0x0102 },
387 	{ 0x0216, 0x00a3 },
388 	{ 0x0217, 0x0048 },
389 	{ 0x0218, 0x92c0 },
390 	{ 0x0219, 0x0000 },
391 	{ 0x021a, 0x00c8 },
392 	{ 0x021b, 0x0020 },
393 	{ 0x02fa, 0x0000 },
394 	{ 0x02fb, 0x0000 },
395 	{ 0x02fc, 0x0000 },
396 	{ 0x02ff, 0x0110 },
397 	{ 0x0300, 0x001f },
398 	{ 0x0301, 0x032c },
399 	{ 0x0302, 0x5f21 },
400 	{ 0x0303, 0x4000 },
401 	{ 0x0304, 0x4000 },
402 	{ 0x0305, 0x06d5 },
403 	{ 0x0306, 0x8000 },
404 	{ 0x0307, 0x0700 },
405 	{ 0x0310, 0x4560 },
406 	{ 0x0311, 0xa4a8 },
407 	{ 0x0312, 0x7418 },
408 	{ 0x0313, 0x0000 },
409 	{ 0x0314, 0x0006 },
410 	{ 0x0315, 0xffff },
411 	{ 0x0316, 0xc400 },
412 	{ 0x0317, 0x0000 },
413 	{ 0x0330, 0x00a6 },
414 	{ 0x0331, 0x04c3 },
415 	{ 0x0332, 0x27c8 },
416 	{ 0x0333, 0xbf50 },
417 	{ 0x0334, 0x0045 },
418 	{ 0x0335, 0x0007 },
419 	{ 0x0336, 0x7418 },
420 	{ 0x0337, 0x0501 },
421 	{ 0x0338, 0x0000 },
422 	{ 0x0339, 0x0010 },
423 	{ 0x033a, 0x1010 },
424 	{ 0x03c0, 0x7e00 },
425 	{ 0x03c1, 0x8000 },
426 	{ 0x03c2, 0x8000 },
427 	{ 0x03c3, 0x8000 },
428 	{ 0x03c4, 0x8000 },
429 	{ 0x03c5, 0x8000 },
430 	{ 0x03c6, 0x8000 },
431 	{ 0x03c7, 0x8000 },
432 	{ 0x03c8, 0x8000 },
433 	{ 0x03c9, 0x8000 },
434 	{ 0x03ca, 0x8000 },
435 	{ 0x03cb, 0x8000 },
436 	{ 0x03cc, 0x8000 },
437 	{ 0x03d0, 0x0000 },
438 	{ 0x03d1, 0x0000 },
439 	{ 0x03d2, 0x0000 },
440 	{ 0x03d3, 0x0000 },
441 	{ 0x03d4, 0x2000 },
442 	{ 0x03d5, 0x2000 },
443 	{ 0x03d6, 0x0000 },
444 	{ 0x03d7, 0x0000 },
445 	{ 0x03d8, 0x2000 },
446 	{ 0x03d9, 0x2000 },
447 	{ 0x03da, 0x2000 },
448 	{ 0x03db, 0x2000 },
449 	{ 0x03dc, 0x0000 },
450 	{ 0x03dd, 0x0000 },
451 	{ 0x03de, 0x0000 },
452 	{ 0x03df, 0x2000 },
453 	{ 0x03e0, 0x0000 },
454 	{ 0x03e1, 0x0000 },
455 	{ 0x03e2, 0x0000 },
456 	{ 0x03e3, 0x0000 },
457 	{ 0x03e4, 0x0000 },
458 	{ 0x03e5, 0x0000 },
459 	{ 0x03e6, 0x0000 },
460 	{ 0x03e7, 0x0000 },
461 	{ 0x03e8, 0x0000 },
462 	{ 0x03e9, 0x0000 },
463 	{ 0x03ea, 0x0000 },
464 	{ 0x03eb, 0x0000 },
465 	{ 0x03ec, 0x0000 },
466 	{ 0x03ed, 0x0000 },
467 	{ 0x03ee, 0x0000 },
468 	{ 0x03ef, 0x0000 },
469 	{ 0x03f0, 0x0800 },
470 	{ 0x03f1, 0x0800 },
471 	{ 0x03f2, 0x0800 },
472 	{ 0x03f3, 0x0800 },
473 	{ 0x03fe, 0x0000 },
474 	{ 0x03ff, 0x0000 },
475 	{ 0x07f0, 0x0000 },
476 	{ 0x07fa, 0x0000 },
477 };
478 
479 static const struct reg_default rt5663_reg[] = {
480 	{ 0x0000, 0x0000 },
481 	{ 0x0002, 0x0008 },
482 	{ 0x0005, 0x1000 },
483 	{ 0x0006, 0x1000 },
484 	{ 0x000a, 0x0000 },
485 	{ 0x0010, 0x000f },
486 	{ 0x0015, 0x42f1 },
487 	{ 0x0016, 0x0000 },
488 	{ 0x0018, 0x000b },
489 	{ 0x0019, 0xafaf },
490 	{ 0x001c, 0x2f2f },
491 	{ 0x001f, 0x0000 },
492 	{ 0x0022, 0x5757 },
493 	{ 0x0023, 0x0039 },
494 	{ 0x0026, 0xc0c0 },
495 	{ 0x0029, 0x8080 },
496 	{ 0x002a, 0x8020 },
497 	{ 0x002c, 0x000c },
498 	{ 0x002d, 0x0000 },
499 	{ 0x0040, 0x0808 },
500 	{ 0x0061, 0x0000 },
501 	{ 0x0062, 0x0000 },
502 	{ 0x0063, 0x003e },
503 	{ 0x0064, 0x0000 },
504 	{ 0x0065, 0x0000 },
505 	{ 0x0066, 0x0000 },
506 	{ 0x006b, 0x0000 },
507 	{ 0x006e, 0x0000 },
508 	{ 0x006f, 0x0000 },
509 	{ 0x0070, 0x8020 },
510 	{ 0x0073, 0x1000 },
511 	{ 0x0074, 0xe400 },
512 	{ 0x0075, 0x0002 },
513 	{ 0x0076, 0x0001 },
514 	{ 0x0077, 0x00f0 },
515 	{ 0x0078, 0x0000 },
516 	{ 0x0079, 0x0000 },
517 	{ 0x007a, 0x0123 },
518 	{ 0x007b, 0x8003 },
519 	{ 0x0080, 0x0000 },
520 	{ 0x0081, 0x0000 },
521 	{ 0x0082, 0x0000 },
522 	{ 0x0083, 0x0000 },
523 	{ 0x0084, 0x0000 },
524 	{ 0x0086, 0x0028 },
525 	{ 0x0087, 0x0000 },
526 	{ 0x008a, 0x0000 },
527 	{ 0x008b, 0x0000 },
528 	{ 0x008c, 0x0003 },
529 	{ 0x008e, 0x0008 },
530 	{ 0x008f, 0x1000 },
531 	{ 0x0090, 0x0646 },
532 	{ 0x0091, 0x0e3e },
533 	{ 0x0092, 0x1071 },
534 	{ 0x0093, 0x0000 },
535 	{ 0x0094, 0x0080 },
536 	{ 0x0097, 0x0000 },
537 	{ 0x0098, 0x0000 },
538 	{ 0x009a, 0x0000 },
539 	{ 0x009f, 0x0000 },
540 	{ 0x00ae, 0x6000 },
541 	{ 0x00af, 0x0000 },
542 	{ 0x00b6, 0x0000 },
543 	{ 0x00b7, 0x0000 },
544 	{ 0x00b8, 0x0000 },
545 	{ 0x00ba, 0x0000 },
546 	{ 0x00bb, 0x0000 },
547 	{ 0x00be, 0x0000 },
548 	{ 0x00bf, 0x0000 },
549 	{ 0x00c0, 0x0000 },
550 	{ 0x00c1, 0x0000 },
551 	{ 0x00c5, 0x0000 },
552 	{ 0x00cb, 0xa02f },
553 	{ 0x00cc, 0x0000 },
554 	{ 0x00cd, 0x0e02 },
555 	{ 0x00d9, 0x08f9 },
556 	{ 0x00db, 0x0008 },
557 	{ 0x00dc, 0x00c0 },
558 	{ 0x00dd, 0x6729 },
559 	{ 0x00de, 0x3131 },
560 	{ 0x00df, 0x0008 },
561 	{ 0x00e0, 0x4000 },
562 	{ 0x00e1, 0x3131 },
563 	{ 0x00e2, 0x0043 },
564 	{ 0x00e4, 0x400b },
565 	{ 0x00e5, 0x8031 },
566 	{ 0x00e6, 0x3080 },
567 	{ 0x00e7, 0x4100 },
568 	{ 0x00e8, 0x1400 },
569 	{ 0x00e9, 0xe00a },
570 	{ 0x00ea, 0x0404 },
571 	{ 0x00eb, 0x0404 },
572 	{ 0x00ec, 0xb320 },
573 	{ 0x00ed, 0x0000 },
574 	{ 0x00f4, 0x0000 },
575 	{ 0x00f6, 0x0000 },
576 	{ 0x00f8, 0x0000 },
577 	{ 0x00fa, 0x8000 },
578 	{ 0x00fd, 0x0001 },
579 	{ 0x00fe, 0x10ec },
580 	{ 0x00ff, 0x6406 },
581 	{ 0x0100, 0xa0a0 },
582 	{ 0x0108, 0x4444 },
583 	{ 0x0109, 0x4444 },
584 	{ 0x010a, 0xaaaa },
585 	{ 0x010b, 0x00a0 },
586 	{ 0x010c, 0x8aaa },
587 	{ 0x010d, 0xaaaa },
588 	{ 0x010e, 0x2aaa },
589 	{ 0x010f, 0x002a },
590 	{ 0x0110, 0xa0a4 },
591 	{ 0x0111, 0x4602 },
592 	{ 0x0112, 0x0101 },
593 	{ 0x0113, 0x2000 },
594 	{ 0x0114, 0x0000 },
595 	{ 0x0116, 0x0000 },
596 	{ 0x0117, 0x0f00 },
597 	{ 0x0118, 0x0006 },
598 	{ 0x0125, 0x2424 },
599 	{ 0x0126, 0x5550 },
600 	{ 0x0127, 0x0400 },
601 	{ 0x0128, 0x7711 },
602 	{ 0x0132, 0x0004 },
603 	{ 0x0137, 0x5441 },
604 	{ 0x0139, 0x79a1 },
605 	{ 0x013a, 0x30c0 },
606 	{ 0x013b, 0x2000 },
607 	{ 0x013c, 0x2005 },
608 	{ 0x013d, 0x30c0 },
609 	{ 0x013e, 0x0000 },
610 	{ 0x0140, 0x3700 },
611 	{ 0x0141, 0x1f00 },
612 	{ 0x0144, 0x0000 },
613 	{ 0x0145, 0x0002 },
614 	{ 0x0146, 0x0000 },
615 	{ 0x0160, 0x0e80 },
616 	{ 0x0161, 0x0080 },
617 	{ 0x0162, 0x0200 },
618 	{ 0x0163, 0x0800 },
619 	{ 0x0164, 0x0000 },
620 	{ 0x0165, 0x0000 },
621 	{ 0x0166, 0x0000 },
622 	{ 0x0167, 0x1417 },
623 	{ 0x0168, 0x0017 },
624 	{ 0x0169, 0x0017 },
625 	{ 0x0180, 0x2000 },
626 	{ 0x0181, 0x0000 },
627 	{ 0x0182, 0x0000 },
628 	{ 0x0183, 0x2000 },
629 	{ 0x0184, 0x0000 },
630 	{ 0x0185, 0x0000 },
631 	{ 0x01b0, 0x4b30 },
632 	{ 0x01b1, 0x0000 },
633 	{ 0x01b2, 0xd870 },
634 	{ 0x01b3, 0x0000 },
635 	{ 0x01b4, 0x0030 },
636 	{ 0x01b5, 0x5757 },
637 	{ 0x01b6, 0x5757 },
638 	{ 0x01b7, 0x5757 },
639 	{ 0x01b8, 0x5757 },
640 	{ 0x01c0, 0x433d },
641 	{ 0x01c1, 0x0540 },
642 	{ 0x01c2, 0x0000 },
643 	{ 0x01c3, 0x0000 },
644 	{ 0x01c4, 0x0000 },
645 	{ 0x01c5, 0x0009 },
646 	{ 0x01c6, 0x0018 },
647 	{ 0x01c7, 0x002a },
648 	{ 0x01c8, 0x004c },
649 	{ 0x01c9, 0x0097 },
650 	{ 0x01ca, 0x01c3 },
651 	{ 0x01cb, 0x03e9 },
652 	{ 0x01cc, 0x1389 },
653 	{ 0x01cd, 0xc351 },
654 	{ 0x01ce, 0x0000 },
655 	{ 0x01cf, 0x0000 },
656 	{ 0x01d0, 0x0000 },
657 	{ 0x01d1, 0x0000 },
658 	{ 0x01d2, 0x0000 },
659 	{ 0x01d3, 0x003c },
660 	{ 0x01d4, 0x5757 },
661 	{ 0x01d5, 0x5757 },
662 	{ 0x01d6, 0x5757 },
663 	{ 0x01d7, 0x5757 },
664 	{ 0x01d8, 0x5757 },
665 	{ 0x01d9, 0x5757 },
666 	{ 0x01da, 0x0000 },
667 	{ 0x01db, 0x0000 },
668 	{ 0x01dd, 0x0009 },
669 	{ 0x01de, 0x7f00 },
670 	{ 0x01df, 0x00c8 },
671 	{ 0x01e0, 0x0691 },
672 	{ 0x01e1, 0x0000 },
673 	{ 0x01e2, 0x0000 },
674 	{ 0x01e3, 0x0000 },
675 	{ 0x01e4, 0x0000 },
676 	{ 0x01e5, 0x0040 },
677 	{ 0x01e6, 0x0000 },
678 	{ 0x01e7, 0x0000 },
679 	{ 0x01e8, 0x0000 },
680 	{ 0x01ea, 0x0000 },
681 	{ 0x01eb, 0x0000 },
682 	{ 0x01ec, 0x0000 },
683 	{ 0x01ed, 0x0000 },
684 	{ 0x01ee, 0x0000 },
685 	{ 0x01ef, 0x0000 },
686 	{ 0x01f0, 0x0000 },
687 	{ 0x01f1, 0x0000 },
688 	{ 0x01f2, 0x0000 },
689 	{ 0x0200, 0x0000 },
690 	{ 0x0201, 0x2244 },
691 	{ 0x0202, 0xaaaa },
692 	{ 0x0250, 0x8010 },
693 	{ 0x0251, 0x0000 },
694 	{ 0x0252, 0x028a },
695 	{ 0x02fa, 0x0000 },
696 	{ 0x02fb, 0x00a4 },
697 	{ 0x02fc, 0x0300 },
698 	{ 0x0300, 0x0000 },
699 	{ 0x03d0, 0x0000 },
700 	{ 0x03d1, 0x0000 },
701 	{ 0x03d2, 0x0000 },
702 	{ 0x03d3, 0x0000 },
703 	{ 0x03d4, 0x2000 },
704 	{ 0x03d5, 0x2000 },
705 	{ 0x03d6, 0x0000 },
706 	{ 0x03d7, 0x0000 },
707 	{ 0x03d8, 0x2000 },
708 	{ 0x03d9, 0x2000 },
709 	{ 0x03da, 0x2000 },
710 	{ 0x03db, 0x2000 },
711 	{ 0x03dc, 0x0000 },
712 	{ 0x03dd, 0x0000 },
713 	{ 0x03de, 0x0000 },
714 	{ 0x03df, 0x2000 },
715 	{ 0x03e0, 0x0000 },
716 	{ 0x03e1, 0x0000 },
717 	{ 0x03e2, 0x0000 },
718 	{ 0x03e3, 0x0000 },
719 	{ 0x03e4, 0x0000 },
720 	{ 0x03e5, 0x0000 },
721 	{ 0x03e6, 0x0000 },
722 	{ 0x03e7, 0x0000 },
723 	{ 0x03e8, 0x0000 },
724 	{ 0x03e9, 0x0000 },
725 	{ 0x03ea, 0x0000 },
726 	{ 0x03eb, 0x0000 },
727 	{ 0x03ec, 0x0000 },
728 	{ 0x03ed, 0x0000 },
729 	{ 0x03ee, 0x0000 },
730 	{ 0x03ef, 0x0000 },
731 	{ 0x03f0, 0x0800 },
732 	{ 0x03f1, 0x0800 },
733 	{ 0x03f2, 0x0800 },
734 	{ 0x03f3, 0x0800 },
735 };
736 
737 static bool rt5663_volatile_register(struct device *dev, unsigned int reg)
738 {
739 	switch (reg) {
740 	case RT5663_RESET:
741 	case RT5663_SIL_DET_CTL:
742 	case RT5663_HP_IMP_GAIN_2:
743 	case RT5663_AD_DA_MIXER:
744 	case RT5663_FRAC_DIV_2:
745 	case RT5663_MICBIAS_1:
746 	case RT5663_ASRC_11_2:
747 	case RT5663_ADC_EQ_1:
748 	case RT5663_INT_ST_1:
749 	case RT5663_INT_ST_2:
750 	case RT5663_GPIO_STA1:
751 	case RT5663_SIN_GEN_1:
752 	case RT5663_IL_CMD_1:
753 	case RT5663_IL_CMD_5:
754 	case RT5663_IL_CMD_PWRSAV1:
755 	case RT5663_EM_JACK_TYPE_1:
756 	case RT5663_EM_JACK_TYPE_2:
757 	case RT5663_EM_JACK_TYPE_3:
758 	case RT5663_JD_CTRL2:
759 	case RT5663_VENDOR_ID:
760 	case RT5663_VENDOR_ID_1:
761 	case RT5663_VENDOR_ID_2:
762 	case RT5663_PLL_INT_REG:
763 	case RT5663_SOFT_RAMP:
764 	case RT5663_STO_DRE_1:
765 	case RT5663_STO_DRE_5:
766 	case RT5663_STO_DRE_6:
767 	case RT5663_STO_DRE_7:
768 	case RT5663_MIC_DECRO_1:
769 	case RT5663_MIC_DECRO_4:
770 	case RT5663_HP_IMP_SEN_1:
771 	case RT5663_HP_IMP_SEN_3:
772 	case RT5663_HP_IMP_SEN_4:
773 	case RT5663_HP_IMP_SEN_5:
774 	case RT5663_HP_CALIB_1_1:
775 	case RT5663_HP_CALIB_9:
776 	case RT5663_HP_CALIB_ST1:
777 	case RT5663_HP_CALIB_ST2:
778 	case RT5663_HP_CALIB_ST3:
779 	case RT5663_HP_CALIB_ST4:
780 	case RT5663_HP_CALIB_ST5:
781 	case RT5663_HP_CALIB_ST6:
782 	case RT5663_HP_CALIB_ST7:
783 	case RT5663_HP_CALIB_ST8:
784 	case RT5663_HP_CALIB_ST9:
785 	case RT5663_ANA_JD:
786 		return true;
787 	default:
788 		return false;
789 	}
790 }
791 
792 static bool rt5663_readable_register(struct device *dev, unsigned int reg)
793 {
794 	switch (reg) {
795 	case RT5663_RESET:
796 	case RT5663_HP_OUT_EN:
797 	case RT5663_HP_LCH_DRE:
798 	case RT5663_HP_RCH_DRE:
799 	case RT5663_CALIB_BST:
800 	case RT5663_RECMIX:
801 	case RT5663_SIL_DET_CTL:
802 	case RT5663_PWR_SAV_SILDET:
803 	case RT5663_SIDETONE_CTL:
804 	case RT5663_STO1_DAC_DIG_VOL:
805 	case RT5663_STO1_ADC_DIG_VOL:
806 	case RT5663_STO1_BOOST:
807 	case RT5663_HP_IMP_GAIN_1:
808 	case RT5663_HP_IMP_GAIN_2:
809 	case RT5663_STO1_ADC_MIXER:
810 	case RT5663_AD_DA_MIXER:
811 	case RT5663_STO_DAC_MIXER:
812 	case RT5663_DIG_SIDE_MIXER:
813 	case RT5663_BYPASS_STO_DAC:
814 	case RT5663_CALIB_REC_MIX:
815 	case RT5663_PWR_DIG_1:
816 	case RT5663_PWR_DIG_2:
817 	case RT5663_PWR_ANLG_1:
818 	case RT5663_PWR_ANLG_2:
819 	case RT5663_PWR_ANLG_3:
820 	case RT5663_PWR_MIXER:
821 	case RT5663_SIG_CLK_DET:
822 	case RT5663_PRE_DIV_GATING_1:
823 	case RT5663_PRE_DIV_GATING_2:
824 	case RT5663_I2S1_SDP:
825 	case RT5663_ADDA_CLK_1:
826 	case RT5663_ADDA_RST:
827 	case RT5663_FRAC_DIV_1:
828 	case RT5663_FRAC_DIV_2:
829 	case RT5663_TDM_1:
830 	case RT5663_TDM_2:
831 	case RT5663_TDM_3:
832 	case RT5663_TDM_4:
833 	case RT5663_TDM_5:
834 	case RT5663_GLB_CLK:
835 	case RT5663_PLL_1:
836 	case RT5663_PLL_2:
837 	case RT5663_ASRC_1:
838 	case RT5663_ASRC_2:
839 	case RT5663_ASRC_4:
840 	case RT5663_DUMMY_REG:
841 	case RT5663_ASRC_8:
842 	case RT5663_ASRC_9:
843 	case RT5663_ASRC_11:
844 	case RT5663_DEPOP_1:
845 	case RT5663_DEPOP_2:
846 	case RT5663_DEPOP_3:
847 	case RT5663_HP_CHARGE_PUMP_1:
848 	case RT5663_HP_CHARGE_PUMP_2:
849 	case RT5663_MICBIAS_1:
850 	case RT5663_RC_CLK:
851 	case RT5663_ASRC_11_2:
852 	case RT5663_DUMMY_REG_2:
853 	case RT5663_REC_PATH_GAIN:
854 	case RT5663_AUTO_1MRC_CLK:
855 	case RT5663_ADC_EQ_1:
856 	case RT5663_ADC_EQ_2:
857 	case RT5663_IRQ_1:
858 	case RT5663_IRQ_2:
859 	case RT5663_IRQ_3:
860 	case RT5663_IRQ_4:
861 	case RT5663_IRQ_5:
862 	case RT5663_INT_ST_1:
863 	case RT5663_INT_ST_2:
864 	case RT5663_GPIO_1:
865 	case RT5663_GPIO_2:
866 	case RT5663_GPIO_STA1:
867 	case RT5663_SIN_GEN_1:
868 	case RT5663_SIN_GEN_2:
869 	case RT5663_SIN_GEN_3:
870 	case RT5663_SOF_VOL_ZC1:
871 	case RT5663_IL_CMD_1:
872 	case RT5663_IL_CMD_2:
873 	case RT5663_IL_CMD_3:
874 	case RT5663_IL_CMD_4:
875 	case RT5663_IL_CMD_5:
876 	case RT5663_IL_CMD_6:
877 	case RT5663_IL_CMD_7:
878 	case RT5663_IL_CMD_8:
879 	case RT5663_IL_CMD_PWRSAV1:
880 	case RT5663_IL_CMD_PWRSAV2:
881 	case RT5663_EM_JACK_TYPE_1:
882 	case RT5663_EM_JACK_TYPE_2:
883 	case RT5663_EM_JACK_TYPE_3:
884 	case RT5663_EM_JACK_TYPE_4:
885 	case RT5663_EM_JACK_TYPE_5:
886 	case RT5663_EM_JACK_TYPE_6:
887 	case RT5663_STO1_HPF_ADJ1:
888 	case RT5663_STO1_HPF_ADJ2:
889 	case RT5663_FAST_OFF_MICBIAS:
890 	case RT5663_JD_CTRL1:
891 	case RT5663_JD_CTRL2:
892 	case RT5663_DIG_MISC:
893 	case RT5663_VENDOR_ID:
894 	case RT5663_VENDOR_ID_1:
895 	case RT5663_VENDOR_ID_2:
896 	case RT5663_DIG_VOL_ZCD:
897 	case RT5663_ANA_BIAS_CUR_1:
898 	case RT5663_ANA_BIAS_CUR_2:
899 	case RT5663_ANA_BIAS_CUR_3:
900 	case RT5663_ANA_BIAS_CUR_4:
901 	case RT5663_ANA_BIAS_CUR_5:
902 	case RT5663_ANA_BIAS_CUR_6:
903 	case RT5663_BIAS_CUR_5:
904 	case RT5663_BIAS_CUR_6:
905 	case RT5663_BIAS_CUR_7:
906 	case RT5663_BIAS_CUR_8:
907 	case RT5663_DACREF_LDO:
908 	case RT5663_DUMMY_REG_3:
909 	case RT5663_BIAS_CUR_9:
910 	case RT5663_DUMMY_REG_4:
911 	case RT5663_VREFADJ_OP:
912 	case RT5663_VREF_RECMIX:
913 	case RT5663_CHARGE_PUMP_1:
914 	case RT5663_CHARGE_PUMP_1_2:
915 	case RT5663_CHARGE_PUMP_1_3:
916 	case RT5663_CHARGE_PUMP_2:
917 	case RT5663_DIG_IN_PIN1:
918 	case RT5663_PAD_DRV_CTL:
919 	case RT5663_PLL_INT_REG:
920 	case RT5663_CHOP_DAC_L:
921 	case RT5663_CHOP_ADC:
922 	case RT5663_CALIB_ADC:
923 	case RT5663_CHOP_DAC_R:
924 	case RT5663_DUMMY_CTL_DACLR:
925 	case RT5663_DUMMY_REG_5:
926 	case RT5663_SOFT_RAMP:
927 	case RT5663_TEST_MODE_1:
928 	case RT5663_TEST_MODE_2:
929 	case RT5663_TEST_MODE_3:
930 	case RT5663_STO_DRE_1:
931 	case RT5663_STO_DRE_2:
932 	case RT5663_STO_DRE_3:
933 	case RT5663_STO_DRE_4:
934 	case RT5663_STO_DRE_5:
935 	case RT5663_STO_DRE_6:
936 	case RT5663_STO_DRE_7:
937 	case RT5663_STO_DRE_8:
938 	case RT5663_STO_DRE_9:
939 	case RT5663_STO_DRE_10:
940 	case RT5663_MIC_DECRO_1:
941 	case RT5663_MIC_DECRO_2:
942 	case RT5663_MIC_DECRO_3:
943 	case RT5663_MIC_DECRO_4:
944 	case RT5663_MIC_DECRO_5:
945 	case RT5663_MIC_DECRO_6:
946 	case RT5663_HP_DECRO_1:
947 	case RT5663_HP_DECRO_2:
948 	case RT5663_HP_DECRO_3:
949 	case RT5663_HP_DECRO_4:
950 	case RT5663_HP_DECOUP:
951 	case RT5663_HP_IMP_SEN_MAP8:
952 	case RT5663_HP_IMP_SEN_MAP9:
953 	case RT5663_HP_IMP_SEN_MAP10:
954 	case RT5663_HP_IMP_SEN_MAP11:
955 	case RT5663_HP_IMP_SEN_1:
956 	case RT5663_HP_IMP_SEN_2:
957 	case RT5663_HP_IMP_SEN_3:
958 	case RT5663_HP_IMP_SEN_4:
959 	case RT5663_HP_IMP_SEN_5:
960 	case RT5663_HP_IMP_SEN_6:
961 	case RT5663_HP_IMP_SEN_7:
962 	case RT5663_HP_IMP_SEN_8:
963 	case RT5663_HP_IMP_SEN_9:
964 	case RT5663_HP_IMP_SEN_10:
965 	case RT5663_HP_IMP_SEN_11:
966 	case RT5663_HP_IMP_SEN_12:
967 	case RT5663_HP_IMP_SEN_13:
968 	case RT5663_HP_IMP_SEN_14:
969 	case RT5663_HP_IMP_SEN_15:
970 	case RT5663_HP_IMP_SEN_16:
971 	case RT5663_HP_IMP_SEN_17:
972 	case RT5663_HP_IMP_SEN_18:
973 	case RT5663_HP_IMP_SEN_19:
974 	case RT5663_HP_IMPSEN_DIG5:
975 	case RT5663_HP_IMPSEN_MAP1:
976 	case RT5663_HP_IMPSEN_MAP2:
977 	case RT5663_HP_IMPSEN_MAP3:
978 	case RT5663_HP_IMPSEN_MAP4:
979 	case RT5663_HP_IMPSEN_MAP5:
980 	case RT5663_HP_IMPSEN_MAP7:
981 	case RT5663_HP_LOGIC_1:
982 	case RT5663_HP_LOGIC_2:
983 	case RT5663_HP_CALIB_1:
984 	case RT5663_HP_CALIB_1_1:
985 	case RT5663_HP_CALIB_2:
986 	case RT5663_HP_CALIB_3:
987 	case RT5663_HP_CALIB_4:
988 	case RT5663_HP_CALIB_5:
989 	case RT5663_HP_CALIB_5_1:
990 	case RT5663_HP_CALIB_6:
991 	case RT5663_HP_CALIB_7:
992 	case RT5663_HP_CALIB_9:
993 	case RT5663_HP_CALIB_10:
994 	case RT5663_HP_CALIB_11:
995 	case RT5663_HP_CALIB_ST1:
996 	case RT5663_HP_CALIB_ST2:
997 	case RT5663_HP_CALIB_ST3:
998 	case RT5663_HP_CALIB_ST4:
999 	case RT5663_HP_CALIB_ST5:
1000 	case RT5663_HP_CALIB_ST6:
1001 	case RT5663_HP_CALIB_ST7:
1002 	case RT5663_HP_CALIB_ST8:
1003 	case RT5663_HP_CALIB_ST9:
1004 	case RT5663_HP_AMP_DET:
1005 	case RT5663_DUMMY_REG_6:
1006 	case RT5663_HP_BIAS:
1007 	case RT5663_CBJ_1:
1008 	case RT5663_CBJ_2:
1009 	case RT5663_CBJ_3:
1010 	case RT5663_DUMMY_1:
1011 	case RT5663_DUMMY_2:
1012 	case RT5663_DUMMY_3:
1013 	case RT5663_ANA_JD:
1014 	case RT5663_ADC_LCH_LPF1_A1:
1015 	case RT5663_ADC_RCH_LPF1_A1:
1016 	case RT5663_ADC_LCH_LPF1_H0:
1017 	case RT5663_ADC_RCH_LPF1_H0:
1018 	case RT5663_ADC_LCH_BPF1_A1:
1019 	case RT5663_ADC_RCH_BPF1_A1:
1020 	case RT5663_ADC_LCH_BPF1_A2:
1021 	case RT5663_ADC_RCH_BPF1_A2:
1022 	case RT5663_ADC_LCH_BPF1_H0:
1023 	case RT5663_ADC_RCH_BPF1_H0:
1024 	case RT5663_ADC_LCH_BPF2_A1:
1025 	case RT5663_ADC_RCH_BPF2_A1:
1026 	case RT5663_ADC_LCH_BPF2_A2:
1027 	case RT5663_ADC_RCH_BPF2_A2:
1028 	case RT5663_ADC_LCH_BPF2_H0:
1029 	case RT5663_ADC_RCH_BPF2_H0:
1030 	case RT5663_ADC_LCH_BPF3_A1:
1031 	case RT5663_ADC_RCH_BPF3_A1:
1032 	case RT5663_ADC_LCH_BPF3_A2:
1033 	case RT5663_ADC_RCH_BPF3_A2:
1034 	case RT5663_ADC_LCH_BPF3_H0:
1035 	case RT5663_ADC_RCH_BPF3_H0:
1036 	case RT5663_ADC_LCH_BPF4_A1:
1037 	case RT5663_ADC_RCH_BPF4_A1:
1038 	case RT5663_ADC_LCH_BPF4_A2:
1039 	case RT5663_ADC_RCH_BPF4_A2:
1040 	case RT5663_ADC_LCH_BPF4_H0:
1041 	case RT5663_ADC_RCH_BPF4_H0:
1042 	case RT5663_ADC_LCH_HPF1_A1:
1043 	case RT5663_ADC_RCH_HPF1_A1:
1044 	case RT5663_ADC_LCH_HPF1_H0:
1045 	case RT5663_ADC_RCH_HPF1_H0:
1046 	case RT5663_ADC_EQ_PRE_VOL_L:
1047 	case RT5663_ADC_EQ_PRE_VOL_R:
1048 	case RT5663_ADC_EQ_POST_VOL_L:
1049 	case RT5663_ADC_EQ_POST_VOL_R:
1050 		return true;
1051 	default:
1052 		return false;
1053 	}
1054 }
1055 
1056 static bool rt5663_v2_volatile_register(struct device *dev, unsigned int reg)
1057 {
1058 	switch (reg) {
1059 	case RT5663_RESET:
1060 	case RT5663_CBJ_TYPE_2:
1061 	case RT5663_PDM_OUT_CTL:
1062 	case RT5663_PDM_I2C_DATA_CTL1:
1063 	case RT5663_PDM_I2C_DATA_CTL4:
1064 	case RT5663_ALC_BK_GAIN:
1065 	case RT5663_PLL_2:
1066 	case RT5663_MICBIAS_1:
1067 	case RT5663_ADC_EQ_1:
1068 	case RT5663_INT_ST_1:
1069 	case RT5663_GPIO_STA2:
1070 	case RT5663_IL_CMD_1:
1071 	case RT5663_IL_CMD_5:
1072 	case RT5663_A_JD_CTRL:
1073 	case RT5663_JD_CTRL2:
1074 	case RT5663_VENDOR_ID:
1075 	case RT5663_VENDOR_ID_1:
1076 	case RT5663_VENDOR_ID_2:
1077 	case RT5663_STO_DRE_1:
1078 	case RT5663_STO_DRE_5:
1079 	case RT5663_STO_DRE_6:
1080 	case RT5663_STO_DRE_7:
1081 	case RT5663_MONO_DYNA_6:
1082 	case RT5663_STO1_SIL_DET:
1083 	case RT5663_MONOL_SIL_DET:
1084 	case RT5663_MONOR_SIL_DET:
1085 	case RT5663_STO2_DAC_SIL:
1086 	case RT5663_MONO_AMP_CAL_ST1:
1087 	case RT5663_MONO_AMP_CAL_ST2:
1088 	case RT5663_MONO_AMP_CAL_ST3:
1089 	case RT5663_MONO_AMP_CAL_ST4:
1090 	case RT5663_HP_IMP_SEN_2:
1091 	case RT5663_HP_IMP_SEN_3:
1092 	case RT5663_HP_IMP_SEN_4:
1093 	case RT5663_HP_IMP_SEN_10:
1094 	case RT5663_HP_CALIB_1:
1095 	case RT5663_HP_CALIB_10:
1096 	case RT5663_HP_CALIB_ST1:
1097 	case RT5663_HP_CALIB_ST4:
1098 	case RT5663_HP_CALIB_ST5:
1099 	case RT5663_HP_CALIB_ST6:
1100 	case RT5663_HP_CALIB_ST7:
1101 	case RT5663_HP_CALIB_ST8:
1102 	case RT5663_HP_CALIB_ST9:
1103 	case RT5663_HP_CALIB_ST10:
1104 	case RT5663_HP_CALIB_ST11:
1105 		return true;
1106 	default:
1107 		return false;
1108 	}
1109 }
1110 
1111 static bool rt5663_v2_readable_register(struct device *dev, unsigned int reg)
1112 {
1113 	switch (reg) {
1114 	case RT5663_LOUT_CTRL:
1115 	case RT5663_HP_AMP_2:
1116 	case RT5663_MONO_OUT:
1117 	case RT5663_MONO_GAIN:
1118 	case RT5663_AEC_BST:
1119 	case RT5663_IN1_IN2:
1120 	case RT5663_IN3_IN4:
1121 	case RT5663_INL1_INR1:
1122 	case RT5663_CBJ_TYPE_2:
1123 	case RT5663_CBJ_TYPE_3:
1124 	case RT5663_CBJ_TYPE_4:
1125 	case RT5663_CBJ_TYPE_5:
1126 	case RT5663_CBJ_TYPE_8:
1127 	case RT5663_DAC3_DIG_VOL:
1128 	case RT5663_DAC3_CTRL:
1129 	case RT5663_MONO_ADC_DIG_VOL:
1130 	case RT5663_STO2_ADC_DIG_VOL:
1131 	case RT5663_MONO_ADC_BST_GAIN:
1132 	case RT5663_STO2_ADC_BST_GAIN:
1133 	case RT5663_SIDETONE_CTRL:
1134 	case RT5663_MONO1_ADC_MIXER:
1135 	case RT5663_STO2_ADC_MIXER:
1136 	case RT5663_MONO_DAC_MIXER:
1137 	case RT5663_DAC2_SRC_CTRL:
1138 	case RT5663_IF_3_4_DATA_CTL:
1139 	case RT5663_IF_5_DATA_CTL:
1140 	case RT5663_PDM_OUT_CTL:
1141 	case RT5663_PDM_I2C_DATA_CTL1:
1142 	case RT5663_PDM_I2C_DATA_CTL2:
1143 	case RT5663_PDM_I2C_DATA_CTL3:
1144 	case RT5663_PDM_I2C_DATA_CTL4:
1145 	case RT5663_RECMIX1_NEW:
1146 	case RT5663_RECMIX1L_0:
1147 	case RT5663_RECMIX1L:
1148 	case RT5663_RECMIX1R_0:
1149 	case RT5663_RECMIX1R:
1150 	case RT5663_RECMIX2_NEW:
1151 	case RT5663_RECMIX2_L_2:
1152 	case RT5663_RECMIX2_R:
1153 	case RT5663_RECMIX2_R_2:
1154 	case RT5663_CALIB_REC_LR:
1155 	case RT5663_ALC_BK_GAIN:
1156 	case RT5663_MONOMIX_GAIN:
1157 	case RT5663_MONOMIX_IN_GAIN:
1158 	case RT5663_OUT_MIXL_GAIN:
1159 	case RT5663_OUT_LMIX_IN_GAIN:
1160 	case RT5663_OUT_RMIX_IN_GAIN:
1161 	case RT5663_OUT_RMIX_IN_GAIN1:
1162 	case RT5663_LOUT_MIXER_CTRL:
1163 	case RT5663_PWR_VOL:
1164 	case RT5663_ADCDAC_RST:
1165 	case RT5663_I2S34_SDP:
1166 	case RT5663_I2S5_SDP:
1167 	case RT5663_TDM_6:
1168 	case RT5663_TDM_7:
1169 	case RT5663_TDM_8:
1170 	case RT5663_TDM_9:
1171 	case RT5663_ASRC_3:
1172 	case RT5663_ASRC_6:
1173 	case RT5663_ASRC_7:
1174 	case RT5663_PLL_TRK_13:
1175 	case RT5663_I2S_M_CLK_CTL:
1176 	case RT5663_FDIV_I2S34_M_CLK:
1177 	case RT5663_FDIV_I2S34_M_CLK2:
1178 	case RT5663_FDIV_I2S5_M_CLK:
1179 	case RT5663_FDIV_I2S5_M_CLK2:
1180 	case RT5663_V2_IRQ_4:
1181 	case RT5663_GPIO_3:
1182 	case RT5663_GPIO_4:
1183 	case RT5663_GPIO_STA2:
1184 	case RT5663_HP_AMP_DET1:
1185 	case RT5663_HP_AMP_DET2:
1186 	case RT5663_HP_AMP_DET3:
1187 	case RT5663_MID_BD_HP_AMP:
1188 	case RT5663_LOW_BD_HP_AMP:
1189 	case RT5663_SOF_VOL_ZC2:
1190 	case RT5663_ADC_STO2_ADJ1:
1191 	case RT5663_ADC_STO2_ADJ2:
1192 	case RT5663_A_JD_CTRL:
1193 	case RT5663_JD1_TRES_CTRL:
1194 	case RT5663_JD2_TRES_CTRL:
1195 	case RT5663_V2_JD_CTRL2:
1196 	case RT5663_DUM_REG_2:
1197 	case RT5663_DUM_REG_3:
1198 	case RT5663_VENDOR_ID:
1199 	case RT5663_VENDOR_ID_1:
1200 	case RT5663_VENDOR_ID_2:
1201 	case RT5663_DACADC_DIG_VOL2:
1202 	case RT5663_DIG_IN_PIN2:
1203 	case RT5663_PAD_DRV_CTL1:
1204 	case RT5663_SOF_RAM_DEPOP:
1205 	case RT5663_VOL_TEST:
1206 	case RT5663_TEST_MODE_4:
1207 	case RT5663_TEST_MODE_5:
1208 	case RT5663_STO_DRE_9:
1209 	case RT5663_MONO_DYNA_1:
1210 	case RT5663_MONO_DYNA_2:
1211 	case RT5663_MONO_DYNA_3:
1212 	case RT5663_MONO_DYNA_4:
1213 	case RT5663_MONO_DYNA_5:
1214 	case RT5663_MONO_DYNA_6:
1215 	case RT5663_STO1_SIL_DET:
1216 	case RT5663_MONOL_SIL_DET:
1217 	case RT5663_MONOR_SIL_DET:
1218 	case RT5663_STO2_DAC_SIL:
1219 	case RT5663_PWR_SAV_CTL1:
1220 	case RT5663_PWR_SAV_CTL2:
1221 	case RT5663_PWR_SAV_CTL3:
1222 	case RT5663_PWR_SAV_CTL4:
1223 	case RT5663_PWR_SAV_CTL5:
1224 	case RT5663_PWR_SAV_CTL6:
1225 	case RT5663_MONO_AMP_CAL1:
1226 	case RT5663_MONO_AMP_CAL2:
1227 	case RT5663_MONO_AMP_CAL3:
1228 	case RT5663_MONO_AMP_CAL4:
1229 	case RT5663_MONO_AMP_CAL5:
1230 	case RT5663_MONO_AMP_CAL6:
1231 	case RT5663_MONO_AMP_CAL7:
1232 	case RT5663_MONO_AMP_CAL_ST1:
1233 	case RT5663_MONO_AMP_CAL_ST2:
1234 	case RT5663_MONO_AMP_CAL_ST3:
1235 	case RT5663_MONO_AMP_CAL_ST4:
1236 	case RT5663_MONO_AMP_CAL_ST5:
1237 	case RT5663_V2_HP_IMP_SEN_13:
1238 	case RT5663_V2_HP_IMP_SEN_14:
1239 	case RT5663_V2_HP_IMP_SEN_6:
1240 	case RT5663_V2_HP_IMP_SEN_7:
1241 	case RT5663_V2_HP_IMP_SEN_8:
1242 	case RT5663_V2_HP_IMP_SEN_9:
1243 	case RT5663_V2_HP_IMP_SEN_10:
1244 	case RT5663_HP_LOGIC_3:
1245 	case RT5663_HP_CALIB_ST10:
1246 	case RT5663_HP_CALIB_ST11:
1247 	case RT5663_PRO_REG_TBL_4:
1248 	case RT5663_PRO_REG_TBL_5:
1249 	case RT5663_PRO_REG_TBL_6:
1250 	case RT5663_PRO_REG_TBL_7:
1251 	case RT5663_PRO_REG_TBL_8:
1252 	case RT5663_PRO_REG_TBL_9:
1253 	case RT5663_SAR_ADC_INL_1:
1254 	case RT5663_SAR_ADC_INL_2:
1255 	case RT5663_SAR_ADC_INL_3:
1256 	case RT5663_SAR_ADC_INL_4:
1257 	case RT5663_SAR_ADC_INL_5:
1258 	case RT5663_SAR_ADC_INL_6:
1259 	case RT5663_SAR_ADC_INL_7:
1260 	case RT5663_SAR_ADC_INL_8:
1261 	case RT5663_SAR_ADC_INL_9:
1262 	case RT5663_SAR_ADC_INL_10:
1263 	case RT5663_SAR_ADC_INL_11:
1264 	case RT5663_SAR_ADC_INL_12:
1265 	case RT5663_DRC_CTRL_1:
1266 	case RT5663_DRC1_CTRL_2:
1267 	case RT5663_DRC1_CTRL_3:
1268 	case RT5663_DRC1_CTRL_4:
1269 	case RT5663_DRC1_CTRL_5:
1270 	case RT5663_DRC1_CTRL_6:
1271 	case RT5663_DRC1_HD_CTRL_1:
1272 	case RT5663_DRC1_HD_CTRL_2:
1273 	case RT5663_DRC1_PRI_REG_1:
1274 	case RT5663_DRC1_PRI_REG_2:
1275 	case RT5663_DRC1_PRI_REG_3:
1276 	case RT5663_DRC1_PRI_REG_4:
1277 	case RT5663_DRC1_PRI_REG_5:
1278 	case RT5663_DRC1_PRI_REG_6:
1279 	case RT5663_DRC1_PRI_REG_7:
1280 	case RT5663_DRC1_PRI_REG_8:
1281 	case RT5663_ALC_PGA_CTL_1:
1282 	case RT5663_ALC_PGA_CTL_2:
1283 	case RT5663_ALC_PGA_CTL_3:
1284 	case RT5663_ALC_PGA_CTL_4:
1285 	case RT5663_ALC_PGA_CTL_5:
1286 	case RT5663_ALC_PGA_CTL_6:
1287 	case RT5663_ALC_PGA_CTL_7:
1288 	case RT5663_ALC_PGA_CTL_8:
1289 	case RT5663_ALC_PGA_REG_1:
1290 	case RT5663_ALC_PGA_REG_2:
1291 	case RT5663_ALC_PGA_REG_3:
1292 	case RT5663_ADC_EQ_RECOV_1:
1293 	case RT5663_ADC_EQ_RECOV_2:
1294 	case RT5663_ADC_EQ_RECOV_3:
1295 	case RT5663_ADC_EQ_RECOV_4:
1296 	case RT5663_ADC_EQ_RECOV_5:
1297 	case RT5663_ADC_EQ_RECOV_6:
1298 	case RT5663_ADC_EQ_RECOV_7:
1299 	case RT5663_ADC_EQ_RECOV_8:
1300 	case RT5663_ADC_EQ_RECOV_9:
1301 	case RT5663_ADC_EQ_RECOV_10:
1302 	case RT5663_ADC_EQ_RECOV_11:
1303 	case RT5663_ADC_EQ_RECOV_12:
1304 	case RT5663_ADC_EQ_RECOV_13:
1305 	case RT5663_VID_HIDDEN:
1306 	case RT5663_VID_CUSTOMER:
1307 	case RT5663_SCAN_MODE:
1308 	case RT5663_I2C_BYPA:
1309 		return true;
1310 	case RT5663_TDM_1:
1311 	case RT5663_DEPOP_3:
1312 	case RT5663_ASRC_11_2:
1313 	case RT5663_INT_ST_2:
1314 	case RT5663_GPIO_STA1:
1315 	case RT5663_SIN_GEN_1:
1316 	case RT5663_SIN_GEN_2:
1317 	case RT5663_SIN_GEN_3:
1318 	case RT5663_IL_CMD_PWRSAV1:
1319 	case RT5663_IL_CMD_PWRSAV2:
1320 	case RT5663_EM_JACK_TYPE_1:
1321 	case RT5663_EM_JACK_TYPE_2:
1322 	case RT5663_EM_JACK_TYPE_3:
1323 	case RT5663_EM_JACK_TYPE_4:
1324 	case RT5663_FAST_OFF_MICBIAS:
1325 	case RT5663_ANA_BIAS_CUR_1:
1326 	case RT5663_ANA_BIAS_CUR_2:
1327 	case RT5663_BIAS_CUR_9:
1328 	case RT5663_DUMMY_REG_4:
1329 	case RT5663_VREF_RECMIX:
1330 	case RT5663_CHARGE_PUMP_1_2:
1331 	case RT5663_CHARGE_PUMP_1_3:
1332 	case RT5663_CHARGE_PUMP_2:
1333 	case RT5663_CHOP_DAC_R:
1334 	case RT5663_DUMMY_CTL_DACLR:
1335 	case RT5663_DUMMY_REG_5:
1336 	case RT5663_SOFT_RAMP:
1337 	case RT5663_TEST_MODE_1:
1338 	case RT5663_STO_DRE_10:
1339 	case RT5663_MIC_DECRO_1:
1340 	case RT5663_MIC_DECRO_2:
1341 	case RT5663_MIC_DECRO_3:
1342 	case RT5663_MIC_DECRO_4:
1343 	case RT5663_MIC_DECRO_5:
1344 	case RT5663_MIC_DECRO_6:
1345 	case RT5663_HP_DECRO_1:
1346 	case RT5663_HP_DECRO_2:
1347 	case RT5663_HP_DECRO_3:
1348 	case RT5663_HP_DECRO_4:
1349 	case RT5663_HP_DECOUP:
1350 	case RT5663_HP_IMPSEN_MAP4:
1351 	case RT5663_HP_IMPSEN_MAP5:
1352 	case RT5663_HP_IMPSEN_MAP7:
1353 	case RT5663_HP_CALIB_1:
1354 	case RT5663_CBJ_1:
1355 	case RT5663_CBJ_2:
1356 	case RT5663_CBJ_3:
1357 		return false;
1358 	default:
1359 		return rt5663_readable_register(dev, reg);
1360 	}
1361 }
1362 
1363 static const DECLARE_TLV_DB_SCALE(rt5663_hp_vol_tlv, -2400, 150, 0);
1364 static const DECLARE_TLV_DB_SCALE(rt5663_v2_hp_vol_tlv, -2250, 150, 0);
1365 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6525, 75, 0);
1366 static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0);
1367 
1368 /* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
1369 static const DECLARE_TLV_DB_RANGE(in_bst_tlv,
1370 	0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
1371 	1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
1372 	2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
1373 	3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
1374 	6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
1375 	7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
1376 	8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0)
1377 );
1378 
1379 /* Interface data select */
1380 static const char * const rt5663_if1_adc_data_select[] = {
1381 	"L/R", "R/L", "L/L", "R/R"
1382 };
1383 
1384 static SOC_ENUM_SINGLE_DECL(rt5663_if1_adc_enum, RT5663_TDM_2,
1385 	RT5663_DATA_SWAP_ADCDAT1_SHIFT, rt5663_if1_adc_data_select);
1386 
1387 static void rt5663_enable_push_button_irq(struct snd_soc_component *component,
1388 	bool enable)
1389 {
1390 	struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
1391 
1392 	if (enable) {
1393 		snd_soc_component_update_bits(component, RT5663_IL_CMD_6,
1394 			RT5663_EN_4BTN_INL_MASK, RT5663_EN_4BTN_INL_EN);
1395 		/* reset in-line command */
1396 		snd_soc_component_update_bits(component, RT5663_IL_CMD_6,
1397 			RT5663_RESET_4BTN_INL_MASK,
1398 			RT5663_RESET_4BTN_INL_RESET);
1399 		snd_soc_component_update_bits(component, RT5663_IL_CMD_6,
1400 			RT5663_RESET_4BTN_INL_MASK,
1401 			RT5663_RESET_4BTN_INL_NOR);
1402 		switch (rt5663->codec_ver) {
1403 		case CODEC_VER_1:
1404 			snd_soc_component_update_bits(component, RT5663_IRQ_3,
1405 				RT5663_V2_EN_IRQ_INLINE_MASK,
1406 				RT5663_V2_EN_IRQ_INLINE_NOR);
1407 			break;
1408 		case CODEC_VER_0:
1409 			snd_soc_component_update_bits(component, RT5663_IRQ_2,
1410 				RT5663_EN_IRQ_INLINE_MASK,
1411 				RT5663_EN_IRQ_INLINE_NOR);
1412 			break;
1413 		default:
1414 			dev_err(component->dev, "Unknown CODEC Version\n");
1415 		}
1416 	} else {
1417 		switch (rt5663->codec_ver) {
1418 		case CODEC_VER_1:
1419 			snd_soc_component_update_bits(component, RT5663_IRQ_3,
1420 				RT5663_V2_EN_IRQ_INLINE_MASK,
1421 				RT5663_V2_EN_IRQ_INLINE_BYP);
1422 			break;
1423 		case CODEC_VER_0:
1424 			snd_soc_component_update_bits(component, RT5663_IRQ_2,
1425 				RT5663_EN_IRQ_INLINE_MASK,
1426 				RT5663_EN_IRQ_INLINE_BYP);
1427 			break;
1428 		default:
1429 			dev_err(component->dev, "Unknown CODEC Version\n");
1430 		}
1431 		snd_soc_component_update_bits(component, RT5663_IL_CMD_6,
1432 			RT5663_EN_4BTN_INL_MASK, RT5663_EN_4BTN_INL_DIS);
1433 		/* reset in-line command */
1434 		snd_soc_component_update_bits(component, RT5663_IL_CMD_6,
1435 			RT5663_RESET_4BTN_INL_MASK,
1436 			RT5663_RESET_4BTN_INL_RESET);
1437 		snd_soc_component_update_bits(component, RT5663_IL_CMD_6,
1438 			RT5663_RESET_4BTN_INL_MASK,
1439 			RT5663_RESET_4BTN_INL_NOR);
1440 	}
1441 }
1442 
1443 /**
1444  * rt5663_v2_jack_detect - Detect headset.
1445  * @component: SoC audio component device.
1446  * @jack_insert: Jack insert or not.
1447  *
1448  * Detect whether is headset or not when jack inserted.
1449  *
1450  * Returns detect status.
1451  */
1452 
1453 static int rt5663_v2_jack_detect(struct snd_soc_component *component, int jack_insert)
1454 {
1455 	struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
1456 	struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
1457 	int val, i = 0, sleep_time[5] = {300, 150, 100, 50, 30};
1458 
1459 	dev_dbg(component->dev, "%s jack_insert:%d\n", __func__, jack_insert);
1460 	if (jack_insert) {
1461 		snd_soc_component_write(component, RT5663_CBJ_TYPE_2, 0x8040);
1462 		snd_soc_component_write(component, RT5663_CBJ_TYPE_3, 0x1484);
1463 
1464 		snd_soc_dapm_force_enable_pin(dapm, "MICBIAS1");
1465 		snd_soc_dapm_force_enable_pin(dapm, "MICBIAS2");
1466 		snd_soc_dapm_force_enable_pin(dapm, "Mic Det Power");
1467 		snd_soc_dapm_force_enable_pin(dapm, "CBJ Power");
1468 		snd_soc_dapm_sync(dapm);
1469 		snd_soc_component_update_bits(component, RT5663_RC_CLK,
1470 			RT5663_DIG_1M_CLK_MASK, RT5663_DIG_1M_CLK_EN);
1471 		snd_soc_component_update_bits(component, RT5663_RECMIX, 0x8, 0x8);
1472 
1473 		while (i < 5) {
1474 			msleep(sleep_time[i]);
1475 			val = snd_soc_component_read32(component, RT5663_CBJ_TYPE_2) & 0x0003;
1476 			if (val == 0x1 || val == 0x2 || val == 0x3)
1477 				break;
1478 			dev_dbg(component->dev, "%s: MX-0011 val=%x sleep %d\n",
1479 				__func__, val, sleep_time[i]);
1480 			i++;
1481 		}
1482 		dev_dbg(component->dev, "%s val = %d\n", __func__, val);
1483 		switch (val) {
1484 		case 1:
1485 		case 2:
1486 			rt5663->jack_type = SND_JACK_HEADSET;
1487 			rt5663_enable_push_button_irq(component, true);
1488 			break;
1489 		default:
1490 			snd_soc_dapm_disable_pin(dapm, "MICBIAS1");
1491 			snd_soc_dapm_disable_pin(dapm, "MICBIAS2");
1492 			snd_soc_dapm_disable_pin(dapm, "Mic Det Power");
1493 			snd_soc_dapm_disable_pin(dapm, "CBJ Power");
1494 			snd_soc_dapm_sync(dapm);
1495 			rt5663->jack_type = SND_JACK_HEADPHONE;
1496 			break;
1497 		}
1498 	} else {
1499 		snd_soc_component_update_bits(component, RT5663_RECMIX, 0x8, 0x0);
1500 
1501 		if (rt5663->jack_type == SND_JACK_HEADSET) {
1502 			rt5663_enable_push_button_irq(component, false);
1503 			snd_soc_dapm_disable_pin(dapm, "MICBIAS1");
1504 			snd_soc_dapm_disable_pin(dapm, "MICBIAS2");
1505 			snd_soc_dapm_disable_pin(dapm, "Mic Det Power");
1506 			snd_soc_dapm_disable_pin(dapm, "CBJ Power");
1507 			snd_soc_dapm_sync(dapm);
1508 		}
1509 		rt5663->jack_type = 0;
1510 	}
1511 
1512 	dev_dbg(component->dev, "jack_type = %d\n", rt5663->jack_type);
1513 	return rt5663->jack_type;
1514 }
1515 
1516 /**
1517  * rt5663_jack_detect - Detect headset.
1518  * @component: SoC audio component device.
1519  * @jack_insert: Jack insert or not.
1520  *
1521  * Detect whether is headset or not when jack inserted.
1522  *
1523  * Returns detect status.
1524  */
1525 static int rt5663_jack_detect(struct snd_soc_component *component, int jack_insert)
1526 {
1527 	struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
1528 	int val, i = 0;
1529 
1530 	dev_dbg(component->dev, "%s jack_insert:%d\n", __func__, jack_insert);
1531 
1532 	if (jack_insert) {
1533 		snd_soc_component_update_bits(component, RT5663_DIG_MISC,
1534 			RT5663_DIG_GATE_CTRL_MASK, RT5663_DIG_GATE_CTRL_EN);
1535 		snd_soc_component_update_bits(component, RT5663_HP_CHARGE_PUMP_1,
1536 			RT5663_SI_HP_MASK | RT5663_OSW_HP_L_MASK |
1537 			RT5663_OSW_HP_R_MASK, RT5663_SI_HP_EN |
1538 			RT5663_OSW_HP_L_DIS | RT5663_OSW_HP_R_DIS);
1539 		snd_soc_component_update_bits(component, RT5663_DUMMY_1,
1540 			RT5663_EMB_CLK_MASK | RT5663_HPA_CPL_BIAS_MASK |
1541 			RT5663_HPA_CPR_BIAS_MASK, RT5663_EMB_CLK_EN |
1542 			RT5663_HPA_CPL_BIAS_1 | RT5663_HPA_CPR_BIAS_1);
1543 		snd_soc_component_update_bits(component, RT5663_CBJ_1,
1544 			RT5663_INBUF_CBJ_BST1_MASK | RT5663_CBJ_SENSE_BST1_MASK,
1545 			RT5663_INBUF_CBJ_BST1_ON | RT5663_CBJ_SENSE_BST1_L);
1546 		snd_soc_component_update_bits(component, RT5663_IL_CMD_2,
1547 			RT5663_PWR_MIC_DET_MASK, RT5663_PWR_MIC_DET_ON);
1548 		/* BST1 power on for JD */
1549 		snd_soc_component_update_bits(component, RT5663_PWR_ANLG_2,
1550 			RT5663_PWR_BST1_MASK, RT5663_PWR_BST1_ON);
1551 		snd_soc_component_update_bits(component, RT5663_EM_JACK_TYPE_1,
1552 			RT5663_CBJ_DET_MASK | RT5663_EXT_JD_MASK |
1553 			RT5663_POL_EXT_JD_MASK, RT5663_CBJ_DET_EN |
1554 			RT5663_EXT_JD_EN | RT5663_POL_EXT_JD_EN);
1555 		snd_soc_component_update_bits(component, RT5663_PWR_ANLG_1,
1556 			RT5663_PWR_MB_MASK | RT5663_LDO1_DVO_MASK |
1557 			RT5663_AMP_HP_MASK, RT5663_PWR_MB |
1558 			RT5663_LDO1_DVO_0_9V | RT5663_AMP_HP_3X);
1559 		snd_soc_component_update_bits(component, RT5663_AUTO_1MRC_CLK,
1560 			RT5663_IRQ_POW_SAV_MASK, RT5663_IRQ_POW_SAV_EN);
1561 		snd_soc_component_update_bits(component, RT5663_IRQ_1,
1562 			RT5663_EN_IRQ_JD1_MASK, RT5663_EN_IRQ_JD1_EN);
1563 		snd_soc_component_update_bits(component, RT5663_EM_JACK_TYPE_1,
1564 			RT5663_EM_JD_MASK, RT5663_EM_JD_RST);
1565 		snd_soc_component_update_bits(component, RT5663_EM_JACK_TYPE_1,
1566 			RT5663_EM_JD_MASK, RT5663_EM_JD_NOR);
1567 
1568 		while (true) {
1569 			regmap_read(rt5663->regmap, RT5663_INT_ST_2, &val);
1570 			if (!(val & 0x80))
1571 				usleep_range(10000, 10005);
1572 			else
1573 				break;
1574 
1575 			if (i > 200)
1576 				break;
1577 			i++;
1578 		}
1579 
1580 		val = snd_soc_component_read32(component, RT5663_EM_JACK_TYPE_2) & 0x0003;
1581 		dev_dbg(component->dev, "%s val = %d\n", __func__, val);
1582 
1583 		snd_soc_component_update_bits(component, RT5663_HP_CHARGE_PUMP_1,
1584 			RT5663_OSW_HP_L_MASK | RT5663_OSW_HP_R_MASK,
1585 			RT5663_OSW_HP_L_EN | RT5663_OSW_HP_R_EN);
1586 
1587 		switch (val) {
1588 		case 1:
1589 		case 2:
1590 			rt5663->jack_type = SND_JACK_HEADSET;
1591 			rt5663_enable_push_button_irq(component, true);
1592 
1593 			if (rt5663->pdata.impedance_sensing_num)
1594 				break;
1595 
1596 			if (rt5663->pdata.dc_offset_l_manual_mic) {
1597 				regmap_write(rt5663->regmap, RT5663_MIC_DECRO_2,
1598 					rt5663->pdata.dc_offset_l_manual_mic >>
1599 					16);
1600 				regmap_write(rt5663->regmap, RT5663_MIC_DECRO_3,
1601 					rt5663->pdata.dc_offset_l_manual_mic &
1602 					0xffff);
1603 			}
1604 
1605 			if (rt5663->pdata.dc_offset_r_manual_mic) {
1606 				regmap_write(rt5663->regmap, RT5663_MIC_DECRO_5,
1607 					rt5663->pdata.dc_offset_r_manual_mic >>
1608 					16);
1609 				regmap_write(rt5663->regmap, RT5663_MIC_DECRO_6,
1610 					rt5663->pdata.dc_offset_r_manual_mic &
1611 					0xffff);
1612 			}
1613 			break;
1614 		default:
1615 			rt5663->jack_type = SND_JACK_HEADPHONE;
1616 
1617 			if (rt5663->pdata.impedance_sensing_num)
1618 				break;
1619 
1620 			if (rt5663->pdata.dc_offset_l_manual) {
1621 				regmap_write(rt5663->regmap, RT5663_MIC_DECRO_2,
1622 					rt5663->pdata.dc_offset_l_manual >> 16);
1623 				regmap_write(rt5663->regmap, RT5663_MIC_DECRO_3,
1624 					rt5663->pdata.dc_offset_l_manual &
1625 					0xffff);
1626 			}
1627 
1628 			if (rt5663->pdata.dc_offset_r_manual) {
1629 				regmap_write(rt5663->regmap, RT5663_MIC_DECRO_5,
1630 					rt5663->pdata.dc_offset_r_manual >> 16);
1631 				regmap_write(rt5663->regmap, RT5663_MIC_DECRO_6,
1632 					rt5663->pdata.dc_offset_r_manual &
1633 					0xffff);
1634 			}
1635 			break;
1636 		}
1637 	} else {
1638 		if (rt5663->jack_type == SND_JACK_HEADSET)
1639 			rt5663_enable_push_button_irq(component, false);
1640 		rt5663->jack_type = 0;
1641 	}
1642 
1643 	dev_dbg(component->dev, "jack_type = %d\n", rt5663->jack_type);
1644 	return rt5663->jack_type;
1645 }
1646 
1647 static int rt5663_impedance_sensing(struct snd_soc_component *component)
1648 {
1649 	struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
1650 	unsigned int value, i, reg84, reg26, reg2fa, reg91, reg10, reg80;
1651 
1652 	for (i = 0; i < rt5663->pdata.impedance_sensing_num; i++) {
1653 		if (rt5663->imp_table[i].vol == 7)
1654 			break;
1655 	}
1656 
1657 	if (rt5663->jack_type == SND_JACK_HEADSET) {
1658 		snd_soc_component_write(component, RT5663_MIC_DECRO_2,
1659 			rt5663->imp_table[i].dc_offset_l_manual_mic >> 16);
1660 		snd_soc_component_write(component, RT5663_MIC_DECRO_3,
1661 			rt5663->imp_table[i].dc_offset_l_manual_mic & 0xffff);
1662 		snd_soc_component_write(component, RT5663_MIC_DECRO_5,
1663 			rt5663->imp_table[i].dc_offset_r_manual_mic >> 16);
1664 		snd_soc_component_write(component, RT5663_MIC_DECRO_6,
1665 			rt5663->imp_table[i].dc_offset_r_manual_mic & 0xffff);
1666 	} else {
1667 		snd_soc_component_write(component, RT5663_MIC_DECRO_2,
1668 			rt5663->imp_table[i].dc_offset_l_manual >> 16);
1669 		snd_soc_component_write(component, RT5663_MIC_DECRO_3,
1670 			rt5663->imp_table[i].dc_offset_l_manual & 0xffff);
1671 		snd_soc_component_write(component, RT5663_MIC_DECRO_5,
1672 			rt5663->imp_table[i].dc_offset_r_manual >> 16);
1673 		snd_soc_component_write(component, RT5663_MIC_DECRO_6,
1674 			rt5663->imp_table[i].dc_offset_r_manual & 0xffff);
1675 	}
1676 
1677 	reg84 = snd_soc_component_read32(component, RT5663_ASRC_2);
1678 	reg26 = snd_soc_component_read32(component, RT5663_STO1_ADC_MIXER);
1679 	reg2fa = snd_soc_component_read32(component, RT5663_DUMMY_1);
1680 	reg91 = snd_soc_component_read32(component, RT5663_HP_CHARGE_PUMP_1);
1681 	reg10 = snd_soc_component_read32(component, RT5663_RECMIX);
1682 	reg80 = snd_soc_component_read32(component, RT5663_GLB_CLK);
1683 
1684 	snd_soc_component_update_bits(component, RT5663_STO_DRE_1, 0x8000, 0);
1685 	snd_soc_component_write(component, RT5663_ASRC_2, 0);
1686 	snd_soc_component_write(component, RT5663_STO1_ADC_MIXER, 0x4040);
1687 	snd_soc_component_update_bits(component, RT5663_PWR_ANLG_1,
1688 		RT5663_PWR_VREF1_MASK | RT5663_PWR_VREF2_MASK |
1689 		RT5663_PWR_FV1_MASK | RT5663_PWR_FV2_MASK,
1690 		RT5663_PWR_VREF1 | RT5663_PWR_VREF2);
1691 	usleep_range(10000, 10005);
1692 	snd_soc_component_update_bits(component, RT5663_PWR_ANLG_1,
1693 		RT5663_PWR_FV1_MASK | RT5663_PWR_FV2_MASK,
1694 		RT5663_PWR_FV1 | RT5663_PWR_FV2);
1695 	snd_soc_component_update_bits(component, RT5663_GLB_CLK, RT5663_SCLK_SRC_MASK,
1696 		RT5663_SCLK_SRC_RCCLK);
1697 	snd_soc_component_update_bits(component, RT5663_RC_CLK, RT5663_DIG_25M_CLK_MASK,
1698 		RT5663_DIG_25M_CLK_EN);
1699 	snd_soc_component_update_bits(component, RT5663_ADDA_CLK_1, RT5663_I2S_PD1_MASK, 0);
1700 	snd_soc_component_write(component, RT5663_PRE_DIV_GATING_1, 0xff00);
1701 	snd_soc_component_write(component, RT5663_PRE_DIV_GATING_2, 0xfffc);
1702 	snd_soc_component_write(component, RT5663_HP_CHARGE_PUMP_1, 0x1232);
1703 	snd_soc_component_write(component, RT5663_HP_LOGIC_2, 0x0005);
1704 	snd_soc_component_write(component, RT5663_DEPOP_2, 0x3003);
1705 	snd_soc_component_update_bits(component, RT5663_DEPOP_1, 0x0030, 0x0030);
1706 	snd_soc_component_update_bits(component, RT5663_DEPOP_1, 0x0003, 0x0003);
1707 	snd_soc_component_update_bits(component, RT5663_PWR_DIG_2,
1708 		RT5663_PWR_ADC_S1F | RT5663_PWR_DAC_S1F,
1709 		RT5663_PWR_ADC_S1F | RT5663_PWR_DAC_S1F);
1710 	snd_soc_component_update_bits(component, RT5663_PWR_DIG_1,
1711 		RT5663_PWR_DAC_L1 | RT5663_PWR_DAC_R1 |
1712 		RT5663_PWR_LDO_DACREF_MASK | RT5663_PWR_ADC_L1 |
1713 		RT5663_PWR_ADC_R1,
1714 		RT5663_PWR_DAC_L1 | RT5663_PWR_DAC_R1 |
1715 		RT5663_PWR_LDO_DACREF_ON | RT5663_PWR_ADC_L1 |
1716 		RT5663_PWR_ADC_R1);
1717 	msleep(40);
1718 	snd_soc_component_update_bits(component, RT5663_PWR_ANLG_2,
1719 		RT5663_PWR_RECMIX1 | RT5663_PWR_RECMIX2,
1720 		RT5663_PWR_RECMIX1 | RT5663_PWR_RECMIX2);
1721 	msleep(30);
1722 	snd_soc_component_write(component, RT5663_HP_CHARGE_PUMP_2, 0x1371);
1723 	snd_soc_component_write(component, RT5663_STO_DAC_MIXER, 0);
1724 	snd_soc_component_write(component, RT5663_BYPASS_STO_DAC, 0x000c);
1725 	snd_soc_component_write(component, RT5663_HP_BIAS, 0xafaa);
1726 	snd_soc_component_write(component, RT5663_CHARGE_PUMP_1, 0x2224);
1727 	snd_soc_component_write(component, RT5663_HP_OUT_EN, 0x8088);
1728 	snd_soc_component_write(component, RT5663_CHOP_ADC, 0x3000);
1729 	snd_soc_component_write(component, RT5663_ADDA_RST, 0xc000);
1730 	snd_soc_component_write(component, RT5663_STO1_HPF_ADJ1, 0x3320);
1731 	snd_soc_component_write(component, RT5663_HP_CALIB_2, 0x00c9);
1732 	snd_soc_component_write(component, RT5663_DUMMY_1, 0x004c);
1733 	snd_soc_component_write(component, RT5663_ANA_BIAS_CUR_1, 0x7733);
1734 	snd_soc_component_write(component, RT5663_CHARGE_PUMP_2, 0x7777);
1735 	snd_soc_component_write(component, RT5663_STO_DRE_9, 0x0007);
1736 	snd_soc_component_write(component, RT5663_STO_DRE_10, 0x0007);
1737 	snd_soc_component_write(component, RT5663_DUMMY_2, 0x02a4);
1738 	snd_soc_component_write(component, RT5663_RECMIX, 0x0005);
1739 	snd_soc_component_write(component, RT5663_HP_IMP_SEN_1, 0x4334);
1740 	snd_soc_component_update_bits(component, RT5663_IRQ_3, 0x0004, 0x0004);
1741 	snd_soc_component_write(component, RT5663_HP_LOGIC_1, 0x2200);
1742 	snd_soc_component_update_bits(component, RT5663_DEPOP_1, 0x3000, 0x3000);
1743 	snd_soc_component_write(component, RT5663_HP_LOGIC_1, 0x6200);
1744 
1745 	for (i = 0; i < 100; i++) {
1746 		msleep(20);
1747 		if (snd_soc_component_read32(component, RT5663_INT_ST_1) & 0x2)
1748 			break;
1749 	}
1750 
1751 	value = snd_soc_component_read32(component, RT5663_HP_IMP_SEN_4);
1752 
1753 	snd_soc_component_update_bits(component, RT5663_DEPOP_1, 0x3000, 0);
1754 	snd_soc_component_write(component, RT5663_INT_ST_1, 0);
1755 	snd_soc_component_write(component, RT5663_HP_LOGIC_1, 0);
1756 	snd_soc_component_update_bits(component, RT5663_RC_CLK, RT5663_DIG_25M_CLK_MASK,
1757 		RT5663_DIG_25M_CLK_DIS);
1758 	snd_soc_component_write(component, RT5663_GLB_CLK, reg80);
1759 	snd_soc_component_write(component, RT5663_RECMIX, reg10);
1760 	snd_soc_component_write(component, RT5663_DUMMY_2, 0x00a4);
1761 	snd_soc_component_write(component, RT5663_DUMMY_1, reg2fa);
1762 	snd_soc_component_write(component, RT5663_HP_CALIB_2, 0x00c8);
1763 	snd_soc_component_write(component, RT5663_STO1_HPF_ADJ1, 0xb320);
1764 	snd_soc_component_write(component, RT5663_ADDA_RST, 0xe400);
1765 	snd_soc_component_write(component, RT5663_CHOP_ADC, 0x2000);
1766 	snd_soc_component_write(component, RT5663_HP_OUT_EN, 0x0008);
1767 	snd_soc_component_update_bits(component, RT5663_PWR_ANLG_2,
1768 		RT5663_PWR_RECMIX1 | RT5663_PWR_RECMIX2, 0);
1769 	snd_soc_component_update_bits(component, RT5663_PWR_DIG_1,
1770 		RT5663_PWR_DAC_L1 | RT5663_PWR_DAC_R1 |
1771 		RT5663_PWR_LDO_DACREF_MASK | RT5663_PWR_ADC_L1 |
1772 		RT5663_PWR_ADC_R1, 0);
1773 	snd_soc_component_update_bits(component, RT5663_PWR_DIG_2,
1774 		RT5663_PWR_ADC_S1F | RT5663_PWR_DAC_S1F, 0);
1775 	snd_soc_component_update_bits(component, RT5663_DEPOP_1, 0x0003, 0);
1776 	snd_soc_component_update_bits(component, RT5663_DEPOP_1, 0x0030, 0);
1777 	snd_soc_component_write(component, RT5663_HP_LOGIC_2, 0);
1778 	snd_soc_component_write(component, RT5663_HP_CHARGE_PUMP_1, reg91);
1779 	snd_soc_component_update_bits(component, RT5663_PWR_ANLG_1,
1780 		RT5663_PWR_VREF1_MASK | RT5663_PWR_VREF2_MASK, 0);
1781 	snd_soc_component_write(component, RT5663_STO1_ADC_MIXER, reg26);
1782 	snd_soc_component_write(component, RT5663_ASRC_2, reg84);
1783 
1784 	for (i = 0; i < rt5663->pdata.impedance_sensing_num; i++) {
1785 		if (value >= rt5663->imp_table[i].imp_min &&
1786 			value <= rt5663->imp_table[i].imp_max)
1787 			break;
1788 	}
1789 
1790 	snd_soc_component_update_bits(component, RT5663_STO_DRE_9, RT5663_DRE_GAIN_HP_MASK,
1791 		rt5663->imp_table[i].vol);
1792 	snd_soc_component_update_bits(component, RT5663_STO_DRE_10, RT5663_DRE_GAIN_HP_MASK,
1793 		rt5663->imp_table[i].vol);
1794 
1795 	if (rt5663->jack_type == SND_JACK_HEADSET) {
1796 		snd_soc_component_write(component, RT5663_MIC_DECRO_2,
1797 			rt5663->imp_table[i].dc_offset_l_manual_mic >> 16);
1798 		snd_soc_component_write(component, RT5663_MIC_DECRO_3,
1799 			rt5663->imp_table[i].dc_offset_l_manual_mic & 0xffff);
1800 		snd_soc_component_write(component, RT5663_MIC_DECRO_5,
1801 			rt5663->imp_table[i].dc_offset_r_manual_mic >> 16);
1802 		snd_soc_component_write(component, RT5663_MIC_DECRO_6,
1803 			rt5663->imp_table[i].dc_offset_r_manual_mic & 0xffff);
1804 	} else {
1805 		snd_soc_component_write(component, RT5663_MIC_DECRO_2,
1806 			rt5663->imp_table[i].dc_offset_l_manual >> 16);
1807 		snd_soc_component_write(component, RT5663_MIC_DECRO_3,
1808 			rt5663->imp_table[i].dc_offset_l_manual & 0xffff);
1809 		snd_soc_component_write(component, RT5663_MIC_DECRO_5,
1810 			rt5663->imp_table[i].dc_offset_r_manual >> 16);
1811 		snd_soc_component_write(component, RT5663_MIC_DECRO_6,
1812 			rt5663->imp_table[i].dc_offset_r_manual & 0xffff);
1813 	}
1814 
1815 	return 0;
1816 }
1817 
1818 static int rt5663_button_detect(struct snd_soc_component *component)
1819 {
1820 	int btn_type, val;
1821 
1822 	val = snd_soc_component_read32(component, RT5663_IL_CMD_5);
1823 	dev_dbg(component->dev, "%s: val=0x%x\n", __func__, val);
1824 	btn_type = val & 0xfff0;
1825 	snd_soc_component_write(component, RT5663_IL_CMD_5, val);
1826 
1827 	return btn_type;
1828 }
1829 
1830 static irqreturn_t rt5663_irq(int irq, void *data)
1831 {
1832 	struct rt5663_priv *rt5663 = data;
1833 
1834 	dev_dbg(regmap_get_device(rt5663->regmap), "%s IRQ queue work\n",
1835 		__func__);
1836 
1837 	queue_delayed_work(system_wq, &rt5663->jack_detect_work,
1838 		msecs_to_jiffies(250));
1839 
1840 	return IRQ_HANDLED;
1841 }
1842 
1843 int rt5663_set_jack_detect(struct snd_soc_component *component,
1844 	struct snd_soc_jack *hs_jack)
1845 {
1846 	struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
1847 
1848 	rt5663->hs_jack = hs_jack;
1849 
1850 	rt5663_irq(0, rt5663);
1851 
1852 	return 0;
1853 }
1854 EXPORT_SYMBOL_GPL(rt5663_set_jack_detect);
1855 
1856 static bool rt5663_check_jd_status(struct snd_soc_component *component)
1857 {
1858 	struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
1859 	int val = snd_soc_component_read32(component, RT5663_INT_ST_1);
1860 
1861 	dev_dbg(component->dev, "%s val=%x\n", __func__, val);
1862 
1863 	/* JD1 */
1864 	switch (rt5663->codec_ver) {
1865 	case CODEC_VER_1:
1866 		return !(val & 0x2000);
1867 	case CODEC_VER_0:
1868 		return !(val & 0x1000);
1869 	default:
1870 		dev_err(component->dev, "Unknown CODEC Version\n");
1871 	}
1872 
1873 	return false;
1874 }
1875 
1876 static void rt5663_jack_detect_work(struct work_struct *work)
1877 {
1878 	struct rt5663_priv *rt5663 =
1879 		container_of(work, struct rt5663_priv, jack_detect_work.work);
1880 	struct snd_soc_component *component = rt5663->component;
1881 	int btn_type, report = 0;
1882 
1883 	if (!component)
1884 		return;
1885 
1886 	if (rt5663_check_jd_status(component)) {
1887 		/* jack in */
1888 		if (rt5663->jack_type == 0) {
1889 			/* jack was out, report jack type */
1890 			switch (rt5663->codec_ver) {
1891 			case CODEC_VER_1:
1892 				report = rt5663_v2_jack_detect(
1893 						rt5663->component, 1);
1894 				break;
1895 			case CODEC_VER_0:
1896 				report = rt5663_jack_detect(rt5663->component, 1);
1897 				if (rt5663->pdata.impedance_sensing_num)
1898 					rt5663_impedance_sensing(rt5663->component);
1899 				break;
1900 			default:
1901 				dev_err(component->dev, "Unknown CODEC Version\n");
1902 			}
1903 
1904 			/* Delay the jack insert report to avoid pop noise */
1905 			msleep(30);
1906 		} else {
1907 			/* jack is already in, report button event */
1908 			report = SND_JACK_HEADSET;
1909 			btn_type = rt5663_button_detect(rt5663->component);
1910 			/**
1911 			 * rt5663 can report three kinds of button behavior,
1912 			 * one click, double click and hold. However,
1913 			 * currently we will report button pressed/released
1914 			 * event. So all the three button behaviors are
1915 			 * treated as button pressed.
1916 			 */
1917 			switch (btn_type) {
1918 			case 0x8000:
1919 			case 0x4000:
1920 			case 0x2000:
1921 				report |= SND_JACK_BTN_0;
1922 				break;
1923 			case 0x1000:
1924 			case 0x0800:
1925 			case 0x0400:
1926 				report |= SND_JACK_BTN_1;
1927 				break;
1928 			case 0x0200:
1929 			case 0x0100:
1930 			case 0x0080:
1931 				report |= SND_JACK_BTN_2;
1932 				break;
1933 			case 0x0040:
1934 			case 0x0020:
1935 			case 0x0010:
1936 				report |= SND_JACK_BTN_3;
1937 				break;
1938 			case 0x0000: /* unpressed */
1939 				break;
1940 			default:
1941 				btn_type = 0;
1942 				dev_err(rt5663->component->dev,
1943 					"Unexpected button code 0x%04x\n",
1944 					btn_type);
1945 				break;
1946 			}
1947 			/* button release or spurious interrput*/
1948 			if (btn_type == 0) {
1949 				report =  rt5663->jack_type;
1950 				cancel_delayed_work_sync(
1951 					&rt5663->jd_unplug_work);
1952 			} else {
1953 				queue_delayed_work(system_wq,
1954 					&rt5663->jd_unplug_work,
1955 					msecs_to_jiffies(500));
1956 			}
1957 		}
1958 	} else {
1959 		/* jack out */
1960 		switch (rt5663->codec_ver) {
1961 		case CODEC_VER_1:
1962 			report = rt5663_v2_jack_detect(rt5663->component, 0);
1963 			break;
1964 		case CODEC_VER_0:
1965 			report = rt5663_jack_detect(rt5663->component, 0);
1966 			break;
1967 		default:
1968 			dev_err(component->dev, "Unknown CODEC Version\n");
1969 		}
1970 	}
1971 	dev_dbg(component->dev, "%s jack report: 0x%04x\n", __func__, report);
1972 	snd_soc_jack_report(rt5663->hs_jack, report, SND_JACK_HEADSET |
1973 			    SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1974 			    SND_JACK_BTN_2 | SND_JACK_BTN_3);
1975 }
1976 
1977 static void rt5663_jd_unplug_work(struct work_struct *work)
1978 {
1979 	struct rt5663_priv *rt5663 =
1980 		container_of(work, struct rt5663_priv, jd_unplug_work.work);
1981 	struct snd_soc_component *component = rt5663->component;
1982 
1983 	if (!component)
1984 		return;
1985 
1986 	if (!rt5663_check_jd_status(component)) {
1987 		/* jack out */
1988 		switch (rt5663->codec_ver) {
1989 		case CODEC_VER_1:
1990 			rt5663_v2_jack_detect(rt5663->component, 0);
1991 			break;
1992 		case CODEC_VER_0:
1993 			rt5663_jack_detect(rt5663->component, 0);
1994 			break;
1995 		default:
1996 			dev_err(component->dev, "Unknown CODEC Version\n");
1997 		}
1998 
1999 		snd_soc_jack_report(rt5663->hs_jack, 0, SND_JACK_HEADSET |
2000 				    SND_JACK_BTN_0 | SND_JACK_BTN_1 |
2001 				    SND_JACK_BTN_2 | SND_JACK_BTN_3);
2002 	} else {
2003 		queue_delayed_work(system_wq, &rt5663->jd_unplug_work,
2004 			msecs_to_jiffies(500));
2005 	}
2006 }
2007 
2008 static const struct snd_kcontrol_new rt5663_snd_controls[] = {
2009 	/* DAC Digital Volume */
2010 	SOC_DOUBLE_TLV("DAC Playback Volume", RT5663_STO1_DAC_DIG_VOL,
2011 		RT5663_DAC_L1_VOL_SHIFT + 1, RT5663_DAC_R1_VOL_SHIFT + 1,
2012 		87, 0, dac_vol_tlv),
2013 	/* ADC Digital Volume Control */
2014 	SOC_DOUBLE("ADC Capture Switch", RT5663_STO1_ADC_DIG_VOL,
2015 		RT5663_ADC_L_MUTE_SHIFT, RT5663_ADC_R_MUTE_SHIFT, 1, 1),
2016 	SOC_DOUBLE_TLV("ADC Capture Volume", RT5663_STO1_ADC_DIG_VOL,
2017 		RT5663_ADC_L_VOL_SHIFT + 1, RT5663_ADC_R_VOL_SHIFT + 1,
2018 		63, 0, adc_vol_tlv),
2019 };
2020 
2021 static const struct snd_kcontrol_new rt5663_v2_specific_controls[] = {
2022 	/* Headphone Output Volume */
2023 	SOC_DOUBLE_R_TLV("Headphone Playback Volume", RT5663_HP_LCH_DRE,
2024 		RT5663_HP_RCH_DRE, RT5663_GAIN_HP_SHIFT, 15, 1,
2025 		rt5663_v2_hp_vol_tlv),
2026 	/* Mic Boost Volume */
2027 	SOC_SINGLE_TLV("IN1 Capture Volume", RT5663_AEC_BST,
2028 		RT5663_GAIN_CBJ_SHIFT, 8, 0, in_bst_tlv),
2029 };
2030 
2031 static const struct snd_kcontrol_new rt5663_specific_controls[] = {
2032 	/* Mic Boost Volume*/
2033 	SOC_SINGLE_TLV("IN1 Capture Volume", RT5663_CBJ_2,
2034 		RT5663_GAIN_BST1_SHIFT, 8, 0, in_bst_tlv),
2035 	/* Data Swap for Slot0/1 in ADCDAT1 */
2036 	SOC_ENUM("IF1 ADC Data Swap", rt5663_if1_adc_enum),
2037 };
2038 
2039 static const struct snd_kcontrol_new rt5663_hpvol_controls[] = {
2040 	/* Headphone Output Volume */
2041 	SOC_DOUBLE_R_TLV("Headphone Playback Volume", RT5663_STO_DRE_9,
2042 		RT5663_STO_DRE_10, RT5663_DRE_GAIN_HP_SHIFT, 23, 1,
2043 		rt5663_hp_vol_tlv),
2044 };
2045 
2046 static int rt5663_is_sys_clk_from_pll(struct snd_soc_dapm_widget *w,
2047 	struct snd_soc_dapm_widget *sink)
2048 {
2049 	unsigned int val;
2050 	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2051 
2052 	val = snd_soc_component_read32(component, RT5663_GLB_CLK);
2053 	val &= RT5663_SCLK_SRC_MASK;
2054 	if (val == RT5663_SCLK_SRC_PLL1)
2055 		return 1;
2056 	else
2057 		return 0;
2058 }
2059 
2060 static int rt5663_is_using_asrc(struct snd_soc_dapm_widget *w,
2061 	struct snd_soc_dapm_widget *sink)
2062 {
2063 	unsigned int reg, shift, val;
2064 	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2065 	struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
2066 
2067 	if (rt5663->codec_ver == CODEC_VER_1) {
2068 		switch (w->shift) {
2069 		case RT5663_ADC_STO1_ASRC_SHIFT:
2070 			reg = RT5663_ASRC_3;
2071 			shift = RT5663_V2_AD_STO1_TRACK_SHIFT;
2072 			break;
2073 		case RT5663_DAC_STO1_ASRC_SHIFT:
2074 			reg = RT5663_ASRC_2;
2075 			shift = RT5663_DA_STO1_TRACK_SHIFT;
2076 			break;
2077 		default:
2078 			return 0;
2079 		}
2080 	} else {
2081 		switch (w->shift) {
2082 		case RT5663_ADC_STO1_ASRC_SHIFT:
2083 			reg = RT5663_ASRC_2;
2084 			shift = RT5663_AD_STO1_TRACK_SHIFT;
2085 			break;
2086 		case RT5663_DAC_STO1_ASRC_SHIFT:
2087 			reg = RT5663_ASRC_2;
2088 			shift = RT5663_DA_STO1_TRACK_SHIFT;
2089 			break;
2090 		default:
2091 			return 0;
2092 		}
2093 	}
2094 
2095 	val = (snd_soc_component_read32(component, reg) >> shift) & 0x7;
2096 
2097 	if (val)
2098 		return 1;
2099 
2100 	return 0;
2101 }
2102 
2103 static int rt5663_i2s_use_asrc(struct snd_soc_dapm_widget *source,
2104 	struct snd_soc_dapm_widget *sink)
2105 {
2106 	struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm);
2107 	struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
2108 	int da_asrc_en, ad_asrc_en;
2109 
2110 	da_asrc_en = (snd_soc_component_read32(component, RT5663_ASRC_2) &
2111 		RT5663_DA_STO1_TRACK_MASK) ? 1 : 0;
2112 	switch (rt5663->codec_ver) {
2113 	case CODEC_VER_1:
2114 		ad_asrc_en = (snd_soc_component_read32(component, RT5663_ASRC_3) &
2115 			RT5663_V2_AD_STO1_TRACK_MASK) ? 1 : 0;
2116 		break;
2117 	case CODEC_VER_0:
2118 		ad_asrc_en = (snd_soc_component_read32(component, RT5663_ASRC_2) &
2119 			RT5663_AD_STO1_TRACK_MASK) ? 1 : 0;
2120 		break;
2121 	default:
2122 		dev_err(component->dev, "Unknown CODEC Version\n");
2123 		return 1;
2124 	}
2125 
2126 	if (da_asrc_en || ad_asrc_en)
2127 		if (rt5663->sysclk > rt5663->lrck * 384)
2128 			return 1;
2129 
2130 	dev_err(component->dev, "sysclk < 384 x fs, disable i2s asrc\n");
2131 
2132 	return 0;
2133 }
2134 
2135 /**
2136  * rt5663_sel_asrc_clk_src - select ASRC clock source for a set of filters
2137  * @component: SoC audio component device.
2138  * @filter_mask: mask of filters.
2139  * @clk_src: clock source
2140  *
2141  * The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5663 can
2142  * only support standard 32fs or 64fs i2s format, ASRC should be enabled to
2143  * support special i2s clock format such as Intel's 100fs(100 * sampling rate).
2144  * ASRC function will track i2s clock and generate a corresponding system clock
2145  * for codec. This function provides an API to select the clock source for a
2146  * set of filters specified by the mask. And the codec driver will turn on ASRC
2147  * for these filters if ASRC is selected as their clock source.
2148  */
2149 int rt5663_sel_asrc_clk_src(struct snd_soc_component *component,
2150 		unsigned int filter_mask, unsigned int clk_src)
2151 {
2152 	struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
2153 	unsigned int asrc2_mask = 0;
2154 	unsigned int asrc2_value = 0;
2155 	unsigned int asrc3_mask = 0;
2156 	unsigned int asrc3_value = 0;
2157 
2158 	switch (clk_src) {
2159 	case RT5663_CLK_SEL_SYS:
2160 	case RT5663_CLK_SEL_I2S1_ASRC:
2161 		break;
2162 
2163 	default:
2164 		return -EINVAL;
2165 	}
2166 
2167 	if (filter_mask & RT5663_DA_STEREO_FILTER) {
2168 		asrc2_mask |= RT5663_DA_STO1_TRACK_MASK;
2169 		asrc2_value |= clk_src << RT5663_DA_STO1_TRACK_SHIFT;
2170 	}
2171 
2172 	if (filter_mask & RT5663_AD_STEREO_FILTER) {
2173 		switch (rt5663->codec_ver) {
2174 		case CODEC_VER_1:
2175 			asrc3_mask |= RT5663_V2_AD_STO1_TRACK_MASK;
2176 			asrc3_value |= clk_src << RT5663_V2_AD_STO1_TRACK_SHIFT;
2177 			break;
2178 		case CODEC_VER_0:
2179 			asrc2_mask |= RT5663_AD_STO1_TRACK_MASK;
2180 			asrc2_value |= clk_src << RT5663_AD_STO1_TRACK_SHIFT;
2181 			break;
2182 		default:
2183 			dev_err(component->dev, "Unknown CODEC Version\n");
2184 		}
2185 	}
2186 
2187 	if (asrc2_mask)
2188 		snd_soc_component_update_bits(component, RT5663_ASRC_2, asrc2_mask,
2189 			asrc2_value);
2190 
2191 	if (asrc3_mask)
2192 		snd_soc_component_update_bits(component, RT5663_ASRC_3, asrc3_mask,
2193 			asrc3_value);
2194 
2195 	return 0;
2196 }
2197 EXPORT_SYMBOL_GPL(rt5663_sel_asrc_clk_src);
2198 
2199 /* Analog Mixer */
2200 static const struct snd_kcontrol_new rt5663_recmix1l[] = {
2201 	SOC_DAPM_SINGLE("BST2 Switch", RT5663_RECMIX1L,
2202 		RT5663_RECMIX1L_BST2_SHIFT, 1, 1),
2203 	SOC_DAPM_SINGLE("BST1 CBJ Switch", RT5663_RECMIX1L,
2204 		RT5663_RECMIX1L_BST1_CBJ_SHIFT, 1, 1),
2205 };
2206 
2207 static const struct snd_kcontrol_new rt5663_recmix1r[] = {
2208 	SOC_DAPM_SINGLE("BST2 Switch", RT5663_RECMIX1R,
2209 		RT5663_RECMIX1R_BST2_SHIFT, 1, 1),
2210 };
2211 
2212 /* Digital Mixer */
2213 static const struct snd_kcontrol_new rt5663_sto1_adc_l_mix[] = {
2214 	SOC_DAPM_SINGLE("ADC1 Switch", RT5663_STO1_ADC_MIXER,
2215 			RT5663_M_STO1_ADC_L1_SHIFT, 1, 1),
2216 	SOC_DAPM_SINGLE("ADC2 Switch", RT5663_STO1_ADC_MIXER,
2217 			RT5663_M_STO1_ADC_L2_SHIFT, 1, 1),
2218 };
2219 
2220 static const struct snd_kcontrol_new rt5663_sto1_adc_r_mix[] = {
2221 	SOC_DAPM_SINGLE("ADC1 Switch", RT5663_STO1_ADC_MIXER,
2222 			RT5663_M_STO1_ADC_R1_SHIFT, 1, 1),
2223 	SOC_DAPM_SINGLE("ADC2 Switch", RT5663_STO1_ADC_MIXER,
2224 			RT5663_M_STO1_ADC_R2_SHIFT, 1, 1),
2225 };
2226 
2227 static const struct snd_kcontrol_new rt5663_adda_l_mix[] = {
2228 	SOC_DAPM_SINGLE("ADC L Switch", RT5663_AD_DA_MIXER,
2229 			RT5663_M_ADCMIX_L_SHIFT, 1, 1),
2230 	SOC_DAPM_SINGLE("DAC L Switch", RT5663_AD_DA_MIXER,
2231 			RT5663_M_DAC1_L_SHIFT, 1, 1),
2232 };
2233 
2234 static const struct snd_kcontrol_new rt5663_adda_r_mix[] = {
2235 	SOC_DAPM_SINGLE("ADC R Switch", RT5663_AD_DA_MIXER,
2236 			RT5663_M_ADCMIX_R_SHIFT, 1, 1),
2237 	SOC_DAPM_SINGLE("DAC R Switch", RT5663_AD_DA_MIXER,
2238 			RT5663_M_DAC1_R_SHIFT, 1, 1),
2239 };
2240 
2241 static const struct snd_kcontrol_new rt5663_sto1_dac_l_mix[] = {
2242 	SOC_DAPM_SINGLE("DAC L Switch", RT5663_STO_DAC_MIXER,
2243 			RT5663_M_DAC_L1_STO_L_SHIFT, 1, 1),
2244 };
2245 
2246 static const struct snd_kcontrol_new rt5663_sto1_dac_r_mix[] = {
2247 	SOC_DAPM_SINGLE("DAC R Switch", RT5663_STO_DAC_MIXER,
2248 			RT5663_M_DAC_R1_STO_R_SHIFT, 1, 1),
2249 };
2250 
2251 /* Out Switch */
2252 static const struct snd_kcontrol_new rt5663_hpo_switch =
2253 	SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5663_HP_AMP_2,
2254 		RT5663_EN_DAC_HPO_SHIFT, 1, 0);
2255 
2256 /* Stereo ADC source */
2257 static const char * const rt5663_sto1_adc_src[] = {
2258 	"ADC L", "ADC R"
2259 };
2260 
2261 static SOC_ENUM_SINGLE_DECL(rt5663_sto1_adcl_enum, RT5663_STO1_ADC_MIXER,
2262 	RT5663_STO1_ADC_L_SRC_SHIFT, rt5663_sto1_adc_src);
2263 
2264 static const struct snd_kcontrol_new rt5663_sto1_adcl_mux =
2265 	SOC_DAPM_ENUM("STO1 ADC L Mux", rt5663_sto1_adcl_enum);
2266 
2267 static SOC_ENUM_SINGLE_DECL(rt5663_sto1_adcr_enum, RT5663_STO1_ADC_MIXER,
2268 	RT5663_STO1_ADC_R_SRC_SHIFT, rt5663_sto1_adc_src);
2269 
2270 static const struct snd_kcontrol_new rt5663_sto1_adcr_mux =
2271 	SOC_DAPM_ENUM("STO1 ADC R Mux", rt5663_sto1_adcr_enum);
2272 
2273 /* RT5663: Analog DACL1 input source */
2274 static const char * const rt5663_alg_dacl_src[] = {
2275 	"DAC L", "STO DAC MIXL"
2276 };
2277 
2278 static SOC_ENUM_SINGLE_DECL(rt5663_alg_dacl_enum, RT5663_BYPASS_STO_DAC,
2279 	RT5663_DACL1_SRC_SHIFT, rt5663_alg_dacl_src);
2280 
2281 static const struct snd_kcontrol_new rt5663_alg_dacl_mux =
2282 	SOC_DAPM_ENUM("DAC L Mux", rt5663_alg_dacl_enum);
2283 
2284 /* RT5663: Analog DACR1 input source */
2285 static const char * const rt5663_alg_dacr_src[] = {
2286 	"DAC R", "STO DAC MIXR"
2287 };
2288 
2289 static SOC_ENUM_SINGLE_DECL(rt5663_alg_dacr_enum, RT5663_BYPASS_STO_DAC,
2290 	RT5663_DACR1_SRC_SHIFT, rt5663_alg_dacr_src);
2291 
2292 static const struct snd_kcontrol_new rt5663_alg_dacr_mux =
2293 	SOC_DAPM_ENUM("DAC R Mux", rt5663_alg_dacr_enum);
2294 
2295 static int rt5663_hp_event(struct snd_soc_dapm_widget *w,
2296 	struct snd_kcontrol *kcontrol, int event)
2297 {
2298 	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2299 	struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
2300 
2301 	switch (event) {
2302 	case SND_SOC_DAPM_POST_PMU:
2303 		if (rt5663->codec_ver == CODEC_VER_1) {
2304 			snd_soc_component_update_bits(component, RT5663_HP_CHARGE_PUMP_1,
2305 				RT5663_SEL_PM_HP_SHIFT, RT5663_SEL_PM_HP_HIGH);
2306 			snd_soc_component_update_bits(component, RT5663_HP_LOGIC_2,
2307 				RT5663_HP_SIG_SRC1_MASK,
2308 				RT5663_HP_SIG_SRC1_SILENCE);
2309 		} else {
2310 			snd_soc_component_write(component, RT5663_DEPOP_2, 0x3003);
2311 			snd_soc_component_update_bits(component, RT5663_HP_CHARGE_PUMP_1,
2312 				RT5663_OVCD_HP_MASK, RT5663_OVCD_HP_DIS);
2313 			snd_soc_component_write(component, RT5663_HP_CHARGE_PUMP_2, 0x1371);
2314 			snd_soc_component_write(component, RT5663_HP_BIAS, 0xabba);
2315 			snd_soc_component_write(component, RT5663_CHARGE_PUMP_1, 0x2224);
2316 			snd_soc_component_write(component, RT5663_ANA_BIAS_CUR_1, 0x7766);
2317 			snd_soc_component_write(component, RT5663_HP_BIAS, 0xafaa);
2318 			snd_soc_component_write(component, RT5663_CHARGE_PUMP_2, 0x7777);
2319 			snd_soc_component_update_bits(component, RT5663_STO_DRE_1, 0x8000,
2320 				0x8000);
2321 			snd_soc_component_update_bits(component, RT5663_DEPOP_1, 0x3000,
2322 				0x3000);
2323 		}
2324 		break;
2325 
2326 	case SND_SOC_DAPM_PRE_PMD:
2327 		if (rt5663->codec_ver == CODEC_VER_1) {
2328 			snd_soc_component_update_bits(component, RT5663_HP_LOGIC_2,
2329 				RT5663_HP_SIG_SRC1_MASK,
2330 				RT5663_HP_SIG_SRC1_REG);
2331 		} else {
2332 			snd_soc_component_update_bits(component, RT5663_DEPOP_1, 0x3000, 0x0);
2333 			snd_soc_component_update_bits(component, RT5663_HP_CHARGE_PUMP_1,
2334 				RT5663_OVCD_HP_MASK, RT5663_OVCD_HP_EN);
2335 		}
2336 		break;
2337 
2338 	default:
2339 		return 0;
2340 	}
2341 
2342 	return 0;
2343 }
2344 
2345 static int rt5663_charge_pump_event(struct snd_soc_dapm_widget *w,
2346 	struct snd_kcontrol *kcontrol, int event)
2347 {
2348 	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2349 	struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
2350 
2351 	switch (event) {
2352 	case SND_SOC_DAPM_PRE_PMU:
2353 		if (rt5663->codec_ver == CODEC_VER_0) {
2354 			snd_soc_component_update_bits(component, RT5663_DEPOP_1, 0x0030,
2355 				0x0030);
2356 			snd_soc_component_update_bits(component, RT5663_DEPOP_1, 0x0003,
2357 				0x0003);
2358 		}
2359 		break;
2360 
2361 	case SND_SOC_DAPM_POST_PMD:
2362 		if (rt5663->codec_ver == CODEC_VER_0) {
2363 			snd_soc_component_update_bits(component, RT5663_DEPOP_1, 0x0003, 0);
2364 			snd_soc_component_update_bits(component, RT5663_DEPOP_1, 0x0030, 0);
2365 		}
2366 		break;
2367 
2368 	default:
2369 		return 0;
2370 	}
2371 
2372 	return 0;
2373 }
2374 
2375 static int rt5663_bst2_power(struct snd_soc_dapm_widget *w,
2376 	struct snd_kcontrol *kcontrol, int event)
2377 {
2378 	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2379 
2380 	switch (event) {
2381 	case SND_SOC_DAPM_POST_PMU:
2382 		snd_soc_component_update_bits(component, RT5663_PWR_ANLG_2,
2383 			RT5663_PWR_BST2_MASK | RT5663_PWR_BST2_OP_MASK,
2384 			RT5663_PWR_BST2 | RT5663_PWR_BST2_OP);
2385 		break;
2386 
2387 	case SND_SOC_DAPM_PRE_PMD:
2388 		snd_soc_component_update_bits(component, RT5663_PWR_ANLG_2,
2389 			RT5663_PWR_BST2_MASK | RT5663_PWR_BST2_OP_MASK, 0);
2390 		break;
2391 
2392 	default:
2393 		return 0;
2394 	}
2395 
2396 	return 0;
2397 }
2398 
2399 static int rt5663_pre_div_power(struct snd_soc_dapm_widget *w,
2400 	struct snd_kcontrol *kcontrol, int event)
2401 {
2402 	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2403 
2404 	switch (event) {
2405 	case SND_SOC_DAPM_POST_PMU:
2406 		snd_soc_component_write(component, RT5663_PRE_DIV_GATING_1, 0xff00);
2407 		snd_soc_component_write(component, RT5663_PRE_DIV_GATING_2, 0xfffc);
2408 		break;
2409 
2410 	case SND_SOC_DAPM_PRE_PMD:
2411 		snd_soc_component_write(component, RT5663_PRE_DIV_GATING_1, 0x0000);
2412 		snd_soc_component_write(component, RT5663_PRE_DIV_GATING_2, 0x0000);
2413 		break;
2414 
2415 	default:
2416 		return 0;
2417 	}
2418 
2419 	return 0;
2420 }
2421 
2422 static const struct snd_soc_dapm_widget rt5663_dapm_widgets[] = {
2423 	SND_SOC_DAPM_SUPPLY("PLL", RT5663_PWR_ANLG_3, RT5663_PWR_PLL_SHIFT, 0,
2424 		NULL, 0),
2425 
2426 	/* micbias */
2427 	SND_SOC_DAPM_MICBIAS("MICBIAS1", RT5663_PWR_ANLG_2,
2428 		RT5663_PWR_MB1_SHIFT, 0),
2429 	SND_SOC_DAPM_MICBIAS("MICBIAS2", RT5663_PWR_ANLG_2,
2430 		RT5663_PWR_MB2_SHIFT, 0),
2431 
2432 	/* Input Lines */
2433 	SND_SOC_DAPM_INPUT("IN1P"),
2434 	SND_SOC_DAPM_INPUT("IN1N"),
2435 
2436 	/* REC Mixer Power */
2437 	SND_SOC_DAPM_SUPPLY("RECMIX1L Power", RT5663_PWR_ANLG_2,
2438 		RT5663_PWR_RECMIX1_SHIFT, 0, NULL, 0),
2439 
2440 	/* ADCs */
2441 	SND_SOC_DAPM_ADC("ADC L", NULL, SND_SOC_NOPM, 0, 0),
2442 	SND_SOC_DAPM_SUPPLY("ADC L Power", RT5663_PWR_DIG_1,
2443 		RT5663_PWR_ADC_L1_SHIFT, 0, NULL, 0),
2444 	SND_SOC_DAPM_SUPPLY("ADC Clock", RT5663_CHOP_ADC,
2445 		RT5663_CKGEN_ADCC_SHIFT, 0, NULL, 0),
2446 
2447 	/* ADC Mixer */
2448 	SND_SOC_DAPM_MIXER("STO1 ADC MIXL", SND_SOC_NOPM,
2449 		0, 0, rt5663_sto1_adc_l_mix,
2450 		ARRAY_SIZE(rt5663_sto1_adc_l_mix)),
2451 
2452 	/* ADC Filter Power */
2453 	SND_SOC_DAPM_SUPPLY("STO1 ADC Filter", RT5663_PWR_DIG_2,
2454 		RT5663_PWR_ADC_S1F_SHIFT, 0, NULL, 0),
2455 
2456 	/* Digital Interface */
2457 	SND_SOC_DAPM_SUPPLY("I2S", RT5663_PWR_DIG_1, RT5663_PWR_I2S1_SHIFT, 0,
2458 		NULL, 0),
2459 	SND_SOC_DAPM_PGA("IF DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
2460 	SND_SOC_DAPM_PGA("IF1 DAC1 L", SND_SOC_NOPM, 0, 0, NULL, 0),
2461 	SND_SOC_DAPM_PGA("IF1 DAC1 R", SND_SOC_NOPM, 0, 0, NULL, 0),
2462 	SND_SOC_DAPM_PGA("IF1 ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2463 	SND_SOC_DAPM_PGA("IF ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2464 
2465 	/* Audio Interface */
2466 	SND_SOC_DAPM_AIF_IN("AIFRX", "AIF Playback", 0, SND_SOC_NOPM, 0, 0),
2467 	SND_SOC_DAPM_AIF_OUT("AIFTX", "AIF Capture", 0, SND_SOC_NOPM, 0, 0),
2468 
2469 	/* DAC mixer before sound effect  */
2470 	SND_SOC_DAPM_MIXER("ADDA MIXL", SND_SOC_NOPM, 0, 0, rt5663_adda_l_mix,
2471 		ARRAY_SIZE(rt5663_adda_l_mix)),
2472 	SND_SOC_DAPM_MIXER("ADDA MIXR", SND_SOC_NOPM, 0, 0, rt5663_adda_r_mix,
2473 		ARRAY_SIZE(rt5663_adda_r_mix)),
2474 	SND_SOC_DAPM_PGA("DAC L1", SND_SOC_NOPM, 0, 0, NULL, 0),
2475 	SND_SOC_DAPM_PGA("DAC R1", SND_SOC_NOPM, 0, 0, NULL, 0),
2476 
2477 	/* DAC Mixer */
2478 	SND_SOC_DAPM_SUPPLY("STO1 DAC Filter", RT5663_PWR_DIG_2,
2479 		RT5663_PWR_DAC_S1F_SHIFT, 0, NULL, 0),
2480 	SND_SOC_DAPM_MIXER("STO1 DAC MIXL", SND_SOC_NOPM, 0, 0,
2481 		rt5663_sto1_dac_l_mix, ARRAY_SIZE(rt5663_sto1_dac_l_mix)),
2482 	SND_SOC_DAPM_MIXER("STO1 DAC MIXR", SND_SOC_NOPM, 0, 0,
2483 		rt5663_sto1_dac_r_mix, ARRAY_SIZE(rt5663_sto1_dac_r_mix)),
2484 
2485 	/* DACs */
2486 	SND_SOC_DAPM_SUPPLY("STO1 DAC L Power", RT5663_PWR_DIG_1,
2487 		RT5663_PWR_DAC_L1_SHIFT, 0, NULL, 0),
2488 	SND_SOC_DAPM_SUPPLY("STO1 DAC R Power", RT5663_PWR_DIG_1,
2489 		RT5663_PWR_DAC_R1_SHIFT, 0, NULL, 0),
2490 	SND_SOC_DAPM_DAC("DAC L", NULL, SND_SOC_NOPM, 0, 0),
2491 	SND_SOC_DAPM_DAC("DAC R", NULL, SND_SOC_NOPM, 0, 0),
2492 
2493 	/* Headphone*/
2494 	SND_SOC_DAPM_SUPPLY("HP Charge Pump", SND_SOC_NOPM, 0, 0,
2495 		rt5663_charge_pump_event, SND_SOC_DAPM_PRE_PMU |
2496 		SND_SOC_DAPM_POST_PMD),
2497 	SND_SOC_DAPM_PGA_S("HP Amp", 1, SND_SOC_NOPM, 0, 0, rt5663_hp_event,
2498 		SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
2499 
2500 	/* Output Lines */
2501 	SND_SOC_DAPM_OUTPUT("HPOL"),
2502 	SND_SOC_DAPM_OUTPUT("HPOR"),
2503 };
2504 
2505 static const struct snd_soc_dapm_widget rt5663_v2_specific_dapm_widgets[] = {
2506 	SND_SOC_DAPM_SUPPLY("LDO2", RT5663_PWR_ANLG_3,
2507 		RT5663_PWR_LDO2_SHIFT, 0, NULL, 0),
2508 	SND_SOC_DAPM_SUPPLY("Mic Det Power", RT5663_PWR_VOL,
2509 		RT5663_V2_PWR_MIC_DET_SHIFT, 0, NULL, 0),
2510 	SND_SOC_DAPM_SUPPLY("LDO DAC", RT5663_PWR_DIG_1,
2511 		RT5663_PWR_LDO_DACREF_SHIFT, 0, NULL, 0),
2512 
2513 	/* ASRC */
2514 	SND_SOC_DAPM_SUPPLY("I2S ASRC", RT5663_ASRC_1,
2515 		RT5663_I2S1_ASRC_SHIFT, 0, NULL, 0),
2516 	SND_SOC_DAPM_SUPPLY("DAC ASRC", RT5663_ASRC_1,
2517 		RT5663_DAC_STO1_ASRC_SHIFT, 0, NULL, 0),
2518 	SND_SOC_DAPM_SUPPLY("ADC ASRC", RT5663_ASRC_1,
2519 		RT5663_ADC_STO1_ASRC_SHIFT, 0, NULL, 0),
2520 
2521 	/* Input Lines */
2522 	SND_SOC_DAPM_INPUT("IN2P"),
2523 	SND_SOC_DAPM_INPUT("IN2N"),
2524 
2525 	/* Boost */
2526 	SND_SOC_DAPM_PGA("BST1 CBJ", SND_SOC_NOPM, 0, 0, NULL, 0),
2527 	SND_SOC_DAPM_SUPPLY("CBJ Power", RT5663_PWR_ANLG_3,
2528 		RT5663_PWR_CBJ_SHIFT, 0, NULL, 0),
2529 	SND_SOC_DAPM_PGA("BST2", SND_SOC_NOPM, 0, 0, NULL, 0),
2530 	SND_SOC_DAPM_SUPPLY("BST2 Power", SND_SOC_NOPM, 0, 0,
2531 		rt5663_bst2_power, SND_SOC_DAPM_PRE_PMD |
2532 		SND_SOC_DAPM_POST_PMU),
2533 
2534 	/* REC Mixer */
2535 	SND_SOC_DAPM_MIXER("RECMIX1L", SND_SOC_NOPM, 0, 0, rt5663_recmix1l,
2536 		ARRAY_SIZE(rt5663_recmix1l)),
2537 	SND_SOC_DAPM_MIXER("RECMIX1R", SND_SOC_NOPM, 0, 0, rt5663_recmix1r,
2538 		ARRAY_SIZE(rt5663_recmix1r)),
2539 	SND_SOC_DAPM_SUPPLY("RECMIX1R Power", RT5663_PWR_ANLG_2,
2540 		RT5663_PWR_RECMIX2_SHIFT, 0, NULL, 0),
2541 
2542 	/* ADC */
2543 	SND_SOC_DAPM_ADC("ADC R", NULL, SND_SOC_NOPM, 0, 0),
2544 	SND_SOC_DAPM_SUPPLY("ADC R Power", RT5663_PWR_DIG_1,
2545 		RT5663_PWR_ADC_R1_SHIFT, 0, NULL, 0),
2546 
2547 	/* ADC Mux */
2548 	SND_SOC_DAPM_PGA("STO1 ADC L1", RT5663_STO1_ADC_MIXER,
2549 		RT5663_STO1_ADC_L1_SRC_SHIFT, 0, NULL, 0),
2550 	SND_SOC_DAPM_PGA("STO1 ADC R1", RT5663_STO1_ADC_MIXER,
2551 		RT5663_STO1_ADC_R1_SRC_SHIFT, 0, NULL, 0),
2552 	SND_SOC_DAPM_PGA("STO1 ADC L2", RT5663_STO1_ADC_MIXER,
2553 		RT5663_STO1_ADC_L2_SRC_SHIFT, 1, NULL, 0),
2554 	SND_SOC_DAPM_PGA("STO1 ADC R2", RT5663_STO1_ADC_MIXER,
2555 		RT5663_STO1_ADC_R2_SRC_SHIFT, 1, NULL, 0),
2556 
2557 	SND_SOC_DAPM_MUX("STO1 ADC L Mux", SND_SOC_NOPM, 0, 0,
2558 		&rt5663_sto1_adcl_mux),
2559 	SND_SOC_DAPM_MUX("STO1 ADC R Mux", SND_SOC_NOPM, 0, 0,
2560 		&rt5663_sto1_adcr_mux),
2561 
2562 	/* ADC Mix */
2563 	SND_SOC_DAPM_MIXER("STO1 ADC MIXR", SND_SOC_NOPM, 0, 0,
2564 		rt5663_sto1_adc_r_mix, ARRAY_SIZE(rt5663_sto1_adc_r_mix)),
2565 
2566 	/* Analog DAC Clock */
2567 	SND_SOC_DAPM_SUPPLY("DAC Clock", RT5663_CHOP_DAC_L,
2568 		RT5663_CKGEN_DAC1_SHIFT, 0, NULL, 0),
2569 
2570 	/* Headphone out */
2571 	SND_SOC_DAPM_SWITCH("HPO Playback", SND_SOC_NOPM, 0, 0,
2572 		&rt5663_hpo_switch),
2573 };
2574 
2575 static const struct snd_soc_dapm_widget rt5663_specific_dapm_widgets[] = {
2576 	/* System Clock Pre Divider Gating */
2577 	SND_SOC_DAPM_SUPPLY("Pre Div Power", SND_SOC_NOPM, 0, 0,
2578 		rt5663_pre_div_power, SND_SOC_DAPM_POST_PMU |
2579 		SND_SOC_DAPM_PRE_PMD),
2580 
2581 	/* LDO */
2582 	SND_SOC_DAPM_SUPPLY("LDO ADC", RT5663_PWR_DIG_1,
2583 		RT5663_PWR_LDO_DACREF_SHIFT, 0, NULL, 0),
2584 
2585 	/* ASRC */
2586 	SND_SOC_DAPM_SUPPLY("I2S ASRC", RT5663_ASRC_1,
2587 		RT5663_I2S1_ASRC_SHIFT, 0, NULL, 0),
2588 	SND_SOC_DAPM_SUPPLY("DAC ASRC", RT5663_ASRC_1,
2589 		RT5663_DAC_STO1_ASRC_SHIFT, 0, NULL, 0),
2590 	SND_SOC_DAPM_SUPPLY("ADC ASRC", RT5663_ASRC_1,
2591 		RT5663_ADC_STO1_ASRC_SHIFT, 0, NULL, 0),
2592 
2593 	/* Boost */
2594 	SND_SOC_DAPM_PGA("BST1", SND_SOC_NOPM, 0, 0, NULL, 0),
2595 
2596 	/* STO ADC */
2597 	SND_SOC_DAPM_PGA("STO1 ADC L1", SND_SOC_NOPM, 0, 0, NULL, 0),
2598 	SND_SOC_DAPM_PGA("STO1 ADC L2", SND_SOC_NOPM, 0, 0, NULL, 0),
2599 
2600 	/* Analog DAC source */
2601 	SND_SOC_DAPM_MUX("DAC L Mux", SND_SOC_NOPM, 0, 0, &rt5663_alg_dacl_mux),
2602 	SND_SOC_DAPM_MUX("DAC R Mux", SND_SOC_NOPM, 0, 0, &rt5663_alg_dacr_mux),
2603 };
2604 
2605 static const struct snd_soc_dapm_route rt5663_dapm_routes[] = {
2606 	/* PLL */
2607 	{ "I2S", NULL, "PLL", rt5663_is_sys_clk_from_pll },
2608 
2609 	/* ASRC */
2610 	{ "STO1 ADC Filter", NULL, "ADC ASRC", rt5663_is_using_asrc },
2611 	{ "STO1 DAC Filter", NULL, "DAC ASRC", rt5663_is_using_asrc },
2612 	{ "I2S", NULL, "I2S ASRC", rt5663_i2s_use_asrc },
2613 
2614 	{ "ADC L", NULL, "ADC L Power" },
2615 	{ "ADC L", NULL, "ADC Clock" },
2616 
2617 	{ "STO1 ADC L2", NULL, "STO1 DAC MIXL" },
2618 
2619 	{ "STO1 ADC MIXL", "ADC1 Switch", "STO1 ADC L1" },
2620 	{ "STO1 ADC MIXL", "ADC2 Switch", "STO1 ADC L2" },
2621 	{ "STO1 ADC MIXL", NULL, "STO1 ADC Filter" },
2622 
2623 	{ "IF1 ADC1", NULL, "STO1 ADC MIXL" },
2624 	{ "IF ADC", NULL, "IF1 ADC1" },
2625 	{ "AIFTX", NULL, "IF ADC" },
2626 	{ "AIFTX", NULL, "I2S" },
2627 
2628 	{ "AIFRX", NULL, "I2S" },
2629 	{ "IF DAC", NULL, "AIFRX" },
2630 	{ "IF1 DAC1 L", NULL, "IF DAC" },
2631 	{ "IF1 DAC1 R", NULL, "IF DAC" },
2632 
2633 	{ "ADDA MIXL", "ADC L Switch", "STO1 ADC MIXL" },
2634 	{ "ADDA MIXL", "DAC L Switch", "IF1 DAC1 L" },
2635 	{ "ADDA MIXL", NULL, "STO1 DAC Filter" },
2636 	{ "ADDA MIXL", NULL, "STO1 DAC L Power" },
2637 	{ "ADDA MIXR", "DAC R Switch", "IF1 DAC1 R" },
2638 	{ "ADDA MIXR", NULL, "STO1 DAC Filter" },
2639 	{ "ADDA MIXR", NULL, "STO1 DAC R Power" },
2640 
2641 	{ "DAC L1", NULL, "ADDA MIXL" },
2642 	{ "DAC R1", NULL, "ADDA MIXR" },
2643 
2644 	{ "STO1 DAC MIXL", "DAC L Switch", "DAC L1" },
2645 	{ "STO1 DAC MIXL", NULL, "STO1 DAC L Power" },
2646 	{ "STO1 DAC MIXL", NULL, "STO1 DAC Filter" },
2647 	{ "STO1 DAC MIXR", "DAC R Switch", "DAC R1" },
2648 	{ "STO1 DAC MIXR", NULL, "STO1 DAC R Power" },
2649 	{ "STO1 DAC MIXR", NULL, "STO1 DAC Filter" },
2650 
2651 	{ "HP Amp", NULL, "HP Charge Pump" },
2652 	{ "HP Amp", NULL, "DAC L" },
2653 	{ "HP Amp", NULL, "DAC R" },
2654 };
2655 
2656 static const struct snd_soc_dapm_route rt5663_v2_specific_dapm_routes[] = {
2657 	{ "MICBIAS1", NULL, "LDO2" },
2658 	{ "MICBIAS2", NULL, "LDO2" },
2659 
2660 	{ "BST1 CBJ", NULL, "IN1P" },
2661 	{ "BST1 CBJ", NULL, "IN1N" },
2662 	{ "BST1 CBJ", NULL, "CBJ Power" },
2663 
2664 	{ "BST2", NULL, "IN2P" },
2665 	{ "BST2", NULL, "IN2N" },
2666 	{ "BST2", NULL, "BST2 Power" },
2667 
2668 	{ "RECMIX1L", "BST2 Switch", "BST2" },
2669 	{ "RECMIX1L", "BST1 CBJ Switch", "BST1 CBJ" },
2670 	{ "RECMIX1L", NULL, "RECMIX1L Power" },
2671 	{ "RECMIX1R", "BST2 Switch", "BST2" },
2672 	{ "RECMIX1R", NULL, "RECMIX1R Power" },
2673 
2674 	{ "ADC L", NULL, "RECMIX1L" },
2675 	{ "ADC R", NULL, "RECMIX1R" },
2676 	{ "ADC R", NULL, "ADC R Power" },
2677 	{ "ADC R", NULL, "ADC Clock" },
2678 
2679 	{ "STO1 ADC L Mux", "ADC L", "ADC L" },
2680 	{ "STO1 ADC L Mux", "ADC R", "ADC R" },
2681 	{ "STO1 ADC L1", NULL, "STO1 ADC L Mux" },
2682 
2683 	{ "STO1 ADC R Mux", "ADC L", "ADC L" },
2684 	{ "STO1 ADC R Mux", "ADC R", "ADC R" },
2685 	{ "STO1 ADC R1", NULL, "STO1 ADC R Mux" },
2686 	{ "STO1 ADC R2", NULL, "STO1 DAC MIXR" },
2687 
2688 	{ "STO1 ADC MIXR", "ADC1 Switch", "STO1 ADC R1" },
2689 	{ "STO1 ADC MIXR", "ADC2 Switch", "STO1 ADC R2" },
2690 	{ "STO1 ADC MIXR", NULL, "STO1 ADC Filter" },
2691 
2692 	{ "IF1 ADC1", NULL, "STO1 ADC MIXR" },
2693 
2694 	{ "ADDA MIXR", "ADC R Switch", "STO1 ADC MIXR" },
2695 
2696 	{ "DAC L", NULL, "STO1 DAC MIXL" },
2697 	{ "DAC L", NULL, "LDO DAC" },
2698 	{ "DAC L", NULL, "DAC Clock" },
2699 	{ "DAC R", NULL, "STO1 DAC MIXR" },
2700 	{ "DAC R", NULL, "LDO DAC" },
2701 	{ "DAC R", NULL, "DAC Clock" },
2702 
2703 	{ "HPO Playback", "Switch", "HP Amp" },
2704 	{ "HPOL", NULL, "HPO Playback" },
2705 	{ "HPOR", NULL, "HPO Playback" },
2706 };
2707 
2708 static const struct snd_soc_dapm_route rt5663_specific_dapm_routes[] = {
2709 	{ "I2S", NULL, "Pre Div Power" },
2710 
2711 	{ "BST1", NULL, "IN1P" },
2712 	{ "BST1", NULL, "IN1N" },
2713 	{ "BST1", NULL, "RECMIX1L Power" },
2714 
2715 	{ "ADC L", NULL, "BST1" },
2716 
2717 	{ "STO1 ADC L1", NULL, "ADC L" },
2718 
2719 	{ "DAC L Mux", "DAC L",  "DAC L1" },
2720 	{ "DAC L Mux", "STO DAC MIXL", "STO1 DAC MIXL" },
2721 	{ "DAC R Mux", "DAC R",  "DAC R1"},
2722 	{ "DAC R Mux", "STO DAC MIXR", "STO1 DAC MIXR" },
2723 
2724 	{ "DAC L", NULL, "DAC L Mux" },
2725 	{ "DAC R", NULL, "DAC R Mux" },
2726 
2727 	{ "HPOL", NULL, "HP Amp" },
2728 	{ "HPOR", NULL, "HP Amp" },
2729 };
2730 
2731 static int rt5663_hw_params(struct snd_pcm_substream *substream,
2732 	struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
2733 {
2734 	struct snd_soc_component *component = dai->component;
2735 	struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
2736 	unsigned int val_len = 0;
2737 	int pre_div;
2738 
2739 	rt5663->lrck = params_rate(params);
2740 
2741 	dev_dbg(dai->dev, "bclk is %dHz and sysclk is %dHz\n",
2742 		rt5663->lrck, rt5663->sysclk);
2743 
2744 	pre_div = rl6231_get_clk_info(rt5663->sysclk, rt5663->lrck);
2745 	if (pre_div < 0) {
2746 		dev_err(component->dev, "Unsupported clock setting %d for DAI %d\n",
2747 			rt5663->lrck, dai->id);
2748 		return -EINVAL;
2749 	}
2750 
2751 	dev_dbg(dai->dev, "pre_div is %d for iis %d\n", pre_div, dai->id);
2752 
2753 	switch (params_width(params)) {
2754 	case 8:
2755 		val_len = RT5663_I2S_DL_8;
2756 		break;
2757 	case 16:
2758 		val_len = RT5663_I2S_DL_16;
2759 		break;
2760 	case 20:
2761 		val_len = RT5663_I2S_DL_20;
2762 		break;
2763 	case 24:
2764 		val_len = RT5663_I2S_DL_24;
2765 		break;
2766 	default:
2767 		return -EINVAL;
2768 	}
2769 
2770 	snd_soc_component_update_bits(component, RT5663_I2S1_SDP,
2771 		RT5663_I2S_DL_MASK, val_len);
2772 
2773 	snd_soc_component_update_bits(component, RT5663_ADDA_CLK_1,
2774 		RT5663_I2S_PD1_MASK, pre_div << RT5663_I2S_PD1_SHIFT);
2775 
2776 	return 0;
2777 }
2778 
2779 static int rt5663_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2780 {
2781 	struct snd_soc_component *component = dai->component;
2782 	unsigned int reg_val = 0;
2783 
2784 	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2785 	case SND_SOC_DAIFMT_CBM_CFM:
2786 		break;
2787 	case SND_SOC_DAIFMT_CBS_CFS:
2788 		reg_val |= RT5663_I2S_MS_S;
2789 		break;
2790 	default:
2791 		return -EINVAL;
2792 	}
2793 
2794 	switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2795 	case SND_SOC_DAIFMT_NB_NF:
2796 		break;
2797 	case SND_SOC_DAIFMT_IB_NF:
2798 		reg_val |= RT5663_I2S_BP_INV;
2799 		break;
2800 	default:
2801 		return -EINVAL;
2802 	}
2803 
2804 	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2805 	case SND_SOC_DAIFMT_I2S:
2806 		break;
2807 	case SND_SOC_DAIFMT_LEFT_J:
2808 		reg_val |= RT5663_I2S_DF_LEFT;
2809 		break;
2810 	case SND_SOC_DAIFMT_DSP_A:
2811 		reg_val |= RT5663_I2S_DF_PCM_A;
2812 		break;
2813 	case SND_SOC_DAIFMT_DSP_B:
2814 		reg_val |= RT5663_I2S_DF_PCM_B;
2815 		break;
2816 	default:
2817 		return -EINVAL;
2818 	}
2819 
2820 	snd_soc_component_update_bits(component, RT5663_I2S1_SDP, RT5663_I2S_MS_MASK |
2821 		RT5663_I2S_BP_MASK | RT5663_I2S_DF_MASK, reg_val);
2822 
2823 	return 0;
2824 }
2825 
2826 static int rt5663_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id,
2827 	unsigned int freq, int dir)
2828 {
2829 	struct snd_soc_component *component = dai->component;
2830 	struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
2831 	unsigned int reg_val = 0;
2832 
2833 	if (freq == rt5663->sysclk && clk_id == rt5663->sysclk_src)
2834 		return 0;
2835 
2836 	switch (clk_id) {
2837 	case RT5663_SCLK_S_MCLK:
2838 		reg_val |= RT5663_SCLK_SRC_MCLK;
2839 		break;
2840 	case RT5663_SCLK_S_PLL1:
2841 		reg_val |= RT5663_SCLK_SRC_PLL1;
2842 		break;
2843 	case RT5663_SCLK_S_RCCLK:
2844 		reg_val |= RT5663_SCLK_SRC_RCCLK;
2845 		break;
2846 	default:
2847 		dev_err(component->dev, "Invalid clock id (%d)\n", clk_id);
2848 		return -EINVAL;
2849 	}
2850 	snd_soc_component_update_bits(component, RT5663_GLB_CLK, RT5663_SCLK_SRC_MASK,
2851 		reg_val);
2852 	rt5663->sysclk = freq;
2853 	rt5663->sysclk_src = clk_id;
2854 
2855 	dev_dbg(component->dev, "Sysclk is %dHz and clock id is %d\n",
2856 		freq, clk_id);
2857 
2858 	return 0;
2859 }
2860 
2861 static int rt5663_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
2862 			unsigned int freq_in, unsigned int freq_out)
2863 {
2864 	struct snd_soc_component *component = dai->component;
2865 	struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
2866 	struct rl6231_pll_code pll_code;
2867 	int ret;
2868 	int mask, shift, val;
2869 
2870 	if (source == rt5663->pll_src && freq_in == rt5663->pll_in &&
2871 	    freq_out == rt5663->pll_out)
2872 		return 0;
2873 
2874 	if (!freq_in || !freq_out) {
2875 		dev_dbg(component->dev, "PLL disabled\n");
2876 
2877 		rt5663->pll_in = 0;
2878 		rt5663->pll_out = 0;
2879 		snd_soc_component_update_bits(component, RT5663_GLB_CLK,
2880 			RT5663_SCLK_SRC_MASK, RT5663_SCLK_SRC_MCLK);
2881 		return 0;
2882 	}
2883 
2884 	switch (rt5663->codec_ver) {
2885 	case CODEC_VER_1:
2886 		mask = RT5663_V2_PLL1_SRC_MASK;
2887 		shift = RT5663_V2_PLL1_SRC_SHIFT;
2888 		break;
2889 	case CODEC_VER_0:
2890 		mask = RT5663_PLL1_SRC_MASK;
2891 		shift = RT5663_PLL1_SRC_SHIFT;
2892 		break;
2893 	default:
2894 		dev_err(component->dev, "Unknown CODEC Version\n");
2895 		return -EINVAL;
2896 	}
2897 
2898 	switch (source) {
2899 	case RT5663_PLL1_S_MCLK:
2900 		val = 0x0;
2901 		break;
2902 	case RT5663_PLL1_S_BCLK1:
2903 		val = 0x1;
2904 		break;
2905 	default:
2906 		dev_err(component->dev, "Unknown PLL source %d\n", source);
2907 		return -EINVAL;
2908 	}
2909 	snd_soc_component_update_bits(component, RT5663_GLB_CLK, mask, (val << shift));
2910 
2911 	ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
2912 	if (ret < 0) {
2913 		dev_err(component->dev, "Unsupport input clock %d\n", freq_in);
2914 		return ret;
2915 	}
2916 
2917 	dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n", pll_code.m_bp,
2918 		(pll_code.m_bp ? 0 : pll_code.m_code), pll_code.n_code,
2919 		pll_code.k_code);
2920 
2921 	snd_soc_component_write(component, RT5663_PLL_1,
2922 		pll_code.n_code << RT5663_PLL_N_SHIFT | pll_code.k_code);
2923 	snd_soc_component_write(component, RT5663_PLL_2,
2924 		(pll_code.m_bp ? 0 : pll_code.m_code) << RT5663_PLL_M_SHIFT |
2925 		pll_code.m_bp << RT5663_PLL_M_BP_SHIFT);
2926 
2927 	rt5663->pll_in = freq_in;
2928 	rt5663->pll_out = freq_out;
2929 	rt5663->pll_src = source;
2930 
2931 	return 0;
2932 }
2933 
2934 static int rt5663_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
2935 	unsigned int rx_mask, int slots, int slot_width)
2936 {
2937 	struct snd_soc_component *component = dai->component;
2938 	struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
2939 	unsigned int val = 0, reg;
2940 
2941 	if (rx_mask || tx_mask)
2942 		val |= RT5663_TDM_MODE_TDM;
2943 
2944 	switch (slots) {
2945 	case 4:
2946 		val |= RT5663_TDM_IN_CH_4;
2947 		val |= RT5663_TDM_OUT_CH_4;
2948 		break;
2949 	case 6:
2950 		val |= RT5663_TDM_IN_CH_6;
2951 		val |= RT5663_TDM_OUT_CH_6;
2952 		break;
2953 	case 8:
2954 		val |= RT5663_TDM_IN_CH_8;
2955 		val |= RT5663_TDM_OUT_CH_8;
2956 		break;
2957 	case 2:
2958 		break;
2959 	default:
2960 		return -EINVAL;
2961 	}
2962 
2963 	switch (slot_width) {
2964 	case 20:
2965 		val |= RT5663_TDM_IN_LEN_20;
2966 		val |= RT5663_TDM_OUT_LEN_20;
2967 		break;
2968 	case 24:
2969 		val |= RT5663_TDM_IN_LEN_24;
2970 		val |= RT5663_TDM_OUT_LEN_24;
2971 		break;
2972 	case 32:
2973 		val |= RT5663_TDM_IN_LEN_32;
2974 		val |= RT5663_TDM_OUT_LEN_32;
2975 		break;
2976 	case 16:
2977 		break;
2978 	default:
2979 		return -EINVAL;
2980 	}
2981 
2982 	switch (rt5663->codec_ver) {
2983 	case CODEC_VER_1:
2984 		reg = RT5663_TDM_2;
2985 		break;
2986 	case CODEC_VER_0:
2987 		reg = RT5663_TDM_1;
2988 		break;
2989 	default:
2990 		dev_err(component->dev, "Unknown CODEC Version\n");
2991 		return -EINVAL;
2992 	}
2993 
2994 	snd_soc_component_update_bits(component, reg, RT5663_TDM_MODE_MASK |
2995 		RT5663_TDM_IN_CH_MASK | RT5663_TDM_OUT_CH_MASK |
2996 		RT5663_TDM_IN_LEN_MASK | RT5663_TDM_OUT_LEN_MASK, val);
2997 
2998 	return 0;
2999 }
3000 
3001 static int rt5663_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio)
3002 {
3003 	struct snd_soc_component *component = dai->component;
3004 	struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
3005 	unsigned int reg;
3006 
3007 	dev_dbg(component->dev, "%s ratio = %d\n", __func__, ratio);
3008 
3009 	if (rt5663->codec_ver == CODEC_VER_1)
3010 		reg = RT5663_TDM_9;
3011 	else
3012 		reg = RT5663_TDM_5;
3013 
3014 	switch (ratio) {
3015 	case 32:
3016 		snd_soc_component_update_bits(component, reg,
3017 			RT5663_TDM_LENGTN_MASK,
3018 			RT5663_TDM_LENGTN_16);
3019 		break;
3020 	case 40:
3021 		snd_soc_component_update_bits(component, reg,
3022 			RT5663_TDM_LENGTN_MASK,
3023 			RT5663_TDM_LENGTN_20);
3024 		break;
3025 	case 48:
3026 		snd_soc_component_update_bits(component, reg,
3027 			RT5663_TDM_LENGTN_MASK,
3028 			RT5663_TDM_LENGTN_24);
3029 		break;
3030 	case 64:
3031 		snd_soc_component_update_bits(component, reg,
3032 			RT5663_TDM_LENGTN_MASK,
3033 			RT5663_TDM_LENGTN_32);
3034 		break;
3035 	default:
3036 		dev_err(component->dev, "Invalid ratio!\n");
3037 		return -EINVAL;
3038 	}
3039 
3040 	return 0;
3041 }
3042 
3043 static int rt5663_set_bias_level(struct snd_soc_component *component,
3044 			enum snd_soc_bias_level level)
3045 {
3046 	struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
3047 
3048 	switch (level) {
3049 	case SND_SOC_BIAS_ON:
3050 		snd_soc_component_update_bits(component, RT5663_PWR_ANLG_1,
3051 			RT5663_PWR_FV1_MASK | RT5663_PWR_FV2_MASK,
3052 			RT5663_PWR_FV1 | RT5663_PWR_FV2);
3053 		break;
3054 
3055 	case SND_SOC_BIAS_PREPARE:
3056 		if (rt5663->codec_ver == CODEC_VER_1) {
3057 			snd_soc_component_update_bits(component, RT5663_DIG_MISC,
3058 				RT5663_DIG_GATE_CTRL_MASK,
3059 				RT5663_DIG_GATE_CTRL_EN);
3060 			snd_soc_component_update_bits(component, RT5663_SIG_CLK_DET,
3061 				RT5663_EN_ANA_CLK_DET_MASK |
3062 				RT5663_PWR_CLK_DET_MASK,
3063 				RT5663_EN_ANA_CLK_DET_AUTO |
3064 				RT5663_PWR_CLK_DET_EN);
3065 		}
3066 		break;
3067 
3068 	case SND_SOC_BIAS_STANDBY:
3069 		if (rt5663->codec_ver == CODEC_VER_1)
3070 			snd_soc_component_update_bits(component, RT5663_DIG_MISC,
3071 				RT5663_DIG_GATE_CTRL_MASK,
3072 				RT5663_DIG_GATE_CTRL_DIS);
3073 		snd_soc_component_update_bits(component, RT5663_PWR_ANLG_1,
3074 			RT5663_PWR_VREF1_MASK | RT5663_PWR_VREF2_MASK |
3075 			RT5663_PWR_FV1_MASK | RT5663_PWR_FV2_MASK |
3076 			RT5663_PWR_MB_MASK, RT5663_PWR_VREF1 |
3077 			RT5663_PWR_VREF2 | RT5663_PWR_MB);
3078 		usleep_range(10000, 10005);
3079 		if (rt5663->codec_ver == CODEC_VER_1) {
3080 			snd_soc_component_update_bits(component, RT5663_SIG_CLK_DET,
3081 				RT5663_EN_ANA_CLK_DET_MASK |
3082 				RT5663_PWR_CLK_DET_MASK,
3083 				RT5663_EN_ANA_CLK_DET_DIS |
3084 				RT5663_PWR_CLK_DET_DIS);
3085 		}
3086 		break;
3087 
3088 	case SND_SOC_BIAS_OFF:
3089 		snd_soc_component_update_bits(component, RT5663_PWR_ANLG_1,
3090 			RT5663_PWR_VREF1_MASK | RT5663_PWR_VREF2_MASK |
3091 			RT5663_PWR_FV1 | RT5663_PWR_FV2, 0x0);
3092 		break;
3093 
3094 	default:
3095 		break;
3096 	}
3097 
3098 	return 0;
3099 }
3100 
3101 static int rt5663_probe(struct snd_soc_component *component)
3102 {
3103 	struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
3104 	struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
3105 
3106 	rt5663->component = component;
3107 
3108 	switch (rt5663->codec_ver) {
3109 	case CODEC_VER_1:
3110 		snd_soc_dapm_new_controls(dapm,
3111 			rt5663_v2_specific_dapm_widgets,
3112 			ARRAY_SIZE(rt5663_v2_specific_dapm_widgets));
3113 		snd_soc_dapm_add_routes(dapm,
3114 			rt5663_v2_specific_dapm_routes,
3115 			ARRAY_SIZE(rt5663_v2_specific_dapm_routes));
3116 		snd_soc_add_component_controls(component, rt5663_v2_specific_controls,
3117 			ARRAY_SIZE(rt5663_v2_specific_controls));
3118 		break;
3119 	case CODEC_VER_0:
3120 		snd_soc_dapm_new_controls(dapm,
3121 			rt5663_specific_dapm_widgets,
3122 			ARRAY_SIZE(rt5663_specific_dapm_widgets));
3123 		snd_soc_dapm_add_routes(dapm,
3124 			rt5663_specific_dapm_routes,
3125 			ARRAY_SIZE(rt5663_specific_dapm_routes));
3126 		snd_soc_add_component_controls(component, rt5663_specific_controls,
3127 			ARRAY_SIZE(rt5663_specific_controls));
3128 
3129 		if (!rt5663->imp_table)
3130 			snd_soc_add_component_controls(component, rt5663_hpvol_controls,
3131 				ARRAY_SIZE(rt5663_hpvol_controls));
3132 		break;
3133 	}
3134 
3135 	return 0;
3136 }
3137 
3138 static void rt5663_remove(struct snd_soc_component *component)
3139 {
3140 	struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
3141 
3142 	regmap_write(rt5663->regmap, RT5663_RESET, 0);
3143 }
3144 
3145 #ifdef CONFIG_PM
3146 static int rt5663_suspend(struct snd_soc_component *component)
3147 {
3148 	struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
3149 
3150 	regcache_cache_only(rt5663->regmap, true);
3151 	regcache_mark_dirty(rt5663->regmap);
3152 
3153 	return 0;
3154 }
3155 
3156 static int rt5663_resume(struct snd_soc_component *component)
3157 {
3158 	struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
3159 
3160 	regcache_cache_only(rt5663->regmap, false);
3161 	regcache_sync(rt5663->regmap);
3162 
3163 	rt5663_irq(0, rt5663);
3164 
3165 	return 0;
3166 }
3167 #else
3168 #define rt5663_suspend NULL
3169 #define rt5663_resume NULL
3170 #endif
3171 
3172 #define RT5663_STEREO_RATES SNDRV_PCM_RATE_8000_192000
3173 #define RT5663_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
3174 			SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
3175 
3176 static const struct snd_soc_dai_ops rt5663_aif_dai_ops = {
3177 	.hw_params = rt5663_hw_params,
3178 	.set_fmt = rt5663_set_dai_fmt,
3179 	.set_sysclk = rt5663_set_dai_sysclk,
3180 	.set_pll = rt5663_set_dai_pll,
3181 	.set_tdm_slot = rt5663_set_tdm_slot,
3182 	.set_bclk_ratio = rt5663_set_bclk_ratio,
3183 };
3184 
3185 static struct snd_soc_dai_driver rt5663_dai[] = {
3186 	{
3187 		.name = "rt5663-aif",
3188 		.id = RT5663_AIF,
3189 		.playback = {
3190 			.stream_name = "AIF Playback",
3191 			.channels_min = 1,
3192 			.channels_max = 2,
3193 			.rates = RT5663_STEREO_RATES,
3194 			.formats = RT5663_FORMATS,
3195 		},
3196 		.capture = {
3197 			.stream_name = "AIF Capture",
3198 			.channels_min = 1,
3199 			.channels_max = 2,
3200 			.rates = RT5663_STEREO_RATES,
3201 			.formats = RT5663_FORMATS,
3202 		},
3203 		.ops = &rt5663_aif_dai_ops,
3204 	},
3205 };
3206 
3207 static const struct snd_soc_component_driver soc_component_dev_rt5663 = {
3208 	.probe			= rt5663_probe,
3209 	.remove			= rt5663_remove,
3210 	.suspend		= rt5663_suspend,
3211 	.resume			= rt5663_resume,
3212 	.set_bias_level		= rt5663_set_bias_level,
3213 	.controls		= rt5663_snd_controls,
3214 	.num_controls		= ARRAY_SIZE(rt5663_snd_controls),
3215 	.dapm_widgets		= rt5663_dapm_widgets,
3216 	.num_dapm_widgets	= ARRAY_SIZE(rt5663_dapm_widgets),
3217 	.dapm_routes		= rt5663_dapm_routes,
3218 	.num_dapm_routes	= ARRAY_SIZE(rt5663_dapm_routes),
3219 	.use_pmdown_time	= 1,
3220 	.endianness		= 1,
3221 	.non_legacy_dai_naming	= 1,
3222 
3223 };
3224 
3225 static const struct regmap_config rt5663_v2_regmap = {
3226 	.reg_bits = 16,
3227 	.val_bits = 16,
3228 	.use_single_rw = true,
3229 	.max_register = 0x07fa,
3230 	.volatile_reg = rt5663_v2_volatile_register,
3231 	.readable_reg = rt5663_v2_readable_register,
3232 	.cache_type = REGCACHE_RBTREE,
3233 	.reg_defaults = rt5663_v2_reg,
3234 	.num_reg_defaults = ARRAY_SIZE(rt5663_v2_reg),
3235 };
3236 
3237 static const struct regmap_config rt5663_regmap = {
3238 	.reg_bits = 16,
3239 	.val_bits = 16,
3240 	.use_single_rw = true,
3241 	.max_register = 0x03f3,
3242 	.volatile_reg = rt5663_volatile_register,
3243 	.readable_reg = rt5663_readable_register,
3244 	.cache_type = REGCACHE_RBTREE,
3245 	.reg_defaults = rt5663_reg,
3246 	.num_reg_defaults = ARRAY_SIZE(rt5663_reg),
3247 };
3248 
3249 static const struct regmap_config temp_regmap = {
3250 	.name = "nocache",
3251 	.reg_bits = 16,
3252 	.val_bits = 16,
3253 	.use_single_rw = true,
3254 	.max_register = 0x03f3,
3255 	.cache_type = REGCACHE_NONE,
3256 };
3257 
3258 static const struct i2c_device_id rt5663_i2c_id[] = {
3259 	{ "rt5663", 0 },
3260 	{}
3261 };
3262 MODULE_DEVICE_TABLE(i2c, rt5663_i2c_id);
3263 
3264 #if defined(CONFIG_OF)
3265 static const struct of_device_id rt5663_of_match[] = {
3266 	{ .compatible = "realtek,rt5663", },
3267 	{},
3268 };
3269 MODULE_DEVICE_TABLE(of, rt5663_of_match);
3270 #endif
3271 
3272 #ifdef CONFIG_ACPI
3273 static const struct acpi_device_id rt5663_acpi_match[] = {
3274 	{ "10EC5663", 0},
3275 	{},
3276 };
3277 MODULE_DEVICE_TABLE(acpi, rt5663_acpi_match);
3278 #endif
3279 
3280 static void rt5663_v2_calibrate(struct rt5663_priv *rt5663)
3281 {
3282 	regmap_write(rt5663->regmap, RT5663_BIAS_CUR_8, 0xa402);
3283 	regmap_write(rt5663->regmap, RT5663_PWR_DIG_1, 0x0100);
3284 	regmap_write(rt5663->regmap, RT5663_RECMIX, 0x4040);
3285 	regmap_write(rt5663->regmap, RT5663_DIG_MISC, 0x0001);
3286 	regmap_write(rt5663->regmap, RT5663_RC_CLK, 0x0380);
3287 	regmap_write(rt5663->regmap, RT5663_GLB_CLK, 0x8000);
3288 	regmap_write(rt5663->regmap, RT5663_ADDA_CLK_1, 0x1000);
3289 	regmap_write(rt5663->regmap, RT5663_CHOP_DAC_L, 0x3030);
3290 	regmap_write(rt5663->regmap, RT5663_CALIB_ADC, 0x3c05);
3291 	regmap_write(rt5663->regmap, RT5663_PWR_ANLG_1, 0xa23e);
3292 	msleep(40);
3293 	regmap_write(rt5663->regmap, RT5663_PWR_ANLG_1, 0xf23e);
3294 	regmap_write(rt5663->regmap, RT5663_HP_CALIB_2, 0x0321);
3295 	regmap_write(rt5663->regmap, RT5663_HP_CALIB_1, 0xfc00);
3296 	msleep(500);
3297 }
3298 
3299 static void rt5663_calibrate(struct rt5663_priv *rt5663)
3300 {
3301 	int value, count;
3302 
3303 	regmap_write(rt5663->regmap, RT5663_RESET, 0x0000);
3304 	msleep(20);
3305 	regmap_write(rt5663->regmap, RT5663_ANA_BIAS_CUR_4, 0x00a1);
3306 	regmap_write(rt5663->regmap, RT5663_RC_CLK, 0x0380);
3307 	regmap_write(rt5663->regmap, RT5663_GLB_CLK, 0x8000);
3308 	regmap_write(rt5663->regmap, RT5663_ADDA_CLK_1, 0x1000);
3309 	regmap_write(rt5663->regmap, RT5663_VREF_RECMIX, 0x0032);
3310 	regmap_write(rt5663->regmap, RT5663_HP_IMP_SEN_19, 0x000c);
3311 	regmap_write(rt5663->regmap, RT5663_DUMMY_1, 0x0324);
3312 	regmap_write(rt5663->regmap, RT5663_DIG_MISC, 0x8001);
3313 	regmap_write(rt5663->regmap, RT5663_PWR_ANLG_1, 0xa23b);
3314 	msleep(30);
3315 	regmap_write(rt5663->regmap, RT5663_PWR_ANLG_1, 0xf23b);
3316 	regmap_write(rt5663->regmap, RT5663_PWR_ANLG_2, 0x8000);
3317 	regmap_write(rt5663->regmap, RT5663_PWR_ANLG_3, 0x0008);
3318 	regmap_write(rt5663->regmap, RT5663_PRE_DIV_GATING_1, 0xffff);
3319 	regmap_write(rt5663->regmap, RT5663_PRE_DIV_GATING_2, 0xffff);
3320 	regmap_write(rt5663->regmap, RT5663_CBJ_1, 0x8c10);
3321 	regmap_write(rt5663->regmap, RT5663_IL_CMD_2, 0x00c1);
3322 	regmap_write(rt5663->regmap, RT5663_EM_JACK_TYPE_1, 0xb880);
3323 	regmap_write(rt5663->regmap, RT5663_EM_JACK_TYPE_2, 0x4110);
3324 	regmap_write(rt5663->regmap, RT5663_EM_JACK_TYPE_2, 0x4118);
3325 
3326 	count = 0;
3327 	while (true) {
3328 		regmap_read(rt5663->regmap, RT5663_INT_ST_2, &value);
3329 		if (!(value & 0x80))
3330 			usleep_range(10000, 10005);
3331 		else
3332 			break;
3333 
3334 		if (++count > 200)
3335 			break;
3336 	}
3337 
3338 	regmap_write(rt5663->regmap, RT5663_HP_IMP_SEN_19, 0x0000);
3339 	regmap_write(rt5663->regmap, RT5663_DEPOP_2, 0x3003);
3340 	regmap_write(rt5663->regmap, RT5663_DEPOP_1, 0x0038);
3341 	regmap_write(rt5663->regmap, RT5663_DEPOP_1, 0x003b);
3342 	regmap_write(rt5663->regmap, RT5663_PWR_DIG_2, 0x8400);
3343 	regmap_write(rt5663->regmap, RT5663_PWR_DIG_1, 0x8df8);
3344 	regmap_write(rt5663->regmap, RT5663_PWR_ANLG_2, 0x8003);
3345 	regmap_write(rt5663->regmap, RT5663_PWR_ANLG_3, 0x018c);
3346 	regmap_write(rt5663->regmap, RT5663_HP_CHARGE_PUMP_1, 0x1e32);
3347 	regmap_write(rt5663->regmap, RT5663_DACREF_LDO, 0x3b0b);
3348 	msleep(40);
3349 	regmap_write(rt5663->regmap, RT5663_STO_DAC_MIXER, 0x0000);
3350 	regmap_write(rt5663->regmap, RT5663_BYPASS_STO_DAC, 0x000c);
3351 	regmap_write(rt5663->regmap, RT5663_HP_BIAS, 0xafaa);
3352 	regmap_write(rt5663->regmap, RT5663_CHARGE_PUMP_1, 0x2224);
3353 	regmap_write(rt5663->regmap, RT5663_HP_OUT_EN, 0x8088);
3354 	regmap_write(rt5663->regmap, RT5663_STO_DRE_9, 0x0017);
3355 	regmap_write(rt5663->regmap, RT5663_STO_DRE_10, 0x0017);
3356 	regmap_write(rt5663->regmap, RT5663_STO1_ADC_MIXER, 0x4040);
3357 	regmap_write(rt5663->regmap, RT5663_CHOP_ADC, 0x3000);
3358 	regmap_write(rt5663->regmap, RT5663_RECMIX, 0x0005);
3359 	regmap_write(rt5663->regmap, RT5663_ADDA_RST, 0xc000);
3360 	regmap_write(rt5663->regmap, RT5663_STO1_HPF_ADJ1, 0x3320);
3361 	regmap_write(rt5663->regmap, RT5663_HP_CALIB_2, 0x00c9);
3362 	regmap_write(rt5663->regmap, RT5663_DUMMY_1, 0x004c);
3363 	regmap_write(rt5663->regmap, RT5663_ANA_BIAS_CUR_1, 0x1111);
3364 	regmap_write(rt5663->regmap, RT5663_BIAS_CUR_8, 0x4402);
3365 	regmap_write(rt5663->regmap, RT5663_CHARGE_PUMP_2, 0x3311);
3366 	regmap_write(rt5663->regmap, RT5663_HP_CALIB_1, 0x0069);
3367 	regmap_write(rt5663->regmap, RT5663_HP_CALIB_3, 0x06ce);
3368 	regmap_write(rt5663->regmap, RT5663_HP_CALIB_1_1, 0x6800);
3369 	regmap_write(rt5663->regmap, RT5663_CHARGE_PUMP_2, 0x1100);
3370 	regmap_write(rt5663->regmap, RT5663_HP_CALIB_7, 0x0057);
3371 	regmap_write(rt5663->regmap, RT5663_HP_CALIB_1_1, 0xe800);
3372 
3373 	count = 0;
3374 	while (true) {
3375 		regmap_read(rt5663->regmap, RT5663_HP_CALIB_1_1, &value);
3376 		if (value & 0x8000)
3377 			usleep_range(10000, 10005);
3378 		else
3379 			break;
3380 
3381 		if (count > 200)
3382 			return;
3383 		count++;
3384 	}
3385 
3386 	regmap_write(rt5663->regmap, RT5663_HP_CALIB_1_1, 0x6200);
3387 	regmap_write(rt5663->regmap, RT5663_HP_CALIB_7, 0x0059);
3388 	regmap_write(rt5663->regmap, RT5663_HP_CALIB_1_1, 0xe200);
3389 
3390 	count = 0;
3391 	while (true) {
3392 		regmap_read(rt5663->regmap, RT5663_HP_CALIB_1_1, &value);
3393 		if (value & 0x8000)
3394 			usleep_range(10000, 10005);
3395 		else
3396 			break;
3397 
3398 		if (count > 200)
3399 			return;
3400 		count++;
3401 	}
3402 
3403 	regmap_write(rt5663->regmap, RT5663_EM_JACK_TYPE_1, 0xb8e0);
3404 	usleep_range(10000, 10005);
3405 	regmap_write(rt5663->regmap, RT5663_PWR_ANLG_1, 0x003b);
3406 	usleep_range(10000, 10005);
3407 	regmap_write(rt5663->regmap, RT5663_PWR_DIG_1, 0x0000);
3408 	usleep_range(10000, 10005);
3409 	regmap_write(rt5663->regmap, RT5663_DEPOP_1, 0x000b);
3410 	usleep_range(10000, 10005);
3411 	regmap_write(rt5663->regmap, RT5663_DEPOP_1, 0x0008);
3412 	usleep_range(10000, 10005);
3413 	regmap_write(rt5663->regmap, RT5663_PWR_ANLG_2, 0x0000);
3414 	usleep_range(10000, 10005);
3415 }
3416 
3417 static int rt5663_parse_dp(struct rt5663_priv *rt5663, struct device *dev)
3418 {
3419 	int table_size;
3420 
3421 	device_property_read_u32(dev, "realtek,dc_offset_l_manual",
3422 		&rt5663->pdata.dc_offset_l_manual);
3423 	device_property_read_u32(dev, "realtek,dc_offset_r_manual",
3424 		&rt5663->pdata.dc_offset_r_manual);
3425 	device_property_read_u32(dev, "realtek,dc_offset_l_manual_mic",
3426 		&rt5663->pdata.dc_offset_l_manual_mic);
3427 	device_property_read_u32(dev, "realtek,dc_offset_r_manual_mic",
3428 		&rt5663->pdata.dc_offset_r_manual_mic);
3429 	device_property_read_u32(dev, "realtek,impedance_sensing_num",
3430 		&rt5663->pdata.impedance_sensing_num);
3431 
3432 	if (rt5663->pdata.impedance_sensing_num) {
3433 		table_size = sizeof(struct impedance_mapping_table) *
3434 			rt5663->pdata.impedance_sensing_num;
3435 		rt5663->imp_table = devm_kzalloc(dev, table_size, GFP_KERNEL);
3436 		device_property_read_u32_array(dev,
3437 			"realtek,impedance_sensing_table",
3438 			(u32 *)rt5663->imp_table, table_size);
3439 	}
3440 
3441 	return 0;
3442 }
3443 
3444 static int rt5663_i2c_probe(struct i2c_client *i2c,
3445 		    const struct i2c_device_id *id)
3446 {
3447 	struct rt5663_platform_data *pdata = dev_get_platdata(&i2c->dev);
3448 	struct rt5663_priv *rt5663;
3449 	int ret;
3450 	unsigned int val;
3451 	struct regmap *regmap;
3452 
3453 	rt5663 = devm_kzalloc(&i2c->dev, sizeof(struct rt5663_priv),
3454 		GFP_KERNEL);
3455 
3456 	if (rt5663 == NULL)
3457 		return -ENOMEM;
3458 
3459 	i2c_set_clientdata(i2c, rt5663);
3460 
3461 	if (pdata)
3462 		rt5663->pdata = *pdata;
3463 	else
3464 		rt5663_parse_dp(rt5663, &i2c->dev);
3465 
3466 	regmap = devm_regmap_init_i2c(i2c, &temp_regmap);
3467 	if (IS_ERR(regmap)) {
3468 		ret = PTR_ERR(regmap);
3469 		dev_err(&i2c->dev, "Failed to allocate temp register map: %d\n",
3470 			ret);
3471 		return ret;
3472 	}
3473 
3474 	ret = regmap_read(regmap, RT5663_VENDOR_ID_2, &val);
3475 	if (ret || (val != RT5663_DEVICE_ID_2 && val != RT5663_DEVICE_ID_1)) {
3476 		dev_err(&i2c->dev,
3477 			"Device with ID register %#x is not rt5663, retry one time.\n",
3478 			val);
3479 		msleep(100);
3480 		regmap_read(regmap, RT5663_VENDOR_ID_2, &val);
3481 	}
3482 
3483 	switch (val) {
3484 	case RT5663_DEVICE_ID_2:
3485 		rt5663->regmap = devm_regmap_init_i2c(i2c, &rt5663_v2_regmap);
3486 		rt5663->codec_ver = CODEC_VER_1;
3487 		break;
3488 	case RT5663_DEVICE_ID_1:
3489 		rt5663->regmap = devm_regmap_init_i2c(i2c, &rt5663_regmap);
3490 		rt5663->codec_ver = CODEC_VER_0;
3491 		break;
3492 	default:
3493 		dev_err(&i2c->dev,
3494 			"Device with ID register %#x is not rt5663\n",
3495 			val);
3496 		return -ENODEV;
3497 	}
3498 
3499 	if (IS_ERR(rt5663->regmap)) {
3500 		ret = PTR_ERR(rt5663->regmap);
3501 		dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
3502 			ret);
3503 		return ret;
3504 	}
3505 
3506 	/* reset and calibrate */
3507 	regmap_write(rt5663->regmap, RT5663_RESET, 0);
3508 	regcache_cache_bypass(rt5663->regmap, true);
3509 	switch (rt5663->codec_ver) {
3510 	case CODEC_VER_1:
3511 		rt5663_v2_calibrate(rt5663);
3512 		break;
3513 	case CODEC_VER_0:
3514 		rt5663_calibrate(rt5663);
3515 		break;
3516 	default:
3517 		dev_err(&i2c->dev, "%s:Unknown codec type\n", __func__);
3518 	}
3519 	regcache_cache_bypass(rt5663->regmap, false);
3520 	regmap_write(rt5663->regmap, RT5663_RESET, 0);
3521 	dev_dbg(&i2c->dev, "calibrate done\n");
3522 
3523 	switch (rt5663->codec_ver) {
3524 	case CODEC_VER_1:
3525 		break;
3526 	case CODEC_VER_0:
3527 		ret = regmap_register_patch(rt5663->regmap, rt5663_patch_list,
3528 					    ARRAY_SIZE(rt5663_patch_list));
3529 		if (ret != 0)
3530 			dev_warn(&i2c->dev,
3531 				"Failed to apply regmap patch: %d\n", ret);
3532 		break;
3533 	default:
3534 		dev_err(&i2c->dev, "%s:Unknown codec type\n", __func__);
3535 	}
3536 
3537 	/* GPIO1 as IRQ */
3538 	regmap_update_bits(rt5663->regmap, RT5663_GPIO_1, RT5663_GP1_PIN_MASK,
3539 		RT5663_GP1_PIN_IRQ);
3540 	/* 4btn inline command debounce */
3541 	regmap_update_bits(rt5663->regmap, RT5663_IL_CMD_5,
3542 		RT5663_4BTN_CLK_DEB_MASK, RT5663_4BTN_CLK_DEB_65MS);
3543 
3544 	switch (rt5663->codec_ver) {
3545 	case CODEC_VER_1:
3546 		regmap_write(rt5663->regmap, RT5663_BIAS_CUR_8, 0xa402);
3547 		/* JD1 */
3548 		regmap_update_bits(rt5663->regmap, RT5663_AUTO_1MRC_CLK,
3549 			RT5663_IRQ_POW_SAV_MASK | RT5663_IRQ_POW_SAV_JD1_MASK,
3550 			RT5663_IRQ_POW_SAV_EN | RT5663_IRQ_POW_SAV_JD1_EN);
3551 		regmap_update_bits(rt5663->regmap, RT5663_PWR_ANLG_2,
3552 			RT5663_PWR_JD1_MASK, RT5663_PWR_JD1);
3553 		regmap_update_bits(rt5663->regmap, RT5663_IRQ_1,
3554 			RT5663_EN_CB_JD_MASK, RT5663_EN_CB_JD_EN);
3555 
3556 		regmap_update_bits(rt5663->regmap, RT5663_HP_LOGIC_2,
3557 			RT5663_HP_SIG_SRC1_MASK, RT5663_HP_SIG_SRC1_REG);
3558 		regmap_update_bits(rt5663->regmap, RT5663_RECMIX,
3559 			RT5663_VREF_BIAS_MASK | RT5663_CBJ_DET_MASK |
3560 			RT5663_DET_TYPE_MASK, RT5663_VREF_BIAS_REG |
3561 			RT5663_CBJ_DET_EN | RT5663_DET_TYPE_QFN);
3562 		/* Set GPIO4 and GPIO8 as input for combo jack */
3563 		regmap_update_bits(rt5663->regmap, RT5663_GPIO_2,
3564 			RT5663_GP4_PIN_CONF_MASK, RT5663_GP4_PIN_CONF_INPUT);
3565 		regmap_update_bits(rt5663->regmap, RT5663_GPIO_3,
3566 			RT5663_GP8_PIN_CONF_MASK, RT5663_GP8_PIN_CONF_INPUT);
3567 		regmap_update_bits(rt5663->regmap, RT5663_PWR_ANLG_1,
3568 			RT5663_LDO1_DVO_MASK | RT5663_AMP_HP_MASK,
3569 			RT5663_LDO1_DVO_0_9V | RT5663_AMP_HP_3X);
3570 			break;
3571 	case CODEC_VER_0:
3572 		regmap_update_bits(rt5663->regmap, RT5663_DIG_MISC,
3573 			RT5663_DIG_GATE_CTRL_MASK, RT5663_DIG_GATE_CTRL_EN);
3574 		regmap_update_bits(rt5663->regmap, RT5663_AUTO_1MRC_CLK,
3575 			RT5663_IRQ_MANUAL_MASK, RT5663_IRQ_MANUAL_EN);
3576 		regmap_update_bits(rt5663->regmap, RT5663_IRQ_1,
3577 			RT5663_EN_IRQ_JD1_MASK, RT5663_EN_IRQ_JD1_EN);
3578 		regmap_update_bits(rt5663->regmap, RT5663_GPIO_1,
3579 			RT5663_GPIO1_TYPE_MASK, RT5663_GPIO1_TYPE_EN);
3580 		regmap_write(rt5663->regmap, RT5663_VREF_RECMIX, 0x0032);
3581 		regmap_write(rt5663->regmap, RT5663_PWR_ANLG_1, 0xa2be);
3582 		msleep(20);
3583 		regmap_write(rt5663->regmap, RT5663_PWR_ANLG_1, 0xf2be);
3584 		regmap_update_bits(rt5663->regmap, RT5663_GPIO_2,
3585 			RT5663_GP1_PIN_CONF_MASK | RT5663_SEL_GPIO1_MASK,
3586 			RT5663_GP1_PIN_CONF_OUTPUT | RT5663_SEL_GPIO1_EN);
3587 		/* DACREF LDO control */
3588 		regmap_update_bits(rt5663->regmap, RT5663_DACREF_LDO, 0x3e0e,
3589 			0x3a0a);
3590 		regmap_update_bits(rt5663->regmap, RT5663_RECMIX,
3591 			RT5663_RECMIX1_BST1_MASK, RT5663_RECMIX1_BST1_ON);
3592 		regmap_update_bits(rt5663->regmap, RT5663_TDM_2,
3593 			RT5663_DATA_SWAP_ADCDAT1_MASK,
3594 			RT5663_DATA_SWAP_ADCDAT1_LL);
3595 			break;
3596 	default:
3597 		dev_err(&i2c->dev, "%s:Unknown codec type\n", __func__);
3598 	}
3599 
3600 	INIT_DELAYED_WORK(&rt5663->jack_detect_work, rt5663_jack_detect_work);
3601 	INIT_DELAYED_WORK(&rt5663->jd_unplug_work, rt5663_jd_unplug_work);
3602 
3603 	if (i2c->irq) {
3604 		ret = request_irq(i2c->irq, rt5663_irq,
3605 			IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING
3606 			| IRQF_ONESHOT, "rt5663", rt5663);
3607 		if (ret)
3608 			dev_err(&i2c->dev, "%s Failed to reguest IRQ: %d\n",
3609 				__func__, ret);
3610 	}
3611 
3612 	ret = devm_snd_soc_register_component(&i2c->dev,
3613 			&soc_component_dev_rt5663,
3614 			rt5663_dai, ARRAY_SIZE(rt5663_dai));
3615 
3616 	if (ret) {
3617 		if (i2c->irq)
3618 			free_irq(i2c->irq, rt5663);
3619 	}
3620 
3621 	return ret;
3622 }
3623 
3624 static int rt5663_i2c_remove(struct i2c_client *i2c)
3625 {
3626 	struct rt5663_priv *rt5663 = i2c_get_clientdata(i2c);
3627 
3628 	if (i2c->irq)
3629 		free_irq(i2c->irq, rt5663);
3630 
3631 	return 0;
3632 }
3633 
3634 static void rt5663_i2c_shutdown(struct i2c_client *client)
3635 {
3636 	struct rt5663_priv *rt5663 = i2c_get_clientdata(client);
3637 
3638 	regmap_write(rt5663->regmap, RT5663_RESET, 0);
3639 }
3640 
3641 static struct i2c_driver rt5663_i2c_driver = {
3642 	.driver = {
3643 		.name = "rt5663",
3644 		.acpi_match_table = ACPI_PTR(rt5663_acpi_match),
3645 		.of_match_table = of_match_ptr(rt5663_of_match),
3646 	},
3647 	.probe = rt5663_i2c_probe,
3648 	.remove = rt5663_i2c_remove,
3649 	.shutdown = rt5663_i2c_shutdown,
3650 	.id_table = rt5663_i2c_id,
3651 };
3652 module_i2c_driver(rt5663_i2c_driver);
3653 
3654 MODULE_DESCRIPTION("ASoC RT5663 driver");
3655 MODULE_AUTHOR("Jack Yu <jack.yu@realtek.com>");
3656 MODULE_LICENSE("GPL v2");
3657