1 /* 2 * rt5663.c -- RT5663 ALSA SoC audio codec driver 3 * 4 * Copyright 2016 Realtek Semiconductor Corp. 5 * Author: Jack Yu <jack.yu@realtek.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11 #include <linux/module.h> 12 #include <linux/moduleparam.h> 13 #include <linux/init.h> 14 #include <linux/delay.h> 15 #include <linux/pm.h> 16 #include <linux/i2c.h> 17 #include <linux/platform_device.h> 18 #include <linux/spi/spi.h> 19 #include <linux/acpi.h> 20 #include <linux/workqueue.h> 21 #include <sound/core.h> 22 #include <sound/pcm.h> 23 #include <sound/pcm_params.h> 24 #include <sound/jack.h> 25 #include <sound/soc.h> 26 #include <sound/soc-dapm.h> 27 #include <sound/initval.h> 28 #include <sound/tlv.h> 29 30 #include "rt5663.h" 31 #include "rl6231.h" 32 33 #define RT5663_DEVICE_ID_2 0x6451 34 #define RT5663_DEVICE_ID_1 0x6406 35 36 enum { 37 CODEC_VER_1, 38 CODEC_VER_0, 39 }; 40 41 struct impedance_mapping_table { 42 unsigned int imp_min; 43 unsigned int imp_max; 44 unsigned int vol; 45 unsigned int dc_offset_l_manual; 46 unsigned int dc_offset_r_manual; 47 unsigned int dc_offset_l_manual_mic; 48 unsigned int dc_offset_r_manual_mic; 49 }; 50 51 struct rt5663_priv { 52 struct snd_soc_component *component; 53 struct rt5663_platform_data pdata; 54 struct regmap *regmap; 55 struct delayed_work jack_detect_work, jd_unplug_work; 56 struct snd_soc_jack *hs_jack; 57 struct timer_list btn_check_timer; 58 struct impedance_mapping_table *imp_table; 59 60 int codec_ver; 61 int sysclk; 62 int sysclk_src; 63 int lrck; 64 65 int pll_src; 66 int pll_in; 67 int pll_out; 68 69 int jack_type; 70 }; 71 72 static const struct reg_sequence rt5663_patch_list[] = { 73 { 0x002a, 0x8020 }, 74 { 0x0086, 0x0028 }, 75 { 0x0100, 0xa020 }, 76 { 0x0117, 0x0f28 }, 77 { 0x02fb, 0x8089 }, 78 }; 79 80 static const struct reg_default rt5663_v2_reg[] = { 81 { 0x0000, 0x0000 }, 82 { 0x0001, 0xc8c8 }, 83 { 0x0002, 0x8080 }, 84 { 0x0003, 0x8000 }, 85 { 0x0004, 0xc80a }, 86 { 0x0005, 0x0000 }, 87 { 0x0006, 0x0000 }, 88 { 0x0007, 0x0000 }, 89 { 0x000a, 0x0000 }, 90 { 0x000b, 0x0000 }, 91 { 0x000c, 0x0000 }, 92 { 0x000d, 0x0000 }, 93 { 0x000f, 0x0808 }, 94 { 0x0010, 0x4000 }, 95 { 0x0011, 0x0000 }, 96 { 0x0012, 0x1404 }, 97 { 0x0013, 0x1000 }, 98 { 0x0014, 0xa00a }, 99 { 0x0015, 0x0404 }, 100 { 0x0016, 0x0404 }, 101 { 0x0017, 0x0011 }, 102 { 0x0018, 0xafaf }, 103 { 0x0019, 0xafaf }, 104 { 0x001a, 0xafaf }, 105 { 0x001b, 0x0011 }, 106 { 0x001c, 0x2f2f }, 107 { 0x001d, 0x2f2f }, 108 { 0x001e, 0x2f2f }, 109 { 0x001f, 0x0000 }, 110 { 0x0020, 0x0000 }, 111 { 0x0021, 0x0000 }, 112 { 0x0022, 0x5757 }, 113 { 0x0023, 0x0039 }, 114 { 0x0024, 0x000b }, 115 { 0x0026, 0xc0c0 }, 116 { 0x0027, 0xc0c0 }, 117 { 0x0028, 0xc0c0 }, 118 { 0x0029, 0x8080 }, 119 { 0x002a, 0xaaaa }, 120 { 0x002b, 0xaaaa }, 121 { 0x002c, 0xaba8 }, 122 { 0x002d, 0x0000 }, 123 { 0x002e, 0x0000 }, 124 { 0x002f, 0x0000 }, 125 { 0x0030, 0x0000 }, 126 { 0x0031, 0x5000 }, 127 { 0x0032, 0x0000 }, 128 { 0x0033, 0x0000 }, 129 { 0x0034, 0x0000 }, 130 { 0x0035, 0x0000 }, 131 { 0x003a, 0x0000 }, 132 { 0x003b, 0x0000 }, 133 { 0x003c, 0x00ff }, 134 { 0x003d, 0x0000 }, 135 { 0x003e, 0x00ff }, 136 { 0x003f, 0x0000 }, 137 { 0x0040, 0x0000 }, 138 { 0x0041, 0x00ff }, 139 { 0x0042, 0x0000 }, 140 { 0x0043, 0x00ff }, 141 { 0x0044, 0x0c0c }, 142 { 0x0049, 0xc00b }, 143 { 0x004a, 0x0000 }, 144 { 0x004b, 0x031f }, 145 { 0x004d, 0x0000 }, 146 { 0x004e, 0x001f }, 147 { 0x004f, 0x0000 }, 148 { 0x0050, 0x001f }, 149 { 0x0052, 0xf000 }, 150 { 0x0061, 0x0000 }, 151 { 0x0062, 0x0000 }, 152 { 0x0063, 0x003e }, 153 { 0x0064, 0x0000 }, 154 { 0x0065, 0x0000 }, 155 { 0x0066, 0x003f }, 156 { 0x0067, 0x0000 }, 157 { 0x006b, 0x0000 }, 158 { 0x006d, 0xff00 }, 159 { 0x006e, 0x2808 }, 160 { 0x006f, 0x000a }, 161 { 0x0070, 0x8000 }, 162 { 0x0071, 0x8000 }, 163 { 0x0072, 0x8000 }, 164 { 0x0073, 0x7000 }, 165 { 0x0074, 0x7770 }, 166 { 0x0075, 0x0002 }, 167 { 0x0076, 0x0001 }, 168 { 0x0078, 0x00f0 }, 169 { 0x0079, 0x0000 }, 170 { 0x007a, 0x0000 }, 171 { 0x007b, 0x0000 }, 172 { 0x007c, 0x0000 }, 173 { 0x007d, 0x0123 }, 174 { 0x007e, 0x4500 }, 175 { 0x007f, 0x8003 }, 176 { 0x0080, 0x0000 }, 177 { 0x0081, 0x0000 }, 178 { 0x0082, 0x0000 }, 179 { 0x0083, 0x0000 }, 180 { 0x0084, 0x0000 }, 181 { 0x0085, 0x0000 }, 182 { 0x0086, 0x0008 }, 183 { 0x0087, 0x0000 }, 184 { 0x0088, 0x0000 }, 185 { 0x0089, 0x0000 }, 186 { 0x008a, 0x0000 }, 187 { 0x008b, 0x0000 }, 188 { 0x008c, 0x0003 }, 189 { 0x008e, 0x0060 }, 190 { 0x008f, 0x1000 }, 191 { 0x0091, 0x0c26 }, 192 { 0x0092, 0x0073 }, 193 { 0x0093, 0x0000 }, 194 { 0x0094, 0x0080 }, 195 { 0x0098, 0x0000 }, 196 { 0x0099, 0x0000 }, 197 { 0x009a, 0x0007 }, 198 { 0x009f, 0x0000 }, 199 { 0x00a0, 0x0000 }, 200 { 0x00a1, 0x0002 }, 201 { 0x00a2, 0x0001 }, 202 { 0x00a3, 0x0002 }, 203 { 0x00a4, 0x0001 }, 204 { 0x00ae, 0x2040 }, 205 { 0x00af, 0x0000 }, 206 { 0x00b6, 0x0000 }, 207 { 0x00b7, 0x0000 }, 208 { 0x00b8, 0x0000 }, 209 { 0x00b9, 0x0000 }, 210 { 0x00ba, 0x0002 }, 211 { 0x00bb, 0x0000 }, 212 { 0x00be, 0x0000 }, 213 { 0x00c0, 0x0000 }, 214 { 0x00c1, 0x0aaa }, 215 { 0x00c2, 0xaa80 }, 216 { 0x00c3, 0x0003 }, 217 { 0x00c4, 0x0000 }, 218 { 0x00d0, 0x0000 }, 219 { 0x00d1, 0x2244 }, 220 { 0x00d2, 0x0000 }, 221 { 0x00d3, 0x3300 }, 222 { 0x00d4, 0x2200 }, 223 { 0x00d9, 0x0809 }, 224 { 0x00da, 0x0000 }, 225 { 0x00db, 0x0008 }, 226 { 0x00dc, 0x00c0 }, 227 { 0x00dd, 0x6724 }, 228 { 0x00de, 0x3131 }, 229 { 0x00df, 0x0008 }, 230 { 0x00e0, 0x4000 }, 231 { 0x00e1, 0x3131 }, 232 { 0x00e2, 0x600c }, 233 { 0x00ea, 0xb320 }, 234 { 0x00eb, 0x0000 }, 235 { 0x00ec, 0xb300 }, 236 { 0x00ed, 0x0000 }, 237 { 0x00ee, 0xb320 }, 238 { 0x00ef, 0x0000 }, 239 { 0x00f0, 0x0201 }, 240 { 0x00f1, 0x0ddd }, 241 { 0x00f2, 0x0ddd }, 242 { 0x00f6, 0x0000 }, 243 { 0x00f7, 0x0000 }, 244 { 0x00f8, 0x0000 }, 245 { 0x00fa, 0x0000 }, 246 { 0x00fb, 0x0000 }, 247 { 0x00fc, 0x0000 }, 248 { 0x00fd, 0x0000 }, 249 { 0x00fe, 0x10ec }, 250 { 0x00ff, 0x6451 }, 251 { 0x0100, 0xaaaa }, 252 { 0x0101, 0x000a }, 253 { 0x010a, 0xaaaa }, 254 { 0x010b, 0xa0a0 }, 255 { 0x010c, 0xaeae }, 256 { 0x010d, 0xaaaa }, 257 { 0x010e, 0xaaaa }, 258 { 0x010f, 0xaaaa }, 259 { 0x0110, 0xe002 }, 260 { 0x0111, 0xa602 }, 261 { 0x0112, 0xaaaa }, 262 { 0x0113, 0x2000 }, 263 { 0x0117, 0x0f00 }, 264 { 0x0125, 0x0420 }, 265 { 0x0132, 0x0000 }, 266 { 0x0133, 0x0000 }, 267 { 0x0136, 0x5555 }, 268 { 0x0137, 0x5540 }, 269 { 0x0138, 0x3700 }, 270 { 0x0139, 0x79a1 }, 271 { 0x013a, 0x2020 }, 272 { 0x013b, 0x2020 }, 273 { 0x013c, 0x2005 }, 274 { 0x013f, 0x0000 }, 275 { 0x0145, 0x0002 }, 276 { 0x0146, 0x0000 }, 277 { 0x0147, 0x0000 }, 278 { 0x0148, 0x0000 }, 279 { 0x0160, 0x4ec0 }, 280 { 0x0161, 0x0080 }, 281 { 0x0162, 0x0200 }, 282 { 0x0163, 0x0800 }, 283 { 0x0164, 0x0000 }, 284 { 0x0165, 0x0000 }, 285 { 0x0166, 0x0000 }, 286 { 0x0167, 0x000f }, 287 { 0x0168, 0x000f }, 288 { 0x0170, 0x4e80 }, 289 { 0x0171, 0x0080 }, 290 { 0x0172, 0x0200 }, 291 { 0x0173, 0x0800 }, 292 { 0x0174, 0x00ff }, 293 { 0x0175, 0x0000 }, 294 { 0x0190, 0x4131 }, 295 { 0x0191, 0x4131 }, 296 { 0x0192, 0x4131 }, 297 { 0x0193, 0x4131 }, 298 { 0x0194, 0x0000 }, 299 { 0x0195, 0x0000 }, 300 { 0x0196, 0x0000 }, 301 { 0x0197, 0x0000 }, 302 { 0x0198, 0x0000 }, 303 { 0x0199, 0x0000 }, 304 { 0x01a0, 0x1e64 }, 305 { 0x01a1, 0x06a3 }, 306 { 0x01a2, 0x0000 }, 307 { 0x01a3, 0x0000 }, 308 { 0x01a4, 0x0000 }, 309 { 0x01a5, 0x0000 }, 310 { 0x01a6, 0x0000 }, 311 { 0x01a7, 0x0000 }, 312 { 0x01a8, 0x0000 }, 313 { 0x01a9, 0x0000 }, 314 { 0x01aa, 0x0000 }, 315 { 0x01ab, 0x0000 }, 316 { 0x01b5, 0x0000 }, 317 { 0x01b6, 0x01c3 }, 318 { 0x01b7, 0x02a0 }, 319 { 0x01b8, 0x03e9 }, 320 { 0x01b9, 0x1389 }, 321 { 0x01ba, 0xc351 }, 322 { 0x01bb, 0x0009 }, 323 { 0x01bc, 0x0018 }, 324 { 0x01bd, 0x002a }, 325 { 0x01be, 0x004c }, 326 { 0x01bf, 0x0097 }, 327 { 0x01c0, 0x433d }, 328 { 0x01c1, 0x0000 }, 329 { 0x01c2, 0x0000 }, 330 { 0x01c3, 0x0000 }, 331 { 0x01c4, 0x0000 }, 332 { 0x01c5, 0x0000 }, 333 { 0x01c6, 0x0000 }, 334 { 0x01c7, 0x0000 }, 335 { 0x01c8, 0x40af }, 336 { 0x01c9, 0x0702 }, 337 { 0x01ca, 0x0000 }, 338 { 0x01cb, 0x0000 }, 339 { 0x01cc, 0x5757 }, 340 { 0x01cd, 0x5757 }, 341 { 0x01ce, 0x5757 }, 342 { 0x01cf, 0x5757 }, 343 { 0x01d0, 0x5757 }, 344 { 0x01d1, 0x5757 }, 345 { 0x01d2, 0x5757 }, 346 { 0x01d3, 0x5757 }, 347 { 0x01d4, 0x5757 }, 348 { 0x01d5, 0x5757 }, 349 { 0x01d6, 0x003c }, 350 { 0x01da, 0x0000 }, 351 { 0x01db, 0x0000 }, 352 { 0x01dc, 0x0000 }, 353 { 0x01de, 0x7c00 }, 354 { 0x01df, 0x0320 }, 355 { 0x01e0, 0x06a1 }, 356 { 0x01e1, 0x0000 }, 357 { 0x01e2, 0x0000 }, 358 { 0x01e3, 0x0000 }, 359 { 0x01e4, 0x0000 }, 360 { 0x01e5, 0x0000 }, 361 { 0x01e6, 0x0001 }, 362 { 0x01e7, 0x0000 }, 363 { 0x01e8, 0x0000 }, 364 { 0x01ea, 0x0000 }, 365 { 0x01eb, 0x0000 }, 366 { 0x01ec, 0x0000 }, 367 { 0x01ed, 0x0000 }, 368 { 0x01ee, 0x0000 }, 369 { 0x01ef, 0x0000 }, 370 { 0x01f0, 0x0000 }, 371 { 0x01f1, 0x0000 }, 372 { 0x01f2, 0x0000 }, 373 { 0x01f3, 0x0000 }, 374 { 0x01f4, 0x0000 }, 375 { 0x0200, 0x0000 }, 376 { 0x0201, 0x0000 }, 377 { 0x0202, 0x0000 }, 378 { 0x0203, 0x0000 }, 379 { 0x0204, 0x0000 }, 380 { 0x0205, 0x0000 }, 381 { 0x0206, 0x0000 }, 382 { 0x0207, 0x0000 }, 383 { 0x0208, 0x0000 }, 384 { 0x0210, 0x60b1 }, 385 { 0x0211, 0xa000 }, 386 { 0x0212, 0x024c }, 387 { 0x0213, 0xf7ff }, 388 { 0x0214, 0x024c }, 389 { 0x0215, 0x0102 }, 390 { 0x0216, 0x00a3 }, 391 { 0x0217, 0x0048 }, 392 { 0x0218, 0x92c0 }, 393 { 0x0219, 0x0000 }, 394 { 0x021a, 0x00c8 }, 395 { 0x021b, 0x0020 }, 396 { 0x02fa, 0x0000 }, 397 { 0x02fb, 0x0000 }, 398 { 0x02fc, 0x0000 }, 399 { 0x02ff, 0x0110 }, 400 { 0x0300, 0x001f }, 401 { 0x0301, 0x032c }, 402 { 0x0302, 0x5f21 }, 403 { 0x0303, 0x4000 }, 404 { 0x0304, 0x4000 }, 405 { 0x0305, 0x06d5 }, 406 { 0x0306, 0x8000 }, 407 { 0x0307, 0x0700 }, 408 { 0x0310, 0x4560 }, 409 { 0x0311, 0xa4a8 }, 410 { 0x0312, 0x7418 }, 411 { 0x0313, 0x0000 }, 412 { 0x0314, 0x0006 }, 413 { 0x0315, 0xffff }, 414 { 0x0316, 0xc400 }, 415 { 0x0317, 0x0000 }, 416 { 0x0330, 0x00a6 }, 417 { 0x0331, 0x04c3 }, 418 { 0x0332, 0x27c8 }, 419 { 0x0333, 0xbf50 }, 420 { 0x0334, 0x0045 }, 421 { 0x0335, 0x0007 }, 422 { 0x0336, 0x7418 }, 423 { 0x0337, 0x0501 }, 424 { 0x0338, 0x0000 }, 425 { 0x0339, 0x0010 }, 426 { 0x033a, 0x1010 }, 427 { 0x03c0, 0x7e00 }, 428 { 0x03c1, 0x8000 }, 429 { 0x03c2, 0x8000 }, 430 { 0x03c3, 0x8000 }, 431 { 0x03c4, 0x8000 }, 432 { 0x03c5, 0x8000 }, 433 { 0x03c6, 0x8000 }, 434 { 0x03c7, 0x8000 }, 435 { 0x03c8, 0x8000 }, 436 { 0x03c9, 0x8000 }, 437 { 0x03ca, 0x8000 }, 438 { 0x03cb, 0x8000 }, 439 { 0x03cc, 0x8000 }, 440 { 0x03d0, 0x0000 }, 441 { 0x03d1, 0x0000 }, 442 { 0x03d2, 0x0000 }, 443 { 0x03d3, 0x0000 }, 444 { 0x03d4, 0x2000 }, 445 { 0x03d5, 0x2000 }, 446 { 0x03d6, 0x0000 }, 447 { 0x03d7, 0x0000 }, 448 { 0x03d8, 0x2000 }, 449 { 0x03d9, 0x2000 }, 450 { 0x03da, 0x2000 }, 451 { 0x03db, 0x2000 }, 452 { 0x03dc, 0x0000 }, 453 { 0x03dd, 0x0000 }, 454 { 0x03de, 0x0000 }, 455 { 0x03df, 0x2000 }, 456 { 0x03e0, 0x0000 }, 457 { 0x03e1, 0x0000 }, 458 { 0x03e2, 0x0000 }, 459 { 0x03e3, 0x0000 }, 460 { 0x03e4, 0x0000 }, 461 { 0x03e5, 0x0000 }, 462 { 0x03e6, 0x0000 }, 463 { 0x03e7, 0x0000 }, 464 { 0x03e8, 0x0000 }, 465 { 0x03e9, 0x0000 }, 466 { 0x03ea, 0x0000 }, 467 { 0x03eb, 0x0000 }, 468 { 0x03ec, 0x0000 }, 469 { 0x03ed, 0x0000 }, 470 { 0x03ee, 0x0000 }, 471 { 0x03ef, 0x0000 }, 472 { 0x03f0, 0x0800 }, 473 { 0x03f1, 0x0800 }, 474 { 0x03f2, 0x0800 }, 475 { 0x03f3, 0x0800 }, 476 { 0x03fe, 0x0000 }, 477 { 0x03ff, 0x0000 }, 478 { 0x07f0, 0x0000 }, 479 { 0x07fa, 0x0000 }, 480 }; 481 482 static const struct reg_default rt5663_reg[] = { 483 { 0x0000, 0x0000 }, 484 { 0x0002, 0x0008 }, 485 { 0x0005, 0x1000 }, 486 { 0x0006, 0x1000 }, 487 { 0x000a, 0x0000 }, 488 { 0x0010, 0x000f }, 489 { 0x0015, 0x42f1 }, 490 { 0x0016, 0x0000 }, 491 { 0x0018, 0x000b }, 492 { 0x0019, 0xafaf }, 493 { 0x001c, 0x2f2f }, 494 { 0x001f, 0x0000 }, 495 { 0x0022, 0x5757 }, 496 { 0x0023, 0x0039 }, 497 { 0x0026, 0xc0c0 }, 498 { 0x0029, 0x8080 }, 499 { 0x002a, 0x8020 }, 500 { 0x002c, 0x000c }, 501 { 0x002d, 0x0000 }, 502 { 0x0040, 0x0808 }, 503 { 0x0061, 0x0000 }, 504 { 0x0062, 0x0000 }, 505 { 0x0063, 0x003e }, 506 { 0x0064, 0x0000 }, 507 { 0x0065, 0x0000 }, 508 { 0x0066, 0x0000 }, 509 { 0x006b, 0x0000 }, 510 { 0x006e, 0x0000 }, 511 { 0x006f, 0x0000 }, 512 { 0x0070, 0x8020 }, 513 { 0x0073, 0x1000 }, 514 { 0x0074, 0xe400 }, 515 { 0x0075, 0x0002 }, 516 { 0x0076, 0x0001 }, 517 { 0x0077, 0x00f0 }, 518 { 0x0078, 0x0000 }, 519 { 0x0079, 0x0000 }, 520 { 0x007a, 0x0123 }, 521 { 0x007b, 0x8003 }, 522 { 0x0080, 0x0000 }, 523 { 0x0081, 0x0000 }, 524 { 0x0082, 0x0000 }, 525 { 0x0083, 0x0000 }, 526 { 0x0084, 0x0000 }, 527 { 0x0086, 0x0028 }, 528 { 0x0087, 0x0000 }, 529 { 0x008a, 0x0000 }, 530 { 0x008b, 0x0000 }, 531 { 0x008c, 0x0003 }, 532 { 0x008e, 0x0008 }, 533 { 0x008f, 0x1000 }, 534 { 0x0090, 0x0646 }, 535 { 0x0091, 0x0e3e }, 536 { 0x0092, 0x1071 }, 537 { 0x0093, 0x0000 }, 538 { 0x0094, 0x0080 }, 539 { 0x0097, 0x0000 }, 540 { 0x0098, 0x0000 }, 541 { 0x009a, 0x0000 }, 542 { 0x009f, 0x0000 }, 543 { 0x00ae, 0x6000 }, 544 { 0x00af, 0x0000 }, 545 { 0x00b6, 0x0000 }, 546 { 0x00b7, 0x0000 }, 547 { 0x00b8, 0x0000 }, 548 { 0x00ba, 0x0000 }, 549 { 0x00bb, 0x0000 }, 550 { 0x00be, 0x0000 }, 551 { 0x00bf, 0x0000 }, 552 { 0x00c0, 0x0000 }, 553 { 0x00c1, 0x0000 }, 554 { 0x00c5, 0x0000 }, 555 { 0x00cb, 0xa02f }, 556 { 0x00cc, 0x0000 }, 557 { 0x00cd, 0x0e02 }, 558 { 0x00d9, 0x08f9 }, 559 { 0x00db, 0x0008 }, 560 { 0x00dc, 0x00c0 }, 561 { 0x00dd, 0x6729 }, 562 { 0x00de, 0x3131 }, 563 { 0x00df, 0x0008 }, 564 { 0x00e0, 0x4000 }, 565 { 0x00e1, 0x3131 }, 566 { 0x00e2, 0x0043 }, 567 { 0x00e4, 0x400b }, 568 { 0x00e5, 0x8031 }, 569 { 0x00e6, 0x3080 }, 570 { 0x00e7, 0x4100 }, 571 { 0x00e8, 0x1400 }, 572 { 0x00e9, 0xe00a }, 573 { 0x00ea, 0x0404 }, 574 { 0x00eb, 0x0404 }, 575 { 0x00ec, 0xb320 }, 576 { 0x00ed, 0x0000 }, 577 { 0x00f4, 0x0000 }, 578 { 0x00f6, 0x0000 }, 579 { 0x00f8, 0x0000 }, 580 { 0x00fa, 0x8000 }, 581 { 0x00fd, 0x0001 }, 582 { 0x00fe, 0x10ec }, 583 { 0x00ff, 0x6406 }, 584 { 0x0100, 0xa020 }, 585 { 0x0108, 0x4444 }, 586 { 0x0109, 0x4444 }, 587 { 0x010a, 0xaaaa }, 588 { 0x010b, 0x00a0 }, 589 { 0x010c, 0x8aaa }, 590 { 0x010d, 0xaaaa }, 591 { 0x010e, 0x2aaa }, 592 { 0x010f, 0x002a }, 593 { 0x0110, 0xa0a4 }, 594 { 0x0111, 0x4602 }, 595 { 0x0112, 0x0101 }, 596 { 0x0113, 0x2000 }, 597 { 0x0114, 0x0000 }, 598 { 0x0116, 0x0000 }, 599 { 0x0117, 0x0f28 }, 600 { 0x0118, 0x0006 }, 601 { 0x0125, 0x2424 }, 602 { 0x0126, 0x5550 }, 603 { 0x0127, 0x0400 }, 604 { 0x0128, 0x7711 }, 605 { 0x0132, 0x0004 }, 606 { 0x0137, 0x5441 }, 607 { 0x0139, 0x79a1 }, 608 { 0x013a, 0x30c0 }, 609 { 0x013b, 0x2000 }, 610 { 0x013c, 0x2005 }, 611 { 0x013d, 0x30c0 }, 612 { 0x013e, 0x0000 }, 613 { 0x0140, 0x3700 }, 614 { 0x0141, 0x1f00 }, 615 { 0x0144, 0x0000 }, 616 { 0x0145, 0x0002 }, 617 { 0x0146, 0x0000 }, 618 { 0x0160, 0x0e80 }, 619 { 0x0161, 0x0080 }, 620 { 0x0162, 0x0200 }, 621 { 0x0163, 0x0800 }, 622 { 0x0164, 0x0000 }, 623 { 0x0165, 0x0000 }, 624 { 0x0166, 0x0000 }, 625 { 0x0167, 0x1417 }, 626 { 0x0168, 0x0017 }, 627 { 0x0169, 0x0017 }, 628 { 0x0180, 0x2000 }, 629 { 0x0181, 0x0000 }, 630 { 0x0182, 0x0000 }, 631 { 0x0183, 0x2000 }, 632 { 0x0184, 0x0000 }, 633 { 0x0185, 0x0000 }, 634 { 0x01b0, 0x4b30 }, 635 { 0x01b1, 0x0000 }, 636 { 0x01b2, 0xd870 }, 637 { 0x01b3, 0x0000 }, 638 { 0x01b4, 0x0030 }, 639 { 0x01b5, 0x5757 }, 640 { 0x01b6, 0x5757 }, 641 { 0x01b7, 0x5757 }, 642 { 0x01b8, 0x5757 }, 643 { 0x01c0, 0x433d }, 644 { 0x01c1, 0x0540 }, 645 { 0x01c2, 0x0000 }, 646 { 0x01c3, 0x0000 }, 647 { 0x01c4, 0x0000 }, 648 { 0x01c5, 0x0009 }, 649 { 0x01c6, 0x0018 }, 650 { 0x01c7, 0x002a }, 651 { 0x01c8, 0x004c }, 652 { 0x01c9, 0x0097 }, 653 { 0x01ca, 0x01c3 }, 654 { 0x01cb, 0x03e9 }, 655 { 0x01cc, 0x1389 }, 656 { 0x01cd, 0xc351 }, 657 { 0x01ce, 0x0000 }, 658 { 0x01cf, 0x0000 }, 659 { 0x01d0, 0x0000 }, 660 { 0x01d1, 0x0000 }, 661 { 0x01d2, 0x0000 }, 662 { 0x01d3, 0x003c }, 663 { 0x01d4, 0x5757 }, 664 { 0x01d5, 0x5757 }, 665 { 0x01d6, 0x5757 }, 666 { 0x01d7, 0x5757 }, 667 { 0x01d8, 0x5757 }, 668 { 0x01d9, 0x5757 }, 669 { 0x01da, 0x0000 }, 670 { 0x01db, 0x0000 }, 671 { 0x01dd, 0x0009 }, 672 { 0x01de, 0x7f00 }, 673 { 0x01df, 0x00c8 }, 674 { 0x01e0, 0x0691 }, 675 { 0x01e1, 0x0000 }, 676 { 0x01e2, 0x0000 }, 677 { 0x01e3, 0x0000 }, 678 { 0x01e4, 0x0000 }, 679 { 0x01e5, 0x0040 }, 680 { 0x01e6, 0x0000 }, 681 { 0x01e7, 0x0000 }, 682 { 0x01e8, 0x0000 }, 683 { 0x01ea, 0x0000 }, 684 { 0x01eb, 0x0000 }, 685 { 0x01ec, 0x0000 }, 686 { 0x01ed, 0x0000 }, 687 { 0x01ee, 0x0000 }, 688 { 0x01ef, 0x0000 }, 689 { 0x01f0, 0x0000 }, 690 { 0x01f1, 0x0000 }, 691 { 0x01f2, 0x0000 }, 692 { 0x0200, 0x0000 }, 693 { 0x0201, 0x2244 }, 694 { 0x0202, 0xaaaa }, 695 { 0x0250, 0x8010 }, 696 { 0x0251, 0x0000 }, 697 { 0x0252, 0x028a }, 698 { 0x02fa, 0x0000 }, 699 { 0x02fb, 0x8089 }, 700 { 0x02fc, 0x0300 }, 701 { 0x0300, 0x0000 }, 702 { 0x03d0, 0x0000 }, 703 { 0x03d1, 0x0000 }, 704 { 0x03d2, 0x0000 }, 705 { 0x03d3, 0x0000 }, 706 { 0x03d4, 0x2000 }, 707 { 0x03d5, 0x2000 }, 708 { 0x03d6, 0x0000 }, 709 { 0x03d7, 0x0000 }, 710 { 0x03d8, 0x2000 }, 711 { 0x03d9, 0x2000 }, 712 { 0x03da, 0x2000 }, 713 { 0x03db, 0x2000 }, 714 { 0x03dc, 0x0000 }, 715 { 0x03dd, 0x0000 }, 716 { 0x03de, 0x0000 }, 717 { 0x03df, 0x2000 }, 718 { 0x03e0, 0x0000 }, 719 { 0x03e1, 0x0000 }, 720 { 0x03e2, 0x0000 }, 721 { 0x03e3, 0x0000 }, 722 { 0x03e4, 0x0000 }, 723 { 0x03e5, 0x0000 }, 724 { 0x03e6, 0x0000 }, 725 { 0x03e7, 0x0000 }, 726 { 0x03e8, 0x0000 }, 727 { 0x03e9, 0x0000 }, 728 { 0x03ea, 0x0000 }, 729 { 0x03eb, 0x0000 }, 730 { 0x03ec, 0x0000 }, 731 { 0x03ed, 0x0000 }, 732 { 0x03ee, 0x0000 }, 733 { 0x03ef, 0x0000 }, 734 { 0x03f0, 0x0800 }, 735 { 0x03f1, 0x0800 }, 736 { 0x03f2, 0x0800 }, 737 { 0x03f3, 0x0800 }, 738 }; 739 740 static bool rt5663_volatile_register(struct device *dev, unsigned int reg) 741 { 742 switch (reg) { 743 case RT5663_RESET: 744 case RT5663_SIL_DET_CTL: 745 case RT5663_HP_IMP_GAIN_2: 746 case RT5663_AD_DA_MIXER: 747 case RT5663_FRAC_DIV_2: 748 case RT5663_MICBIAS_1: 749 case RT5663_ASRC_11_2: 750 case RT5663_ADC_EQ_1: 751 case RT5663_INT_ST_1: 752 case RT5663_INT_ST_2: 753 case RT5663_GPIO_STA1: 754 case RT5663_SIN_GEN_1: 755 case RT5663_IL_CMD_1: 756 case RT5663_IL_CMD_5: 757 case RT5663_IL_CMD_PWRSAV1: 758 case RT5663_EM_JACK_TYPE_1: 759 case RT5663_EM_JACK_TYPE_2: 760 case RT5663_EM_JACK_TYPE_3: 761 case RT5663_JD_CTRL2: 762 case RT5663_VENDOR_ID: 763 case RT5663_VENDOR_ID_1: 764 case RT5663_VENDOR_ID_2: 765 case RT5663_PLL_INT_REG: 766 case RT5663_SOFT_RAMP: 767 case RT5663_STO_DRE_1: 768 case RT5663_STO_DRE_5: 769 case RT5663_STO_DRE_6: 770 case RT5663_STO_DRE_7: 771 case RT5663_MIC_DECRO_1: 772 case RT5663_MIC_DECRO_4: 773 case RT5663_HP_IMP_SEN_1: 774 case RT5663_HP_IMP_SEN_3: 775 case RT5663_HP_IMP_SEN_4: 776 case RT5663_HP_IMP_SEN_5: 777 case RT5663_HP_CALIB_1_1: 778 case RT5663_HP_CALIB_9: 779 case RT5663_HP_CALIB_ST1: 780 case RT5663_HP_CALIB_ST2: 781 case RT5663_HP_CALIB_ST3: 782 case RT5663_HP_CALIB_ST4: 783 case RT5663_HP_CALIB_ST5: 784 case RT5663_HP_CALIB_ST6: 785 case RT5663_HP_CALIB_ST7: 786 case RT5663_HP_CALIB_ST8: 787 case RT5663_HP_CALIB_ST9: 788 case RT5663_ANA_JD: 789 return true; 790 default: 791 return false; 792 } 793 } 794 795 static bool rt5663_readable_register(struct device *dev, unsigned int reg) 796 { 797 switch (reg) { 798 case RT5663_RESET: 799 case RT5663_HP_OUT_EN: 800 case RT5663_HP_LCH_DRE: 801 case RT5663_HP_RCH_DRE: 802 case RT5663_CALIB_BST: 803 case RT5663_RECMIX: 804 case RT5663_SIL_DET_CTL: 805 case RT5663_PWR_SAV_SILDET: 806 case RT5663_SIDETONE_CTL: 807 case RT5663_STO1_DAC_DIG_VOL: 808 case RT5663_STO1_ADC_DIG_VOL: 809 case RT5663_STO1_BOOST: 810 case RT5663_HP_IMP_GAIN_1: 811 case RT5663_HP_IMP_GAIN_2: 812 case RT5663_STO1_ADC_MIXER: 813 case RT5663_AD_DA_MIXER: 814 case RT5663_STO_DAC_MIXER: 815 case RT5663_DIG_SIDE_MIXER: 816 case RT5663_BYPASS_STO_DAC: 817 case RT5663_CALIB_REC_MIX: 818 case RT5663_PWR_DIG_1: 819 case RT5663_PWR_DIG_2: 820 case RT5663_PWR_ANLG_1: 821 case RT5663_PWR_ANLG_2: 822 case RT5663_PWR_ANLG_3: 823 case RT5663_PWR_MIXER: 824 case RT5663_SIG_CLK_DET: 825 case RT5663_PRE_DIV_GATING_1: 826 case RT5663_PRE_DIV_GATING_2: 827 case RT5663_I2S1_SDP: 828 case RT5663_ADDA_CLK_1: 829 case RT5663_ADDA_RST: 830 case RT5663_FRAC_DIV_1: 831 case RT5663_FRAC_DIV_2: 832 case RT5663_TDM_1: 833 case RT5663_TDM_2: 834 case RT5663_TDM_3: 835 case RT5663_TDM_4: 836 case RT5663_TDM_5: 837 case RT5663_GLB_CLK: 838 case RT5663_PLL_1: 839 case RT5663_PLL_2: 840 case RT5663_ASRC_1: 841 case RT5663_ASRC_2: 842 case RT5663_ASRC_4: 843 case RT5663_DUMMY_REG: 844 case RT5663_ASRC_8: 845 case RT5663_ASRC_9: 846 case RT5663_ASRC_11: 847 case RT5663_DEPOP_1: 848 case RT5663_DEPOP_2: 849 case RT5663_DEPOP_3: 850 case RT5663_HP_CHARGE_PUMP_1: 851 case RT5663_HP_CHARGE_PUMP_2: 852 case RT5663_MICBIAS_1: 853 case RT5663_RC_CLK: 854 case RT5663_ASRC_11_2: 855 case RT5663_DUMMY_REG_2: 856 case RT5663_REC_PATH_GAIN: 857 case RT5663_AUTO_1MRC_CLK: 858 case RT5663_ADC_EQ_1: 859 case RT5663_ADC_EQ_2: 860 case RT5663_IRQ_1: 861 case RT5663_IRQ_2: 862 case RT5663_IRQ_3: 863 case RT5663_IRQ_4: 864 case RT5663_IRQ_5: 865 case RT5663_INT_ST_1: 866 case RT5663_INT_ST_2: 867 case RT5663_GPIO_1: 868 case RT5663_GPIO_2: 869 case RT5663_GPIO_STA1: 870 case RT5663_SIN_GEN_1: 871 case RT5663_SIN_GEN_2: 872 case RT5663_SIN_GEN_3: 873 case RT5663_SOF_VOL_ZC1: 874 case RT5663_IL_CMD_1: 875 case RT5663_IL_CMD_2: 876 case RT5663_IL_CMD_3: 877 case RT5663_IL_CMD_4: 878 case RT5663_IL_CMD_5: 879 case RT5663_IL_CMD_6: 880 case RT5663_IL_CMD_7: 881 case RT5663_IL_CMD_8: 882 case RT5663_IL_CMD_PWRSAV1: 883 case RT5663_IL_CMD_PWRSAV2: 884 case RT5663_EM_JACK_TYPE_1: 885 case RT5663_EM_JACK_TYPE_2: 886 case RT5663_EM_JACK_TYPE_3: 887 case RT5663_EM_JACK_TYPE_4: 888 case RT5663_EM_JACK_TYPE_5: 889 case RT5663_EM_JACK_TYPE_6: 890 case RT5663_STO1_HPF_ADJ1: 891 case RT5663_STO1_HPF_ADJ2: 892 case RT5663_FAST_OFF_MICBIAS: 893 case RT5663_JD_CTRL1: 894 case RT5663_JD_CTRL2: 895 case RT5663_DIG_MISC: 896 case RT5663_VENDOR_ID: 897 case RT5663_VENDOR_ID_1: 898 case RT5663_VENDOR_ID_2: 899 case RT5663_DIG_VOL_ZCD: 900 case RT5663_ANA_BIAS_CUR_1: 901 case RT5663_ANA_BIAS_CUR_2: 902 case RT5663_ANA_BIAS_CUR_3: 903 case RT5663_ANA_BIAS_CUR_4: 904 case RT5663_ANA_BIAS_CUR_5: 905 case RT5663_ANA_BIAS_CUR_6: 906 case RT5663_BIAS_CUR_5: 907 case RT5663_BIAS_CUR_6: 908 case RT5663_BIAS_CUR_7: 909 case RT5663_BIAS_CUR_8: 910 case RT5663_DACREF_LDO: 911 case RT5663_DUMMY_REG_3: 912 case RT5663_BIAS_CUR_9: 913 case RT5663_DUMMY_REG_4: 914 case RT5663_VREFADJ_OP: 915 case RT5663_VREF_RECMIX: 916 case RT5663_CHARGE_PUMP_1: 917 case RT5663_CHARGE_PUMP_1_2: 918 case RT5663_CHARGE_PUMP_1_3: 919 case RT5663_CHARGE_PUMP_2: 920 case RT5663_DIG_IN_PIN1: 921 case RT5663_PAD_DRV_CTL: 922 case RT5663_PLL_INT_REG: 923 case RT5663_CHOP_DAC_L: 924 case RT5663_CHOP_ADC: 925 case RT5663_CALIB_ADC: 926 case RT5663_CHOP_DAC_R: 927 case RT5663_DUMMY_CTL_DACLR: 928 case RT5663_DUMMY_REG_5: 929 case RT5663_SOFT_RAMP: 930 case RT5663_TEST_MODE_1: 931 case RT5663_TEST_MODE_2: 932 case RT5663_TEST_MODE_3: 933 case RT5663_STO_DRE_1: 934 case RT5663_STO_DRE_2: 935 case RT5663_STO_DRE_3: 936 case RT5663_STO_DRE_4: 937 case RT5663_STO_DRE_5: 938 case RT5663_STO_DRE_6: 939 case RT5663_STO_DRE_7: 940 case RT5663_STO_DRE_8: 941 case RT5663_STO_DRE_9: 942 case RT5663_STO_DRE_10: 943 case RT5663_MIC_DECRO_1: 944 case RT5663_MIC_DECRO_2: 945 case RT5663_MIC_DECRO_3: 946 case RT5663_MIC_DECRO_4: 947 case RT5663_MIC_DECRO_5: 948 case RT5663_MIC_DECRO_6: 949 case RT5663_HP_DECRO_1: 950 case RT5663_HP_DECRO_2: 951 case RT5663_HP_DECRO_3: 952 case RT5663_HP_DECRO_4: 953 case RT5663_HP_DECOUP: 954 case RT5663_HP_IMP_SEN_MAP8: 955 case RT5663_HP_IMP_SEN_MAP9: 956 case RT5663_HP_IMP_SEN_MAP10: 957 case RT5663_HP_IMP_SEN_MAP11: 958 case RT5663_HP_IMP_SEN_1: 959 case RT5663_HP_IMP_SEN_2: 960 case RT5663_HP_IMP_SEN_3: 961 case RT5663_HP_IMP_SEN_4: 962 case RT5663_HP_IMP_SEN_5: 963 case RT5663_HP_IMP_SEN_6: 964 case RT5663_HP_IMP_SEN_7: 965 case RT5663_HP_IMP_SEN_8: 966 case RT5663_HP_IMP_SEN_9: 967 case RT5663_HP_IMP_SEN_10: 968 case RT5663_HP_IMP_SEN_11: 969 case RT5663_HP_IMP_SEN_12: 970 case RT5663_HP_IMP_SEN_13: 971 case RT5663_HP_IMP_SEN_14: 972 case RT5663_HP_IMP_SEN_15: 973 case RT5663_HP_IMP_SEN_16: 974 case RT5663_HP_IMP_SEN_17: 975 case RT5663_HP_IMP_SEN_18: 976 case RT5663_HP_IMP_SEN_19: 977 case RT5663_HP_IMPSEN_DIG5: 978 case RT5663_HP_IMPSEN_MAP1: 979 case RT5663_HP_IMPSEN_MAP2: 980 case RT5663_HP_IMPSEN_MAP3: 981 case RT5663_HP_IMPSEN_MAP4: 982 case RT5663_HP_IMPSEN_MAP5: 983 case RT5663_HP_IMPSEN_MAP7: 984 case RT5663_HP_LOGIC_1: 985 case RT5663_HP_LOGIC_2: 986 case RT5663_HP_CALIB_1: 987 case RT5663_HP_CALIB_1_1: 988 case RT5663_HP_CALIB_2: 989 case RT5663_HP_CALIB_3: 990 case RT5663_HP_CALIB_4: 991 case RT5663_HP_CALIB_5: 992 case RT5663_HP_CALIB_5_1: 993 case RT5663_HP_CALIB_6: 994 case RT5663_HP_CALIB_7: 995 case RT5663_HP_CALIB_9: 996 case RT5663_HP_CALIB_10: 997 case RT5663_HP_CALIB_11: 998 case RT5663_HP_CALIB_ST1: 999 case RT5663_HP_CALIB_ST2: 1000 case RT5663_HP_CALIB_ST3: 1001 case RT5663_HP_CALIB_ST4: 1002 case RT5663_HP_CALIB_ST5: 1003 case RT5663_HP_CALIB_ST6: 1004 case RT5663_HP_CALIB_ST7: 1005 case RT5663_HP_CALIB_ST8: 1006 case RT5663_HP_CALIB_ST9: 1007 case RT5663_HP_AMP_DET: 1008 case RT5663_DUMMY_REG_6: 1009 case RT5663_HP_BIAS: 1010 case RT5663_CBJ_1: 1011 case RT5663_CBJ_2: 1012 case RT5663_CBJ_3: 1013 case RT5663_DUMMY_1: 1014 case RT5663_DUMMY_2: 1015 case RT5663_DUMMY_3: 1016 case RT5663_ANA_JD: 1017 case RT5663_ADC_LCH_LPF1_A1: 1018 case RT5663_ADC_RCH_LPF1_A1: 1019 case RT5663_ADC_LCH_LPF1_H0: 1020 case RT5663_ADC_RCH_LPF1_H0: 1021 case RT5663_ADC_LCH_BPF1_A1: 1022 case RT5663_ADC_RCH_BPF1_A1: 1023 case RT5663_ADC_LCH_BPF1_A2: 1024 case RT5663_ADC_RCH_BPF1_A2: 1025 case RT5663_ADC_LCH_BPF1_H0: 1026 case RT5663_ADC_RCH_BPF1_H0: 1027 case RT5663_ADC_LCH_BPF2_A1: 1028 case RT5663_ADC_RCH_BPF2_A1: 1029 case RT5663_ADC_LCH_BPF2_A2: 1030 case RT5663_ADC_RCH_BPF2_A2: 1031 case RT5663_ADC_LCH_BPF2_H0: 1032 case RT5663_ADC_RCH_BPF2_H0: 1033 case RT5663_ADC_LCH_BPF3_A1: 1034 case RT5663_ADC_RCH_BPF3_A1: 1035 case RT5663_ADC_LCH_BPF3_A2: 1036 case RT5663_ADC_RCH_BPF3_A2: 1037 case RT5663_ADC_LCH_BPF3_H0: 1038 case RT5663_ADC_RCH_BPF3_H0: 1039 case RT5663_ADC_LCH_BPF4_A1: 1040 case RT5663_ADC_RCH_BPF4_A1: 1041 case RT5663_ADC_LCH_BPF4_A2: 1042 case RT5663_ADC_RCH_BPF4_A2: 1043 case RT5663_ADC_LCH_BPF4_H0: 1044 case RT5663_ADC_RCH_BPF4_H0: 1045 case RT5663_ADC_LCH_HPF1_A1: 1046 case RT5663_ADC_RCH_HPF1_A1: 1047 case RT5663_ADC_LCH_HPF1_H0: 1048 case RT5663_ADC_RCH_HPF1_H0: 1049 case RT5663_ADC_EQ_PRE_VOL_L: 1050 case RT5663_ADC_EQ_PRE_VOL_R: 1051 case RT5663_ADC_EQ_POST_VOL_L: 1052 case RT5663_ADC_EQ_POST_VOL_R: 1053 return true; 1054 default: 1055 return false; 1056 } 1057 } 1058 1059 static bool rt5663_v2_volatile_register(struct device *dev, unsigned int reg) 1060 { 1061 switch (reg) { 1062 case RT5663_RESET: 1063 case RT5663_CBJ_TYPE_2: 1064 case RT5663_PDM_OUT_CTL: 1065 case RT5663_PDM_I2C_DATA_CTL1: 1066 case RT5663_PDM_I2C_DATA_CTL4: 1067 case RT5663_ALC_BK_GAIN: 1068 case RT5663_PLL_2: 1069 case RT5663_MICBIAS_1: 1070 case RT5663_ADC_EQ_1: 1071 case RT5663_INT_ST_1: 1072 case RT5663_GPIO_STA2: 1073 case RT5663_IL_CMD_1: 1074 case RT5663_IL_CMD_5: 1075 case RT5663_A_JD_CTRL: 1076 case RT5663_JD_CTRL2: 1077 case RT5663_VENDOR_ID: 1078 case RT5663_VENDOR_ID_1: 1079 case RT5663_VENDOR_ID_2: 1080 case RT5663_STO_DRE_1: 1081 case RT5663_STO_DRE_5: 1082 case RT5663_STO_DRE_6: 1083 case RT5663_STO_DRE_7: 1084 case RT5663_MONO_DYNA_6: 1085 case RT5663_STO1_SIL_DET: 1086 case RT5663_MONOL_SIL_DET: 1087 case RT5663_MONOR_SIL_DET: 1088 case RT5663_STO2_DAC_SIL: 1089 case RT5663_MONO_AMP_CAL_ST1: 1090 case RT5663_MONO_AMP_CAL_ST2: 1091 case RT5663_MONO_AMP_CAL_ST3: 1092 case RT5663_MONO_AMP_CAL_ST4: 1093 case RT5663_HP_IMP_SEN_2: 1094 case RT5663_HP_IMP_SEN_3: 1095 case RT5663_HP_IMP_SEN_4: 1096 case RT5663_HP_IMP_SEN_10: 1097 case RT5663_HP_CALIB_1: 1098 case RT5663_HP_CALIB_10: 1099 case RT5663_HP_CALIB_ST1: 1100 case RT5663_HP_CALIB_ST4: 1101 case RT5663_HP_CALIB_ST5: 1102 case RT5663_HP_CALIB_ST6: 1103 case RT5663_HP_CALIB_ST7: 1104 case RT5663_HP_CALIB_ST8: 1105 case RT5663_HP_CALIB_ST9: 1106 case RT5663_HP_CALIB_ST10: 1107 case RT5663_HP_CALIB_ST11: 1108 return true; 1109 default: 1110 return false; 1111 } 1112 } 1113 1114 static bool rt5663_v2_readable_register(struct device *dev, unsigned int reg) 1115 { 1116 switch (reg) { 1117 case RT5663_LOUT_CTRL: 1118 case RT5663_HP_AMP_2: 1119 case RT5663_MONO_OUT: 1120 case RT5663_MONO_GAIN: 1121 case RT5663_AEC_BST: 1122 case RT5663_IN1_IN2: 1123 case RT5663_IN3_IN4: 1124 case RT5663_INL1_INR1: 1125 case RT5663_CBJ_TYPE_2: 1126 case RT5663_CBJ_TYPE_3: 1127 case RT5663_CBJ_TYPE_4: 1128 case RT5663_CBJ_TYPE_5: 1129 case RT5663_CBJ_TYPE_8: 1130 case RT5663_DAC3_DIG_VOL: 1131 case RT5663_DAC3_CTRL: 1132 case RT5663_MONO_ADC_DIG_VOL: 1133 case RT5663_STO2_ADC_DIG_VOL: 1134 case RT5663_MONO_ADC_BST_GAIN: 1135 case RT5663_STO2_ADC_BST_GAIN: 1136 case RT5663_SIDETONE_CTRL: 1137 case RT5663_MONO1_ADC_MIXER: 1138 case RT5663_STO2_ADC_MIXER: 1139 case RT5663_MONO_DAC_MIXER: 1140 case RT5663_DAC2_SRC_CTRL: 1141 case RT5663_IF_3_4_DATA_CTL: 1142 case RT5663_IF_5_DATA_CTL: 1143 case RT5663_PDM_OUT_CTL: 1144 case RT5663_PDM_I2C_DATA_CTL1: 1145 case RT5663_PDM_I2C_DATA_CTL2: 1146 case RT5663_PDM_I2C_DATA_CTL3: 1147 case RT5663_PDM_I2C_DATA_CTL4: 1148 case RT5663_RECMIX1_NEW: 1149 case RT5663_RECMIX1L_0: 1150 case RT5663_RECMIX1L: 1151 case RT5663_RECMIX1R_0: 1152 case RT5663_RECMIX1R: 1153 case RT5663_RECMIX2_NEW: 1154 case RT5663_RECMIX2_L_2: 1155 case RT5663_RECMIX2_R: 1156 case RT5663_RECMIX2_R_2: 1157 case RT5663_CALIB_REC_LR: 1158 case RT5663_ALC_BK_GAIN: 1159 case RT5663_MONOMIX_GAIN: 1160 case RT5663_MONOMIX_IN_GAIN: 1161 case RT5663_OUT_MIXL_GAIN: 1162 case RT5663_OUT_LMIX_IN_GAIN: 1163 case RT5663_OUT_RMIX_IN_GAIN: 1164 case RT5663_OUT_RMIX_IN_GAIN1: 1165 case RT5663_LOUT_MIXER_CTRL: 1166 case RT5663_PWR_VOL: 1167 case RT5663_ADCDAC_RST: 1168 case RT5663_I2S34_SDP: 1169 case RT5663_I2S5_SDP: 1170 case RT5663_TDM_6: 1171 case RT5663_TDM_7: 1172 case RT5663_TDM_8: 1173 case RT5663_TDM_9: 1174 case RT5663_ASRC_3: 1175 case RT5663_ASRC_6: 1176 case RT5663_ASRC_7: 1177 case RT5663_PLL_TRK_13: 1178 case RT5663_I2S_M_CLK_CTL: 1179 case RT5663_FDIV_I2S34_M_CLK: 1180 case RT5663_FDIV_I2S34_M_CLK2: 1181 case RT5663_FDIV_I2S5_M_CLK: 1182 case RT5663_FDIV_I2S5_M_CLK2: 1183 case RT5663_V2_IRQ_4: 1184 case RT5663_GPIO_3: 1185 case RT5663_GPIO_4: 1186 case RT5663_GPIO_STA2: 1187 case RT5663_HP_AMP_DET1: 1188 case RT5663_HP_AMP_DET2: 1189 case RT5663_HP_AMP_DET3: 1190 case RT5663_MID_BD_HP_AMP: 1191 case RT5663_LOW_BD_HP_AMP: 1192 case RT5663_SOF_VOL_ZC2: 1193 case RT5663_ADC_STO2_ADJ1: 1194 case RT5663_ADC_STO2_ADJ2: 1195 case RT5663_A_JD_CTRL: 1196 case RT5663_JD1_TRES_CTRL: 1197 case RT5663_JD2_TRES_CTRL: 1198 case RT5663_V2_JD_CTRL2: 1199 case RT5663_DUM_REG_2: 1200 case RT5663_DUM_REG_3: 1201 case RT5663_VENDOR_ID: 1202 case RT5663_VENDOR_ID_1: 1203 case RT5663_VENDOR_ID_2: 1204 case RT5663_DACADC_DIG_VOL2: 1205 case RT5663_DIG_IN_PIN2: 1206 case RT5663_PAD_DRV_CTL1: 1207 case RT5663_SOF_RAM_DEPOP: 1208 case RT5663_VOL_TEST: 1209 case RT5663_TEST_MODE_4: 1210 case RT5663_TEST_MODE_5: 1211 case RT5663_STO_DRE_9: 1212 case RT5663_MONO_DYNA_1: 1213 case RT5663_MONO_DYNA_2: 1214 case RT5663_MONO_DYNA_3: 1215 case RT5663_MONO_DYNA_4: 1216 case RT5663_MONO_DYNA_5: 1217 case RT5663_MONO_DYNA_6: 1218 case RT5663_STO1_SIL_DET: 1219 case RT5663_MONOL_SIL_DET: 1220 case RT5663_MONOR_SIL_DET: 1221 case RT5663_STO2_DAC_SIL: 1222 case RT5663_PWR_SAV_CTL1: 1223 case RT5663_PWR_SAV_CTL2: 1224 case RT5663_PWR_SAV_CTL3: 1225 case RT5663_PWR_SAV_CTL4: 1226 case RT5663_PWR_SAV_CTL5: 1227 case RT5663_PWR_SAV_CTL6: 1228 case RT5663_MONO_AMP_CAL1: 1229 case RT5663_MONO_AMP_CAL2: 1230 case RT5663_MONO_AMP_CAL3: 1231 case RT5663_MONO_AMP_CAL4: 1232 case RT5663_MONO_AMP_CAL5: 1233 case RT5663_MONO_AMP_CAL6: 1234 case RT5663_MONO_AMP_CAL7: 1235 case RT5663_MONO_AMP_CAL_ST1: 1236 case RT5663_MONO_AMP_CAL_ST2: 1237 case RT5663_MONO_AMP_CAL_ST3: 1238 case RT5663_MONO_AMP_CAL_ST4: 1239 case RT5663_MONO_AMP_CAL_ST5: 1240 case RT5663_V2_HP_IMP_SEN_13: 1241 case RT5663_V2_HP_IMP_SEN_14: 1242 case RT5663_V2_HP_IMP_SEN_6: 1243 case RT5663_V2_HP_IMP_SEN_7: 1244 case RT5663_V2_HP_IMP_SEN_8: 1245 case RT5663_V2_HP_IMP_SEN_9: 1246 case RT5663_V2_HP_IMP_SEN_10: 1247 case RT5663_HP_LOGIC_3: 1248 case RT5663_HP_CALIB_ST10: 1249 case RT5663_HP_CALIB_ST11: 1250 case RT5663_PRO_REG_TBL_4: 1251 case RT5663_PRO_REG_TBL_5: 1252 case RT5663_PRO_REG_TBL_6: 1253 case RT5663_PRO_REG_TBL_7: 1254 case RT5663_PRO_REG_TBL_8: 1255 case RT5663_PRO_REG_TBL_9: 1256 case RT5663_SAR_ADC_INL_1: 1257 case RT5663_SAR_ADC_INL_2: 1258 case RT5663_SAR_ADC_INL_3: 1259 case RT5663_SAR_ADC_INL_4: 1260 case RT5663_SAR_ADC_INL_5: 1261 case RT5663_SAR_ADC_INL_6: 1262 case RT5663_SAR_ADC_INL_7: 1263 case RT5663_SAR_ADC_INL_8: 1264 case RT5663_SAR_ADC_INL_9: 1265 case RT5663_SAR_ADC_INL_10: 1266 case RT5663_SAR_ADC_INL_11: 1267 case RT5663_SAR_ADC_INL_12: 1268 case RT5663_DRC_CTRL_1: 1269 case RT5663_DRC1_CTRL_2: 1270 case RT5663_DRC1_CTRL_3: 1271 case RT5663_DRC1_CTRL_4: 1272 case RT5663_DRC1_CTRL_5: 1273 case RT5663_DRC1_CTRL_6: 1274 case RT5663_DRC1_HD_CTRL_1: 1275 case RT5663_DRC1_HD_CTRL_2: 1276 case RT5663_DRC1_PRI_REG_1: 1277 case RT5663_DRC1_PRI_REG_2: 1278 case RT5663_DRC1_PRI_REG_3: 1279 case RT5663_DRC1_PRI_REG_4: 1280 case RT5663_DRC1_PRI_REG_5: 1281 case RT5663_DRC1_PRI_REG_6: 1282 case RT5663_DRC1_PRI_REG_7: 1283 case RT5663_DRC1_PRI_REG_8: 1284 case RT5663_ALC_PGA_CTL_1: 1285 case RT5663_ALC_PGA_CTL_2: 1286 case RT5663_ALC_PGA_CTL_3: 1287 case RT5663_ALC_PGA_CTL_4: 1288 case RT5663_ALC_PGA_CTL_5: 1289 case RT5663_ALC_PGA_CTL_6: 1290 case RT5663_ALC_PGA_CTL_7: 1291 case RT5663_ALC_PGA_CTL_8: 1292 case RT5663_ALC_PGA_REG_1: 1293 case RT5663_ALC_PGA_REG_2: 1294 case RT5663_ALC_PGA_REG_3: 1295 case RT5663_ADC_EQ_RECOV_1: 1296 case RT5663_ADC_EQ_RECOV_2: 1297 case RT5663_ADC_EQ_RECOV_3: 1298 case RT5663_ADC_EQ_RECOV_4: 1299 case RT5663_ADC_EQ_RECOV_5: 1300 case RT5663_ADC_EQ_RECOV_6: 1301 case RT5663_ADC_EQ_RECOV_7: 1302 case RT5663_ADC_EQ_RECOV_8: 1303 case RT5663_ADC_EQ_RECOV_9: 1304 case RT5663_ADC_EQ_RECOV_10: 1305 case RT5663_ADC_EQ_RECOV_11: 1306 case RT5663_ADC_EQ_RECOV_12: 1307 case RT5663_ADC_EQ_RECOV_13: 1308 case RT5663_VID_HIDDEN: 1309 case RT5663_VID_CUSTOMER: 1310 case RT5663_SCAN_MODE: 1311 case RT5663_I2C_BYPA: 1312 return true; 1313 case RT5663_TDM_1: 1314 case RT5663_DEPOP_3: 1315 case RT5663_ASRC_11_2: 1316 case RT5663_INT_ST_2: 1317 case RT5663_GPIO_STA1: 1318 case RT5663_SIN_GEN_1: 1319 case RT5663_SIN_GEN_2: 1320 case RT5663_SIN_GEN_3: 1321 case RT5663_IL_CMD_PWRSAV1: 1322 case RT5663_IL_CMD_PWRSAV2: 1323 case RT5663_EM_JACK_TYPE_1: 1324 case RT5663_EM_JACK_TYPE_2: 1325 case RT5663_EM_JACK_TYPE_3: 1326 case RT5663_EM_JACK_TYPE_4: 1327 case RT5663_FAST_OFF_MICBIAS: 1328 case RT5663_ANA_BIAS_CUR_1: 1329 case RT5663_ANA_BIAS_CUR_2: 1330 case RT5663_BIAS_CUR_9: 1331 case RT5663_DUMMY_REG_4: 1332 case RT5663_VREF_RECMIX: 1333 case RT5663_CHARGE_PUMP_1_2: 1334 case RT5663_CHARGE_PUMP_1_3: 1335 case RT5663_CHARGE_PUMP_2: 1336 case RT5663_CHOP_DAC_R: 1337 case RT5663_DUMMY_CTL_DACLR: 1338 case RT5663_DUMMY_REG_5: 1339 case RT5663_SOFT_RAMP: 1340 case RT5663_TEST_MODE_1: 1341 case RT5663_STO_DRE_10: 1342 case RT5663_MIC_DECRO_1: 1343 case RT5663_MIC_DECRO_2: 1344 case RT5663_MIC_DECRO_3: 1345 case RT5663_MIC_DECRO_4: 1346 case RT5663_MIC_DECRO_5: 1347 case RT5663_MIC_DECRO_6: 1348 case RT5663_HP_DECRO_1: 1349 case RT5663_HP_DECRO_2: 1350 case RT5663_HP_DECRO_3: 1351 case RT5663_HP_DECRO_4: 1352 case RT5663_HP_DECOUP: 1353 case RT5663_HP_IMPSEN_MAP4: 1354 case RT5663_HP_IMPSEN_MAP5: 1355 case RT5663_HP_IMPSEN_MAP7: 1356 case RT5663_HP_CALIB_1: 1357 case RT5663_CBJ_1: 1358 case RT5663_CBJ_2: 1359 case RT5663_CBJ_3: 1360 return false; 1361 default: 1362 return rt5663_readable_register(dev, reg); 1363 } 1364 } 1365 1366 static const DECLARE_TLV_DB_SCALE(rt5663_hp_vol_tlv, -2400, 150, 0); 1367 static const DECLARE_TLV_DB_SCALE(rt5663_v2_hp_vol_tlv, -2250, 150, 0); 1368 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6525, 75, 0); 1369 static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0); 1370 1371 /* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */ 1372 static const DECLARE_TLV_DB_RANGE(in_bst_tlv, 1373 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0), 1374 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0), 1375 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0), 1376 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0), 1377 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0), 1378 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0), 1379 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0) 1380 ); 1381 1382 /* Interface data select */ 1383 static const char * const rt5663_if1_adc_data_select[] = { 1384 "L/R", "R/L", "L/L", "R/R" 1385 }; 1386 1387 static SOC_ENUM_SINGLE_DECL(rt5663_if1_adc_enum, RT5663_TDM_2, 1388 RT5663_DATA_SWAP_ADCDAT1_SHIFT, rt5663_if1_adc_data_select); 1389 1390 static void rt5663_enable_push_button_irq(struct snd_soc_component *component, 1391 bool enable) 1392 { 1393 struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component); 1394 1395 if (enable) { 1396 snd_soc_component_update_bits(component, RT5663_IL_CMD_6, 1397 RT5663_EN_4BTN_INL_MASK, RT5663_EN_4BTN_INL_EN); 1398 /* reset in-line command */ 1399 snd_soc_component_update_bits(component, RT5663_IL_CMD_6, 1400 RT5663_RESET_4BTN_INL_MASK, 1401 RT5663_RESET_4BTN_INL_RESET); 1402 snd_soc_component_update_bits(component, RT5663_IL_CMD_6, 1403 RT5663_RESET_4BTN_INL_MASK, 1404 RT5663_RESET_4BTN_INL_NOR); 1405 switch (rt5663->codec_ver) { 1406 case CODEC_VER_1: 1407 snd_soc_component_update_bits(component, RT5663_IRQ_3, 1408 RT5663_V2_EN_IRQ_INLINE_MASK, 1409 RT5663_V2_EN_IRQ_INLINE_NOR); 1410 break; 1411 case CODEC_VER_0: 1412 snd_soc_component_update_bits(component, RT5663_IRQ_2, 1413 RT5663_EN_IRQ_INLINE_MASK, 1414 RT5663_EN_IRQ_INLINE_NOR); 1415 break; 1416 default: 1417 dev_err(component->dev, "Unknown CODEC Version\n"); 1418 } 1419 } else { 1420 switch (rt5663->codec_ver) { 1421 case CODEC_VER_1: 1422 snd_soc_component_update_bits(component, RT5663_IRQ_3, 1423 RT5663_V2_EN_IRQ_INLINE_MASK, 1424 RT5663_V2_EN_IRQ_INLINE_BYP); 1425 break; 1426 case CODEC_VER_0: 1427 snd_soc_component_update_bits(component, RT5663_IRQ_2, 1428 RT5663_EN_IRQ_INLINE_MASK, 1429 RT5663_EN_IRQ_INLINE_BYP); 1430 break; 1431 default: 1432 dev_err(component->dev, "Unknown CODEC Version\n"); 1433 } 1434 snd_soc_component_update_bits(component, RT5663_IL_CMD_6, 1435 RT5663_EN_4BTN_INL_MASK, RT5663_EN_4BTN_INL_DIS); 1436 /* reset in-line command */ 1437 snd_soc_component_update_bits(component, RT5663_IL_CMD_6, 1438 RT5663_RESET_4BTN_INL_MASK, 1439 RT5663_RESET_4BTN_INL_RESET); 1440 snd_soc_component_update_bits(component, RT5663_IL_CMD_6, 1441 RT5663_RESET_4BTN_INL_MASK, 1442 RT5663_RESET_4BTN_INL_NOR); 1443 } 1444 } 1445 1446 /** 1447 * rt5663_v2_jack_detect - Detect headset. 1448 * @component: SoC audio component device. 1449 * @jack_insert: Jack insert or not. 1450 * 1451 * Detect whether is headset or not when jack inserted. 1452 * 1453 * Returns detect status. 1454 */ 1455 1456 static int rt5663_v2_jack_detect(struct snd_soc_component *component, int jack_insert) 1457 { 1458 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); 1459 struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component); 1460 int val, i = 0, sleep_time[5] = {300, 150, 100, 50, 30}; 1461 1462 dev_dbg(component->dev, "%s jack_insert:%d\n", __func__, jack_insert); 1463 if (jack_insert) { 1464 snd_soc_component_write(component, RT5663_CBJ_TYPE_2, 0x8040); 1465 snd_soc_component_write(component, RT5663_CBJ_TYPE_3, 0x1484); 1466 1467 snd_soc_dapm_force_enable_pin(dapm, "MICBIAS1"); 1468 snd_soc_dapm_force_enable_pin(dapm, "MICBIAS2"); 1469 snd_soc_dapm_force_enable_pin(dapm, "Mic Det Power"); 1470 snd_soc_dapm_force_enable_pin(dapm, "CBJ Power"); 1471 snd_soc_dapm_sync(dapm); 1472 snd_soc_component_update_bits(component, RT5663_RC_CLK, 1473 RT5663_DIG_1M_CLK_MASK, RT5663_DIG_1M_CLK_EN); 1474 snd_soc_component_update_bits(component, RT5663_RECMIX, 0x8, 0x8); 1475 1476 while (i < 5) { 1477 msleep(sleep_time[i]); 1478 val = snd_soc_component_read32(component, RT5663_CBJ_TYPE_2) & 0x0003; 1479 if (val == 0x1 || val == 0x2 || val == 0x3) 1480 break; 1481 dev_dbg(component->dev, "%s: MX-0011 val=%x sleep %d\n", 1482 __func__, val, sleep_time[i]); 1483 i++; 1484 } 1485 dev_dbg(component->dev, "%s val = %d\n", __func__, val); 1486 switch (val) { 1487 case 1: 1488 case 2: 1489 rt5663->jack_type = SND_JACK_HEADSET; 1490 rt5663_enable_push_button_irq(component, true); 1491 break; 1492 default: 1493 snd_soc_dapm_disable_pin(dapm, "MICBIAS1"); 1494 snd_soc_dapm_disable_pin(dapm, "MICBIAS2"); 1495 snd_soc_dapm_disable_pin(dapm, "Mic Det Power"); 1496 snd_soc_dapm_disable_pin(dapm, "CBJ Power"); 1497 snd_soc_dapm_sync(dapm); 1498 rt5663->jack_type = SND_JACK_HEADPHONE; 1499 break; 1500 } 1501 } else { 1502 snd_soc_component_update_bits(component, RT5663_RECMIX, 0x8, 0x0); 1503 1504 if (rt5663->jack_type == SND_JACK_HEADSET) { 1505 rt5663_enable_push_button_irq(component, false); 1506 snd_soc_dapm_disable_pin(dapm, "MICBIAS1"); 1507 snd_soc_dapm_disable_pin(dapm, "MICBIAS2"); 1508 snd_soc_dapm_disable_pin(dapm, "Mic Det Power"); 1509 snd_soc_dapm_disable_pin(dapm, "CBJ Power"); 1510 snd_soc_dapm_sync(dapm); 1511 } 1512 rt5663->jack_type = 0; 1513 } 1514 1515 dev_dbg(component->dev, "jack_type = %d\n", rt5663->jack_type); 1516 return rt5663->jack_type; 1517 } 1518 1519 /** 1520 * rt5663_jack_detect - Detect headset. 1521 * @component: SoC audio component device. 1522 * @jack_insert: Jack insert or not. 1523 * 1524 * Detect whether is headset or not when jack inserted. 1525 * 1526 * Returns detect status. 1527 */ 1528 static int rt5663_jack_detect(struct snd_soc_component *component, int jack_insert) 1529 { 1530 struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component); 1531 int val, i = 0; 1532 1533 dev_dbg(component->dev, "%s jack_insert:%d\n", __func__, jack_insert); 1534 1535 if (jack_insert) { 1536 snd_soc_component_update_bits(component, RT5663_DIG_MISC, 1537 RT5663_DIG_GATE_CTRL_MASK, RT5663_DIG_GATE_CTRL_EN); 1538 snd_soc_component_update_bits(component, RT5663_HP_CHARGE_PUMP_1, 1539 RT5663_SI_HP_MASK | RT5663_OSW_HP_L_MASK | 1540 RT5663_OSW_HP_R_MASK, RT5663_SI_HP_EN | 1541 RT5663_OSW_HP_L_DIS | RT5663_OSW_HP_R_DIS); 1542 snd_soc_component_update_bits(component, RT5663_DUMMY_1, 1543 RT5663_EMB_CLK_MASK | RT5663_HPA_CPL_BIAS_MASK | 1544 RT5663_HPA_CPR_BIAS_MASK, RT5663_EMB_CLK_EN | 1545 RT5663_HPA_CPL_BIAS_1 | RT5663_HPA_CPR_BIAS_1); 1546 snd_soc_component_update_bits(component, RT5663_CBJ_1, 1547 RT5663_INBUF_CBJ_BST1_MASK | RT5663_CBJ_SENSE_BST1_MASK, 1548 RT5663_INBUF_CBJ_BST1_ON | RT5663_CBJ_SENSE_BST1_L); 1549 snd_soc_component_update_bits(component, RT5663_IL_CMD_2, 1550 RT5663_PWR_MIC_DET_MASK, RT5663_PWR_MIC_DET_ON); 1551 /* BST1 power on for JD */ 1552 snd_soc_component_update_bits(component, RT5663_PWR_ANLG_2, 1553 RT5663_PWR_BST1_MASK, RT5663_PWR_BST1_ON); 1554 snd_soc_component_update_bits(component, RT5663_EM_JACK_TYPE_1, 1555 RT5663_CBJ_DET_MASK | RT5663_EXT_JD_MASK | 1556 RT5663_POL_EXT_JD_MASK, RT5663_CBJ_DET_EN | 1557 RT5663_EXT_JD_EN | RT5663_POL_EXT_JD_EN); 1558 snd_soc_component_update_bits(component, RT5663_PWR_ANLG_1, 1559 RT5663_PWR_MB_MASK | RT5663_LDO1_DVO_MASK | 1560 RT5663_AMP_HP_MASK, RT5663_PWR_MB | 1561 RT5663_LDO1_DVO_0_9V | RT5663_AMP_HP_3X); 1562 snd_soc_component_update_bits(component, RT5663_PWR_ANLG_1, 1563 RT5663_PWR_VREF1_MASK | RT5663_PWR_VREF2_MASK | 1564 RT5663_PWR_FV1_MASK | RT5663_PWR_FV2_MASK, 1565 RT5663_PWR_VREF1 | RT5663_PWR_VREF2); 1566 msleep(20); 1567 snd_soc_component_update_bits(component, RT5663_PWR_ANLG_1, 1568 RT5663_PWR_FV1_MASK | RT5663_PWR_FV2_MASK, 1569 RT5663_PWR_FV1 | RT5663_PWR_FV2); 1570 snd_soc_component_update_bits(component, RT5663_AUTO_1MRC_CLK, 1571 RT5663_IRQ_POW_SAV_MASK, RT5663_IRQ_POW_SAV_EN); 1572 snd_soc_component_update_bits(component, RT5663_IRQ_1, 1573 RT5663_EN_IRQ_JD1_MASK, RT5663_EN_IRQ_JD1_EN); 1574 snd_soc_component_update_bits(component, RT5663_EM_JACK_TYPE_1, 1575 RT5663_EM_JD_MASK, RT5663_EM_JD_RST); 1576 snd_soc_component_update_bits(component, RT5663_EM_JACK_TYPE_1, 1577 RT5663_EM_JD_MASK, RT5663_EM_JD_NOR); 1578 1579 while (true) { 1580 regmap_read(rt5663->regmap, RT5663_INT_ST_2, &val); 1581 if (!(val & 0x80)) 1582 usleep_range(10000, 10005); 1583 else 1584 break; 1585 1586 if (i > 200) 1587 break; 1588 i++; 1589 } 1590 1591 val = snd_soc_component_read32(component, RT5663_EM_JACK_TYPE_2) & 0x0003; 1592 dev_dbg(component->dev, "%s val = %d\n", __func__, val); 1593 1594 snd_soc_component_update_bits(component, RT5663_HP_CHARGE_PUMP_1, 1595 RT5663_OSW_HP_L_MASK | RT5663_OSW_HP_R_MASK, 1596 RT5663_OSW_HP_L_EN | RT5663_OSW_HP_R_EN); 1597 1598 switch (val) { 1599 case 1: 1600 case 2: 1601 rt5663->jack_type = SND_JACK_HEADSET; 1602 rt5663_enable_push_button_irq(component, true); 1603 1604 if (rt5663->pdata.impedance_sensing_num) 1605 break; 1606 1607 if (rt5663->pdata.dc_offset_l_manual_mic) { 1608 regmap_write(rt5663->regmap, RT5663_MIC_DECRO_2, 1609 rt5663->pdata.dc_offset_l_manual_mic >> 1610 16); 1611 regmap_write(rt5663->regmap, RT5663_MIC_DECRO_3, 1612 rt5663->pdata.dc_offset_l_manual_mic & 1613 0xffff); 1614 } 1615 1616 if (rt5663->pdata.dc_offset_r_manual_mic) { 1617 regmap_write(rt5663->regmap, RT5663_MIC_DECRO_5, 1618 rt5663->pdata.dc_offset_r_manual_mic >> 1619 16); 1620 regmap_write(rt5663->regmap, RT5663_MIC_DECRO_6, 1621 rt5663->pdata.dc_offset_r_manual_mic & 1622 0xffff); 1623 } 1624 break; 1625 default: 1626 rt5663->jack_type = SND_JACK_HEADPHONE; 1627 snd_soc_component_update_bits(component, 1628 RT5663_PWR_ANLG_1, 1629 RT5663_PWR_MB_MASK | RT5663_PWR_VREF1_MASK | 1630 RT5663_PWR_VREF2_MASK, 0); 1631 if (rt5663->pdata.impedance_sensing_num) 1632 break; 1633 1634 if (rt5663->pdata.dc_offset_l_manual) { 1635 regmap_write(rt5663->regmap, RT5663_MIC_DECRO_2, 1636 rt5663->pdata.dc_offset_l_manual >> 16); 1637 regmap_write(rt5663->regmap, RT5663_MIC_DECRO_3, 1638 rt5663->pdata.dc_offset_l_manual & 1639 0xffff); 1640 } 1641 1642 if (rt5663->pdata.dc_offset_r_manual) { 1643 regmap_write(rt5663->regmap, RT5663_MIC_DECRO_5, 1644 rt5663->pdata.dc_offset_r_manual >> 16); 1645 regmap_write(rt5663->regmap, RT5663_MIC_DECRO_6, 1646 rt5663->pdata.dc_offset_r_manual & 1647 0xffff); 1648 } 1649 break; 1650 } 1651 } else { 1652 if (rt5663->jack_type == SND_JACK_HEADSET) 1653 rt5663_enable_push_button_irq(component, false); 1654 rt5663->jack_type = 0; 1655 snd_soc_component_update_bits(component, RT5663_PWR_ANLG_1, 1656 RT5663_PWR_MB_MASK | RT5663_PWR_VREF1_MASK | 1657 RT5663_PWR_VREF2_MASK, 0); 1658 } 1659 1660 dev_dbg(component->dev, "jack_type = %d\n", rt5663->jack_type); 1661 return rt5663->jack_type; 1662 } 1663 1664 static int rt5663_impedance_sensing(struct snd_soc_component *component) 1665 { 1666 struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component); 1667 unsigned int value, i, reg84, reg26, reg2fa, reg91, reg10, reg80; 1668 1669 for (i = 0; i < rt5663->pdata.impedance_sensing_num; i++) { 1670 if (rt5663->imp_table[i].vol == 7) 1671 break; 1672 } 1673 1674 if (rt5663->jack_type == SND_JACK_HEADSET) { 1675 snd_soc_component_write(component, RT5663_MIC_DECRO_2, 1676 rt5663->imp_table[i].dc_offset_l_manual_mic >> 16); 1677 snd_soc_component_write(component, RT5663_MIC_DECRO_3, 1678 rt5663->imp_table[i].dc_offset_l_manual_mic & 0xffff); 1679 snd_soc_component_write(component, RT5663_MIC_DECRO_5, 1680 rt5663->imp_table[i].dc_offset_r_manual_mic >> 16); 1681 snd_soc_component_write(component, RT5663_MIC_DECRO_6, 1682 rt5663->imp_table[i].dc_offset_r_manual_mic & 0xffff); 1683 } else { 1684 snd_soc_component_write(component, RT5663_MIC_DECRO_2, 1685 rt5663->imp_table[i].dc_offset_l_manual >> 16); 1686 snd_soc_component_write(component, RT5663_MIC_DECRO_3, 1687 rt5663->imp_table[i].dc_offset_l_manual & 0xffff); 1688 snd_soc_component_write(component, RT5663_MIC_DECRO_5, 1689 rt5663->imp_table[i].dc_offset_r_manual >> 16); 1690 snd_soc_component_write(component, RT5663_MIC_DECRO_6, 1691 rt5663->imp_table[i].dc_offset_r_manual & 0xffff); 1692 } 1693 1694 reg84 = snd_soc_component_read32(component, RT5663_ASRC_2); 1695 reg26 = snd_soc_component_read32(component, RT5663_STO1_ADC_MIXER); 1696 reg2fa = snd_soc_component_read32(component, RT5663_DUMMY_1); 1697 reg91 = snd_soc_component_read32(component, RT5663_HP_CHARGE_PUMP_1); 1698 reg10 = snd_soc_component_read32(component, RT5663_RECMIX); 1699 reg80 = snd_soc_component_read32(component, RT5663_GLB_CLK); 1700 1701 snd_soc_component_update_bits(component, RT5663_STO_DRE_1, 0x8000, 0); 1702 snd_soc_component_write(component, RT5663_ASRC_2, 0); 1703 snd_soc_component_write(component, RT5663_STO1_ADC_MIXER, 0x4040); 1704 snd_soc_component_update_bits(component, RT5663_PWR_ANLG_1, 1705 RT5663_PWR_VREF1_MASK | RT5663_PWR_VREF2_MASK | 1706 RT5663_PWR_FV1_MASK | RT5663_PWR_FV2_MASK, 1707 RT5663_PWR_VREF1 | RT5663_PWR_VREF2); 1708 usleep_range(10000, 10005); 1709 snd_soc_component_update_bits(component, RT5663_PWR_ANLG_1, 1710 RT5663_PWR_FV1_MASK | RT5663_PWR_FV2_MASK, 1711 RT5663_PWR_FV1 | RT5663_PWR_FV2); 1712 snd_soc_component_update_bits(component, RT5663_GLB_CLK, RT5663_SCLK_SRC_MASK, 1713 RT5663_SCLK_SRC_RCCLK); 1714 snd_soc_component_update_bits(component, RT5663_RC_CLK, RT5663_DIG_25M_CLK_MASK, 1715 RT5663_DIG_25M_CLK_EN); 1716 snd_soc_component_update_bits(component, RT5663_ADDA_CLK_1, RT5663_I2S_PD1_MASK, 0); 1717 snd_soc_component_write(component, RT5663_PRE_DIV_GATING_1, 0xff00); 1718 snd_soc_component_write(component, RT5663_PRE_DIV_GATING_2, 0xfffc); 1719 snd_soc_component_write(component, RT5663_HP_CHARGE_PUMP_1, 0x1232); 1720 snd_soc_component_write(component, RT5663_HP_LOGIC_2, 0x0005); 1721 snd_soc_component_write(component, RT5663_DEPOP_2, 0x3003); 1722 snd_soc_component_update_bits(component, RT5663_DEPOP_1, 0x0030, 0x0030); 1723 snd_soc_component_update_bits(component, RT5663_DEPOP_1, 0x0003, 0x0003); 1724 snd_soc_component_update_bits(component, RT5663_PWR_DIG_2, 1725 RT5663_PWR_ADC_S1F | RT5663_PWR_DAC_S1F, 1726 RT5663_PWR_ADC_S1F | RT5663_PWR_DAC_S1F); 1727 snd_soc_component_update_bits(component, RT5663_PWR_DIG_1, 1728 RT5663_PWR_DAC_L1 | RT5663_PWR_DAC_R1 | 1729 RT5663_PWR_LDO_DACREF_MASK | RT5663_PWR_ADC_L1 | 1730 RT5663_PWR_ADC_R1, 1731 RT5663_PWR_DAC_L1 | RT5663_PWR_DAC_R1 | 1732 RT5663_PWR_LDO_DACREF_ON | RT5663_PWR_ADC_L1 | 1733 RT5663_PWR_ADC_R1); 1734 msleep(40); 1735 snd_soc_component_update_bits(component, RT5663_PWR_ANLG_2, 1736 RT5663_PWR_RECMIX1 | RT5663_PWR_RECMIX2, 1737 RT5663_PWR_RECMIX1 | RT5663_PWR_RECMIX2); 1738 msleep(30); 1739 snd_soc_component_write(component, RT5663_HP_CHARGE_PUMP_2, 0x1371); 1740 snd_soc_component_write(component, RT5663_STO_DAC_MIXER, 0); 1741 snd_soc_component_write(component, RT5663_BYPASS_STO_DAC, 0x000c); 1742 snd_soc_component_write(component, RT5663_HP_BIAS, 0xafaa); 1743 snd_soc_component_write(component, RT5663_CHARGE_PUMP_1, 0x2224); 1744 snd_soc_component_write(component, RT5663_HP_OUT_EN, 0x8088); 1745 snd_soc_component_write(component, RT5663_CHOP_ADC, 0x3000); 1746 snd_soc_component_write(component, RT5663_ADDA_RST, 0xc000); 1747 snd_soc_component_write(component, RT5663_STO1_HPF_ADJ1, 0x3320); 1748 snd_soc_component_write(component, RT5663_HP_CALIB_2, 0x00c9); 1749 snd_soc_component_write(component, RT5663_DUMMY_1, 0x004c); 1750 snd_soc_component_write(component, RT5663_ANA_BIAS_CUR_1, 0x7733); 1751 snd_soc_component_write(component, RT5663_CHARGE_PUMP_2, 0x7777); 1752 snd_soc_component_write(component, RT5663_STO_DRE_9, 0x0007); 1753 snd_soc_component_write(component, RT5663_STO_DRE_10, 0x0007); 1754 snd_soc_component_write(component, RT5663_DUMMY_2, 0x02a4); 1755 snd_soc_component_write(component, RT5663_RECMIX, 0x0005); 1756 snd_soc_component_write(component, RT5663_HP_IMP_SEN_1, 0x4334); 1757 snd_soc_component_update_bits(component, RT5663_IRQ_3, 0x0004, 0x0004); 1758 snd_soc_component_write(component, RT5663_HP_LOGIC_1, 0x2200); 1759 snd_soc_component_update_bits(component, RT5663_DEPOP_1, 0x3000, 0x3000); 1760 snd_soc_component_write(component, RT5663_HP_LOGIC_1, 0x6200); 1761 1762 for (i = 0; i < 100; i++) { 1763 msleep(20); 1764 if (snd_soc_component_read32(component, RT5663_INT_ST_1) & 0x2) 1765 break; 1766 } 1767 1768 value = snd_soc_component_read32(component, RT5663_HP_IMP_SEN_4); 1769 1770 snd_soc_component_update_bits(component, RT5663_DEPOP_1, 0x3000, 0); 1771 snd_soc_component_write(component, RT5663_INT_ST_1, 0); 1772 snd_soc_component_write(component, RT5663_HP_LOGIC_1, 0); 1773 snd_soc_component_update_bits(component, RT5663_RC_CLK, RT5663_DIG_25M_CLK_MASK, 1774 RT5663_DIG_25M_CLK_DIS); 1775 snd_soc_component_write(component, RT5663_GLB_CLK, reg80); 1776 snd_soc_component_write(component, RT5663_RECMIX, reg10); 1777 snd_soc_component_write(component, RT5663_DUMMY_2, 0x00a4); 1778 snd_soc_component_write(component, RT5663_DUMMY_1, reg2fa); 1779 snd_soc_component_write(component, RT5663_HP_CALIB_2, 0x00c8); 1780 snd_soc_component_write(component, RT5663_STO1_HPF_ADJ1, 0xb320); 1781 snd_soc_component_write(component, RT5663_ADDA_RST, 0xe400); 1782 snd_soc_component_write(component, RT5663_CHOP_ADC, 0x2000); 1783 snd_soc_component_write(component, RT5663_HP_OUT_EN, 0x0008); 1784 snd_soc_component_update_bits(component, RT5663_PWR_ANLG_2, 1785 RT5663_PWR_RECMIX1 | RT5663_PWR_RECMIX2, 0); 1786 snd_soc_component_update_bits(component, RT5663_PWR_DIG_1, 1787 RT5663_PWR_DAC_L1 | RT5663_PWR_DAC_R1 | 1788 RT5663_PWR_LDO_DACREF_MASK | RT5663_PWR_ADC_L1 | 1789 RT5663_PWR_ADC_R1, 0); 1790 snd_soc_component_update_bits(component, RT5663_PWR_DIG_2, 1791 RT5663_PWR_ADC_S1F | RT5663_PWR_DAC_S1F, 0); 1792 snd_soc_component_update_bits(component, RT5663_DEPOP_1, 0x0003, 0); 1793 snd_soc_component_update_bits(component, RT5663_DEPOP_1, 0x0030, 0); 1794 snd_soc_component_write(component, RT5663_HP_LOGIC_2, 0); 1795 snd_soc_component_write(component, RT5663_HP_CHARGE_PUMP_1, reg91); 1796 snd_soc_component_update_bits(component, RT5663_PWR_ANLG_1, 1797 RT5663_PWR_VREF1_MASK | RT5663_PWR_VREF2_MASK, 0); 1798 snd_soc_component_write(component, RT5663_STO1_ADC_MIXER, reg26); 1799 snd_soc_component_write(component, RT5663_ASRC_2, reg84); 1800 1801 for (i = 0; i < rt5663->pdata.impedance_sensing_num; i++) { 1802 if (value >= rt5663->imp_table[i].imp_min && 1803 value <= rt5663->imp_table[i].imp_max) 1804 break; 1805 } 1806 1807 snd_soc_component_update_bits(component, RT5663_STO_DRE_9, RT5663_DRE_GAIN_HP_MASK, 1808 rt5663->imp_table[i].vol); 1809 snd_soc_component_update_bits(component, RT5663_STO_DRE_10, RT5663_DRE_GAIN_HP_MASK, 1810 rt5663->imp_table[i].vol); 1811 1812 if (rt5663->jack_type == SND_JACK_HEADSET) { 1813 snd_soc_component_write(component, RT5663_MIC_DECRO_2, 1814 rt5663->imp_table[i].dc_offset_l_manual_mic >> 16); 1815 snd_soc_component_write(component, RT5663_MIC_DECRO_3, 1816 rt5663->imp_table[i].dc_offset_l_manual_mic & 0xffff); 1817 snd_soc_component_write(component, RT5663_MIC_DECRO_5, 1818 rt5663->imp_table[i].dc_offset_r_manual_mic >> 16); 1819 snd_soc_component_write(component, RT5663_MIC_DECRO_6, 1820 rt5663->imp_table[i].dc_offset_r_manual_mic & 0xffff); 1821 } else { 1822 snd_soc_component_write(component, RT5663_MIC_DECRO_2, 1823 rt5663->imp_table[i].dc_offset_l_manual >> 16); 1824 snd_soc_component_write(component, RT5663_MIC_DECRO_3, 1825 rt5663->imp_table[i].dc_offset_l_manual & 0xffff); 1826 snd_soc_component_write(component, RT5663_MIC_DECRO_5, 1827 rt5663->imp_table[i].dc_offset_r_manual >> 16); 1828 snd_soc_component_write(component, RT5663_MIC_DECRO_6, 1829 rt5663->imp_table[i].dc_offset_r_manual & 0xffff); 1830 } 1831 1832 return 0; 1833 } 1834 1835 static int rt5663_button_detect(struct snd_soc_component *component) 1836 { 1837 int btn_type, val; 1838 1839 val = snd_soc_component_read32(component, RT5663_IL_CMD_5); 1840 dev_dbg(component->dev, "%s: val=0x%x\n", __func__, val); 1841 btn_type = val & 0xfff0; 1842 snd_soc_component_write(component, RT5663_IL_CMD_5, val); 1843 1844 return btn_type; 1845 } 1846 1847 static irqreturn_t rt5663_irq(int irq, void *data) 1848 { 1849 struct rt5663_priv *rt5663 = data; 1850 1851 dev_dbg(regmap_get_device(rt5663->regmap), "%s IRQ queue work\n", 1852 __func__); 1853 1854 queue_delayed_work(system_wq, &rt5663->jack_detect_work, 1855 msecs_to_jiffies(250)); 1856 1857 return IRQ_HANDLED; 1858 } 1859 1860 static int rt5663_set_jack_detect(struct snd_soc_component *component, 1861 struct snd_soc_jack *hs_jack, void *data) 1862 { 1863 struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component); 1864 1865 rt5663->hs_jack = hs_jack; 1866 1867 rt5663_irq(0, rt5663); 1868 1869 return 0; 1870 } 1871 1872 static bool rt5663_check_jd_status(struct snd_soc_component *component) 1873 { 1874 struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component); 1875 int val = snd_soc_component_read32(component, RT5663_INT_ST_1); 1876 1877 dev_dbg(component->dev, "%s val=%x\n", __func__, val); 1878 1879 /* JD1 */ 1880 switch (rt5663->codec_ver) { 1881 case CODEC_VER_1: 1882 return !(val & 0x2000); 1883 case CODEC_VER_0: 1884 return !(val & 0x1000); 1885 default: 1886 dev_err(component->dev, "Unknown CODEC Version\n"); 1887 } 1888 1889 return false; 1890 } 1891 1892 static void rt5663_jack_detect_work(struct work_struct *work) 1893 { 1894 struct rt5663_priv *rt5663 = 1895 container_of(work, struct rt5663_priv, jack_detect_work.work); 1896 struct snd_soc_component *component = rt5663->component; 1897 int btn_type, report = 0; 1898 1899 if (!component) 1900 return; 1901 1902 if (rt5663_check_jd_status(component)) { 1903 /* jack in */ 1904 if (rt5663->jack_type == 0) { 1905 /* jack was out, report jack type */ 1906 switch (rt5663->codec_ver) { 1907 case CODEC_VER_1: 1908 report = rt5663_v2_jack_detect( 1909 rt5663->component, 1); 1910 break; 1911 case CODEC_VER_0: 1912 report = rt5663_jack_detect(rt5663->component, 1); 1913 if (rt5663->pdata.impedance_sensing_num) 1914 rt5663_impedance_sensing(rt5663->component); 1915 break; 1916 default: 1917 dev_err(component->dev, "Unknown CODEC Version\n"); 1918 } 1919 1920 /* Delay the jack insert report to avoid pop noise */ 1921 msleep(30); 1922 } else { 1923 /* jack is already in, report button event */ 1924 report = SND_JACK_HEADSET; 1925 btn_type = rt5663_button_detect(rt5663->component); 1926 /** 1927 * rt5663 can report three kinds of button behavior, 1928 * one click, double click and hold. However, 1929 * currently we will report button pressed/released 1930 * event. So all the three button behaviors are 1931 * treated as button pressed. 1932 */ 1933 switch (btn_type) { 1934 case 0x8000: 1935 case 0x4000: 1936 case 0x2000: 1937 report |= SND_JACK_BTN_0; 1938 break; 1939 case 0x1000: 1940 case 0x0800: 1941 case 0x0400: 1942 report |= SND_JACK_BTN_1; 1943 break; 1944 case 0x0200: 1945 case 0x0100: 1946 case 0x0080: 1947 report |= SND_JACK_BTN_2; 1948 break; 1949 case 0x0040: 1950 case 0x0020: 1951 case 0x0010: 1952 report |= SND_JACK_BTN_3; 1953 break; 1954 case 0x0000: /* unpressed */ 1955 break; 1956 default: 1957 btn_type = 0; 1958 dev_err(rt5663->component->dev, 1959 "Unexpected button code 0x%04x\n", 1960 btn_type); 1961 break; 1962 } 1963 /* button release or spurious interrput*/ 1964 if (btn_type == 0) { 1965 report = rt5663->jack_type; 1966 cancel_delayed_work_sync( 1967 &rt5663->jd_unplug_work); 1968 } else { 1969 queue_delayed_work(system_wq, 1970 &rt5663->jd_unplug_work, 1971 msecs_to_jiffies(500)); 1972 } 1973 } 1974 } else { 1975 /* jack out */ 1976 switch (rt5663->codec_ver) { 1977 case CODEC_VER_1: 1978 report = rt5663_v2_jack_detect(rt5663->component, 0); 1979 break; 1980 case CODEC_VER_0: 1981 report = rt5663_jack_detect(rt5663->component, 0); 1982 break; 1983 default: 1984 dev_err(component->dev, "Unknown CODEC Version\n"); 1985 } 1986 } 1987 dev_dbg(component->dev, "%s jack report: 0x%04x\n", __func__, report); 1988 snd_soc_jack_report(rt5663->hs_jack, report, SND_JACK_HEADSET | 1989 SND_JACK_BTN_0 | SND_JACK_BTN_1 | 1990 SND_JACK_BTN_2 | SND_JACK_BTN_3); 1991 } 1992 1993 static void rt5663_jd_unplug_work(struct work_struct *work) 1994 { 1995 struct rt5663_priv *rt5663 = 1996 container_of(work, struct rt5663_priv, jd_unplug_work.work); 1997 struct snd_soc_component *component = rt5663->component; 1998 1999 if (!component) 2000 return; 2001 2002 if (!rt5663_check_jd_status(component)) { 2003 /* jack out */ 2004 switch (rt5663->codec_ver) { 2005 case CODEC_VER_1: 2006 rt5663_v2_jack_detect(rt5663->component, 0); 2007 break; 2008 case CODEC_VER_0: 2009 rt5663_jack_detect(rt5663->component, 0); 2010 break; 2011 default: 2012 dev_err(component->dev, "Unknown CODEC Version\n"); 2013 } 2014 2015 snd_soc_jack_report(rt5663->hs_jack, 0, SND_JACK_HEADSET | 2016 SND_JACK_BTN_0 | SND_JACK_BTN_1 | 2017 SND_JACK_BTN_2 | SND_JACK_BTN_3); 2018 } else { 2019 queue_delayed_work(system_wq, &rt5663->jd_unplug_work, 2020 msecs_to_jiffies(500)); 2021 } 2022 } 2023 2024 static const struct snd_kcontrol_new rt5663_snd_controls[] = { 2025 /* DAC Digital Volume */ 2026 SOC_DOUBLE_TLV("DAC Playback Volume", RT5663_STO1_DAC_DIG_VOL, 2027 RT5663_DAC_L1_VOL_SHIFT + 1, RT5663_DAC_R1_VOL_SHIFT + 1, 2028 87, 0, dac_vol_tlv), 2029 /* ADC Digital Volume Control */ 2030 SOC_DOUBLE("ADC Capture Switch", RT5663_STO1_ADC_DIG_VOL, 2031 RT5663_ADC_L_MUTE_SHIFT, RT5663_ADC_R_MUTE_SHIFT, 1, 1), 2032 SOC_DOUBLE_TLV("ADC Capture Volume", RT5663_STO1_ADC_DIG_VOL, 2033 RT5663_ADC_L_VOL_SHIFT + 1, RT5663_ADC_R_VOL_SHIFT + 1, 2034 63, 0, adc_vol_tlv), 2035 }; 2036 2037 static const struct snd_kcontrol_new rt5663_v2_specific_controls[] = { 2038 /* Headphone Output Volume */ 2039 SOC_DOUBLE_R_TLV("Headphone Playback Volume", RT5663_HP_LCH_DRE, 2040 RT5663_HP_RCH_DRE, RT5663_GAIN_HP_SHIFT, 15, 1, 2041 rt5663_v2_hp_vol_tlv), 2042 /* Mic Boost Volume */ 2043 SOC_SINGLE_TLV("IN1 Capture Volume", RT5663_AEC_BST, 2044 RT5663_GAIN_CBJ_SHIFT, 8, 0, in_bst_tlv), 2045 }; 2046 2047 static const struct snd_kcontrol_new rt5663_specific_controls[] = { 2048 /* Mic Boost Volume*/ 2049 SOC_SINGLE_TLV("IN1 Capture Volume", RT5663_CBJ_2, 2050 RT5663_GAIN_BST1_SHIFT, 8, 0, in_bst_tlv), 2051 /* Data Swap for Slot0/1 in ADCDAT1 */ 2052 SOC_ENUM("IF1 ADC Data Swap", rt5663_if1_adc_enum), 2053 }; 2054 2055 static const struct snd_kcontrol_new rt5663_hpvol_controls[] = { 2056 /* Headphone Output Volume */ 2057 SOC_DOUBLE_R_TLV("Headphone Playback Volume", RT5663_STO_DRE_9, 2058 RT5663_STO_DRE_10, RT5663_DRE_GAIN_HP_SHIFT, 23, 1, 2059 rt5663_hp_vol_tlv), 2060 }; 2061 2062 static int rt5663_is_sys_clk_from_pll(struct snd_soc_dapm_widget *w, 2063 struct snd_soc_dapm_widget *sink) 2064 { 2065 unsigned int val; 2066 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 2067 2068 val = snd_soc_component_read32(component, RT5663_GLB_CLK); 2069 val &= RT5663_SCLK_SRC_MASK; 2070 if (val == RT5663_SCLK_SRC_PLL1) 2071 return 1; 2072 else 2073 return 0; 2074 } 2075 2076 static int rt5663_is_using_asrc(struct snd_soc_dapm_widget *w, 2077 struct snd_soc_dapm_widget *sink) 2078 { 2079 unsigned int reg, shift, val; 2080 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 2081 struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component); 2082 2083 if (rt5663->codec_ver == CODEC_VER_1) { 2084 switch (w->shift) { 2085 case RT5663_ADC_STO1_ASRC_SHIFT: 2086 reg = RT5663_ASRC_3; 2087 shift = RT5663_V2_AD_STO1_TRACK_SHIFT; 2088 break; 2089 case RT5663_DAC_STO1_ASRC_SHIFT: 2090 reg = RT5663_ASRC_2; 2091 shift = RT5663_DA_STO1_TRACK_SHIFT; 2092 break; 2093 default: 2094 return 0; 2095 } 2096 } else { 2097 switch (w->shift) { 2098 case RT5663_ADC_STO1_ASRC_SHIFT: 2099 reg = RT5663_ASRC_2; 2100 shift = RT5663_AD_STO1_TRACK_SHIFT; 2101 break; 2102 case RT5663_DAC_STO1_ASRC_SHIFT: 2103 reg = RT5663_ASRC_2; 2104 shift = RT5663_DA_STO1_TRACK_SHIFT; 2105 break; 2106 default: 2107 return 0; 2108 } 2109 } 2110 2111 val = (snd_soc_component_read32(component, reg) >> shift) & 0x7; 2112 2113 if (val) 2114 return 1; 2115 2116 return 0; 2117 } 2118 2119 static int rt5663_i2s_use_asrc(struct snd_soc_dapm_widget *source, 2120 struct snd_soc_dapm_widget *sink) 2121 { 2122 struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm); 2123 struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component); 2124 int da_asrc_en, ad_asrc_en; 2125 2126 da_asrc_en = (snd_soc_component_read32(component, RT5663_ASRC_2) & 2127 RT5663_DA_STO1_TRACK_MASK) ? 1 : 0; 2128 switch (rt5663->codec_ver) { 2129 case CODEC_VER_1: 2130 ad_asrc_en = (snd_soc_component_read32(component, RT5663_ASRC_3) & 2131 RT5663_V2_AD_STO1_TRACK_MASK) ? 1 : 0; 2132 break; 2133 case CODEC_VER_0: 2134 ad_asrc_en = (snd_soc_component_read32(component, RT5663_ASRC_2) & 2135 RT5663_AD_STO1_TRACK_MASK) ? 1 : 0; 2136 break; 2137 default: 2138 dev_err(component->dev, "Unknown CODEC Version\n"); 2139 return 1; 2140 } 2141 2142 if (da_asrc_en || ad_asrc_en) 2143 if (rt5663->sysclk > rt5663->lrck * 384) 2144 return 1; 2145 2146 dev_err(component->dev, "sysclk < 384 x fs, disable i2s asrc\n"); 2147 2148 return 0; 2149 } 2150 2151 /** 2152 * rt5663_sel_asrc_clk_src - select ASRC clock source for a set of filters 2153 * @component: SoC audio component device. 2154 * @filter_mask: mask of filters. 2155 * @clk_src: clock source 2156 * 2157 * The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5663 can 2158 * only support standard 32fs or 64fs i2s format, ASRC should be enabled to 2159 * support special i2s clock format such as Intel's 100fs(100 * sampling rate). 2160 * ASRC function will track i2s clock and generate a corresponding system clock 2161 * for codec. This function provides an API to select the clock source for a 2162 * set of filters specified by the mask. And the codec driver will turn on ASRC 2163 * for these filters if ASRC is selected as their clock source. 2164 */ 2165 int rt5663_sel_asrc_clk_src(struct snd_soc_component *component, 2166 unsigned int filter_mask, unsigned int clk_src) 2167 { 2168 struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component); 2169 unsigned int asrc2_mask = 0; 2170 unsigned int asrc2_value = 0; 2171 unsigned int asrc3_mask = 0; 2172 unsigned int asrc3_value = 0; 2173 2174 switch (clk_src) { 2175 case RT5663_CLK_SEL_SYS: 2176 case RT5663_CLK_SEL_I2S1_ASRC: 2177 break; 2178 2179 default: 2180 return -EINVAL; 2181 } 2182 2183 if (filter_mask & RT5663_DA_STEREO_FILTER) { 2184 asrc2_mask |= RT5663_DA_STO1_TRACK_MASK; 2185 asrc2_value |= clk_src << RT5663_DA_STO1_TRACK_SHIFT; 2186 } 2187 2188 if (filter_mask & RT5663_AD_STEREO_FILTER) { 2189 switch (rt5663->codec_ver) { 2190 case CODEC_VER_1: 2191 asrc3_mask |= RT5663_V2_AD_STO1_TRACK_MASK; 2192 asrc3_value |= clk_src << RT5663_V2_AD_STO1_TRACK_SHIFT; 2193 break; 2194 case CODEC_VER_0: 2195 asrc2_mask |= RT5663_AD_STO1_TRACK_MASK; 2196 asrc2_value |= clk_src << RT5663_AD_STO1_TRACK_SHIFT; 2197 break; 2198 default: 2199 dev_err(component->dev, "Unknown CODEC Version\n"); 2200 } 2201 } 2202 2203 if (asrc2_mask) 2204 snd_soc_component_update_bits(component, RT5663_ASRC_2, asrc2_mask, 2205 asrc2_value); 2206 2207 if (asrc3_mask) 2208 snd_soc_component_update_bits(component, RT5663_ASRC_3, asrc3_mask, 2209 asrc3_value); 2210 2211 return 0; 2212 } 2213 EXPORT_SYMBOL_GPL(rt5663_sel_asrc_clk_src); 2214 2215 /* Analog Mixer */ 2216 static const struct snd_kcontrol_new rt5663_recmix1l[] = { 2217 SOC_DAPM_SINGLE("BST2 Switch", RT5663_RECMIX1L, 2218 RT5663_RECMIX1L_BST2_SHIFT, 1, 1), 2219 SOC_DAPM_SINGLE("BST1 CBJ Switch", RT5663_RECMIX1L, 2220 RT5663_RECMIX1L_BST1_CBJ_SHIFT, 1, 1), 2221 }; 2222 2223 static const struct snd_kcontrol_new rt5663_recmix1r[] = { 2224 SOC_DAPM_SINGLE("BST2 Switch", RT5663_RECMIX1R, 2225 RT5663_RECMIX1R_BST2_SHIFT, 1, 1), 2226 }; 2227 2228 /* Digital Mixer */ 2229 static const struct snd_kcontrol_new rt5663_sto1_adc_l_mix[] = { 2230 SOC_DAPM_SINGLE("ADC1 Switch", RT5663_STO1_ADC_MIXER, 2231 RT5663_M_STO1_ADC_L1_SHIFT, 1, 1), 2232 SOC_DAPM_SINGLE("ADC2 Switch", RT5663_STO1_ADC_MIXER, 2233 RT5663_M_STO1_ADC_L2_SHIFT, 1, 1), 2234 }; 2235 2236 static const struct snd_kcontrol_new rt5663_sto1_adc_r_mix[] = { 2237 SOC_DAPM_SINGLE("ADC1 Switch", RT5663_STO1_ADC_MIXER, 2238 RT5663_M_STO1_ADC_R1_SHIFT, 1, 1), 2239 SOC_DAPM_SINGLE("ADC2 Switch", RT5663_STO1_ADC_MIXER, 2240 RT5663_M_STO1_ADC_R2_SHIFT, 1, 1), 2241 }; 2242 2243 static const struct snd_kcontrol_new rt5663_adda_l_mix[] = { 2244 SOC_DAPM_SINGLE("ADC L Switch", RT5663_AD_DA_MIXER, 2245 RT5663_M_ADCMIX_L_SHIFT, 1, 1), 2246 SOC_DAPM_SINGLE("DAC L Switch", RT5663_AD_DA_MIXER, 2247 RT5663_M_DAC1_L_SHIFT, 1, 1), 2248 }; 2249 2250 static const struct snd_kcontrol_new rt5663_adda_r_mix[] = { 2251 SOC_DAPM_SINGLE("ADC R Switch", RT5663_AD_DA_MIXER, 2252 RT5663_M_ADCMIX_R_SHIFT, 1, 1), 2253 SOC_DAPM_SINGLE("DAC R Switch", RT5663_AD_DA_MIXER, 2254 RT5663_M_DAC1_R_SHIFT, 1, 1), 2255 }; 2256 2257 static const struct snd_kcontrol_new rt5663_sto1_dac_l_mix[] = { 2258 SOC_DAPM_SINGLE("DAC L Switch", RT5663_STO_DAC_MIXER, 2259 RT5663_M_DAC_L1_STO_L_SHIFT, 1, 1), 2260 }; 2261 2262 static const struct snd_kcontrol_new rt5663_sto1_dac_r_mix[] = { 2263 SOC_DAPM_SINGLE("DAC R Switch", RT5663_STO_DAC_MIXER, 2264 RT5663_M_DAC_R1_STO_R_SHIFT, 1, 1), 2265 }; 2266 2267 /* Out Switch */ 2268 static const struct snd_kcontrol_new rt5663_hpo_switch = 2269 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5663_HP_AMP_2, 2270 RT5663_EN_DAC_HPO_SHIFT, 1, 0); 2271 2272 /* Stereo ADC source */ 2273 static const char * const rt5663_sto1_adc_src[] = { 2274 "ADC L", "ADC R" 2275 }; 2276 2277 static SOC_ENUM_SINGLE_DECL(rt5663_sto1_adcl_enum, RT5663_STO1_ADC_MIXER, 2278 RT5663_STO1_ADC_L_SRC_SHIFT, rt5663_sto1_adc_src); 2279 2280 static const struct snd_kcontrol_new rt5663_sto1_adcl_mux = 2281 SOC_DAPM_ENUM("STO1 ADC L Mux", rt5663_sto1_adcl_enum); 2282 2283 static SOC_ENUM_SINGLE_DECL(rt5663_sto1_adcr_enum, RT5663_STO1_ADC_MIXER, 2284 RT5663_STO1_ADC_R_SRC_SHIFT, rt5663_sto1_adc_src); 2285 2286 static const struct snd_kcontrol_new rt5663_sto1_adcr_mux = 2287 SOC_DAPM_ENUM("STO1 ADC R Mux", rt5663_sto1_adcr_enum); 2288 2289 /* RT5663: Analog DACL1 input source */ 2290 static const char * const rt5663_alg_dacl_src[] = { 2291 "DAC L", "STO DAC MIXL" 2292 }; 2293 2294 static SOC_ENUM_SINGLE_DECL(rt5663_alg_dacl_enum, RT5663_BYPASS_STO_DAC, 2295 RT5663_DACL1_SRC_SHIFT, rt5663_alg_dacl_src); 2296 2297 static const struct snd_kcontrol_new rt5663_alg_dacl_mux = 2298 SOC_DAPM_ENUM("DAC L Mux", rt5663_alg_dacl_enum); 2299 2300 /* RT5663: Analog DACR1 input source */ 2301 static const char * const rt5663_alg_dacr_src[] = { 2302 "DAC R", "STO DAC MIXR" 2303 }; 2304 2305 static SOC_ENUM_SINGLE_DECL(rt5663_alg_dacr_enum, RT5663_BYPASS_STO_DAC, 2306 RT5663_DACR1_SRC_SHIFT, rt5663_alg_dacr_src); 2307 2308 static const struct snd_kcontrol_new rt5663_alg_dacr_mux = 2309 SOC_DAPM_ENUM("DAC R Mux", rt5663_alg_dacr_enum); 2310 2311 static int rt5663_hp_event(struct snd_soc_dapm_widget *w, 2312 struct snd_kcontrol *kcontrol, int event) 2313 { 2314 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 2315 struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component); 2316 2317 switch (event) { 2318 case SND_SOC_DAPM_POST_PMU: 2319 if (rt5663->codec_ver == CODEC_VER_1) { 2320 snd_soc_component_update_bits(component, RT5663_HP_CHARGE_PUMP_1, 2321 RT5663_SEL_PM_HP_SHIFT, RT5663_SEL_PM_HP_HIGH); 2322 snd_soc_component_update_bits(component, RT5663_HP_LOGIC_2, 2323 RT5663_HP_SIG_SRC1_MASK, 2324 RT5663_HP_SIG_SRC1_SILENCE); 2325 } else { 2326 snd_soc_component_update_bits(component, 2327 RT5663_DACREF_LDO, 0x3e0e, 0x3a0a); 2328 snd_soc_component_write(component, RT5663_DEPOP_2, 0x3003); 2329 snd_soc_component_update_bits(component, RT5663_HP_CHARGE_PUMP_1, 2330 RT5663_OVCD_HP_MASK, RT5663_OVCD_HP_DIS); 2331 snd_soc_component_write(component, RT5663_HP_CHARGE_PUMP_2, 0x1371); 2332 snd_soc_component_write(component, RT5663_HP_BIAS, 0xabba); 2333 snd_soc_component_write(component, RT5663_CHARGE_PUMP_1, 0x2224); 2334 snd_soc_component_write(component, RT5663_ANA_BIAS_CUR_1, 0x7766); 2335 snd_soc_component_write(component, RT5663_HP_BIAS, 0xafaa); 2336 snd_soc_component_write(component, RT5663_CHARGE_PUMP_2, 0x7777); 2337 snd_soc_component_update_bits(component, RT5663_STO_DRE_1, 0x8000, 2338 0x8000); 2339 snd_soc_component_update_bits(component, RT5663_DEPOP_1, 0x3000, 2340 0x3000); 2341 snd_soc_component_update_bits(component, 2342 RT5663_DIG_VOL_ZCD, 0x00c0, 0x0080); 2343 } 2344 break; 2345 2346 case SND_SOC_DAPM_PRE_PMD: 2347 if (rt5663->codec_ver == CODEC_VER_1) { 2348 snd_soc_component_update_bits(component, RT5663_HP_LOGIC_2, 2349 RT5663_HP_SIG_SRC1_MASK, 2350 RT5663_HP_SIG_SRC1_REG); 2351 } else { 2352 snd_soc_component_update_bits(component, RT5663_DEPOP_1, 0x3000, 0x0); 2353 snd_soc_component_update_bits(component, RT5663_HP_CHARGE_PUMP_1, 2354 RT5663_OVCD_HP_MASK, RT5663_OVCD_HP_EN); 2355 snd_soc_component_update_bits(component, 2356 RT5663_DACREF_LDO, 0x3e0e, 0); 2357 snd_soc_component_update_bits(component, 2358 RT5663_DIG_VOL_ZCD, 0x00c0, 0); 2359 } 2360 break; 2361 2362 default: 2363 return 0; 2364 } 2365 2366 return 0; 2367 } 2368 2369 static int rt5663_charge_pump_event(struct snd_soc_dapm_widget *w, 2370 struct snd_kcontrol *kcontrol, int event) 2371 { 2372 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 2373 struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component); 2374 2375 switch (event) { 2376 case SND_SOC_DAPM_PRE_PMU: 2377 if (rt5663->codec_ver == CODEC_VER_0) { 2378 snd_soc_component_update_bits(component, RT5663_DEPOP_1, 0x0030, 2379 0x0030); 2380 snd_soc_component_update_bits(component, RT5663_DEPOP_1, 0x0003, 2381 0x0003); 2382 } 2383 break; 2384 2385 case SND_SOC_DAPM_POST_PMD: 2386 if (rt5663->codec_ver == CODEC_VER_0) { 2387 snd_soc_component_update_bits(component, RT5663_DEPOP_1, 0x0003, 0); 2388 snd_soc_component_update_bits(component, RT5663_DEPOP_1, 0x0030, 0); 2389 } 2390 break; 2391 2392 default: 2393 return 0; 2394 } 2395 2396 return 0; 2397 } 2398 2399 static int rt5663_bst2_power(struct snd_soc_dapm_widget *w, 2400 struct snd_kcontrol *kcontrol, int event) 2401 { 2402 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 2403 2404 switch (event) { 2405 case SND_SOC_DAPM_POST_PMU: 2406 snd_soc_component_update_bits(component, RT5663_PWR_ANLG_2, 2407 RT5663_PWR_BST2_MASK | RT5663_PWR_BST2_OP_MASK, 2408 RT5663_PWR_BST2 | RT5663_PWR_BST2_OP); 2409 break; 2410 2411 case SND_SOC_DAPM_PRE_PMD: 2412 snd_soc_component_update_bits(component, RT5663_PWR_ANLG_2, 2413 RT5663_PWR_BST2_MASK | RT5663_PWR_BST2_OP_MASK, 0); 2414 break; 2415 2416 default: 2417 return 0; 2418 } 2419 2420 return 0; 2421 } 2422 2423 static int rt5663_pre_div_power(struct snd_soc_dapm_widget *w, 2424 struct snd_kcontrol *kcontrol, int event) 2425 { 2426 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 2427 2428 switch (event) { 2429 case SND_SOC_DAPM_POST_PMU: 2430 snd_soc_component_write(component, RT5663_PRE_DIV_GATING_1, 0xff00); 2431 snd_soc_component_write(component, RT5663_PRE_DIV_GATING_2, 0xfffc); 2432 break; 2433 2434 case SND_SOC_DAPM_PRE_PMD: 2435 snd_soc_component_write(component, RT5663_PRE_DIV_GATING_1, 0x0000); 2436 snd_soc_component_write(component, RT5663_PRE_DIV_GATING_2, 0x0000); 2437 break; 2438 2439 default: 2440 return 0; 2441 } 2442 2443 return 0; 2444 } 2445 2446 static const struct snd_soc_dapm_widget rt5663_dapm_widgets[] = { 2447 SND_SOC_DAPM_SUPPLY("PLL", RT5663_PWR_ANLG_3, RT5663_PWR_PLL_SHIFT, 0, 2448 NULL, 0), 2449 2450 /* micbias */ 2451 SND_SOC_DAPM_MICBIAS("MICBIAS1", RT5663_PWR_ANLG_2, 2452 RT5663_PWR_MB1_SHIFT, 0), 2453 SND_SOC_DAPM_MICBIAS("MICBIAS2", RT5663_PWR_ANLG_2, 2454 RT5663_PWR_MB2_SHIFT, 0), 2455 2456 /* Input Lines */ 2457 SND_SOC_DAPM_INPUT("IN1P"), 2458 SND_SOC_DAPM_INPUT("IN1N"), 2459 2460 /* REC Mixer Power */ 2461 SND_SOC_DAPM_SUPPLY("RECMIX1L Power", RT5663_PWR_ANLG_2, 2462 RT5663_PWR_RECMIX1_SHIFT, 0, NULL, 0), 2463 2464 /* ADCs */ 2465 SND_SOC_DAPM_ADC("ADC L", NULL, SND_SOC_NOPM, 0, 0), 2466 SND_SOC_DAPM_SUPPLY("ADC L Power", RT5663_PWR_DIG_1, 2467 RT5663_PWR_ADC_L1_SHIFT, 0, NULL, 0), 2468 SND_SOC_DAPM_SUPPLY("ADC Clock", RT5663_CHOP_ADC, 2469 RT5663_CKGEN_ADCC_SHIFT, 0, NULL, 0), 2470 2471 /* ADC Mixer */ 2472 SND_SOC_DAPM_MIXER("STO1 ADC MIXL", SND_SOC_NOPM, 2473 0, 0, rt5663_sto1_adc_l_mix, 2474 ARRAY_SIZE(rt5663_sto1_adc_l_mix)), 2475 2476 /* ADC Filter Power */ 2477 SND_SOC_DAPM_SUPPLY("STO1 ADC Filter", RT5663_PWR_DIG_2, 2478 RT5663_PWR_ADC_S1F_SHIFT, 0, NULL, 0), 2479 2480 /* Digital Interface */ 2481 SND_SOC_DAPM_SUPPLY("I2S", RT5663_PWR_DIG_1, RT5663_PWR_I2S1_SHIFT, 0, 2482 NULL, 0), 2483 SND_SOC_DAPM_PGA("IF DAC", SND_SOC_NOPM, 0, 0, NULL, 0), 2484 SND_SOC_DAPM_PGA("IF1 DAC1 L", SND_SOC_NOPM, 0, 0, NULL, 0), 2485 SND_SOC_DAPM_PGA("IF1 DAC1 R", SND_SOC_NOPM, 0, 0, NULL, 0), 2486 SND_SOC_DAPM_PGA("IF1 ADC1", SND_SOC_NOPM, 0, 0, NULL, 0), 2487 SND_SOC_DAPM_PGA("IF ADC", SND_SOC_NOPM, 0, 0, NULL, 0), 2488 2489 /* Audio Interface */ 2490 SND_SOC_DAPM_AIF_IN("AIFRX", "AIF Playback", 0, SND_SOC_NOPM, 0, 0), 2491 SND_SOC_DAPM_AIF_OUT("AIFTX", "AIF Capture", 0, SND_SOC_NOPM, 0, 0), 2492 2493 /* DAC mixer before sound effect */ 2494 SND_SOC_DAPM_MIXER("ADDA MIXL", SND_SOC_NOPM, 0, 0, rt5663_adda_l_mix, 2495 ARRAY_SIZE(rt5663_adda_l_mix)), 2496 SND_SOC_DAPM_MIXER("ADDA MIXR", SND_SOC_NOPM, 0, 0, rt5663_adda_r_mix, 2497 ARRAY_SIZE(rt5663_adda_r_mix)), 2498 SND_SOC_DAPM_PGA("DAC L1", SND_SOC_NOPM, 0, 0, NULL, 0), 2499 SND_SOC_DAPM_PGA("DAC R1", SND_SOC_NOPM, 0, 0, NULL, 0), 2500 2501 /* DAC Mixer */ 2502 SND_SOC_DAPM_SUPPLY("STO1 DAC Filter", RT5663_PWR_DIG_2, 2503 RT5663_PWR_DAC_S1F_SHIFT, 0, NULL, 0), 2504 SND_SOC_DAPM_MIXER("STO1 DAC MIXL", SND_SOC_NOPM, 0, 0, 2505 rt5663_sto1_dac_l_mix, ARRAY_SIZE(rt5663_sto1_dac_l_mix)), 2506 SND_SOC_DAPM_MIXER("STO1 DAC MIXR", SND_SOC_NOPM, 0, 0, 2507 rt5663_sto1_dac_r_mix, ARRAY_SIZE(rt5663_sto1_dac_r_mix)), 2508 2509 /* DACs */ 2510 SND_SOC_DAPM_SUPPLY("STO1 DAC L Power", RT5663_PWR_DIG_1, 2511 RT5663_PWR_DAC_L1_SHIFT, 0, NULL, 0), 2512 SND_SOC_DAPM_SUPPLY("STO1 DAC R Power", RT5663_PWR_DIG_1, 2513 RT5663_PWR_DAC_R1_SHIFT, 0, NULL, 0), 2514 SND_SOC_DAPM_DAC("DAC L", NULL, SND_SOC_NOPM, 0, 0), 2515 SND_SOC_DAPM_DAC("DAC R", NULL, SND_SOC_NOPM, 0, 0), 2516 2517 /* Headphone*/ 2518 SND_SOC_DAPM_SUPPLY("HP Charge Pump", SND_SOC_NOPM, 0, 0, 2519 rt5663_charge_pump_event, SND_SOC_DAPM_PRE_PMU | 2520 SND_SOC_DAPM_POST_PMD), 2521 SND_SOC_DAPM_PGA_S("HP Amp", 1, SND_SOC_NOPM, 0, 0, rt5663_hp_event, 2522 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU), 2523 2524 /* Output Lines */ 2525 SND_SOC_DAPM_OUTPUT("HPOL"), 2526 SND_SOC_DAPM_OUTPUT("HPOR"), 2527 }; 2528 2529 static const struct snd_soc_dapm_widget rt5663_v2_specific_dapm_widgets[] = { 2530 SND_SOC_DAPM_SUPPLY("LDO2", RT5663_PWR_ANLG_3, 2531 RT5663_PWR_LDO2_SHIFT, 0, NULL, 0), 2532 SND_SOC_DAPM_SUPPLY("Mic Det Power", RT5663_PWR_VOL, 2533 RT5663_V2_PWR_MIC_DET_SHIFT, 0, NULL, 0), 2534 SND_SOC_DAPM_SUPPLY("LDO DAC", RT5663_PWR_DIG_1, 2535 RT5663_PWR_LDO_DACREF_SHIFT, 0, NULL, 0), 2536 2537 /* ASRC */ 2538 SND_SOC_DAPM_SUPPLY("I2S ASRC", RT5663_ASRC_1, 2539 RT5663_I2S1_ASRC_SHIFT, 0, NULL, 0), 2540 SND_SOC_DAPM_SUPPLY("DAC ASRC", RT5663_ASRC_1, 2541 RT5663_DAC_STO1_ASRC_SHIFT, 0, NULL, 0), 2542 SND_SOC_DAPM_SUPPLY("ADC ASRC", RT5663_ASRC_1, 2543 RT5663_ADC_STO1_ASRC_SHIFT, 0, NULL, 0), 2544 2545 /* Input Lines */ 2546 SND_SOC_DAPM_INPUT("IN2P"), 2547 SND_SOC_DAPM_INPUT("IN2N"), 2548 2549 /* Boost */ 2550 SND_SOC_DAPM_PGA("BST1 CBJ", SND_SOC_NOPM, 0, 0, NULL, 0), 2551 SND_SOC_DAPM_SUPPLY("CBJ Power", RT5663_PWR_ANLG_3, 2552 RT5663_PWR_CBJ_SHIFT, 0, NULL, 0), 2553 SND_SOC_DAPM_PGA("BST2", SND_SOC_NOPM, 0, 0, NULL, 0), 2554 SND_SOC_DAPM_SUPPLY("BST2 Power", SND_SOC_NOPM, 0, 0, 2555 rt5663_bst2_power, SND_SOC_DAPM_PRE_PMD | 2556 SND_SOC_DAPM_POST_PMU), 2557 2558 /* REC Mixer */ 2559 SND_SOC_DAPM_MIXER("RECMIX1L", SND_SOC_NOPM, 0, 0, rt5663_recmix1l, 2560 ARRAY_SIZE(rt5663_recmix1l)), 2561 SND_SOC_DAPM_MIXER("RECMIX1R", SND_SOC_NOPM, 0, 0, rt5663_recmix1r, 2562 ARRAY_SIZE(rt5663_recmix1r)), 2563 SND_SOC_DAPM_SUPPLY("RECMIX1R Power", RT5663_PWR_ANLG_2, 2564 RT5663_PWR_RECMIX2_SHIFT, 0, NULL, 0), 2565 2566 /* ADC */ 2567 SND_SOC_DAPM_ADC("ADC R", NULL, SND_SOC_NOPM, 0, 0), 2568 SND_SOC_DAPM_SUPPLY("ADC R Power", RT5663_PWR_DIG_1, 2569 RT5663_PWR_ADC_R1_SHIFT, 0, NULL, 0), 2570 2571 /* ADC Mux */ 2572 SND_SOC_DAPM_PGA("STO1 ADC L1", RT5663_STO1_ADC_MIXER, 2573 RT5663_STO1_ADC_L1_SRC_SHIFT, 0, NULL, 0), 2574 SND_SOC_DAPM_PGA("STO1 ADC R1", RT5663_STO1_ADC_MIXER, 2575 RT5663_STO1_ADC_R1_SRC_SHIFT, 0, NULL, 0), 2576 SND_SOC_DAPM_PGA("STO1 ADC L2", RT5663_STO1_ADC_MIXER, 2577 RT5663_STO1_ADC_L2_SRC_SHIFT, 1, NULL, 0), 2578 SND_SOC_DAPM_PGA("STO1 ADC R2", RT5663_STO1_ADC_MIXER, 2579 RT5663_STO1_ADC_R2_SRC_SHIFT, 1, NULL, 0), 2580 2581 SND_SOC_DAPM_MUX("STO1 ADC L Mux", SND_SOC_NOPM, 0, 0, 2582 &rt5663_sto1_adcl_mux), 2583 SND_SOC_DAPM_MUX("STO1 ADC R Mux", SND_SOC_NOPM, 0, 0, 2584 &rt5663_sto1_adcr_mux), 2585 2586 /* ADC Mix */ 2587 SND_SOC_DAPM_MIXER("STO1 ADC MIXR", SND_SOC_NOPM, 0, 0, 2588 rt5663_sto1_adc_r_mix, ARRAY_SIZE(rt5663_sto1_adc_r_mix)), 2589 2590 /* Analog DAC Clock */ 2591 SND_SOC_DAPM_SUPPLY("DAC Clock", RT5663_CHOP_DAC_L, 2592 RT5663_CKGEN_DAC1_SHIFT, 0, NULL, 0), 2593 2594 /* Headphone out */ 2595 SND_SOC_DAPM_SWITCH("HPO Playback", SND_SOC_NOPM, 0, 0, 2596 &rt5663_hpo_switch), 2597 }; 2598 2599 static const struct snd_soc_dapm_widget rt5663_specific_dapm_widgets[] = { 2600 /* System Clock Pre Divider Gating */ 2601 SND_SOC_DAPM_SUPPLY("Pre Div Power", SND_SOC_NOPM, 0, 0, 2602 rt5663_pre_div_power, SND_SOC_DAPM_POST_PMU | 2603 SND_SOC_DAPM_PRE_PMD), 2604 2605 /* LDO */ 2606 SND_SOC_DAPM_SUPPLY("LDO ADC", RT5663_PWR_DIG_1, 2607 RT5663_PWR_LDO_DACREF_SHIFT, 0, NULL, 0), 2608 2609 /* ASRC */ 2610 SND_SOC_DAPM_SUPPLY("I2S ASRC", RT5663_ASRC_1, 2611 RT5663_I2S1_ASRC_SHIFT, 0, NULL, 0), 2612 SND_SOC_DAPM_SUPPLY("DAC ASRC", RT5663_ASRC_1, 2613 RT5663_DAC_STO1_ASRC_SHIFT, 0, NULL, 0), 2614 SND_SOC_DAPM_SUPPLY("ADC ASRC", RT5663_ASRC_1, 2615 RT5663_ADC_STO1_ASRC_SHIFT, 0, NULL, 0), 2616 2617 /* Boost */ 2618 SND_SOC_DAPM_PGA("BST1", SND_SOC_NOPM, 0, 0, NULL, 0), 2619 2620 /* STO ADC */ 2621 SND_SOC_DAPM_PGA("STO1 ADC L1", SND_SOC_NOPM, 0, 0, NULL, 0), 2622 SND_SOC_DAPM_PGA("STO1 ADC L2", SND_SOC_NOPM, 0, 0, NULL, 0), 2623 2624 /* Analog DAC source */ 2625 SND_SOC_DAPM_MUX("DAC L Mux", SND_SOC_NOPM, 0, 0, &rt5663_alg_dacl_mux), 2626 SND_SOC_DAPM_MUX("DAC R Mux", SND_SOC_NOPM, 0, 0, &rt5663_alg_dacr_mux), 2627 }; 2628 2629 static const struct snd_soc_dapm_route rt5663_dapm_routes[] = { 2630 /* PLL */ 2631 { "I2S", NULL, "PLL", rt5663_is_sys_clk_from_pll }, 2632 2633 /* ASRC */ 2634 { "STO1 ADC Filter", NULL, "ADC ASRC", rt5663_is_using_asrc }, 2635 { "STO1 DAC Filter", NULL, "DAC ASRC", rt5663_is_using_asrc }, 2636 { "I2S", NULL, "I2S ASRC", rt5663_i2s_use_asrc }, 2637 2638 { "ADC L", NULL, "ADC L Power" }, 2639 { "ADC L", NULL, "ADC Clock" }, 2640 2641 { "STO1 ADC L2", NULL, "STO1 DAC MIXL" }, 2642 2643 { "STO1 ADC MIXL", "ADC1 Switch", "STO1 ADC L1" }, 2644 { "STO1 ADC MIXL", "ADC2 Switch", "STO1 ADC L2" }, 2645 { "STO1 ADC MIXL", NULL, "STO1 ADC Filter" }, 2646 2647 { "IF1 ADC1", NULL, "STO1 ADC MIXL" }, 2648 { "IF ADC", NULL, "IF1 ADC1" }, 2649 { "AIFTX", NULL, "IF ADC" }, 2650 { "AIFTX", NULL, "I2S" }, 2651 2652 { "AIFRX", NULL, "I2S" }, 2653 { "IF DAC", NULL, "AIFRX" }, 2654 { "IF1 DAC1 L", NULL, "IF DAC" }, 2655 { "IF1 DAC1 R", NULL, "IF DAC" }, 2656 2657 { "ADDA MIXL", "ADC L Switch", "STO1 ADC MIXL" }, 2658 { "ADDA MIXL", "DAC L Switch", "IF1 DAC1 L" }, 2659 { "ADDA MIXL", NULL, "STO1 DAC Filter" }, 2660 { "ADDA MIXL", NULL, "STO1 DAC L Power" }, 2661 { "ADDA MIXR", "DAC R Switch", "IF1 DAC1 R" }, 2662 { "ADDA MIXR", NULL, "STO1 DAC Filter" }, 2663 { "ADDA MIXR", NULL, "STO1 DAC R Power" }, 2664 2665 { "DAC L1", NULL, "ADDA MIXL" }, 2666 { "DAC R1", NULL, "ADDA MIXR" }, 2667 2668 { "STO1 DAC MIXL", "DAC L Switch", "DAC L1" }, 2669 { "STO1 DAC MIXL", NULL, "STO1 DAC L Power" }, 2670 { "STO1 DAC MIXL", NULL, "STO1 DAC Filter" }, 2671 { "STO1 DAC MIXR", "DAC R Switch", "DAC R1" }, 2672 { "STO1 DAC MIXR", NULL, "STO1 DAC R Power" }, 2673 { "STO1 DAC MIXR", NULL, "STO1 DAC Filter" }, 2674 2675 { "HP Amp", NULL, "HP Charge Pump" }, 2676 { "HP Amp", NULL, "DAC L" }, 2677 { "HP Amp", NULL, "DAC R" }, 2678 }; 2679 2680 static const struct snd_soc_dapm_route rt5663_v2_specific_dapm_routes[] = { 2681 { "MICBIAS1", NULL, "LDO2" }, 2682 { "MICBIAS2", NULL, "LDO2" }, 2683 2684 { "BST1 CBJ", NULL, "IN1P" }, 2685 { "BST1 CBJ", NULL, "IN1N" }, 2686 { "BST1 CBJ", NULL, "CBJ Power" }, 2687 2688 { "BST2", NULL, "IN2P" }, 2689 { "BST2", NULL, "IN2N" }, 2690 { "BST2", NULL, "BST2 Power" }, 2691 2692 { "RECMIX1L", "BST2 Switch", "BST2" }, 2693 { "RECMIX1L", "BST1 CBJ Switch", "BST1 CBJ" }, 2694 { "RECMIX1L", NULL, "RECMIX1L Power" }, 2695 { "RECMIX1R", "BST2 Switch", "BST2" }, 2696 { "RECMIX1R", NULL, "RECMIX1R Power" }, 2697 2698 { "ADC L", NULL, "RECMIX1L" }, 2699 { "ADC R", NULL, "RECMIX1R" }, 2700 { "ADC R", NULL, "ADC R Power" }, 2701 { "ADC R", NULL, "ADC Clock" }, 2702 2703 { "STO1 ADC L Mux", "ADC L", "ADC L" }, 2704 { "STO1 ADC L Mux", "ADC R", "ADC R" }, 2705 { "STO1 ADC L1", NULL, "STO1 ADC L Mux" }, 2706 2707 { "STO1 ADC R Mux", "ADC L", "ADC L" }, 2708 { "STO1 ADC R Mux", "ADC R", "ADC R" }, 2709 { "STO1 ADC R1", NULL, "STO1 ADC R Mux" }, 2710 { "STO1 ADC R2", NULL, "STO1 DAC MIXR" }, 2711 2712 { "STO1 ADC MIXR", "ADC1 Switch", "STO1 ADC R1" }, 2713 { "STO1 ADC MIXR", "ADC2 Switch", "STO1 ADC R2" }, 2714 { "STO1 ADC MIXR", NULL, "STO1 ADC Filter" }, 2715 2716 { "IF1 ADC1", NULL, "STO1 ADC MIXR" }, 2717 2718 { "ADDA MIXR", "ADC R Switch", "STO1 ADC MIXR" }, 2719 2720 { "DAC L", NULL, "STO1 DAC MIXL" }, 2721 { "DAC L", NULL, "LDO DAC" }, 2722 { "DAC L", NULL, "DAC Clock" }, 2723 { "DAC R", NULL, "STO1 DAC MIXR" }, 2724 { "DAC R", NULL, "LDO DAC" }, 2725 { "DAC R", NULL, "DAC Clock" }, 2726 2727 { "HPO Playback", "Switch", "HP Amp" }, 2728 { "HPOL", NULL, "HPO Playback" }, 2729 { "HPOR", NULL, "HPO Playback" }, 2730 }; 2731 2732 static const struct snd_soc_dapm_route rt5663_specific_dapm_routes[] = { 2733 { "I2S", NULL, "Pre Div Power" }, 2734 2735 { "BST1", NULL, "IN1P" }, 2736 { "BST1", NULL, "IN1N" }, 2737 { "BST1", NULL, "RECMIX1L Power" }, 2738 2739 { "ADC L", NULL, "BST1" }, 2740 2741 { "STO1 ADC L1", NULL, "ADC L" }, 2742 2743 { "DAC L Mux", "DAC L", "DAC L1" }, 2744 { "DAC L Mux", "STO DAC MIXL", "STO1 DAC MIXL" }, 2745 { "DAC R Mux", "DAC R", "DAC R1"}, 2746 { "DAC R Mux", "STO DAC MIXR", "STO1 DAC MIXR" }, 2747 2748 { "DAC L", NULL, "DAC L Mux" }, 2749 { "DAC R", NULL, "DAC R Mux" }, 2750 2751 { "HPOL", NULL, "HP Amp" }, 2752 { "HPOR", NULL, "HP Amp" }, 2753 }; 2754 2755 static int rt5663_hw_params(struct snd_pcm_substream *substream, 2756 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) 2757 { 2758 struct snd_soc_component *component = dai->component; 2759 struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component); 2760 unsigned int val_len = 0; 2761 int pre_div; 2762 2763 rt5663->lrck = params_rate(params); 2764 2765 dev_dbg(dai->dev, "bclk is %dHz and sysclk is %dHz\n", 2766 rt5663->lrck, rt5663->sysclk); 2767 2768 pre_div = rl6231_get_clk_info(rt5663->sysclk, rt5663->lrck); 2769 if (pre_div < 0) { 2770 dev_err(component->dev, "Unsupported clock setting %d for DAI %d\n", 2771 rt5663->lrck, dai->id); 2772 return -EINVAL; 2773 } 2774 2775 dev_dbg(dai->dev, "pre_div is %d for iis %d\n", pre_div, dai->id); 2776 2777 switch (params_width(params)) { 2778 case 8: 2779 val_len = RT5663_I2S_DL_8; 2780 break; 2781 case 16: 2782 val_len = RT5663_I2S_DL_16; 2783 break; 2784 case 20: 2785 val_len = RT5663_I2S_DL_20; 2786 break; 2787 case 24: 2788 val_len = RT5663_I2S_DL_24; 2789 break; 2790 default: 2791 return -EINVAL; 2792 } 2793 2794 snd_soc_component_update_bits(component, RT5663_I2S1_SDP, 2795 RT5663_I2S_DL_MASK, val_len); 2796 2797 snd_soc_component_update_bits(component, RT5663_ADDA_CLK_1, 2798 RT5663_I2S_PD1_MASK, pre_div << RT5663_I2S_PD1_SHIFT); 2799 2800 return 0; 2801 } 2802 2803 static int rt5663_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) 2804 { 2805 struct snd_soc_component *component = dai->component; 2806 unsigned int reg_val = 0; 2807 2808 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 2809 case SND_SOC_DAIFMT_CBM_CFM: 2810 break; 2811 case SND_SOC_DAIFMT_CBS_CFS: 2812 reg_val |= RT5663_I2S_MS_S; 2813 break; 2814 default: 2815 return -EINVAL; 2816 } 2817 2818 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 2819 case SND_SOC_DAIFMT_NB_NF: 2820 break; 2821 case SND_SOC_DAIFMT_IB_NF: 2822 reg_val |= RT5663_I2S_BP_INV; 2823 break; 2824 default: 2825 return -EINVAL; 2826 } 2827 2828 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 2829 case SND_SOC_DAIFMT_I2S: 2830 break; 2831 case SND_SOC_DAIFMT_LEFT_J: 2832 reg_val |= RT5663_I2S_DF_LEFT; 2833 break; 2834 case SND_SOC_DAIFMT_DSP_A: 2835 reg_val |= RT5663_I2S_DF_PCM_A; 2836 break; 2837 case SND_SOC_DAIFMT_DSP_B: 2838 reg_val |= RT5663_I2S_DF_PCM_B; 2839 break; 2840 default: 2841 return -EINVAL; 2842 } 2843 2844 snd_soc_component_update_bits(component, RT5663_I2S1_SDP, RT5663_I2S_MS_MASK | 2845 RT5663_I2S_BP_MASK | RT5663_I2S_DF_MASK, reg_val); 2846 2847 return 0; 2848 } 2849 2850 static int rt5663_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id, 2851 unsigned int freq, int dir) 2852 { 2853 struct snd_soc_component *component = dai->component; 2854 struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component); 2855 unsigned int reg_val = 0; 2856 2857 if (freq == rt5663->sysclk && clk_id == rt5663->sysclk_src) 2858 return 0; 2859 2860 switch (clk_id) { 2861 case RT5663_SCLK_S_MCLK: 2862 reg_val |= RT5663_SCLK_SRC_MCLK; 2863 break; 2864 case RT5663_SCLK_S_PLL1: 2865 reg_val |= RT5663_SCLK_SRC_PLL1; 2866 break; 2867 case RT5663_SCLK_S_RCCLK: 2868 reg_val |= RT5663_SCLK_SRC_RCCLK; 2869 break; 2870 default: 2871 dev_err(component->dev, "Invalid clock id (%d)\n", clk_id); 2872 return -EINVAL; 2873 } 2874 snd_soc_component_update_bits(component, RT5663_GLB_CLK, RT5663_SCLK_SRC_MASK, 2875 reg_val); 2876 rt5663->sysclk = freq; 2877 rt5663->sysclk_src = clk_id; 2878 2879 dev_dbg(component->dev, "Sysclk is %dHz and clock id is %d\n", 2880 freq, clk_id); 2881 2882 return 0; 2883 } 2884 2885 static int rt5663_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source, 2886 unsigned int freq_in, unsigned int freq_out) 2887 { 2888 struct snd_soc_component *component = dai->component; 2889 struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component); 2890 struct rl6231_pll_code pll_code; 2891 int ret; 2892 int mask, shift, val; 2893 2894 if (source == rt5663->pll_src && freq_in == rt5663->pll_in && 2895 freq_out == rt5663->pll_out) 2896 return 0; 2897 2898 if (!freq_in || !freq_out) { 2899 dev_dbg(component->dev, "PLL disabled\n"); 2900 2901 rt5663->pll_in = 0; 2902 rt5663->pll_out = 0; 2903 snd_soc_component_update_bits(component, RT5663_GLB_CLK, 2904 RT5663_SCLK_SRC_MASK, RT5663_SCLK_SRC_MCLK); 2905 return 0; 2906 } 2907 2908 switch (rt5663->codec_ver) { 2909 case CODEC_VER_1: 2910 mask = RT5663_V2_PLL1_SRC_MASK; 2911 shift = RT5663_V2_PLL1_SRC_SHIFT; 2912 break; 2913 case CODEC_VER_0: 2914 mask = RT5663_PLL1_SRC_MASK; 2915 shift = RT5663_PLL1_SRC_SHIFT; 2916 break; 2917 default: 2918 dev_err(component->dev, "Unknown CODEC Version\n"); 2919 return -EINVAL; 2920 } 2921 2922 switch (source) { 2923 case RT5663_PLL1_S_MCLK: 2924 val = 0x0; 2925 break; 2926 case RT5663_PLL1_S_BCLK1: 2927 val = 0x1; 2928 break; 2929 default: 2930 dev_err(component->dev, "Unknown PLL source %d\n", source); 2931 return -EINVAL; 2932 } 2933 snd_soc_component_update_bits(component, RT5663_GLB_CLK, mask, (val << shift)); 2934 2935 ret = rl6231_pll_calc(freq_in, freq_out, &pll_code); 2936 if (ret < 0) { 2937 dev_err(component->dev, "Unsupport input clock %d\n", freq_in); 2938 return ret; 2939 } 2940 2941 dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n", pll_code.m_bp, 2942 (pll_code.m_bp ? 0 : pll_code.m_code), pll_code.n_code, 2943 pll_code.k_code); 2944 2945 snd_soc_component_write(component, RT5663_PLL_1, 2946 pll_code.n_code << RT5663_PLL_N_SHIFT | pll_code.k_code); 2947 snd_soc_component_write(component, RT5663_PLL_2, 2948 (pll_code.m_bp ? 0 : pll_code.m_code) << RT5663_PLL_M_SHIFT | 2949 pll_code.m_bp << RT5663_PLL_M_BP_SHIFT); 2950 2951 rt5663->pll_in = freq_in; 2952 rt5663->pll_out = freq_out; 2953 rt5663->pll_src = source; 2954 2955 return 0; 2956 } 2957 2958 static int rt5663_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask, 2959 unsigned int rx_mask, int slots, int slot_width) 2960 { 2961 struct snd_soc_component *component = dai->component; 2962 struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component); 2963 unsigned int val = 0, reg; 2964 2965 if (rx_mask || tx_mask) 2966 val |= RT5663_TDM_MODE_TDM; 2967 2968 switch (slots) { 2969 case 4: 2970 val |= RT5663_TDM_IN_CH_4; 2971 val |= RT5663_TDM_OUT_CH_4; 2972 break; 2973 case 6: 2974 val |= RT5663_TDM_IN_CH_6; 2975 val |= RT5663_TDM_OUT_CH_6; 2976 break; 2977 case 8: 2978 val |= RT5663_TDM_IN_CH_8; 2979 val |= RT5663_TDM_OUT_CH_8; 2980 break; 2981 case 2: 2982 break; 2983 default: 2984 return -EINVAL; 2985 } 2986 2987 switch (slot_width) { 2988 case 20: 2989 val |= RT5663_TDM_IN_LEN_20; 2990 val |= RT5663_TDM_OUT_LEN_20; 2991 break; 2992 case 24: 2993 val |= RT5663_TDM_IN_LEN_24; 2994 val |= RT5663_TDM_OUT_LEN_24; 2995 break; 2996 case 32: 2997 val |= RT5663_TDM_IN_LEN_32; 2998 val |= RT5663_TDM_OUT_LEN_32; 2999 break; 3000 case 16: 3001 break; 3002 default: 3003 return -EINVAL; 3004 } 3005 3006 switch (rt5663->codec_ver) { 3007 case CODEC_VER_1: 3008 reg = RT5663_TDM_2; 3009 break; 3010 case CODEC_VER_0: 3011 reg = RT5663_TDM_1; 3012 break; 3013 default: 3014 dev_err(component->dev, "Unknown CODEC Version\n"); 3015 return -EINVAL; 3016 } 3017 3018 snd_soc_component_update_bits(component, reg, RT5663_TDM_MODE_MASK | 3019 RT5663_TDM_IN_CH_MASK | RT5663_TDM_OUT_CH_MASK | 3020 RT5663_TDM_IN_LEN_MASK | RT5663_TDM_OUT_LEN_MASK, val); 3021 3022 return 0; 3023 } 3024 3025 static int rt5663_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio) 3026 { 3027 struct snd_soc_component *component = dai->component; 3028 struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component); 3029 unsigned int reg; 3030 3031 dev_dbg(component->dev, "%s ratio = %d\n", __func__, ratio); 3032 3033 if (rt5663->codec_ver == CODEC_VER_1) 3034 reg = RT5663_TDM_9; 3035 else 3036 reg = RT5663_TDM_5; 3037 3038 switch (ratio) { 3039 case 32: 3040 snd_soc_component_update_bits(component, reg, 3041 RT5663_TDM_LENGTN_MASK, 3042 RT5663_TDM_LENGTN_16); 3043 break; 3044 case 40: 3045 snd_soc_component_update_bits(component, reg, 3046 RT5663_TDM_LENGTN_MASK, 3047 RT5663_TDM_LENGTN_20); 3048 break; 3049 case 48: 3050 snd_soc_component_update_bits(component, reg, 3051 RT5663_TDM_LENGTN_MASK, 3052 RT5663_TDM_LENGTN_24); 3053 break; 3054 case 64: 3055 snd_soc_component_update_bits(component, reg, 3056 RT5663_TDM_LENGTN_MASK, 3057 RT5663_TDM_LENGTN_32); 3058 break; 3059 default: 3060 dev_err(component->dev, "Invalid ratio!\n"); 3061 return -EINVAL; 3062 } 3063 3064 return 0; 3065 } 3066 3067 static int rt5663_set_bias_level(struct snd_soc_component *component, 3068 enum snd_soc_bias_level level) 3069 { 3070 struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component); 3071 3072 switch (level) { 3073 case SND_SOC_BIAS_ON: 3074 snd_soc_component_update_bits(component, RT5663_PWR_ANLG_1, 3075 RT5663_PWR_FV1_MASK | RT5663_PWR_FV2_MASK, 3076 RT5663_PWR_FV1 | RT5663_PWR_FV2); 3077 break; 3078 3079 case SND_SOC_BIAS_PREPARE: 3080 if (rt5663->codec_ver == CODEC_VER_1) { 3081 snd_soc_component_update_bits(component, RT5663_DIG_MISC, 3082 RT5663_DIG_GATE_CTRL_MASK, 3083 RT5663_DIG_GATE_CTRL_EN); 3084 snd_soc_component_update_bits(component, RT5663_SIG_CLK_DET, 3085 RT5663_EN_ANA_CLK_DET_MASK | 3086 RT5663_PWR_CLK_DET_MASK, 3087 RT5663_EN_ANA_CLK_DET_AUTO | 3088 RT5663_PWR_CLK_DET_EN); 3089 } 3090 break; 3091 3092 case SND_SOC_BIAS_STANDBY: 3093 if (rt5663->codec_ver == CODEC_VER_1) 3094 snd_soc_component_update_bits(component, RT5663_DIG_MISC, 3095 RT5663_DIG_GATE_CTRL_MASK, 3096 RT5663_DIG_GATE_CTRL_DIS); 3097 snd_soc_component_update_bits(component, RT5663_PWR_ANLG_1, 3098 RT5663_PWR_VREF1_MASK | RT5663_PWR_VREF2_MASK | 3099 RT5663_PWR_FV1_MASK | RT5663_PWR_FV2_MASK | 3100 RT5663_PWR_MB_MASK, RT5663_PWR_VREF1 | 3101 RT5663_PWR_VREF2 | RT5663_PWR_MB); 3102 usleep_range(10000, 10005); 3103 if (rt5663->codec_ver == CODEC_VER_1) { 3104 snd_soc_component_update_bits(component, RT5663_SIG_CLK_DET, 3105 RT5663_EN_ANA_CLK_DET_MASK | 3106 RT5663_PWR_CLK_DET_MASK, 3107 RT5663_EN_ANA_CLK_DET_DIS | 3108 RT5663_PWR_CLK_DET_DIS); 3109 } 3110 break; 3111 3112 case SND_SOC_BIAS_OFF: 3113 if (rt5663->jack_type != SND_JACK_HEADSET) 3114 snd_soc_component_update_bits(component, 3115 RT5663_PWR_ANLG_1, 3116 RT5663_PWR_VREF1_MASK | RT5663_PWR_VREF2_MASK | 3117 RT5663_PWR_FV1 | RT5663_PWR_FV2 | 3118 RT5663_PWR_MB_MASK, 0); 3119 else 3120 snd_soc_component_update_bits(component, 3121 RT5663_PWR_ANLG_1, 3122 RT5663_PWR_FV1_MASK | RT5663_PWR_FV2_MASK, 3123 RT5663_PWR_FV1 | RT5663_PWR_FV2); 3124 break; 3125 3126 default: 3127 break; 3128 } 3129 3130 return 0; 3131 } 3132 3133 static int rt5663_probe(struct snd_soc_component *component) 3134 { 3135 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); 3136 struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component); 3137 3138 rt5663->component = component; 3139 3140 switch (rt5663->codec_ver) { 3141 case CODEC_VER_1: 3142 snd_soc_dapm_new_controls(dapm, 3143 rt5663_v2_specific_dapm_widgets, 3144 ARRAY_SIZE(rt5663_v2_specific_dapm_widgets)); 3145 snd_soc_dapm_add_routes(dapm, 3146 rt5663_v2_specific_dapm_routes, 3147 ARRAY_SIZE(rt5663_v2_specific_dapm_routes)); 3148 snd_soc_add_component_controls(component, rt5663_v2_specific_controls, 3149 ARRAY_SIZE(rt5663_v2_specific_controls)); 3150 break; 3151 case CODEC_VER_0: 3152 snd_soc_dapm_new_controls(dapm, 3153 rt5663_specific_dapm_widgets, 3154 ARRAY_SIZE(rt5663_specific_dapm_widgets)); 3155 snd_soc_dapm_add_routes(dapm, 3156 rt5663_specific_dapm_routes, 3157 ARRAY_SIZE(rt5663_specific_dapm_routes)); 3158 snd_soc_add_component_controls(component, rt5663_specific_controls, 3159 ARRAY_SIZE(rt5663_specific_controls)); 3160 3161 if (!rt5663->imp_table) 3162 snd_soc_add_component_controls(component, rt5663_hpvol_controls, 3163 ARRAY_SIZE(rt5663_hpvol_controls)); 3164 break; 3165 } 3166 3167 return 0; 3168 } 3169 3170 static void rt5663_remove(struct snd_soc_component *component) 3171 { 3172 struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component); 3173 3174 regmap_write(rt5663->regmap, RT5663_RESET, 0); 3175 } 3176 3177 #ifdef CONFIG_PM 3178 static int rt5663_suspend(struct snd_soc_component *component) 3179 { 3180 struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component); 3181 3182 regcache_cache_only(rt5663->regmap, true); 3183 regcache_mark_dirty(rt5663->regmap); 3184 3185 return 0; 3186 } 3187 3188 static int rt5663_resume(struct snd_soc_component *component) 3189 { 3190 struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component); 3191 3192 regcache_cache_only(rt5663->regmap, false); 3193 regcache_sync(rt5663->regmap); 3194 3195 rt5663_irq(0, rt5663); 3196 3197 return 0; 3198 } 3199 #else 3200 #define rt5663_suspend NULL 3201 #define rt5663_resume NULL 3202 #endif 3203 3204 #define RT5663_STEREO_RATES SNDRV_PCM_RATE_8000_192000 3205 #define RT5663_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ 3206 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8) 3207 3208 static const struct snd_soc_dai_ops rt5663_aif_dai_ops = { 3209 .hw_params = rt5663_hw_params, 3210 .set_fmt = rt5663_set_dai_fmt, 3211 .set_sysclk = rt5663_set_dai_sysclk, 3212 .set_pll = rt5663_set_dai_pll, 3213 .set_tdm_slot = rt5663_set_tdm_slot, 3214 .set_bclk_ratio = rt5663_set_bclk_ratio, 3215 }; 3216 3217 static struct snd_soc_dai_driver rt5663_dai[] = { 3218 { 3219 .name = "rt5663-aif", 3220 .id = RT5663_AIF, 3221 .playback = { 3222 .stream_name = "AIF Playback", 3223 .channels_min = 1, 3224 .channels_max = 2, 3225 .rates = RT5663_STEREO_RATES, 3226 .formats = RT5663_FORMATS, 3227 }, 3228 .capture = { 3229 .stream_name = "AIF Capture", 3230 .channels_min = 1, 3231 .channels_max = 2, 3232 .rates = RT5663_STEREO_RATES, 3233 .formats = RT5663_FORMATS, 3234 }, 3235 .ops = &rt5663_aif_dai_ops, 3236 }, 3237 }; 3238 3239 static const struct snd_soc_component_driver soc_component_dev_rt5663 = { 3240 .probe = rt5663_probe, 3241 .remove = rt5663_remove, 3242 .suspend = rt5663_suspend, 3243 .resume = rt5663_resume, 3244 .set_bias_level = rt5663_set_bias_level, 3245 .controls = rt5663_snd_controls, 3246 .num_controls = ARRAY_SIZE(rt5663_snd_controls), 3247 .dapm_widgets = rt5663_dapm_widgets, 3248 .num_dapm_widgets = ARRAY_SIZE(rt5663_dapm_widgets), 3249 .dapm_routes = rt5663_dapm_routes, 3250 .num_dapm_routes = ARRAY_SIZE(rt5663_dapm_routes), 3251 .set_jack = rt5663_set_jack_detect, 3252 .use_pmdown_time = 1, 3253 .endianness = 1, 3254 .non_legacy_dai_naming = 1, 3255 }; 3256 3257 static const struct regmap_config rt5663_v2_regmap = { 3258 .reg_bits = 16, 3259 .val_bits = 16, 3260 .use_single_read = true, 3261 .use_single_write = true, 3262 .max_register = 0x07fa, 3263 .volatile_reg = rt5663_v2_volatile_register, 3264 .readable_reg = rt5663_v2_readable_register, 3265 .cache_type = REGCACHE_RBTREE, 3266 .reg_defaults = rt5663_v2_reg, 3267 .num_reg_defaults = ARRAY_SIZE(rt5663_v2_reg), 3268 }; 3269 3270 static const struct regmap_config rt5663_regmap = { 3271 .reg_bits = 16, 3272 .val_bits = 16, 3273 .use_single_read = true, 3274 .use_single_write = true, 3275 .max_register = 0x03f3, 3276 .volatile_reg = rt5663_volatile_register, 3277 .readable_reg = rt5663_readable_register, 3278 .cache_type = REGCACHE_RBTREE, 3279 .reg_defaults = rt5663_reg, 3280 .num_reg_defaults = ARRAY_SIZE(rt5663_reg), 3281 }; 3282 3283 static const struct regmap_config temp_regmap = { 3284 .name = "nocache", 3285 .reg_bits = 16, 3286 .val_bits = 16, 3287 .use_single_read = true, 3288 .use_single_write = true, 3289 .max_register = 0x03f3, 3290 .cache_type = REGCACHE_NONE, 3291 }; 3292 3293 static const struct i2c_device_id rt5663_i2c_id[] = { 3294 { "rt5663", 0 }, 3295 {} 3296 }; 3297 MODULE_DEVICE_TABLE(i2c, rt5663_i2c_id); 3298 3299 #if defined(CONFIG_OF) 3300 static const struct of_device_id rt5663_of_match[] = { 3301 { .compatible = "realtek,rt5663", }, 3302 {}, 3303 }; 3304 MODULE_DEVICE_TABLE(of, rt5663_of_match); 3305 #endif 3306 3307 #ifdef CONFIG_ACPI 3308 static const struct acpi_device_id rt5663_acpi_match[] = { 3309 { "10EC5663", 0}, 3310 {}, 3311 }; 3312 MODULE_DEVICE_TABLE(acpi, rt5663_acpi_match); 3313 #endif 3314 3315 static void rt5663_v2_calibrate(struct rt5663_priv *rt5663) 3316 { 3317 regmap_write(rt5663->regmap, RT5663_BIAS_CUR_8, 0xa402); 3318 regmap_write(rt5663->regmap, RT5663_PWR_DIG_1, 0x0100); 3319 regmap_write(rt5663->regmap, RT5663_RECMIX, 0x4040); 3320 regmap_write(rt5663->regmap, RT5663_DIG_MISC, 0x0001); 3321 regmap_write(rt5663->regmap, RT5663_RC_CLK, 0x0380); 3322 regmap_write(rt5663->regmap, RT5663_GLB_CLK, 0x8000); 3323 regmap_write(rt5663->regmap, RT5663_ADDA_CLK_1, 0x1000); 3324 regmap_write(rt5663->regmap, RT5663_CHOP_DAC_L, 0x3030); 3325 regmap_write(rt5663->regmap, RT5663_CALIB_ADC, 0x3c05); 3326 regmap_write(rt5663->regmap, RT5663_PWR_ANLG_1, 0xa23e); 3327 msleep(40); 3328 regmap_write(rt5663->regmap, RT5663_PWR_ANLG_1, 0xf23e); 3329 regmap_write(rt5663->regmap, RT5663_HP_CALIB_2, 0x0321); 3330 regmap_write(rt5663->regmap, RT5663_HP_CALIB_1, 0xfc00); 3331 msleep(500); 3332 } 3333 3334 static void rt5663_calibrate(struct rt5663_priv *rt5663) 3335 { 3336 int value, count; 3337 3338 regmap_write(rt5663->regmap, RT5663_RESET, 0x0000); 3339 msleep(20); 3340 regmap_write(rt5663->regmap, RT5663_ANA_BIAS_CUR_4, 0x00a1); 3341 regmap_write(rt5663->regmap, RT5663_RC_CLK, 0x0380); 3342 regmap_write(rt5663->regmap, RT5663_GLB_CLK, 0x8000); 3343 regmap_write(rt5663->regmap, RT5663_ADDA_CLK_1, 0x1000); 3344 regmap_write(rt5663->regmap, RT5663_VREF_RECMIX, 0x0032); 3345 regmap_write(rt5663->regmap, RT5663_HP_IMP_SEN_19, 0x000c); 3346 regmap_write(rt5663->regmap, RT5663_DUMMY_1, 0x0324); 3347 regmap_write(rt5663->regmap, RT5663_DIG_MISC, 0x8001); 3348 regmap_write(rt5663->regmap, RT5663_VREFADJ_OP, 0x0f28); 3349 regmap_write(rt5663->regmap, RT5663_PWR_ANLG_1, 0xa23b); 3350 msleep(30); 3351 regmap_write(rt5663->regmap, RT5663_PWR_ANLG_1, 0xf23b); 3352 regmap_write(rt5663->regmap, RT5663_PWR_ANLG_2, 0x8000); 3353 regmap_write(rt5663->regmap, RT5663_PWR_ANLG_3, 0x0008); 3354 regmap_write(rt5663->regmap, RT5663_PRE_DIV_GATING_1, 0xffff); 3355 regmap_write(rt5663->regmap, RT5663_PRE_DIV_GATING_2, 0xffff); 3356 regmap_write(rt5663->regmap, RT5663_CBJ_1, 0x8c10); 3357 regmap_write(rt5663->regmap, RT5663_IL_CMD_2, 0x00c1); 3358 regmap_write(rt5663->regmap, RT5663_EM_JACK_TYPE_1, 0xb880); 3359 regmap_write(rt5663->regmap, RT5663_EM_JACK_TYPE_2, 0x4110); 3360 regmap_write(rt5663->regmap, RT5663_EM_JACK_TYPE_2, 0x4118); 3361 3362 count = 0; 3363 while (true) { 3364 regmap_read(rt5663->regmap, RT5663_INT_ST_2, &value); 3365 if (!(value & 0x80)) 3366 usleep_range(10000, 10005); 3367 else 3368 break; 3369 3370 if (++count > 200) 3371 break; 3372 } 3373 3374 regmap_write(rt5663->regmap, RT5663_HP_IMP_SEN_19, 0x0000); 3375 regmap_write(rt5663->regmap, RT5663_DEPOP_2, 0x3003); 3376 regmap_write(rt5663->regmap, RT5663_DEPOP_1, 0x0038); 3377 regmap_write(rt5663->regmap, RT5663_DEPOP_1, 0x003b); 3378 regmap_write(rt5663->regmap, RT5663_PWR_DIG_2, 0x8400); 3379 regmap_write(rt5663->regmap, RT5663_PWR_DIG_1, 0x8df8); 3380 regmap_write(rt5663->regmap, RT5663_PWR_ANLG_2, 0x8003); 3381 regmap_write(rt5663->regmap, RT5663_PWR_ANLG_3, 0x018c); 3382 regmap_write(rt5663->regmap, RT5663_HP_CHARGE_PUMP_1, 0x1e32); 3383 regmap_write(rt5663->regmap, RT5663_DUMMY_2, 0x8089); 3384 regmap_write(rt5663->regmap, RT5663_DACREF_LDO, 0x3b0b); 3385 msleep(40); 3386 regmap_write(rt5663->regmap, RT5663_STO_DAC_MIXER, 0x0000); 3387 regmap_write(rt5663->regmap, RT5663_BYPASS_STO_DAC, 0x000c); 3388 regmap_write(rt5663->regmap, RT5663_HP_BIAS, 0xafaa); 3389 regmap_write(rt5663->regmap, RT5663_CHARGE_PUMP_1, 0x2224); 3390 regmap_write(rt5663->regmap, RT5663_HP_OUT_EN, 0x8088); 3391 regmap_write(rt5663->regmap, RT5663_STO_DRE_9, 0x0017); 3392 regmap_write(rt5663->regmap, RT5663_STO_DRE_10, 0x0017); 3393 regmap_write(rt5663->regmap, RT5663_STO1_ADC_MIXER, 0x4040); 3394 regmap_write(rt5663->regmap, RT5663_CHOP_ADC, 0x3000); 3395 regmap_write(rt5663->regmap, RT5663_RECMIX, 0x0005); 3396 regmap_write(rt5663->regmap, RT5663_ADDA_RST, 0xc000); 3397 regmap_write(rt5663->regmap, RT5663_STO1_HPF_ADJ1, 0x3320); 3398 regmap_write(rt5663->regmap, RT5663_HP_CALIB_2, 0x00c9); 3399 regmap_write(rt5663->regmap, RT5663_DUMMY_1, 0x004c); 3400 regmap_write(rt5663->regmap, RT5663_ANA_BIAS_CUR_1, 0x1111); 3401 regmap_write(rt5663->regmap, RT5663_BIAS_CUR_8, 0x4402); 3402 regmap_write(rt5663->regmap, RT5663_CHARGE_PUMP_2, 0x3311); 3403 regmap_write(rt5663->regmap, RT5663_HP_CALIB_1, 0x0069); 3404 regmap_write(rt5663->regmap, RT5663_HP_CALIB_3, 0x06ce); 3405 regmap_write(rt5663->regmap, RT5663_HP_CALIB_1_1, 0x6800); 3406 regmap_write(rt5663->regmap, RT5663_CHARGE_PUMP_2, 0x1100); 3407 regmap_write(rt5663->regmap, RT5663_HP_CALIB_7, 0x0057); 3408 regmap_write(rt5663->regmap, RT5663_HP_CALIB_1_1, 0xe800); 3409 3410 count = 0; 3411 while (true) { 3412 regmap_read(rt5663->regmap, RT5663_HP_CALIB_1_1, &value); 3413 if (value & 0x8000) 3414 usleep_range(10000, 10005); 3415 else 3416 break; 3417 3418 if (count > 200) 3419 return; 3420 count++; 3421 } 3422 3423 regmap_write(rt5663->regmap, RT5663_HP_CALIB_1_1, 0x6200); 3424 regmap_write(rt5663->regmap, RT5663_HP_CALIB_7, 0x0059); 3425 regmap_write(rt5663->regmap, RT5663_HP_CALIB_1_1, 0xe200); 3426 3427 count = 0; 3428 while (true) { 3429 regmap_read(rt5663->regmap, RT5663_HP_CALIB_1_1, &value); 3430 if (value & 0x8000) 3431 usleep_range(10000, 10005); 3432 else 3433 break; 3434 3435 if (count > 200) 3436 return; 3437 count++; 3438 } 3439 3440 regmap_write(rt5663->regmap, RT5663_EM_JACK_TYPE_1, 0xb8e0); 3441 usleep_range(10000, 10005); 3442 regmap_write(rt5663->regmap, RT5663_PWR_ANLG_1, 0x003b); 3443 usleep_range(10000, 10005); 3444 regmap_write(rt5663->regmap, RT5663_PWR_DIG_1, 0x0000); 3445 usleep_range(10000, 10005); 3446 regmap_write(rt5663->regmap, RT5663_DEPOP_1, 0x000b); 3447 usleep_range(10000, 10005); 3448 regmap_write(rt5663->regmap, RT5663_DEPOP_1, 0x0008); 3449 usleep_range(10000, 10005); 3450 regmap_write(rt5663->regmap, RT5663_PWR_ANLG_2, 0x0000); 3451 usleep_range(10000, 10005); 3452 } 3453 3454 static int rt5663_parse_dp(struct rt5663_priv *rt5663, struct device *dev) 3455 { 3456 int table_size; 3457 3458 device_property_read_u32(dev, "realtek,dc_offset_l_manual", 3459 &rt5663->pdata.dc_offset_l_manual); 3460 device_property_read_u32(dev, "realtek,dc_offset_r_manual", 3461 &rt5663->pdata.dc_offset_r_manual); 3462 device_property_read_u32(dev, "realtek,dc_offset_l_manual_mic", 3463 &rt5663->pdata.dc_offset_l_manual_mic); 3464 device_property_read_u32(dev, "realtek,dc_offset_r_manual_mic", 3465 &rt5663->pdata.dc_offset_r_manual_mic); 3466 device_property_read_u32(dev, "realtek,impedance_sensing_num", 3467 &rt5663->pdata.impedance_sensing_num); 3468 3469 if (rt5663->pdata.impedance_sensing_num) { 3470 table_size = sizeof(struct impedance_mapping_table) * 3471 rt5663->pdata.impedance_sensing_num; 3472 rt5663->imp_table = devm_kzalloc(dev, table_size, GFP_KERNEL); 3473 device_property_read_u32_array(dev, 3474 "realtek,impedance_sensing_table", 3475 (u32 *)rt5663->imp_table, table_size); 3476 } 3477 3478 return 0; 3479 } 3480 3481 static int rt5663_i2c_probe(struct i2c_client *i2c, 3482 const struct i2c_device_id *id) 3483 { 3484 struct rt5663_platform_data *pdata = dev_get_platdata(&i2c->dev); 3485 struct rt5663_priv *rt5663; 3486 int ret; 3487 unsigned int val; 3488 struct regmap *regmap; 3489 3490 rt5663 = devm_kzalloc(&i2c->dev, sizeof(struct rt5663_priv), 3491 GFP_KERNEL); 3492 3493 if (rt5663 == NULL) 3494 return -ENOMEM; 3495 3496 i2c_set_clientdata(i2c, rt5663); 3497 3498 if (pdata) 3499 rt5663->pdata = *pdata; 3500 else 3501 rt5663_parse_dp(rt5663, &i2c->dev); 3502 3503 regmap = devm_regmap_init_i2c(i2c, &temp_regmap); 3504 if (IS_ERR(regmap)) { 3505 ret = PTR_ERR(regmap); 3506 dev_err(&i2c->dev, "Failed to allocate temp register map: %d\n", 3507 ret); 3508 return ret; 3509 } 3510 3511 ret = regmap_read(regmap, RT5663_VENDOR_ID_2, &val); 3512 if (ret || (val != RT5663_DEVICE_ID_2 && val != RT5663_DEVICE_ID_1)) { 3513 dev_err(&i2c->dev, 3514 "Device with ID register %#x is not rt5663, retry one time.\n", 3515 val); 3516 msleep(100); 3517 regmap_read(regmap, RT5663_VENDOR_ID_2, &val); 3518 } 3519 3520 switch (val) { 3521 case RT5663_DEVICE_ID_2: 3522 rt5663->regmap = devm_regmap_init_i2c(i2c, &rt5663_v2_regmap); 3523 rt5663->codec_ver = CODEC_VER_1; 3524 break; 3525 case RT5663_DEVICE_ID_1: 3526 rt5663->regmap = devm_regmap_init_i2c(i2c, &rt5663_regmap); 3527 rt5663->codec_ver = CODEC_VER_0; 3528 break; 3529 default: 3530 dev_err(&i2c->dev, 3531 "Device with ID register %#x is not rt5663\n", 3532 val); 3533 return -ENODEV; 3534 } 3535 3536 if (IS_ERR(rt5663->regmap)) { 3537 ret = PTR_ERR(rt5663->regmap); 3538 dev_err(&i2c->dev, "Failed to allocate register map: %d\n", 3539 ret); 3540 return ret; 3541 } 3542 3543 /* reset and calibrate */ 3544 regmap_write(rt5663->regmap, RT5663_RESET, 0); 3545 regcache_cache_bypass(rt5663->regmap, true); 3546 switch (rt5663->codec_ver) { 3547 case CODEC_VER_1: 3548 rt5663_v2_calibrate(rt5663); 3549 break; 3550 case CODEC_VER_0: 3551 rt5663_calibrate(rt5663); 3552 break; 3553 default: 3554 dev_err(&i2c->dev, "%s:Unknown codec type\n", __func__); 3555 } 3556 regcache_cache_bypass(rt5663->regmap, false); 3557 regmap_write(rt5663->regmap, RT5663_RESET, 0); 3558 dev_dbg(&i2c->dev, "calibrate done\n"); 3559 3560 switch (rt5663->codec_ver) { 3561 case CODEC_VER_1: 3562 break; 3563 case CODEC_VER_0: 3564 ret = regmap_register_patch(rt5663->regmap, rt5663_patch_list, 3565 ARRAY_SIZE(rt5663_patch_list)); 3566 if (ret != 0) 3567 dev_warn(&i2c->dev, 3568 "Failed to apply regmap patch: %d\n", ret); 3569 break; 3570 default: 3571 dev_err(&i2c->dev, "%s:Unknown codec type\n", __func__); 3572 } 3573 3574 /* GPIO1 as IRQ */ 3575 regmap_update_bits(rt5663->regmap, RT5663_GPIO_1, RT5663_GP1_PIN_MASK, 3576 RT5663_GP1_PIN_IRQ); 3577 /* 4btn inline command debounce */ 3578 regmap_update_bits(rt5663->regmap, RT5663_IL_CMD_5, 3579 RT5663_4BTN_CLK_DEB_MASK, RT5663_4BTN_CLK_DEB_65MS); 3580 3581 switch (rt5663->codec_ver) { 3582 case CODEC_VER_1: 3583 regmap_write(rt5663->regmap, RT5663_BIAS_CUR_8, 0xa402); 3584 /* JD1 */ 3585 regmap_update_bits(rt5663->regmap, RT5663_AUTO_1MRC_CLK, 3586 RT5663_IRQ_POW_SAV_MASK | RT5663_IRQ_POW_SAV_JD1_MASK, 3587 RT5663_IRQ_POW_SAV_EN | RT5663_IRQ_POW_SAV_JD1_EN); 3588 regmap_update_bits(rt5663->regmap, RT5663_PWR_ANLG_2, 3589 RT5663_PWR_JD1_MASK, RT5663_PWR_JD1); 3590 regmap_update_bits(rt5663->regmap, RT5663_IRQ_1, 3591 RT5663_EN_CB_JD_MASK, RT5663_EN_CB_JD_EN); 3592 3593 regmap_update_bits(rt5663->regmap, RT5663_HP_LOGIC_2, 3594 RT5663_HP_SIG_SRC1_MASK, RT5663_HP_SIG_SRC1_REG); 3595 regmap_update_bits(rt5663->regmap, RT5663_RECMIX, 3596 RT5663_VREF_BIAS_MASK | RT5663_CBJ_DET_MASK | 3597 RT5663_DET_TYPE_MASK, RT5663_VREF_BIAS_REG | 3598 RT5663_CBJ_DET_EN | RT5663_DET_TYPE_QFN); 3599 /* Set GPIO4 and GPIO8 as input for combo jack */ 3600 regmap_update_bits(rt5663->regmap, RT5663_GPIO_2, 3601 RT5663_GP4_PIN_CONF_MASK, RT5663_GP4_PIN_CONF_INPUT); 3602 regmap_update_bits(rt5663->regmap, RT5663_GPIO_3, 3603 RT5663_GP8_PIN_CONF_MASK, RT5663_GP8_PIN_CONF_INPUT); 3604 regmap_update_bits(rt5663->regmap, RT5663_PWR_ANLG_1, 3605 RT5663_LDO1_DVO_MASK | RT5663_AMP_HP_MASK, 3606 RT5663_LDO1_DVO_0_9V | RT5663_AMP_HP_3X); 3607 break; 3608 case CODEC_VER_0: 3609 regmap_update_bits(rt5663->regmap, RT5663_DIG_MISC, 3610 RT5663_DIG_GATE_CTRL_MASK, RT5663_DIG_GATE_CTRL_EN); 3611 regmap_update_bits(rt5663->regmap, RT5663_AUTO_1MRC_CLK, 3612 RT5663_IRQ_MANUAL_MASK, RT5663_IRQ_MANUAL_EN); 3613 regmap_update_bits(rt5663->regmap, RT5663_IRQ_1, 3614 RT5663_EN_IRQ_JD1_MASK, RT5663_EN_IRQ_JD1_EN); 3615 regmap_update_bits(rt5663->regmap, RT5663_GPIO_1, 3616 RT5663_GPIO1_TYPE_MASK, RT5663_GPIO1_TYPE_EN); 3617 regmap_write(rt5663->regmap, RT5663_VREF_RECMIX, 0x0032); 3618 regmap_update_bits(rt5663->regmap, RT5663_GPIO_2, 3619 RT5663_GP1_PIN_CONF_MASK | RT5663_SEL_GPIO1_MASK, 3620 RT5663_GP1_PIN_CONF_OUTPUT | RT5663_SEL_GPIO1_EN); 3621 regmap_update_bits(rt5663->regmap, RT5663_RECMIX, 3622 RT5663_RECMIX1_BST1_MASK, RT5663_RECMIX1_BST1_ON); 3623 regmap_update_bits(rt5663->regmap, RT5663_TDM_2, 3624 RT5663_DATA_SWAP_ADCDAT1_MASK, 3625 RT5663_DATA_SWAP_ADCDAT1_LL); 3626 break; 3627 default: 3628 dev_err(&i2c->dev, "%s:Unknown codec type\n", __func__); 3629 } 3630 3631 INIT_DELAYED_WORK(&rt5663->jack_detect_work, rt5663_jack_detect_work); 3632 INIT_DELAYED_WORK(&rt5663->jd_unplug_work, rt5663_jd_unplug_work); 3633 3634 if (i2c->irq) { 3635 ret = request_irq(i2c->irq, rt5663_irq, 3636 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING 3637 | IRQF_ONESHOT, "rt5663", rt5663); 3638 if (ret) 3639 dev_err(&i2c->dev, "%s Failed to reguest IRQ: %d\n", 3640 __func__, ret); 3641 } 3642 3643 ret = devm_snd_soc_register_component(&i2c->dev, 3644 &soc_component_dev_rt5663, 3645 rt5663_dai, ARRAY_SIZE(rt5663_dai)); 3646 3647 if (ret) { 3648 if (i2c->irq) 3649 free_irq(i2c->irq, rt5663); 3650 } 3651 3652 return ret; 3653 } 3654 3655 static int rt5663_i2c_remove(struct i2c_client *i2c) 3656 { 3657 struct rt5663_priv *rt5663 = i2c_get_clientdata(i2c); 3658 3659 if (i2c->irq) 3660 free_irq(i2c->irq, rt5663); 3661 3662 return 0; 3663 } 3664 3665 static void rt5663_i2c_shutdown(struct i2c_client *client) 3666 { 3667 struct rt5663_priv *rt5663 = i2c_get_clientdata(client); 3668 3669 regmap_write(rt5663->regmap, RT5663_RESET, 0); 3670 } 3671 3672 static struct i2c_driver rt5663_i2c_driver = { 3673 .driver = { 3674 .name = "rt5663", 3675 .acpi_match_table = ACPI_PTR(rt5663_acpi_match), 3676 .of_match_table = of_match_ptr(rt5663_of_match), 3677 }, 3678 .probe = rt5663_i2c_probe, 3679 .remove = rt5663_i2c_remove, 3680 .shutdown = rt5663_i2c_shutdown, 3681 .id_table = rt5663_i2c_id, 3682 }; 3683 module_i2c_driver(rt5663_i2c_driver); 3684 3685 MODULE_DESCRIPTION("ASoC RT5663 driver"); 3686 MODULE_AUTHOR("Jack Yu <jack.yu@realtek.com>"); 3687 MODULE_LICENSE("GPL v2"); 3688