1 /* 2 * rt5651.c -- RT5651 ALSA SoC audio codec driver 3 * 4 * Copyright 2014 Realtek Semiconductor Corp. 5 * Author: Bard Liao <bardliao@realtek.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11 12 #include <linux/module.h> 13 #include <linux/moduleparam.h> 14 #include <linux/init.h> 15 #include <linux/delay.h> 16 #include <linux/pm.h> 17 #include <linux/i2c.h> 18 #include <linux/regmap.h> 19 #include <linux/platform_device.h> 20 #include <linux/spi/spi.h> 21 #include <linux/acpi.h> 22 #include <sound/core.h> 23 #include <sound/pcm.h> 24 #include <sound/pcm_params.h> 25 #include <sound/soc.h> 26 #include <sound/soc-dapm.h> 27 #include <sound/initval.h> 28 #include <sound/tlv.h> 29 30 #include "rl6231.h" 31 #include "rt5651.h" 32 33 #define RT5651_DEVICE_ID_VALUE 0x6281 34 35 #define RT5651_PR_RANGE_BASE (0xff + 1) 36 #define RT5651_PR_SPACING 0x100 37 38 #define RT5651_PR_BASE (RT5651_PR_RANGE_BASE + (0 * RT5651_PR_SPACING)) 39 40 static const struct regmap_range_cfg rt5651_ranges[] = { 41 { .name = "PR", .range_min = RT5651_PR_BASE, 42 .range_max = RT5651_PR_BASE + 0xb4, 43 .selector_reg = RT5651_PRIV_INDEX, 44 .selector_mask = 0xff, 45 .selector_shift = 0x0, 46 .window_start = RT5651_PRIV_DATA, 47 .window_len = 0x1, }, 48 }; 49 50 static const struct reg_sequence init_list[] = { 51 {RT5651_PR_BASE + 0x3d, 0x3e00}, 52 }; 53 54 static const struct reg_default rt5651_reg[] = { 55 { 0x00, 0x0000 }, 56 { 0x02, 0xc8c8 }, 57 { 0x03, 0xc8c8 }, 58 { 0x05, 0x0000 }, 59 { 0x0d, 0x0000 }, 60 { 0x0e, 0x0000 }, 61 { 0x0f, 0x0808 }, 62 { 0x10, 0x0808 }, 63 { 0x19, 0xafaf }, 64 { 0x1a, 0xafaf }, 65 { 0x1b, 0x0c00 }, 66 { 0x1c, 0x2f2f }, 67 { 0x1d, 0x2f2f }, 68 { 0x1e, 0x0000 }, 69 { 0x27, 0x7860 }, 70 { 0x28, 0x7070 }, 71 { 0x29, 0x8080 }, 72 { 0x2a, 0x5252 }, 73 { 0x2b, 0x5454 }, 74 { 0x2f, 0x0000 }, 75 { 0x30, 0x5000 }, 76 { 0x3b, 0x0000 }, 77 { 0x3c, 0x006f }, 78 { 0x3d, 0x0000 }, 79 { 0x3e, 0x006f }, 80 { 0x45, 0x6000 }, 81 { 0x4d, 0x0000 }, 82 { 0x4e, 0x0000 }, 83 { 0x4f, 0x0279 }, 84 { 0x50, 0x0000 }, 85 { 0x51, 0x0000 }, 86 { 0x52, 0x0279 }, 87 { 0x53, 0xf000 }, 88 { 0x61, 0x0000 }, 89 { 0x62, 0x0000 }, 90 { 0x63, 0x00c0 }, 91 { 0x64, 0x0000 }, 92 { 0x65, 0x0000 }, 93 { 0x66, 0x0000 }, 94 { 0x70, 0x8000 }, 95 { 0x71, 0x8000 }, 96 { 0x73, 0x1104 }, 97 { 0x74, 0x0c00 }, 98 { 0x75, 0x1400 }, 99 { 0x77, 0x0c00 }, 100 { 0x78, 0x4000 }, 101 { 0x79, 0x0123 }, 102 { 0x80, 0x0000 }, 103 { 0x81, 0x0000 }, 104 { 0x82, 0x0000 }, 105 { 0x83, 0x0800 }, 106 { 0x84, 0x0000 }, 107 { 0x85, 0x0008 }, 108 { 0x89, 0x0000 }, 109 { 0x8e, 0x0004 }, 110 { 0x8f, 0x1100 }, 111 { 0x90, 0x0000 }, 112 { 0x93, 0x2000 }, 113 { 0x94, 0x0200 }, 114 { 0xb0, 0x2080 }, 115 { 0xb1, 0x0000 }, 116 { 0xb4, 0x2206 }, 117 { 0xb5, 0x1f00 }, 118 { 0xb6, 0x0000 }, 119 { 0xbb, 0x0000 }, 120 { 0xbc, 0x0000 }, 121 { 0xbd, 0x0000 }, 122 { 0xbe, 0x0000 }, 123 { 0xbf, 0x0000 }, 124 { 0xc0, 0x0400 }, 125 { 0xc1, 0x0000 }, 126 { 0xc2, 0x0000 }, 127 { 0xcf, 0x0013 }, 128 { 0xd0, 0x0680 }, 129 { 0xd1, 0x1c17 }, 130 { 0xd3, 0xb320 }, 131 { 0xd9, 0x0809 }, 132 { 0xfa, 0x0010 }, 133 { 0xfe, 0x10ec }, 134 { 0xff, 0x6281 }, 135 }; 136 137 static bool rt5651_volatile_register(struct device *dev, unsigned int reg) 138 { 139 int i; 140 141 for (i = 0; i < ARRAY_SIZE(rt5651_ranges); i++) { 142 if ((reg >= rt5651_ranges[i].window_start && 143 reg <= rt5651_ranges[i].window_start + 144 rt5651_ranges[i].window_len) || 145 (reg >= rt5651_ranges[i].range_min && 146 reg <= rt5651_ranges[i].range_max)) { 147 return true; 148 } 149 } 150 151 switch (reg) { 152 case RT5651_RESET: 153 case RT5651_PRIV_DATA: 154 case RT5651_EQ_CTRL1: 155 case RT5651_ALC_1: 156 case RT5651_IRQ_CTRL2: 157 case RT5651_INT_IRQ_ST: 158 case RT5651_PGM_REG_ARR1: 159 case RT5651_PGM_REG_ARR3: 160 case RT5651_VENDOR_ID: 161 case RT5651_DEVICE_ID: 162 return true; 163 default: 164 return false; 165 } 166 } 167 168 static bool rt5651_readable_register(struct device *dev, unsigned int reg) 169 { 170 int i; 171 172 for (i = 0; i < ARRAY_SIZE(rt5651_ranges); i++) { 173 if ((reg >= rt5651_ranges[i].window_start && 174 reg <= rt5651_ranges[i].window_start + 175 rt5651_ranges[i].window_len) || 176 (reg >= rt5651_ranges[i].range_min && 177 reg <= rt5651_ranges[i].range_max)) { 178 return true; 179 } 180 } 181 182 switch (reg) { 183 case RT5651_RESET: 184 case RT5651_VERSION_ID: 185 case RT5651_VENDOR_ID: 186 case RT5651_DEVICE_ID: 187 case RT5651_HP_VOL: 188 case RT5651_LOUT_CTRL1: 189 case RT5651_LOUT_CTRL2: 190 case RT5651_IN1_IN2: 191 case RT5651_IN3: 192 case RT5651_INL1_INR1_VOL: 193 case RT5651_INL2_INR2_VOL: 194 case RT5651_DAC1_DIG_VOL: 195 case RT5651_DAC2_DIG_VOL: 196 case RT5651_DAC2_CTRL: 197 case RT5651_ADC_DIG_VOL: 198 case RT5651_ADC_DATA: 199 case RT5651_ADC_BST_VOL: 200 case RT5651_STO1_ADC_MIXER: 201 case RT5651_STO2_ADC_MIXER: 202 case RT5651_AD_DA_MIXER: 203 case RT5651_STO_DAC_MIXER: 204 case RT5651_DD_MIXER: 205 case RT5651_DIG_INF_DATA: 206 case RT5651_PDM_CTL: 207 case RT5651_REC_L1_MIXER: 208 case RT5651_REC_L2_MIXER: 209 case RT5651_REC_R1_MIXER: 210 case RT5651_REC_R2_MIXER: 211 case RT5651_HPO_MIXER: 212 case RT5651_OUT_L1_MIXER: 213 case RT5651_OUT_L2_MIXER: 214 case RT5651_OUT_L3_MIXER: 215 case RT5651_OUT_R1_MIXER: 216 case RT5651_OUT_R2_MIXER: 217 case RT5651_OUT_R3_MIXER: 218 case RT5651_LOUT_MIXER: 219 case RT5651_PWR_DIG1: 220 case RT5651_PWR_DIG2: 221 case RT5651_PWR_ANLG1: 222 case RT5651_PWR_ANLG2: 223 case RT5651_PWR_MIXER: 224 case RT5651_PWR_VOL: 225 case RT5651_PRIV_INDEX: 226 case RT5651_PRIV_DATA: 227 case RT5651_I2S1_SDP: 228 case RT5651_I2S2_SDP: 229 case RT5651_ADDA_CLK1: 230 case RT5651_ADDA_CLK2: 231 case RT5651_DMIC: 232 case RT5651_TDM_CTL_1: 233 case RT5651_TDM_CTL_2: 234 case RT5651_TDM_CTL_3: 235 case RT5651_GLB_CLK: 236 case RT5651_PLL_CTRL1: 237 case RT5651_PLL_CTRL2: 238 case RT5651_PLL_MODE_1: 239 case RT5651_PLL_MODE_2: 240 case RT5651_PLL_MODE_3: 241 case RT5651_PLL_MODE_4: 242 case RT5651_PLL_MODE_5: 243 case RT5651_PLL_MODE_6: 244 case RT5651_PLL_MODE_7: 245 case RT5651_DEPOP_M1: 246 case RT5651_DEPOP_M2: 247 case RT5651_DEPOP_M3: 248 case RT5651_CHARGE_PUMP: 249 case RT5651_MICBIAS: 250 case RT5651_A_JD_CTL1: 251 case RT5651_EQ_CTRL1: 252 case RT5651_EQ_CTRL2: 253 case RT5651_ALC_1: 254 case RT5651_ALC_2: 255 case RT5651_ALC_3: 256 case RT5651_JD_CTRL1: 257 case RT5651_JD_CTRL2: 258 case RT5651_IRQ_CTRL1: 259 case RT5651_IRQ_CTRL2: 260 case RT5651_INT_IRQ_ST: 261 case RT5651_GPIO_CTRL1: 262 case RT5651_GPIO_CTRL2: 263 case RT5651_GPIO_CTRL3: 264 case RT5651_PGM_REG_ARR1: 265 case RT5651_PGM_REG_ARR2: 266 case RT5651_PGM_REG_ARR3: 267 case RT5651_PGM_REG_ARR4: 268 case RT5651_PGM_REG_ARR5: 269 case RT5651_SCB_FUNC: 270 case RT5651_SCB_CTRL: 271 case RT5651_BASE_BACK: 272 case RT5651_MP3_PLUS1: 273 case RT5651_MP3_PLUS2: 274 case RT5651_ADJ_HPF_CTRL1: 275 case RT5651_ADJ_HPF_CTRL2: 276 case RT5651_HP_CALIB_AMP_DET: 277 case RT5651_HP_CALIB2: 278 case RT5651_SV_ZCD1: 279 case RT5651_SV_ZCD2: 280 case RT5651_D_MISC: 281 case RT5651_DUMMY2: 282 case RT5651_DUMMY3: 283 return true; 284 default: 285 return false; 286 } 287 } 288 289 static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -4650, 150, 0); 290 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -65625, 375, 0); 291 static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -3450, 150, 0); 292 static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -17625, 375, 0); 293 static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0); 294 295 /* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */ 296 static const DECLARE_TLV_DB_RANGE(bst_tlv, 297 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0), 298 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0), 299 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0), 300 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0), 301 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0), 302 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0), 303 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0) 304 ); 305 306 /* Interface data select */ 307 static const char * const rt5651_data_select[] = { 308 "Normal", "Swap", "left copy to right", "right copy to left"}; 309 310 static SOC_ENUM_SINGLE_DECL(rt5651_if2_dac_enum, RT5651_DIG_INF_DATA, 311 RT5651_IF2_DAC_SEL_SFT, rt5651_data_select); 312 313 static SOC_ENUM_SINGLE_DECL(rt5651_if2_adc_enum, RT5651_DIG_INF_DATA, 314 RT5651_IF2_ADC_SEL_SFT, rt5651_data_select); 315 316 static const struct snd_kcontrol_new rt5651_snd_controls[] = { 317 /* Headphone Output Volume */ 318 SOC_DOUBLE_TLV("HP Playback Volume", RT5651_HP_VOL, 319 RT5651_L_VOL_SFT, RT5651_R_VOL_SFT, 39, 1, out_vol_tlv), 320 /* OUTPUT Control */ 321 SOC_DOUBLE_TLV("OUT Playback Volume", RT5651_LOUT_CTRL1, 322 RT5651_L_VOL_SFT, RT5651_R_VOL_SFT, 39, 1, out_vol_tlv), 323 324 /* DAC Digital Volume */ 325 SOC_DOUBLE("DAC2 Playback Switch", RT5651_DAC2_CTRL, 326 RT5651_M_DAC_L2_VOL_SFT, RT5651_M_DAC_R2_VOL_SFT, 1, 1), 327 SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5651_DAC1_DIG_VOL, 328 RT5651_L_VOL_SFT, RT5651_R_VOL_SFT, 329 175, 0, dac_vol_tlv), 330 SOC_DOUBLE_TLV("Mono DAC Playback Volume", RT5651_DAC2_DIG_VOL, 331 RT5651_L_VOL_SFT, RT5651_R_VOL_SFT, 332 175, 0, dac_vol_tlv), 333 /* IN1/IN2 Control */ 334 SOC_SINGLE_TLV("IN1 Boost", RT5651_IN1_IN2, 335 RT5651_BST_SFT1, 8, 0, bst_tlv), 336 SOC_SINGLE_TLV("IN2 Boost", RT5651_IN1_IN2, 337 RT5651_BST_SFT2, 8, 0, bst_tlv), 338 /* INL/INR Volume Control */ 339 SOC_DOUBLE_TLV("IN Capture Volume", RT5651_INL1_INR1_VOL, 340 RT5651_INL_VOL_SFT, RT5651_INR_VOL_SFT, 341 31, 1, in_vol_tlv), 342 /* ADC Digital Volume Control */ 343 SOC_DOUBLE("ADC Capture Switch", RT5651_ADC_DIG_VOL, 344 RT5651_L_MUTE_SFT, RT5651_R_MUTE_SFT, 1, 1), 345 SOC_DOUBLE_TLV("ADC Capture Volume", RT5651_ADC_DIG_VOL, 346 RT5651_L_VOL_SFT, RT5651_R_VOL_SFT, 347 127, 0, adc_vol_tlv), 348 SOC_DOUBLE_TLV("Mono ADC Capture Volume", RT5651_ADC_DATA, 349 RT5651_L_VOL_SFT, RT5651_R_VOL_SFT, 350 127, 0, adc_vol_tlv), 351 /* ADC Boost Volume Control */ 352 SOC_DOUBLE_TLV("ADC Boost Gain", RT5651_ADC_BST_VOL, 353 RT5651_ADC_L_BST_SFT, RT5651_ADC_R_BST_SFT, 354 3, 0, adc_bst_tlv), 355 356 /* ASRC */ 357 SOC_SINGLE("IF1 ASRC Switch", RT5651_PLL_MODE_1, 358 RT5651_STO1_T_SFT, 1, 0), 359 SOC_SINGLE("IF2 ASRC Switch", RT5651_PLL_MODE_1, 360 RT5651_STO2_T_SFT, 1, 0), 361 SOC_SINGLE("DMIC ASRC Switch", RT5651_PLL_MODE_1, 362 RT5651_DMIC_1_M_SFT, 1, 0), 363 364 SOC_ENUM("ADC IF2 Data Switch", rt5651_if2_adc_enum), 365 SOC_ENUM("DAC IF2 Data Switch", rt5651_if2_dac_enum), 366 }; 367 368 /** 369 * set_dmic_clk - Set parameter of dmic. 370 * 371 * @w: DAPM widget. 372 * @kcontrol: The kcontrol of this widget. 373 * @event: Event id. 374 * 375 */ 376 static int set_dmic_clk(struct snd_soc_dapm_widget *w, 377 struct snd_kcontrol *kcontrol, int event) 378 { 379 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); 380 struct rt5651_priv *rt5651 = snd_soc_codec_get_drvdata(codec); 381 int idx, rate; 382 383 rate = rt5651->sysclk / rl6231_get_pre_div(rt5651->regmap, 384 RT5651_ADDA_CLK1, RT5651_I2S_PD1_SFT); 385 idx = rl6231_calc_dmic_clk(rate); 386 if (idx < 0) 387 dev_err(codec->dev, "Failed to set DMIC clock\n"); 388 else 389 snd_soc_update_bits(codec, RT5651_DMIC, RT5651_DMIC_CLK_MASK, 390 idx << RT5651_DMIC_CLK_SFT); 391 392 return idx; 393 } 394 395 static int is_sysclk_from_pll(struct snd_soc_dapm_widget *source, 396 struct snd_soc_dapm_widget *sink) 397 { 398 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(source->dapm); 399 unsigned int val; 400 401 val = snd_soc_read(codec, RT5651_GLB_CLK); 402 val &= RT5651_SCLK_SRC_MASK; 403 if (val == RT5651_SCLK_SRC_PLL1) 404 return 1; 405 else 406 return 0; 407 } 408 409 /* Digital Mixer */ 410 static const struct snd_kcontrol_new rt5651_sto1_adc_l_mix[] = { 411 SOC_DAPM_SINGLE("ADC1 Switch", RT5651_STO1_ADC_MIXER, 412 RT5651_M_STO1_ADC_L1_SFT, 1, 1), 413 SOC_DAPM_SINGLE("ADC2 Switch", RT5651_STO1_ADC_MIXER, 414 RT5651_M_STO1_ADC_L2_SFT, 1, 1), 415 }; 416 417 static const struct snd_kcontrol_new rt5651_sto1_adc_r_mix[] = { 418 SOC_DAPM_SINGLE("ADC1 Switch", RT5651_STO1_ADC_MIXER, 419 RT5651_M_STO1_ADC_R1_SFT, 1, 1), 420 SOC_DAPM_SINGLE("ADC2 Switch", RT5651_STO1_ADC_MIXER, 421 RT5651_M_STO1_ADC_R2_SFT, 1, 1), 422 }; 423 424 static const struct snd_kcontrol_new rt5651_sto2_adc_l_mix[] = { 425 SOC_DAPM_SINGLE("ADC1 Switch", RT5651_STO2_ADC_MIXER, 426 RT5651_M_STO2_ADC_L1_SFT, 1, 1), 427 SOC_DAPM_SINGLE("ADC2 Switch", RT5651_STO2_ADC_MIXER, 428 RT5651_M_STO2_ADC_L2_SFT, 1, 1), 429 }; 430 431 static const struct snd_kcontrol_new rt5651_sto2_adc_r_mix[] = { 432 SOC_DAPM_SINGLE("ADC1 Switch", RT5651_STO2_ADC_MIXER, 433 RT5651_M_STO2_ADC_R1_SFT, 1, 1), 434 SOC_DAPM_SINGLE("ADC2 Switch", RT5651_STO2_ADC_MIXER, 435 RT5651_M_STO2_ADC_R2_SFT, 1, 1), 436 }; 437 438 static const struct snd_kcontrol_new rt5651_dac_l_mix[] = { 439 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5651_AD_DA_MIXER, 440 RT5651_M_ADCMIX_L_SFT, 1, 1), 441 SOC_DAPM_SINGLE("INF1 Switch", RT5651_AD_DA_MIXER, 442 RT5651_M_IF1_DAC_L_SFT, 1, 1), 443 }; 444 445 static const struct snd_kcontrol_new rt5651_dac_r_mix[] = { 446 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5651_AD_DA_MIXER, 447 RT5651_M_ADCMIX_R_SFT, 1, 1), 448 SOC_DAPM_SINGLE("INF1 Switch", RT5651_AD_DA_MIXER, 449 RT5651_M_IF1_DAC_R_SFT, 1, 1), 450 }; 451 452 static const struct snd_kcontrol_new rt5651_sto_dac_l_mix[] = { 453 SOC_DAPM_SINGLE("DAC L1 Switch", RT5651_STO_DAC_MIXER, 454 RT5651_M_DAC_L1_MIXL_SFT, 1, 1), 455 SOC_DAPM_SINGLE("DAC L2 Switch", RT5651_STO_DAC_MIXER, 456 RT5651_M_DAC_L2_MIXL_SFT, 1, 1), 457 SOC_DAPM_SINGLE("DAC R1 Switch", RT5651_STO_DAC_MIXER, 458 RT5651_M_DAC_R1_MIXL_SFT, 1, 1), 459 }; 460 461 static const struct snd_kcontrol_new rt5651_sto_dac_r_mix[] = { 462 SOC_DAPM_SINGLE("DAC R1 Switch", RT5651_STO_DAC_MIXER, 463 RT5651_M_DAC_R1_MIXR_SFT, 1, 1), 464 SOC_DAPM_SINGLE("DAC R2 Switch", RT5651_STO_DAC_MIXER, 465 RT5651_M_DAC_R2_MIXR_SFT, 1, 1), 466 SOC_DAPM_SINGLE("DAC L1 Switch", RT5651_STO_DAC_MIXER, 467 RT5651_M_DAC_L1_MIXR_SFT, 1, 1), 468 }; 469 470 static const struct snd_kcontrol_new rt5651_dd_dac_l_mix[] = { 471 SOC_DAPM_SINGLE("DAC L1 Switch", RT5651_DD_MIXER, 472 RT5651_M_STO_DD_L1_SFT, 1, 1), 473 SOC_DAPM_SINGLE("DAC L2 Switch", RT5651_DD_MIXER, 474 RT5651_M_STO_DD_L2_SFT, 1, 1), 475 SOC_DAPM_SINGLE("DAC R2 Switch", RT5651_DD_MIXER, 476 RT5651_M_STO_DD_R2_L_SFT, 1, 1), 477 }; 478 479 static const struct snd_kcontrol_new rt5651_dd_dac_r_mix[] = { 480 SOC_DAPM_SINGLE("DAC R1 Switch", RT5651_DD_MIXER, 481 RT5651_M_STO_DD_R1_SFT, 1, 1), 482 SOC_DAPM_SINGLE("DAC R2 Switch", RT5651_DD_MIXER, 483 RT5651_M_STO_DD_R2_SFT, 1, 1), 484 SOC_DAPM_SINGLE("DAC L2 Switch", RT5651_DD_MIXER, 485 RT5651_M_STO_DD_L2_R_SFT, 1, 1), 486 }; 487 488 /* Analog Input Mixer */ 489 static const struct snd_kcontrol_new rt5651_rec_l_mix[] = { 490 SOC_DAPM_SINGLE("INL1 Switch", RT5651_REC_L2_MIXER, 491 RT5651_M_IN1_L_RM_L_SFT, 1, 1), 492 SOC_DAPM_SINGLE("BST3 Switch", RT5651_REC_L2_MIXER, 493 RT5651_M_BST3_RM_L_SFT, 1, 1), 494 SOC_DAPM_SINGLE("BST2 Switch", RT5651_REC_L2_MIXER, 495 RT5651_M_BST2_RM_L_SFT, 1, 1), 496 SOC_DAPM_SINGLE("BST1 Switch", RT5651_REC_L2_MIXER, 497 RT5651_M_BST1_RM_L_SFT, 1, 1), 498 }; 499 500 static const struct snd_kcontrol_new rt5651_rec_r_mix[] = { 501 SOC_DAPM_SINGLE("INR1 Switch", RT5651_REC_R2_MIXER, 502 RT5651_M_IN1_R_RM_R_SFT, 1, 1), 503 SOC_DAPM_SINGLE("BST3 Switch", RT5651_REC_R2_MIXER, 504 RT5651_M_BST3_RM_R_SFT, 1, 1), 505 SOC_DAPM_SINGLE("BST2 Switch", RT5651_REC_R2_MIXER, 506 RT5651_M_BST2_RM_R_SFT, 1, 1), 507 SOC_DAPM_SINGLE("BST1 Switch", RT5651_REC_R2_MIXER, 508 RT5651_M_BST1_RM_R_SFT, 1, 1), 509 }; 510 511 /* Analog Output Mixer */ 512 513 static const struct snd_kcontrol_new rt5651_out_l_mix[] = { 514 SOC_DAPM_SINGLE("BST1 Switch", RT5651_OUT_L3_MIXER, 515 RT5651_M_BST1_OM_L_SFT, 1, 1), 516 SOC_DAPM_SINGLE("BST2 Switch", RT5651_OUT_L3_MIXER, 517 RT5651_M_BST2_OM_L_SFT, 1, 1), 518 SOC_DAPM_SINGLE("INL1 Switch", RT5651_OUT_L3_MIXER, 519 RT5651_M_IN1_L_OM_L_SFT, 1, 1), 520 SOC_DAPM_SINGLE("REC MIXL Switch", RT5651_OUT_L3_MIXER, 521 RT5651_M_RM_L_OM_L_SFT, 1, 1), 522 SOC_DAPM_SINGLE("DAC L1 Switch", RT5651_OUT_L3_MIXER, 523 RT5651_M_DAC_L1_OM_L_SFT, 1, 1), 524 }; 525 526 static const struct snd_kcontrol_new rt5651_out_r_mix[] = { 527 SOC_DAPM_SINGLE("BST2 Switch", RT5651_OUT_R3_MIXER, 528 RT5651_M_BST2_OM_R_SFT, 1, 1), 529 SOC_DAPM_SINGLE("BST1 Switch", RT5651_OUT_R3_MIXER, 530 RT5651_M_BST1_OM_R_SFT, 1, 1), 531 SOC_DAPM_SINGLE("INR1 Switch", RT5651_OUT_R3_MIXER, 532 RT5651_M_IN1_R_OM_R_SFT, 1, 1), 533 SOC_DAPM_SINGLE("REC MIXR Switch", RT5651_OUT_R3_MIXER, 534 RT5651_M_RM_R_OM_R_SFT, 1, 1), 535 SOC_DAPM_SINGLE("DAC R1 Switch", RT5651_OUT_R3_MIXER, 536 RT5651_M_DAC_R1_OM_R_SFT, 1, 1), 537 }; 538 539 static const struct snd_kcontrol_new rt5651_hpo_mix[] = { 540 SOC_DAPM_SINGLE("HPO MIX DAC1 Switch", RT5651_HPO_MIXER, 541 RT5651_M_DAC1_HM_SFT, 1, 1), 542 SOC_DAPM_SINGLE("HPO MIX HPVOL Switch", RT5651_HPO_MIXER, 543 RT5651_M_HPVOL_HM_SFT, 1, 1), 544 }; 545 546 static const struct snd_kcontrol_new rt5651_lout_mix[] = { 547 SOC_DAPM_SINGLE("DAC L1 Switch", RT5651_LOUT_MIXER, 548 RT5651_M_DAC_L1_LM_SFT, 1, 1), 549 SOC_DAPM_SINGLE("DAC R1 Switch", RT5651_LOUT_MIXER, 550 RT5651_M_DAC_R1_LM_SFT, 1, 1), 551 SOC_DAPM_SINGLE("OUTVOL L Switch", RT5651_LOUT_MIXER, 552 RT5651_M_OV_L_LM_SFT, 1, 1), 553 SOC_DAPM_SINGLE("OUTVOL R Switch", RT5651_LOUT_MIXER, 554 RT5651_M_OV_R_LM_SFT, 1, 1), 555 }; 556 557 static const struct snd_kcontrol_new outvol_l_control = 558 SOC_DAPM_SINGLE("Switch", RT5651_LOUT_CTRL1, 559 RT5651_VOL_L_SFT, 1, 1); 560 561 static const struct snd_kcontrol_new outvol_r_control = 562 SOC_DAPM_SINGLE("Switch", RT5651_LOUT_CTRL1, 563 RT5651_VOL_R_SFT, 1, 1); 564 565 static const struct snd_kcontrol_new lout_l_mute_control = 566 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5651_LOUT_CTRL1, 567 RT5651_L_MUTE_SFT, 1, 1); 568 569 static const struct snd_kcontrol_new lout_r_mute_control = 570 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5651_LOUT_CTRL1, 571 RT5651_R_MUTE_SFT, 1, 1); 572 573 static const struct snd_kcontrol_new hpovol_l_control = 574 SOC_DAPM_SINGLE("Switch", RT5651_HP_VOL, 575 RT5651_VOL_L_SFT, 1, 1); 576 577 static const struct snd_kcontrol_new hpovol_r_control = 578 SOC_DAPM_SINGLE("Switch", RT5651_HP_VOL, 579 RT5651_VOL_R_SFT, 1, 1); 580 581 static const struct snd_kcontrol_new hpo_l_mute_control = 582 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5651_HP_VOL, 583 RT5651_L_MUTE_SFT, 1, 1); 584 585 static const struct snd_kcontrol_new hpo_r_mute_control = 586 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5651_HP_VOL, 587 RT5651_R_MUTE_SFT, 1, 1); 588 589 /* Stereo ADC source */ 590 static const char * const rt5651_stereo1_adc1_src[] = {"DD MIX", "ADC"}; 591 592 static SOC_ENUM_SINGLE_DECL( 593 rt5651_stereo1_adc1_enum, RT5651_STO1_ADC_MIXER, 594 RT5651_STO1_ADC_1_SRC_SFT, rt5651_stereo1_adc1_src); 595 596 static const struct snd_kcontrol_new rt5651_sto1_adc_l1_mux = 597 SOC_DAPM_ENUM("Stereo1 ADC L1 source", rt5651_stereo1_adc1_enum); 598 599 static const struct snd_kcontrol_new rt5651_sto1_adc_r1_mux = 600 SOC_DAPM_ENUM("Stereo1 ADC R1 source", rt5651_stereo1_adc1_enum); 601 602 static const char * const rt5651_stereo1_adc2_src[] = {"DMIC", "DD MIX"}; 603 604 static SOC_ENUM_SINGLE_DECL( 605 rt5651_stereo1_adc2_enum, RT5651_STO1_ADC_MIXER, 606 RT5651_STO1_ADC_2_SRC_SFT, rt5651_stereo1_adc2_src); 607 608 static const struct snd_kcontrol_new rt5651_sto1_adc_l2_mux = 609 SOC_DAPM_ENUM("Stereo1 ADC L2 source", rt5651_stereo1_adc2_enum); 610 611 static const struct snd_kcontrol_new rt5651_sto1_adc_r2_mux = 612 SOC_DAPM_ENUM("Stereo1 ADC R2 source", rt5651_stereo1_adc2_enum); 613 614 /* Mono ADC source */ 615 static const char * const rt5651_sto2_adc_l1_src[] = {"DD MIXL", "ADCL"}; 616 617 static SOC_ENUM_SINGLE_DECL( 618 rt5651_sto2_adc_l1_enum, RT5651_STO1_ADC_MIXER, 619 RT5651_STO2_ADC_L1_SRC_SFT, rt5651_sto2_adc_l1_src); 620 621 static const struct snd_kcontrol_new rt5651_sto2_adc_l1_mux = 622 SOC_DAPM_ENUM("Stereo2 ADC1 left source", rt5651_sto2_adc_l1_enum); 623 624 static const char * const rt5651_sto2_adc_l2_src[] = {"DMIC L", "DD MIXL"}; 625 626 static SOC_ENUM_SINGLE_DECL( 627 rt5651_sto2_adc_l2_enum, RT5651_STO1_ADC_MIXER, 628 RT5651_STO2_ADC_L2_SRC_SFT, rt5651_sto2_adc_l2_src); 629 630 static const struct snd_kcontrol_new rt5651_sto2_adc_l2_mux = 631 SOC_DAPM_ENUM("Stereo2 ADC2 left source", rt5651_sto2_adc_l2_enum); 632 633 static const char * const rt5651_sto2_adc_r1_src[] = {"DD MIXR", "ADCR"}; 634 635 static SOC_ENUM_SINGLE_DECL( 636 rt5651_sto2_adc_r1_enum, RT5651_STO1_ADC_MIXER, 637 RT5651_STO2_ADC_R1_SRC_SFT, rt5651_sto2_adc_r1_src); 638 639 static const struct snd_kcontrol_new rt5651_sto2_adc_r1_mux = 640 SOC_DAPM_ENUM("Stereo2 ADC1 right source", rt5651_sto2_adc_r1_enum); 641 642 static const char * const rt5651_sto2_adc_r2_src[] = {"DMIC R", "DD MIXR"}; 643 644 static SOC_ENUM_SINGLE_DECL( 645 rt5651_sto2_adc_r2_enum, RT5651_STO1_ADC_MIXER, 646 RT5651_STO2_ADC_R2_SRC_SFT, rt5651_sto2_adc_r2_src); 647 648 static const struct snd_kcontrol_new rt5651_sto2_adc_r2_mux = 649 SOC_DAPM_ENUM("Stereo2 ADC2 right source", rt5651_sto2_adc_r2_enum); 650 651 /* DAC2 channel source */ 652 653 static const char * const rt5651_dac_src[] = {"IF1", "IF2"}; 654 655 static SOC_ENUM_SINGLE_DECL(rt5651_dac_l2_enum, RT5651_DAC2_CTRL, 656 RT5651_SEL_DAC_L2_SFT, rt5651_dac_src); 657 658 static const struct snd_kcontrol_new rt5651_dac_l2_mux = 659 SOC_DAPM_ENUM("DAC2 left channel source", rt5651_dac_l2_enum); 660 661 static SOC_ENUM_SINGLE_DECL( 662 rt5651_dac_r2_enum, RT5651_DAC2_CTRL, 663 RT5651_SEL_DAC_R2_SFT, rt5651_dac_src); 664 665 static const struct snd_kcontrol_new rt5651_dac_r2_mux = 666 SOC_DAPM_ENUM("DAC2 right channel source", rt5651_dac_r2_enum); 667 668 /* IF2_ADC channel source */ 669 670 static const char * const rt5651_adc_src[] = {"IF1 ADC1", "IF1 ADC2"}; 671 672 static SOC_ENUM_SINGLE_DECL(rt5651_if2_adc_src_enum, RT5651_DIG_INF_DATA, 673 RT5651_IF2_ADC_SRC_SFT, rt5651_adc_src); 674 675 static const struct snd_kcontrol_new rt5651_if2_adc_src_mux = 676 SOC_DAPM_ENUM("IF2 ADC channel source", rt5651_if2_adc_src_enum); 677 678 /* PDM select */ 679 static const char * const rt5651_pdm_sel[] = {"DD MIX", "Stereo DAC MIX"}; 680 681 static SOC_ENUM_SINGLE_DECL( 682 rt5651_pdm_l_sel_enum, RT5651_PDM_CTL, 683 RT5651_PDM_L_SEL_SFT, rt5651_pdm_sel); 684 685 static SOC_ENUM_SINGLE_DECL( 686 rt5651_pdm_r_sel_enum, RT5651_PDM_CTL, 687 RT5651_PDM_R_SEL_SFT, rt5651_pdm_sel); 688 689 static const struct snd_kcontrol_new rt5651_pdm_l_mux = 690 SOC_DAPM_ENUM("PDM L select", rt5651_pdm_l_sel_enum); 691 692 static const struct snd_kcontrol_new rt5651_pdm_r_mux = 693 SOC_DAPM_ENUM("PDM R select", rt5651_pdm_r_sel_enum); 694 695 static int rt5651_amp_power_event(struct snd_soc_dapm_widget *w, 696 struct snd_kcontrol *kcontrol, int event) 697 { 698 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); 699 struct rt5651_priv *rt5651 = snd_soc_codec_get_drvdata(codec); 700 701 switch (event) { 702 case SND_SOC_DAPM_POST_PMU: 703 /* depop parameters */ 704 regmap_update_bits(rt5651->regmap, RT5651_PR_BASE + 705 RT5651_CHPUMP_INT_REG1, 0x0700, 0x0200); 706 regmap_update_bits(rt5651->regmap, RT5651_DEPOP_M2, 707 RT5651_DEPOP_MASK, RT5651_DEPOP_MAN); 708 regmap_update_bits(rt5651->regmap, RT5651_DEPOP_M1, 709 RT5651_HP_CP_MASK | RT5651_HP_SG_MASK | 710 RT5651_HP_CB_MASK, RT5651_HP_CP_PU | 711 RT5651_HP_SG_DIS | RT5651_HP_CB_PU); 712 regmap_write(rt5651->regmap, RT5651_PR_BASE + 713 RT5651_HP_DCC_INT1, 0x9f00); 714 /* headphone amp power on */ 715 regmap_update_bits(rt5651->regmap, RT5651_PWR_ANLG1, 716 RT5651_PWR_FV1 | RT5651_PWR_FV2, 0); 717 regmap_update_bits(rt5651->regmap, RT5651_PWR_ANLG1, 718 RT5651_PWR_HA, 719 RT5651_PWR_HA); 720 usleep_range(10000, 15000); 721 regmap_update_bits(rt5651->regmap, RT5651_PWR_ANLG1, 722 RT5651_PWR_FV1 | RT5651_PWR_FV2 , 723 RT5651_PWR_FV1 | RT5651_PWR_FV2); 724 break; 725 726 default: 727 return 0; 728 } 729 730 return 0; 731 } 732 733 static int rt5651_hp_event(struct snd_soc_dapm_widget *w, 734 struct snd_kcontrol *kcontrol, int event) 735 { 736 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); 737 struct rt5651_priv *rt5651 = snd_soc_codec_get_drvdata(codec); 738 739 switch (event) { 740 case SND_SOC_DAPM_POST_PMU: 741 /* headphone unmute sequence */ 742 regmap_update_bits(rt5651->regmap, RT5651_DEPOP_M2, 743 RT5651_DEPOP_MASK | RT5651_DIG_DP_MASK, 744 RT5651_DEPOP_AUTO | RT5651_DIG_DP_EN); 745 regmap_update_bits(rt5651->regmap, RT5651_CHARGE_PUMP, 746 RT5651_PM_HP_MASK, RT5651_PM_HP_HV); 747 748 regmap_update_bits(rt5651->regmap, RT5651_DEPOP_M3, 749 RT5651_CP_FQ1_MASK | RT5651_CP_FQ2_MASK | 750 RT5651_CP_FQ3_MASK, 751 (RT5651_CP_FQ_192_KHZ << RT5651_CP_FQ1_SFT) | 752 (RT5651_CP_FQ_12_KHZ << RT5651_CP_FQ2_SFT) | 753 (RT5651_CP_FQ_192_KHZ << RT5651_CP_FQ3_SFT)); 754 755 regmap_write(rt5651->regmap, RT5651_PR_BASE + 756 RT5651_MAMP_INT_REG2, 0x1c00); 757 regmap_update_bits(rt5651->regmap, RT5651_DEPOP_M1, 758 RT5651_HP_CP_MASK | RT5651_HP_SG_MASK, 759 RT5651_HP_CP_PD | RT5651_HP_SG_EN); 760 regmap_update_bits(rt5651->regmap, RT5651_PR_BASE + 761 RT5651_CHPUMP_INT_REG1, 0x0700, 0x0400); 762 rt5651->hp_mute = 0; 763 break; 764 765 case SND_SOC_DAPM_PRE_PMD: 766 rt5651->hp_mute = 1; 767 usleep_range(70000, 75000); 768 break; 769 770 default: 771 return 0; 772 } 773 774 return 0; 775 } 776 777 static int rt5651_hp_post_event(struct snd_soc_dapm_widget *w, 778 struct snd_kcontrol *kcontrol, int event) 779 { 780 781 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); 782 struct rt5651_priv *rt5651 = snd_soc_codec_get_drvdata(codec); 783 784 switch (event) { 785 case SND_SOC_DAPM_POST_PMU: 786 if (!rt5651->hp_mute) 787 usleep_range(80000, 85000); 788 789 break; 790 791 default: 792 return 0; 793 } 794 795 return 0; 796 } 797 798 static int rt5651_bst1_event(struct snd_soc_dapm_widget *w, 799 struct snd_kcontrol *kcontrol, int event) 800 { 801 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); 802 803 switch (event) { 804 case SND_SOC_DAPM_POST_PMU: 805 snd_soc_update_bits(codec, RT5651_PWR_ANLG2, 806 RT5651_PWR_BST1_OP2, RT5651_PWR_BST1_OP2); 807 break; 808 809 case SND_SOC_DAPM_PRE_PMD: 810 snd_soc_update_bits(codec, RT5651_PWR_ANLG2, 811 RT5651_PWR_BST1_OP2, 0); 812 break; 813 814 default: 815 return 0; 816 } 817 818 return 0; 819 } 820 821 static int rt5651_bst2_event(struct snd_soc_dapm_widget *w, 822 struct snd_kcontrol *kcontrol, int event) 823 { 824 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); 825 826 switch (event) { 827 case SND_SOC_DAPM_POST_PMU: 828 snd_soc_update_bits(codec, RT5651_PWR_ANLG2, 829 RT5651_PWR_BST2_OP2, RT5651_PWR_BST2_OP2); 830 break; 831 832 case SND_SOC_DAPM_PRE_PMD: 833 snd_soc_update_bits(codec, RT5651_PWR_ANLG2, 834 RT5651_PWR_BST2_OP2, 0); 835 break; 836 837 default: 838 return 0; 839 } 840 841 return 0; 842 } 843 844 static int rt5651_bst3_event(struct snd_soc_dapm_widget *w, 845 struct snd_kcontrol *kcontrol, int event) 846 { 847 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); 848 849 switch (event) { 850 case SND_SOC_DAPM_POST_PMU: 851 snd_soc_update_bits(codec, RT5651_PWR_ANLG2, 852 RT5651_PWR_BST3_OP2, RT5651_PWR_BST3_OP2); 853 break; 854 855 case SND_SOC_DAPM_PRE_PMD: 856 snd_soc_update_bits(codec, RT5651_PWR_ANLG2, 857 RT5651_PWR_BST3_OP2, 0); 858 break; 859 860 default: 861 return 0; 862 } 863 864 return 0; 865 } 866 867 static const struct snd_soc_dapm_widget rt5651_dapm_widgets[] = { 868 /* ASRC */ 869 SND_SOC_DAPM_SUPPLY_S("I2S1 ASRC", 1, RT5651_PLL_MODE_2, 870 15, 0, NULL, 0), 871 SND_SOC_DAPM_SUPPLY_S("I2S2 ASRC", 1, RT5651_PLL_MODE_2, 872 14, 0, NULL, 0), 873 SND_SOC_DAPM_SUPPLY_S("STO1 DAC ASRC", 1, RT5651_PLL_MODE_2, 874 13, 0, NULL, 0), 875 SND_SOC_DAPM_SUPPLY_S("STO2 DAC ASRC", 1, RT5651_PLL_MODE_2, 876 12, 0, NULL, 0), 877 SND_SOC_DAPM_SUPPLY_S("ADC ASRC", 1, RT5651_PLL_MODE_2, 878 11, 0, NULL, 0), 879 880 SND_SOC_DAPM_SUPPLY("PLL1", RT5651_PWR_ANLG2, 881 RT5651_PWR_PLL_BIT, 0, NULL, 0), 882 /* Input Side */ 883 /* micbias */ 884 SND_SOC_DAPM_SUPPLY("LDO", RT5651_PWR_ANLG1, 885 RT5651_PWR_LDO_BIT, 0, NULL, 0), 886 SND_SOC_DAPM_MICBIAS("micbias1", RT5651_PWR_ANLG2, 887 RT5651_PWR_MB1_BIT, 0), 888 /* Input Lines */ 889 SND_SOC_DAPM_INPUT("MIC1"), 890 SND_SOC_DAPM_INPUT("MIC2"), 891 SND_SOC_DAPM_INPUT("MIC3"), 892 893 SND_SOC_DAPM_INPUT("IN1P"), 894 SND_SOC_DAPM_INPUT("IN2P"), 895 SND_SOC_DAPM_INPUT("IN2N"), 896 SND_SOC_DAPM_INPUT("IN3P"), 897 SND_SOC_DAPM_INPUT("DMIC L1"), 898 SND_SOC_DAPM_INPUT("DMIC R1"), 899 SND_SOC_DAPM_SUPPLY("DMIC CLK", RT5651_DMIC, RT5651_DMIC_1_EN_SFT, 900 0, set_dmic_clk, SND_SOC_DAPM_PRE_PMU), 901 /* Boost */ 902 SND_SOC_DAPM_PGA_E("BST1", RT5651_PWR_ANLG2, 903 RT5651_PWR_BST1_BIT, 0, NULL, 0, rt5651_bst1_event, 904 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU), 905 SND_SOC_DAPM_PGA_E("BST2", RT5651_PWR_ANLG2, 906 RT5651_PWR_BST2_BIT, 0, NULL, 0, rt5651_bst2_event, 907 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU), 908 SND_SOC_DAPM_PGA_E("BST3", RT5651_PWR_ANLG2, 909 RT5651_PWR_BST3_BIT, 0, NULL, 0, rt5651_bst3_event, 910 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU), 911 /* Input Volume */ 912 SND_SOC_DAPM_PGA("INL1 VOL", RT5651_PWR_VOL, 913 RT5651_PWR_IN1_L_BIT, 0, NULL, 0), 914 SND_SOC_DAPM_PGA("INR1 VOL", RT5651_PWR_VOL, 915 RT5651_PWR_IN1_R_BIT, 0, NULL, 0), 916 SND_SOC_DAPM_PGA("INL2 VOL", RT5651_PWR_VOL, 917 RT5651_PWR_IN2_L_BIT, 0, NULL, 0), 918 SND_SOC_DAPM_PGA("INR2 VOL", RT5651_PWR_VOL, 919 RT5651_PWR_IN2_R_BIT, 0, NULL, 0), 920 921 /* REC Mixer */ 922 SND_SOC_DAPM_MIXER("RECMIXL", RT5651_PWR_MIXER, RT5651_PWR_RM_L_BIT, 0, 923 rt5651_rec_l_mix, ARRAY_SIZE(rt5651_rec_l_mix)), 924 SND_SOC_DAPM_MIXER("RECMIXR", RT5651_PWR_MIXER, RT5651_PWR_RM_R_BIT, 0, 925 rt5651_rec_r_mix, ARRAY_SIZE(rt5651_rec_r_mix)), 926 /* ADCs */ 927 SND_SOC_DAPM_ADC("ADC L", NULL, SND_SOC_NOPM, 0, 0), 928 SND_SOC_DAPM_ADC("ADC R", NULL, SND_SOC_NOPM, 0, 0), 929 SND_SOC_DAPM_SUPPLY("ADC L Power", RT5651_PWR_DIG1, 930 RT5651_PWR_ADC_L_BIT, 0, NULL, 0), 931 SND_SOC_DAPM_SUPPLY("ADC R Power", RT5651_PWR_DIG1, 932 RT5651_PWR_ADC_R_BIT, 0, NULL, 0), 933 /* ADC Mux */ 934 SND_SOC_DAPM_MUX("Stereo1 ADC L2 Mux", SND_SOC_NOPM, 0, 0, 935 &rt5651_sto1_adc_l2_mux), 936 SND_SOC_DAPM_MUX("Stereo1 ADC R2 Mux", SND_SOC_NOPM, 0, 0, 937 &rt5651_sto1_adc_r2_mux), 938 SND_SOC_DAPM_MUX("Stereo1 ADC L1 Mux", SND_SOC_NOPM, 0, 0, 939 &rt5651_sto1_adc_l1_mux), 940 SND_SOC_DAPM_MUX("Stereo1 ADC R1 Mux", SND_SOC_NOPM, 0, 0, 941 &rt5651_sto1_adc_r1_mux), 942 SND_SOC_DAPM_MUX("Stereo2 ADC L2 Mux", SND_SOC_NOPM, 0, 0, 943 &rt5651_sto2_adc_l2_mux), 944 SND_SOC_DAPM_MUX("Stereo2 ADC L1 Mux", SND_SOC_NOPM, 0, 0, 945 &rt5651_sto2_adc_l1_mux), 946 SND_SOC_DAPM_MUX("Stereo2 ADC R1 Mux", SND_SOC_NOPM, 0, 0, 947 &rt5651_sto2_adc_r1_mux), 948 SND_SOC_DAPM_MUX("Stereo2 ADC R2 Mux", SND_SOC_NOPM, 0, 0, 949 &rt5651_sto2_adc_r2_mux), 950 /* ADC Mixer */ 951 SND_SOC_DAPM_SUPPLY("Stereo1 Filter", RT5651_PWR_DIG2, 952 RT5651_PWR_ADC_STO1_F_BIT, 0, NULL, 0), 953 SND_SOC_DAPM_SUPPLY("Stereo2 Filter", RT5651_PWR_DIG2, 954 RT5651_PWR_ADC_STO2_F_BIT, 0, NULL, 0), 955 SND_SOC_DAPM_MIXER("Stereo1 ADC MIXL", SND_SOC_NOPM, 0, 0, 956 rt5651_sto1_adc_l_mix, 957 ARRAY_SIZE(rt5651_sto1_adc_l_mix)), 958 SND_SOC_DAPM_MIXER("Stereo1 ADC MIXR", SND_SOC_NOPM, 0, 0, 959 rt5651_sto1_adc_r_mix, 960 ARRAY_SIZE(rt5651_sto1_adc_r_mix)), 961 SND_SOC_DAPM_MIXER("Stereo2 ADC MIXL", SND_SOC_NOPM, 0, 0, 962 rt5651_sto2_adc_l_mix, 963 ARRAY_SIZE(rt5651_sto2_adc_l_mix)), 964 SND_SOC_DAPM_MIXER("Stereo2 ADC MIXR", SND_SOC_NOPM, 0, 0, 965 rt5651_sto2_adc_r_mix, 966 ARRAY_SIZE(rt5651_sto2_adc_r_mix)), 967 968 /* Digital Interface */ 969 SND_SOC_DAPM_SUPPLY("I2S1", RT5651_PWR_DIG1, 970 RT5651_PWR_I2S1_BIT, 0, NULL, 0), 971 SND_SOC_DAPM_PGA("IF1 DAC", SND_SOC_NOPM, 0, 0, NULL, 0), 972 SND_SOC_DAPM_PGA("IF1 DAC1 L", SND_SOC_NOPM, 0, 0, NULL, 0), 973 SND_SOC_DAPM_PGA("IF1 DAC1 R", SND_SOC_NOPM, 0, 0, NULL, 0), 974 SND_SOC_DAPM_PGA("IF1 ADC1", SND_SOC_NOPM, 0, 0, NULL, 0), 975 SND_SOC_DAPM_PGA("IF1 DAC2 L", SND_SOC_NOPM, 0, 0, NULL, 0), 976 SND_SOC_DAPM_PGA("IF1 DAC2 R", SND_SOC_NOPM, 0, 0, NULL, 0), 977 SND_SOC_DAPM_PGA("IF1 ADC2", SND_SOC_NOPM, 0, 0, NULL, 0), 978 SND_SOC_DAPM_SUPPLY("I2S2", RT5651_PWR_DIG1, 979 RT5651_PWR_I2S2_BIT, 0, NULL, 0), 980 SND_SOC_DAPM_PGA("IF2 DAC", SND_SOC_NOPM, 0, 0, NULL, 0), 981 SND_SOC_DAPM_PGA("IF2 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0), 982 SND_SOC_DAPM_PGA("IF2 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0), 983 SND_SOC_DAPM_MUX("IF2 ADC", SND_SOC_NOPM, 0, 0, 984 &rt5651_if2_adc_src_mux), 985 986 /* Digital Interface Select */ 987 988 SND_SOC_DAPM_MUX("PDM L Mux", RT5651_PDM_CTL, 989 RT5651_M_PDM_L_SFT, 1, &rt5651_pdm_l_mux), 990 SND_SOC_DAPM_MUX("PDM R Mux", RT5651_PDM_CTL, 991 RT5651_M_PDM_R_SFT, 1, &rt5651_pdm_r_mux), 992 /* Audio Interface */ 993 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0), 994 SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0), 995 SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0), 996 SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0), 997 998 /* Audio DSP */ 999 SND_SOC_DAPM_PGA("Audio DSP", SND_SOC_NOPM, 0, 0, NULL, 0), 1000 1001 /* Output Side */ 1002 /* DAC mixer before sound effect */ 1003 SND_SOC_DAPM_MIXER("DAC MIXL", SND_SOC_NOPM, 0, 0, 1004 rt5651_dac_l_mix, ARRAY_SIZE(rt5651_dac_l_mix)), 1005 SND_SOC_DAPM_MIXER("DAC MIXR", SND_SOC_NOPM, 0, 0, 1006 rt5651_dac_r_mix, ARRAY_SIZE(rt5651_dac_r_mix)), 1007 1008 /* DAC2 channel Mux */ 1009 SND_SOC_DAPM_MUX("DAC L2 Mux", SND_SOC_NOPM, 0, 0, &rt5651_dac_l2_mux), 1010 SND_SOC_DAPM_MUX("DAC R2 Mux", SND_SOC_NOPM, 0, 0, &rt5651_dac_r2_mux), 1011 SND_SOC_DAPM_PGA("DAC L2 Volume", SND_SOC_NOPM, 0, 0, NULL, 0), 1012 SND_SOC_DAPM_PGA("DAC R2 Volume", SND_SOC_NOPM, 0, 0, NULL, 0), 1013 1014 SND_SOC_DAPM_SUPPLY("Stero1 DAC Power", RT5651_PWR_DIG2, 1015 RT5651_PWR_DAC_STO1_F_BIT, 0, NULL, 0), 1016 SND_SOC_DAPM_SUPPLY("Stero2 DAC Power", RT5651_PWR_DIG2, 1017 RT5651_PWR_DAC_STO2_F_BIT, 0, NULL, 0), 1018 /* DAC Mixer */ 1019 SND_SOC_DAPM_MIXER("Stereo DAC MIXL", SND_SOC_NOPM, 0, 0, 1020 rt5651_sto_dac_l_mix, 1021 ARRAY_SIZE(rt5651_sto_dac_l_mix)), 1022 SND_SOC_DAPM_MIXER("Stereo DAC MIXR", SND_SOC_NOPM, 0, 0, 1023 rt5651_sto_dac_r_mix, 1024 ARRAY_SIZE(rt5651_sto_dac_r_mix)), 1025 SND_SOC_DAPM_MIXER("DD MIXL", SND_SOC_NOPM, 0, 0, 1026 rt5651_dd_dac_l_mix, 1027 ARRAY_SIZE(rt5651_dd_dac_l_mix)), 1028 SND_SOC_DAPM_MIXER("DD MIXR", SND_SOC_NOPM, 0, 0, 1029 rt5651_dd_dac_r_mix, 1030 ARRAY_SIZE(rt5651_dd_dac_r_mix)), 1031 1032 /* DACs */ 1033 SND_SOC_DAPM_DAC("DAC L1", NULL, SND_SOC_NOPM, 0, 0), 1034 SND_SOC_DAPM_DAC("DAC R1", NULL, SND_SOC_NOPM, 0, 0), 1035 SND_SOC_DAPM_SUPPLY("DAC L1 Power", RT5651_PWR_DIG1, 1036 RT5651_PWR_DAC_L1_BIT, 0, NULL, 0), 1037 SND_SOC_DAPM_SUPPLY("DAC R1 Power", RT5651_PWR_DIG1, 1038 RT5651_PWR_DAC_R1_BIT, 0, NULL, 0), 1039 /* OUT Mixer */ 1040 SND_SOC_DAPM_MIXER("OUT MIXL", RT5651_PWR_MIXER, RT5651_PWR_OM_L_BIT, 1041 0, rt5651_out_l_mix, ARRAY_SIZE(rt5651_out_l_mix)), 1042 SND_SOC_DAPM_MIXER("OUT MIXR", RT5651_PWR_MIXER, RT5651_PWR_OM_R_BIT, 1043 0, rt5651_out_r_mix, ARRAY_SIZE(rt5651_out_r_mix)), 1044 /* Ouput Volume */ 1045 SND_SOC_DAPM_SWITCH("OUTVOL L", RT5651_PWR_VOL, 1046 RT5651_PWR_OV_L_BIT, 0, &outvol_l_control), 1047 SND_SOC_DAPM_SWITCH("OUTVOL R", RT5651_PWR_VOL, 1048 RT5651_PWR_OV_R_BIT, 0, &outvol_r_control), 1049 SND_SOC_DAPM_SWITCH("HPOVOL L", RT5651_PWR_VOL, 1050 RT5651_PWR_HV_L_BIT, 0, &hpovol_l_control), 1051 SND_SOC_DAPM_SWITCH("HPOVOL R", RT5651_PWR_VOL, 1052 RT5651_PWR_HV_R_BIT, 0, &hpovol_r_control), 1053 SND_SOC_DAPM_PGA("INL1", RT5651_PWR_VOL, 1054 RT5651_PWR_IN1_L_BIT, 0, NULL, 0), 1055 SND_SOC_DAPM_PGA("INR1", RT5651_PWR_VOL, 1056 RT5651_PWR_IN1_R_BIT, 0, NULL, 0), 1057 SND_SOC_DAPM_PGA("INL2", RT5651_PWR_VOL, 1058 RT5651_PWR_IN2_L_BIT, 0, NULL, 0), 1059 SND_SOC_DAPM_PGA("INR2", RT5651_PWR_VOL, 1060 RT5651_PWR_IN2_R_BIT, 0, NULL, 0), 1061 /* HPO/LOUT/Mono Mixer */ 1062 SND_SOC_DAPM_MIXER("HPOL MIX", SND_SOC_NOPM, 0, 0, 1063 rt5651_hpo_mix, ARRAY_SIZE(rt5651_hpo_mix)), 1064 SND_SOC_DAPM_MIXER("HPOR MIX", SND_SOC_NOPM, 0, 0, 1065 rt5651_hpo_mix, ARRAY_SIZE(rt5651_hpo_mix)), 1066 SND_SOC_DAPM_SUPPLY("HP L Amp", RT5651_PWR_ANLG1, 1067 RT5651_PWR_HP_L_BIT, 0, NULL, 0), 1068 SND_SOC_DAPM_SUPPLY("HP R Amp", RT5651_PWR_ANLG1, 1069 RT5651_PWR_HP_R_BIT, 0, NULL, 0), 1070 SND_SOC_DAPM_MIXER("LOUT MIX", RT5651_PWR_ANLG1, RT5651_PWR_LM_BIT, 0, 1071 rt5651_lout_mix, ARRAY_SIZE(rt5651_lout_mix)), 1072 1073 SND_SOC_DAPM_SUPPLY("Amp Power", RT5651_PWR_ANLG1, 1074 RT5651_PWR_HA_BIT, 0, rt5651_amp_power_event, 1075 SND_SOC_DAPM_POST_PMU), 1076 SND_SOC_DAPM_PGA_S("HP Amp", 1, SND_SOC_NOPM, 0, 0, rt5651_hp_event, 1077 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU), 1078 SND_SOC_DAPM_SWITCH("HPO L Playback", SND_SOC_NOPM, 0, 0, 1079 &hpo_l_mute_control), 1080 SND_SOC_DAPM_SWITCH("HPO R Playback", SND_SOC_NOPM, 0, 0, 1081 &hpo_r_mute_control), 1082 SND_SOC_DAPM_SWITCH("LOUT L Playback", SND_SOC_NOPM, 0, 0, 1083 &lout_l_mute_control), 1084 SND_SOC_DAPM_SWITCH("LOUT R Playback", SND_SOC_NOPM, 0, 0, 1085 &lout_r_mute_control), 1086 SND_SOC_DAPM_POST("HP Post", rt5651_hp_post_event), 1087 1088 /* Output Lines */ 1089 SND_SOC_DAPM_OUTPUT("HPOL"), 1090 SND_SOC_DAPM_OUTPUT("HPOR"), 1091 SND_SOC_DAPM_OUTPUT("LOUTL"), 1092 SND_SOC_DAPM_OUTPUT("LOUTR"), 1093 SND_SOC_DAPM_OUTPUT("PDML"), 1094 SND_SOC_DAPM_OUTPUT("PDMR"), 1095 }; 1096 1097 static const struct snd_soc_dapm_route rt5651_dapm_routes[] = { 1098 {"Stero1 DAC Power", NULL, "STO1 DAC ASRC"}, 1099 {"Stero2 DAC Power", NULL, "STO2 DAC ASRC"}, 1100 {"I2S1", NULL, "I2S1 ASRC"}, 1101 {"I2S2", NULL, "I2S2 ASRC"}, 1102 1103 {"IN1P", NULL, "LDO"}, 1104 {"IN2P", NULL, "LDO"}, 1105 {"IN3P", NULL, "LDO"}, 1106 1107 {"IN1P", NULL, "MIC1"}, 1108 {"IN2P", NULL, "MIC2"}, 1109 {"IN2N", NULL, "MIC2"}, 1110 {"IN3P", NULL, "MIC3"}, 1111 1112 {"BST1", NULL, "IN1P"}, 1113 {"BST2", NULL, "IN2P"}, 1114 {"BST2", NULL, "IN2N"}, 1115 {"BST3", NULL, "IN3P"}, 1116 1117 {"INL1 VOL", NULL, "IN2P"}, 1118 {"INR1 VOL", NULL, "IN2N"}, 1119 1120 {"RECMIXL", "INL1 Switch", "INL1 VOL"}, 1121 {"RECMIXL", "BST3 Switch", "BST3"}, 1122 {"RECMIXL", "BST2 Switch", "BST2"}, 1123 {"RECMIXL", "BST1 Switch", "BST1"}, 1124 1125 {"RECMIXR", "INR1 Switch", "INR1 VOL"}, 1126 {"RECMIXR", "BST3 Switch", "BST3"}, 1127 {"RECMIXR", "BST2 Switch", "BST2"}, 1128 {"RECMIXR", "BST1 Switch", "BST1"}, 1129 1130 {"ADC L", NULL, "RECMIXL"}, 1131 {"ADC L", NULL, "ADC L Power"}, 1132 {"ADC R", NULL, "RECMIXR"}, 1133 {"ADC R", NULL, "ADC R Power"}, 1134 1135 {"DMIC L1", NULL, "DMIC CLK"}, 1136 {"DMIC R1", NULL, "DMIC CLK"}, 1137 1138 {"Stereo1 ADC L2 Mux", "DMIC", "DMIC L1"}, 1139 {"Stereo1 ADC L2 Mux", "DD MIX", "DD MIXL"}, 1140 {"Stereo1 ADC L1 Mux", "ADC", "ADC L"}, 1141 {"Stereo1 ADC L1 Mux", "DD MIX", "DD MIXL"}, 1142 1143 {"Stereo1 ADC R1 Mux", "ADC", "ADC R"}, 1144 {"Stereo1 ADC R1 Mux", "DD MIX", "DD MIXR"}, 1145 {"Stereo1 ADC R2 Mux", "DMIC", "DMIC R1"}, 1146 {"Stereo1 ADC R2 Mux", "DD MIX", "DD MIXR"}, 1147 1148 {"Stereo2 ADC L2 Mux", "DMIC L", "DMIC L1"}, 1149 {"Stereo2 ADC L2 Mux", "DD MIXL", "DD MIXL"}, 1150 {"Stereo2 ADC L1 Mux", "DD MIXL", "DD MIXL"}, 1151 {"Stereo2 ADC L1 Mux", "ADCL", "ADC L"}, 1152 1153 {"Stereo2 ADC R1 Mux", "DD MIXR", "DD MIXR"}, 1154 {"Stereo2 ADC R1 Mux", "ADCR", "ADC R"}, 1155 {"Stereo2 ADC R2 Mux", "DMIC R", "DMIC R1"}, 1156 {"Stereo2 ADC R2 Mux", "DD MIXR", "DD MIXR"}, 1157 1158 {"Stereo1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC L1 Mux"}, 1159 {"Stereo1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC L2 Mux"}, 1160 {"Stereo1 ADC MIXL", NULL, "Stereo1 Filter"}, 1161 {"Stereo1 Filter", NULL, "PLL1", is_sysclk_from_pll}, 1162 {"Stereo1 Filter", NULL, "ADC ASRC"}, 1163 1164 {"Stereo1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC R1 Mux"}, 1165 {"Stereo1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC R2 Mux"}, 1166 {"Stereo1 ADC MIXR", NULL, "Stereo1 Filter"}, 1167 1168 {"Stereo2 ADC MIXL", "ADC1 Switch", "Stereo2 ADC L1 Mux"}, 1169 {"Stereo2 ADC MIXL", "ADC2 Switch", "Stereo2 ADC L2 Mux"}, 1170 {"Stereo2 ADC MIXL", NULL, "Stereo2 Filter"}, 1171 {"Stereo2 Filter", NULL, "PLL1", is_sysclk_from_pll}, 1172 {"Stereo2 Filter", NULL, "ADC ASRC"}, 1173 1174 {"Stereo2 ADC MIXR", "ADC1 Switch", "Stereo2 ADC R1 Mux"}, 1175 {"Stereo2 ADC MIXR", "ADC2 Switch", "Stereo2 ADC R2 Mux"}, 1176 {"Stereo2 ADC MIXR", NULL, "Stereo2 Filter"}, 1177 1178 {"IF1 ADC2", NULL, "Stereo2 ADC MIXL"}, 1179 {"IF1 ADC2", NULL, "Stereo2 ADC MIXR"}, 1180 {"IF1 ADC1", NULL, "Stereo1 ADC MIXL"}, 1181 {"IF1 ADC1", NULL, "Stereo1 ADC MIXR"}, 1182 1183 {"IF1 ADC1", NULL, "I2S1"}, 1184 1185 {"IF2 ADC", "IF1 ADC1", "IF1 ADC1"}, 1186 {"IF2 ADC", "IF1 ADC2", "IF1 ADC2"}, 1187 {"IF2 ADC", NULL, "I2S2"}, 1188 1189 {"AIF1TX", NULL, "IF1 ADC1"}, 1190 {"AIF1TX", NULL, "IF1 ADC2"}, 1191 {"AIF2TX", NULL, "IF2 ADC"}, 1192 1193 {"IF1 DAC", NULL, "AIF1RX"}, 1194 {"IF1 DAC", NULL, "I2S1"}, 1195 {"IF2 DAC", NULL, "AIF2RX"}, 1196 {"IF2 DAC", NULL, "I2S2"}, 1197 1198 {"IF1 DAC1 L", NULL, "IF1 DAC"}, 1199 {"IF1 DAC1 R", NULL, "IF1 DAC"}, 1200 {"IF1 DAC2 L", NULL, "IF1 DAC"}, 1201 {"IF1 DAC2 R", NULL, "IF1 DAC"}, 1202 {"IF2 DAC L", NULL, "IF2 DAC"}, 1203 {"IF2 DAC R", NULL, "IF2 DAC"}, 1204 1205 {"DAC MIXL", "Stereo ADC Switch", "Stereo1 ADC MIXL"}, 1206 {"DAC MIXL", "INF1 Switch", "IF1 DAC1 L"}, 1207 {"DAC MIXR", "Stereo ADC Switch", "Stereo1 ADC MIXR"}, 1208 {"DAC MIXR", "INF1 Switch", "IF1 DAC1 R"}, 1209 1210 {"Audio DSP", NULL, "DAC MIXL"}, 1211 {"Audio DSP", NULL, "DAC MIXR"}, 1212 1213 {"DAC L2 Mux", "IF1", "IF1 DAC2 L"}, 1214 {"DAC L2 Mux", "IF2", "IF2 DAC L"}, 1215 {"DAC L2 Volume", NULL, "DAC L2 Mux"}, 1216 1217 {"DAC R2 Mux", "IF1", "IF1 DAC2 R"}, 1218 {"DAC R2 Mux", "IF2", "IF2 DAC R"}, 1219 {"DAC R2 Volume", NULL, "DAC R2 Mux"}, 1220 1221 {"Stereo DAC MIXL", "DAC L1 Switch", "Audio DSP"}, 1222 {"Stereo DAC MIXL", "DAC L2 Switch", "DAC L2 Volume"}, 1223 {"Stereo DAC MIXL", "DAC R1 Switch", "DAC MIXR"}, 1224 {"Stereo DAC MIXL", NULL, "Stero1 DAC Power"}, 1225 {"Stereo DAC MIXL", NULL, "Stero2 DAC Power"}, 1226 {"Stereo DAC MIXR", "DAC R1 Switch", "Audio DSP"}, 1227 {"Stereo DAC MIXR", "DAC R2 Switch", "DAC R2 Volume"}, 1228 {"Stereo DAC MIXR", "DAC L1 Switch", "DAC MIXL"}, 1229 {"Stereo DAC MIXR", NULL, "Stero1 DAC Power"}, 1230 {"Stereo DAC MIXR", NULL, "Stero2 DAC Power"}, 1231 1232 {"PDM L Mux", "Stereo DAC MIX", "Stereo DAC MIXL"}, 1233 {"PDM L Mux", "DD MIX", "DAC MIXL"}, 1234 {"PDM R Mux", "Stereo DAC MIX", "Stereo DAC MIXR"}, 1235 {"PDM R Mux", "DD MIX", "DAC MIXR"}, 1236 1237 {"DAC L1", NULL, "Stereo DAC MIXL"}, 1238 {"DAC L1", NULL, "PLL1", is_sysclk_from_pll}, 1239 {"DAC L1", NULL, "DAC L1 Power"}, 1240 {"DAC R1", NULL, "Stereo DAC MIXR"}, 1241 {"DAC R1", NULL, "PLL1", is_sysclk_from_pll}, 1242 {"DAC R1", NULL, "DAC R1 Power"}, 1243 1244 {"DD MIXL", "DAC L1 Switch", "DAC MIXL"}, 1245 {"DD MIXL", "DAC L2 Switch", "DAC L2 Volume"}, 1246 {"DD MIXL", "DAC R2 Switch", "DAC R2 Volume"}, 1247 {"DD MIXL", NULL, "Stero2 DAC Power"}, 1248 1249 {"DD MIXR", "DAC R1 Switch", "DAC MIXR"}, 1250 {"DD MIXR", "DAC R2 Switch", "DAC R2 Volume"}, 1251 {"DD MIXR", "DAC L2 Switch", "DAC L2 Volume"}, 1252 {"DD MIXR", NULL, "Stero2 DAC Power"}, 1253 1254 {"OUT MIXL", "BST1 Switch", "BST1"}, 1255 {"OUT MIXL", "BST2 Switch", "BST2"}, 1256 {"OUT MIXL", "INL1 Switch", "INL1 VOL"}, 1257 {"OUT MIXL", "REC MIXL Switch", "RECMIXL"}, 1258 {"OUT MIXL", "DAC L1 Switch", "DAC L1"}, 1259 1260 {"OUT MIXR", "BST2 Switch", "BST2"}, 1261 {"OUT MIXR", "BST1 Switch", "BST1"}, 1262 {"OUT MIXR", "INR1 Switch", "INR1 VOL"}, 1263 {"OUT MIXR", "REC MIXR Switch", "RECMIXR"}, 1264 {"OUT MIXR", "DAC R1 Switch", "DAC R1"}, 1265 1266 {"HPOVOL L", "Switch", "OUT MIXL"}, 1267 {"HPOVOL R", "Switch", "OUT MIXR"}, 1268 {"OUTVOL L", "Switch", "OUT MIXL"}, 1269 {"OUTVOL R", "Switch", "OUT MIXR"}, 1270 1271 {"HPOL MIX", "HPO MIX DAC1 Switch", "DAC L1"}, 1272 {"HPOL MIX", "HPO MIX HPVOL Switch", "HPOVOL L"}, 1273 {"HPOL MIX", NULL, "HP L Amp"}, 1274 {"HPOR MIX", "HPO MIX DAC1 Switch", "DAC R1"}, 1275 {"HPOR MIX", "HPO MIX HPVOL Switch", "HPOVOL R"}, 1276 {"HPOR MIX", NULL, "HP R Amp"}, 1277 1278 {"LOUT MIX", "DAC L1 Switch", "DAC L1"}, 1279 {"LOUT MIX", "DAC R1 Switch", "DAC R1"}, 1280 {"LOUT MIX", "OUTVOL L Switch", "OUTVOL L"}, 1281 {"LOUT MIX", "OUTVOL R Switch", "OUTVOL R"}, 1282 1283 {"HP Amp", NULL, "HPOL MIX"}, 1284 {"HP Amp", NULL, "HPOR MIX"}, 1285 {"HP Amp", NULL, "Amp Power"}, 1286 {"HPO L Playback", "Switch", "HP Amp"}, 1287 {"HPO R Playback", "Switch", "HP Amp"}, 1288 {"HPOL", NULL, "HPO L Playback"}, 1289 {"HPOR", NULL, "HPO R Playback"}, 1290 1291 {"LOUT L Playback", "Switch", "LOUT MIX"}, 1292 {"LOUT R Playback", "Switch", "LOUT MIX"}, 1293 {"LOUTL", NULL, "LOUT L Playback"}, 1294 {"LOUTL", NULL, "Amp Power"}, 1295 {"LOUTR", NULL, "LOUT R Playback"}, 1296 {"LOUTR", NULL, "Amp Power"}, 1297 1298 {"PDML", NULL, "PDM L Mux"}, 1299 {"PDMR", NULL, "PDM R Mux"}, 1300 }; 1301 1302 static int rt5651_hw_params(struct snd_pcm_substream *substream, 1303 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) 1304 { 1305 struct snd_soc_codec *codec = dai->codec; 1306 struct rt5651_priv *rt5651 = snd_soc_codec_get_drvdata(codec); 1307 unsigned int val_len = 0, val_clk, mask_clk; 1308 int pre_div, bclk_ms, frame_size; 1309 1310 rt5651->lrck[dai->id] = params_rate(params); 1311 pre_div = rl6231_get_clk_info(rt5651->sysclk, rt5651->lrck[dai->id]); 1312 1313 if (pre_div < 0) { 1314 dev_err(codec->dev, "Unsupported clock setting\n"); 1315 return -EINVAL; 1316 } 1317 frame_size = snd_soc_params_to_frame_size(params); 1318 if (frame_size < 0) { 1319 dev_err(codec->dev, "Unsupported frame size: %d\n", frame_size); 1320 return -EINVAL; 1321 } 1322 bclk_ms = frame_size > 32 ? 1 : 0; 1323 rt5651->bclk[dai->id] = rt5651->lrck[dai->id] * (32 << bclk_ms); 1324 1325 dev_dbg(dai->dev, "bclk is %dHz and lrck is %dHz\n", 1326 rt5651->bclk[dai->id], rt5651->lrck[dai->id]); 1327 dev_dbg(dai->dev, "bclk_ms is %d and pre_div is %d for iis %d\n", 1328 bclk_ms, pre_div, dai->id); 1329 1330 switch (params_width(params)) { 1331 case 16: 1332 break; 1333 case 20: 1334 val_len |= RT5651_I2S_DL_20; 1335 break; 1336 case 24: 1337 val_len |= RT5651_I2S_DL_24; 1338 break; 1339 case 8: 1340 val_len |= RT5651_I2S_DL_8; 1341 break; 1342 default: 1343 return -EINVAL; 1344 } 1345 1346 switch (dai->id) { 1347 case RT5651_AIF1: 1348 mask_clk = RT5651_I2S_PD1_MASK; 1349 val_clk = pre_div << RT5651_I2S_PD1_SFT; 1350 snd_soc_update_bits(codec, RT5651_I2S1_SDP, 1351 RT5651_I2S_DL_MASK, val_len); 1352 snd_soc_update_bits(codec, RT5651_ADDA_CLK1, mask_clk, val_clk); 1353 break; 1354 case RT5651_AIF2: 1355 mask_clk = RT5651_I2S_BCLK_MS2_MASK | RT5651_I2S_PD2_MASK; 1356 val_clk = pre_div << RT5651_I2S_PD2_SFT; 1357 snd_soc_update_bits(codec, RT5651_I2S2_SDP, 1358 RT5651_I2S_DL_MASK, val_len); 1359 snd_soc_update_bits(codec, RT5651_ADDA_CLK1, mask_clk, val_clk); 1360 break; 1361 default: 1362 dev_err(codec->dev, "Wrong dai->id: %d\n", dai->id); 1363 return -EINVAL; 1364 } 1365 1366 return 0; 1367 } 1368 1369 static int rt5651_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) 1370 { 1371 struct snd_soc_codec *codec = dai->codec; 1372 struct rt5651_priv *rt5651 = snd_soc_codec_get_drvdata(codec); 1373 unsigned int reg_val = 0; 1374 1375 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 1376 case SND_SOC_DAIFMT_CBM_CFM: 1377 rt5651->master[dai->id] = 1; 1378 break; 1379 case SND_SOC_DAIFMT_CBS_CFS: 1380 reg_val |= RT5651_I2S_MS_S; 1381 rt5651->master[dai->id] = 0; 1382 break; 1383 default: 1384 return -EINVAL; 1385 } 1386 1387 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 1388 case SND_SOC_DAIFMT_NB_NF: 1389 break; 1390 case SND_SOC_DAIFMT_IB_NF: 1391 reg_val |= RT5651_I2S_BP_INV; 1392 break; 1393 default: 1394 return -EINVAL; 1395 } 1396 1397 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1398 case SND_SOC_DAIFMT_I2S: 1399 break; 1400 case SND_SOC_DAIFMT_LEFT_J: 1401 reg_val |= RT5651_I2S_DF_LEFT; 1402 break; 1403 case SND_SOC_DAIFMT_DSP_A: 1404 reg_val |= RT5651_I2S_DF_PCM_A; 1405 break; 1406 case SND_SOC_DAIFMT_DSP_B: 1407 reg_val |= RT5651_I2S_DF_PCM_B; 1408 break; 1409 default: 1410 return -EINVAL; 1411 } 1412 1413 switch (dai->id) { 1414 case RT5651_AIF1: 1415 snd_soc_update_bits(codec, RT5651_I2S1_SDP, 1416 RT5651_I2S_MS_MASK | RT5651_I2S_BP_MASK | 1417 RT5651_I2S_DF_MASK, reg_val); 1418 break; 1419 case RT5651_AIF2: 1420 snd_soc_update_bits(codec, RT5651_I2S2_SDP, 1421 RT5651_I2S_MS_MASK | RT5651_I2S_BP_MASK | 1422 RT5651_I2S_DF_MASK, reg_val); 1423 break; 1424 default: 1425 dev_err(codec->dev, "Wrong dai->id: %d\n", dai->id); 1426 return -EINVAL; 1427 } 1428 return 0; 1429 } 1430 1431 static int rt5651_set_dai_sysclk(struct snd_soc_dai *dai, 1432 int clk_id, unsigned int freq, int dir) 1433 { 1434 struct snd_soc_codec *codec = dai->codec; 1435 struct rt5651_priv *rt5651 = snd_soc_codec_get_drvdata(codec); 1436 unsigned int reg_val = 0; 1437 1438 if (freq == rt5651->sysclk && clk_id == rt5651->sysclk_src) 1439 return 0; 1440 1441 switch (clk_id) { 1442 case RT5651_SCLK_S_MCLK: 1443 reg_val |= RT5651_SCLK_SRC_MCLK; 1444 break; 1445 case RT5651_SCLK_S_PLL1: 1446 reg_val |= RT5651_SCLK_SRC_PLL1; 1447 break; 1448 case RT5651_SCLK_S_RCCLK: 1449 reg_val |= RT5651_SCLK_SRC_RCCLK; 1450 break; 1451 default: 1452 dev_err(codec->dev, "Invalid clock id (%d)\n", clk_id); 1453 return -EINVAL; 1454 } 1455 snd_soc_update_bits(codec, RT5651_GLB_CLK, 1456 RT5651_SCLK_SRC_MASK, reg_val); 1457 rt5651->sysclk = freq; 1458 rt5651->sysclk_src = clk_id; 1459 1460 dev_dbg(dai->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id); 1461 1462 return 0; 1463 } 1464 1465 static int rt5651_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source, 1466 unsigned int freq_in, unsigned int freq_out) 1467 { 1468 struct snd_soc_codec *codec = dai->codec; 1469 struct rt5651_priv *rt5651 = snd_soc_codec_get_drvdata(codec); 1470 struct rl6231_pll_code pll_code; 1471 int ret; 1472 1473 if (source == rt5651->pll_src && freq_in == rt5651->pll_in && 1474 freq_out == rt5651->pll_out) 1475 return 0; 1476 1477 if (!freq_in || !freq_out) { 1478 dev_dbg(codec->dev, "PLL disabled\n"); 1479 1480 rt5651->pll_in = 0; 1481 rt5651->pll_out = 0; 1482 snd_soc_update_bits(codec, RT5651_GLB_CLK, 1483 RT5651_SCLK_SRC_MASK, RT5651_SCLK_SRC_MCLK); 1484 return 0; 1485 } 1486 1487 switch (source) { 1488 case RT5651_PLL1_S_MCLK: 1489 snd_soc_update_bits(codec, RT5651_GLB_CLK, 1490 RT5651_PLL1_SRC_MASK, RT5651_PLL1_SRC_MCLK); 1491 break; 1492 case RT5651_PLL1_S_BCLK1: 1493 snd_soc_update_bits(codec, RT5651_GLB_CLK, 1494 RT5651_PLL1_SRC_MASK, RT5651_PLL1_SRC_BCLK1); 1495 break; 1496 case RT5651_PLL1_S_BCLK2: 1497 snd_soc_update_bits(codec, RT5651_GLB_CLK, 1498 RT5651_PLL1_SRC_MASK, RT5651_PLL1_SRC_BCLK2); 1499 break; 1500 default: 1501 dev_err(codec->dev, "Unknown PLL source %d\n", source); 1502 return -EINVAL; 1503 } 1504 1505 ret = rl6231_pll_calc(freq_in, freq_out, &pll_code); 1506 if (ret < 0) { 1507 dev_err(codec->dev, "Unsupport input clock %d\n", freq_in); 1508 return ret; 1509 } 1510 1511 dev_dbg(codec->dev, "bypass=%d m=%d n=%d k=%d\n", 1512 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code), 1513 pll_code.n_code, pll_code.k_code); 1514 1515 snd_soc_write(codec, RT5651_PLL_CTRL1, 1516 pll_code.n_code << RT5651_PLL_N_SFT | pll_code.k_code); 1517 snd_soc_write(codec, RT5651_PLL_CTRL2, 1518 (pll_code.m_bp ? 0 : pll_code.m_code) << RT5651_PLL_M_SFT | 1519 pll_code.m_bp << RT5651_PLL_M_BP_SFT); 1520 1521 rt5651->pll_in = freq_in; 1522 rt5651->pll_out = freq_out; 1523 rt5651->pll_src = source; 1524 1525 return 0; 1526 } 1527 1528 static int rt5651_set_bias_level(struct snd_soc_codec *codec, 1529 enum snd_soc_bias_level level) 1530 { 1531 switch (level) { 1532 case SND_SOC_BIAS_PREPARE: 1533 if (SND_SOC_BIAS_STANDBY == snd_soc_codec_get_bias_level(codec)) { 1534 snd_soc_update_bits(codec, RT5651_PWR_ANLG1, 1535 RT5651_PWR_VREF1 | RT5651_PWR_MB | 1536 RT5651_PWR_BG | RT5651_PWR_VREF2, 1537 RT5651_PWR_VREF1 | RT5651_PWR_MB | 1538 RT5651_PWR_BG | RT5651_PWR_VREF2); 1539 usleep_range(10000, 15000); 1540 snd_soc_update_bits(codec, RT5651_PWR_ANLG1, 1541 RT5651_PWR_FV1 | RT5651_PWR_FV2, 1542 RT5651_PWR_FV1 | RT5651_PWR_FV2); 1543 snd_soc_update_bits(codec, RT5651_PWR_ANLG1, 1544 RT5651_PWR_LDO_DVO_MASK, 1545 RT5651_PWR_LDO_DVO_1_2V); 1546 snd_soc_update_bits(codec, RT5651_D_MISC, 0x1, 0x1); 1547 if (snd_soc_read(codec, RT5651_PLL_MODE_1) & 0x9200) 1548 snd_soc_update_bits(codec, RT5651_D_MISC, 1549 0xc00, 0xc00); 1550 } 1551 break; 1552 1553 case SND_SOC_BIAS_STANDBY: 1554 snd_soc_write(codec, RT5651_D_MISC, 0x0010); 1555 snd_soc_write(codec, RT5651_PWR_DIG1, 0x0000); 1556 snd_soc_write(codec, RT5651_PWR_DIG2, 0x0000); 1557 snd_soc_write(codec, RT5651_PWR_VOL, 0x0000); 1558 snd_soc_write(codec, RT5651_PWR_MIXER, 0x0000); 1559 snd_soc_write(codec, RT5651_PWR_ANLG1, 0x0000); 1560 snd_soc_write(codec, RT5651_PWR_ANLG2, 0x0000); 1561 break; 1562 1563 default: 1564 break; 1565 } 1566 1567 return 0; 1568 } 1569 1570 static int rt5651_probe(struct snd_soc_codec *codec) 1571 { 1572 struct rt5651_priv *rt5651 = snd_soc_codec_get_drvdata(codec); 1573 1574 rt5651->codec = codec; 1575 1576 snd_soc_update_bits(codec, RT5651_PWR_ANLG1, 1577 RT5651_PWR_VREF1 | RT5651_PWR_MB | 1578 RT5651_PWR_BG | RT5651_PWR_VREF2, 1579 RT5651_PWR_VREF1 | RT5651_PWR_MB | 1580 RT5651_PWR_BG | RT5651_PWR_VREF2); 1581 usleep_range(10000, 15000); 1582 snd_soc_update_bits(codec, RT5651_PWR_ANLG1, 1583 RT5651_PWR_FV1 | RT5651_PWR_FV2, 1584 RT5651_PWR_FV1 | RT5651_PWR_FV2); 1585 1586 snd_soc_codec_force_bias_level(codec, SND_SOC_BIAS_OFF); 1587 1588 return 0; 1589 } 1590 1591 #ifdef CONFIG_PM 1592 static int rt5651_suspend(struct snd_soc_codec *codec) 1593 { 1594 struct rt5651_priv *rt5651 = snd_soc_codec_get_drvdata(codec); 1595 1596 regcache_cache_only(rt5651->regmap, true); 1597 regcache_mark_dirty(rt5651->regmap); 1598 return 0; 1599 } 1600 1601 static int rt5651_resume(struct snd_soc_codec *codec) 1602 { 1603 struct rt5651_priv *rt5651 = snd_soc_codec_get_drvdata(codec); 1604 1605 regcache_cache_only(rt5651->regmap, false); 1606 snd_soc_cache_sync(codec); 1607 1608 return 0; 1609 } 1610 #else 1611 #define rt5651_suspend NULL 1612 #define rt5651_resume NULL 1613 #endif 1614 1615 #define RT5651_STEREO_RATES SNDRV_PCM_RATE_8000_96000 1616 #define RT5651_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ 1617 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8) 1618 1619 static const struct snd_soc_dai_ops rt5651_aif_dai_ops = { 1620 .hw_params = rt5651_hw_params, 1621 .set_fmt = rt5651_set_dai_fmt, 1622 .set_sysclk = rt5651_set_dai_sysclk, 1623 .set_pll = rt5651_set_dai_pll, 1624 }; 1625 1626 static struct snd_soc_dai_driver rt5651_dai[] = { 1627 { 1628 .name = "rt5651-aif1", 1629 .id = RT5651_AIF1, 1630 .playback = { 1631 .stream_name = "AIF1 Playback", 1632 .channels_min = 1, 1633 .channels_max = 2, 1634 .rates = RT5651_STEREO_RATES, 1635 .formats = RT5651_FORMATS, 1636 }, 1637 .capture = { 1638 .stream_name = "AIF1 Capture", 1639 .channels_min = 1, 1640 .channels_max = 2, 1641 .rates = RT5651_STEREO_RATES, 1642 .formats = RT5651_FORMATS, 1643 }, 1644 .ops = &rt5651_aif_dai_ops, 1645 }, 1646 { 1647 .name = "rt5651-aif2", 1648 .id = RT5651_AIF2, 1649 .playback = { 1650 .stream_name = "AIF2 Playback", 1651 .channels_min = 1, 1652 .channels_max = 2, 1653 .rates = RT5651_STEREO_RATES, 1654 .formats = RT5651_FORMATS, 1655 }, 1656 .capture = { 1657 .stream_name = "AIF2 Capture", 1658 .channels_min = 1, 1659 .channels_max = 2, 1660 .rates = RT5651_STEREO_RATES, 1661 .formats = RT5651_FORMATS, 1662 }, 1663 .ops = &rt5651_aif_dai_ops, 1664 }, 1665 }; 1666 1667 static struct snd_soc_codec_driver soc_codec_dev_rt5651 = { 1668 .probe = rt5651_probe, 1669 .suspend = rt5651_suspend, 1670 .resume = rt5651_resume, 1671 .set_bias_level = rt5651_set_bias_level, 1672 .idle_bias_off = true, 1673 .component_driver = { 1674 .controls = rt5651_snd_controls, 1675 .num_controls = ARRAY_SIZE(rt5651_snd_controls), 1676 .dapm_widgets = rt5651_dapm_widgets, 1677 .num_dapm_widgets = ARRAY_SIZE(rt5651_dapm_widgets), 1678 .dapm_routes = rt5651_dapm_routes, 1679 .num_dapm_routes = ARRAY_SIZE(rt5651_dapm_routes), 1680 }, 1681 }; 1682 1683 static const struct regmap_config rt5651_regmap = { 1684 .reg_bits = 8, 1685 .val_bits = 16, 1686 1687 .max_register = RT5651_DEVICE_ID + 1 + (ARRAY_SIZE(rt5651_ranges) * 1688 RT5651_PR_SPACING), 1689 .volatile_reg = rt5651_volatile_register, 1690 .readable_reg = rt5651_readable_register, 1691 1692 .cache_type = REGCACHE_RBTREE, 1693 .reg_defaults = rt5651_reg, 1694 .num_reg_defaults = ARRAY_SIZE(rt5651_reg), 1695 .ranges = rt5651_ranges, 1696 .num_ranges = ARRAY_SIZE(rt5651_ranges), 1697 }; 1698 1699 #if defined(CONFIG_OF) 1700 static const struct of_device_id rt5651_of_match[] = { 1701 { .compatible = "realtek,rt5651", }, 1702 {}, 1703 }; 1704 MODULE_DEVICE_TABLE(of, rt5651_of_match); 1705 #endif 1706 1707 #ifdef CONFIG_ACPI 1708 static const struct acpi_device_id rt5651_acpi_match[] = { 1709 { "10EC5651", 0 }, 1710 { }, 1711 }; 1712 MODULE_DEVICE_TABLE(acpi, rt5651_acpi_match); 1713 #endif 1714 1715 static const struct i2c_device_id rt5651_i2c_id[] = { 1716 { "rt5651", 0 }, 1717 { } 1718 }; 1719 MODULE_DEVICE_TABLE(i2c, rt5651_i2c_id); 1720 1721 static int rt5651_parse_dt(struct rt5651_priv *rt5651, struct device_node *np) 1722 { 1723 rt5651->pdata.in2_diff = of_property_read_bool(np, 1724 "realtek,in2-differential"); 1725 rt5651->pdata.dmic_en = of_property_read_bool(np, 1726 "realtek,dmic-en"); 1727 1728 return 0; 1729 } 1730 1731 static int rt5651_i2c_probe(struct i2c_client *i2c, 1732 const struct i2c_device_id *id) 1733 { 1734 struct rt5651_platform_data *pdata = dev_get_platdata(&i2c->dev); 1735 struct rt5651_priv *rt5651; 1736 int ret; 1737 1738 rt5651 = devm_kzalloc(&i2c->dev, sizeof(*rt5651), 1739 GFP_KERNEL); 1740 if (NULL == rt5651) 1741 return -ENOMEM; 1742 1743 i2c_set_clientdata(i2c, rt5651); 1744 1745 if (pdata) 1746 rt5651->pdata = *pdata; 1747 else if (i2c->dev.of_node) 1748 rt5651_parse_dt(rt5651, i2c->dev.of_node); 1749 1750 rt5651->regmap = devm_regmap_init_i2c(i2c, &rt5651_regmap); 1751 if (IS_ERR(rt5651->regmap)) { 1752 ret = PTR_ERR(rt5651->regmap); 1753 dev_err(&i2c->dev, "Failed to allocate register map: %d\n", 1754 ret); 1755 return ret; 1756 } 1757 1758 regmap_read(rt5651->regmap, RT5651_DEVICE_ID, &ret); 1759 if (ret != RT5651_DEVICE_ID_VALUE) { 1760 dev_err(&i2c->dev, 1761 "Device with ID register %#x is not rt5651\n", ret); 1762 return -ENODEV; 1763 } 1764 1765 regmap_write(rt5651->regmap, RT5651_RESET, 0); 1766 1767 ret = regmap_register_patch(rt5651->regmap, init_list, 1768 ARRAY_SIZE(init_list)); 1769 if (ret != 0) 1770 dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret); 1771 1772 if (rt5651->pdata.in2_diff) 1773 regmap_update_bits(rt5651->regmap, RT5651_IN1_IN2, 1774 RT5651_IN_DF2, RT5651_IN_DF2); 1775 1776 if (rt5651->pdata.dmic_en) 1777 regmap_update_bits(rt5651->regmap, RT5651_GPIO_CTRL1, 1778 RT5651_GP2_PIN_MASK, RT5651_GP2_PIN_DMIC1_SCL); 1779 1780 rt5651->hp_mute = 1; 1781 1782 ret = snd_soc_register_codec(&i2c->dev, &soc_codec_dev_rt5651, 1783 rt5651_dai, ARRAY_SIZE(rt5651_dai)); 1784 1785 return ret; 1786 } 1787 1788 static int rt5651_i2c_remove(struct i2c_client *i2c) 1789 { 1790 snd_soc_unregister_codec(&i2c->dev); 1791 1792 return 0; 1793 } 1794 1795 static struct i2c_driver rt5651_i2c_driver = { 1796 .driver = { 1797 .name = "rt5651", 1798 .acpi_match_table = ACPI_PTR(rt5651_acpi_match), 1799 .of_match_table = of_match_ptr(rt5651_of_match), 1800 }, 1801 .probe = rt5651_i2c_probe, 1802 .remove = rt5651_i2c_remove, 1803 .id_table = rt5651_i2c_id, 1804 }; 1805 module_i2c_driver(rt5651_i2c_driver); 1806 1807 MODULE_DESCRIPTION("ASoC RT5651 driver"); 1808 MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>"); 1809 MODULE_LICENSE("GPL v2"); 1810