1 /* 2 * rt5651.c -- RT5651 ALSA SoC audio codec driver 3 * 4 * Copyright 2014 Realtek Semiconductor Corp. 5 * Author: Bard Liao <bardliao@realtek.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11 12 #include <linux/module.h> 13 #include <linux/moduleparam.h> 14 #include <linux/init.h> 15 #include <linux/delay.h> 16 #include <linux/pm.h> 17 #include <linux/i2c.h> 18 #include <linux/regmap.h> 19 #include <linux/platform_device.h> 20 #include <linux/spi/spi.h> 21 #include <linux/acpi.h> 22 #include <linux/dmi.h> 23 #include <sound/core.h> 24 #include <sound/pcm.h> 25 #include <sound/pcm_params.h> 26 #include <sound/soc.h> 27 #include <sound/soc-dapm.h> 28 #include <sound/initval.h> 29 #include <sound/tlv.h> 30 #include <sound/jack.h> 31 32 #include "rl6231.h" 33 #include "rt5651.h" 34 35 #define RT5651_JD_MAP(quirk) ((quirk) & GENMASK(7, 0)) 36 #define RT5651_IN2_DIFF BIT(16) 37 #define RT5651_DMIC_EN BIT(17) 38 39 #define RT5651_DEVICE_ID_VALUE 0x6281 40 41 #define RT5651_PR_RANGE_BASE (0xff + 1) 42 #define RT5651_PR_SPACING 0x100 43 44 #define RT5651_PR_BASE (RT5651_PR_RANGE_BASE + (0 * RT5651_PR_SPACING)) 45 46 static unsigned long rt5651_quirk; 47 48 static const struct regmap_range_cfg rt5651_ranges[] = { 49 { .name = "PR", .range_min = RT5651_PR_BASE, 50 .range_max = RT5651_PR_BASE + 0xb4, 51 .selector_reg = RT5651_PRIV_INDEX, 52 .selector_mask = 0xff, 53 .selector_shift = 0x0, 54 .window_start = RT5651_PRIV_DATA, 55 .window_len = 0x1, }, 56 }; 57 58 static const struct reg_sequence init_list[] = { 59 {RT5651_PR_BASE + 0x3d, 0x3e00}, 60 }; 61 62 static const struct reg_default rt5651_reg[] = { 63 { 0x00, 0x0000 }, 64 { 0x02, 0xc8c8 }, 65 { 0x03, 0xc8c8 }, 66 { 0x05, 0x0000 }, 67 { 0x0d, 0x0000 }, 68 { 0x0e, 0x0000 }, 69 { 0x0f, 0x0808 }, 70 { 0x10, 0x0808 }, 71 { 0x19, 0xafaf }, 72 { 0x1a, 0xafaf }, 73 { 0x1b, 0x0c00 }, 74 { 0x1c, 0x2f2f }, 75 { 0x1d, 0x2f2f }, 76 { 0x1e, 0x0000 }, 77 { 0x27, 0x7860 }, 78 { 0x28, 0x7070 }, 79 { 0x29, 0x8080 }, 80 { 0x2a, 0x5252 }, 81 { 0x2b, 0x5454 }, 82 { 0x2f, 0x0000 }, 83 { 0x30, 0x5000 }, 84 { 0x3b, 0x0000 }, 85 { 0x3c, 0x006f }, 86 { 0x3d, 0x0000 }, 87 { 0x3e, 0x006f }, 88 { 0x45, 0x6000 }, 89 { 0x4d, 0x0000 }, 90 { 0x4e, 0x0000 }, 91 { 0x4f, 0x0279 }, 92 { 0x50, 0x0000 }, 93 { 0x51, 0x0000 }, 94 { 0x52, 0x0279 }, 95 { 0x53, 0xf000 }, 96 { 0x61, 0x0000 }, 97 { 0x62, 0x0000 }, 98 { 0x63, 0x00c0 }, 99 { 0x64, 0x0000 }, 100 { 0x65, 0x0000 }, 101 { 0x66, 0x0000 }, 102 { 0x70, 0x8000 }, 103 { 0x71, 0x8000 }, 104 { 0x73, 0x1104 }, 105 { 0x74, 0x0c00 }, 106 { 0x75, 0x1400 }, 107 { 0x77, 0x0c00 }, 108 { 0x78, 0x4000 }, 109 { 0x79, 0x0123 }, 110 { 0x80, 0x0000 }, 111 { 0x81, 0x0000 }, 112 { 0x82, 0x0000 }, 113 { 0x83, 0x0800 }, 114 { 0x84, 0x0000 }, 115 { 0x85, 0x0008 }, 116 { 0x89, 0x0000 }, 117 { 0x8e, 0x0004 }, 118 { 0x8f, 0x1100 }, 119 { 0x90, 0x0000 }, 120 { 0x93, 0x2000 }, 121 { 0x94, 0x0200 }, 122 { 0xb0, 0x2080 }, 123 { 0xb1, 0x0000 }, 124 { 0xb4, 0x2206 }, 125 { 0xb5, 0x1f00 }, 126 { 0xb6, 0x0000 }, 127 { 0xbb, 0x0000 }, 128 { 0xbc, 0x0000 }, 129 { 0xbd, 0x0000 }, 130 { 0xbe, 0x0000 }, 131 { 0xbf, 0x0000 }, 132 { 0xc0, 0x0400 }, 133 { 0xc1, 0x0000 }, 134 { 0xc2, 0x0000 }, 135 { 0xcf, 0x0013 }, 136 { 0xd0, 0x0680 }, 137 { 0xd1, 0x1c17 }, 138 { 0xd3, 0xb320 }, 139 { 0xd9, 0x0809 }, 140 { 0xfa, 0x0010 }, 141 { 0xfe, 0x10ec }, 142 { 0xff, 0x6281 }, 143 }; 144 145 static bool rt5651_volatile_register(struct device *dev, unsigned int reg) 146 { 147 int i; 148 149 for (i = 0; i < ARRAY_SIZE(rt5651_ranges); i++) { 150 if ((reg >= rt5651_ranges[i].window_start && 151 reg <= rt5651_ranges[i].window_start + 152 rt5651_ranges[i].window_len) || 153 (reg >= rt5651_ranges[i].range_min && 154 reg <= rt5651_ranges[i].range_max)) { 155 return true; 156 } 157 } 158 159 switch (reg) { 160 case RT5651_RESET: 161 case RT5651_PRIV_DATA: 162 case RT5651_EQ_CTRL1: 163 case RT5651_ALC_1: 164 case RT5651_IRQ_CTRL2: 165 case RT5651_INT_IRQ_ST: 166 case RT5651_PGM_REG_ARR1: 167 case RT5651_PGM_REG_ARR3: 168 case RT5651_VENDOR_ID: 169 case RT5651_DEVICE_ID: 170 return true; 171 default: 172 return false; 173 } 174 } 175 176 static bool rt5651_readable_register(struct device *dev, unsigned int reg) 177 { 178 int i; 179 180 for (i = 0; i < ARRAY_SIZE(rt5651_ranges); i++) { 181 if ((reg >= rt5651_ranges[i].window_start && 182 reg <= rt5651_ranges[i].window_start + 183 rt5651_ranges[i].window_len) || 184 (reg >= rt5651_ranges[i].range_min && 185 reg <= rt5651_ranges[i].range_max)) { 186 return true; 187 } 188 } 189 190 switch (reg) { 191 case RT5651_RESET: 192 case RT5651_VERSION_ID: 193 case RT5651_VENDOR_ID: 194 case RT5651_DEVICE_ID: 195 case RT5651_HP_VOL: 196 case RT5651_LOUT_CTRL1: 197 case RT5651_LOUT_CTRL2: 198 case RT5651_IN1_IN2: 199 case RT5651_IN3: 200 case RT5651_INL1_INR1_VOL: 201 case RT5651_INL2_INR2_VOL: 202 case RT5651_DAC1_DIG_VOL: 203 case RT5651_DAC2_DIG_VOL: 204 case RT5651_DAC2_CTRL: 205 case RT5651_ADC_DIG_VOL: 206 case RT5651_ADC_DATA: 207 case RT5651_ADC_BST_VOL: 208 case RT5651_STO1_ADC_MIXER: 209 case RT5651_STO2_ADC_MIXER: 210 case RT5651_AD_DA_MIXER: 211 case RT5651_STO_DAC_MIXER: 212 case RT5651_DD_MIXER: 213 case RT5651_DIG_INF_DATA: 214 case RT5651_PDM_CTL: 215 case RT5651_REC_L1_MIXER: 216 case RT5651_REC_L2_MIXER: 217 case RT5651_REC_R1_MIXER: 218 case RT5651_REC_R2_MIXER: 219 case RT5651_HPO_MIXER: 220 case RT5651_OUT_L1_MIXER: 221 case RT5651_OUT_L2_MIXER: 222 case RT5651_OUT_L3_MIXER: 223 case RT5651_OUT_R1_MIXER: 224 case RT5651_OUT_R2_MIXER: 225 case RT5651_OUT_R3_MIXER: 226 case RT5651_LOUT_MIXER: 227 case RT5651_PWR_DIG1: 228 case RT5651_PWR_DIG2: 229 case RT5651_PWR_ANLG1: 230 case RT5651_PWR_ANLG2: 231 case RT5651_PWR_MIXER: 232 case RT5651_PWR_VOL: 233 case RT5651_PRIV_INDEX: 234 case RT5651_PRIV_DATA: 235 case RT5651_I2S1_SDP: 236 case RT5651_I2S2_SDP: 237 case RT5651_ADDA_CLK1: 238 case RT5651_ADDA_CLK2: 239 case RT5651_DMIC: 240 case RT5651_TDM_CTL_1: 241 case RT5651_TDM_CTL_2: 242 case RT5651_TDM_CTL_3: 243 case RT5651_GLB_CLK: 244 case RT5651_PLL_CTRL1: 245 case RT5651_PLL_CTRL2: 246 case RT5651_PLL_MODE_1: 247 case RT5651_PLL_MODE_2: 248 case RT5651_PLL_MODE_3: 249 case RT5651_PLL_MODE_4: 250 case RT5651_PLL_MODE_5: 251 case RT5651_PLL_MODE_6: 252 case RT5651_PLL_MODE_7: 253 case RT5651_DEPOP_M1: 254 case RT5651_DEPOP_M2: 255 case RT5651_DEPOP_M3: 256 case RT5651_CHARGE_PUMP: 257 case RT5651_MICBIAS: 258 case RT5651_A_JD_CTL1: 259 case RT5651_EQ_CTRL1: 260 case RT5651_EQ_CTRL2: 261 case RT5651_ALC_1: 262 case RT5651_ALC_2: 263 case RT5651_ALC_3: 264 case RT5651_JD_CTRL1: 265 case RT5651_JD_CTRL2: 266 case RT5651_IRQ_CTRL1: 267 case RT5651_IRQ_CTRL2: 268 case RT5651_INT_IRQ_ST: 269 case RT5651_GPIO_CTRL1: 270 case RT5651_GPIO_CTRL2: 271 case RT5651_GPIO_CTRL3: 272 case RT5651_PGM_REG_ARR1: 273 case RT5651_PGM_REG_ARR2: 274 case RT5651_PGM_REG_ARR3: 275 case RT5651_PGM_REG_ARR4: 276 case RT5651_PGM_REG_ARR5: 277 case RT5651_SCB_FUNC: 278 case RT5651_SCB_CTRL: 279 case RT5651_BASE_BACK: 280 case RT5651_MP3_PLUS1: 281 case RT5651_MP3_PLUS2: 282 case RT5651_ADJ_HPF_CTRL1: 283 case RT5651_ADJ_HPF_CTRL2: 284 case RT5651_HP_CALIB_AMP_DET: 285 case RT5651_HP_CALIB2: 286 case RT5651_SV_ZCD1: 287 case RT5651_SV_ZCD2: 288 case RT5651_D_MISC: 289 case RT5651_DUMMY2: 290 case RT5651_DUMMY3: 291 return true; 292 default: 293 return false; 294 } 295 } 296 297 static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -4650, 150, 0); 298 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -65625, 375, 0); 299 static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -3450, 150, 0); 300 static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -17625, 375, 0); 301 static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0); 302 303 /* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */ 304 static const DECLARE_TLV_DB_RANGE(bst_tlv, 305 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0), 306 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0), 307 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0), 308 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0), 309 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0), 310 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0), 311 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0) 312 ); 313 314 /* Interface data select */ 315 static const char * const rt5651_data_select[] = { 316 "Normal", "Swap", "left copy to right", "right copy to left"}; 317 318 static SOC_ENUM_SINGLE_DECL(rt5651_if2_dac_enum, RT5651_DIG_INF_DATA, 319 RT5651_IF2_DAC_SEL_SFT, rt5651_data_select); 320 321 static SOC_ENUM_SINGLE_DECL(rt5651_if2_adc_enum, RT5651_DIG_INF_DATA, 322 RT5651_IF2_ADC_SEL_SFT, rt5651_data_select); 323 324 static const struct snd_kcontrol_new rt5651_snd_controls[] = { 325 /* Headphone Output Volume */ 326 SOC_DOUBLE_TLV("HP Playback Volume", RT5651_HP_VOL, 327 RT5651_L_VOL_SFT, RT5651_R_VOL_SFT, 39, 1, out_vol_tlv), 328 /* OUTPUT Control */ 329 SOC_DOUBLE_TLV("OUT Playback Volume", RT5651_LOUT_CTRL1, 330 RT5651_L_VOL_SFT, RT5651_R_VOL_SFT, 39, 1, out_vol_tlv), 331 332 /* DAC Digital Volume */ 333 SOC_DOUBLE("DAC2 Playback Switch", RT5651_DAC2_CTRL, 334 RT5651_M_DAC_L2_VOL_SFT, RT5651_M_DAC_R2_VOL_SFT, 1, 1), 335 SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5651_DAC1_DIG_VOL, 336 RT5651_L_VOL_SFT, RT5651_R_VOL_SFT, 337 175, 0, dac_vol_tlv), 338 SOC_DOUBLE_TLV("Mono DAC Playback Volume", RT5651_DAC2_DIG_VOL, 339 RT5651_L_VOL_SFT, RT5651_R_VOL_SFT, 340 175, 0, dac_vol_tlv), 341 /* IN1/IN2 Control */ 342 SOC_SINGLE_TLV("IN1 Boost", RT5651_IN1_IN2, 343 RT5651_BST_SFT1, 8, 0, bst_tlv), 344 SOC_SINGLE_TLV("IN2 Boost", RT5651_IN1_IN2, 345 RT5651_BST_SFT2, 8, 0, bst_tlv), 346 /* INL/INR Volume Control */ 347 SOC_DOUBLE_TLV("IN Capture Volume", RT5651_INL1_INR1_VOL, 348 RT5651_INL_VOL_SFT, RT5651_INR_VOL_SFT, 349 31, 1, in_vol_tlv), 350 /* ADC Digital Volume Control */ 351 SOC_DOUBLE("ADC Capture Switch", RT5651_ADC_DIG_VOL, 352 RT5651_L_MUTE_SFT, RT5651_R_MUTE_SFT, 1, 1), 353 SOC_DOUBLE_TLV("ADC Capture Volume", RT5651_ADC_DIG_VOL, 354 RT5651_L_VOL_SFT, RT5651_R_VOL_SFT, 355 127, 0, adc_vol_tlv), 356 SOC_DOUBLE_TLV("Mono ADC Capture Volume", RT5651_ADC_DATA, 357 RT5651_L_VOL_SFT, RT5651_R_VOL_SFT, 358 127, 0, adc_vol_tlv), 359 /* ADC Boost Volume Control */ 360 SOC_DOUBLE_TLV("ADC Boost Gain", RT5651_ADC_BST_VOL, 361 RT5651_ADC_L_BST_SFT, RT5651_ADC_R_BST_SFT, 362 3, 0, adc_bst_tlv), 363 364 /* ASRC */ 365 SOC_SINGLE("IF1 ASRC Switch", RT5651_PLL_MODE_1, 366 RT5651_STO1_T_SFT, 1, 0), 367 SOC_SINGLE("IF2 ASRC Switch", RT5651_PLL_MODE_1, 368 RT5651_STO2_T_SFT, 1, 0), 369 SOC_SINGLE("DMIC ASRC Switch", RT5651_PLL_MODE_1, 370 RT5651_DMIC_1_M_SFT, 1, 0), 371 372 SOC_ENUM("ADC IF2 Data Switch", rt5651_if2_adc_enum), 373 SOC_ENUM("DAC IF2 Data Switch", rt5651_if2_dac_enum), 374 }; 375 376 /** 377 * set_dmic_clk - Set parameter of dmic. 378 * 379 * @w: DAPM widget. 380 * @kcontrol: The kcontrol of this widget. 381 * @event: Event id. 382 * 383 */ 384 static int set_dmic_clk(struct snd_soc_dapm_widget *w, 385 struct snd_kcontrol *kcontrol, int event) 386 { 387 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); 388 struct rt5651_priv *rt5651 = snd_soc_codec_get_drvdata(codec); 389 int idx, rate; 390 391 rate = rt5651->sysclk / rl6231_get_pre_div(rt5651->regmap, 392 RT5651_ADDA_CLK1, RT5651_I2S_PD1_SFT); 393 idx = rl6231_calc_dmic_clk(rate); 394 if (idx < 0) 395 dev_err(codec->dev, "Failed to set DMIC clock\n"); 396 else 397 snd_soc_update_bits(codec, RT5651_DMIC, RT5651_DMIC_CLK_MASK, 398 idx << RT5651_DMIC_CLK_SFT); 399 400 return idx; 401 } 402 403 static int is_sysclk_from_pll(struct snd_soc_dapm_widget *source, 404 struct snd_soc_dapm_widget *sink) 405 { 406 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(source->dapm); 407 unsigned int val; 408 409 val = snd_soc_read(codec, RT5651_GLB_CLK); 410 val &= RT5651_SCLK_SRC_MASK; 411 if (val == RT5651_SCLK_SRC_PLL1) 412 return 1; 413 else 414 return 0; 415 } 416 417 /* Digital Mixer */ 418 static const struct snd_kcontrol_new rt5651_sto1_adc_l_mix[] = { 419 SOC_DAPM_SINGLE("ADC1 Switch", RT5651_STO1_ADC_MIXER, 420 RT5651_M_STO1_ADC_L1_SFT, 1, 1), 421 SOC_DAPM_SINGLE("ADC2 Switch", RT5651_STO1_ADC_MIXER, 422 RT5651_M_STO1_ADC_L2_SFT, 1, 1), 423 }; 424 425 static const struct snd_kcontrol_new rt5651_sto1_adc_r_mix[] = { 426 SOC_DAPM_SINGLE("ADC1 Switch", RT5651_STO1_ADC_MIXER, 427 RT5651_M_STO1_ADC_R1_SFT, 1, 1), 428 SOC_DAPM_SINGLE("ADC2 Switch", RT5651_STO1_ADC_MIXER, 429 RT5651_M_STO1_ADC_R2_SFT, 1, 1), 430 }; 431 432 static const struct snd_kcontrol_new rt5651_sto2_adc_l_mix[] = { 433 SOC_DAPM_SINGLE("ADC1 Switch", RT5651_STO2_ADC_MIXER, 434 RT5651_M_STO2_ADC_L1_SFT, 1, 1), 435 SOC_DAPM_SINGLE("ADC2 Switch", RT5651_STO2_ADC_MIXER, 436 RT5651_M_STO2_ADC_L2_SFT, 1, 1), 437 }; 438 439 static const struct snd_kcontrol_new rt5651_sto2_adc_r_mix[] = { 440 SOC_DAPM_SINGLE("ADC1 Switch", RT5651_STO2_ADC_MIXER, 441 RT5651_M_STO2_ADC_R1_SFT, 1, 1), 442 SOC_DAPM_SINGLE("ADC2 Switch", RT5651_STO2_ADC_MIXER, 443 RT5651_M_STO2_ADC_R2_SFT, 1, 1), 444 }; 445 446 static const struct snd_kcontrol_new rt5651_dac_l_mix[] = { 447 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5651_AD_DA_MIXER, 448 RT5651_M_ADCMIX_L_SFT, 1, 1), 449 SOC_DAPM_SINGLE("INF1 Switch", RT5651_AD_DA_MIXER, 450 RT5651_M_IF1_DAC_L_SFT, 1, 1), 451 }; 452 453 static const struct snd_kcontrol_new rt5651_dac_r_mix[] = { 454 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5651_AD_DA_MIXER, 455 RT5651_M_ADCMIX_R_SFT, 1, 1), 456 SOC_DAPM_SINGLE("INF1 Switch", RT5651_AD_DA_MIXER, 457 RT5651_M_IF1_DAC_R_SFT, 1, 1), 458 }; 459 460 static const struct snd_kcontrol_new rt5651_sto_dac_l_mix[] = { 461 SOC_DAPM_SINGLE("DAC L1 Switch", RT5651_STO_DAC_MIXER, 462 RT5651_M_DAC_L1_MIXL_SFT, 1, 1), 463 SOC_DAPM_SINGLE("DAC L2 Switch", RT5651_STO_DAC_MIXER, 464 RT5651_M_DAC_L2_MIXL_SFT, 1, 1), 465 SOC_DAPM_SINGLE("DAC R1 Switch", RT5651_STO_DAC_MIXER, 466 RT5651_M_DAC_R1_MIXL_SFT, 1, 1), 467 }; 468 469 static const struct snd_kcontrol_new rt5651_sto_dac_r_mix[] = { 470 SOC_DAPM_SINGLE("DAC R1 Switch", RT5651_STO_DAC_MIXER, 471 RT5651_M_DAC_R1_MIXR_SFT, 1, 1), 472 SOC_DAPM_SINGLE("DAC R2 Switch", RT5651_STO_DAC_MIXER, 473 RT5651_M_DAC_R2_MIXR_SFT, 1, 1), 474 SOC_DAPM_SINGLE("DAC L1 Switch", RT5651_STO_DAC_MIXER, 475 RT5651_M_DAC_L1_MIXR_SFT, 1, 1), 476 }; 477 478 static const struct snd_kcontrol_new rt5651_dd_dac_l_mix[] = { 479 SOC_DAPM_SINGLE("DAC L1 Switch", RT5651_DD_MIXER, 480 RT5651_M_STO_DD_L1_SFT, 1, 1), 481 SOC_DAPM_SINGLE("DAC L2 Switch", RT5651_DD_MIXER, 482 RT5651_M_STO_DD_L2_SFT, 1, 1), 483 SOC_DAPM_SINGLE("DAC R2 Switch", RT5651_DD_MIXER, 484 RT5651_M_STO_DD_R2_L_SFT, 1, 1), 485 }; 486 487 static const struct snd_kcontrol_new rt5651_dd_dac_r_mix[] = { 488 SOC_DAPM_SINGLE("DAC R1 Switch", RT5651_DD_MIXER, 489 RT5651_M_STO_DD_R1_SFT, 1, 1), 490 SOC_DAPM_SINGLE("DAC R2 Switch", RT5651_DD_MIXER, 491 RT5651_M_STO_DD_R2_SFT, 1, 1), 492 SOC_DAPM_SINGLE("DAC L2 Switch", RT5651_DD_MIXER, 493 RT5651_M_STO_DD_L2_R_SFT, 1, 1), 494 }; 495 496 /* Analog Input Mixer */ 497 static const struct snd_kcontrol_new rt5651_rec_l_mix[] = { 498 SOC_DAPM_SINGLE("INL1 Switch", RT5651_REC_L2_MIXER, 499 RT5651_M_IN1_L_RM_L_SFT, 1, 1), 500 SOC_DAPM_SINGLE("BST3 Switch", RT5651_REC_L2_MIXER, 501 RT5651_M_BST3_RM_L_SFT, 1, 1), 502 SOC_DAPM_SINGLE("BST2 Switch", RT5651_REC_L2_MIXER, 503 RT5651_M_BST2_RM_L_SFT, 1, 1), 504 SOC_DAPM_SINGLE("BST1 Switch", RT5651_REC_L2_MIXER, 505 RT5651_M_BST1_RM_L_SFT, 1, 1), 506 }; 507 508 static const struct snd_kcontrol_new rt5651_rec_r_mix[] = { 509 SOC_DAPM_SINGLE("INR1 Switch", RT5651_REC_R2_MIXER, 510 RT5651_M_IN1_R_RM_R_SFT, 1, 1), 511 SOC_DAPM_SINGLE("BST3 Switch", RT5651_REC_R2_MIXER, 512 RT5651_M_BST3_RM_R_SFT, 1, 1), 513 SOC_DAPM_SINGLE("BST2 Switch", RT5651_REC_R2_MIXER, 514 RT5651_M_BST2_RM_R_SFT, 1, 1), 515 SOC_DAPM_SINGLE("BST1 Switch", RT5651_REC_R2_MIXER, 516 RT5651_M_BST1_RM_R_SFT, 1, 1), 517 }; 518 519 /* Analog Output Mixer */ 520 521 static const struct snd_kcontrol_new rt5651_out_l_mix[] = { 522 SOC_DAPM_SINGLE("BST1 Switch", RT5651_OUT_L3_MIXER, 523 RT5651_M_BST1_OM_L_SFT, 1, 1), 524 SOC_DAPM_SINGLE("BST2 Switch", RT5651_OUT_L3_MIXER, 525 RT5651_M_BST2_OM_L_SFT, 1, 1), 526 SOC_DAPM_SINGLE("INL1 Switch", RT5651_OUT_L3_MIXER, 527 RT5651_M_IN1_L_OM_L_SFT, 1, 1), 528 SOC_DAPM_SINGLE("REC MIXL Switch", RT5651_OUT_L3_MIXER, 529 RT5651_M_RM_L_OM_L_SFT, 1, 1), 530 SOC_DAPM_SINGLE("DAC L1 Switch", RT5651_OUT_L3_MIXER, 531 RT5651_M_DAC_L1_OM_L_SFT, 1, 1), 532 }; 533 534 static const struct snd_kcontrol_new rt5651_out_r_mix[] = { 535 SOC_DAPM_SINGLE("BST2 Switch", RT5651_OUT_R3_MIXER, 536 RT5651_M_BST2_OM_R_SFT, 1, 1), 537 SOC_DAPM_SINGLE("BST1 Switch", RT5651_OUT_R3_MIXER, 538 RT5651_M_BST1_OM_R_SFT, 1, 1), 539 SOC_DAPM_SINGLE("INR1 Switch", RT5651_OUT_R3_MIXER, 540 RT5651_M_IN1_R_OM_R_SFT, 1, 1), 541 SOC_DAPM_SINGLE("REC MIXR Switch", RT5651_OUT_R3_MIXER, 542 RT5651_M_RM_R_OM_R_SFT, 1, 1), 543 SOC_DAPM_SINGLE("DAC R1 Switch", RT5651_OUT_R3_MIXER, 544 RT5651_M_DAC_R1_OM_R_SFT, 1, 1), 545 }; 546 547 static const struct snd_kcontrol_new rt5651_hpo_mix[] = { 548 SOC_DAPM_SINGLE("HPO MIX DAC1 Switch", RT5651_HPO_MIXER, 549 RT5651_M_DAC1_HM_SFT, 1, 1), 550 SOC_DAPM_SINGLE("HPO MIX HPVOL Switch", RT5651_HPO_MIXER, 551 RT5651_M_HPVOL_HM_SFT, 1, 1), 552 }; 553 554 static const struct snd_kcontrol_new rt5651_lout_mix[] = { 555 SOC_DAPM_SINGLE("DAC L1 Switch", RT5651_LOUT_MIXER, 556 RT5651_M_DAC_L1_LM_SFT, 1, 1), 557 SOC_DAPM_SINGLE("DAC R1 Switch", RT5651_LOUT_MIXER, 558 RT5651_M_DAC_R1_LM_SFT, 1, 1), 559 SOC_DAPM_SINGLE("OUTVOL L Switch", RT5651_LOUT_MIXER, 560 RT5651_M_OV_L_LM_SFT, 1, 1), 561 SOC_DAPM_SINGLE("OUTVOL R Switch", RT5651_LOUT_MIXER, 562 RT5651_M_OV_R_LM_SFT, 1, 1), 563 }; 564 565 static const struct snd_kcontrol_new outvol_l_control = 566 SOC_DAPM_SINGLE("Switch", RT5651_LOUT_CTRL1, 567 RT5651_VOL_L_SFT, 1, 1); 568 569 static const struct snd_kcontrol_new outvol_r_control = 570 SOC_DAPM_SINGLE("Switch", RT5651_LOUT_CTRL1, 571 RT5651_VOL_R_SFT, 1, 1); 572 573 static const struct snd_kcontrol_new lout_l_mute_control = 574 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5651_LOUT_CTRL1, 575 RT5651_L_MUTE_SFT, 1, 1); 576 577 static const struct snd_kcontrol_new lout_r_mute_control = 578 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5651_LOUT_CTRL1, 579 RT5651_R_MUTE_SFT, 1, 1); 580 581 static const struct snd_kcontrol_new hpovol_l_control = 582 SOC_DAPM_SINGLE("Switch", RT5651_HP_VOL, 583 RT5651_VOL_L_SFT, 1, 1); 584 585 static const struct snd_kcontrol_new hpovol_r_control = 586 SOC_DAPM_SINGLE("Switch", RT5651_HP_VOL, 587 RT5651_VOL_R_SFT, 1, 1); 588 589 static const struct snd_kcontrol_new hpo_l_mute_control = 590 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5651_HP_VOL, 591 RT5651_L_MUTE_SFT, 1, 1); 592 593 static const struct snd_kcontrol_new hpo_r_mute_control = 594 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5651_HP_VOL, 595 RT5651_R_MUTE_SFT, 1, 1); 596 597 /* Stereo ADC source */ 598 static const char * const rt5651_stereo1_adc1_src[] = {"DD MIX", "ADC"}; 599 600 static SOC_ENUM_SINGLE_DECL( 601 rt5651_stereo1_adc1_enum, RT5651_STO1_ADC_MIXER, 602 RT5651_STO1_ADC_1_SRC_SFT, rt5651_stereo1_adc1_src); 603 604 static const struct snd_kcontrol_new rt5651_sto1_adc_l1_mux = 605 SOC_DAPM_ENUM("Stereo1 ADC L1 source", rt5651_stereo1_adc1_enum); 606 607 static const struct snd_kcontrol_new rt5651_sto1_adc_r1_mux = 608 SOC_DAPM_ENUM("Stereo1 ADC R1 source", rt5651_stereo1_adc1_enum); 609 610 static const char * const rt5651_stereo1_adc2_src[] = {"DMIC", "DD MIX"}; 611 612 static SOC_ENUM_SINGLE_DECL( 613 rt5651_stereo1_adc2_enum, RT5651_STO1_ADC_MIXER, 614 RT5651_STO1_ADC_2_SRC_SFT, rt5651_stereo1_adc2_src); 615 616 static const struct snd_kcontrol_new rt5651_sto1_adc_l2_mux = 617 SOC_DAPM_ENUM("Stereo1 ADC L2 source", rt5651_stereo1_adc2_enum); 618 619 static const struct snd_kcontrol_new rt5651_sto1_adc_r2_mux = 620 SOC_DAPM_ENUM("Stereo1 ADC R2 source", rt5651_stereo1_adc2_enum); 621 622 /* Mono ADC source */ 623 static const char * const rt5651_sto2_adc_l1_src[] = {"DD MIXL", "ADCL"}; 624 625 static SOC_ENUM_SINGLE_DECL( 626 rt5651_sto2_adc_l1_enum, RT5651_STO1_ADC_MIXER, 627 RT5651_STO2_ADC_L1_SRC_SFT, rt5651_sto2_adc_l1_src); 628 629 static const struct snd_kcontrol_new rt5651_sto2_adc_l1_mux = 630 SOC_DAPM_ENUM("Stereo2 ADC1 left source", rt5651_sto2_adc_l1_enum); 631 632 static const char * const rt5651_sto2_adc_l2_src[] = {"DMIC L", "DD MIXL"}; 633 634 static SOC_ENUM_SINGLE_DECL( 635 rt5651_sto2_adc_l2_enum, RT5651_STO1_ADC_MIXER, 636 RT5651_STO2_ADC_L2_SRC_SFT, rt5651_sto2_adc_l2_src); 637 638 static const struct snd_kcontrol_new rt5651_sto2_adc_l2_mux = 639 SOC_DAPM_ENUM("Stereo2 ADC2 left source", rt5651_sto2_adc_l2_enum); 640 641 static const char * const rt5651_sto2_adc_r1_src[] = {"DD MIXR", "ADCR"}; 642 643 static SOC_ENUM_SINGLE_DECL( 644 rt5651_sto2_adc_r1_enum, RT5651_STO1_ADC_MIXER, 645 RT5651_STO2_ADC_R1_SRC_SFT, rt5651_sto2_adc_r1_src); 646 647 static const struct snd_kcontrol_new rt5651_sto2_adc_r1_mux = 648 SOC_DAPM_ENUM("Stereo2 ADC1 right source", rt5651_sto2_adc_r1_enum); 649 650 static const char * const rt5651_sto2_adc_r2_src[] = {"DMIC R", "DD MIXR"}; 651 652 static SOC_ENUM_SINGLE_DECL( 653 rt5651_sto2_adc_r2_enum, RT5651_STO1_ADC_MIXER, 654 RT5651_STO2_ADC_R2_SRC_SFT, rt5651_sto2_adc_r2_src); 655 656 static const struct snd_kcontrol_new rt5651_sto2_adc_r2_mux = 657 SOC_DAPM_ENUM("Stereo2 ADC2 right source", rt5651_sto2_adc_r2_enum); 658 659 /* DAC2 channel source */ 660 661 static const char * const rt5651_dac_src[] = {"IF1", "IF2"}; 662 663 static SOC_ENUM_SINGLE_DECL(rt5651_dac_l2_enum, RT5651_DAC2_CTRL, 664 RT5651_SEL_DAC_L2_SFT, rt5651_dac_src); 665 666 static const struct snd_kcontrol_new rt5651_dac_l2_mux = 667 SOC_DAPM_ENUM("DAC2 left channel source", rt5651_dac_l2_enum); 668 669 static SOC_ENUM_SINGLE_DECL( 670 rt5651_dac_r2_enum, RT5651_DAC2_CTRL, 671 RT5651_SEL_DAC_R2_SFT, rt5651_dac_src); 672 673 static const struct snd_kcontrol_new rt5651_dac_r2_mux = 674 SOC_DAPM_ENUM("DAC2 right channel source", rt5651_dac_r2_enum); 675 676 /* IF2_ADC channel source */ 677 678 static const char * const rt5651_adc_src[] = {"IF1 ADC1", "IF1 ADC2"}; 679 680 static SOC_ENUM_SINGLE_DECL(rt5651_if2_adc_src_enum, RT5651_DIG_INF_DATA, 681 RT5651_IF2_ADC_SRC_SFT, rt5651_adc_src); 682 683 static const struct snd_kcontrol_new rt5651_if2_adc_src_mux = 684 SOC_DAPM_ENUM("IF2 ADC channel source", rt5651_if2_adc_src_enum); 685 686 /* PDM select */ 687 static const char * const rt5651_pdm_sel[] = {"DD MIX", "Stereo DAC MIX"}; 688 689 static SOC_ENUM_SINGLE_DECL( 690 rt5651_pdm_l_sel_enum, RT5651_PDM_CTL, 691 RT5651_PDM_L_SEL_SFT, rt5651_pdm_sel); 692 693 static SOC_ENUM_SINGLE_DECL( 694 rt5651_pdm_r_sel_enum, RT5651_PDM_CTL, 695 RT5651_PDM_R_SEL_SFT, rt5651_pdm_sel); 696 697 static const struct snd_kcontrol_new rt5651_pdm_l_mux = 698 SOC_DAPM_ENUM("PDM L select", rt5651_pdm_l_sel_enum); 699 700 static const struct snd_kcontrol_new rt5651_pdm_r_mux = 701 SOC_DAPM_ENUM("PDM R select", rt5651_pdm_r_sel_enum); 702 703 static int rt5651_amp_power_event(struct snd_soc_dapm_widget *w, 704 struct snd_kcontrol *kcontrol, int event) 705 { 706 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); 707 struct rt5651_priv *rt5651 = snd_soc_codec_get_drvdata(codec); 708 709 switch (event) { 710 case SND_SOC_DAPM_POST_PMU: 711 /* depop parameters */ 712 regmap_update_bits(rt5651->regmap, RT5651_PR_BASE + 713 RT5651_CHPUMP_INT_REG1, 0x0700, 0x0200); 714 regmap_update_bits(rt5651->regmap, RT5651_DEPOP_M2, 715 RT5651_DEPOP_MASK, RT5651_DEPOP_MAN); 716 regmap_update_bits(rt5651->regmap, RT5651_DEPOP_M1, 717 RT5651_HP_CP_MASK | RT5651_HP_SG_MASK | 718 RT5651_HP_CB_MASK, RT5651_HP_CP_PU | 719 RT5651_HP_SG_DIS | RT5651_HP_CB_PU); 720 regmap_write(rt5651->regmap, RT5651_PR_BASE + 721 RT5651_HP_DCC_INT1, 0x9f00); 722 /* headphone amp power on */ 723 regmap_update_bits(rt5651->regmap, RT5651_PWR_ANLG1, 724 RT5651_PWR_FV1 | RT5651_PWR_FV2, 0); 725 regmap_update_bits(rt5651->regmap, RT5651_PWR_ANLG1, 726 RT5651_PWR_HA, 727 RT5651_PWR_HA); 728 usleep_range(10000, 15000); 729 regmap_update_bits(rt5651->regmap, RT5651_PWR_ANLG1, 730 RT5651_PWR_FV1 | RT5651_PWR_FV2 , 731 RT5651_PWR_FV1 | RT5651_PWR_FV2); 732 break; 733 734 default: 735 return 0; 736 } 737 738 return 0; 739 } 740 741 static int rt5651_hp_event(struct snd_soc_dapm_widget *w, 742 struct snd_kcontrol *kcontrol, int event) 743 { 744 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); 745 struct rt5651_priv *rt5651 = snd_soc_codec_get_drvdata(codec); 746 747 switch (event) { 748 case SND_SOC_DAPM_POST_PMU: 749 /* headphone unmute sequence */ 750 regmap_update_bits(rt5651->regmap, RT5651_DEPOP_M2, 751 RT5651_DEPOP_MASK | RT5651_DIG_DP_MASK, 752 RT5651_DEPOP_AUTO | RT5651_DIG_DP_EN); 753 regmap_update_bits(rt5651->regmap, RT5651_CHARGE_PUMP, 754 RT5651_PM_HP_MASK, RT5651_PM_HP_HV); 755 756 regmap_update_bits(rt5651->regmap, RT5651_DEPOP_M3, 757 RT5651_CP_FQ1_MASK | RT5651_CP_FQ2_MASK | 758 RT5651_CP_FQ3_MASK, 759 (RT5651_CP_FQ_192_KHZ << RT5651_CP_FQ1_SFT) | 760 (RT5651_CP_FQ_12_KHZ << RT5651_CP_FQ2_SFT) | 761 (RT5651_CP_FQ_192_KHZ << RT5651_CP_FQ3_SFT)); 762 763 regmap_write(rt5651->regmap, RT5651_PR_BASE + 764 RT5651_MAMP_INT_REG2, 0x1c00); 765 regmap_update_bits(rt5651->regmap, RT5651_DEPOP_M1, 766 RT5651_HP_CP_MASK | RT5651_HP_SG_MASK, 767 RT5651_HP_CP_PD | RT5651_HP_SG_EN); 768 regmap_update_bits(rt5651->regmap, RT5651_PR_BASE + 769 RT5651_CHPUMP_INT_REG1, 0x0700, 0x0400); 770 rt5651->hp_mute = 0; 771 break; 772 773 case SND_SOC_DAPM_PRE_PMD: 774 rt5651->hp_mute = 1; 775 usleep_range(70000, 75000); 776 break; 777 778 default: 779 return 0; 780 } 781 782 return 0; 783 } 784 785 static int rt5651_hp_post_event(struct snd_soc_dapm_widget *w, 786 struct snd_kcontrol *kcontrol, int event) 787 { 788 789 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); 790 struct rt5651_priv *rt5651 = snd_soc_codec_get_drvdata(codec); 791 792 switch (event) { 793 case SND_SOC_DAPM_POST_PMU: 794 if (!rt5651->hp_mute) 795 usleep_range(80000, 85000); 796 797 break; 798 799 default: 800 return 0; 801 } 802 803 return 0; 804 } 805 806 static int rt5651_bst1_event(struct snd_soc_dapm_widget *w, 807 struct snd_kcontrol *kcontrol, int event) 808 { 809 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); 810 811 switch (event) { 812 case SND_SOC_DAPM_POST_PMU: 813 snd_soc_update_bits(codec, RT5651_PWR_ANLG2, 814 RT5651_PWR_BST1_OP2, RT5651_PWR_BST1_OP2); 815 break; 816 817 case SND_SOC_DAPM_PRE_PMD: 818 snd_soc_update_bits(codec, RT5651_PWR_ANLG2, 819 RT5651_PWR_BST1_OP2, 0); 820 break; 821 822 default: 823 return 0; 824 } 825 826 return 0; 827 } 828 829 static int rt5651_bst2_event(struct snd_soc_dapm_widget *w, 830 struct snd_kcontrol *kcontrol, int event) 831 { 832 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); 833 834 switch (event) { 835 case SND_SOC_DAPM_POST_PMU: 836 snd_soc_update_bits(codec, RT5651_PWR_ANLG2, 837 RT5651_PWR_BST2_OP2, RT5651_PWR_BST2_OP2); 838 break; 839 840 case SND_SOC_DAPM_PRE_PMD: 841 snd_soc_update_bits(codec, RT5651_PWR_ANLG2, 842 RT5651_PWR_BST2_OP2, 0); 843 break; 844 845 default: 846 return 0; 847 } 848 849 return 0; 850 } 851 852 static int rt5651_bst3_event(struct snd_soc_dapm_widget *w, 853 struct snd_kcontrol *kcontrol, int event) 854 { 855 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); 856 857 switch (event) { 858 case SND_SOC_DAPM_POST_PMU: 859 snd_soc_update_bits(codec, RT5651_PWR_ANLG2, 860 RT5651_PWR_BST3_OP2, RT5651_PWR_BST3_OP2); 861 break; 862 863 case SND_SOC_DAPM_PRE_PMD: 864 snd_soc_update_bits(codec, RT5651_PWR_ANLG2, 865 RT5651_PWR_BST3_OP2, 0); 866 break; 867 868 default: 869 return 0; 870 } 871 872 return 0; 873 } 874 875 static const struct snd_soc_dapm_widget rt5651_dapm_widgets[] = { 876 /* ASRC */ 877 SND_SOC_DAPM_SUPPLY_S("I2S1 ASRC", 1, RT5651_PLL_MODE_2, 878 15, 0, NULL, 0), 879 SND_SOC_DAPM_SUPPLY_S("I2S2 ASRC", 1, RT5651_PLL_MODE_2, 880 14, 0, NULL, 0), 881 SND_SOC_DAPM_SUPPLY_S("STO1 DAC ASRC", 1, RT5651_PLL_MODE_2, 882 13, 0, NULL, 0), 883 SND_SOC_DAPM_SUPPLY_S("STO2 DAC ASRC", 1, RT5651_PLL_MODE_2, 884 12, 0, NULL, 0), 885 SND_SOC_DAPM_SUPPLY_S("ADC ASRC", 1, RT5651_PLL_MODE_2, 886 11, 0, NULL, 0), 887 888 SND_SOC_DAPM_SUPPLY("PLL1", RT5651_PWR_ANLG2, 889 RT5651_PWR_PLL_BIT, 0, NULL, 0), 890 /* Input Side */ 891 SND_SOC_DAPM_SUPPLY("JD Power", RT5651_PWR_ANLG2, 892 RT5651_PWM_JD_M_BIT, 0, NULL, 0), 893 894 /* micbias */ 895 SND_SOC_DAPM_SUPPLY("LDO", RT5651_PWR_ANLG1, 896 RT5651_PWR_LDO_BIT, 0, NULL, 0), 897 SND_SOC_DAPM_SUPPLY("micbias1", RT5651_PWR_ANLG2, 898 RT5651_PWR_MB1_BIT, 0, NULL, 0), 899 /* Input Lines */ 900 SND_SOC_DAPM_INPUT("MIC1"), 901 SND_SOC_DAPM_INPUT("MIC2"), 902 SND_SOC_DAPM_INPUT("MIC3"), 903 904 SND_SOC_DAPM_INPUT("IN1P"), 905 SND_SOC_DAPM_INPUT("IN2P"), 906 SND_SOC_DAPM_INPUT("IN2N"), 907 SND_SOC_DAPM_INPUT("IN3P"), 908 SND_SOC_DAPM_INPUT("DMIC L1"), 909 SND_SOC_DAPM_INPUT("DMIC R1"), 910 SND_SOC_DAPM_SUPPLY("DMIC CLK", RT5651_DMIC, RT5651_DMIC_1_EN_SFT, 911 0, set_dmic_clk, SND_SOC_DAPM_PRE_PMU), 912 /* Boost */ 913 SND_SOC_DAPM_PGA_E("BST1", RT5651_PWR_ANLG2, 914 RT5651_PWR_BST1_BIT, 0, NULL, 0, rt5651_bst1_event, 915 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU), 916 SND_SOC_DAPM_PGA_E("BST2", RT5651_PWR_ANLG2, 917 RT5651_PWR_BST2_BIT, 0, NULL, 0, rt5651_bst2_event, 918 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU), 919 SND_SOC_DAPM_PGA_E("BST3", RT5651_PWR_ANLG2, 920 RT5651_PWR_BST3_BIT, 0, NULL, 0, rt5651_bst3_event, 921 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU), 922 /* Input Volume */ 923 SND_SOC_DAPM_PGA("INL1 VOL", RT5651_PWR_VOL, 924 RT5651_PWR_IN1_L_BIT, 0, NULL, 0), 925 SND_SOC_DAPM_PGA("INR1 VOL", RT5651_PWR_VOL, 926 RT5651_PWR_IN1_R_BIT, 0, NULL, 0), 927 SND_SOC_DAPM_PGA("INL2 VOL", RT5651_PWR_VOL, 928 RT5651_PWR_IN2_L_BIT, 0, NULL, 0), 929 SND_SOC_DAPM_PGA("INR2 VOL", RT5651_PWR_VOL, 930 RT5651_PWR_IN2_R_BIT, 0, NULL, 0), 931 932 /* REC Mixer */ 933 SND_SOC_DAPM_MIXER("RECMIXL", RT5651_PWR_MIXER, RT5651_PWR_RM_L_BIT, 0, 934 rt5651_rec_l_mix, ARRAY_SIZE(rt5651_rec_l_mix)), 935 SND_SOC_DAPM_MIXER("RECMIXR", RT5651_PWR_MIXER, RT5651_PWR_RM_R_BIT, 0, 936 rt5651_rec_r_mix, ARRAY_SIZE(rt5651_rec_r_mix)), 937 /* ADCs */ 938 SND_SOC_DAPM_ADC("ADC L", NULL, SND_SOC_NOPM, 0, 0), 939 SND_SOC_DAPM_ADC("ADC R", NULL, SND_SOC_NOPM, 0, 0), 940 SND_SOC_DAPM_SUPPLY("ADC L Power", RT5651_PWR_DIG1, 941 RT5651_PWR_ADC_L_BIT, 0, NULL, 0), 942 SND_SOC_DAPM_SUPPLY("ADC R Power", RT5651_PWR_DIG1, 943 RT5651_PWR_ADC_R_BIT, 0, NULL, 0), 944 /* ADC Mux */ 945 SND_SOC_DAPM_MUX("Stereo1 ADC L2 Mux", SND_SOC_NOPM, 0, 0, 946 &rt5651_sto1_adc_l2_mux), 947 SND_SOC_DAPM_MUX("Stereo1 ADC R2 Mux", SND_SOC_NOPM, 0, 0, 948 &rt5651_sto1_adc_r2_mux), 949 SND_SOC_DAPM_MUX("Stereo1 ADC L1 Mux", SND_SOC_NOPM, 0, 0, 950 &rt5651_sto1_adc_l1_mux), 951 SND_SOC_DAPM_MUX("Stereo1 ADC R1 Mux", SND_SOC_NOPM, 0, 0, 952 &rt5651_sto1_adc_r1_mux), 953 SND_SOC_DAPM_MUX("Stereo2 ADC L2 Mux", SND_SOC_NOPM, 0, 0, 954 &rt5651_sto2_adc_l2_mux), 955 SND_SOC_DAPM_MUX("Stereo2 ADC L1 Mux", SND_SOC_NOPM, 0, 0, 956 &rt5651_sto2_adc_l1_mux), 957 SND_SOC_DAPM_MUX("Stereo2 ADC R1 Mux", SND_SOC_NOPM, 0, 0, 958 &rt5651_sto2_adc_r1_mux), 959 SND_SOC_DAPM_MUX("Stereo2 ADC R2 Mux", SND_SOC_NOPM, 0, 0, 960 &rt5651_sto2_adc_r2_mux), 961 /* ADC Mixer */ 962 SND_SOC_DAPM_SUPPLY("Stereo1 Filter", RT5651_PWR_DIG2, 963 RT5651_PWR_ADC_STO1_F_BIT, 0, NULL, 0), 964 SND_SOC_DAPM_SUPPLY("Stereo2 Filter", RT5651_PWR_DIG2, 965 RT5651_PWR_ADC_STO2_F_BIT, 0, NULL, 0), 966 SND_SOC_DAPM_MIXER("Stereo1 ADC MIXL", SND_SOC_NOPM, 0, 0, 967 rt5651_sto1_adc_l_mix, 968 ARRAY_SIZE(rt5651_sto1_adc_l_mix)), 969 SND_SOC_DAPM_MIXER("Stereo1 ADC MIXR", SND_SOC_NOPM, 0, 0, 970 rt5651_sto1_adc_r_mix, 971 ARRAY_SIZE(rt5651_sto1_adc_r_mix)), 972 SND_SOC_DAPM_MIXER("Stereo2 ADC MIXL", SND_SOC_NOPM, 0, 0, 973 rt5651_sto2_adc_l_mix, 974 ARRAY_SIZE(rt5651_sto2_adc_l_mix)), 975 SND_SOC_DAPM_MIXER("Stereo2 ADC MIXR", SND_SOC_NOPM, 0, 0, 976 rt5651_sto2_adc_r_mix, 977 ARRAY_SIZE(rt5651_sto2_adc_r_mix)), 978 979 /* Digital Interface */ 980 SND_SOC_DAPM_SUPPLY("I2S1", RT5651_PWR_DIG1, 981 RT5651_PWR_I2S1_BIT, 0, NULL, 0), 982 SND_SOC_DAPM_PGA("IF1 DAC", SND_SOC_NOPM, 0, 0, NULL, 0), 983 SND_SOC_DAPM_PGA("IF1 DAC1 L", SND_SOC_NOPM, 0, 0, NULL, 0), 984 SND_SOC_DAPM_PGA("IF1 DAC1 R", SND_SOC_NOPM, 0, 0, NULL, 0), 985 SND_SOC_DAPM_PGA("IF1 ADC1", SND_SOC_NOPM, 0, 0, NULL, 0), 986 SND_SOC_DAPM_PGA("IF1 DAC2 L", SND_SOC_NOPM, 0, 0, NULL, 0), 987 SND_SOC_DAPM_PGA("IF1 DAC2 R", SND_SOC_NOPM, 0, 0, NULL, 0), 988 SND_SOC_DAPM_PGA("IF1 ADC2", SND_SOC_NOPM, 0, 0, NULL, 0), 989 SND_SOC_DAPM_SUPPLY("I2S2", RT5651_PWR_DIG1, 990 RT5651_PWR_I2S2_BIT, 0, NULL, 0), 991 SND_SOC_DAPM_PGA("IF2 DAC", SND_SOC_NOPM, 0, 0, NULL, 0), 992 SND_SOC_DAPM_PGA("IF2 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0), 993 SND_SOC_DAPM_PGA("IF2 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0), 994 SND_SOC_DAPM_MUX("IF2 ADC", SND_SOC_NOPM, 0, 0, 995 &rt5651_if2_adc_src_mux), 996 997 /* Digital Interface Select */ 998 999 SND_SOC_DAPM_MUX("PDM L Mux", RT5651_PDM_CTL, 1000 RT5651_M_PDM_L_SFT, 1, &rt5651_pdm_l_mux), 1001 SND_SOC_DAPM_MUX("PDM R Mux", RT5651_PDM_CTL, 1002 RT5651_M_PDM_R_SFT, 1, &rt5651_pdm_r_mux), 1003 /* Audio Interface */ 1004 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0), 1005 SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0), 1006 SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0), 1007 SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0), 1008 1009 /* Audio DSP */ 1010 SND_SOC_DAPM_PGA("Audio DSP", SND_SOC_NOPM, 0, 0, NULL, 0), 1011 1012 /* Output Side */ 1013 /* DAC mixer before sound effect */ 1014 SND_SOC_DAPM_MIXER("DAC MIXL", SND_SOC_NOPM, 0, 0, 1015 rt5651_dac_l_mix, ARRAY_SIZE(rt5651_dac_l_mix)), 1016 SND_SOC_DAPM_MIXER("DAC MIXR", SND_SOC_NOPM, 0, 0, 1017 rt5651_dac_r_mix, ARRAY_SIZE(rt5651_dac_r_mix)), 1018 1019 /* DAC2 channel Mux */ 1020 SND_SOC_DAPM_MUX("DAC L2 Mux", SND_SOC_NOPM, 0, 0, &rt5651_dac_l2_mux), 1021 SND_SOC_DAPM_MUX("DAC R2 Mux", SND_SOC_NOPM, 0, 0, &rt5651_dac_r2_mux), 1022 SND_SOC_DAPM_PGA("DAC L2 Volume", SND_SOC_NOPM, 0, 0, NULL, 0), 1023 SND_SOC_DAPM_PGA("DAC R2 Volume", SND_SOC_NOPM, 0, 0, NULL, 0), 1024 1025 SND_SOC_DAPM_SUPPLY("Stero1 DAC Power", RT5651_PWR_DIG2, 1026 RT5651_PWR_DAC_STO1_F_BIT, 0, NULL, 0), 1027 SND_SOC_DAPM_SUPPLY("Stero2 DAC Power", RT5651_PWR_DIG2, 1028 RT5651_PWR_DAC_STO2_F_BIT, 0, NULL, 0), 1029 /* DAC Mixer */ 1030 SND_SOC_DAPM_MIXER("Stereo DAC MIXL", SND_SOC_NOPM, 0, 0, 1031 rt5651_sto_dac_l_mix, 1032 ARRAY_SIZE(rt5651_sto_dac_l_mix)), 1033 SND_SOC_DAPM_MIXER("Stereo DAC MIXR", SND_SOC_NOPM, 0, 0, 1034 rt5651_sto_dac_r_mix, 1035 ARRAY_SIZE(rt5651_sto_dac_r_mix)), 1036 SND_SOC_DAPM_MIXER("DD MIXL", SND_SOC_NOPM, 0, 0, 1037 rt5651_dd_dac_l_mix, 1038 ARRAY_SIZE(rt5651_dd_dac_l_mix)), 1039 SND_SOC_DAPM_MIXER("DD MIXR", SND_SOC_NOPM, 0, 0, 1040 rt5651_dd_dac_r_mix, 1041 ARRAY_SIZE(rt5651_dd_dac_r_mix)), 1042 1043 /* DACs */ 1044 SND_SOC_DAPM_DAC("DAC L1", NULL, SND_SOC_NOPM, 0, 0), 1045 SND_SOC_DAPM_DAC("DAC R1", NULL, SND_SOC_NOPM, 0, 0), 1046 SND_SOC_DAPM_SUPPLY("DAC L1 Power", RT5651_PWR_DIG1, 1047 RT5651_PWR_DAC_L1_BIT, 0, NULL, 0), 1048 SND_SOC_DAPM_SUPPLY("DAC R1 Power", RT5651_PWR_DIG1, 1049 RT5651_PWR_DAC_R1_BIT, 0, NULL, 0), 1050 /* OUT Mixer */ 1051 SND_SOC_DAPM_MIXER("OUT MIXL", RT5651_PWR_MIXER, RT5651_PWR_OM_L_BIT, 1052 0, rt5651_out_l_mix, ARRAY_SIZE(rt5651_out_l_mix)), 1053 SND_SOC_DAPM_MIXER("OUT MIXR", RT5651_PWR_MIXER, RT5651_PWR_OM_R_BIT, 1054 0, rt5651_out_r_mix, ARRAY_SIZE(rt5651_out_r_mix)), 1055 /* Ouput Volume */ 1056 SND_SOC_DAPM_SWITCH("OUTVOL L", RT5651_PWR_VOL, 1057 RT5651_PWR_OV_L_BIT, 0, &outvol_l_control), 1058 SND_SOC_DAPM_SWITCH("OUTVOL R", RT5651_PWR_VOL, 1059 RT5651_PWR_OV_R_BIT, 0, &outvol_r_control), 1060 SND_SOC_DAPM_SWITCH("HPOVOL L", RT5651_PWR_VOL, 1061 RT5651_PWR_HV_L_BIT, 0, &hpovol_l_control), 1062 SND_SOC_DAPM_SWITCH("HPOVOL R", RT5651_PWR_VOL, 1063 RT5651_PWR_HV_R_BIT, 0, &hpovol_r_control), 1064 SND_SOC_DAPM_PGA("INL1", RT5651_PWR_VOL, 1065 RT5651_PWR_IN1_L_BIT, 0, NULL, 0), 1066 SND_SOC_DAPM_PGA("INR1", RT5651_PWR_VOL, 1067 RT5651_PWR_IN1_R_BIT, 0, NULL, 0), 1068 SND_SOC_DAPM_PGA("INL2", RT5651_PWR_VOL, 1069 RT5651_PWR_IN2_L_BIT, 0, NULL, 0), 1070 SND_SOC_DAPM_PGA("INR2", RT5651_PWR_VOL, 1071 RT5651_PWR_IN2_R_BIT, 0, NULL, 0), 1072 /* HPO/LOUT/Mono Mixer */ 1073 SND_SOC_DAPM_MIXER("HPOL MIX", SND_SOC_NOPM, 0, 0, 1074 rt5651_hpo_mix, ARRAY_SIZE(rt5651_hpo_mix)), 1075 SND_SOC_DAPM_MIXER("HPOR MIX", SND_SOC_NOPM, 0, 0, 1076 rt5651_hpo_mix, ARRAY_SIZE(rt5651_hpo_mix)), 1077 SND_SOC_DAPM_SUPPLY("HP L Amp", RT5651_PWR_ANLG1, 1078 RT5651_PWR_HP_L_BIT, 0, NULL, 0), 1079 SND_SOC_DAPM_SUPPLY("HP R Amp", RT5651_PWR_ANLG1, 1080 RT5651_PWR_HP_R_BIT, 0, NULL, 0), 1081 SND_SOC_DAPM_MIXER("LOUT MIX", RT5651_PWR_ANLG1, RT5651_PWR_LM_BIT, 0, 1082 rt5651_lout_mix, ARRAY_SIZE(rt5651_lout_mix)), 1083 1084 SND_SOC_DAPM_SUPPLY("Amp Power", RT5651_PWR_ANLG1, 1085 RT5651_PWR_HA_BIT, 0, rt5651_amp_power_event, 1086 SND_SOC_DAPM_POST_PMU), 1087 SND_SOC_DAPM_PGA_S("HP Amp", 1, SND_SOC_NOPM, 0, 0, rt5651_hp_event, 1088 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU), 1089 SND_SOC_DAPM_SWITCH("HPO L Playback", SND_SOC_NOPM, 0, 0, 1090 &hpo_l_mute_control), 1091 SND_SOC_DAPM_SWITCH("HPO R Playback", SND_SOC_NOPM, 0, 0, 1092 &hpo_r_mute_control), 1093 SND_SOC_DAPM_SWITCH("LOUT L Playback", SND_SOC_NOPM, 0, 0, 1094 &lout_l_mute_control), 1095 SND_SOC_DAPM_SWITCH("LOUT R Playback", SND_SOC_NOPM, 0, 0, 1096 &lout_r_mute_control), 1097 SND_SOC_DAPM_POST("HP Post", rt5651_hp_post_event), 1098 1099 /* Output Lines */ 1100 SND_SOC_DAPM_OUTPUT("HPOL"), 1101 SND_SOC_DAPM_OUTPUT("HPOR"), 1102 SND_SOC_DAPM_OUTPUT("LOUTL"), 1103 SND_SOC_DAPM_OUTPUT("LOUTR"), 1104 SND_SOC_DAPM_OUTPUT("PDML"), 1105 SND_SOC_DAPM_OUTPUT("PDMR"), 1106 }; 1107 1108 static const struct snd_soc_dapm_route rt5651_dapm_routes[] = { 1109 {"Stero1 DAC Power", NULL, "STO1 DAC ASRC"}, 1110 {"Stero2 DAC Power", NULL, "STO2 DAC ASRC"}, 1111 {"I2S1", NULL, "I2S1 ASRC"}, 1112 {"I2S2", NULL, "I2S2 ASRC"}, 1113 1114 {"IN1P", NULL, "LDO"}, 1115 {"IN2P", NULL, "LDO"}, 1116 {"IN3P", NULL, "LDO"}, 1117 1118 {"IN1P", NULL, "MIC1"}, 1119 {"IN2P", NULL, "MIC2"}, 1120 {"IN2N", NULL, "MIC2"}, 1121 {"IN3P", NULL, "MIC3"}, 1122 1123 {"BST1", NULL, "IN1P"}, 1124 {"BST2", NULL, "IN2P"}, 1125 {"BST2", NULL, "IN2N"}, 1126 {"BST3", NULL, "IN3P"}, 1127 1128 {"INL1 VOL", NULL, "IN2P"}, 1129 {"INR1 VOL", NULL, "IN2N"}, 1130 1131 {"RECMIXL", "INL1 Switch", "INL1 VOL"}, 1132 {"RECMIXL", "BST3 Switch", "BST3"}, 1133 {"RECMIXL", "BST2 Switch", "BST2"}, 1134 {"RECMIXL", "BST1 Switch", "BST1"}, 1135 1136 {"RECMIXR", "INR1 Switch", "INR1 VOL"}, 1137 {"RECMIXR", "BST3 Switch", "BST3"}, 1138 {"RECMIXR", "BST2 Switch", "BST2"}, 1139 {"RECMIXR", "BST1 Switch", "BST1"}, 1140 1141 {"ADC L", NULL, "RECMIXL"}, 1142 {"ADC L", NULL, "ADC L Power"}, 1143 {"ADC R", NULL, "RECMIXR"}, 1144 {"ADC R", NULL, "ADC R Power"}, 1145 1146 {"DMIC L1", NULL, "DMIC CLK"}, 1147 {"DMIC R1", NULL, "DMIC CLK"}, 1148 1149 {"Stereo1 ADC L2 Mux", "DMIC", "DMIC L1"}, 1150 {"Stereo1 ADC L2 Mux", "DD MIX", "DD MIXL"}, 1151 {"Stereo1 ADC L1 Mux", "ADC", "ADC L"}, 1152 {"Stereo1 ADC L1 Mux", "DD MIX", "DD MIXL"}, 1153 1154 {"Stereo1 ADC R1 Mux", "ADC", "ADC R"}, 1155 {"Stereo1 ADC R1 Mux", "DD MIX", "DD MIXR"}, 1156 {"Stereo1 ADC R2 Mux", "DMIC", "DMIC R1"}, 1157 {"Stereo1 ADC R2 Mux", "DD MIX", "DD MIXR"}, 1158 1159 {"Stereo2 ADC L2 Mux", "DMIC L", "DMIC L1"}, 1160 {"Stereo2 ADC L2 Mux", "DD MIXL", "DD MIXL"}, 1161 {"Stereo2 ADC L1 Mux", "DD MIXL", "DD MIXL"}, 1162 {"Stereo2 ADC L1 Mux", "ADCL", "ADC L"}, 1163 1164 {"Stereo2 ADC R1 Mux", "DD MIXR", "DD MIXR"}, 1165 {"Stereo2 ADC R1 Mux", "ADCR", "ADC R"}, 1166 {"Stereo2 ADC R2 Mux", "DMIC R", "DMIC R1"}, 1167 {"Stereo2 ADC R2 Mux", "DD MIXR", "DD MIXR"}, 1168 1169 {"Stereo1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC L1 Mux"}, 1170 {"Stereo1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC L2 Mux"}, 1171 {"Stereo1 ADC MIXL", NULL, "Stereo1 Filter"}, 1172 {"Stereo1 Filter", NULL, "PLL1", is_sysclk_from_pll}, 1173 {"Stereo1 Filter", NULL, "ADC ASRC"}, 1174 1175 {"Stereo1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC R1 Mux"}, 1176 {"Stereo1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC R2 Mux"}, 1177 {"Stereo1 ADC MIXR", NULL, "Stereo1 Filter"}, 1178 1179 {"Stereo2 ADC MIXL", "ADC1 Switch", "Stereo2 ADC L1 Mux"}, 1180 {"Stereo2 ADC MIXL", "ADC2 Switch", "Stereo2 ADC L2 Mux"}, 1181 {"Stereo2 ADC MIXL", NULL, "Stereo2 Filter"}, 1182 {"Stereo2 Filter", NULL, "PLL1", is_sysclk_from_pll}, 1183 {"Stereo2 Filter", NULL, "ADC ASRC"}, 1184 1185 {"Stereo2 ADC MIXR", "ADC1 Switch", "Stereo2 ADC R1 Mux"}, 1186 {"Stereo2 ADC MIXR", "ADC2 Switch", "Stereo2 ADC R2 Mux"}, 1187 {"Stereo2 ADC MIXR", NULL, "Stereo2 Filter"}, 1188 1189 {"IF1 ADC2", NULL, "Stereo2 ADC MIXL"}, 1190 {"IF1 ADC2", NULL, "Stereo2 ADC MIXR"}, 1191 {"IF1 ADC1", NULL, "Stereo1 ADC MIXL"}, 1192 {"IF1 ADC1", NULL, "Stereo1 ADC MIXR"}, 1193 1194 {"IF1 ADC1", NULL, "I2S1"}, 1195 1196 {"IF2 ADC", "IF1 ADC1", "IF1 ADC1"}, 1197 {"IF2 ADC", "IF1 ADC2", "IF1 ADC2"}, 1198 {"IF2 ADC", NULL, "I2S2"}, 1199 1200 {"AIF1TX", NULL, "IF1 ADC1"}, 1201 {"AIF1TX", NULL, "IF1 ADC2"}, 1202 {"AIF2TX", NULL, "IF2 ADC"}, 1203 1204 {"IF1 DAC", NULL, "AIF1RX"}, 1205 {"IF1 DAC", NULL, "I2S1"}, 1206 {"IF2 DAC", NULL, "AIF2RX"}, 1207 {"IF2 DAC", NULL, "I2S2"}, 1208 1209 {"IF1 DAC1 L", NULL, "IF1 DAC"}, 1210 {"IF1 DAC1 R", NULL, "IF1 DAC"}, 1211 {"IF1 DAC2 L", NULL, "IF1 DAC"}, 1212 {"IF1 DAC2 R", NULL, "IF1 DAC"}, 1213 {"IF2 DAC L", NULL, "IF2 DAC"}, 1214 {"IF2 DAC R", NULL, "IF2 DAC"}, 1215 1216 {"DAC MIXL", "Stereo ADC Switch", "Stereo1 ADC MIXL"}, 1217 {"DAC MIXL", "INF1 Switch", "IF1 DAC1 L"}, 1218 {"DAC MIXR", "Stereo ADC Switch", "Stereo1 ADC MIXR"}, 1219 {"DAC MIXR", "INF1 Switch", "IF1 DAC1 R"}, 1220 1221 {"Audio DSP", NULL, "DAC MIXL"}, 1222 {"Audio DSP", NULL, "DAC MIXR"}, 1223 1224 {"DAC L2 Mux", "IF1", "IF1 DAC2 L"}, 1225 {"DAC L2 Mux", "IF2", "IF2 DAC L"}, 1226 {"DAC L2 Volume", NULL, "DAC L2 Mux"}, 1227 1228 {"DAC R2 Mux", "IF1", "IF1 DAC2 R"}, 1229 {"DAC R2 Mux", "IF2", "IF2 DAC R"}, 1230 {"DAC R2 Volume", NULL, "DAC R2 Mux"}, 1231 1232 {"Stereo DAC MIXL", "DAC L1 Switch", "Audio DSP"}, 1233 {"Stereo DAC MIXL", "DAC L2 Switch", "DAC L2 Volume"}, 1234 {"Stereo DAC MIXL", "DAC R1 Switch", "DAC MIXR"}, 1235 {"Stereo DAC MIXL", NULL, "Stero1 DAC Power"}, 1236 {"Stereo DAC MIXL", NULL, "Stero2 DAC Power"}, 1237 {"Stereo DAC MIXR", "DAC R1 Switch", "Audio DSP"}, 1238 {"Stereo DAC MIXR", "DAC R2 Switch", "DAC R2 Volume"}, 1239 {"Stereo DAC MIXR", "DAC L1 Switch", "DAC MIXL"}, 1240 {"Stereo DAC MIXR", NULL, "Stero1 DAC Power"}, 1241 {"Stereo DAC MIXR", NULL, "Stero2 DAC Power"}, 1242 1243 {"PDM L Mux", "Stereo DAC MIX", "Stereo DAC MIXL"}, 1244 {"PDM L Mux", "DD MIX", "DAC MIXL"}, 1245 {"PDM R Mux", "Stereo DAC MIX", "Stereo DAC MIXR"}, 1246 {"PDM R Mux", "DD MIX", "DAC MIXR"}, 1247 1248 {"DAC L1", NULL, "Stereo DAC MIXL"}, 1249 {"DAC L1", NULL, "PLL1", is_sysclk_from_pll}, 1250 {"DAC L1", NULL, "DAC L1 Power"}, 1251 {"DAC R1", NULL, "Stereo DAC MIXR"}, 1252 {"DAC R1", NULL, "PLL1", is_sysclk_from_pll}, 1253 {"DAC R1", NULL, "DAC R1 Power"}, 1254 1255 {"DD MIXL", "DAC L1 Switch", "DAC MIXL"}, 1256 {"DD MIXL", "DAC L2 Switch", "DAC L2 Volume"}, 1257 {"DD MIXL", "DAC R2 Switch", "DAC R2 Volume"}, 1258 {"DD MIXL", NULL, "Stero2 DAC Power"}, 1259 1260 {"DD MIXR", "DAC R1 Switch", "DAC MIXR"}, 1261 {"DD MIXR", "DAC R2 Switch", "DAC R2 Volume"}, 1262 {"DD MIXR", "DAC L2 Switch", "DAC L2 Volume"}, 1263 {"DD MIXR", NULL, "Stero2 DAC Power"}, 1264 1265 {"OUT MIXL", "BST1 Switch", "BST1"}, 1266 {"OUT MIXL", "BST2 Switch", "BST2"}, 1267 {"OUT MIXL", "INL1 Switch", "INL1 VOL"}, 1268 {"OUT MIXL", "REC MIXL Switch", "RECMIXL"}, 1269 {"OUT MIXL", "DAC L1 Switch", "DAC L1"}, 1270 1271 {"OUT MIXR", "BST2 Switch", "BST2"}, 1272 {"OUT MIXR", "BST1 Switch", "BST1"}, 1273 {"OUT MIXR", "INR1 Switch", "INR1 VOL"}, 1274 {"OUT MIXR", "REC MIXR Switch", "RECMIXR"}, 1275 {"OUT MIXR", "DAC R1 Switch", "DAC R1"}, 1276 1277 {"HPOVOL L", "Switch", "OUT MIXL"}, 1278 {"HPOVOL R", "Switch", "OUT MIXR"}, 1279 {"OUTVOL L", "Switch", "OUT MIXL"}, 1280 {"OUTVOL R", "Switch", "OUT MIXR"}, 1281 1282 {"HPOL MIX", "HPO MIX DAC1 Switch", "DAC L1"}, 1283 {"HPOL MIX", "HPO MIX HPVOL Switch", "HPOVOL L"}, 1284 {"HPOL MIX", NULL, "HP L Amp"}, 1285 {"HPOR MIX", "HPO MIX DAC1 Switch", "DAC R1"}, 1286 {"HPOR MIX", "HPO MIX HPVOL Switch", "HPOVOL R"}, 1287 {"HPOR MIX", NULL, "HP R Amp"}, 1288 1289 {"LOUT MIX", "DAC L1 Switch", "DAC L1"}, 1290 {"LOUT MIX", "DAC R1 Switch", "DAC R1"}, 1291 {"LOUT MIX", "OUTVOL L Switch", "OUTVOL L"}, 1292 {"LOUT MIX", "OUTVOL R Switch", "OUTVOL R"}, 1293 1294 {"HP Amp", NULL, "HPOL MIX"}, 1295 {"HP Amp", NULL, "HPOR MIX"}, 1296 {"HP Amp", NULL, "Amp Power"}, 1297 {"HPO L Playback", "Switch", "HP Amp"}, 1298 {"HPO R Playback", "Switch", "HP Amp"}, 1299 {"HPOL", NULL, "HPO L Playback"}, 1300 {"HPOR", NULL, "HPO R Playback"}, 1301 1302 {"LOUT L Playback", "Switch", "LOUT MIX"}, 1303 {"LOUT R Playback", "Switch", "LOUT MIX"}, 1304 {"LOUTL", NULL, "LOUT L Playback"}, 1305 {"LOUTL", NULL, "Amp Power"}, 1306 {"LOUTR", NULL, "LOUT R Playback"}, 1307 {"LOUTR", NULL, "Amp Power"}, 1308 1309 {"PDML", NULL, "PDM L Mux"}, 1310 {"PDMR", NULL, "PDM R Mux"}, 1311 }; 1312 1313 static int rt5651_hw_params(struct snd_pcm_substream *substream, 1314 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) 1315 { 1316 struct snd_soc_codec *codec = dai->codec; 1317 struct rt5651_priv *rt5651 = snd_soc_codec_get_drvdata(codec); 1318 unsigned int val_len = 0, val_clk, mask_clk; 1319 int pre_div, bclk_ms, frame_size; 1320 1321 rt5651->lrck[dai->id] = params_rate(params); 1322 pre_div = rl6231_get_clk_info(rt5651->sysclk, rt5651->lrck[dai->id]); 1323 1324 if (pre_div < 0) { 1325 dev_err(codec->dev, "Unsupported clock setting\n"); 1326 return -EINVAL; 1327 } 1328 frame_size = snd_soc_params_to_frame_size(params); 1329 if (frame_size < 0) { 1330 dev_err(codec->dev, "Unsupported frame size: %d\n", frame_size); 1331 return -EINVAL; 1332 } 1333 bclk_ms = frame_size > 32 ? 1 : 0; 1334 rt5651->bclk[dai->id] = rt5651->lrck[dai->id] * (32 << bclk_ms); 1335 1336 dev_dbg(dai->dev, "bclk is %dHz and lrck is %dHz\n", 1337 rt5651->bclk[dai->id], rt5651->lrck[dai->id]); 1338 dev_dbg(dai->dev, "bclk_ms is %d and pre_div is %d for iis %d\n", 1339 bclk_ms, pre_div, dai->id); 1340 1341 switch (params_width(params)) { 1342 case 16: 1343 break; 1344 case 20: 1345 val_len |= RT5651_I2S_DL_20; 1346 break; 1347 case 24: 1348 val_len |= RT5651_I2S_DL_24; 1349 break; 1350 case 8: 1351 val_len |= RT5651_I2S_DL_8; 1352 break; 1353 default: 1354 return -EINVAL; 1355 } 1356 1357 switch (dai->id) { 1358 case RT5651_AIF1: 1359 mask_clk = RT5651_I2S_PD1_MASK; 1360 val_clk = pre_div << RT5651_I2S_PD1_SFT; 1361 snd_soc_update_bits(codec, RT5651_I2S1_SDP, 1362 RT5651_I2S_DL_MASK, val_len); 1363 snd_soc_update_bits(codec, RT5651_ADDA_CLK1, mask_clk, val_clk); 1364 break; 1365 case RT5651_AIF2: 1366 mask_clk = RT5651_I2S_BCLK_MS2_MASK | RT5651_I2S_PD2_MASK; 1367 val_clk = pre_div << RT5651_I2S_PD2_SFT; 1368 snd_soc_update_bits(codec, RT5651_I2S2_SDP, 1369 RT5651_I2S_DL_MASK, val_len); 1370 snd_soc_update_bits(codec, RT5651_ADDA_CLK1, mask_clk, val_clk); 1371 break; 1372 default: 1373 dev_err(codec->dev, "Wrong dai->id: %d\n", dai->id); 1374 return -EINVAL; 1375 } 1376 1377 return 0; 1378 } 1379 1380 static int rt5651_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) 1381 { 1382 struct snd_soc_codec *codec = dai->codec; 1383 struct rt5651_priv *rt5651 = snd_soc_codec_get_drvdata(codec); 1384 unsigned int reg_val = 0; 1385 1386 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 1387 case SND_SOC_DAIFMT_CBM_CFM: 1388 rt5651->master[dai->id] = 1; 1389 break; 1390 case SND_SOC_DAIFMT_CBS_CFS: 1391 reg_val |= RT5651_I2S_MS_S; 1392 rt5651->master[dai->id] = 0; 1393 break; 1394 default: 1395 return -EINVAL; 1396 } 1397 1398 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 1399 case SND_SOC_DAIFMT_NB_NF: 1400 break; 1401 case SND_SOC_DAIFMT_IB_NF: 1402 reg_val |= RT5651_I2S_BP_INV; 1403 break; 1404 default: 1405 return -EINVAL; 1406 } 1407 1408 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1409 case SND_SOC_DAIFMT_I2S: 1410 break; 1411 case SND_SOC_DAIFMT_LEFT_J: 1412 reg_val |= RT5651_I2S_DF_LEFT; 1413 break; 1414 case SND_SOC_DAIFMT_DSP_A: 1415 reg_val |= RT5651_I2S_DF_PCM_A; 1416 break; 1417 case SND_SOC_DAIFMT_DSP_B: 1418 reg_val |= RT5651_I2S_DF_PCM_B; 1419 break; 1420 default: 1421 return -EINVAL; 1422 } 1423 1424 switch (dai->id) { 1425 case RT5651_AIF1: 1426 snd_soc_update_bits(codec, RT5651_I2S1_SDP, 1427 RT5651_I2S_MS_MASK | RT5651_I2S_BP_MASK | 1428 RT5651_I2S_DF_MASK, reg_val); 1429 break; 1430 case RT5651_AIF2: 1431 snd_soc_update_bits(codec, RT5651_I2S2_SDP, 1432 RT5651_I2S_MS_MASK | RT5651_I2S_BP_MASK | 1433 RT5651_I2S_DF_MASK, reg_val); 1434 break; 1435 default: 1436 dev_err(codec->dev, "Wrong dai->id: %d\n", dai->id); 1437 return -EINVAL; 1438 } 1439 return 0; 1440 } 1441 1442 static int rt5651_set_dai_sysclk(struct snd_soc_dai *dai, 1443 int clk_id, unsigned int freq, int dir) 1444 { 1445 struct snd_soc_codec *codec = dai->codec; 1446 struct rt5651_priv *rt5651 = snd_soc_codec_get_drvdata(codec); 1447 unsigned int reg_val = 0; 1448 1449 if (freq == rt5651->sysclk && clk_id == rt5651->sysclk_src) 1450 return 0; 1451 1452 switch (clk_id) { 1453 case RT5651_SCLK_S_MCLK: 1454 reg_val |= RT5651_SCLK_SRC_MCLK; 1455 break; 1456 case RT5651_SCLK_S_PLL1: 1457 reg_val |= RT5651_SCLK_SRC_PLL1; 1458 break; 1459 case RT5651_SCLK_S_RCCLK: 1460 reg_val |= RT5651_SCLK_SRC_RCCLK; 1461 break; 1462 default: 1463 dev_err(codec->dev, "Invalid clock id (%d)\n", clk_id); 1464 return -EINVAL; 1465 } 1466 snd_soc_update_bits(codec, RT5651_GLB_CLK, 1467 RT5651_SCLK_SRC_MASK, reg_val); 1468 rt5651->sysclk = freq; 1469 rt5651->sysclk_src = clk_id; 1470 1471 dev_dbg(dai->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id); 1472 1473 return 0; 1474 } 1475 1476 static int rt5651_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source, 1477 unsigned int freq_in, unsigned int freq_out) 1478 { 1479 struct snd_soc_codec *codec = dai->codec; 1480 struct rt5651_priv *rt5651 = snd_soc_codec_get_drvdata(codec); 1481 struct rl6231_pll_code pll_code; 1482 int ret; 1483 1484 if (source == rt5651->pll_src && freq_in == rt5651->pll_in && 1485 freq_out == rt5651->pll_out) 1486 return 0; 1487 1488 if (!freq_in || !freq_out) { 1489 dev_dbg(codec->dev, "PLL disabled\n"); 1490 1491 rt5651->pll_in = 0; 1492 rt5651->pll_out = 0; 1493 snd_soc_update_bits(codec, RT5651_GLB_CLK, 1494 RT5651_SCLK_SRC_MASK, RT5651_SCLK_SRC_MCLK); 1495 return 0; 1496 } 1497 1498 switch (source) { 1499 case RT5651_PLL1_S_MCLK: 1500 snd_soc_update_bits(codec, RT5651_GLB_CLK, 1501 RT5651_PLL1_SRC_MASK, RT5651_PLL1_SRC_MCLK); 1502 break; 1503 case RT5651_PLL1_S_BCLK1: 1504 snd_soc_update_bits(codec, RT5651_GLB_CLK, 1505 RT5651_PLL1_SRC_MASK, RT5651_PLL1_SRC_BCLK1); 1506 break; 1507 case RT5651_PLL1_S_BCLK2: 1508 snd_soc_update_bits(codec, RT5651_GLB_CLK, 1509 RT5651_PLL1_SRC_MASK, RT5651_PLL1_SRC_BCLK2); 1510 break; 1511 default: 1512 dev_err(codec->dev, "Unknown PLL source %d\n", source); 1513 return -EINVAL; 1514 } 1515 1516 ret = rl6231_pll_calc(freq_in, freq_out, &pll_code); 1517 if (ret < 0) { 1518 dev_err(codec->dev, "Unsupport input clock %d\n", freq_in); 1519 return ret; 1520 } 1521 1522 dev_dbg(codec->dev, "bypass=%d m=%d n=%d k=%d\n", 1523 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code), 1524 pll_code.n_code, pll_code.k_code); 1525 1526 snd_soc_write(codec, RT5651_PLL_CTRL1, 1527 pll_code.n_code << RT5651_PLL_N_SFT | pll_code.k_code); 1528 snd_soc_write(codec, RT5651_PLL_CTRL2, 1529 (pll_code.m_bp ? 0 : pll_code.m_code) << RT5651_PLL_M_SFT | 1530 pll_code.m_bp << RT5651_PLL_M_BP_SFT); 1531 1532 rt5651->pll_in = freq_in; 1533 rt5651->pll_out = freq_out; 1534 rt5651->pll_src = source; 1535 1536 return 0; 1537 } 1538 1539 static int rt5651_set_bias_level(struct snd_soc_codec *codec, 1540 enum snd_soc_bias_level level) 1541 { 1542 struct rt5651_priv *rt5651 = snd_soc_codec_get_drvdata(codec); 1543 1544 switch (level) { 1545 case SND_SOC_BIAS_PREPARE: 1546 if (SND_SOC_BIAS_STANDBY == snd_soc_codec_get_bias_level(codec)) { 1547 snd_soc_update_bits(codec, RT5651_PWR_ANLG1, 1548 RT5651_PWR_VREF1 | RT5651_PWR_MB | 1549 RT5651_PWR_BG | RT5651_PWR_VREF2, 1550 RT5651_PWR_VREF1 | RT5651_PWR_MB | 1551 RT5651_PWR_BG | RT5651_PWR_VREF2); 1552 usleep_range(10000, 15000); 1553 snd_soc_update_bits(codec, RT5651_PWR_ANLG1, 1554 RT5651_PWR_FV1 | RT5651_PWR_FV2, 1555 RT5651_PWR_FV1 | RT5651_PWR_FV2); 1556 snd_soc_update_bits(codec, RT5651_PWR_ANLG1, 1557 RT5651_PWR_LDO_DVO_MASK, 1558 RT5651_PWR_LDO_DVO_1_2V); 1559 snd_soc_update_bits(codec, RT5651_D_MISC, 0x1, 0x1); 1560 if (snd_soc_read(codec, RT5651_PLL_MODE_1) & 0x9200) 1561 snd_soc_update_bits(codec, RT5651_D_MISC, 1562 0xc00, 0xc00); 1563 } 1564 break; 1565 1566 case SND_SOC_BIAS_STANDBY: 1567 snd_soc_write(codec, RT5651_D_MISC, 0x0010); 1568 snd_soc_write(codec, RT5651_PWR_DIG1, 0x0000); 1569 snd_soc_write(codec, RT5651_PWR_DIG2, 0x0000); 1570 snd_soc_write(codec, RT5651_PWR_VOL, 0x0000); 1571 snd_soc_write(codec, RT5651_PWR_MIXER, 0x0000); 1572 if (rt5651->pdata.jd_src) { 1573 snd_soc_write(codec, RT5651_PWR_ANLG2, 0x0204); 1574 snd_soc_write(codec, RT5651_PWR_ANLG1, 0x0002); 1575 } else { 1576 snd_soc_write(codec, RT5651_PWR_ANLG1, 0x0000); 1577 snd_soc_write(codec, RT5651_PWR_ANLG2, 0x0000); 1578 } 1579 break; 1580 1581 default: 1582 break; 1583 } 1584 1585 return 0; 1586 } 1587 1588 static int rt5651_probe(struct snd_soc_codec *codec) 1589 { 1590 struct rt5651_priv *rt5651 = snd_soc_codec_get_drvdata(codec); 1591 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec); 1592 1593 rt5651->codec = codec; 1594 1595 snd_soc_update_bits(codec, RT5651_PWR_ANLG1, 1596 RT5651_PWR_VREF1 | RT5651_PWR_MB | 1597 RT5651_PWR_BG | RT5651_PWR_VREF2, 1598 RT5651_PWR_VREF1 | RT5651_PWR_MB | 1599 RT5651_PWR_BG | RT5651_PWR_VREF2); 1600 usleep_range(10000, 15000); 1601 snd_soc_update_bits(codec, RT5651_PWR_ANLG1, 1602 RT5651_PWR_FV1 | RT5651_PWR_FV2, 1603 RT5651_PWR_FV1 | RT5651_PWR_FV2); 1604 1605 snd_soc_codec_force_bias_level(codec, SND_SOC_BIAS_OFF); 1606 1607 if (rt5651->pdata.jd_src) { 1608 snd_soc_dapm_force_enable_pin(dapm, "JD Power"); 1609 snd_soc_dapm_force_enable_pin(dapm, "LDO"); 1610 snd_soc_dapm_sync(dapm); 1611 1612 regmap_update_bits(rt5651->regmap, RT5651_MICBIAS, 1613 0x38, 0x38); 1614 } 1615 1616 return 0; 1617 } 1618 1619 #ifdef CONFIG_PM 1620 static int rt5651_suspend(struct snd_soc_codec *codec) 1621 { 1622 struct rt5651_priv *rt5651 = snd_soc_codec_get_drvdata(codec); 1623 1624 regcache_cache_only(rt5651->regmap, true); 1625 regcache_mark_dirty(rt5651->regmap); 1626 return 0; 1627 } 1628 1629 static int rt5651_resume(struct snd_soc_codec *codec) 1630 { 1631 struct rt5651_priv *rt5651 = snd_soc_codec_get_drvdata(codec); 1632 1633 regcache_cache_only(rt5651->regmap, false); 1634 snd_soc_cache_sync(codec); 1635 1636 return 0; 1637 } 1638 #else 1639 #define rt5651_suspend NULL 1640 #define rt5651_resume NULL 1641 #endif 1642 1643 #define RT5651_STEREO_RATES SNDRV_PCM_RATE_8000_96000 1644 #define RT5651_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ 1645 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8) 1646 1647 static const struct snd_soc_dai_ops rt5651_aif_dai_ops = { 1648 .hw_params = rt5651_hw_params, 1649 .set_fmt = rt5651_set_dai_fmt, 1650 .set_sysclk = rt5651_set_dai_sysclk, 1651 .set_pll = rt5651_set_dai_pll, 1652 }; 1653 1654 static struct snd_soc_dai_driver rt5651_dai[] = { 1655 { 1656 .name = "rt5651-aif1", 1657 .id = RT5651_AIF1, 1658 .playback = { 1659 .stream_name = "AIF1 Playback", 1660 .channels_min = 1, 1661 .channels_max = 2, 1662 .rates = RT5651_STEREO_RATES, 1663 .formats = RT5651_FORMATS, 1664 }, 1665 .capture = { 1666 .stream_name = "AIF1 Capture", 1667 .channels_min = 1, 1668 .channels_max = 2, 1669 .rates = RT5651_STEREO_RATES, 1670 .formats = RT5651_FORMATS, 1671 }, 1672 .ops = &rt5651_aif_dai_ops, 1673 }, 1674 { 1675 .name = "rt5651-aif2", 1676 .id = RT5651_AIF2, 1677 .playback = { 1678 .stream_name = "AIF2 Playback", 1679 .channels_min = 1, 1680 .channels_max = 2, 1681 .rates = RT5651_STEREO_RATES, 1682 .formats = RT5651_FORMATS, 1683 }, 1684 .capture = { 1685 .stream_name = "AIF2 Capture", 1686 .channels_min = 1, 1687 .channels_max = 2, 1688 .rates = RT5651_STEREO_RATES, 1689 .formats = RT5651_FORMATS, 1690 }, 1691 .ops = &rt5651_aif_dai_ops, 1692 }, 1693 }; 1694 1695 static const struct snd_soc_codec_driver soc_codec_dev_rt5651 = { 1696 .probe = rt5651_probe, 1697 .suspend = rt5651_suspend, 1698 .resume = rt5651_resume, 1699 .set_bias_level = rt5651_set_bias_level, 1700 .idle_bias_off = true, 1701 .component_driver = { 1702 .controls = rt5651_snd_controls, 1703 .num_controls = ARRAY_SIZE(rt5651_snd_controls), 1704 .dapm_widgets = rt5651_dapm_widgets, 1705 .num_dapm_widgets = ARRAY_SIZE(rt5651_dapm_widgets), 1706 .dapm_routes = rt5651_dapm_routes, 1707 .num_dapm_routes = ARRAY_SIZE(rt5651_dapm_routes), 1708 }, 1709 }; 1710 1711 static const struct regmap_config rt5651_regmap = { 1712 .reg_bits = 8, 1713 .val_bits = 16, 1714 1715 .max_register = RT5651_DEVICE_ID + 1 + (ARRAY_SIZE(rt5651_ranges) * 1716 RT5651_PR_SPACING), 1717 .volatile_reg = rt5651_volatile_register, 1718 .readable_reg = rt5651_readable_register, 1719 1720 .cache_type = REGCACHE_RBTREE, 1721 .reg_defaults = rt5651_reg, 1722 .num_reg_defaults = ARRAY_SIZE(rt5651_reg), 1723 .ranges = rt5651_ranges, 1724 .num_ranges = ARRAY_SIZE(rt5651_ranges), 1725 .use_single_rw = true, 1726 }; 1727 1728 #if defined(CONFIG_OF) 1729 static const struct of_device_id rt5651_of_match[] = { 1730 { .compatible = "realtek,rt5651", }, 1731 {}, 1732 }; 1733 MODULE_DEVICE_TABLE(of, rt5651_of_match); 1734 #endif 1735 1736 #ifdef CONFIG_ACPI 1737 static const struct acpi_device_id rt5651_acpi_match[] = { 1738 { "10EC5651", 0 }, 1739 { }, 1740 }; 1741 MODULE_DEVICE_TABLE(acpi, rt5651_acpi_match); 1742 #endif 1743 1744 static const struct i2c_device_id rt5651_i2c_id[] = { 1745 { "rt5651", 0 }, 1746 { } 1747 }; 1748 MODULE_DEVICE_TABLE(i2c, rt5651_i2c_id); 1749 1750 static int rt5651_quirk_cb(const struct dmi_system_id *id) 1751 { 1752 rt5651_quirk = (unsigned long) id->driver_data; 1753 return 1; 1754 } 1755 1756 static const struct dmi_system_id rt5651_quirk_table[] = { 1757 { 1758 .callback = rt5651_quirk_cb, 1759 .matches = { 1760 DMI_MATCH(DMI_SYS_VENDOR, "KIANO"), 1761 DMI_MATCH(DMI_PRODUCT_NAME, "KIANO SlimNote 14.2"), 1762 }, 1763 .driver_data = (unsigned long *) RT5651_JD1_1, 1764 }, 1765 {} 1766 }; 1767 1768 static int rt5651_parse_dt(struct rt5651_priv *rt5651, struct device_node *np) 1769 { 1770 if (of_property_read_bool(np, "realtek,in2-differential")) 1771 rt5651_quirk |= RT5651_IN2_DIFF; 1772 if (of_property_read_bool(np, "realtek,dmic-en")) 1773 rt5651_quirk |= RT5651_DMIC_EN; 1774 1775 return 0; 1776 } 1777 1778 static void rt5651_set_pdata(struct rt5651_priv *rt5651) 1779 { 1780 if (rt5651_quirk & RT5651_IN2_DIFF) 1781 rt5651->pdata.in2_diff = true; 1782 if (rt5651_quirk & RT5651_DMIC_EN) 1783 rt5651->pdata.dmic_en = true; 1784 if (RT5651_JD_MAP(rt5651_quirk)) 1785 rt5651->pdata.jd_src = RT5651_JD_MAP(rt5651_quirk); 1786 } 1787 1788 static irqreturn_t rt5651_irq(int irq, void *data) 1789 { 1790 struct rt5651_priv *rt5651 = data; 1791 1792 queue_delayed_work(system_power_efficient_wq, 1793 &rt5651->jack_detect_work, msecs_to_jiffies(250)); 1794 1795 return IRQ_HANDLED; 1796 } 1797 1798 static int rt5651_jack_detect(struct snd_soc_codec *codec, int jack_insert) 1799 { 1800 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec); 1801 int jack_type; 1802 1803 if (jack_insert) { 1804 snd_soc_dapm_force_enable_pin(dapm, "LDO"); 1805 snd_soc_dapm_sync(dapm); 1806 1807 snd_soc_update_bits(codec, RT5651_MICBIAS, 1808 RT5651_MIC1_OVCD_MASK | 1809 RT5651_MIC1_OVTH_MASK | 1810 RT5651_PWR_CLK12M_MASK | 1811 RT5651_PWR_MB_MASK, 1812 RT5651_MIC1_OVCD_EN | 1813 RT5651_MIC1_OVTH_600UA | 1814 RT5651_PWR_MB_PU | 1815 RT5651_PWR_CLK12M_PU); 1816 msleep(100); 1817 if (snd_soc_read(codec, RT5651_IRQ_CTRL2) & RT5651_MB1_OC_CLR) 1818 jack_type = SND_JACK_HEADPHONE; 1819 else 1820 jack_type = SND_JACK_HEADSET; 1821 snd_soc_update_bits(codec, RT5651_IRQ_CTRL2, 1822 RT5651_MB1_OC_CLR, 0); 1823 } else { /* jack out */ 1824 jack_type = 0; 1825 1826 snd_soc_update_bits(codec, RT5651_MICBIAS, 1827 RT5651_MIC1_OVCD_MASK, 1828 RT5651_MIC1_OVCD_DIS); 1829 } 1830 1831 return jack_type; 1832 } 1833 1834 static void rt5651_jack_detect_work(struct work_struct *work) 1835 { 1836 struct rt5651_priv *rt5651 = 1837 container_of(work, struct rt5651_priv, jack_detect_work.work); 1838 1839 int report, val = 0; 1840 1841 if (!rt5651->codec) 1842 return; 1843 1844 switch (rt5651->pdata.jd_src) { 1845 case RT5651_JD1_1: 1846 val = snd_soc_read(rt5651->codec, RT5651_INT_IRQ_ST) & 0x1000; 1847 break; 1848 case RT5651_JD1_2: 1849 val = snd_soc_read(rt5651->codec, RT5651_INT_IRQ_ST) & 0x2000; 1850 break; 1851 case RT5651_JD2: 1852 val = snd_soc_read(rt5651->codec, RT5651_INT_IRQ_ST) & 0x4000; 1853 break; 1854 default: 1855 break; 1856 } 1857 1858 report = rt5651_jack_detect(rt5651->codec, !val); 1859 1860 snd_soc_jack_report(rt5651->hp_jack, report, SND_JACK_HEADSET); 1861 } 1862 1863 int rt5651_set_jack_detect(struct snd_soc_codec *codec, 1864 struct snd_soc_jack *hp_jack) 1865 { 1866 struct rt5651_priv *rt5651 = snd_soc_codec_get_drvdata(codec); 1867 1868 rt5651->hp_jack = hp_jack; 1869 rt5651_irq(0, rt5651); 1870 1871 return 0; 1872 } 1873 EXPORT_SYMBOL_GPL(rt5651_set_jack_detect); 1874 1875 static int rt5651_i2c_probe(struct i2c_client *i2c, 1876 const struct i2c_device_id *id) 1877 { 1878 struct rt5651_platform_data *pdata = dev_get_platdata(&i2c->dev); 1879 struct rt5651_priv *rt5651; 1880 int ret; 1881 1882 rt5651 = devm_kzalloc(&i2c->dev, sizeof(*rt5651), 1883 GFP_KERNEL); 1884 if (NULL == rt5651) 1885 return -ENOMEM; 1886 1887 i2c_set_clientdata(i2c, rt5651); 1888 1889 if (pdata) 1890 rt5651->pdata = *pdata; 1891 else if (i2c->dev.of_node) 1892 rt5651_parse_dt(rt5651, i2c->dev.of_node); 1893 else 1894 dmi_check_system(rt5651_quirk_table); 1895 1896 rt5651_set_pdata(rt5651); 1897 1898 rt5651->regmap = devm_regmap_init_i2c(i2c, &rt5651_regmap); 1899 if (IS_ERR(rt5651->regmap)) { 1900 ret = PTR_ERR(rt5651->regmap); 1901 dev_err(&i2c->dev, "Failed to allocate register map: %d\n", 1902 ret); 1903 return ret; 1904 } 1905 1906 regmap_read(rt5651->regmap, RT5651_DEVICE_ID, &ret); 1907 if (ret != RT5651_DEVICE_ID_VALUE) { 1908 dev_err(&i2c->dev, 1909 "Device with ID register %#x is not rt5651\n", ret); 1910 return -ENODEV; 1911 } 1912 1913 regmap_write(rt5651->regmap, RT5651_RESET, 0); 1914 1915 ret = regmap_register_patch(rt5651->regmap, init_list, 1916 ARRAY_SIZE(init_list)); 1917 if (ret != 0) 1918 dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret); 1919 1920 if (rt5651->pdata.in2_diff) 1921 regmap_update_bits(rt5651->regmap, RT5651_IN1_IN2, 1922 RT5651_IN_DF2, RT5651_IN_DF2); 1923 1924 if (rt5651->pdata.dmic_en) 1925 regmap_update_bits(rt5651->regmap, RT5651_GPIO_CTRL1, 1926 RT5651_GP2_PIN_MASK, RT5651_GP2_PIN_DMIC1_SCL); 1927 1928 rt5651->hp_mute = 1; 1929 1930 if (rt5651->pdata.jd_src) { 1931 1932 /* IRQ output on GPIO1 */ 1933 regmap_update_bits(rt5651->regmap, RT5651_GPIO_CTRL1, 1934 RT5651_GP1_PIN_MASK, RT5651_GP1_PIN_IRQ); 1935 1936 switch (rt5651->pdata.jd_src) { 1937 case RT5651_JD1_1: 1938 regmap_update_bits(rt5651->regmap, RT5651_JD_CTRL2, 1939 RT5651_JD_TRG_SEL_MASK, 1940 RT5651_JD_TRG_SEL_JD1_1); 1941 regmap_update_bits(rt5651->regmap, RT5651_IRQ_CTRL1, 1942 RT5651_JD1_1_IRQ_EN, 1943 RT5651_JD1_1_IRQ_EN); 1944 break; 1945 case RT5651_JD1_2: 1946 regmap_update_bits(rt5651->regmap, RT5651_JD_CTRL2, 1947 RT5651_JD_TRG_SEL_MASK, 1948 RT5651_JD_TRG_SEL_JD1_2); 1949 regmap_update_bits(rt5651->regmap, RT5651_IRQ_CTRL1, 1950 RT5651_JD1_2_IRQ_EN, 1951 RT5651_JD1_2_IRQ_EN); 1952 break; 1953 case RT5651_JD2: 1954 regmap_update_bits(rt5651->regmap, RT5651_JD_CTRL2, 1955 RT5651_JD_TRG_SEL_MASK, 1956 RT5651_JD_TRG_SEL_JD2); 1957 regmap_update_bits(rt5651->regmap, RT5651_IRQ_CTRL1, 1958 RT5651_JD2_IRQ_EN, 1959 RT5651_JD2_IRQ_EN); 1960 break; 1961 case RT5651_JD_NULL: 1962 break; 1963 default: 1964 dev_warn(&i2c->dev, "Currently only JD1_1 / JD1_2 / JD2 are supported\n"); 1965 break; 1966 } 1967 } 1968 1969 INIT_DELAYED_WORK(&rt5651->jack_detect_work, rt5651_jack_detect_work); 1970 1971 if (i2c->irq) { 1972 ret = devm_request_threaded_irq(&i2c->dev, i2c->irq, NULL, 1973 rt5651_irq, 1974 IRQF_TRIGGER_RISING | 1975 IRQF_TRIGGER_FALLING | 1976 IRQF_ONESHOT, "rt5651", rt5651); 1977 if (ret) { 1978 dev_err(&i2c->dev, "Failed to reguest IRQ: %d\n", ret); 1979 return ret; 1980 } 1981 } 1982 1983 ret = snd_soc_register_codec(&i2c->dev, &soc_codec_dev_rt5651, 1984 rt5651_dai, ARRAY_SIZE(rt5651_dai)); 1985 1986 return ret; 1987 } 1988 1989 static int rt5651_i2c_remove(struct i2c_client *i2c) 1990 { 1991 struct rt5651_priv *rt5651 = i2c_get_clientdata(i2c); 1992 1993 cancel_delayed_work_sync(&rt5651->jack_detect_work); 1994 snd_soc_unregister_codec(&i2c->dev); 1995 1996 return 0; 1997 } 1998 1999 static struct i2c_driver rt5651_i2c_driver = { 2000 .driver = { 2001 .name = "rt5651", 2002 .acpi_match_table = ACPI_PTR(rt5651_acpi_match), 2003 .of_match_table = of_match_ptr(rt5651_of_match), 2004 }, 2005 .probe = rt5651_i2c_probe, 2006 .remove = rt5651_i2c_remove, 2007 .id_table = rt5651_i2c_id, 2008 }; 2009 module_i2c_driver(rt5651_i2c_driver); 2010 2011 MODULE_DESCRIPTION("ASoC RT5651 driver"); 2012 MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>"); 2013 MODULE_LICENSE("GPL v2"); 2014