1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * rt5645.c -- RT5645 ALSA SoC audio codec driver 4 * 5 * Copyright 2013 Realtek Semiconductor Corp. 6 * Author: Bard Liao <bardliao@realtek.com> 7 */ 8 9 #include <linux/module.h> 10 #include <linux/moduleparam.h> 11 #include <linux/init.h> 12 #include <linux/delay.h> 13 #include <linux/pm.h> 14 #include <linux/i2c.h> 15 #include <linux/platform_device.h> 16 #include <linux/spi/spi.h> 17 #include <linux/gpio.h> 18 #include <linux/gpio/consumer.h> 19 #include <linux/acpi.h> 20 #include <linux/dmi.h> 21 #include <linux/regulator/consumer.h> 22 #include <sound/core.h> 23 #include <sound/pcm.h> 24 #include <sound/pcm_params.h> 25 #include <sound/jack.h> 26 #include <sound/soc.h> 27 #include <sound/soc-dapm.h> 28 #include <sound/initval.h> 29 #include <sound/tlv.h> 30 31 #include "rl6231.h" 32 #include "rt5645.h" 33 34 #define QUIRK_INV_JD1_1(q) ((q) & 1) 35 #define QUIRK_LEVEL_IRQ(q) (((q) >> 1) & 1) 36 #define QUIRK_IN2_DIFF(q) (((q) >> 2) & 1) 37 #define QUIRK_INV_HP_POL(q) (((q) >> 3) & 1) 38 #define QUIRK_JD_MODE(q) (((q) >> 4) & 7) 39 #define QUIRK_DMIC1_DATA_PIN(q) (((q) >> 8) & 3) 40 #define QUIRK_DMIC2_DATA_PIN(q) (((q) >> 12) & 3) 41 42 static unsigned int quirk = -1; 43 module_param(quirk, uint, 0444); 44 MODULE_PARM_DESC(quirk, "RT5645 pdata quirk override"); 45 46 static const struct acpi_gpio_mapping *cht_rt5645_gpios; 47 48 #define RT5645_DEVICE_ID 0x6308 49 #define RT5650_DEVICE_ID 0x6419 50 51 #define RT5645_PR_RANGE_BASE (0xff + 1) 52 #define RT5645_PR_SPACING 0x100 53 54 #define RT5645_PR_BASE (RT5645_PR_RANGE_BASE + (0 * RT5645_PR_SPACING)) 55 56 #define RT5645_HWEQ_NUM 57 57 58 #define TIME_TO_POWER_MS 400 59 60 static const struct regmap_range_cfg rt5645_ranges[] = { 61 { 62 .name = "PR", 63 .range_min = RT5645_PR_BASE, 64 .range_max = RT5645_PR_BASE + 0xf8, 65 .selector_reg = RT5645_PRIV_INDEX, 66 .selector_mask = 0xff, 67 .selector_shift = 0x0, 68 .window_start = RT5645_PRIV_DATA, 69 .window_len = 0x1, 70 }, 71 }; 72 73 static const struct reg_sequence init_list[] = { 74 {RT5645_PR_BASE + 0x3d, 0x3600}, 75 {RT5645_PR_BASE + 0x1c, 0xfd70}, 76 {RT5645_PR_BASE + 0x20, 0x611f}, 77 {RT5645_PR_BASE + 0x21, 0x4040}, 78 {RT5645_PR_BASE + 0x23, 0x0004}, 79 {RT5645_ASRC_4, 0x0120}, 80 }; 81 82 static const struct reg_sequence rt5650_init_list[] = { 83 {0xf6, 0x0100}, 84 }; 85 86 static const struct reg_default rt5645_reg[] = { 87 { 0x00, 0x0000 }, 88 { 0x01, 0xc8c8 }, 89 { 0x02, 0xc8c8 }, 90 { 0x03, 0xc8c8 }, 91 { 0x0a, 0x0002 }, 92 { 0x0b, 0x2827 }, 93 { 0x0c, 0xe000 }, 94 { 0x0d, 0x0000 }, 95 { 0x0e, 0x0000 }, 96 { 0x0f, 0x0808 }, 97 { 0x14, 0x3333 }, 98 { 0x16, 0x4b00 }, 99 { 0x18, 0x018b }, 100 { 0x19, 0xafaf }, 101 { 0x1a, 0xafaf }, 102 { 0x1b, 0x0001 }, 103 { 0x1c, 0x2f2f }, 104 { 0x1d, 0x2f2f }, 105 { 0x1e, 0x0000 }, 106 { 0x20, 0x0000 }, 107 { 0x27, 0x7060 }, 108 { 0x28, 0x7070 }, 109 { 0x29, 0x8080 }, 110 { 0x2a, 0x5656 }, 111 { 0x2b, 0x5454 }, 112 { 0x2c, 0xaaa0 }, 113 { 0x2d, 0x0000 }, 114 { 0x2f, 0x1002 }, 115 { 0x31, 0x5000 }, 116 { 0x32, 0x0000 }, 117 { 0x33, 0x0000 }, 118 { 0x34, 0x0000 }, 119 { 0x35, 0x0000 }, 120 { 0x3b, 0x0000 }, 121 { 0x3c, 0x007f }, 122 { 0x3d, 0x0000 }, 123 { 0x3e, 0x007f }, 124 { 0x3f, 0x0000 }, 125 { 0x40, 0x001f }, 126 { 0x41, 0x0000 }, 127 { 0x42, 0x001f }, 128 { 0x45, 0x6000 }, 129 { 0x46, 0x003e }, 130 { 0x47, 0x003e }, 131 { 0x48, 0xf807 }, 132 { 0x4a, 0x0004 }, 133 { 0x4d, 0x0000 }, 134 { 0x4e, 0x0000 }, 135 { 0x4f, 0x01ff }, 136 { 0x50, 0x0000 }, 137 { 0x51, 0x0000 }, 138 { 0x52, 0x01ff }, 139 { 0x53, 0xf000 }, 140 { 0x56, 0x0111 }, 141 { 0x57, 0x0064 }, 142 { 0x58, 0xef0e }, 143 { 0x59, 0xf0f0 }, 144 { 0x5a, 0xef0e }, 145 { 0x5b, 0xf0f0 }, 146 { 0x5c, 0xef0e }, 147 { 0x5d, 0xf0f0 }, 148 { 0x5e, 0xf000 }, 149 { 0x5f, 0x0000 }, 150 { 0x61, 0x0300 }, 151 { 0x62, 0x0000 }, 152 { 0x63, 0x00c2 }, 153 { 0x64, 0x0000 }, 154 { 0x65, 0x0000 }, 155 { 0x66, 0x0000 }, 156 { 0x6a, 0x0000 }, 157 { 0x6c, 0x0aaa }, 158 { 0x70, 0x8000 }, 159 { 0x71, 0x8000 }, 160 { 0x72, 0x8000 }, 161 { 0x73, 0x7770 }, 162 { 0x74, 0x3e00 }, 163 { 0x75, 0x2409 }, 164 { 0x76, 0x000a }, 165 { 0x77, 0x0c00 }, 166 { 0x78, 0x0000 }, 167 { 0x79, 0x0123 }, 168 { 0x80, 0x0000 }, 169 { 0x81, 0x0000 }, 170 { 0x82, 0x0000 }, 171 { 0x83, 0x0000 }, 172 { 0x84, 0x0000 }, 173 { 0x85, 0x0000 }, 174 { 0x8a, 0x0120 }, 175 { 0x8e, 0x0004 }, 176 { 0x8f, 0x1100 }, 177 { 0x90, 0x0646 }, 178 { 0x91, 0x0c06 }, 179 { 0x93, 0x0000 }, 180 { 0x94, 0x0200 }, 181 { 0x95, 0x0000 }, 182 { 0x9a, 0x2184 }, 183 { 0x9b, 0x010a }, 184 { 0x9c, 0x0aea }, 185 { 0x9d, 0x000c }, 186 { 0x9e, 0x0400 }, 187 { 0xa0, 0xa0a8 }, 188 { 0xa1, 0x0059 }, 189 { 0xa2, 0x0001 }, 190 { 0xae, 0x6000 }, 191 { 0xaf, 0x0000 }, 192 { 0xb0, 0x6000 }, 193 { 0xb1, 0x0000 }, 194 { 0xb2, 0x0000 }, 195 { 0xb3, 0x001f }, 196 { 0xb4, 0x020c }, 197 { 0xb5, 0x1f00 }, 198 { 0xb6, 0x0000 }, 199 { 0xbb, 0x0000 }, 200 { 0xbc, 0x0000 }, 201 { 0xbd, 0x0000 }, 202 { 0xbe, 0x0000 }, 203 { 0xbf, 0x3100 }, 204 { 0xc0, 0x0000 }, 205 { 0xc1, 0x0000 }, 206 { 0xc2, 0x0000 }, 207 { 0xc3, 0x2000 }, 208 { 0xcd, 0x0000 }, 209 { 0xce, 0x0000 }, 210 { 0xcf, 0x1813 }, 211 { 0xd0, 0x0690 }, 212 { 0xd1, 0x1c17 }, 213 { 0xd3, 0xb320 }, 214 { 0xd4, 0x0000 }, 215 { 0xd6, 0x0400 }, 216 { 0xd9, 0x0809 }, 217 { 0xda, 0x0000 }, 218 { 0xdb, 0x0003 }, 219 { 0xdc, 0x0049 }, 220 { 0xdd, 0x001b }, 221 { 0xdf, 0x0008 }, 222 { 0xe0, 0x4000 }, 223 { 0xe6, 0x8000 }, 224 { 0xe7, 0x0200 }, 225 { 0xec, 0xb300 }, 226 { 0xed, 0x0000 }, 227 { 0xf0, 0x001f }, 228 { 0xf1, 0x020c }, 229 { 0xf2, 0x1f00 }, 230 { 0xf3, 0x0000 }, 231 { 0xf4, 0x4000 }, 232 { 0xf8, 0x0000 }, 233 { 0xf9, 0x0000 }, 234 { 0xfa, 0x2060 }, 235 { 0xfb, 0x4040 }, 236 { 0xfc, 0x0000 }, 237 { 0xfd, 0x0002 }, 238 { 0xfe, 0x10ec }, 239 { 0xff, 0x6308 }, 240 }; 241 242 static const struct reg_default rt5650_reg[] = { 243 { 0x00, 0x0000 }, 244 { 0x01, 0xc8c8 }, 245 { 0x02, 0xc8c8 }, 246 { 0x03, 0xc8c8 }, 247 { 0x0a, 0x0002 }, 248 { 0x0b, 0x2827 }, 249 { 0x0c, 0xe000 }, 250 { 0x0d, 0x0000 }, 251 { 0x0e, 0x0000 }, 252 { 0x0f, 0x0808 }, 253 { 0x14, 0x3333 }, 254 { 0x16, 0x4b00 }, 255 { 0x18, 0x018b }, 256 { 0x19, 0xafaf }, 257 { 0x1a, 0xafaf }, 258 { 0x1b, 0x0001 }, 259 { 0x1c, 0x2f2f }, 260 { 0x1d, 0x2f2f }, 261 { 0x1e, 0x0000 }, 262 { 0x20, 0x0000 }, 263 { 0x27, 0x7060 }, 264 { 0x28, 0x7070 }, 265 { 0x29, 0x8080 }, 266 { 0x2a, 0x5656 }, 267 { 0x2b, 0x5454 }, 268 { 0x2c, 0xaaa0 }, 269 { 0x2d, 0x0000 }, 270 { 0x2f, 0x5002 }, 271 { 0x31, 0x5000 }, 272 { 0x32, 0x0000 }, 273 { 0x33, 0x0000 }, 274 { 0x34, 0x0000 }, 275 { 0x35, 0x0000 }, 276 { 0x3b, 0x0000 }, 277 { 0x3c, 0x007f }, 278 { 0x3d, 0x0000 }, 279 { 0x3e, 0x007f }, 280 { 0x3f, 0x0000 }, 281 { 0x40, 0x001f }, 282 { 0x41, 0x0000 }, 283 { 0x42, 0x001f }, 284 { 0x45, 0x6000 }, 285 { 0x46, 0x003e }, 286 { 0x47, 0x003e }, 287 { 0x48, 0xf807 }, 288 { 0x4a, 0x0004 }, 289 { 0x4d, 0x0000 }, 290 { 0x4e, 0x0000 }, 291 { 0x4f, 0x01ff }, 292 { 0x50, 0x0000 }, 293 { 0x51, 0x0000 }, 294 { 0x52, 0x01ff }, 295 { 0x53, 0xf000 }, 296 { 0x56, 0x0111 }, 297 { 0x57, 0x0064 }, 298 { 0x58, 0xef0e }, 299 { 0x59, 0xf0f0 }, 300 { 0x5a, 0xef0e }, 301 { 0x5b, 0xf0f0 }, 302 { 0x5c, 0xef0e }, 303 { 0x5d, 0xf0f0 }, 304 { 0x5e, 0xf000 }, 305 { 0x5f, 0x0000 }, 306 { 0x61, 0x0300 }, 307 { 0x62, 0x0000 }, 308 { 0x63, 0x00c2 }, 309 { 0x64, 0x0000 }, 310 { 0x65, 0x0000 }, 311 { 0x66, 0x0000 }, 312 { 0x6a, 0x0000 }, 313 { 0x6c, 0x0aaa }, 314 { 0x70, 0x8000 }, 315 { 0x71, 0x8000 }, 316 { 0x72, 0x8000 }, 317 { 0x73, 0x7770 }, 318 { 0x74, 0x3e00 }, 319 { 0x75, 0x2409 }, 320 { 0x76, 0x000a }, 321 { 0x77, 0x0c00 }, 322 { 0x78, 0x0000 }, 323 { 0x79, 0x0123 }, 324 { 0x7a, 0x0123 }, 325 { 0x80, 0x0000 }, 326 { 0x81, 0x0000 }, 327 { 0x82, 0x0000 }, 328 { 0x83, 0x0000 }, 329 { 0x84, 0x0000 }, 330 { 0x85, 0x0000 }, 331 { 0x8a, 0x0120 }, 332 { 0x8e, 0x0004 }, 333 { 0x8f, 0x1100 }, 334 { 0x90, 0x0646 }, 335 { 0x91, 0x0c06 }, 336 { 0x93, 0x0000 }, 337 { 0x94, 0x0200 }, 338 { 0x95, 0x0000 }, 339 { 0x9a, 0x2184 }, 340 { 0x9b, 0x010a }, 341 { 0x9c, 0x0aea }, 342 { 0x9d, 0x000c }, 343 { 0x9e, 0x0400 }, 344 { 0xa0, 0xa0a8 }, 345 { 0xa1, 0x0059 }, 346 { 0xa2, 0x0001 }, 347 { 0xae, 0x6000 }, 348 { 0xaf, 0x0000 }, 349 { 0xb0, 0x6000 }, 350 { 0xb1, 0x0000 }, 351 { 0xb2, 0x0000 }, 352 { 0xb3, 0x001f }, 353 { 0xb4, 0x020c }, 354 { 0xb5, 0x1f00 }, 355 { 0xb6, 0x0000 }, 356 { 0xbb, 0x0000 }, 357 { 0xbc, 0x0000 }, 358 { 0xbd, 0x0000 }, 359 { 0xbe, 0x0000 }, 360 { 0xbf, 0x3100 }, 361 { 0xc0, 0x0000 }, 362 { 0xc1, 0x0000 }, 363 { 0xc2, 0x0000 }, 364 { 0xc3, 0x2000 }, 365 { 0xcd, 0x0000 }, 366 { 0xce, 0x0000 }, 367 { 0xcf, 0x1813 }, 368 { 0xd0, 0x0690 }, 369 { 0xd1, 0x1c17 }, 370 { 0xd3, 0xb320 }, 371 { 0xd4, 0x0000 }, 372 { 0xd6, 0x0400 }, 373 { 0xd9, 0x0809 }, 374 { 0xda, 0x0000 }, 375 { 0xdb, 0x0003 }, 376 { 0xdc, 0x0049 }, 377 { 0xdd, 0x001b }, 378 { 0xdf, 0x0008 }, 379 { 0xe0, 0x4000 }, 380 { 0xe6, 0x8000 }, 381 { 0xe7, 0x0200 }, 382 { 0xec, 0xb300 }, 383 { 0xed, 0x0000 }, 384 { 0xf0, 0x001f }, 385 { 0xf1, 0x020c }, 386 { 0xf2, 0x1f00 }, 387 { 0xf3, 0x0000 }, 388 { 0xf4, 0x4000 }, 389 { 0xf8, 0x0000 }, 390 { 0xf9, 0x0000 }, 391 { 0xfa, 0x2060 }, 392 { 0xfb, 0x4040 }, 393 { 0xfc, 0x0000 }, 394 { 0xfd, 0x0002 }, 395 { 0xfe, 0x10ec }, 396 { 0xff, 0x6308 }, 397 }; 398 399 struct rt5645_eq_param_s { 400 unsigned short reg; 401 unsigned short val; 402 }; 403 404 struct rt5645_eq_param_s_be16 { 405 __be16 reg; 406 __be16 val; 407 }; 408 409 static const char *const rt5645_supply_names[] = { 410 "avdd", 411 "cpvdd", 412 }; 413 414 struct rt5645_priv { 415 struct snd_soc_component *component; 416 struct rt5645_platform_data pdata; 417 struct regmap *regmap; 418 struct i2c_client *i2c; 419 struct gpio_desc *gpiod_hp_det; 420 struct snd_soc_jack *hp_jack; 421 struct snd_soc_jack *mic_jack; 422 struct snd_soc_jack *btn_jack; 423 struct delayed_work jack_detect_work, rcclock_work; 424 struct regulator_bulk_data supplies[ARRAY_SIZE(rt5645_supply_names)]; 425 struct rt5645_eq_param_s *eq_param; 426 struct timer_list btn_check_timer; 427 428 int codec_type; 429 int sysclk; 430 int sysclk_src; 431 int lrck[RT5645_AIFS]; 432 int bclk[RT5645_AIFS]; 433 int master[RT5645_AIFS]; 434 435 int pll_src; 436 int pll_in; 437 int pll_out; 438 439 int jack_type; 440 bool en_button_func; 441 int v_id; 442 }; 443 444 static int rt5645_reset(struct snd_soc_component *component) 445 { 446 return snd_soc_component_write(component, RT5645_RESET, 0); 447 } 448 449 static bool rt5645_volatile_register(struct device *dev, unsigned int reg) 450 { 451 int i; 452 453 for (i = 0; i < ARRAY_SIZE(rt5645_ranges); i++) { 454 if (reg >= rt5645_ranges[i].range_min && 455 reg <= rt5645_ranges[i].range_max) { 456 return true; 457 } 458 } 459 460 switch (reg) { 461 case RT5645_RESET: 462 case RT5645_PRIV_INDEX: 463 case RT5645_PRIV_DATA: 464 case RT5645_IN1_CTRL1: 465 case RT5645_IN1_CTRL2: 466 case RT5645_IN1_CTRL3: 467 case RT5645_A_JD_CTRL1: 468 case RT5645_ADC_EQ_CTRL1: 469 case RT5645_EQ_CTRL1: 470 case RT5645_ALC_CTRL_1: 471 case RT5645_IRQ_CTRL2: 472 case RT5645_IRQ_CTRL3: 473 case RT5645_INT_IRQ_ST: 474 case RT5645_IL_CMD: 475 case RT5650_4BTN_IL_CMD1: 476 case RT5645_VENDOR_ID: 477 case RT5645_VENDOR_ID1: 478 case RT5645_VENDOR_ID2: 479 return true; 480 default: 481 return false; 482 } 483 } 484 485 static bool rt5645_readable_register(struct device *dev, unsigned int reg) 486 { 487 int i; 488 489 for (i = 0; i < ARRAY_SIZE(rt5645_ranges); i++) { 490 if (reg >= rt5645_ranges[i].range_min && 491 reg <= rt5645_ranges[i].range_max) { 492 return true; 493 } 494 } 495 496 switch (reg) { 497 case RT5645_RESET: 498 case RT5645_SPK_VOL: 499 case RT5645_HP_VOL: 500 case RT5645_LOUT1: 501 case RT5645_IN1_CTRL1: 502 case RT5645_IN1_CTRL2: 503 case RT5645_IN1_CTRL3: 504 case RT5645_IN2_CTRL: 505 case RT5645_INL1_INR1_VOL: 506 case RT5645_SPK_FUNC_LIM: 507 case RT5645_ADJ_HPF_CTRL: 508 case RT5645_DAC1_DIG_VOL: 509 case RT5645_DAC2_DIG_VOL: 510 case RT5645_DAC_CTRL: 511 case RT5645_STO1_ADC_DIG_VOL: 512 case RT5645_MONO_ADC_DIG_VOL: 513 case RT5645_ADC_BST_VOL1: 514 case RT5645_ADC_BST_VOL2: 515 case RT5645_STO1_ADC_MIXER: 516 case RT5645_MONO_ADC_MIXER: 517 case RT5645_AD_DA_MIXER: 518 case RT5645_STO_DAC_MIXER: 519 case RT5645_MONO_DAC_MIXER: 520 case RT5645_DIG_MIXER: 521 case RT5650_A_DAC_SOUR: 522 case RT5645_DIG_INF1_DATA: 523 case RT5645_PDM_OUT_CTRL: 524 case RT5645_REC_L1_MIXER: 525 case RT5645_REC_L2_MIXER: 526 case RT5645_REC_R1_MIXER: 527 case RT5645_REC_R2_MIXER: 528 case RT5645_HPMIXL_CTRL: 529 case RT5645_HPOMIXL_CTRL: 530 case RT5645_HPMIXR_CTRL: 531 case RT5645_HPOMIXR_CTRL: 532 case RT5645_HPO_MIXER: 533 case RT5645_SPK_L_MIXER: 534 case RT5645_SPK_R_MIXER: 535 case RT5645_SPO_MIXER: 536 case RT5645_SPO_CLSD_RATIO: 537 case RT5645_OUT_L1_MIXER: 538 case RT5645_OUT_R1_MIXER: 539 case RT5645_OUT_L_GAIN1: 540 case RT5645_OUT_L_GAIN2: 541 case RT5645_OUT_R_GAIN1: 542 case RT5645_OUT_R_GAIN2: 543 case RT5645_LOUT_MIXER: 544 case RT5645_HAPTIC_CTRL1: 545 case RT5645_HAPTIC_CTRL2: 546 case RT5645_HAPTIC_CTRL3: 547 case RT5645_HAPTIC_CTRL4: 548 case RT5645_HAPTIC_CTRL5: 549 case RT5645_HAPTIC_CTRL6: 550 case RT5645_HAPTIC_CTRL7: 551 case RT5645_HAPTIC_CTRL8: 552 case RT5645_HAPTIC_CTRL9: 553 case RT5645_HAPTIC_CTRL10: 554 case RT5645_PWR_DIG1: 555 case RT5645_PWR_DIG2: 556 case RT5645_PWR_ANLG1: 557 case RT5645_PWR_ANLG2: 558 case RT5645_PWR_MIXER: 559 case RT5645_PWR_VOL: 560 case RT5645_PRIV_INDEX: 561 case RT5645_PRIV_DATA: 562 case RT5645_I2S1_SDP: 563 case RT5645_I2S2_SDP: 564 case RT5645_ADDA_CLK1: 565 case RT5645_ADDA_CLK2: 566 case RT5645_DMIC_CTRL1: 567 case RT5645_DMIC_CTRL2: 568 case RT5645_TDM_CTRL_1: 569 case RT5645_TDM_CTRL_2: 570 case RT5645_TDM_CTRL_3: 571 case RT5650_TDM_CTRL_4: 572 case RT5645_GLB_CLK: 573 case RT5645_PLL_CTRL1: 574 case RT5645_PLL_CTRL2: 575 case RT5645_ASRC_1: 576 case RT5645_ASRC_2: 577 case RT5645_ASRC_3: 578 case RT5645_ASRC_4: 579 case RT5645_DEPOP_M1: 580 case RT5645_DEPOP_M2: 581 case RT5645_DEPOP_M3: 582 case RT5645_CHARGE_PUMP: 583 case RT5645_MICBIAS: 584 case RT5645_A_JD_CTRL1: 585 case RT5645_VAD_CTRL4: 586 case RT5645_CLSD_OUT_CTRL: 587 case RT5645_ADC_EQ_CTRL1: 588 case RT5645_ADC_EQ_CTRL2: 589 case RT5645_EQ_CTRL1: 590 case RT5645_EQ_CTRL2: 591 case RT5645_ALC_CTRL_1: 592 case RT5645_ALC_CTRL_2: 593 case RT5645_ALC_CTRL_3: 594 case RT5645_ALC_CTRL_4: 595 case RT5645_ALC_CTRL_5: 596 case RT5645_JD_CTRL: 597 case RT5645_IRQ_CTRL1: 598 case RT5645_IRQ_CTRL2: 599 case RT5645_IRQ_CTRL3: 600 case RT5645_INT_IRQ_ST: 601 case RT5645_GPIO_CTRL1: 602 case RT5645_GPIO_CTRL2: 603 case RT5645_GPIO_CTRL3: 604 case RT5645_BASS_BACK: 605 case RT5645_MP3_PLUS1: 606 case RT5645_MP3_PLUS2: 607 case RT5645_ADJ_HPF1: 608 case RT5645_ADJ_HPF2: 609 case RT5645_HP_CALIB_AMP_DET: 610 case RT5645_SV_ZCD1: 611 case RT5645_SV_ZCD2: 612 case RT5645_IL_CMD: 613 case RT5645_IL_CMD2: 614 case RT5645_IL_CMD3: 615 case RT5650_4BTN_IL_CMD1: 616 case RT5650_4BTN_IL_CMD2: 617 case RT5645_DRC1_HL_CTRL1: 618 case RT5645_DRC2_HL_CTRL1: 619 case RT5645_ADC_MONO_HP_CTRL1: 620 case RT5645_ADC_MONO_HP_CTRL2: 621 case RT5645_DRC2_CTRL1: 622 case RT5645_DRC2_CTRL2: 623 case RT5645_DRC2_CTRL3: 624 case RT5645_DRC2_CTRL4: 625 case RT5645_DRC2_CTRL5: 626 case RT5645_JD_CTRL3: 627 case RT5645_JD_CTRL4: 628 case RT5645_GEN_CTRL1: 629 case RT5645_GEN_CTRL2: 630 case RT5645_GEN_CTRL3: 631 case RT5645_VENDOR_ID: 632 case RT5645_VENDOR_ID1: 633 case RT5645_VENDOR_ID2: 634 return true; 635 default: 636 return false; 637 } 638 } 639 640 static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -4650, 150, 0); 641 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6525, 75, 0); 642 static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -3450, 150, 0); 643 static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0); 644 static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0); 645 646 /* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */ 647 static const DECLARE_TLV_DB_RANGE(bst_tlv, 648 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0), 649 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0), 650 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0), 651 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0), 652 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0), 653 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0), 654 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0) 655 ); 656 657 /* {-6, -4.5, -3, -1.5, 0, 0.82, 1.58, 2.28} dB */ 658 static const DECLARE_TLV_DB_RANGE(spk_clsd_tlv, 659 0, 4, TLV_DB_SCALE_ITEM(-600, 150, 0), 660 5, 5, TLV_DB_SCALE_ITEM(82, 0, 0), 661 6, 6, TLV_DB_SCALE_ITEM(158, 0, 0), 662 7, 7, TLV_DB_SCALE_ITEM(228, 0, 0) 663 ); 664 665 static int rt5645_hweq_info(struct snd_kcontrol *kcontrol, 666 struct snd_ctl_elem_info *uinfo) 667 { 668 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES; 669 uinfo->count = RT5645_HWEQ_NUM * sizeof(struct rt5645_eq_param_s); 670 671 return 0; 672 } 673 674 static int rt5645_hweq_get(struct snd_kcontrol *kcontrol, 675 struct snd_ctl_elem_value *ucontrol) 676 { 677 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 678 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component); 679 struct rt5645_eq_param_s_be16 *eq_param = 680 (struct rt5645_eq_param_s_be16 *)ucontrol->value.bytes.data; 681 int i; 682 683 for (i = 0; i < RT5645_HWEQ_NUM; i++) { 684 eq_param[i].reg = cpu_to_be16(rt5645->eq_param[i].reg); 685 eq_param[i].val = cpu_to_be16(rt5645->eq_param[i].val); 686 } 687 688 return 0; 689 } 690 691 static bool rt5645_validate_hweq(unsigned short reg) 692 { 693 if ((reg >= 0x1a4 && reg <= 0x1cd) | (reg >= 0x1e5 && reg <= 0x1f8) | 694 (reg == RT5645_EQ_CTRL2)) 695 return true; 696 697 return false; 698 } 699 700 static int rt5645_hweq_put(struct snd_kcontrol *kcontrol, 701 struct snd_ctl_elem_value *ucontrol) 702 { 703 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 704 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component); 705 struct rt5645_eq_param_s_be16 *eq_param = 706 (struct rt5645_eq_param_s_be16 *)ucontrol->value.bytes.data; 707 int i; 708 709 for (i = 0; i < RT5645_HWEQ_NUM; i++) { 710 rt5645->eq_param[i].reg = be16_to_cpu(eq_param[i].reg); 711 rt5645->eq_param[i].val = be16_to_cpu(eq_param[i].val); 712 } 713 714 /* The final setting of the table should be RT5645_EQ_CTRL2 */ 715 for (i = RT5645_HWEQ_NUM - 1; i >= 0; i--) { 716 if (rt5645->eq_param[i].reg == 0) 717 continue; 718 else if (rt5645->eq_param[i].reg != RT5645_EQ_CTRL2) 719 return 0; 720 else 721 break; 722 } 723 724 for (i = 0; i < RT5645_HWEQ_NUM; i++) { 725 if (!rt5645_validate_hweq(rt5645->eq_param[i].reg) && 726 rt5645->eq_param[i].reg != 0) 727 return 0; 728 else if (rt5645->eq_param[i].reg == 0) 729 break; 730 } 731 732 return 0; 733 } 734 735 #define RT5645_HWEQ(xname) \ 736 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 737 .info = rt5645_hweq_info, \ 738 .get = rt5645_hweq_get, \ 739 .put = rt5645_hweq_put \ 740 } 741 742 static int rt5645_spk_put_volsw(struct snd_kcontrol *kcontrol, 743 struct snd_ctl_elem_value *ucontrol) 744 { 745 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 746 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component); 747 int ret; 748 749 regmap_update_bits(rt5645->regmap, RT5645_MICBIAS, 750 RT5645_PWR_CLK25M_MASK, RT5645_PWR_CLK25M_PU); 751 752 ret = snd_soc_put_volsw(kcontrol, ucontrol); 753 754 mod_delayed_work(system_power_efficient_wq, &rt5645->rcclock_work, 755 msecs_to_jiffies(200)); 756 757 return ret; 758 } 759 760 static const char * const rt5645_dac1_vol_ctrl_mode_text[] = { 761 "immediately", "zero crossing", "soft ramp" 762 }; 763 764 static SOC_ENUM_SINGLE_DECL( 765 rt5645_dac1_vol_ctrl_mode, RT5645_PR_BASE, 766 RT5645_DA1_ZDET_SFT, rt5645_dac1_vol_ctrl_mode_text); 767 768 static const struct snd_kcontrol_new rt5645_snd_controls[] = { 769 /* Speaker Output Volume */ 770 SOC_DOUBLE("Speaker Channel Switch", RT5645_SPK_VOL, 771 RT5645_VOL_L_SFT, RT5645_VOL_R_SFT, 1, 1), 772 SOC_DOUBLE_EXT_TLV("Speaker Playback Volume", RT5645_SPK_VOL, 773 RT5645_L_VOL_SFT, RT5645_R_VOL_SFT, 39, 1, snd_soc_get_volsw, 774 rt5645_spk_put_volsw, out_vol_tlv), 775 776 /* ClassD modulator Speaker Gain Ratio */ 777 SOC_SINGLE_TLV("Speaker ClassD Playback Volume", RT5645_SPO_CLSD_RATIO, 778 RT5645_SPK_G_CLSD_SFT, 7, 0, spk_clsd_tlv), 779 780 /* Headphone Output Volume */ 781 SOC_DOUBLE("Headphone Channel Switch", RT5645_HP_VOL, 782 RT5645_VOL_L_SFT, RT5645_VOL_R_SFT, 1, 1), 783 SOC_DOUBLE_TLV("Headphone Playback Volume", RT5645_HP_VOL, 784 RT5645_L_VOL_SFT, RT5645_R_VOL_SFT, 39, 1, out_vol_tlv), 785 786 /* OUTPUT Control */ 787 SOC_DOUBLE("OUT Playback Switch", RT5645_LOUT1, 788 RT5645_L_MUTE_SFT, RT5645_R_MUTE_SFT, 1, 1), 789 SOC_DOUBLE("OUT Channel Switch", RT5645_LOUT1, 790 RT5645_VOL_L_SFT, RT5645_VOL_R_SFT, 1, 1), 791 SOC_DOUBLE_TLV("OUT Playback Volume", RT5645_LOUT1, 792 RT5645_L_VOL_SFT, RT5645_R_VOL_SFT, 39, 1, out_vol_tlv), 793 794 /* DAC Digital Volume */ 795 SOC_DOUBLE("DAC2 Playback Switch", RT5645_DAC_CTRL, 796 RT5645_M_DAC_L2_VOL_SFT, RT5645_M_DAC_R2_VOL_SFT, 1, 1), 797 SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5645_DAC1_DIG_VOL, 798 RT5645_L_VOL_SFT + 1, RT5645_R_VOL_SFT + 1, 87, 0, dac_vol_tlv), 799 SOC_DOUBLE_TLV("Mono DAC Playback Volume", RT5645_DAC2_DIG_VOL, 800 RT5645_L_VOL_SFT + 1, RT5645_R_VOL_SFT + 1, 87, 0, dac_vol_tlv), 801 802 /* IN1/IN2 Control */ 803 SOC_SINGLE_TLV("IN1 Boost", RT5645_IN1_CTRL1, 804 RT5645_BST_SFT1, 12, 0, bst_tlv), 805 SOC_SINGLE_TLV("IN2 Boost", RT5645_IN2_CTRL, 806 RT5645_BST_SFT2, 8, 0, bst_tlv), 807 808 /* INL/INR Volume Control */ 809 SOC_DOUBLE_TLV("IN Capture Volume", RT5645_INL1_INR1_VOL, 810 RT5645_INL_VOL_SFT, RT5645_INR_VOL_SFT, 31, 1, in_vol_tlv), 811 812 /* ADC Digital Volume Control */ 813 SOC_DOUBLE("ADC Capture Switch", RT5645_STO1_ADC_DIG_VOL, 814 RT5645_L_MUTE_SFT, RT5645_R_MUTE_SFT, 1, 1), 815 SOC_DOUBLE_TLV("ADC Capture Volume", RT5645_STO1_ADC_DIG_VOL, 816 RT5645_L_VOL_SFT + 1, RT5645_R_VOL_SFT + 1, 63, 0, adc_vol_tlv), 817 SOC_DOUBLE("Mono ADC Capture Switch", RT5645_MONO_ADC_DIG_VOL, 818 RT5645_L_MUTE_SFT, RT5645_R_MUTE_SFT, 1, 1), 819 SOC_DOUBLE_TLV("Mono ADC Capture Volume", RT5645_MONO_ADC_DIG_VOL, 820 RT5645_L_VOL_SFT + 1, RT5645_R_VOL_SFT + 1, 63, 0, adc_vol_tlv), 821 822 /* ADC Boost Volume Control */ 823 SOC_DOUBLE_TLV("ADC Boost Capture Volume", RT5645_ADC_BST_VOL1, 824 RT5645_STO1_ADC_L_BST_SFT, RT5645_STO1_ADC_R_BST_SFT, 3, 0, 825 adc_bst_tlv), 826 SOC_DOUBLE_TLV("Mono ADC Boost Capture Volume", RT5645_ADC_BST_VOL2, 827 RT5645_MONO_ADC_L_BST_SFT, RT5645_MONO_ADC_R_BST_SFT, 3, 0, 828 adc_bst_tlv), 829 830 /* I2S2 function select */ 831 SOC_SINGLE("I2S2 Func Switch", RT5645_GPIO_CTRL1, RT5645_I2S2_SEL_SFT, 832 1, 1), 833 RT5645_HWEQ("Speaker HWEQ"), 834 835 /* Digital Soft Volume Control */ 836 SOC_ENUM("DAC1 Digital Volume Control Func", rt5645_dac1_vol_ctrl_mode), 837 }; 838 839 /** 840 * set_dmic_clk - Set parameter of dmic. 841 * 842 * @w: DAPM widget. 843 * @kcontrol: The kcontrol of this widget. 844 * @event: Event id. 845 * 846 */ 847 static int set_dmic_clk(struct snd_soc_dapm_widget *w, 848 struct snd_kcontrol *kcontrol, int event) 849 { 850 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 851 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component); 852 int idx, rate; 853 854 rate = rt5645->sysclk / rl6231_get_pre_div(rt5645->regmap, 855 RT5645_ADDA_CLK1, RT5645_I2S_PD1_SFT); 856 idx = rl6231_calc_dmic_clk(rate); 857 if (idx < 0) 858 dev_err(component->dev, "Failed to set DMIC clock\n"); 859 else 860 snd_soc_component_update_bits(component, RT5645_DMIC_CTRL1, 861 RT5645_DMIC_CLK_MASK, idx << RT5645_DMIC_CLK_SFT); 862 return idx; 863 } 864 865 static int is_sys_clk_from_pll(struct snd_soc_dapm_widget *source, 866 struct snd_soc_dapm_widget *sink) 867 { 868 struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm); 869 unsigned int val; 870 871 val = snd_soc_component_read(component, RT5645_GLB_CLK); 872 val &= RT5645_SCLK_SRC_MASK; 873 if (val == RT5645_SCLK_SRC_PLL1) 874 return 1; 875 else 876 return 0; 877 } 878 879 static int is_using_asrc(struct snd_soc_dapm_widget *source, 880 struct snd_soc_dapm_widget *sink) 881 { 882 struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm); 883 unsigned int reg, shift, val; 884 885 switch (source->shift) { 886 case 0: 887 reg = RT5645_ASRC_3; 888 shift = 0; 889 break; 890 case 1: 891 reg = RT5645_ASRC_3; 892 shift = 4; 893 break; 894 case 3: 895 reg = RT5645_ASRC_2; 896 shift = 0; 897 break; 898 case 8: 899 reg = RT5645_ASRC_2; 900 shift = 4; 901 break; 902 case 9: 903 reg = RT5645_ASRC_2; 904 shift = 8; 905 break; 906 case 10: 907 reg = RT5645_ASRC_2; 908 shift = 12; 909 break; 910 default: 911 return 0; 912 } 913 914 val = (snd_soc_component_read(component, reg) >> shift) & 0xf; 915 switch (val) { 916 case 1: 917 case 2: 918 case 3: 919 case 4: 920 return 1; 921 default: 922 return 0; 923 } 924 925 } 926 927 static int rt5645_enable_hweq(struct snd_soc_component *component) 928 { 929 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component); 930 int i; 931 932 for (i = 0; i < RT5645_HWEQ_NUM; i++) { 933 if (rt5645_validate_hweq(rt5645->eq_param[i].reg)) 934 regmap_write(rt5645->regmap, rt5645->eq_param[i].reg, 935 rt5645->eq_param[i].val); 936 else 937 break; 938 } 939 940 return 0; 941 } 942 943 /** 944 * rt5645_sel_asrc_clk_src - select ASRC clock source for a set of filters 945 * @component: SoC audio component device. 946 * @filter_mask: mask of filters. 947 * @clk_src: clock source 948 * 949 * The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5645 can 950 * only support standard 32fs or 64fs i2s format, ASRC should be enabled to 951 * support special i2s clock format such as Intel's 100fs(100 * sampling rate). 952 * ASRC function will track i2s clock and generate a corresponding system clock 953 * for codec. This function provides an API to select the clock source for a 954 * set of filters specified by the mask. And the codec driver will turn on ASRC 955 * for these filters if ASRC is selected as their clock source. 956 */ 957 int rt5645_sel_asrc_clk_src(struct snd_soc_component *component, 958 unsigned int filter_mask, unsigned int clk_src) 959 { 960 unsigned int asrc2_mask = 0; 961 unsigned int asrc2_value = 0; 962 unsigned int asrc3_mask = 0; 963 unsigned int asrc3_value = 0; 964 965 switch (clk_src) { 966 case RT5645_CLK_SEL_SYS: 967 case RT5645_CLK_SEL_I2S1_ASRC: 968 case RT5645_CLK_SEL_I2S2_ASRC: 969 case RT5645_CLK_SEL_SYS2: 970 break; 971 972 default: 973 return -EINVAL; 974 } 975 976 if (filter_mask & RT5645_DA_STEREO_FILTER) { 977 asrc2_mask |= RT5645_DA_STO_CLK_SEL_MASK; 978 asrc2_value = (asrc2_value & ~RT5645_DA_STO_CLK_SEL_MASK) 979 | (clk_src << RT5645_DA_STO_CLK_SEL_SFT); 980 } 981 982 if (filter_mask & RT5645_DA_MONO_L_FILTER) { 983 asrc2_mask |= RT5645_DA_MONOL_CLK_SEL_MASK; 984 asrc2_value = (asrc2_value & ~RT5645_DA_MONOL_CLK_SEL_MASK) 985 | (clk_src << RT5645_DA_MONOL_CLK_SEL_SFT); 986 } 987 988 if (filter_mask & RT5645_DA_MONO_R_FILTER) { 989 asrc2_mask |= RT5645_DA_MONOR_CLK_SEL_MASK; 990 asrc2_value = (asrc2_value & ~RT5645_DA_MONOR_CLK_SEL_MASK) 991 | (clk_src << RT5645_DA_MONOR_CLK_SEL_SFT); 992 } 993 994 if (filter_mask & RT5645_AD_STEREO_FILTER) { 995 asrc2_mask |= RT5645_AD_STO1_CLK_SEL_MASK; 996 asrc2_value = (asrc2_value & ~RT5645_AD_STO1_CLK_SEL_MASK) 997 | (clk_src << RT5645_AD_STO1_CLK_SEL_SFT); 998 } 999 1000 if (filter_mask & RT5645_AD_MONO_L_FILTER) { 1001 asrc3_mask |= RT5645_AD_MONOL_CLK_SEL_MASK; 1002 asrc3_value = (asrc3_value & ~RT5645_AD_MONOL_CLK_SEL_MASK) 1003 | (clk_src << RT5645_AD_MONOL_CLK_SEL_SFT); 1004 } 1005 1006 if (filter_mask & RT5645_AD_MONO_R_FILTER) { 1007 asrc3_mask |= RT5645_AD_MONOR_CLK_SEL_MASK; 1008 asrc3_value = (asrc3_value & ~RT5645_AD_MONOR_CLK_SEL_MASK) 1009 | (clk_src << RT5645_AD_MONOR_CLK_SEL_SFT); 1010 } 1011 1012 if (asrc2_mask) 1013 snd_soc_component_update_bits(component, RT5645_ASRC_2, 1014 asrc2_mask, asrc2_value); 1015 1016 if (asrc3_mask) 1017 snd_soc_component_update_bits(component, RT5645_ASRC_3, 1018 asrc3_mask, asrc3_value); 1019 1020 return 0; 1021 } 1022 EXPORT_SYMBOL_GPL(rt5645_sel_asrc_clk_src); 1023 1024 /* Digital Mixer */ 1025 static const struct snd_kcontrol_new rt5645_sto1_adc_l_mix[] = { 1026 SOC_DAPM_SINGLE("ADC1 Switch", RT5645_STO1_ADC_MIXER, 1027 RT5645_M_ADC_L1_SFT, 1, 1), 1028 SOC_DAPM_SINGLE("ADC2 Switch", RT5645_STO1_ADC_MIXER, 1029 RT5645_M_ADC_L2_SFT, 1, 1), 1030 }; 1031 1032 static const struct snd_kcontrol_new rt5645_sto1_adc_r_mix[] = { 1033 SOC_DAPM_SINGLE("ADC1 Switch", RT5645_STO1_ADC_MIXER, 1034 RT5645_M_ADC_R1_SFT, 1, 1), 1035 SOC_DAPM_SINGLE("ADC2 Switch", RT5645_STO1_ADC_MIXER, 1036 RT5645_M_ADC_R2_SFT, 1, 1), 1037 }; 1038 1039 static const struct snd_kcontrol_new rt5645_mono_adc_l_mix[] = { 1040 SOC_DAPM_SINGLE("ADC1 Switch", RT5645_MONO_ADC_MIXER, 1041 RT5645_M_MONO_ADC_L1_SFT, 1, 1), 1042 SOC_DAPM_SINGLE("ADC2 Switch", RT5645_MONO_ADC_MIXER, 1043 RT5645_M_MONO_ADC_L2_SFT, 1, 1), 1044 }; 1045 1046 static const struct snd_kcontrol_new rt5645_mono_adc_r_mix[] = { 1047 SOC_DAPM_SINGLE("ADC1 Switch", RT5645_MONO_ADC_MIXER, 1048 RT5645_M_MONO_ADC_R1_SFT, 1, 1), 1049 SOC_DAPM_SINGLE("ADC2 Switch", RT5645_MONO_ADC_MIXER, 1050 RT5645_M_MONO_ADC_R2_SFT, 1, 1), 1051 }; 1052 1053 static const struct snd_kcontrol_new rt5645_dac_l_mix[] = { 1054 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5645_AD_DA_MIXER, 1055 RT5645_M_ADCMIX_L_SFT, 1, 1), 1056 SOC_DAPM_SINGLE_AUTODISABLE("DAC1 Switch", RT5645_AD_DA_MIXER, 1057 RT5645_M_DAC1_L_SFT, 1, 1), 1058 }; 1059 1060 static const struct snd_kcontrol_new rt5645_dac_r_mix[] = { 1061 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5645_AD_DA_MIXER, 1062 RT5645_M_ADCMIX_R_SFT, 1, 1), 1063 SOC_DAPM_SINGLE_AUTODISABLE("DAC1 Switch", RT5645_AD_DA_MIXER, 1064 RT5645_M_DAC1_R_SFT, 1, 1), 1065 }; 1066 1067 static const struct snd_kcontrol_new rt5645_sto_dac_l_mix[] = { 1068 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_STO_DAC_MIXER, 1069 RT5645_M_DAC_L1_SFT, 1, 1), 1070 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_STO_DAC_MIXER, 1071 RT5645_M_DAC_L2_SFT, 1, 1), 1072 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_STO_DAC_MIXER, 1073 RT5645_M_DAC_R1_STO_L_SFT, 1, 1), 1074 }; 1075 1076 static const struct snd_kcontrol_new rt5645_sto_dac_r_mix[] = { 1077 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_STO_DAC_MIXER, 1078 RT5645_M_DAC_R1_SFT, 1, 1), 1079 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_STO_DAC_MIXER, 1080 RT5645_M_DAC_R2_SFT, 1, 1), 1081 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_STO_DAC_MIXER, 1082 RT5645_M_DAC_L1_STO_R_SFT, 1, 1), 1083 }; 1084 1085 static const struct snd_kcontrol_new rt5645_mono_dac_l_mix[] = { 1086 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_MONO_DAC_MIXER, 1087 RT5645_M_DAC_L1_MONO_L_SFT, 1, 1), 1088 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_MONO_DAC_MIXER, 1089 RT5645_M_DAC_L2_MONO_L_SFT, 1, 1), 1090 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_MONO_DAC_MIXER, 1091 RT5645_M_DAC_R2_MONO_L_SFT, 1, 1), 1092 }; 1093 1094 static const struct snd_kcontrol_new rt5645_mono_dac_r_mix[] = { 1095 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_MONO_DAC_MIXER, 1096 RT5645_M_DAC_R1_MONO_R_SFT, 1, 1), 1097 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_MONO_DAC_MIXER, 1098 RT5645_M_DAC_R2_MONO_R_SFT, 1, 1), 1099 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_MONO_DAC_MIXER, 1100 RT5645_M_DAC_L2_MONO_R_SFT, 1, 1), 1101 }; 1102 1103 static const struct snd_kcontrol_new rt5645_dig_l_mix[] = { 1104 SOC_DAPM_SINGLE("Sto DAC Mix L Switch", RT5645_DIG_MIXER, 1105 RT5645_M_STO_L_DAC_L_SFT, 1, 1), 1106 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_DIG_MIXER, 1107 RT5645_M_DAC_L2_DAC_L_SFT, 1, 1), 1108 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_DIG_MIXER, 1109 RT5645_M_DAC_R2_DAC_L_SFT, 1, 1), 1110 }; 1111 1112 static const struct snd_kcontrol_new rt5645_dig_r_mix[] = { 1113 SOC_DAPM_SINGLE("Sto DAC Mix R Switch", RT5645_DIG_MIXER, 1114 RT5645_M_STO_R_DAC_R_SFT, 1, 1), 1115 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_DIG_MIXER, 1116 RT5645_M_DAC_R2_DAC_R_SFT, 1, 1), 1117 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_DIG_MIXER, 1118 RT5645_M_DAC_L2_DAC_R_SFT, 1, 1), 1119 }; 1120 1121 /* Analog Input Mixer */ 1122 static const struct snd_kcontrol_new rt5645_rec_l_mix[] = { 1123 SOC_DAPM_SINGLE("HPOL Switch", RT5645_REC_L2_MIXER, 1124 RT5645_M_HP_L_RM_L_SFT, 1, 1), 1125 SOC_DAPM_SINGLE("INL Switch", RT5645_REC_L2_MIXER, 1126 RT5645_M_IN_L_RM_L_SFT, 1, 1), 1127 SOC_DAPM_SINGLE("BST2 Switch", RT5645_REC_L2_MIXER, 1128 RT5645_M_BST2_RM_L_SFT, 1, 1), 1129 SOC_DAPM_SINGLE("BST1 Switch", RT5645_REC_L2_MIXER, 1130 RT5645_M_BST1_RM_L_SFT, 1, 1), 1131 SOC_DAPM_SINGLE("OUT MIXL Switch", RT5645_REC_L2_MIXER, 1132 RT5645_M_OM_L_RM_L_SFT, 1, 1), 1133 }; 1134 1135 static const struct snd_kcontrol_new rt5645_rec_r_mix[] = { 1136 SOC_DAPM_SINGLE("HPOR Switch", RT5645_REC_R2_MIXER, 1137 RT5645_M_HP_R_RM_R_SFT, 1, 1), 1138 SOC_DAPM_SINGLE("INR Switch", RT5645_REC_R2_MIXER, 1139 RT5645_M_IN_R_RM_R_SFT, 1, 1), 1140 SOC_DAPM_SINGLE("BST2 Switch", RT5645_REC_R2_MIXER, 1141 RT5645_M_BST2_RM_R_SFT, 1, 1), 1142 SOC_DAPM_SINGLE("BST1 Switch", RT5645_REC_R2_MIXER, 1143 RT5645_M_BST1_RM_R_SFT, 1, 1), 1144 SOC_DAPM_SINGLE("OUT MIXR Switch", RT5645_REC_R2_MIXER, 1145 RT5645_M_OM_R_RM_R_SFT, 1, 1), 1146 }; 1147 1148 static const struct snd_kcontrol_new rt5645_spk_l_mix[] = { 1149 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_SPK_L_MIXER, 1150 RT5645_M_DAC_L1_SM_L_SFT, 1, 1), 1151 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_SPK_L_MIXER, 1152 RT5645_M_DAC_L2_SM_L_SFT, 1, 1), 1153 SOC_DAPM_SINGLE("INL Switch", RT5645_SPK_L_MIXER, 1154 RT5645_M_IN_L_SM_L_SFT, 1, 1), 1155 SOC_DAPM_SINGLE("BST1 Switch", RT5645_SPK_L_MIXER, 1156 RT5645_M_BST1_L_SM_L_SFT, 1, 1), 1157 }; 1158 1159 static const struct snd_kcontrol_new rt5645_spk_r_mix[] = { 1160 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_SPK_R_MIXER, 1161 RT5645_M_DAC_R1_SM_R_SFT, 1, 1), 1162 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_SPK_R_MIXER, 1163 RT5645_M_DAC_R2_SM_R_SFT, 1, 1), 1164 SOC_DAPM_SINGLE("INR Switch", RT5645_SPK_R_MIXER, 1165 RT5645_M_IN_R_SM_R_SFT, 1, 1), 1166 SOC_DAPM_SINGLE("BST2 Switch", RT5645_SPK_R_MIXER, 1167 RT5645_M_BST2_R_SM_R_SFT, 1, 1), 1168 }; 1169 1170 static const struct snd_kcontrol_new rt5645_out_l_mix[] = { 1171 SOC_DAPM_SINGLE("BST1 Switch", RT5645_OUT_L1_MIXER, 1172 RT5645_M_BST1_OM_L_SFT, 1, 1), 1173 SOC_DAPM_SINGLE("INL Switch", RT5645_OUT_L1_MIXER, 1174 RT5645_M_IN_L_OM_L_SFT, 1, 1), 1175 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_OUT_L1_MIXER, 1176 RT5645_M_DAC_L2_OM_L_SFT, 1, 1), 1177 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_OUT_L1_MIXER, 1178 RT5645_M_DAC_L1_OM_L_SFT, 1, 1), 1179 }; 1180 1181 static const struct snd_kcontrol_new rt5645_out_r_mix[] = { 1182 SOC_DAPM_SINGLE("BST2 Switch", RT5645_OUT_R1_MIXER, 1183 RT5645_M_BST2_OM_R_SFT, 1, 1), 1184 SOC_DAPM_SINGLE("INR Switch", RT5645_OUT_R1_MIXER, 1185 RT5645_M_IN_R_OM_R_SFT, 1, 1), 1186 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_OUT_R1_MIXER, 1187 RT5645_M_DAC_R2_OM_R_SFT, 1, 1), 1188 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_OUT_R1_MIXER, 1189 RT5645_M_DAC_R1_OM_R_SFT, 1, 1), 1190 }; 1191 1192 static const struct snd_kcontrol_new rt5645_spo_l_mix[] = { 1193 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_SPO_MIXER, 1194 RT5645_M_DAC_R1_SPM_L_SFT, 1, 1), 1195 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_SPO_MIXER, 1196 RT5645_M_DAC_L1_SPM_L_SFT, 1, 1), 1197 SOC_DAPM_SINGLE("SPKVOL R Switch", RT5645_SPO_MIXER, 1198 RT5645_M_SV_R_SPM_L_SFT, 1, 1), 1199 SOC_DAPM_SINGLE("SPKVOL L Switch", RT5645_SPO_MIXER, 1200 RT5645_M_SV_L_SPM_L_SFT, 1, 1), 1201 }; 1202 1203 static const struct snd_kcontrol_new rt5645_spo_r_mix[] = { 1204 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_SPO_MIXER, 1205 RT5645_M_DAC_R1_SPM_R_SFT, 1, 1), 1206 SOC_DAPM_SINGLE("SPKVOL R Switch", RT5645_SPO_MIXER, 1207 RT5645_M_SV_R_SPM_R_SFT, 1, 1), 1208 }; 1209 1210 static const struct snd_kcontrol_new rt5645_hpo_mix[] = { 1211 SOC_DAPM_SINGLE("DAC1 Switch", RT5645_HPO_MIXER, 1212 RT5645_M_DAC1_HM_SFT, 1, 1), 1213 SOC_DAPM_SINGLE("HPVOL Switch", RT5645_HPO_MIXER, 1214 RT5645_M_HPVOL_HM_SFT, 1, 1), 1215 }; 1216 1217 static const struct snd_kcontrol_new rt5645_hpvoll_mix[] = { 1218 SOC_DAPM_SINGLE("DAC1 Switch", RT5645_HPOMIXL_CTRL, 1219 RT5645_M_DAC1_HV_SFT, 1, 1), 1220 SOC_DAPM_SINGLE("DAC2 Switch", RT5645_HPOMIXL_CTRL, 1221 RT5645_M_DAC2_HV_SFT, 1, 1), 1222 SOC_DAPM_SINGLE("INL Switch", RT5645_HPOMIXL_CTRL, 1223 RT5645_M_IN_HV_SFT, 1, 1), 1224 SOC_DAPM_SINGLE("BST1 Switch", RT5645_HPOMIXL_CTRL, 1225 RT5645_M_BST1_HV_SFT, 1, 1), 1226 }; 1227 1228 static const struct snd_kcontrol_new rt5645_hpvolr_mix[] = { 1229 SOC_DAPM_SINGLE("DAC1 Switch", RT5645_HPOMIXR_CTRL, 1230 RT5645_M_DAC1_HV_SFT, 1, 1), 1231 SOC_DAPM_SINGLE("DAC2 Switch", RT5645_HPOMIXR_CTRL, 1232 RT5645_M_DAC2_HV_SFT, 1, 1), 1233 SOC_DAPM_SINGLE("INR Switch", RT5645_HPOMIXR_CTRL, 1234 RT5645_M_IN_HV_SFT, 1, 1), 1235 SOC_DAPM_SINGLE("BST2 Switch", RT5645_HPOMIXR_CTRL, 1236 RT5645_M_BST2_HV_SFT, 1, 1), 1237 }; 1238 1239 static const struct snd_kcontrol_new rt5645_lout_mix[] = { 1240 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_LOUT_MIXER, 1241 RT5645_M_DAC_L1_LM_SFT, 1, 1), 1242 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_LOUT_MIXER, 1243 RT5645_M_DAC_R1_LM_SFT, 1, 1), 1244 SOC_DAPM_SINGLE("OUTMIX L Switch", RT5645_LOUT_MIXER, 1245 RT5645_M_OV_L_LM_SFT, 1, 1), 1246 SOC_DAPM_SINGLE("OUTMIX R Switch", RT5645_LOUT_MIXER, 1247 RT5645_M_OV_R_LM_SFT, 1, 1), 1248 }; 1249 1250 /*DAC1 L/R source*/ /* MX-29 [9:8] [11:10] */ 1251 static const char * const rt5645_dac1_src[] = { 1252 "IF1 DAC", "IF2 DAC", "IF3 DAC" 1253 }; 1254 1255 static SOC_ENUM_SINGLE_DECL( 1256 rt5645_dac1l_enum, RT5645_AD_DA_MIXER, 1257 RT5645_DAC1_L_SEL_SFT, rt5645_dac1_src); 1258 1259 static const struct snd_kcontrol_new rt5645_dac1l_mux = 1260 SOC_DAPM_ENUM("DAC1 L source", rt5645_dac1l_enum); 1261 1262 static SOC_ENUM_SINGLE_DECL( 1263 rt5645_dac1r_enum, RT5645_AD_DA_MIXER, 1264 RT5645_DAC1_R_SEL_SFT, rt5645_dac1_src); 1265 1266 static const struct snd_kcontrol_new rt5645_dac1r_mux = 1267 SOC_DAPM_ENUM("DAC1 R source", rt5645_dac1r_enum); 1268 1269 /*DAC2 L/R source*/ /* MX-1B [6:4] [2:0] */ 1270 static const char * const rt5645_dac12_src[] = { 1271 "IF1 DAC", "IF2 DAC", "IF3 DAC", "Mono ADC", "VAD_ADC" 1272 }; 1273 1274 static SOC_ENUM_SINGLE_DECL( 1275 rt5645_dac2l_enum, RT5645_DAC_CTRL, 1276 RT5645_DAC2_L_SEL_SFT, rt5645_dac12_src); 1277 1278 static const struct snd_kcontrol_new rt5645_dac_l2_mux = 1279 SOC_DAPM_ENUM("DAC2 L source", rt5645_dac2l_enum); 1280 1281 static const char * const rt5645_dacr2_src[] = { 1282 "IF1 DAC", "IF2 DAC", "IF3 DAC", "Mono ADC", "Haptic" 1283 }; 1284 1285 static SOC_ENUM_SINGLE_DECL( 1286 rt5645_dac2r_enum, RT5645_DAC_CTRL, 1287 RT5645_DAC2_R_SEL_SFT, rt5645_dacr2_src); 1288 1289 static const struct snd_kcontrol_new rt5645_dac_r2_mux = 1290 SOC_DAPM_ENUM("DAC2 R source", rt5645_dac2r_enum); 1291 1292 /* Stereo1 ADC source */ 1293 /* MX-27 [12] */ 1294 static const char * const rt5645_stereo_adc1_src[] = { 1295 "DAC MIX", "ADC" 1296 }; 1297 1298 static SOC_ENUM_SINGLE_DECL( 1299 rt5645_stereo1_adc1_enum, RT5645_STO1_ADC_MIXER, 1300 RT5645_ADC_1_SRC_SFT, rt5645_stereo_adc1_src); 1301 1302 static const struct snd_kcontrol_new rt5645_sto_adc1_mux = 1303 SOC_DAPM_ENUM("Stereo1 ADC1 Mux", rt5645_stereo1_adc1_enum); 1304 1305 /* MX-27 [11] */ 1306 static const char * const rt5645_stereo_adc2_src[] = { 1307 "DAC MIX", "DMIC" 1308 }; 1309 1310 static SOC_ENUM_SINGLE_DECL( 1311 rt5645_stereo1_adc2_enum, RT5645_STO1_ADC_MIXER, 1312 RT5645_ADC_2_SRC_SFT, rt5645_stereo_adc2_src); 1313 1314 static const struct snd_kcontrol_new rt5645_sto_adc2_mux = 1315 SOC_DAPM_ENUM("Stereo1 ADC2 Mux", rt5645_stereo1_adc2_enum); 1316 1317 /* MX-27 [8] */ 1318 static const char * const rt5645_stereo_dmic_src[] = { 1319 "DMIC1", "DMIC2" 1320 }; 1321 1322 static SOC_ENUM_SINGLE_DECL( 1323 rt5645_stereo1_dmic_enum, RT5645_STO1_ADC_MIXER, 1324 RT5645_DMIC_SRC_SFT, rt5645_stereo_dmic_src); 1325 1326 static const struct snd_kcontrol_new rt5645_sto1_dmic_mux = 1327 SOC_DAPM_ENUM("Stereo1 DMIC source", rt5645_stereo1_dmic_enum); 1328 1329 /* Mono ADC source */ 1330 /* MX-28 [12] */ 1331 static const char * const rt5645_mono_adc_l1_src[] = { 1332 "Mono DAC MIXL", "ADC" 1333 }; 1334 1335 static SOC_ENUM_SINGLE_DECL( 1336 rt5645_mono_adc_l1_enum, RT5645_MONO_ADC_MIXER, 1337 RT5645_MONO_ADC_L1_SRC_SFT, rt5645_mono_adc_l1_src); 1338 1339 static const struct snd_kcontrol_new rt5645_mono_adc_l1_mux = 1340 SOC_DAPM_ENUM("Mono ADC1 left source", rt5645_mono_adc_l1_enum); 1341 /* MX-28 [11] */ 1342 static const char * const rt5645_mono_adc_l2_src[] = { 1343 "Mono DAC MIXL", "DMIC" 1344 }; 1345 1346 static SOC_ENUM_SINGLE_DECL( 1347 rt5645_mono_adc_l2_enum, RT5645_MONO_ADC_MIXER, 1348 RT5645_MONO_ADC_L2_SRC_SFT, rt5645_mono_adc_l2_src); 1349 1350 static const struct snd_kcontrol_new rt5645_mono_adc_l2_mux = 1351 SOC_DAPM_ENUM("Mono ADC2 left source", rt5645_mono_adc_l2_enum); 1352 1353 /* MX-28 [8] */ 1354 static const char * const rt5645_mono_dmic_src[] = { 1355 "DMIC1", "DMIC2" 1356 }; 1357 1358 static SOC_ENUM_SINGLE_DECL( 1359 rt5645_mono_dmic_l_enum, RT5645_MONO_ADC_MIXER, 1360 RT5645_MONO_DMIC_L_SRC_SFT, rt5645_mono_dmic_src); 1361 1362 static const struct snd_kcontrol_new rt5645_mono_dmic_l_mux = 1363 SOC_DAPM_ENUM("Mono DMIC left source", rt5645_mono_dmic_l_enum); 1364 /* MX-28 [1:0] */ 1365 static SOC_ENUM_SINGLE_DECL( 1366 rt5645_mono_dmic_r_enum, RT5645_MONO_ADC_MIXER, 1367 RT5645_MONO_DMIC_R_SRC_SFT, rt5645_mono_dmic_src); 1368 1369 static const struct snd_kcontrol_new rt5645_mono_dmic_r_mux = 1370 SOC_DAPM_ENUM("Mono DMIC Right source", rt5645_mono_dmic_r_enum); 1371 /* MX-28 [4] */ 1372 static const char * const rt5645_mono_adc_r1_src[] = { 1373 "Mono DAC MIXR", "ADC" 1374 }; 1375 1376 static SOC_ENUM_SINGLE_DECL( 1377 rt5645_mono_adc_r1_enum, RT5645_MONO_ADC_MIXER, 1378 RT5645_MONO_ADC_R1_SRC_SFT, rt5645_mono_adc_r1_src); 1379 1380 static const struct snd_kcontrol_new rt5645_mono_adc_r1_mux = 1381 SOC_DAPM_ENUM("Mono ADC1 right source", rt5645_mono_adc_r1_enum); 1382 /* MX-28 [3] */ 1383 static const char * const rt5645_mono_adc_r2_src[] = { 1384 "Mono DAC MIXR", "DMIC" 1385 }; 1386 1387 static SOC_ENUM_SINGLE_DECL( 1388 rt5645_mono_adc_r2_enum, RT5645_MONO_ADC_MIXER, 1389 RT5645_MONO_ADC_R2_SRC_SFT, rt5645_mono_adc_r2_src); 1390 1391 static const struct snd_kcontrol_new rt5645_mono_adc_r2_mux = 1392 SOC_DAPM_ENUM("Mono ADC2 right source", rt5645_mono_adc_r2_enum); 1393 1394 /* MX-77 [9:8] */ 1395 static const char * const rt5645_if1_adc_in_src[] = { 1396 "IF_ADC1/IF_ADC2/VAD_ADC", "IF_ADC2/IF_ADC1/VAD_ADC", 1397 "VAD_ADC/IF_ADC1/IF_ADC2", "VAD_ADC/IF_ADC2/IF_ADC1" 1398 }; 1399 1400 static SOC_ENUM_SINGLE_DECL( 1401 rt5645_if1_adc_in_enum, RT5645_TDM_CTRL_1, 1402 RT5645_IF1_ADC_IN_SFT, rt5645_if1_adc_in_src); 1403 1404 static const struct snd_kcontrol_new rt5645_if1_adc_in_mux = 1405 SOC_DAPM_ENUM("IF1 ADC IN source", rt5645_if1_adc_in_enum); 1406 1407 /* MX-78 [4:0] */ 1408 static const char * const rt5650_if1_adc_in_src[] = { 1409 "IF_ADC1/IF_ADC2/DAC_REF/Null", 1410 "IF_ADC1/IF_ADC2/Null/DAC_REF", 1411 "IF_ADC1/DAC_REF/IF_ADC2/Null", 1412 "IF_ADC1/DAC_REF/Null/IF_ADC2", 1413 "IF_ADC1/Null/DAC_REF/IF_ADC2", 1414 "IF_ADC1/Null/IF_ADC2/DAC_REF", 1415 1416 "IF_ADC2/IF_ADC1/DAC_REF/Null", 1417 "IF_ADC2/IF_ADC1/Null/DAC_REF", 1418 "IF_ADC2/DAC_REF/IF_ADC1/Null", 1419 "IF_ADC2/DAC_REF/Null/IF_ADC1", 1420 "IF_ADC2/Null/DAC_REF/IF_ADC1", 1421 "IF_ADC2/Null/IF_ADC1/DAC_REF", 1422 1423 "DAC_REF/IF_ADC1/IF_ADC2/Null", 1424 "DAC_REF/IF_ADC1/Null/IF_ADC2", 1425 "DAC_REF/IF_ADC2/IF_ADC1/Null", 1426 "DAC_REF/IF_ADC2/Null/IF_ADC1", 1427 "DAC_REF/Null/IF_ADC1/IF_ADC2", 1428 "DAC_REF/Null/IF_ADC2/IF_ADC1", 1429 1430 "Null/IF_ADC1/IF_ADC2/DAC_REF", 1431 "Null/IF_ADC1/DAC_REF/IF_ADC2", 1432 "Null/IF_ADC2/IF_ADC1/DAC_REF", 1433 "Null/IF_ADC2/DAC_REF/IF_ADC1", 1434 "Null/DAC_REF/IF_ADC1/IF_ADC2", 1435 "Null/DAC_REF/IF_ADC2/IF_ADC1", 1436 }; 1437 1438 static SOC_ENUM_SINGLE_DECL( 1439 rt5650_if1_adc_in_enum, RT5645_TDM_CTRL_2, 1440 0, rt5650_if1_adc_in_src); 1441 1442 static const struct snd_kcontrol_new rt5650_if1_adc_in_mux = 1443 SOC_DAPM_ENUM("IF1 ADC IN source", rt5650_if1_adc_in_enum); 1444 1445 /* MX-78 [15:14][13:12][11:10] */ 1446 static const char * const rt5645_tdm_adc_swap_select[] = { 1447 "L/R", "R/L", "L/L", "R/R" 1448 }; 1449 1450 static SOC_ENUM_SINGLE_DECL(rt5650_tdm_adc_slot0_1_enum, 1451 RT5645_TDM_CTRL_2, 14, rt5645_tdm_adc_swap_select); 1452 1453 static const struct snd_kcontrol_new rt5650_if1_adc1_in_mux = 1454 SOC_DAPM_ENUM("IF1 ADC1 IN source", rt5650_tdm_adc_slot0_1_enum); 1455 1456 static SOC_ENUM_SINGLE_DECL(rt5650_tdm_adc_slot2_3_enum, 1457 RT5645_TDM_CTRL_2, 12, rt5645_tdm_adc_swap_select); 1458 1459 static const struct snd_kcontrol_new rt5650_if1_adc2_in_mux = 1460 SOC_DAPM_ENUM("IF1 ADC2 IN source", rt5650_tdm_adc_slot2_3_enum); 1461 1462 static SOC_ENUM_SINGLE_DECL(rt5650_tdm_adc_slot4_5_enum, 1463 RT5645_TDM_CTRL_2, 10, rt5645_tdm_adc_swap_select); 1464 1465 static const struct snd_kcontrol_new rt5650_if1_adc3_in_mux = 1466 SOC_DAPM_ENUM("IF1 ADC3 IN source", rt5650_tdm_adc_slot4_5_enum); 1467 1468 /* MX-77 [7:6][5:4][3:2] */ 1469 static SOC_ENUM_SINGLE_DECL(rt5645_tdm_adc_slot0_1_enum, 1470 RT5645_TDM_CTRL_1, 6, rt5645_tdm_adc_swap_select); 1471 1472 static const struct snd_kcontrol_new rt5645_if1_adc1_in_mux = 1473 SOC_DAPM_ENUM("IF1 ADC1 IN source", rt5645_tdm_adc_slot0_1_enum); 1474 1475 static SOC_ENUM_SINGLE_DECL(rt5645_tdm_adc_slot2_3_enum, 1476 RT5645_TDM_CTRL_1, 4, rt5645_tdm_adc_swap_select); 1477 1478 static const struct snd_kcontrol_new rt5645_if1_adc2_in_mux = 1479 SOC_DAPM_ENUM("IF1 ADC2 IN source", rt5645_tdm_adc_slot2_3_enum); 1480 1481 static SOC_ENUM_SINGLE_DECL(rt5645_tdm_adc_slot4_5_enum, 1482 RT5645_TDM_CTRL_1, 2, rt5645_tdm_adc_swap_select); 1483 1484 static const struct snd_kcontrol_new rt5645_if1_adc3_in_mux = 1485 SOC_DAPM_ENUM("IF1 ADC3 IN source", rt5645_tdm_adc_slot4_5_enum); 1486 1487 /* MX-79 [14:12][10:8][6:4][2:0] */ 1488 static const char * const rt5645_tdm_dac_swap_select[] = { 1489 "Slot0", "Slot1", "Slot2", "Slot3" 1490 }; 1491 1492 static SOC_ENUM_SINGLE_DECL(rt5645_tdm_dac0_enum, 1493 RT5645_TDM_CTRL_3, 12, rt5645_tdm_dac_swap_select); 1494 1495 static const struct snd_kcontrol_new rt5645_if1_dac0_tdm_sel_mux = 1496 SOC_DAPM_ENUM("IF1 DAC0 source", rt5645_tdm_dac0_enum); 1497 1498 static SOC_ENUM_SINGLE_DECL(rt5645_tdm_dac1_enum, 1499 RT5645_TDM_CTRL_3, 8, rt5645_tdm_dac_swap_select); 1500 1501 static const struct snd_kcontrol_new rt5645_if1_dac1_tdm_sel_mux = 1502 SOC_DAPM_ENUM("IF1 DAC1 source", rt5645_tdm_dac1_enum); 1503 1504 static SOC_ENUM_SINGLE_DECL(rt5645_tdm_dac2_enum, 1505 RT5645_TDM_CTRL_3, 4, rt5645_tdm_dac_swap_select); 1506 1507 static const struct snd_kcontrol_new rt5645_if1_dac2_tdm_sel_mux = 1508 SOC_DAPM_ENUM("IF1 DAC2 source", rt5645_tdm_dac2_enum); 1509 1510 static SOC_ENUM_SINGLE_DECL(rt5645_tdm_dac3_enum, 1511 RT5645_TDM_CTRL_3, 0, rt5645_tdm_dac_swap_select); 1512 1513 static const struct snd_kcontrol_new rt5645_if1_dac3_tdm_sel_mux = 1514 SOC_DAPM_ENUM("IF1 DAC3 source", rt5645_tdm_dac3_enum); 1515 1516 /* MX-7a [14:12][10:8][6:4][2:0] */ 1517 static SOC_ENUM_SINGLE_DECL(rt5650_tdm_dac0_enum, 1518 RT5650_TDM_CTRL_4, 12, rt5645_tdm_dac_swap_select); 1519 1520 static const struct snd_kcontrol_new rt5650_if1_dac0_tdm_sel_mux = 1521 SOC_DAPM_ENUM("IF1 DAC0 source", rt5650_tdm_dac0_enum); 1522 1523 static SOC_ENUM_SINGLE_DECL(rt5650_tdm_dac1_enum, 1524 RT5650_TDM_CTRL_4, 8, rt5645_tdm_dac_swap_select); 1525 1526 static const struct snd_kcontrol_new rt5650_if1_dac1_tdm_sel_mux = 1527 SOC_DAPM_ENUM("IF1 DAC1 source", rt5650_tdm_dac1_enum); 1528 1529 static SOC_ENUM_SINGLE_DECL(rt5650_tdm_dac2_enum, 1530 RT5650_TDM_CTRL_4, 4, rt5645_tdm_dac_swap_select); 1531 1532 static const struct snd_kcontrol_new rt5650_if1_dac2_tdm_sel_mux = 1533 SOC_DAPM_ENUM("IF1 DAC2 source", rt5650_tdm_dac2_enum); 1534 1535 static SOC_ENUM_SINGLE_DECL(rt5650_tdm_dac3_enum, 1536 RT5650_TDM_CTRL_4, 0, rt5645_tdm_dac_swap_select); 1537 1538 static const struct snd_kcontrol_new rt5650_if1_dac3_tdm_sel_mux = 1539 SOC_DAPM_ENUM("IF1 DAC3 source", rt5650_tdm_dac3_enum); 1540 1541 /* MX-2d [3] [2] */ 1542 static const char * const rt5650_a_dac1_src[] = { 1543 "DAC1", "Stereo DAC Mixer" 1544 }; 1545 1546 static SOC_ENUM_SINGLE_DECL( 1547 rt5650_a_dac1_l_enum, RT5650_A_DAC_SOUR, 1548 RT5650_A_DAC1_L_IN_SFT, rt5650_a_dac1_src); 1549 1550 static const struct snd_kcontrol_new rt5650_a_dac1_l_mux = 1551 SOC_DAPM_ENUM("A DAC1 L source", rt5650_a_dac1_l_enum); 1552 1553 static SOC_ENUM_SINGLE_DECL( 1554 rt5650_a_dac1_r_enum, RT5650_A_DAC_SOUR, 1555 RT5650_A_DAC1_R_IN_SFT, rt5650_a_dac1_src); 1556 1557 static const struct snd_kcontrol_new rt5650_a_dac1_r_mux = 1558 SOC_DAPM_ENUM("A DAC1 R source", rt5650_a_dac1_r_enum); 1559 1560 /* MX-2d [1] [0] */ 1561 static const char * const rt5650_a_dac2_src[] = { 1562 "Stereo DAC Mixer", "Mono DAC Mixer" 1563 }; 1564 1565 static SOC_ENUM_SINGLE_DECL( 1566 rt5650_a_dac2_l_enum, RT5650_A_DAC_SOUR, 1567 RT5650_A_DAC2_L_IN_SFT, rt5650_a_dac2_src); 1568 1569 static const struct snd_kcontrol_new rt5650_a_dac2_l_mux = 1570 SOC_DAPM_ENUM("A DAC2 L source", rt5650_a_dac2_l_enum); 1571 1572 static SOC_ENUM_SINGLE_DECL( 1573 rt5650_a_dac2_r_enum, RT5650_A_DAC_SOUR, 1574 RT5650_A_DAC2_R_IN_SFT, rt5650_a_dac2_src); 1575 1576 static const struct snd_kcontrol_new rt5650_a_dac2_r_mux = 1577 SOC_DAPM_ENUM("A DAC2 R source", rt5650_a_dac2_r_enum); 1578 1579 /* MX-2F [13:12] */ 1580 static const char * const rt5645_if2_adc_in_src[] = { 1581 "IF_ADC1", "IF_ADC2", "VAD_ADC" 1582 }; 1583 1584 static SOC_ENUM_SINGLE_DECL( 1585 rt5645_if2_adc_in_enum, RT5645_DIG_INF1_DATA, 1586 RT5645_IF2_ADC_IN_SFT, rt5645_if2_adc_in_src); 1587 1588 static const struct snd_kcontrol_new rt5645_if2_adc_in_mux = 1589 SOC_DAPM_ENUM("IF2 ADC IN source", rt5645_if2_adc_in_enum); 1590 1591 /* MX-31 [15] [13] [11] [9] */ 1592 static const char * const rt5645_pdm_src[] = { 1593 "Mono DAC", "Stereo DAC" 1594 }; 1595 1596 static SOC_ENUM_SINGLE_DECL( 1597 rt5645_pdm1_l_enum, RT5645_PDM_OUT_CTRL, 1598 RT5645_PDM1_L_SFT, rt5645_pdm_src); 1599 1600 static const struct snd_kcontrol_new rt5645_pdm1_l_mux = 1601 SOC_DAPM_ENUM("PDM1 L source", rt5645_pdm1_l_enum); 1602 1603 static SOC_ENUM_SINGLE_DECL( 1604 rt5645_pdm1_r_enum, RT5645_PDM_OUT_CTRL, 1605 RT5645_PDM1_R_SFT, rt5645_pdm_src); 1606 1607 static const struct snd_kcontrol_new rt5645_pdm1_r_mux = 1608 SOC_DAPM_ENUM("PDM1 R source", rt5645_pdm1_r_enum); 1609 1610 /* MX-9D [9:8] */ 1611 static const char * const rt5645_vad_adc_src[] = { 1612 "Sto1 ADC L", "Mono ADC L", "Mono ADC R" 1613 }; 1614 1615 static SOC_ENUM_SINGLE_DECL( 1616 rt5645_vad_adc_enum, RT5645_VAD_CTRL4, 1617 RT5645_VAD_SEL_SFT, rt5645_vad_adc_src); 1618 1619 static const struct snd_kcontrol_new rt5645_vad_adc_mux = 1620 SOC_DAPM_ENUM("VAD ADC source", rt5645_vad_adc_enum); 1621 1622 static const struct snd_kcontrol_new spk_l_vol_control = 1623 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_SPK_VOL, 1624 RT5645_L_MUTE_SFT, 1, 1); 1625 1626 static const struct snd_kcontrol_new spk_r_vol_control = 1627 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_SPK_VOL, 1628 RT5645_R_MUTE_SFT, 1, 1); 1629 1630 static const struct snd_kcontrol_new hp_l_vol_control = 1631 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_HP_VOL, 1632 RT5645_L_MUTE_SFT, 1, 1); 1633 1634 static const struct snd_kcontrol_new hp_r_vol_control = 1635 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_HP_VOL, 1636 RT5645_R_MUTE_SFT, 1, 1); 1637 1638 static const struct snd_kcontrol_new pdm1_l_vol_control = 1639 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_PDM_OUT_CTRL, 1640 RT5645_M_PDM1_L, 1, 1); 1641 1642 static const struct snd_kcontrol_new pdm1_r_vol_control = 1643 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_PDM_OUT_CTRL, 1644 RT5645_M_PDM1_R, 1, 1); 1645 1646 static void hp_amp_power(struct snd_soc_component *component, int on) 1647 { 1648 static int hp_amp_power_count; 1649 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component); 1650 int i, val; 1651 1652 if (on) { 1653 if (hp_amp_power_count <= 0) { 1654 if (rt5645->codec_type == CODEC_TYPE_RT5650) { 1655 snd_soc_component_write(component, RT5645_DEPOP_M2, 0x3100); 1656 snd_soc_component_write(component, RT5645_CHARGE_PUMP, 1657 0x0e06); 1658 snd_soc_component_write(component, RT5645_DEPOP_M1, 0x000d); 1659 regmap_write(rt5645->regmap, RT5645_PR_BASE + 1660 RT5645_HP_DCC_INT1, 0x9f01); 1661 for (i = 0; i < 20; i++) { 1662 usleep_range(1000, 1500); 1663 regmap_read(rt5645->regmap, RT5645_PR_BASE + 1664 RT5645_HP_DCC_INT1, &val); 1665 if (!(val & 0x8000)) 1666 break; 1667 } 1668 snd_soc_component_update_bits(component, RT5645_DEPOP_M1, 1669 RT5645_HP_CO_MASK, RT5645_HP_CO_EN); 1670 regmap_write(rt5645->regmap, RT5645_PR_BASE + 1671 0x3e, 0x7400); 1672 snd_soc_component_write(component, RT5645_DEPOP_M3, 0x0737); 1673 regmap_write(rt5645->regmap, RT5645_PR_BASE + 1674 RT5645_MAMP_INT_REG2, 0xfc00); 1675 snd_soc_component_write(component, RT5645_DEPOP_M2, 0x1140); 1676 msleep(90); 1677 } else { 1678 /* depop parameters */ 1679 snd_soc_component_update_bits(component, RT5645_DEPOP_M2, 1680 RT5645_DEPOP_MASK, RT5645_DEPOP_MAN); 1681 snd_soc_component_write(component, RT5645_DEPOP_M1, 0x000d); 1682 regmap_write(rt5645->regmap, RT5645_PR_BASE + 1683 RT5645_HP_DCC_INT1, 0x9f01); 1684 mdelay(150); 1685 /* headphone amp power on */ 1686 snd_soc_component_update_bits(component, RT5645_PWR_ANLG1, 1687 RT5645_PWR_FV1 | RT5645_PWR_FV2, 0); 1688 snd_soc_component_update_bits(component, RT5645_PWR_VOL, 1689 RT5645_PWR_HV_L | RT5645_PWR_HV_R, 1690 RT5645_PWR_HV_L | RT5645_PWR_HV_R); 1691 snd_soc_component_update_bits(component, RT5645_PWR_ANLG1, 1692 RT5645_PWR_HP_L | RT5645_PWR_HP_R | 1693 RT5645_PWR_HA, 1694 RT5645_PWR_HP_L | RT5645_PWR_HP_R | 1695 RT5645_PWR_HA); 1696 mdelay(5); 1697 snd_soc_component_update_bits(component, RT5645_PWR_ANLG1, 1698 RT5645_PWR_FV1 | RT5645_PWR_FV2, 1699 RT5645_PWR_FV1 | RT5645_PWR_FV2); 1700 1701 snd_soc_component_update_bits(component, RT5645_DEPOP_M1, 1702 RT5645_HP_CO_MASK | RT5645_HP_SG_MASK, 1703 RT5645_HP_CO_EN | RT5645_HP_SG_EN); 1704 regmap_write(rt5645->regmap, RT5645_PR_BASE + 1705 0x14, 0x1aaa); 1706 regmap_write(rt5645->regmap, RT5645_PR_BASE + 1707 0x24, 0x0430); 1708 } 1709 } 1710 hp_amp_power_count++; 1711 } else { 1712 hp_amp_power_count--; 1713 if (hp_amp_power_count <= 0) { 1714 if (rt5645->codec_type == CODEC_TYPE_RT5650) { 1715 regmap_write(rt5645->regmap, RT5645_PR_BASE + 1716 0x3e, 0x7400); 1717 snd_soc_component_write(component, RT5645_DEPOP_M3, 0x0737); 1718 regmap_write(rt5645->regmap, RT5645_PR_BASE + 1719 RT5645_MAMP_INT_REG2, 0xfc00); 1720 snd_soc_component_write(component, RT5645_DEPOP_M2, 0x1140); 1721 msleep(100); 1722 snd_soc_component_write(component, RT5645_DEPOP_M1, 0x0001); 1723 1724 } else { 1725 snd_soc_component_update_bits(component, RT5645_DEPOP_M1, 1726 RT5645_HP_SG_MASK | 1727 RT5645_HP_L_SMT_MASK | 1728 RT5645_HP_R_SMT_MASK, 1729 RT5645_HP_SG_DIS | 1730 RT5645_HP_L_SMT_DIS | 1731 RT5645_HP_R_SMT_DIS); 1732 /* headphone amp power down */ 1733 snd_soc_component_write(component, RT5645_DEPOP_M1, 0x0000); 1734 snd_soc_component_update_bits(component, RT5645_PWR_ANLG1, 1735 RT5645_PWR_HP_L | RT5645_PWR_HP_R | 1736 RT5645_PWR_HA, 0); 1737 snd_soc_component_update_bits(component, RT5645_DEPOP_M2, 1738 RT5645_DEPOP_MASK, 0); 1739 } 1740 } 1741 } 1742 } 1743 1744 static int rt5645_hp_event(struct snd_soc_dapm_widget *w, 1745 struct snd_kcontrol *kcontrol, int event) 1746 { 1747 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1748 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component); 1749 1750 switch (event) { 1751 case SND_SOC_DAPM_POST_PMU: 1752 hp_amp_power(component, 1); 1753 /* headphone unmute sequence */ 1754 if (rt5645->codec_type == CODEC_TYPE_RT5645) { 1755 snd_soc_component_update_bits(component, RT5645_DEPOP_M3, 1756 RT5645_CP_FQ1_MASK | RT5645_CP_FQ2_MASK | 1757 RT5645_CP_FQ3_MASK, 1758 (RT5645_CP_FQ_192_KHZ << RT5645_CP_FQ1_SFT) | 1759 (RT5645_CP_FQ_12_KHZ << RT5645_CP_FQ2_SFT) | 1760 (RT5645_CP_FQ_192_KHZ << RT5645_CP_FQ3_SFT)); 1761 regmap_write(rt5645->regmap, RT5645_PR_BASE + 1762 RT5645_MAMP_INT_REG2, 0xfc00); 1763 snd_soc_component_update_bits(component, RT5645_DEPOP_M1, 1764 RT5645_SMT_TRIG_MASK, RT5645_SMT_TRIG_EN); 1765 snd_soc_component_update_bits(component, RT5645_DEPOP_M1, 1766 RT5645_RSTN_MASK, RT5645_RSTN_EN); 1767 snd_soc_component_update_bits(component, RT5645_DEPOP_M1, 1768 RT5645_RSTN_MASK | RT5645_HP_L_SMT_MASK | 1769 RT5645_HP_R_SMT_MASK, RT5645_RSTN_DIS | 1770 RT5645_HP_L_SMT_EN | RT5645_HP_R_SMT_EN); 1771 msleep(40); 1772 snd_soc_component_update_bits(component, RT5645_DEPOP_M1, 1773 RT5645_HP_SG_MASK | RT5645_HP_L_SMT_MASK | 1774 RT5645_HP_R_SMT_MASK, RT5645_HP_SG_DIS | 1775 RT5645_HP_L_SMT_DIS | RT5645_HP_R_SMT_DIS); 1776 } 1777 break; 1778 1779 case SND_SOC_DAPM_PRE_PMD: 1780 /* headphone mute sequence */ 1781 if (rt5645->codec_type == CODEC_TYPE_RT5645) { 1782 snd_soc_component_update_bits(component, RT5645_DEPOP_M3, 1783 RT5645_CP_FQ1_MASK | RT5645_CP_FQ2_MASK | 1784 RT5645_CP_FQ3_MASK, 1785 (RT5645_CP_FQ_96_KHZ << RT5645_CP_FQ1_SFT) | 1786 (RT5645_CP_FQ_12_KHZ << RT5645_CP_FQ2_SFT) | 1787 (RT5645_CP_FQ_96_KHZ << RT5645_CP_FQ3_SFT)); 1788 regmap_write(rt5645->regmap, RT5645_PR_BASE + 1789 RT5645_MAMP_INT_REG2, 0xfc00); 1790 snd_soc_component_update_bits(component, RT5645_DEPOP_M1, 1791 RT5645_HP_SG_MASK, RT5645_HP_SG_EN); 1792 snd_soc_component_update_bits(component, RT5645_DEPOP_M1, 1793 RT5645_RSTP_MASK, RT5645_RSTP_EN); 1794 snd_soc_component_update_bits(component, RT5645_DEPOP_M1, 1795 RT5645_RSTP_MASK | RT5645_HP_L_SMT_MASK | 1796 RT5645_HP_R_SMT_MASK, RT5645_RSTP_DIS | 1797 RT5645_HP_L_SMT_EN | RT5645_HP_R_SMT_EN); 1798 msleep(30); 1799 } 1800 hp_amp_power(component, 0); 1801 break; 1802 1803 default: 1804 return 0; 1805 } 1806 1807 return 0; 1808 } 1809 1810 static int rt5645_spk_event(struct snd_soc_dapm_widget *w, 1811 struct snd_kcontrol *kcontrol, int event) 1812 { 1813 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1814 1815 switch (event) { 1816 case SND_SOC_DAPM_POST_PMU: 1817 rt5645_enable_hweq(component); 1818 snd_soc_component_update_bits(component, RT5645_PWR_DIG1, 1819 RT5645_PWR_CLS_D | RT5645_PWR_CLS_D_R | 1820 RT5645_PWR_CLS_D_L, 1821 RT5645_PWR_CLS_D | RT5645_PWR_CLS_D_R | 1822 RT5645_PWR_CLS_D_L); 1823 snd_soc_component_update_bits(component, RT5645_GEN_CTRL3, 1824 RT5645_DET_CLK_MASK, RT5645_DET_CLK_MODE1); 1825 break; 1826 1827 case SND_SOC_DAPM_PRE_PMD: 1828 snd_soc_component_update_bits(component, RT5645_GEN_CTRL3, 1829 RT5645_DET_CLK_MASK, RT5645_DET_CLK_DIS); 1830 snd_soc_component_write(component, RT5645_EQ_CTRL2, 0); 1831 snd_soc_component_update_bits(component, RT5645_PWR_DIG1, 1832 RT5645_PWR_CLS_D | RT5645_PWR_CLS_D_R | 1833 RT5645_PWR_CLS_D_L, 0); 1834 break; 1835 1836 default: 1837 return 0; 1838 } 1839 1840 return 0; 1841 } 1842 1843 static int rt5645_lout_event(struct snd_soc_dapm_widget *w, 1844 struct snd_kcontrol *kcontrol, int event) 1845 { 1846 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1847 1848 switch (event) { 1849 case SND_SOC_DAPM_POST_PMU: 1850 hp_amp_power(component, 1); 1851 snd_soc_component_update_bits(component, RT5645_PWR_ANLG1, 1852 RT5645_PWR_LM, RT5645_PWR_LM); 1853 snd_soc_component_update_bits(component, RT5645_LOUT1, 1854 RT5645_L_MUTE | RT5645_R_MUTE, 0); 1855 break; 1856 1857 case SND_SOC_DAPM_PRE_PMD: 1858 snd_soc_component_update_bits(component, RT5645_LOUT1, 1859 RT5645_L_MUTE | RT5645_R_MUTE, 1860 RT5645_L_MUTE | RT5645_R_MUTE); 1861 snd_soc_component_update_bits(component, RT5645_PWR_ANLG1, 1862 RT5645_PWR_LM, 0); 1863 hp_amp_power(component, 0); 1864 break; 1865 1866 default: 1867 return 0; 1868 } 1869 1870 return 0; 1871 } 1872 1873 static int rt5645_bst2_event(struct snd_soc_dapm_widget *w, 1874 struct snd_kcontrol *kcontrol, int event) 1875 { 1876 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1877 1878 switch (event) { 1879 case SND_SOC_DAPM_POST_PMU: 1880 snd_soc_component_update_bits(component, RT5645_PWR_ANLG2, 1881 RT5645_PWR_BST2_P, RT5645_PWR_BST2_P); 1882 break; 1883 1884 case SND_SOC_DAPM_PRE_PMD: 1885 snd_soc_component_update_bits(component, RT5645_PWR_ANLG2, 1886 RT5645_PWR_BST2_P, 0); 1887 break; 1888 1889 default: 1890 return 0; 1891 } 1892 1893 return 0; 1894 } 1895 1896 static int rt5645_set_micbias1_event(struct snd_soc_dapm_widget *w, 1897 struct snd_kcontrol *k, int event) 1898 { 1899 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1900 1901 switch (event) { 1902 case SND_SOC_DAPM_PRE_PMU: 1903 snd_soc_component_update_bits(component, RT5645_GEN_CTRL2, 1904 RT5645_MICBIAS1_POW_CTRL_SEL_MASK, 1905 RT5645_MICBIAS1_POW_CTRL_SEL_M); 1906 break; 1907 1908 case SND_SOC_DAPM_POST_PMD: 1909 snd_soc_component_update_bits(component, RT5645_GEN_CTRL2, 1910 RT5645_MICBIAS1_POW_CTRL_SEL_MASK, 1911 RT5645_MICBIAS1_POW_CTRL_SEL_A); 1912 break; 1913 1914 default: 1915 return 0; 1916 } 1917 1918 return 0; 1919 } 1920 1921 static int rt5645_set_micbias2_event(struct snd_soc_dapm_widget *w, 1922 struct snd_kcontrol *k, int event) 1923 { 1924 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1925 1926 switch (event) { 1927 case SND_SOC_DAPM_PRE_PMU: 1928 snd_soc_component_update_bits(component, RT5645_GEN_CTRL2, 1929 RT5645_MICBIAS2_POW_CTRL_SEL_MASK, 1930 RT5645_MICBIAS2_POW_CTRL_SEL_M); 1931 break; 1932 1933 case SND_SOC_DAPM_POST_PMD: 1934 snd_soc_component_update_bits(component, RT5645_GEN_CTRL2, 1935 RT5645_MICBIAS2_POW_CTRL_SEL_MASK, 1936 RT5645_MICBIAS2_POW_CTRL_SEL_A); 1937 break; 1938 1939 default: 1940 return 0; 1941 } 1942 1943 return 0; 1944 } 1945 1946 static const struct snd_soc_dapm_widget rt5645_dapm_widgets[] = { 1947 SND_SOC_DAPM_SUPPLY("LDO2", RT5645_PWR_MIXER, 1948 RT5645_PWR_LDO2_BIT, 0, NULL, 0), 1949 SND_SOC_DAPM_SUPPLY("PLL1", RT5645_PWR_ANLG2, 1950 RT5645_PWR_PLL_BIT, 0, NULL, 0), 1951 1952 SND_SOC_DAPM_SUPPLY("JD Power", RT5645_PWR_ANLG2, 1953 RT5645_PWR_JD1_BIT, 0, NULL, 0), 1954 SND_SOC_DAPM_SUPPLY("Mic Det Power", RT5645_PWR_VOL, 1955 RT5645_PWR_MIC_DET_BIT, 0, NULL, 0), 1956 1957 /* ASRC */ 1958 SND_SOC_DAPM_SUPPLY_S("I2S1 ASRC", 1, RT5645_ASRC_1, 1959 11, 0, NULL, 0), 1960 SND_SOC_DAPM_SUPPLY_S("I2S2 ASRC", 1, RT5645_ASRC_1, 1961 12, 0, NULL, 0), 1962 SND_SOC_DAPM_SUPPLY_S("DAC STO ASRC", 1, RT5645_ASRC_1, 1963 10, 0, NULL, 0), 1964 SND_SOC_DAPM_SUPPLY_S("DAC MONO L ASRC", 1, RT5645_ASRC_1, 1965 9, 0, NULL, 0), 1966 SND_SOC_DAPM_SUPPLY_S("DAC MONO R ASRC", 1, RT5645_ASRC_1, 1967 8, 0, NULL, 0), 1968 SND_SOC_DAPM_SUPPLY_S("DMIC STO1 ASRC", 1, RT5645_ASRC_1, 1969 7, 0, NULL, 0), 1970 SND_SOC_DAPM_SUPPLY_S("DMIC MONO L ASRC", 1, RT5645_ASRC_1, 1971 5, 0, NULL, 0), 1972 SND_SOC_DAPM_SUPPLY_S("DMIC MONO R ASRC", 1, RT5645_ASRC_1, 1973 4, 0, NULL, 0), 1974 SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5645_ASRC_1, 1975 3, 0, NULL, 0), 1976 SND_SOC_DAPM_SUPPLY_S("ADC MONO L ASRC", 1, RT5645_ASRC_1, 1977 1, 0, NULL, 0), 1978 SND_SOC_DAPM_SUPPLY_S("ADC MONO R ASRC", 1, RT5645_ASRC_1, 1979 0, 0, NULL, 0), 1980 1981 /* Input Side */ 1982 /* micbias */ 1983 SND_SOC_DAPM_SUPPLY("micbias1", RT5645_PWR_ANLG2, 1984 RT5645_PWR_MB1_BIT, 0, rt5645_set_micbias1_event, 1985 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 1986 SND_SOC_DAPM_SUPPLY("micbias2", RT5645_PWR_ANLG2, 1987 RT5645_PWR_MB2_BIT, 0, rt5645_set_micbias2_event, 1988 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 1989 /* Input Lines */ 1990 SND_SOC_DAPM_INPUT("DMIC L1"), 1991 SND_SOC_DAPM_INPUT("DMIC R1"), 1992 SND_SOC_DAPM_INPUT("DMIC L2"), 1993 SND_SOC_DAPM_INPUT("DMIC R2"), 1994 1995 SND_SOC_DAPM_INPUT("IN1P"), 1996 SND_SOC_DAPM_INPUT("IN1N"), 1997 SND_SOC_DAPM_INPUT("IN2P"), 1998 SND_SOC_DAPM_INPUT("IN2N"), 1999 2000 SND_SOC_DAPM_INPUT("Haptic Generator"), 2001 2002 SND_SOC_DAPM_PGA("DMIC1", SND_SOC_NOPM, 0, 0, NULL, 0), 2003 SND_SOC_DAPM_PGA("DMIC2", SND_SOC_NOPM, 0, 0, NULL, 0), 2004 SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0, 2005 set_dmic_clk, SND_SOC_DAPM_PRE_PMU), 2006 SND_SOC_DAPM_SUPPLY("DMIC1 Power", RT5645_DMIC_CTRL1, 2007 RT5645_DMIC_1_EN_SFT, 0, NULL, 0), 2008 SND_SOC_DAPM_SUPPLY("DMIC2 Power", RT5645_DMIC_CTRL1, 2009 RT5645_DMIC_2_EN_SFT, 0, NULL, 0), 2010 /* Boost */ 2011 SND_SOC_DAPM_PGA("BST1", RT5645_PWR_ANLG2, 2012 RT5645_PWR_BST1_BIT, 0, NULL, 0), 2013 SND_SOC_DAPM_PGA_E("BST2", RT5645_PWR_ANLG2, 2014 RT5645_PWR_BST2_BIT, 0, NULL, 0, rt5645_bst2_event, 2015 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU), 2016 /* Input Volume */ 2017 SND_SOC_DAPM_PGA("INL VOL", RT5645_PWR_VOL, 2018 RT5645_PWR_IN_L_BIT, 0, NULL, 0), 2019 SND_SOC_DAPM_PGA("INR VOL", RT5645_PWR_VOL, 2020 RT5645_PWR_IN_R_BIT, 0, NULL, 0), 2021 /* REC Mixer */ 2022 SND_SOC_DAPM_MIXER("RECMIXL", RT5645_PWR_MIXER, RT5645_PWR_RM_L_BIT, 2023 0, rt5645_rec_l_mix, ARRAY_SIZE(rt5645_rec_l_mix)), 2024 SND_SOC_DAPM_MIXER("RECMIXR", RT5645_PWR_MIXER, RT5645_PWR_RM_R_BIT, 2025 0, rt5645_rec_r_mix, ARRAY_SIZE(rt5645_rec_r_mix)), 2026 /* ADCs */ 2027 SND_SOC_DAPM_ADC("ADC L", NULL, SND_SOC_NOPM, 0, 0), 2028 SND_SOC_DAPM_ADC("ADC R", NULL, SND_SOC_NOPM, 0, 0), 2029 2030 SND_SOC_DAPM_SUPPLY("ADC L power", RT5645_PWR_DIG1, 2031 RT5645_PWR_ADC_L_BIT, 0, NULL, 0), 2032 SND_SOC_DAPM_SUPPLY("ADC R power", RT5645_PWR_DIG1, 2033 RT5645_PWR_ADC_R_BIT, 0, NULL, 0), 2034 2035 /* ADC Mux */ 2036 SND_SOC_DAPM_MUX("Stereo1 DMIC Mux", SND_SOC_NOPM, 0, 0, 2037 &rt5645_sto1_dmic_mux), 2038 SND_SOC_DAPM_MUX("Stereo1 ADC L2 Mux", SND_SOC_NOPM, 0, 0, 2039 &rt5645_sto_adc2_mux), 2040 SND_SOC_DAPM_MUX("Stereo1 ADC R2 Mux", SND_SOC_NOPM, 0, 0, 2041 &rt5645_sto_adc2_mux), 2042 SND_SOC_DAPM_MUX("Stereo1 ADC L1 Mux", SND_SOC_NOPM, 0, 0, 2043 &rt5645_sto_adc1_mux), 2044 SND_SOC_DAPM_MUX("Stereo1 ADC R1 Mux", SND_SOC_NOPM, 0, 0, 2045 &rt5645_sto_adc1_mux), 2046 SND_SOC_DAPM_MUX("Mono DMIC L Mux", SND_SOC_NOPM, 0, 0, 2047 &rt5645_mono_dmic_l_mux), 2048 SND_SOC_DAPM_MUX("Mono DMIC R Mux", SND_SOC_NOPM, 0, 0, 2049 &rt5645_mono_dmic_r_mux), 2050 SND_SOC_DAPM_MUX("Mono ADC L2 Mux", SND_SOC_NOPM, 0, 0, 2051 &rt5645_mono_adc_l2_mux), 2052 SND_SOC_DAPM_MUX("Mono ADC L1 Mux", SND_SOC_NOPM, 0, 0, 2053 &rt5645_mono_adc_l1_mux), 2054 SND_SOC_DAPM_MUX("Mono ADC R1 Mux", SND_SOC_NOPM, 0, 0, 2055 &rt5645_mono_adc_r1_mux), 2056 SND_SOC_DAPM_MUX("Mono ADC R2 Mux", SND_SOC_NOPM, 0, 0, 2057 &rt5645_mono_adc_r2_mux), 2058 /* ADC Mixer */ 2059 2060 SND_SOC_DAPM_SUPPLY_S("adc stereo1 filter", 1, RT5645_PWR_DIG2, 2061 RT5645_PWR_ADC_S1F_BIT, 0, NULL, 0), 2062 SND_SOC_DAPM_MIXER_E("Sto1 ADC MIXL", SND_SOC_NOPM, 0, 0, 2063 rt5645_sto1_adc_l_mix, ARRAY_SIZE(rt5645_sto1_adc_l_mix), 2064 NULL, 0), 2065 SND_SOC_DAPM_MIXER_E("Sto1 ADC MIXR", SND_SOC_NOPM, 0, 0, 2066 rt5645_sto1_adc_r_mix, ARRAY_SIZE(rt5645_sto1_adc_r_mix), 2067 NULL, 0), 2068 SND_SOC_DAPM_SUPPLY_S("adc mono left filter", 1, RT5645_PWR_DIG2, 2069 RT5645_PWR_ADC_MF_L_BIT, 0, NULL, 0), 2070 SND_SOC_DAPM_MIXER_E("Mono ADC MIXL", SND_SOC_NOPM, 0, 0, 2071 rt5645_mono_adc_l_mix, ARRAY_SIZE(rt5645_mono_adc_l_mix), 2072 NULL, 0), 2073 SND_SOC_DAPM_SUPPLY_S("adc mono right filter", 1, RT5645_PWR_DIG2, 2074 RT5645_PWR_ADC_MF_R_BIT, 0, NULL, 0), 2075 SND_SOC_DAPM_MIXER_E("Mono ADC MIXR", SND_SOC_NOPM, 0, 0, 2076 rt5645_mono_adc_r_mix, ARRAY_SIZE(rt5645_mono_adc_r_mix), 2077 NULL, 0), 2078 2079 /* ADC PGA */ 2080 SND_SOC_DAPM_PGA("Stereo1 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0), 2081 SND_SOC_DAPM_PGA("Stereo1 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0), 2082 SND_SOC_DAPM_PGA("Sto2 ADC LR MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 2083 SND_SOC_DAPM_PGA("VAD_ADC", SND_SOC_NOPM, 0, 0, NULL, 0), 2084 SND_SOC_DAPM_PGA("IF_ADC1", SND_SOC_NOPM, 0, 0, NULL, 0), 2085 SND_SOC_DAPM_PGA("IF_ADC2", SND_SOC_NOPM, 0, 0, NULL, 0), 2086 SND_SOC_DAPM_PGA("IF1_ADC1", SND_SOC_NOPM, 0, 0, NULL, 0), 2087 SND_SOC_DAPM_PGA("IF1_ADC2", SND_SOC_NOPM, 0, 0, NULL, 0), 2088 SND_SOC_DAPM_PGA("IF1_ADC3", SND_SOC_NOPM, 0, 0, NULL, 0), 2089 SND_SOC_DAPM_PGA("IF1_ADC4", SND_SOC_NOPM, 0, 0, NULL, 0), 2090 2091 /* IF1 2 Mux */ 2092 SND_SOC_DAPM_MUX("IF2 ADC Mux", SND_SOC_NOPM, 2093 0, 0, &rt5645_if2_adc_in_mux), 2094 2095 /* Digital Interface */ 2096 SND_SOC_DAPM_SUPPLY("I2S1", RT5645_PWR_DIG1, 2097 RT5645_PWR_I2S1_BIT, 0, NULL, 0), 2098 SND_SOC_DAPM_PGA("IF1 DAC0", SND_SOC_NOPM, 0, 0, NULL, 0), 2099 SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0), 2100 SND_SOC_DAPM_PGA("IF1 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0), 2101 SND_SOC_DAPM_PGA("IF1 DAC3", SND_SOC_NOPM, 0, 0, NULL, 0), 2102 SND_SOC_DAPM_PGA("IF1 ADC", SND_SOC_NOPM, 0, 0, NULL, 0), 2103 SND_SOC_DAPM_PGA("IF1 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0), 2104 SND_SOC_DAPM_PGA("IF1 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0), 2105 SND_SOC_DAPM_SUPPLY("I2S2", RT5645_PWR_DIG1, 2106 RT5645_PWR_I2S2_BIT, 0, NULL, 0), 2107 SND_SOC_DAPM_PGA("IF2 DAC", SND_SOC_NOPM, 0, 0, NULL, 0), 2108 SND_SOC_DAPM_PGA("IF2 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0), 2109 SND_SOC_DAPM_PGA("IF2 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0), 2110 SND_SOC_DAPM_PGA("IF2 ADC", SND_SOC_NOPM, 0, 0, NULL, 0), 2111 2112 /* Digital Interface Select */ 2113 SND_SOC_DAPM_MUX("VAD ADC Mux", SND_SOC_NOPM, 2114 0, 0, &rt5645_vad_adc_mux), 2115 2116 /* Audio Interface */ 2117 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0), 2118 SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0), 2119 SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0), 2120 SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0), 2121 2122 /* Output Side */ 2123 /* DAC mixer before sound effect */ 2124 SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0, 2125 rt5645_dac_l_mix, ARRAY_SIZE(rt5645_dac_l_mix)), 2126 SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0, 2127 rt5645_dac_r_mix, ARRAY_SIZE(rt5645_dac_r_mix)), 2128 2129 /* DAC2 channel Mux */ 2130 SND_SOC_DAPM_MUX("DAC L2 Mux", SND_SOC_NOPM, 0, 0, &rt5645_dac_l2_mux), 2131 SND_SOC_DAPM_MUX("DAC R2 Mux", SND_SOC_NOPM, 0, 0, &rt5645_dac_r2_mux), 2132 SND_SOC_DAPM_PGA("DAC L2 Volume", RT5645_PWR_DIG1, 2133 RT5645_PWR_DAC_L2_BIT, 0, NULL, 0), 2134 SND_SOC_DAPM_PGA("DAC R2 Volume", RT5645_PWR_DIG1, 2135 RT5645_PWR_DAC_R2_BIT, 0, NULL, 0), 2136 2137 SND_SOC_DAPM_MUX("DAC1 L Mux", SND_SOC_NOPM, 0, 0, &rt5645_dac1l_mux), 2138 SND_SOC_DAPM_MUX("DAC1 R Mux", SND_SOC_NOPM, 0, 0, &rt5645_dac1r_mux), 2139 2140 /* DAC Mixer */ 2141 SND_SOC_DAPM_SUPPLY_S("dac stereo1 filter", 1, RT5645_PWR_DIG2, 2142 RT5645_PWR_DAC_S1F_BIT, 0, NULL, 0), 2143 SND_SOC_DAPM_SUPPLY_S("dac mono left filter", 1, RT5645_PWR_DIG2, 2144 RT5645_PWR_DAC_MF_L_BIT, 0, NULL, 0), 2145 SND_SOC_DAPM_SUPPLY_S("dac mono right filter", 1, RT5645_PWR_DIG2, 2146 RT5645_PWR_DAC_MF_R_BIT, 0, NULL, 0), 2147 SND_SOC_DAPM_MIXER("Stereo DAC MIXL", SND_SOC_NOPM, 0, 0, 2148 rt5645_sto_dac_l_mix, ARRAY_SIZE(rt5645_sto_dac_l_mix)), 2149 SND_SOC_DAPM_MIXER("Stereo DAC MIXR", SND_SOC_NOPM, 0, 0, 2150 rt5645_sto_dac_r_mix, ARRAY_SIZE(rt5645_sto_dac_r_mix)), 2151 SND_SOC_DAPM_MIXER("Mono DAC MIXL", SND_SOC_NOPM, 0, 0, 2152 rt5645_mono_dac_l_mix, ARRAY_SIZE(rt5645_mono_dac_l_mix)), 2153 SND_SOC_DAPM_MIXER("Mono DAC MIXR", SND_SOC_NOPM, 0, 0, 2154 rt5645_mono_dac_r_mix, ARRAY_SIZE(rt5645_mono_dac_r_mix)), 2155 SND_SOC_DAPM_MIXER("DAC MIXL", SND_SOC_NOPM, 0, 0, 2156 rt5645_dig_l_mix, ARRAY_SIZE(rt5645_dig_l_mix)), 2157 SND_SOC_DAPM_MIXER("DAC MIXR", SND_SOC_NOPM, 0, 0, 2158 rt5645_dig_r_mix, ARRAY_SIZE(rt5645_dig_r_mix)), 2159 2160 /* DACs */ 2161 SND_SOC_DAPM_DAC("DAC L1", NULL, RT5645_PWR_DIG1, RT5645_PWR_DAC_L1_BIT, 2162 0), 2163 SND_SOC_DAPM_DAC("DAC L2", NULL, RT5645_PWR_DIG1, RT5645_PWR_DAC_L2_BIT, 2164 0), 2165 SND_SOC_DAPM_DAC("DAC R1", NULL, RT5645_PWR_DIG1, RT5645_PWR_DAC_R1_BIT, 2166 0), 2167 SND_SOC_DAPM_DAC("DAC R2", NULL, RT5645_PWR_DIG1, RT5645_PWR_DAC_R2_BIT, 2168 0), 2169 /* OUT Mixer */ 2170 SND_SOC_DAPM_MIXER("SPK MIXL", RT5645_PWR_MIXER, RT5645_PWR_SM_L_BIT, 2171 0, rt5645_spk_l_mix, ARRAY_SIZE(rt5645_spk_l_mix)), 2172 SND_SOC_DAPM_MIXER("SPK MIXR", RT5645_PWR_MIXER, RT5645_PWR_SM_R_BIT, 2173 0, rt5645_spk_r_mix, ARRAY_SIZE(rt5645_spk_r_mix)), 2174 SND_SOC_DAPM_MIXER("OUT MIXL", RT5645_PWR_MIXER, RT5645_PWR_OM_L_BIT, 2175 0, rt5645_out_l_mix, ARRAY_SIZE(rt5645_out_l_mix)), 2176 SND_SOC_DAPM_MIXER("OUT MIXR", RT5645_PWR_MIXER, RT5645_PWR_OM_R_BIT, 2177 0, rt5645_out_r_mix, ARRAY_SIZE(rt5645_out_r_mix)), 2178 /* Ouput Volume */ 2179 SND_SOC_DAPM_SWITCH("SPKVOL L", RT5645_PWR_VOL, RT5645_PWR_SV_L_BIT, 0, 2180 &spk_l_vol_control), 2181 SND_SOC_DAPM_SWITCH("SPKVOL R", RT5645_PWR_VOL, RT5645_PWR_SV_R_BIT, 0, 2182 &spk_r_vol_control), 2183 SND_SOC_DAPM_MIXER("HPOVOL MIXL", RT5645_PWR_VOL, RT5645_PWR_HV_L_BIT, 2184 0, rt5645_hpvoll_mix, ARRAY_SIZE(rt5645_hpvoll_mix)), 2185 SND_SOC_DAPM_MIXER("HPOVOL MIXR", RT5645_PWR_VOL, RT5645_PWR_HV_R_BIT, 2186 0, rt5645_hpvolr_mix, ARRAY_SIZE(rt5645_hpvolr_mix)), 2187 SND_SOC_DAPM_SUPPLY("HPOVOL MIXL Power", RT5645_PWR_MIXER, 2188 RT5645_PWR_HM_L_BIT, 0, NULL, 0), 2189 SND_SOC_DAPM_SUPPLY("HPOVOL MIXR Power", RT5645_PWR_MIXER, 2190 RT5645_PWR_HM_R_BIT, 0, NULL, 0), 2191 SND_SOC_DAPM_PGA("DAC 1", SND_SOC_NOPM, 0, 0, NULL, 0), 2192 SND_SOC_DAPM_PGA("DAC 2", SND_SOC_NOPM, 0, 0, NULL, 0), 2193 SND_SOC_DAPM_PGA("HPOVOL", SND_SOC_NOPM, 0, 0, NULL, 0), 2194 SND_SOC_DAPM_SWITCH("HPOVOL L", SND_SOC_NOPM, 0, 0, &hp_l_vol_control), 2195 SND_SOC_DAPM_SWITCH("HPOVOL R", SND_SOC_NOPM, 0, 0, &hp_r_vol_control), 2196 2197 /* HPO/LOUT/Mono Mixer */ 2198 SND_SOC_DAPM_MIXER("SPOL MIX", SND_SOC_NOPM, 0, 0, rt5645_spo_l_mix, 2199 ARRAY_SIZE(rt5645_spo_l_mix)), 2200 SND_SOC_DAPM_MIXER("SPOR MIX", SND_SOC_NOPM, 0, 0, rt5645_spo_r_mix, 2201 ARRAY_SIZE(rt5645_spo_r_mix)), 2202 SND_SOC_DAPM_MIXER("HPO MIX", SND_SOC_NOPM, 0, 0, rt5645_hpo_mix, 2203 ARRAY_SIZE(rt5645_hpo_mix)), 2204 SND_SOC_DAPM_MIXER("LOUT MIX", SND_SOC_NOPM, 0, 0, rt5645_lout_mix, 2205 ARRAY_SIZE(rt5645_lout_mix)), 2206 2207 SND_SOC_DAPM_PGA_S("HP amp", 1, SND_SOC_NOPM, 0, 0, rt5645_hp_event, 2208 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU), 2209 SND_SOC_DAPM_PGA_S("LOUT amp", 1, SND_SOC_NOPM, 0, 0, rt5645_lout_event, 2210 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU), 2211 SND_SOC_DAPM_PGA_S("SPK amp", 2, SND_SOC_NOPM, 0, 0, rt5645_spk_event, 2212 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU), 2213 2214 /* PDM */ 2215 SND_SOC_DAPM_SUPPLY("PDM1 Power", RT5645_PWR_DIG2, RT5645_PWR_PDM1_BIT, 2216 0, NULL, 0), 2217 SND_SOC_DAPM_MUX("PDM1 L Mux", SND_SOC_NOPM, 0, 0, &rt5645_pdm1_l_mux), 2218 SND_SOC_DAPM_MUX("PDM1 R Mux", SND_SOC_NOPM, 0, 0, &rt5645_pdm1_r_mux), 2219 2220 SND_SOC_DAPM_SWITCH("PDM1 L", SND_SOC_NOPM, 0, 0, &pdm1_l_vol_control), 2221 SND_SOC_DAPM_SWITCH("PDM1 R", SND_SOC_NOPM, 0, 0, &pdm1_r_vol_control), 2222 2223 /* Output Lines */ 2224 SND_SOC_DAPM_OUTPUT("HPOL"), 2225 SND_SOC_DAPM_OUTPUT("HPOR"), 2226 SND_SOC_DAPM_OUTPUT("LOUTL"), 2227 SND_SOC_DAPM_OUTPUT("LOUTR"), 2228 SND_SOC_DAPM_OUTPUT("PDM1L"), 2229 SND_SOC_DAPM_OUTPUT("PDM1R"), 2230 SND_SOC_DAPM_OUTPUT("SPOL"), 2231 SND_SOC_DAPM_OUTPUT("SPOR"), 2232 }; 2233 2234 static const struct snd_soc_dapm_widget rt5645_specific_dapm_widgets[] = { 2235 SND_SOC_DAPM_MUX("RT5645 IF1 DAC1 L Mux", SND_SOC_NOPM, 0, 0, 2236 &rt5645_if1_dac0_tdm_sel_mux), 2237 SND_SOC_DAPM_MUX("RT5645 IF1 DAC1 R Mux", SND_SOC_NOPM, 0, 0, 2238 &rt5645_if1_dac1_tdm_sel_mux), 2239 SND_SOC_DAPM_MUX("RT5645 IF1 DAC2 L Mux", SND_SOC_NOPM, 0, 0, 2240 &rt5645_if1_dac2_tdm_sel_mux), 2241 SND_SOC_DAPM_MUX("RT5645 IF1 DAC2 R Mux", SND_SOC_NOPM, 0, 0, 2242 &rt5645_if1_dac3_tdm_sel_mux), 2243 SND_SOC_DAPM_MUX("RT5645 IF1 ADC Mux", SND_SOC_NOPM, 2244 0, 0, &rt5645_if1_adc_in_mux), 2245 SND_SOC_DAPM_MUX("RT5645 IF1 ADC1 Swap Mux", SND_SOC_NOPM, 2246 0, 0, &rt5645_if1_adc1_in_mux), 2247 SND_SOC_DAPM_MUX("RT5645 IF1 ADC2 Swap Mux", SND_SOC_NOPM, 2248 0, 0, &rt5645_if1_adc2_in_mux), 2249 SND_SOC_DAPM_MUX("RT5645 IF1 ADC3 Swap Mux", SND_SOC_NOPM, 2250 0, 0, &rt5645_if1_adc3_in_mux), 2251 }; 2252 2253 static const struct snd_soc_dapm_widget rt5650_specific_dapm_widgets[] = { 2254 SND_SOC_DAPM_MUX("A DAC1 L Mux", SND_SOC_NOPM, 2255 0, 0, &rt5650_a_dac1_l_mux), 2256 SND_SOC_DAPM_MUX("A DAC1 R Mux", SND_SOC_NOPM, 2257 0, 0, &rt5650_a_dac1_r_mux), 2258 SND_SOC_DAPM_MUX("A DAC2 L Mux", SND_SOC_NOPM, 2259 0, 0, &rt5650_a_dac2_l_mux), 2260 SND_SOC_DAPM_MUX("A DAC2 R Mux", SND_SOC_NOPM, 2261 0, 0, &rt5650_a_dac2_r_mux), 2262 2263 SND_SOC_DAPM_MUX("RT5650 IF1 ADC1 Swap Mux", SND_SOC_NOPM, 2264 0, 0, &rt5650_if1_adc1_in_mux), 2265 SND_SOC_DAPM_MUX("RT5650 IF1 ADC2 Swap Mux", SND_SOC_NOPM, 2266 0, 0, &rt5650_if1_adc2_in_mux), 2267 SND_SOC_DAPM_MUX("RT5650 IF1 ADC3 Swap Mux", SND_SOC_NOPM, 2268 0, 0, &rt5650_if1_adc3_in_mux), 2269 SND_SOC_DAPM_MUX("RT5650 IF1 ADC Mux", SND_SOC_NOPM, 2270 0, 0, &rt5650_if1_adc_in_mux), 2271 2272 SND_SOC_DAPM_MUX("RT5650 IF1 DAC1 L Mux", SND_SOC_NOPM, 0, 0, 2273 &rt5650_if1_dac0_tdm_sel_mux), 2274 SND_SOC_DAPM_MUX("RT5650 IF1 DAC1 R Mux", SND_SOC_NOPM, 0, 0, 2275 &rt5650_if1_dac1_tdm_sel_mux), 2276 SND_SOC_DAPM_MUX("RT5650 IF1 DAC2 L Mux", SND_SOC_NOPM, 0, 0, 2277 &rt5650_if1_dac2_tdm_sel_mux), 2278 SND_SOC_DAPM_MUX("RT5650 IF1 DAC2 R Mux", SND_SOC_NOPM, 0, 0, 2279 &rt5650_if1_dac3_tdm_sel_mux), 2280 }; 2281 2282 static const struct snd_soc_dapm_route rt5645_dapm_routes[] = { 2283 { "adc stereo1 filter", NULL, "ADC STO1 ASRC", is_using_asrc }, 2284 { "adc mono left filter", NULL, "ADC MONO L ASRC", is_using_asrc }, 2285 { "adc mono right filter", NULL, "ADC MONO R ASRC", is_using_asrc }, 2286 { "dac mono left filter", NULL, "DAC MONO L ASRC", is_using_asrc }, 2287 { "dac mono right filter", NULL, "DAC MONO R ASRC", is_using_asrc }, 2288 { "dac stereo1 filter", NULL, "DAC STO ASRC", is_using_asrc }, 2289 2290 { "I2S1", NULL, "I2S1 ASRC" }, 2291 { "I2S2", NULL, "I2S2 ASRC" }, 2292 2293 { "IN1P", NULL, "LDO2" }, 2294 { "IN2P", NULL, "LDO2" }, 2295 2296 { "DMIC1", NULL, "DMIC L1" }, 2297 { "DMIC1", NULL, "DMIC R1" }, 2298 { "DMIC2", NULL, "DMIC L2" }, 2299 { "DMIC2", NULL, "DMIC R2" }, 2300 2301 { "BST1", NULL, "IN1P" }, 2302 { "BST1", NULL, "IN1N" }, 2303 { "BST1", NULL, "JD Power" }, 2304 { "BST1", NULL, "Mic Det Power" }, 2305 { "BST2", NULL, "IN2P" }, 2306 { "BST2", NULL, "IN2N" }, 2307 2308 { "INL VOL", NULL, "IN2P" }, 2309 { "INR VOL", NULL, "IN2N" }, 2310 2311 { "RECMIXL", "HPOL Switch", "HPOL" }, 2312 { "RECMIXL", "INL Switch", "INL VOL" }, 2313 { "RECMIXL", "BST2 Switch", "BST2" }, 2314 { "RECMIXL", "BST1 Switch", "BST1" }, 2315 { "RECMIXL", "OUT MIXL Switch", "OUT MIXL" }, 2316 2317 { "RECMIXR", "HPOR Switch", "HPOR" }, 2318 { "RECMIXR", "INR Switch", "INR VOL" }, 2319 { "RECMIXR", "BST2 Switch", "BST2" }, 2320 { "RECMIXR", "BST1 Switch", "BST1" }, 2321 { "RECMIXR", "OUT MIXR Switch", "OUT MIXR" }, 2322 2323 { "ADC L", NULL, "RECMIXL" }, 2324 { "ADC L", NULL, "ADC L power" }, 2325 { "ADC R", NULL, "RECMIXR" }, 2326 { "ADC R", NULL, "ADC R power" }, 2327 2328 {"DMIC L1", NULL, "DMIC CLK"}, 2329 {"DMIC L1", NULL, "DMIC1 Power"}, 2330 {"DMIC R1", NULL, "DMIC CLK"}, 2331 {"DMIC R1", NULL, "DMIC1 Power"}, 2332 {"DMIC L2", NULL, "DMIC CLK"}, 2333 {"DMIC L2", NULL, "DMIC2 Power"}, 2334 {"DMIC R2", NULL, "DMIC CLK"}, 2335 {"DMIC R2", NULL, "DMIC2 Power"}, 2336 2337 { "Stereo1 DMIC Mux", "DMIC1", "DMIC1" }, 2338 { "Stereo1 DMIC Mux", "DMIC2", "DMIC2" }, 2339 { "Stereo1 DMIC Mux", NULL, "DMIC STO1 ASRC" }, 2340 2341 { "Mono DMIC L Mux", "DMIC1", "DMIC L1" }, 2342 { "Mono DMIC L Mux", "DMIC2", "DMIC L2" }, 2343 { "Mono DMIC L Mux", NULL, "DMIC MONO L ASRC" }, 2344 2345 { "Mono DMIC R Mux", "DMIC1", "DMIC R1" }, 2346 { "Mono DMIC R Mux", "DMIC2", "DMIC R2" }, 2347 { "Mono DMIC R Mux", NULL, "DMIC MONO R ASRC" }, 2348 2349 { "Stereo1 ADC L2 Mux", "DMIC", "Stereo1 DMIC Mux" }, 2350 { "Stereo1 ADC L2 Mux", "DAC MIX", "DAC MIXL" }, 2351 { "Stereo1 ADC L1 Mux", "ADC", "ADC L" }, 2352 { "Stereo1 ADC L1 Mux", "DAC MIX", "DAC MIXL" }, 2353 2354 { "Stereo1 ADC R1 Mux", "ADC", "ADC R" }, 2355 { "Stereo1 ADC R1 Mux", "DAC MIX", "DAC MIXR" }, 2356 { "Stereo1 ADC R2 Mux", "DMIC", "Stereo1 DMIC Mux" }, 2357 { "Stereo1 ADC R2 Mux", "DAC MIX", "DAC MIXR" }, 2358 2359 { "Mono ADC L2 Mux", "DMIC", "Mono DMIC L Mux" }, 2360 { "Mono ADC L2 Mux", "Mono DAC MIXL", "Mono DAC MIXL" }, 2361 { "Mono ADC L1 Mux", "Mono DAC MIXL", "Mono DAC MIXL" }, 2362 { "Mono ADC L1 Mux", "ADC", "ADC L" }, 2363 2364 { "Mono ADC R1 Mux", "Mono DAC MIXR", "Mono DAC MIXR" }, 2365 { "Mono ADC R1 Mux", "ADC", "ADC R" }, 2366 { "Mono ADC R2 Mux", "DMIC", "Mono DMIC R Mux" }, 2367 { "Mono ADC R2 Mux", "Mono DAC MIXR", "Mono DAC MIXR" }, 2368 2369 { "Sto1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC L1 Mux" }, 2370 { "Sto1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC L2 Mux" }, 2371 { "Sto1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC R1 Mux" }, 2372 { "Sto1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC R2 Mux" }, 2373 2374 { "Stereo1 ADC MIXL", NULL, "Sto1 ADC MIXL" }, 2375 { "Stereo1 ADC MIXL", NULL, "adc stereo1 filter" }, 2376 { "adc stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll }, 2377 2378 { "Stereo1 ADC MIXR", NULL, "Sto1 ADC MIXR" }, 2379 { "Stereo1 ADC MIXR", NULL, "adc stereo1 filter" }, 2380 { "adc stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll }, 2381 2382 { "Mono ADC MIXL", "ADC1 Switch", "Mono ADC L1 Mux" }, 2383 { "Mono ADC MIXL", "ADC2 Switch", "Mono ADC L2 Mux" }, 2384 { "Mono ADC MIXL", NULL, "adc mono left filter" }, 2385 { "adc mono left filter", NULL, "PLL1", is_sys_clk_from_pll }, 2386 2387 { "Mono ADC MIXR", "ADC1 Switch", "Mono ADC R1 Mux" }, 2388 { "Mono ADC MIXR", "ADC2 Switch", "Mono ADC R2 Mux" }, 2389 { "Mono ADC MIXR", NULL, "adc mono right filter" }, 2390 { "adc mono right filter", NULL, "PLL1", is_sys_clk_from_pll }, 2391 2392 { "VAD ADC Mux", "Sto1 ADC L", "Stereo1 ADC MIXL" }, 2393 { "VAD ADC Mux", "Mono ADC L", "Mono ADC MIXL" }, 2394 { "VAD ADC Mux", "Mono ADC R", "Mono ADC MIXR" }, 2395 2396 { "IF_ADC1", NULL, "Stereo1 ADC MIXL" }, 2397 { "IF_ADC1", NULL, "Stereo1 ADC MIXR" }, 2398 { "IF_ADC2", NULL, "Mono ADC MIXL" }, 2399 { "IF_ADC2", NULL, "Mono ADC MIXR" }, 2400 { "VAD_ADC", NULL, "VAD ADC Mux" }, 2401 2402 { "IF2 ADC Mux", "IF_ADC1", "IF_ADC1" }, 2403 { "IF2 ADC Mux", "IF_ADC2", "IF_ADC2" }, 2404 { "IF2 ADC Mux", "VAD_ADC", "VAD_ADC" }, 2405 2406 { "IF1 ADC", NULL, "I2S1" }, 2407 { "IF2 ADC", NULL, "I2S2" }, 2408 { "IF2 ADC", NULL, "IF2 ADC Mux" }, 2409 2410 { "AIF2TX", NULL, "IF2 ADC" }, 2411 2412 { "IF1 DAC0", NULL, "AIF1RX" }, 2413 { "IF1 DAC1", NULL, "AIF1RX" }, 2414 { "IF1 DAC2", NULL, "AIF1RX" }, 2415 { "IF1 DAC3", NULL, "AIF1RX" }, 2416 { "IF2 DAC", NULL, "AIF2RX" }, 2417 2418 { "IF1 DAC0", NULL, "I2S1" }, 2419 { "IF1 DAC1", NULL, "I2S1" }, 2420 { "IF1 DAC2", NULL, "I2S1" }, 2421 { "IF1 DAC3", NULL, "I2S1" }, 2422 { "IF2 DAC", NULL, "I2S2" }, 2423 2424 { "IF2 DAC L", NULL, "IF2 DAC" }, 2425 { "IF2 DAC R", NULL, "IF2 DAC" }, 2426 2427 { "DAC1 L Mux", "IF2 DAC", "IF2 DAC L" }, 2428 { "DAC1 R Mux", "IF2 DAC", "IF2 DAC R" }, 2429 2430 { "DAC1 MIXL", "Stereo ADC Switch", "Stereo1 ADC MIXL" }, 2431 { "DAC1 MIXL", "DAC1 Switch", "DAC1 L Mux" }, 2432 { "DAC1 MIXL", NULL, "dac stereo1 filter" }, 2433 { "DAC1 MIXR", "Stereo ADC Switch", "Stereo1 ADC MIXR" }, 2434 { "DAC1 MIXR", "DAC1 Switch", "DAC1 R Mux" }, 2435 { "DAC1 MIXR", NULL, "dac stereo1 filter" }, 2436 2437 { "DAC L2 Mux", "IF2 DAC", "IF2 DAC L" }, 2438 { "DAC L2 Mux", "Mono ADC", "Mono ADC MIXL" }, 2439 { "DAC L2 Mux", "VAD_ADC", "VAD_ADC" }, 2440 { "DAC L2 Volume", NULL, "DAC L2 Mux" }, 2441 { "DAC L2 Volume", NULL, "dac mono left filter" }, 2442 2443 { "DAC R2 Mux", "IF2 DAC", "IF2 DAC R" }, 2444 { "DAC R2 Mux", "Mono ADC", "Mono ADC MIXR" }, 2445 { "DAC R2 Mux", "Haptic", "Haptic Generator" }, 2446 { "DAC R2 Volume", NULL, "DAC R2 Mux" }, 2447 { "DAC R2 Volume", NULL, "dac mono right filter" }, 2448 2449 { "Stereo DAC MIXL", "DAC L1 Switch", "DAC1 MIXL" }, 2450 { "Stereo DAC MIXL", "DAC R1 Switch", "DAC1 MIXR" }, 2451 { "Stereo DAC MIXL", "DAC L2 Switch", "DAC L2 Volume" }, 2452 { "Stereo DAC MIXL", NULL, "dac stereo1 filter" }, 2453 { "Stereo DAC MIXR", "DAC R1 Switch", "DAC1 MIXR" }, 2454 { "Stereo DAC MIXR", "DAC L1 Switch", "DAC1 MIXL" }, 2455 { "Stereo DAC MIXR", "DAC R2 Switch", "DAC R2 Volume" }, 2456 { "Stereo DAC MIXR", NULL, "dac stereo1 filter" }, 2457 2458 { "Mono DAC MIXL", "DAC L1 Switch", "DAC1 MIXL" }, 2459 { "Mono DAC MIXL", "DAC L2 Switch", "DAC L2 Volume" }, 2460 { "Mono DAC MIXL", "DAC R2 Switch", "DAC R2 Volume" }, 2461 { "Mono DAC MIXL", NULL, "dac mono left filter" }, 2462 { "Mono DAC MIXR", "DAC R1 Switch", "DAC1 MIXR" }, 2463 { "Mono DAC MIXR", "DAC R2 Switch", "DAC R2 Volume" }, 2464 { "Mono DAC MIXR", "DAC L2 Switch", "DAC L2 Volume" }, 2465 { "Mono DAC MIXR", NULL, "dac mono right filter" }, 2466 2467 { "DAC MIXL", "Sto DAC Mix L Switch", "Stereo DAC MIXL" }, 2468 { "DAC MIXL", "DAC L2 Switch", "DAC L2 Volume" }, 2469 { "DAC MIXL", "DAC R2 Switch", "DAC R2 Volume" }, 2470 { "DAC MIXR", "Sto DAC Mix R Switch", "Stereo DAC MIXR" }, 2471 { "DAC MIXR", "DAC R2 Switch", "DAC R2 Volume" }, 2472 { "DAC MIXR", "DAC L2 Switch", "DAC L2 Volume" }, 2473 2474 { "DAC L1", NULL, "PLL1", is_sys_clk_from_pll }, 2475 { "DAC R1", NULL, "PLL1", is_sys_clk_from_pll }, 2476 { "DAC L2", NULL, "PLL1", is_sys_clk_from_pll }, 2477 { "DAC R2", NULL, "PLL1", is_sys_clk_from_pll }, 2478 2479 { "SPK MIXL", "BST1 Switch", "BST1" }, 2480 { "SPK MIXL", "INL Switch", "INL VOL" }, 2481 { "SPK MIXL", "DAC L1 Switch", "DAC L1" }, 2482 { "SPK MIXL", "DAC L2 Switch", "DAC L2" }, 2483 { "SPK MIXR", "BST2 Switch", "BST2" }, 2484 { "SPK MIXR", "INR Switch", "INR VOL" }, 2485 { "SPK MIXR", "DAC R1 Switch", "DAC R1" }, 2486 { "SPK MIXR", "DAC R2 Switch", "DAC R2" }, 2487 2488 { "OUT MIXL", "BST1 Switch", "BST1" }, 2489 { "OUT MIXL", "INL Switch", "INL VOL" }, 2490 { "OUT MIXL", "DAC L2 Switch", "DAC L2" }, 2491 { "OUT MIXL", "DAC L1 Switch", "DAC L1" }, 2492 2493 { "OUT MIXR", "BST2 Switch", "BST2" }, 2494 { "OUT MIXR", "INR Switch", "INR VOL" }, 2495 { "OUT MIXR", "DAC R2 Switch", "DAC R2" }, 2496 { "OUT MIXR", "DAC R1 Switch", "DAC R1" }, 2497 2498 { "HPOVOL MIXL", "DAC1 Switch", "DAC L1" }, 2499 { "HPOVOL MIXL", "DAC2 Switch", "DAC L2" }, 2500 { "HPOVOL MIXL", "INL Switch", "INL VOL" }, 2501 { "HPOVOL MIXL", "BST1 Switch", "BST1" }, 2502 { "HPOVOL MIXL", NULL, "HPOVOL MIXL Power" }, 2503 { "HPOVOL MIXR", "DAC1 Switch", "DAC R1" }, 2504 { "HPOVOL MIXR", "DAC2 Switch", "DAC R2" }, 2505 { "HPOVOL MIXR", "INR Switch", "INR VOL" }, 2506 { "HPOVOL MIXR", "BST2 Switch", "BST2" }, 2507 { "HPOVOL MIXR", NULL, "HPOVOL MIXR Power" }, 2508 2509 { "DAC 2", NULL, "DAC L2" }, 2510 { "DAC 2", NULL, "DAC R2" }, 2511 { "DAC 1", NULL, "DAC L1" }, 2512 { "DAC 1", NULL, "DAC R1" }, 2513 { "HPOVOL L", "Switch", "HPOVOL MIXL" }, 2514 { "HPOVOL R", "Switch", "HPOVOL MIXR" }, 2515 { "HPOVOL", NULL, "HPOVOL L" }, 2516 { "HPOVOL", NULL, "HPOVOL R" }, 2517 { "HPO MIX", "DAC1 Switch", "DAC 1" }, 2518 { "HPO MIX", "HPVOL Switch", "HPOVOL" }, 2519 2520 { "SPKVOL L", "Switch", "SPK MIXL" }, 2521 { "SPKVOL R", "Switch", "SPK MIXR" }, 2522 2523 { "SPOL MIX", "DAC L1 Switch", "DAC L1" }, 2524 { "SPOL MIX", "SPKVOL L Switch", "SPKVOL L" }, 2525 { "SPOR MIX", "DAC R1 Switch", "DAC R1" }, 2526 { "SPOR MIX", "SPKVOL R Switch", "SPKVOL R" }, 2527 2528 { "LOUT MIX", "DAC L1 Switch", "DAC L1" }, 2529 { "LOUT MIX", "DAC R1 Switch", "DAC R1" }, 2530 { "LOUT MIX", "OUTMIX L Switch", "OUT MIXL" }, 2531 { "LOUT MIX", "OUTMIX R Switch", "OUT MIXR" }, 2532 2533 { "PDM1 L Mux", "Stereo DAC", "Stereo DAC MIXL" }, 2534 { "PDM1 L Mux", "Mono DAC", "Mono DAC MIXL" }, 2535 { "PDM1 L Mux", NULL, "PDM1 Power" }, 2536 { "PDM1 R Mux", "Stereo DAC", "Stereo DAC MIXR" }, 2537 { "PDM1 R Mux", "Mono DAC", "Mono DAC MIXR" }, 2538 { "PDM1 R Mux", NULL, "PDM1 Power" }, 2539 2540 { "HP amp", NULL, "HPO MIX" }, 2541 { "HP amp", NULL, "JD Power" }, 2542 { "HP amp", NULL, "Mic Det Power" }, 2543 { "HP amp", NULL, "LDO2" }, 2544 { "HPOL", NULL, "HP amp" }, 2545 { "HPOR", NULL, "HP amp" }, 2546 2547 { "LOUT amp", NULL, "LOUT MIX" }, 2548 { "LOUTL", NULL, "LOUT amp" }, 2549 { "LOUTR", NULL, "LOUT amp" }, 2550 2551 { "PDM1 L", "Switch", "PDM1 L Mux" }, 2552 { "PDM1 R", "Switch", "PDM1 R Mux" }, 2553 2554 { "PDM1L", NULL, "PDM1 L" }, 2555 { "PDM1R", NULL, "PDM1 R" }, 2556 2557 { "SPK amp", NULL, "SPOL MIX" }, 2558 { "SPK amp", NULL, "SPOR MIX" }, 2559 { "SPOL", NULL, "SPK amp" }, 2560 { "SPOR", NULL, "SPK amp" }, 2561 }; 2562 2563 static const struct snd_soc_dapm_route rt5650_specific_dapm_routes[] = { 2564 { "A DAC1 L Mux", "DAC1", "DAC1 MIXL"}, 2565 { "A DAC1 L Mux", "Stereo DAC Mixer", "Stereo DAC MIXL"}, 2566 { "A DAC1 R Mux", "DAC1", "DAC1 MIXR"}, 2567 { "A DAC1 R Mux", "Stereo DAC Mixer", "Stereo DAC MIXR"}, 2568 2569 { "A DAC2 L Mux", "Stereo DAC Mixer", "Stereo DAC MIXL"}, 2570 { "A DAC2 L Mux", "Mono DAC Mixer", "Mono DAC MIXL"}, 2571 { "A DAC2 R Mux", "Stereo DAC Mixer", "Stereo DAC MIXR"}, 2572 { "A DAC2 R Mux", "Mono DAC Mixer", "Mono DAC MIXR"}, 2573 2574 { "DAC L1", NULL, "A DAC1 L Mux" }, 2575 { "DAC R1", NULL, "A DAC1 R Mux" }, 2576 { "DAC L2", NULL, "A DAC2 L Mux" }, 2577 { "DAC R2", NULL, "A DAC2 R Mux" }, 2578 2579 { "RT5650 IF1 ADC1 Swap Mux", "L/R", "IF_ADC1" }, 2580 { "RT5650 IF1 ADC1 Swap Mux", "R/L", "IF_ADC1" }, 2581 { "RT5650 IF1 ADC1 Swap Mux", "L/L", "IF_ADC1" }, 2582 { "RT5650 IF1 ADC1 Swap Mux", "R/R", "IF_ADC1" }, 2583 2584 { "RT5650 IF1 ADC2 Swap Mux", "L/R", "IF_ADC2" }, 2585 { "RT5650 IF1 ADC2 Swap Mux", "R/L", "IF_ADC2" }, 2586 { "RT5650 IF1 ADC2 Swap Mux", "L/L", "IF_ADC2" }, 2587 { "RT5650 IF1 ADC2 Swap Mux", "R/R", "IF_ADC2" }, 2588 2589 { "RT5650 IF1 ADC3 Swap Mux", "L/R", "VAD_ADC" }, 2590 { "RT5650 IF1 ADC3 Swap Mux", "R/L", "VAD_ADC" }, 2591 { "RT5650 IF1 ADC3 Swap Mux", "L/L", "VAD_ADC" }, 2592 { "RT5650 IF1 ADC3 Swap Mux", "R/R", "VAD_ADC" }, 2593 2594 { "IF1 ADC", NULL, "RT5650 IF1 ADC1 Swap Mux" }, 2595 { "IF1 ADC", NULL, "RT5650 IF1 ADC2 Swap Mux" }, 2596 { "IF1 ADC", NULL, "RT5650 IF1 ADC3 Swap Mux" }, 2597 2598 { "RT5650 IF1 ADC Mux", "IF_ADC1/IF_ADC2/DAC_REF/Null", "IF1 ADC" }, 2599 { "RT5650 IF1 ADC Mux", "IF_ADC1/IF_ADC2/Null/DAC_REF", "IF1 ADC" }, 2600 { "RT5650 IF1 ADC Mux", "IF_ADC1/DAC_REF/IF_ADC2/Null", "IF1 ADC" }, 2601 { "RT5650 IF1 ADC Mux", "IF_ADC1/DAC_REF/Null/IF_ADC2", "IF1 ADC" }, 2602 { "RT5650 IF1 ADC Mux", "IF_ADC1/Null/DAC_REF/IF_ADC2", "IF1 ADC" }, 2603 { "RT5650 IF1 ADC Mux", "IF_ADC1/Null/IF_ADC2/DAC_REF", "IF1 ADC" }, 2604 2605 { "RT5650 IF1 ADC Mux", "IF_ADC2/IF_ADC1/DAC_REF/Null", "IF1 ADC" }, 2606 { "RT5650 IF1 ADC Mux", "IF_ADC2/IF_ADC1/Null/DAC_REF", "IF1 ADC" }, 2607 { "RT5650 IF1 ADC Mux", "IF_ADC2/DAC_REF/IF_ADC1/Null", "IF1 ADC" }, 2608 { "RT5650 IF1 ADC Mux", "IF_ADC2/DAC_REF/Null/IF_ADC1", "IF1 ADC" }, 2609 { "RT5650 IF1 ADC Mux", "IF_ADC2/Null/DAC_REF/IF_ADC1", "IF1 ADC" }, 2610 { "RT5650 IF1 ADC Mux", "IF_ADC2/Null/IF_ADC1/DAC_REF", "IF1 ADC" }, 2611 2612 { "RT5650 IF1 ADC Mux", "DAC_REF/IF_ADC1/IF_ADC2/Null", "IF1 ADC" }, 2613 { "RT5650 IF1 ADC Mux", "DAC_REF/IF_ADC1/Null/IF_ADC2", "IF1 ADC" }, 2614 { "RT5650 IF1 ADC Mux", "DAC_REF/IF_ADC2/IF_ADC1/Null", "IF1 ADC" }, 2615 { "RT5650 IF1 ADC Mux", "DAC_REF/IF_ADC2/Null/IF_ADC1", "IF1 ADC" }, 2616 { "RT5650 IF1 ADC Mux", "DAC_REF/Null/IF_ADC1/IF_ADC2", "IF1 ADC" }, 2617 { "RT5650 IF1 ADC Mux", "DAC_REF/Null/IF_ADC2/IF_ADC1", "IF1 ADC" }, 2618 2619 { "RT5650 IF1 ADC Mux", "Null/IF_ADC1/IF_ADC2/DAC_REF", "IF1 ADC" }, 2620 { "RT5650 IF1 ADC Mux", "Null/IF_ADC1/DAC_REF/IF_ADC2", "IF1 ADC" }, 2621 { "RT5650 IF1 ADC Mux", "Null/IF_ADC2/IF_ADC1/DAC_REF", "IF1 ADC" }, 2622 { "RT5650 IF1 ADC Mux", "Null/IF_ADC2/DAC_REF/IF_ADC1", "IF1 ADC" }, 2623 { "RT5650 IF1 ADC Mux", "Null/DAC_REF/IF_ADC1/IF_ADC2", "IF1 ADC" }, 2624 { "RT5650 IF1 ADC Mux", "Null/DAC_REF/IF_ADC2/IF_ADC1", "IF1 ADC" }, 2625 { "AIF1TX", NULL, "RT5650 IF1 ADC Mux" }, 2626 2627 { "RT5650 IF1 DAC1 L Mux", "Slot0", "IF1 DAC0" }, 2628 { "RT5650 IF1 DAC1 L Mux", "Slot1", "IF1 DAC1" }, 2629 { "RT5650 IF1 DAC1 L Mux", "Slot2", "IF1 DAC2" }, 2630 { "RT5650 IF1 DAC1 L Mux", "Slot3", "IF1 DAC3" }, 2631 2632 { "RT5650 IF1 DAC1 R Mux", "Slot0", "IF1 DAC0" }, 2633 { "RT5650 IF1 DAC1 R Mux", "Slot1", "IF1 DAC1" }, 2634 { "RT5650 IF1 DAC1 R Mux", "Slot2", "IF1 DAC2" }, 2635 { "RT5650 IF1 DAC1 R Mux", "Slot3", "IF1 DAC3" }, 2636 2637 { "RT5650 IF1 DAC2 L Mux", "Slot0", "IF1 DAC0" }, 2638 { "RT5650 IF1 DAC2 L Mux", "Slot1", "IF1 DAC1" }, 2639 { "RT5650 IF1 DAC2 L Mux", "Slot2", "IF1 DAC2" }, 2640 { "RT5650 IF1 DAC2 L Mux", "Slot3", "IF1 DAC3" }, 2641 2642 { "RT5650 IF1 DAC2 R Mux", "Slot0", "IF1 DAC0" }, 2643 { "RT5650 IF1 DAC2 R Mux", "Slot1", "IF1 DAC1" }, 2644 { "RT5650 IF1 DAC2 R Mux", "Slot2", "IF1 DAC2" }, 2645 { "RT5650 IF1 DAC2 R Mux", "Slot3", "IF1 DAC3" }, 2646 2647 { "DAC1 L Mux", "IF1 DAC", "RT5650 IF1 DAC1 L Mux" }, 2648 { "DAC1 R Mux", "IF1 DAC", "RT5650 IF1 DAC1 R Mux" }, 2649 2650 { "DAC L2 Mux", "IF1 DAC", "RT5650 IF1 DAC2 L Mux" }, 2651 { "DAC R2 Mux", "IF1 DAC", "RT5650 IF1 DAC2 R Mux" }, 2652 }; 2653 2654 static const struct snd_soc_dapm_route rt5645_specific_dapm_routes[] = { 2655 { "DAC L1", NULL, "Stereo DAC MIXL" }, 2656 { "DAC R1", NULL, "Stereo DAC MIXR" }, 2657 { "DAC L2", NULL, "Mono DAC MIXL" }, 2658 { "DAC R2", NULL, "Mono DAC MIXR" }, 2659 2660 { "RT5645 IF1 ADC1 Swap Mux", "L/R", "IF_ADC1" }, 2661 { "RT5645 IF1 ADC1 Swap Mux", "R/L", "IF_ADC1" }, 2662 { "RT5645 IF1 ADC1 Swap Mux", "L/L", "IF_ADC1" }, 2663 { "RT5645 IF1 ADC1 Swap Mux", "R/R", "IF_ADC1" }, 2664 2665 { "RT5645 IF1 ADC2 Swap Mux", "L/R", "IF_ADC2" }, 2666 { "RT5645 IF1 ADC2 Swap Mux", "R/L", "IF_ADC2" }, 2667 { "RT5645 IF1 ADC2 Swap Mux", "L/L", "IF_ADC2" }, 2668 { "RT5645 IF1 ADC2 Swap Mux", "R/R", "IF_ADC2" }, 2669 2670 { "RT5645 IF1 ADC3 Swap Mux", "L/R", "VAD_ADC" }, 2671 { "RT5645 IF1 ADC3 Swap Mux", "R/L", "VAD_ADC" }, 2672 { "RT5645 IF1 ADC3 Swap Mux", "L/L", "VAD_ADC" }, 2673 { "RT5645 IF1 ADC3 Swap Mux", "R/R", "VAD_ADC" }, 2674 2675 { "IF1 ADC", NULL, "RT5645 IF1 ADC1 Swap Mux" }, 2676 { "IF1 ADC", NULL, "RT5645 IF1 ADC2 Swap Mux" }, 2677 { "IF1 ADC", NULL, "RT5645 IF1 ADC3 Swap Mux" }, 2678 2679 { "RT5645 IF1 ADC Mux", "IF_ADC1/IF_ADC2/VAD_ADC", "IF1 ADC" }, 2680 { "RT5645 IF1 ADC Mux", "IF_ADC2/IF_ADC1/VAD_ADC", "IF1 ADC" }, 2681 { "RT5645 IF1 ADC Mux", "VAD_ADC/IF_ADC1/IF_ADC2", "IF1 ADC" }, 2682 { "RT5645 IF1 ADC Mux", "VAD_ADC/IF_ADC2/IF_ADC1", "IF1 ADC" }, 2683 { "AIF1TX", NULL, "RT5645 IF1 ADC Mux" }, 2684 2685 { "RT5645 IF1 DAC1 L Mux", "Slot0", "IF1 DAC0" }, 2686 { "RT5645 IF1 DAC1 L Mux", "Slot1", "IF1 DAC1" }, 2687 { "RT5645 IF1 DAC1 L Mux", "Slot2", "IF1 DAC2" }, 2688 { "RT5645 IF1 DAC1 L Mux", "Slot3", "IF1 DAC3" }, 2689 2690 { "RT5645 IF1 DAC1 R Mux", "Slot0", "IF1 DAC0" }, 2691 { "RT5645 IF1 DAC1 R Mux", "Slot1", "IF1 DAC1" }, 2692 { "RT5645 IF1 DAC1 R Mux", "Slot2", "IF1 DAC2" }, 2693 { "RT5645 IF1 DAC1 R Mux", "Slot3", "IF1 DAC3" }, 2694 2695 { "RT5645 IF1 DAC2 L Mux", "Slot0", "IF1 DAC0" }, 2696 { "RT5645 IF1 DAC2 L Mux", "Slot1", "IF1 DAC1" }, 2697 { "RT5645 IF1 DAC2 L Mux", "Slot2", "IF1 DAC2" }, 2698 { "RT5645 IF1 DAC2 L Mux", "Slot3", "IF1 DAC3" }, 2699 2700 { "RT5645 IF1 DAC2 R Mux", "Slot0", "IF1 DAC0" }, 2701 { "RT5645 IF1 DAC2 R Mux", "Slot1", "IF1 DAC1" }, 2702 { "RT5645 IF1 DAC2 R Mux", "Slot2", "IF1 DAC2" }, 2703 { "RT5645 IF1 DAC2 R Mux", "Slot3", "IF1 DAC3" }, 2704 2705 { "DAC1 L Mux", "IF1 DAC", "RT5645 IF1 DAC1 L Mux" }, 2706 { "DAC1 R Mux", "IF1 DAC", "RT5645 IF1 DAC1 R Mux" }, 2707 2708 { "DAC L2 Mux", "IF1 DAC", "RT5645 IF1 DAC2 L Mux" }, 2709 { "DAC R2 Mux", "IF1 DAC", "RT5645 IF1 DAC2 R Mux" }, 2710 }; 2711 2712 static const struct snd_soc_dapm_route rt5645_old_dapm_routes[] = { 2713 { "SPOL MIX", "DAC R1 Switch", "DAC R1" }, 2714 { "SPOL MIX", "SPKVOL R Switch", "SPKVOL R" }, 2715 }; 2716 2717 static int rt5645_hw_params(struct snd_pcm_substream *substream, 2718 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) 2719 { 2720 struct snd_soc_component *component = dai->component; 2721 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component); 2722 unsigned int val_len = 0, val_clk, mask_clk, dl_sft; 2723 int pre_div, bclk_ms, frame_size; 2724 2725 rt5645->lrck[dai->id] = params_rate(params); 2726 pre_div = rl6231_get_clk_info(rt5645->sysclk, rt5645->lrck[dai->id]); 2727 if (pre_div < 0) { 2728 dev_err(component->dev, "Unsupported clock setting\n"); 2729 return -EINVAL; 2730 } 2731 frame_size = snd_soc_params_to_frame_size(params); 2732 if (frame_size < 0) { 2733 dev_err(component->dev, "Unsupported frame size: %d\n", frame_size); 2734 return -EINVAL; 2735 } 2736 2737 switch (rt5645->codec_type) { 2738 case CODEC_TYPE_RT5650: 2739 dl_sft = 4; 2740 break; 2741 default: 2742 dl_sft = 2; 2743 break; 2744 } 2745 2746 bclk_ms = frame_size > 32; 2747 rt5645->bclk[dai->id] = rt5645->lrck[dai->id] * (32 << bclk_ms); 2748 2749 dev_dbg(dai->dev, "bclk is %dHz and lrck is %dHz\n", 2750 rt5645->bclk[dai->id], rt5645->lrck[dai->id]); 2751 dev_dbg(dai->dev, "bclk_ms is %d and pre_div is %d for iis %d\n", 2752 bclk_ms, pre_div, dai->id); 2753 2754 switch (params_width(params)) { 2755 case 16: 2756 break; 2757 case 20: 2758 val_len = 0x1; 2759 break; 2760 case 24: 2761 val_len = 0x2; 2762 break; 2763 case 8: 2764 val_len = 0x3; 2765 break; 2766 default: 2767 return -EINVAL; 2768 } 2769 2770 switch (dai->id) { 2771 case RT5645_AIF1: 2772 mask_clk = RT5645_I2S_PD1_MASK; 2773 val_clk = pre_div << RT5645_I2S_PD1_SFT; 2774 snd_soc_component_update_bits(component, RT5645_I2S1_SDP, 2775 (0x3 << dl_sft), (val_len << dl_sft)); 2776 snd_soc_component_update_bits(component, RT5645_ADDA_CLK1, mask_clk, val_clk); 2777 break; 2778 case RT5645_AIF2: 2779 mask_clk = RT5645_I2S_BCLK_MS2_MASK | RT5645_I2S_PD2_MASK; 2780 val_clk = bclk_ms << RT5645_I2S_BCLK_MS2_SFT | 2781 pre_div << RT5645_I2S_PD2_SFT; 2782 snd_soc_component_update_bits(component, RT5645_I2S2_SDP, 2783 (0x3 << dl_sft), (val_len << dl_sft)); 2784 snd_soc_component_update_bits(component, RT5645_ADDA_CLK1, mask_clk, val_clk); 2785 break; 2786 default: 2787 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id); 2788 return -EINVAL; 2789 } 2790 2791 return 0; 2792 } 2793 2794 static int rt5645_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) 2795 { 2796 struct snd_soc_component *component = dai->component; 2797 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component); 2798 unsigned int reg_val = 0, pol_sft; 2799 2800 switch (rt5645->codec_type) { 2801 case CODEC_TYPE_RT5650: 2802 pol_sft = 8; 2803 break; 2804 default: 2805 pol_sft = 7; 2806 break; 2807 } 2808 2809 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 2810 case SND_SOC_DAIFMT_CBM_CFM: 2811 rt5645->master[dai->id] = 1; 2812 break; 2813 case SND_SOC_DAIFMT_CBS_CFS: 2814 reg_val |= RT5645_I2S_MS_S; 2815 rt5645->master[dai->id] = 0; 2816 break; 2817 default: 2818 return -EINVAL; 2819 } 2820 2821 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 2822 case SND_SOC_DAIFMT_NB_NF: 2823 break; 2824 case SND_SOC_DAIFMT_IB_NF: 2825 reg_val |= (1 << pol_sft); 2826 break; 2827 default: 2828 return -EINVAL; 2829 } 2830 2831 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 2832 case SND_SOC_DAIFMT_I2S: 2833 break; 2834 case SND_SOC_DAIFMT_LEFT_J: 2835 reg_val |= RT5645_I2S_DF_LEFT; 2836 break; 2837 case SND_SOC_DAIFMT_DSP_A: 2838 reg_val |= RT5645_I2S_DF_PCM_A; 2839 break; 2840 case SND_SOC_DAIFMT_DSP_B: 2841 reg_val |= RT5645_I2S_DF_PCM_B; 2842 break; 2843 default: 2844 return -EINVAL; 2845 } 2846 switch (dai->id) { 2847 case RT5645_AIF1: 2848 snd_soc_component_update_bits(component, RT5645_I2S1_SDP, 2849 RT5645_I2S_MS_MASK | (1 << pol_sft) | 2850 RT5645_I2S_DF_MASK, reg_val); 2851 break; 2852 case RT5645_AIF2: 2853 snd_soc_component_update_bits(component, RT5645_I2S2_SDP, 2854 RT5645_I2S_MS_MASK | (1 << pol_sft) | 2855 RT5645_I2S_DF_MASK, reg_val); 2856 break; 2857 default: 2858 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id); 2859 return -EINVAL; 2860 } 2861 return 0; 2862 } 2863 2864 static int rt5645_set_dai_sysclk(struct snd_soc_dai *dai, 2865 int clk_id, unsigned int freq, int dir) 2866 { 2867 struct snd_soc_component *component = dai->component; 2868 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component); 2869 unsigned int reg_val = 0; 2870 2871 if (freq == rt5645->sysclk && clk_id == rt5645->sysclk_src) 2872 return 0; 2873 2874 switch (clk_id) { 2875 case RT5645_SCLK_S_MCLK: 2876 reg_val |= RT5645_SCLK_SRC_MCLK; 2877 break; 2878 case RT5645_SCLK_S_PLL1: 2879 reg_val |= RT5645_SCLK_SRC_PLL1; 2880 break; 2881 case RT5645_SCLK_S_RCCLK: 2882 reg_val |= RT5645_SCLK_SRC_RCCLK; 2883 break; 2884 default: 2885 dev_err(component->dev, "Invalid clock id (%d)\n", clk_id); 2886 return -EINVAL; 2887 } 2888 snd_soc_component_update_bits(component, RT5645_GLB_CLK, 2889 RT5645_SCLK_SRC_MASK, reg_val); 2890 rt5645->sysclk = freq; 2891 rt5645->sysclk_src = clk_id; 2892 2893 dev_dbg(dai->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id); 2894 2895 return 0; 2896 } 2897 2898 static int rt5645_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source, 2899 unsigned int freq_in, unsigned int freq_out) 2900 { 2901 struct snd_soc_component *component = dai->component; 2902 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component); 2903 struct rl6231_pll_code pll_code; 2904 int ret; 2905 2906 if (source == rt5645->pll_src && freq_in == rt5645->pll_in && 2907 freq_out == rt5645->pll_out) 2908 return 0; 2909 2910 if (!freq_in || !freq_out) { 2911 dev_dbg(component->dev, "PLL disabled\n"); 2912 2913 rt5645->pll_in = 0; 2914 rt5645->pll_out = 0; 2915 snd_soc_component_update_bits(component, RT5645_GLB_CLK, 2916 RT5645_SCLK_SRC_MASK, RT5645_SCLK_SRC_MCLK); 2917 return 0; 2918 } 2919 2920 switch (source) { 2921 case RT5645_PLL1_S_MCLK: 2922 snd_soc_component_update_bits(component, RT5645_GLB_CLK, 2923 RT5645_PLL1_SRC_MASK, RT5645_PLL1_SRC_MCLK); 2924 break; 2925 case RT5645_PLL1_S_BCLK1: 2926 case RT5645_PLL1_S_BCLK2: 2927 switch (dai->id) { 2928 case RT5645_AIF1: 2929 snd_soc_component_update_bits(component, RT5645_GLB_CLK, 2930 RT5645_PLL1_SRC_MASK, RT5645_PLL1_SRC_BCLK1); 2931 break; 2932 case RT5645_AIF2: 2933 snd_soc_component_update_bits(component, RT5645_GLB_CLK, 2934 RT5645_PLL1_SRC_MASK, RT5645_PLL1_SRC_BCLK2); 2935 break; 2936 default: 2937 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id); 2938 return -EINVAL; 2939 } 2940 break; 2941 default: 2942 dev_err(component->dev, "Unknown PLL source %d\n", source); 2943 return -EINVAL; 2944 } 2945 2946 ret = rl6231_pll_calc(freq_in, freq_out, &pll_code); 2947 if (ret < 0) { 2948 dev_err(component->dev, "Unsupport input clock %d\n", freq_in); 2949 return ret; 2950 } 2951 2952 dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n", 2953 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code), 2954 pll_code.n_code, pll_code.k_code); 2955 2956 snd_soc_component_write(component, RT5645_PLL_CTRL1, 2957 pll_code.n_code << RT5645_PLL_N_SFT | pll_code.k_code); 2958 snd_soc_component_write(component, RT5645_PLL_CTRL2, 2959 (pll_code.m_bp ? 0 : pll_code.m_code) << RT5645_PLL_M_SFT | 2960 pll_code.m_bp << RT5645_PLL_M_BP_SFT); 2961 2962 rt5645->pll_in = freq_in; 2963 rt5645->pll_out = freq_out; 2964 rt5645->pll_src = source; 2965 2966 return 0; 2967 } 2968 2969 static int rt5645_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask, 2970 unsigned int rx_mask, int slots, int slot_width) 2971 { 2972 struct snd_soc_component *component = dai->component; 2973 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component); 2974 unsigned int i_slot_sft, o_slot_sft, i_width_sht, o_width_sht, en_sft; 2975 unsigned int mask, val = 0; 2976 2977 switch (rt5645->codec_type) { 2978 case CODEC_TYPE_RT5650: 2979 en_sft = 15; 2980 i_slot_sft = 10; 2981 o_slot_sft = 8; 2982 i_width_sht = 6; 2983 o_width_sht = 4; 2984 mask = 0x8ff0; 2985 break; 2986 default: 2987 en_sft = 14; 2988 i_slot_sft = o_slot_sft = 12; 2989 i_width_sht = o_width_sht = 10; 2990 mask = 0x7c00; 2991 break; 2992 } 2993 if (rx_mask || tx_mask) { 2994 val |= (1 << en_sft); 2995 if (rt5645->codec_type == CODEC_TYPE_RT5645) 2996 snd_soc_component_update_bits(component, RT5645_BASS_BACK, 2997 RT5645_G_BB_BST_MASK, RT5645_G_BB_BST_25DB); 2998 } 2999 3000 switch (slots) { 3001 case 4: 3002 val |= (1 << i_slot_sft) | (1 << o_slot_sft); 3003 break; 3004 case 6: 3005 val |= (2 << i_slot_sft) | (2 << o_slot_sft); 3006 break; 3007 case 8: 3008 val |= (3 << i_slot_sft) | (3 << o_slot_sft); 3009 break; 3010 case 2: 3011 default: 3012 break; 3013 } 3014 3015 switch (slot_width) { 3016 case 20: 3017 val |= (1 << i_width_sht) | (1 << o_width_sht); 3018 break; 3019 case 24: 3020 val |= (2 << i_width_sht) | (2 << o_width_sht); 3021 break; 3022 case 32: 3023 val |= (3 << i_width_sht) | (3 << o_width_sht); 3024 break; 3025 case 16: 3026 default: 3027 break; 3028 } 3029 3030 snd_soc_component_update_bits(component, RT5645_TDM_CTRL_1, mask, val); 3031 3032 return 0; 3033 } 3034 3035 static int rt5645_set_bias_level(struct snd_soc_component *component, 3036 enum snd_soc_bias_level level) 3037 { 3038 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component); 3039 3040 switch (level) { 3041 case SND_SOC_BIAS_PREPARE: 3042 if (SND_SOC_BIAS_STANDBY == snd_soc_component_get_bias_level(component)) { 3043 snd_soc_component_update_bits(component, RT5645_PWR_ANLG1, 3044 RT5645_PWR_VREF1 | RT5645_PWR_MB | 3045 RT5645_PWR_BG | RT5645_PWR_VREF2, 3046 RT5645_PWR_VREF1 | RT5645_PWR_MB | 3047 RT5645_PWR_BG | RT5645_PWR_VREF2); 3048 mdelay(10); 3049 snd_soc_component_update_bits(component, RT5645_PWR_ANLG1, 3050 RT5645_PWR_FV1 | RT5645_PWR_FV2, 3051 RT5645_PWR_FV1 | RT5645_PWR_FV2); 3052 snd_soc_component_update_bits(component, RT5645_GEN_CTRL1, 3053 RT5645_DIG_GATE_CTRL, RT5645_DIG_GATE_CTRL); 3054 } 3055 break; 3056 3057 case SND_SOC_BIAS_STANDBY: 3058 snd_soc_component_update_bits(component, RT5645_PWR_ANLG1, 3059 RT5645_PWR_VREF1 | RT5645_PWR_MB | 3060 RT5645_PWR_BG | RT5645_PWR_VREF2, 3061 RT5645_PWR_VREF1 | RT5645_PWR_MB | 3062 RT5645_PWR_BG | RT5645_PWR_VREF2); 3063 mdelay(10); 3064 snd_soc_component_update_bits(component, RT5645_PWR_ANLG1, 3065 RT5645_PWR_FV1 | RT5645_PWR_FV2, 3066 RT5645_PWR_FV1 | RT5645_PWR_FV2); 3067 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) { 3068 snd_soc_component_write(component, RT5645_DEPOP_M2, 0x1140); 3069 msleep(40); 3070 if (rt5645->en_button_func) 3071 queue_delayed_work(system_power_efficient_wq, 3072 &rt5645->jack_detect_work, 3073 msecs_to_jiffies(0)); 3074 } 3075 break; 3076 3077 case SND_SOC_BIAS_OFF: 3078 snd_soc_component_write(component, RT5645_DEPOP_M2, 0x1100); 3079 if (!rt5645->en_button_func) 3080 snd_soc_component_update_bits(component, RT5645_GEN_CTRL1, 3081 RT5645_DIG_GATE_CTRL, 0); 3082 snd_soc_component_update_bits(component, RT5645_PWR_ANLG1, 3083 RT5645_PWR_VREF1 | RT5645_PWR_MB | 3084 RT5645_PWR_BG | RT5645_PWR_VREF2 | 3085 RT5645_PWR_FV1 | RT5645_PWR_FV2, 0x0); 3086 break; 3087 3088 default: 3089 break; 3090 } 3091 3092 return 0; 3093 } 3094 3095 static void rt5645_enable_push_button_irq(struct snd_soc_component *component, 3096 bool enable) 3097 { 3098 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); 3099 3100 if (enable) { 3101 snd_soc_dapm_force_enable_pin(dapm, "ADC L power"); 3102 snd_soc_dapm_force_enable_pin(dapm, "ADC R power"); 3103 snd_soc_dapm_sync(dapm); 3104 3105 snd_soc_component_update_bits(component, RT5650_4BTN_IL_CMD1, 0x3, 0x3); 3106 snd_soc_component_update_bits(component, 3107 RT5645_INT_IRQ_ST, 0x8, 0x8); 3108 snd_soc_component_update_bits(component, 3109 RT5650_4BTN_IL_CMD2, 0x8000, 0x8000); 3110 snd_soc_component_read(component, RT5650_4BTN_IL_CMD1); 3111 pr_debug("%s read %x = %x\n", __func__, RT5650_4BTN_IL_CMD1, 3112 snd_soc_component_read(component, RT5650_4BTN_IL_CMD1)); 3113 } else { 3114 snd_soc_component_update_bits(component, RT5650_4BTN_IL_CMD2, 0x8000, 0x0); 3115 snd_soc_component_update_bits(component, RT5645_INT_IRQ_ST, 0x8, 0x0); 3116 3117 snd_soc_dapm_disable_pin(dapm, "ADC L power"); 3118 snd_soc_dapm_disable_pin(dapm, "ADC R power"); 3119 snd_soc_dapm_sync(dapm); 3120 } 3121 } 3122 3123 static int rt5645_jack_detect(struct snd_soc_component *component, int jack_insert) 3124 { 3125 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); 3126 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component); 3127 unsigned int val; 3128 3129 if (jack_insert) { 3130 regmap_write(rt5645->regmap, RT5645_CHARGE_PUMP, 0x0e06); 3131 3132 /* for jack type detect */ 3133 snd_soc_dapm_force_enable_pin(dapm, "LDO2"); 3134 snd_soc_dapm_force_enable_pin(dapm, "Mic Det Power"); 3135 snd_soc_dapm_sync(dapm); 3136 if (!dapm->card->instantiated) { 3137 /* Power up necessary bits for JD if dapm is 3138 not ready yet */ 3139 regmap_update_bits(rt5645->regmap, RT5645_PWR_ANLG1, 3140 RT5645_PWR_MB | RT5645_PWR_VREF2, 3141 RT5645_PWR_MB | RT5645_PWR_VREF2); 3142 regmap_update_bits(rt5645->regmap, RT5645_PWR_MIXER, 3143 RT5645_PWR_LDO2, RT5645_PWR_LDO2); 3144 regmap_update_bits(rt5645->regmap, RT5645_PWR_VOL, 3145 RT5645_PWR_MIC_DET, RT5645_PWR_MIC_DET); 3146 } 3147 3148 regmap_write(rt5645->regmap, RT5645_JD_CTRL3, 0x00f0); 3149 regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL2, 3150 RT5645_CBJ_MN_JD, RT5645_CBJ_MN_JD); 3151 regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL1, 3152 RT5645_CBJ_BST1_EN, RT5645_CBJ_BST1_EN); 3153 msleep(100); 3154 regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL2, 3155 RT5645_CBJ_MN_JD, 0); 3156 3157 msleep(600); 3158 regmap_read(rt5645->regmap, RT5645_IN1_CTRL3, &val); 3159 val &= 0x7; 3160 dev_dbg(component->dev, "val = %d\n", val); 3161 3162 if (val == 1 || val == 2) { 3163 rt5645->jack_type = SND_JACK_HEADSET; 3164 if (rt5645->en_button_func) { 3165 rt5645_enable_push_button_irq(component, true); 3166 } 3167 } else { 3168 snd_soc_dapm_disable_pin(dapm, "Mic Det Power"); 3169 snd_soc_dapm_sync(dapm); 3170 rt5645->jack_type = SND_JACK_HEADPHONE; 3171 } 3172 if (rt5645->pdata.level_trigger_irq) 3173 regmap_update_bits(rt5645->regmap, RT5645_IRQ_CTRL2, 3174 RT5645_JD_1_1_MASK, RT5645_JD_1_1_NOR); 3175 } else { /* jack out */ 3176 rt5645->jack_type = 0; 3177 3178 regmap_update_bits(rt5645->regmap, RT5645_HP_VOL, 3179 RT5645_L_MUTE | RT5645_R_MUTE, 3180 RT5645_L_MUTE | RT5645_R_MUTE); 3181 regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL2, 3182 RT5645_CBJ_MN_JD, RT5645_CBJ_MN_JD); 3183 regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL1, 3184 RT5645_CBJ_BST1_EN, 0); 3185 3186 if (rt5645->en_button_func) 3187 rt5645_enable_push_button_irq(component, false); 3188 3189 if (rt5645->pdata.jd_mode == 0) 3190 snd_soc_dapm_disable_pin(dapm, "LDO2"); 3191 snd_soc_dapm_disable_pin(dapm, "Mic Det Power"); 3192 snd_soc_dapm_sync(dapm); 3193 if (rt5645->pdata.level_trigger_irq) 3194 regmap_update_bits(rt5645->regmap, RT5645_IRQ_CTRL2, 3195 RT5645_JD_1_1_MASK, RT5645_JD_1_1_INV); 3196 } 3197 3198 return rt5645->jack_type; 3199 } 3200 3201 static int rt5645_button_detect(struct snd_soc_component *component) 3202 { 3203 int btn_type, val; 3204 3205 val = snd_soc_component_read(component, RT5650_4BTN_IL_CMD1); 3206 pr_debug("val=0x%x\n", val); 3207 btn_type = val & 0xfff0; 3208 snd_soc_component_write(component, RT5650_4BTN_IL_CMD1, val); 3209 3210 return btn_type; 3211 } 3212 3213 static irqreturn_t rt5645_irq(int irq, void *data); 3214 3215 int rt5645_set_jack_detect(struct snd_soc_component *component, 3216 struct snd_soc_jack *hp_jack, struct snd_soc_jack *mic_jack, 3217 struct snd_soc_jack *btn_jack) 3218 { 3219 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component); 3220 3221 rt5645->hp_jack = hp_jack; 3222 rt5645->mic_jack = mic_jack; 3223 rt5645->btn_jack = btn_jack; 3224 if (rt5645->btn_jack && rt5645->codec_type == CODEC_TYPE_RT5650) { 3225 rt5645->en_button_func = true; 3226 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1, 3227 RT5645_GP1_PIN_IRQ, RT5645_GP1_PIN_IRQ); 3228 regmap_update_bits(rt5645->regmap, RT5645_GEN_CTRL1, 3229 RT5645_DIG_GATE_CTRL, RT5645_DIG_GATE_CTRL); 3230 } 3231 rt5645_irq(0, rt5645); 3232 3233 return 0; 3234 } 3235 EXPORT_SYMBOL_GPL(rt5645_set_jack_detect); 3236 3237 static void rt5645_jack_detect_work(struct work_struct *work) 3238 { 3239 struct rt5645_priv *rt5645 = 3240 container_of(work, struct rt5645_priv, jack_detect_work.work); 3241 int val, btn_type, gpio_state = 0, report = 0; 3242 3243 if (!rt5645->component) 3244 return; 3245 3246 switch (rt5645->pdata.jd_mode) { 3247 case 0: /* Not using rt5645 JD */ 3248 if (rt5645->gpiod_hp_det) { 3249 gpio_state = gpiod_get_value(rt5645->gpiod_hp_det); 3250 if (rt5645->pdata.inv_hp_pol) 3251 gpio_state ^= 1; 3252 dev_dbg(rt5645->component->dev, "gpio_state = %d\n", 3253 gpio_state); 3254 report = rt5645_jack_detect(rt5645->component, gpio_state); 3255 } 3256 snd_soc_jack_report(rt5645->hp_jack, 3257 report, SND_JACK_HEADPHONE); 3258 snd_soc_jack_report(rt5645->mic_jack, 3259 report, SND_JACK_MICROPHONE); 3260 return; 3261 case 4: 3262 val = snd_soc_component_read(rt5645->component, RT5645_A_JD_CTRL1) & 0x0020; 3263 break; 3264 default: /* read rt5645 jd1_1 status */ 3265 val = snd_soc_component_read(rt5645->component, RT5645_INT_IRQ_ST) & 0x1000; 3266 break; 3267 3268 } 3269 3270 if (!val && (rt5645->jack_type == 0)) { /* jack in */ 3271 report = rt5645_jack_detect(rt5645->component, 1); 3272 } else if (!val && rt5645->jack_type != 0) { 3273 /* for push button and jack out */ 3274 btn_type = 0; 3275 if (snd_soc_component_read(rt5645->component, RT5645_INT_IRQ_ST) & 0x4) { 3276 /* button pressed */ 3277 report = SND_JACK_HEADSET; 3278 btn_type = rt5645_button_detect(rt5645->component); 3279 /* rt5650 can report three kinds of button behavior, 3280 one click, double click and hold. However, 3281 currently we will report button pressed/released 3282 event. So all the three button behaviors are 3283 treated as button pressed. */ 3284 switch (btn_type) { 3285 case 0x8000: 3286 case 0x4000: 3287 case 0x2000: 3288 report |= SND_JACK_BTN_0; 3289 break; 3290 case 0x1000: 3291 case 0x0800: 3292 case 0x0400: 3293 report |= SND_JACK_BTN_1; 3294 break; 3295 case 0x0200: 3296 case 0x0100: 3297 case 0x0080: 3298 report |= SND_JACK_BTN_2; 3299 break; 3300 case 0x0040: 3301 case 0x0020: 3302 case 0x0010: 3303 report |= SND_JACK_BTN_3; 3304 break; 3305 case 0x0000: /* unpressed */ 3306 break; 3307 default: 3308 dev_err(rt5645->component->dev, 3309 "Unexpected button code 0x%04x\n", 3310 btn_type); 3311 break; 3312 } 3313 } 3314 if (btn_type == 0)/* button release */ 3315 report = rt5645->jack_type; 3316 else { 3317 mod_timer(&rt5645->btn_check_timer, 3318 msecs_to_jiffies(100)); 3319 } 3320 } else { 3321 /* jack out */ 3322 report = 0; 3323 snd_soc_component_update_bits(rt5645->component, 3324 RT5645_INT_IRQ_ST, 0x1, 0x0); 3325 rt5645_jack_detect(rt5645->component, 0); 3326 } 3327 3328 snd_soc_jack_report(rt5645->hp_jack, report, SND_JACK_HEADPHONE); 3329 snd_soc_jack_report(rt5645->mic_jack, report, SND_JACK_MICROPHONE); 3330 if (rt5645->en_button_func) 3331 snd_soc_jack_report(rt5645->btn_jack, 3332 report, SND_JACK_BTN_0 | SND_JACK_BTN_1 | 3333 SND_JACK_BTN_2 | SND_JACK_BTN_3); 3334 } 3335 3336 static void rt5645_rcclock_work(struct work_struct *work) 3337 { 3338 struct rt5645_priv *rt5645 = 3339 container_of(work, struct rt5645_priv, rcclock_work.work); 3340 3341 regmap_update_bits(rt5645->regmap, RT5645_MICBIAS, 3342 RT5645_PWR_CLK25M_MASK, RT5645_PWR_CLK25M_PD); 3343 } 3344 3345 static irqreturn_t rt5645_irq(int irq, void *data) 3346 { 3347 struct rt5645_priv *rt5645 = data; 3348 3349 queue_delayed_work(system_power_efficient_wq, 3350 &rt5645->jack_detect_work, msecs_to_jiffies(250)); 3351 3352 return IRQ_HANDLED; 3353 } 3354 3355 static void rt5645_btn_check_callback(struct timer_list *t) 3356 { 3357 struct rt5645_priv *rt5645 = from_timer(rt5645, t, btn_check_timer); 3358 3359 queue_delayed_work(system_power_efficient_wq, 3360 &rt5645->jack_detect_work, msecs_to_jiffies(5)); 3361 } 3362 3363 static int rt5645_probe(struct snd_soc_component *component) 3364 { 3365 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); 3366 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component); 3367 3368 rt5645->component = component; 3369 3370 switch (rt5645->codec_type) { 3371 case CODEC_TYPE_RT5645: 3372 snd_soc_dapm_new_controls(dapm, 3373 rt5645_specific_dapm_widgets, 3374 ARRAY_SIZE(rt5645_specific_dapm_widgets)); 3375 snd_soc_dapm_add_routes(dapm, 3376 rt5645_specific_dapm_routes, 3377 ARRAY_SIZE(rt5645_specific_dapm_routes)); 3378 if (rt5645->v_id < 3) { 3379 snd_soc_dapm_add_routes(dapm, 3380 rt5645_old_dapm_routes, 3381 ARRAY_SIZE(rt5645_old_dapm_routes)); 3382 } 3383 break; 3384 case CODEC_TYPE_RT5650: 3385 snd_soc_dapm_new_controls(dapm, 3386 rt5650_specific_dapm_widgets, 3387 ARRAY_SIZE(rt5650_specific_dapm_widgets)); 3388 snd_soc_dapm_add_routes(dapm, 3389 rt5650_specific_dapm_routes, 3390 ARRAY_SIZE(rt5650_specific_dapm_routes)); 3391 break; 3392 } 3393 3394 snd_soc_component_force_bias_level(component, SND_SOC_BIAS_OFF); 3395 3396 /* for JD function */ 3397 if (rt5645->pdata.jd_mode) { 3398 snd_soc_dapm_force_enable_pin(dapm, "JD Power"); 3399 snd_soc_dapm_force_enable_pin(dapm, "LDO2"); 3400 snd_soc_dapm_sync(dapm); 3401 } 3402 3403 if (rt5645->pdata.long_name) 3404 component->card->long_name = rt5645->pdata.long_name; 3405 3406 rt5645->eq_param = devm_kcalloc(component->dev, 3407 RT5645_HWEQ_NUM, sizeof(struct rt5645_eq_param_s), 3408 GFP_KERNEL); 3409 3410 if (!rt5645->eq_param) 3411 return -ENOMEM; 3412 3413 return 0; 3414 } 3415 3416 static void rt5645_remove(struct snd_soc_component *component) 3417 { 3418 rt5645_reset(component); 3419 } 3420 3421 #ifdef CONFIG_PM 3422 static int rt5645_suspend(struct snd_soc_component *component) 3423 { 3424 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component); 3425 3426 regcache_cache_only(rt5645->regmap, true); 3427 regcache_mark_dirty(rt5645->regmap); 3428 3429 return 0; 3430 } 3431 3432 static int rt5645_resume(struct snd_soc_component *component) 3433 { 3434 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component); 3435 3436 regcache_cache_only(rt5645->regmap, false); 3437 regcache_sync(rt5645->regmap); 3438 3439 return 0; 3440 } 3441 #else 3442 #define rt5645_suspend NULL 3443 #define rt5645_resume NULL 3444 #endif 3445 3446 #define RT5645_STEREO_RATES SNDRV_PCM_RATE_8000_96000 3447 #define RT5645_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ 3448 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8) 3449 3450 static const struct snd_soc_dai_ops rt5645_aif_dai_ops = { 3451 .hw_params = rt5645_hw_params, 3452 .set_fmt = rt5645_set_dai_fmt, 3453 .set_sysclk = rt5645_set_dai_sysclk, 3454 .set_tdm_slot = rt5645_set_tdm_slot, 3455 .set_pll = rt5645_set_dai_pll, 3456 }; 3457 3458 static struct snd_soc_dai_driver rt5645_dai[] = { 3459 { 3460 .name = "rt5645-aif1", 3461 .id = RT5645_AIF1, 3462 .playback = { 3463 .stream_name = "AIF1 Playback", 3464 .channels_min = 1, 3465 .channels_max = 2, 3466 .rates = RT5645_STEREO_RATES, 3467 .formats = RT5645_FORMATS, 3468 }, 3469 .capture = { 3470 .stream_name = "AIF1 Capture", 3471 .channels_min = 1, 3472 .channels_max = 4, 3473 .rates = RT5645_STEREO_RATES, 3474 .formats = RT5645_FORMATS, 3475 }, 3476 .ops = &rt5645_aif_dai_ops, 3477 }, 3478 { 3479 .name = "rt5645-aif2", 3480 .id = RT5645_AIF2, 3481 .playback = { 3482 .stream_name = "AIF2 Playback", 3483 .channels_min = 1, 3484 .channels_max = 2, 3485 .rates = RT5645_STEREO_RATES, 3486 .formats = RT5645_FORMATS, 3487 }, 3488 .capture = { 3489 .stream_name = "AIF2 Capture", 3490 .channels_min = 1, 3491 .channels_max = 2, 3492 .rates = RT5645_STEREO_RATES, 3493 .formats = RT5645_FORMATS, 3494 }, 3495 .ops = &rt5645_aif_dai_ops, 3496 }, 3497 }; 3498 3499 static const struct snd_soc_component_driver soc_component_dev_rt5645 = { 3500 .probe = rt5645_probe, 3501 .remove = rt5645_remove, 3502 .suspend = rt5645_suspend, 3503 .resume = rt5645_resume, 3504 .set_bias_level = rt5645_set_bias_level, 3505 .controls = rt5645_snd_controls, 3506 .num_controls = ARRAY_SIZE(rt5645_snd_controls), 3507 .dapm_widgets = rt5645_dapm_widgets, 3508 .num_dapm_widgets = ARRAY_SIZE(rt5645_dapm_widgets), 3509 .dapm_routes = rt5645_dapm_routes, 3510 .num_dapm_routes = ARRAY_SIZE(rt5645_dapm_routes), 3511 .use_pmdown_time = 1, 3512 .endianness = 1, 3513 .non_legacy_dai_naming = 1, 3514 }; 3515 3516 static const struct regmap_config rt5645_regmap = { 3517 .reg_bits = 8, 3518 .val_bits = 16, 3519 .use_single_read = true, 3520 .use_single_write = true, 3521 .max_register = RT5645_VENDOR_ID2 + 1 + (ARRAY_SIZE(rt5645_ranges) * 3522 RT5645_PR_SPACING), 3523 .volatile_reg = rt5645_volatile_register, 3524 .readable_reg = rt5645_readable_register, 3525 3526 .cache_type = REGCACHE_RBTREE, 3527 .reg_defaults = rt5645_reg, 3528 .num_reg_defaults = ARRAY_SIZE(rt5645_reg), 3529 .ranges = rt5645_ranges, 3530 .num_ranges = ARRAY_SIZE(rt5645_ranges), 3531 }; 3532 3533 static const struct regmap_config rt5650_regmap = { 3534 .reg_bits = 8, 3535 .val_bits = 16, 3536 .use_single_read = true, 3537 .use_single_write = true, 3538 .max_register = RT5645_VENDOR_ID2 + 1 + (ARRAY_SIZE(rt5645_ranges) * 3539 RT5645_PR_SPACING), 3540 .volatile_reg = rt5645_volatile_register, 3541 .readable_reg = rt5645_readable_register, 3542 3543 .cache_type = REGCACHE_RBTREE, 3544 .reg_defaults = rt5650_reg, 3545 .num_reg_defaults = ARRAY_SIZE(rt5650_reg), 3546 .ranges = rt5645_ranges, 3547 .num_ranges = ARRAY_SIZE(rt5645_ranges), 3548 }; 3549 3550 static const struct regmap_config temp_regmap = { 3551 .name="nocache", 3552 .reg_bits = 8, 3553 .val_bits = 16, 3554 .use_single_read = true, 3555 .use_single_write = true, 3556 .max_register = RT5645_VENDOR_ID2 + 1, 3557 .cache_type = REGCACHE_NONE, 3558 }; 3559 3560 static const struct i2c_device_id rt5645_i2c_id[] = { 3561 { "rt5645", 0 }, 3562 { "rt5650", 0 }, 3563 { } 3564 }; 3565 MODULE_DEVICE_TABLE(i2c, rt5645_i2c_id); 3566 3567 #ifdef CONFIG_OF 3568 static const struct of_device_id rt5645_of_match[] = { 3569 { .compatible = "realtek,rt5645", }, 3570 { .compatible = "realtek,rt5650", }, 3571 { } 3572 }; 3573 MODULE_DEVICE_TABLE(of, rt5645_of_match); 3574 #endif 3575 3576 #ifdef CONFIG_ACPI 3577 static const struct acpi_device_id rt5645_acpi_match[] = { 3578 { "10EC5645", 0 }, 3579 { "10EC5648", 0 }, 3580 { "10EC5650", 0 }, 3581 { "10EC5640", 0 }, 3582 { "10EC3270", 0 }, 3583 {}, 3584 }; 3585 MODULE_DEVICE_TABLE(acpi, rt5645_acpi_match); 3586 #endif 3587 3588 static const struct rt5645_platform_data intel_braswell_platform_data = { 3589 .dmic1_data_pin = RT5645_DMIC1_DISABLE, 3590 .dmic2_data_pin = RT5645_DMIC_DATA_IN2P, 3591 .jd_mode = 3, 3592 }; 3593 3594 static const struct rt5645_platform_data buddy_platform_data = { 3595 .dmic1_data_pin = RT5645_DMIC_DATA_GPIO5, 3596 .dmic2_data_pin = RT5645_DMIC_DATA_IN2P, 3597 .jd_mode = 4, 3598 .level_trigger_irq = true, 3599 }; 3600 3601 static const struct rt5645_platform_data gpd_win_platform_data = { 3602 .jd_mode = 3, 3603 .inv_jd1_1 = true, 3604 .long_name = "gpd-win-pocket-rt5645", 3605 /* The GPD pocket has a diff. mic, for the win this does not matter. */ 3606 .in2_diff = true, 3607 }; 3608 3609 static const struct rt5645_platform_data asus_t100ha_platform_data = { 3610 .dmic1_data_pin = RT5645_DMIC_DATA_IN2N, 3611 .dmic2_data_pin = RT5645_DMIC2_DISABLE, 3612 .jd_mode = 3, 3613 .inv_jd1_1 = true, 3614 }; 3615 3616 static const struct rt5645_platform_data asus_t101ha_platform_data = { 3617 .dmic1_data_pin = RT5645_DMIC_DATA_IN2N, 3618 .dmic2_data_pin = RT5645_DMIC2_DISABLE, 3619 .jd_mode = 3, 3620 }; 3621 3622 static const struct rt5645_platform_data lenovo_ideapad_miix_310_pdata = { 3623 .jd_mode = 3, 3624 .in2_diff = true, 3625 }; 3626 3627 static const struct rt5645_platform_data jd_mode3_platform_data = { 3628 .jd_mode = 3, 3629 }; 3630 3631 static const struct rt5645_platform_data lattepanda_board_platform_data = { 3632 .jd_mode = 2, 3633 .inv_jd1_1 = true 3634 }; 3635 3636 static const struct rt5645_platform_data kahlee_platform_data = { 3637 .dmic1_data_pin = RT5645_DMIC_DATA_GPIO5, 3638 .dmic2_data_pin = RT5645_DMIC_DATA_IN2P, 3639 .jd_mode = 3, 3640 }; 3641 3642 static const struct rt5645_platform_data ecs_ef20_platform_data = { 3643 .dmic1_data_pin = RT5645_DMIC1_DISABLE, 3644 .dmic2_data_pin = RT5645_DMIC_DATA_IN2P, 3645 .inv_hp_pol = 1, 3646 }; 3647 3648 static const struct acpi_gpio_params ef20_hp_detect = { 1, 0, false }; 3649 3650 static const struct acpi_gpio_mapping cht_rt5645_ef20_gpios[] = { 3651 { "hp-detect-gpios", &ef20_hp_detect, 1 }, 3652 { }, 3653 }; 3654 3655 static int cht_rt5645_ef20_quirk_cb(const struct dmi_system_id *id) 3656 { 3657 cht_rt5645_gpios = cht_rt5645_ef20_gpios; 3658 return 1; 3659 } 3660 3661 static const struct dmi_system_id dmi_platform_data[] = { 3662 { 3663 .ident = "Chrome Buddy", 3664 .matches = { 3665 DMI_MATCH(DMI_PRODUCT_NAME, "Buddy"), 3666 }, 3667 .driver_data = (void *)&buddy_platform_data, 3668 }, 3669 { 3670 .ident = "Intel Strago", 3671 .matches = { 3672 DMI_MATCH(DMI_PRODUCT_NAME, "Strago"), 3673 }, 3674 .driver_data = (void *)&intel_braswell_platform_data, 3675 }, 3676 { 3677 .ident = "Google Chrome", 3678 .matches = { 3679 DMI_MATCH(DMI_SYS_VENDOR, "GOOGLE"), 3680 }, 3681 .driver_data = (void *)&intel_braswell_platform_data, 3682 }, 3683 { 3684 .ident = "Google Setzer", 3685 .matches = { 3686 DMI_MATCH(DMI_PRODUCT_NAME, "Setzer"), 3687 }, 3688 .driver_data = (void *)&intel_braswell_platform_data, 3689 }, 3690 { 3691 .ident = "Microsoft Surface 3", 3692 .matches = { 3693 DMI_MATCH(DMI_PRODUCT_NAME, "Surface 3"), 3694 }, 3695 .driver_data = (void *)&intel_braswell_platform_data, 3696 }, 3697 { 3698 /* 3699 * Match for the GPDwin which unfortunately uses somewhat 3700 * generic dmi strings, which is why we test for 4 strings. 3701 * Comparing against 23 other byt/cht boards, board_vendor 3702 * and board_name are unique to the GPDwin, where as only one 3703 * other board has the same board_serial and 3 others have 3704 * the same default product_name. Also the GPDwin is the 3705 * only device to have both board_ and product_name not set. 3706 */ 3707 .ident = "GPD Win / Pocket", 3708 .matches = { 3709 DMI_MATCH(DMI_BOARD_VENDOR, "AMI Corporation"), 3710 DMI_MATCH(DMI_BOARD_NAME, "Default string"), 3711 DMI_MATCH(DMI_BOARD_SERIAL, "Default string"), 3712 DMI_MATCH(DMI_PRODUCT_NAME, "Default string"), 3713 }, 3714 .driver_data = (void *)&gpd_win_platform_data, 3715 }, 3716 { 3717 .ident = "ASUS T100HAN", 3718 .matches = { 3719 DMI_EXACT_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."), 3720 DMI_MATCH(DMI_PRODUCT_NAME, "T100HAN"), 3721 }, 3722 .driver_data = (void *)&asus_t100ha_platform_data, 3723 }, 3724 { 3725 .ident = "ASUS T101HA", 3726 .matches = { 3727 DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."), 3728 DMI_MATCH(DMI_PRODUCT_NAME, "T101HA"), 3729 }, 3730 .driver_data = (void *)&asus_t101ha_platform_data, 3731 }, 3732 { 3733 .ident = "MINIX Z83-4", 3734 .matches = { 3735 DMI_EXACT_MATCH(DMI_SYS_VENDOR, "MINIX"), 3736 DMI_MATCH(DMI_PRODUCT_NAME, "Z83-4"), 3737 }, 3738 .driver_data = (void *)&jd_mode3_platform_data, 3739 }, 3740 { 3741 .ident = "Teclast X80 Pro", 3742 .matches = { 3743 DMI_MATCH(DMI_SYS_VENDOR, "TECLAST"), 3744 DMI_MATCH(DMI_PRODUCT_NAME, "X80 Pro"), 3745 }, 3746 .driver_data = (void *)&jd_mode3_platform_data, 3747 }, 3748 { 3749 .ident = "Lenovo Ideapad Miix 310", 3750 .matches = { 3751 DMI_EXACT_MATCH(DMI_SYS_VENDOR, "LENOVO"), 3752 DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "80SG"), 3753 DMI_EXACT_MATCH(DMI_PRODUCT_VERSION, "MIIX 310-10ICR"), 3754 }, 3755 .driver_data = (void *)&lenovo_ideapad_miix_310_pdata, 3756 }, 3757 { 3758 .ident = "Lenovo Ideapad Miix 320", 3759 .matches = { 3760 DMI_EXACT_MATCH(DMI_SYS_VENDOR, "LENOVO"), 3761 DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "80XF"), 3762 DMI_EXACT_MATCH(DMI_PRODUCT_VERSION, "Lenovo MIIX 320-10ICR"), 3763 }, 3764 .driver_data = (void *)&intel_braswell_platform_data, 3765 }, 3766 { 3767 .ident = "LattePanda board", 3768 .matches = { 3769 DMI_EXACT_MATCH(DMI_BOARD_VENDOR, "AMI Corporation"), 3770 DMI_EXACT_MATCH(DMI_BOARD_NAME, "Cherry Trail CR"), 3771 DMI_EXACT_MATCH(DMI_BOARD_VERSION, "Default string"), 3772 }, 3773 .driver_data = (void *)&lattepanda_board_platform_data, 3774 }, 3775 { 3776 .ident = "Chrome Kahlee", 3777 .matches = { 3778 DMI_MATCH(DMI_PRODUCT_NAME, "Kahlee"), 3779 }, 3780 .driver_data = (void *)&kahlee_platform_data, 3781 }, 3782 { 3783 .ident = "Medion E1239T", 3784 .matches = { 3785 DMI_EXACT_MATCH(DMI_SYS_VENDOR, "MEDION"), 3786 DMI_MATCH(DMI_PRODUCT_NAME, "E1239T MD60568"), 3787 }, 3788 .driver_data = (void *)&intel_braswell_platform_data, 3789 }, 3790 { 3791 .ident = "EF20", 3792 .callback = cht_rt5645_ef20_quirk_cb, 3793 .matches = { 3794 DMI_MATCH(DMI_PRODUCT_NAME, "EF20"), 3795 }, 3796 .driver_data = (void *)&ecs_ef20_platform_data, 3797 }, 3798 { 3799 .ident = "EF20EA", 3800 .callback = cht_rt5645_ef20_quirk_cb, 3801 .matches = { 3802 DMI_MATCH(DMI_PRODUCT_NAME, "EF20EA"), 3803 }, 3804 .driver_data = (void *)&ecs_ef20_platform_data, 3805 }, 3806 { } 3807 }; 3808 3809 static bool rt5645_check_dp(struct device *dev) 3810 { 3811 if (device_property_present(dev, "realtek,in2-differential") || 3812 device_property_present(dev, "realtek,dmic1-data-pin") || 3813 device_property_present(dev, "realtek,dmic2-data-pin") || 3814 device_property_present(dev, "realtek,jd-mode")) 3815 return true; 3816 3817 return false; 3818 } 3819 3820 static int rt5645_parse_dt(struct rt5645_priv *rt5645, struct device *dev) 3821 { 3822 rt5645->pdata.in2_diff = device_property_read_bool(dev, 3823 "realtek,in2-differential"); 3824 device_property_read_u32(dev, 3825 "realtek,dmic1-data-pin", &rt5645->pdata.dmic1_data_pin); 3826 device_property_read_u32(dev, 3827 "realtek,dmic2-data-pin", &rt5645->pdata.dmic2_data_pin); 3828 device_property_read_u32(dev, 3829 "realtek,jd-mode", &rt5645->pdata.jd_mode); 3830 3831 return 0; 3832 } 3833 3834 static int rt5645_i2c_probe(struct i2c_client *i2c, 3835 const struct i2c_device_id *id) 3836 { 3837 struct rt5645_platform_data *pdata = dev_get_platdata(&i2c->dev); 3838 const struct dmi_system_id *dmi_data; 3839 struct rt5645_priv *rt5645; 3840 int ret, i; 3841 unsigned int val; 3842 struct regmap *regmap; 3843 3844 rt5645 = devm_kzalloc(&i2c->dev, sizeof(struct rt5645_priv), 3845 GFP_KERNEL); 3846 if (rt5645 == NULL) 3847 return -ENOMEM; 3848 3849 rt5645->i2c = i2c; 3850 i2c_set_clientdata(i2c, rt5645); 3851 3852 dmi_data = dmi_first_match(dmi_platform_data); 3853 if (dmi_data) { 3854 dev_info(&i2c->dev, "Detected %s platform\n", dmi_data->ident); 3855 pdata = dmi_data->driver_data; 3856 } 3857 3858 if (pdata) 3859 rt5645->pdata = *pdata; 3860 else if (rt5645_check_dp(&i2c->dev)) 3861 rt5645_parse_dt(rt5645, &i2c->dev); 3862 else 3863 rt5645->pdata = jd_mode3_platform_data; 3864 3865 if (quirk != -1) { 3866 rt5645->pdata.in2_diff = QUIRK_IN2_DIFF(quirk); 3867 rt5645->pdata.level_trigger_irq = QUIRK_LEVEL_IRQ(quirk); 3868 rt5645->pdata.inv_jd1_1 = QUIRK_INV_JD1_1(quirk); 3869 rt5645->pdata.inv_hp_pol = QUIRK_INV_HP_POL(quirk); 3870 rt5645->pdata.jd_mode = QUIRK_JD_MODE(quirk); 3871 rt5645->pdata.dmic1_data_pin = QUIRK_DMIC1_DATA_PIN(quirk); 3872 rt5645->pdata.dmic2_data_pin = QUIRK_DMIC2_DATA_PIN(quirk); 3873 } 3874 3875 if (cht_rt5645_gpios && has_acpi_companion(&i2c->dev)) 3876 if (devm_acpi_dev_add_driver_gpios(&i2c->dev, cht_rt5645_gpios)) 3877 dev_dbg(&i2c->dev, "Failed to add driver gpios\n"); 3878 3879 rt5645->gpiod_hp_det = devm_gpiod_get_optional(&i2c->dev, "hp-detect", 3880 GPIOD_IN); 3881 3882 if (IS_ERR(rt5645->gpiod_hp_det)) { 3883 dev_info(&i2c->dev, "failed to initialize gpiod\n"); 3884 ret = PTR_ERR(rt5645->gpiod_hp_det); 3885 /* 3886 * Continue if optional gpiod is missing, bail for all other 3887 * errors, including -EPROBE_DEFER 3888 */ 3889 if (ret != -ENOENT) 3890 return ret; 3891 } 3892 3893 for (i = 0; i < ARRAY_SIZE(rt5645->supplies); i++) 3894 rt5645->supplies[i].supply = rt5645_supply_names[i]; 3895 3896 ret = devm_regulator_bulk_get(&i2c->dev, 3897 ARRAY_SIZE(rt5645->supplies), 3898 rt5645->supplies); 3899 if (ret) { 3900 dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret); 3901 return ret; 3902 } 3903 3904 ret = regulator_bulk_enable(ARRAY_SIZE(rt5645->supplies), 3905 rt5645->supplies); 3906 if (ret) { 3907 dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret); 3908 return ret; 3909 } 3910 3911 regmap = devm_regmap_init_i2c(i2c, &temp_regmap); 3912 if (IS_ERR(regmap)) { 3913 ret = PTR_ERR(regmap); 3914 dev_err(&i2c->dev, "Failed to allocate temp register map: %d\n", 3915 ret); 3916 return ret; 3917 } 3918 3919 /* 3920 * Read after 400msec, as it is the interval required between 3921 * read and power On. 3922 */ 3923 msleep(TIME_TO_POWER_MS); 3924 regmap_read(regmap, RT5645_VENDOR_ID2, &val); 3925 3926 switch (val) { 3927 case RT5645_DEVICE_ID: 3928 rt5645->regmap = devm_regmap_init_i2c(i2c, &rt5645_regmap); 3929 rt5645->codec_type = CODEC_TYPE_RT5645; 3930 break; 3931 case RT5650_DEVICE_ID: 3932 rt5645->regmap = devm_regmap_init_i2c(i2c, &rt5650_regmap); 3933 rt5645->codec_type = CODEC_TYPE_RT5650; 3934 break; 3935 default: 3936 dev_err(&i2c->dev, 3937 "Device with ID register %#x is not rt5645 or rt5650\n", 3938 val); 3939 ret = -ENODEV; 3940 goto err_enable; 3941 } 3942 3943 if (IS_ERR(rt5645->regmap)) { 3944 ret = PTR_ERR(rt5645->regmap); 3945 dev_err(&i2c->dev, "Failed to allocate register map: %d\n", 3946 ret); 3947 return ret; 3948 } 3949 3950 regmap_write(rt5645->regmap, RT5645_RESET, 0); 3951 3952 regmap_read(regmap, RT5645_VENDOR_ID, &val); 3953 rt5645->v_id = val & 0xff; 3954 3955 regmap_write(rt5645->regmap, RT5645_AD_DA_MIXER, 0x8080); 3956 3957 ret = regmap_register_patch(rt5645->regmap, init_list, 3958 ARRAY_SIZE(init_list)); 3959 if (ret != 0) 3960 dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret); 3961 3962 if (rt5645->codec_type == CODEC_TYPE_RT5650) { 3963 ret = regmap_register_patch(rt5645->regmap, rt5650_init_list, 3964 ARRAY_SIZE(rt5650_init_list)); 3965 if (ret != 0) 3966 dev_warn(&i2c->dev, "Apply rt5650 patch failed: %d\n", 3967 ret); 3968 } 3969 3970 regmap_update_bits(rt5645->regmap, RT5645_CLSD_OUT_CTRL, 0xc0, 0xc0); 3971 3972 if (rt5645->pdata.in2_diff) 3973 regmap_update_bits(rt5645->regmap, RT5645_IN2_CTRL, 3974 RT5645_IN_DF2, RT5645_IN_DF2); 3975 3976 if (rt5645->pdata.dmic1_data_pin || rt5645->pdata.dmic2_data_pin) { 3977 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1, 3978 RT5645_GP2_PIN_MASK, RT5645_GP2_PIN_DMIC1_SCL); 3979 } 3980 switch (rt5645->pdata.dmic1_data_pin) { 3981 case RT5645_DMIC_DATA_IN2N: 3982 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1, 3983 RT5645_DMIC_1_DP_MASK, RT5645_DMIC_1_DP_IN2N); 3984 break; 3985 3986 case RT5645_DMIC_DATA_GPIO5: 3987 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1, 3988 RT5645_I2S2_DAC_PIN_MASK, RT5645_I2S2_DAC_PIN_GPIO); 3989 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1, 3990 RT5645_DMIC_1_DP_MASK, RT5645_DMIC_1_DP_GPIO5); 3991 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1, 3992 RT5645_GP5_PIN_MASK, RT5645_GP5_PIN_DMIC1_SDA); 3993 break; 3994 3995 case RT5645_DMIC_DATA_GPIO11: 3996 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1, 3997 RT5645_DMIC_1_DP_MASK, RT5645_DMIC_1_DP_GPIO11); 3998 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1, 3999 RT5645_GP11_PIN_MASK, 4000 RT5645_GP11_PIN_DMIC1_SDA); 4001 break; 4002 4003 default: 4004 break; 4005 } 4006 4007 switch (rt5645->pdata.dmic2_data_pin) { 4008 case RT5645_DMIC_DATA_IN2P: 4009 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1, 4010 RT5645_DMIC_2_DP_MASK, RT5645_DMIC_2_DP_IN2P); 4011 break; 4012 4013 case RT5645_DMIC_DATA_GPIO6: 4014 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1, 4015 RT5645_DMIC_2_DP_MASK, RT5645_DMIC_2_DP_GPIO6); 4016 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1, 4017 RT5645_GP6_PIN_MASK, RT5645_GP6_PIN_DMIC2_SDA); 4018 break; 4019 4020 case RT5645_DMIC_DATA_GPIO10: 4021 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1, 4022 RT5645_DMIC_2_DP_MASK, RT5645_DMIC_2_DP_GPIO10); 4023 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1, 4024 RT5645_GP10_PIN_MASK, 4025 RT5645_GP10_PIN_DMIC2_SDA); 4026 break; 4027 4028 case RT5645_DMIC_DATA_GPIO12: 4029 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1, 4030 RT5645_DMIC_2_DP_MASK, RT5645_DMIC_2_DP_GPIO12); 4031 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1, 4032 RT5645_GP12_PIN_MASK, 4033 RT5645_GP12_PIN_DMIC2_SDA); 4034 break; 4035 4036 default: 4037 break; 4038 } 4039 4040 if (rt5645->pdata.jd_mode) { 4041 regmap_update_bits(rt5645->regmap, RT5645_GEN_CTRL3, 4042 RT5645_IRQ_CLK_GATE_CTRL, 4043 RT5645_IRQ_CLK_GATE_CTRL); 4044 regmap_update_bits(rt5645->regmap, RT5645_MICBIAS, 4045 RT5645_IRQ_CLK_INT, RT5645_IRQ_CLK_INT); 4046 regmap_update_bits(rt5645->regmap, RT5645_IRQ_CTRL2, 4047 RT5645_IRQ_JD_1_1_EN, RT5645_IRQ_JD_1_1_EN); 4048 regmap_update_bits(rt5645->regmap, RT5645_GEN_CTRL3, 4049 RT5645_JD_PSV_MODE, RT5645_JD_PSV_MODE); 4050 regmap_update_bits(rt5645->regmap, RT5645_HPO_MIXER, 4051 RT5645_IRQ_PSV_MODE, RT5645_IRQ_PSV_MODE); 4052 regmap_update_bits(rt5645->regmap, RT5645_MICBIAS, 4053 RT5645_MIC2_OVCD_EN, RT5645_MIC2_OVCD_EN); 4054 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1, 4055 RT5645_GP1_PIN_IRQ, RT5645_GP1_PIN_IRQ); 4056 switch (rt5645->pdata.jd_mode) { 4057 case 1: 4058 regmap_update_bits(rt5645->regmap, RT5645_A_JD_CTRL1, 4059 RT5645_JD1_MODE_MASK, 4060 RT5645_JD1_MODE_0); 4061 break; 4062 case 2: 4063 regmap_update_bits(rt5645->regmap, RT5645_A_JD_CTRL1, 4064 RT5645_JD1_MODE_MASK, 4065 RT5645_JD1_MODE_1); 4066 break; 4067 case 3: 4068 case 4: 4069 regmap_update_bits(rt5645->regmap, RT5645_A_JD_CTRL1, 4070 RT5645_JD1_MODE_MASK, 4071 RT5645_JD1_MODE_2); 4072 break; 4073 default: 4074 break; 4075 } 4076 if (rt5645->pdata.inv_jd1_1) { 4077 regmap_update_bits(rt5645->regmap, RT5645_IRQ_CTRL2, 4078 RT5645_JD_1_1_MASK, RT5645_JD_1_1_INV); 4079 } 4080 } 4081 4082 regmap_update_bits(rt5645->regmap, RT5645_ADDA_CLK1, 4083 RT5645_I2S_PD1_MASK, RT5645_I2S_PD1_2); 4084 4085 if (rt5645->pdata.level_trigger_irq) { 4086 regmap_update_bits(rt5645->regmap, RT5645_IRQ_CTRL2, 4087 RT5645_JD_1_1_MASK, RT5645_JD_1_1_INV); 4088 } 4089 timer_setup(&rt5645->btn_check_timer, rt5645_btn_check_callback, 0); 4090 4091 INIT_DELAYED_WORK(&rt5645->jack_detect_work, rt5645_jack_detect_work); 4092 INIT_DELAYED_WORK(&rt5645->rcclock_work, rt5645_rcclock_work); 4093 4094 if (rt5645->i2c->irq) { 4095 ret = request_threaded_irq(rt5645->i2c->irq, NULL, rt5645_irq, 4096 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING 4097 | IRQF_ONESHOT, "rt5645", rt5645); 4098 if (ret) { 4099 dev_err(&i2c->dev, "Failed to reguest IRQ: %d\n", ret); 4100 goto err_enable; 4101 } 4102 } 4103 4104 ret = devm_snd_soc_register_component(&i2c->dev, &soc_component_dev_rt5645, 4105 rt5645_dai, ARRAY_SIZE(rt5645_dai)); 4106 if (ret) 4107 goto err_irq; 4108 4109 return 0; 4110 4111 err_irq: 4112 if (rt5645->i2c->irq) 4113 free_irq(rt5645->i2c->irq, rt5645); 4114 err_enable: 4115 regulator_bulk_disable(ARRAY_SIZE(rt5645->supplies), rt5645->supplies); 4116 return ret; 4117 } 4118 4119 static int rt5645_i2c_remove(struct i2c_client *i2c) 4120 { 4121 struct rt5645_priv *rt5645 = i2c_get_clientdata(i2c); 4122 4123 if (i2c->irq) 4124 free_irq(i2c->irq, rt5645); 4125 4126 cancel_delayed_work_sync(&rt5645->jack_detect_work); 4127 cancel_delayed_work_sync(&rt5645->rcclock_work); 4128 del_timer_sync(&rt5645->btn_check_timer); 4129 4130 regulator_bulk_disable(ARRAY_SIZE(rt5645->supplies), rt5645->supplies); 4131 4132 return 0; 4133 } 4134 4135 static void rt5645_i2c_shutdown(struct i2c_client *i2c) 4136 { 4137 struct rt5645_priv *rt5645 = i2c_get_clientdata(i2c); 4138 4139 regmap_update_bits(rt5645->regmap, RT5645_GEN_CTRL3, 4140 RT5645_RING2_SLEEVE_GND, RT5645_RING2_SLEEVE_GND); 4141 regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL2, RT5645_CBJ_MN_JD, 4142 RT5645_CBJ_MN_JD); 4143 regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL1, RT5645_CBJ_BST1_EN, 4144 0); 4145 msleep(20); 4146 regmap_write(rt5645->regmap, RT5645_RESET, 0); 4147 } 4148 4149 static struct i2c_driver rt5645_i2c_driver = { 4150 .driver = { 4151 .name = "rt5645", 4152 .of_match_table = of_match_ptr(rt5645_of_match), 4153 .acpi_match_table = ACPI_PTR(rt5645_acpi_match), 4154 }, 4155 .probe = rt5645_i2c_probe, 4156 .remove = rt5645_i2c_remove, 4157 .shutdown = rt5645_i2c_shutdown, 4158 .id_table = rt5645_i2c_id, 4159 }; 4160 module_i2c_driver(rt5645_i2c_driver); 4161 4162 MODULE_DESCRIPTION("ASoC RT5645 driver"); 4163 MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>"); 4164 MODULE_LICENSE("GPL v2"); 4165