1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * rt5645.c -- RT5645 ALSA SoC audio codec driver 4 * 5 * Copyright 2013 Realtek Semiconductor Corp. 6 * Author: Bard Liao <bardliao@realtek.com> 7 */ 8 9 #include <linux/module.h> 10 #include <linux/moduleparam.h> 11 #include <linux/init.h> 12 #include <linux/delay.h> 13 #include <linux/pm.h> 14 #include <linux/i2c.h> 15 #include <linux/platform_device.h> 16 #include <linux/spi/spi.h> 17 #include <linux/gpio/consumer.h> 18 #include <linux/acpi.h> 19 #include <linux/dmi.h> 20 #include <linux/regulator/consumer.h> 21 #include <sound/core.h> 22 #include <sound/pcm.h> 23 #include <sound/pcm_params.h> 24 #include <sound/jack.h> 25 #include <sound/soc.h> 26 #include <sound/soc-dapm.h> 27 #include <sound/initval.h> 28 #include <sound/tlv.h> 29 30 #include "rl6231.h" 31 #include "rt5645.h" 32 33 #define QUIRK_INV_JD1_1(q) ((q) & 1) 34 #define QUIRK_LEVEL_IRQ(q) (((q) >> 1) & 1) 35 #define QUIRK_IN2_DIFF(q) (((q) >> 2) & 1) 36 #define QUIRK_INV_HP_POL(q) (((q) >> 3) & 1) 37 #define QUIRK_JD_MODE(q) (((q) >> 4) & 7) 38 #define QUIRK_DMIC1_DATA_PIN(q) (((q) >> 8) & 3) 39 #define QUIRK_DMIC2_DATA_PIN(q) (((q) >> 12) & 3) 40 41 static unsigned int quirk = -1; 42 module_param(quirk, uint, 0444); 43 MODULE_PARM_DESC(quirk, "RT5645 pdata quirk override"); 44 45 static const struct acpi_gpio_mapping *cht_rt5645_gpios; 46 47 #define RT5645_DEVICE_ID 0x6308 48 #define RT5650_DEVICE_ID 0x6419 49 50 #define RT5645_PR_RANGE_BASE (0xff + 1) 51 #define RT5645_PR_SPACING 0x100 52 53 #define RT5645_PR_BASE (RT5645_PR_RANGE_BASE + (0 * RT5645_PR_SPACING)) 54 55 #define RT5645_HWEQ_NUM 57 56 57 #define TIME_TO_POWER_MS 400 58 59 static const struct regmap_range_cfg rt5645_ranges[] = { 60 { 61 .name = "PR", 62 .range_min = RT5645_PR_BASE, 63 .range_max = RT5645_PR_BASE + 0xf8, 64 .selector_reg = RT5645_PRIV_INDEX, 65 .selector_mask = 0xff, 66 .selector_shift = 0x0, 67 .window_start = RT5645_PRIV_DATA, 68 .window_len = 0x1, 69 }, 70 }; 71 72 static const struct reg_sequence init_list[] = { 73 {RT5645_PR_BASE + 0x3d, 0x3600}, 74 {RT5645_PR_BASE + 0x1c, 0xfd70}, 75 {RT5645_PR_BASE + 0x20, 0x611f}, 76 {RT5645_PR_BASE + 0x21, 0x4040}, 77 {RT5645_PR_BASE + 0x23, 0x0004}, 78 {RT5645_ASRC_4, 0x0120}, 79 }; 80 81 static const struct reg_sequence rt5650_init_list[] = { 82 {0xf6, 0x0100}, 83 }; 84 85 static const struct reg_default rt5645_reg[] = { 86 { 0x00, 0x0000 }, 87 { 0x01, 0xc8c8 }, 88 { 0x02, 0xc8c8 }, 89 { 0x03, 0xc8c8 }, 90 { 0x0a, 0x0002 }, 91 { 0x0b, 0x2827 }, 92 { 0x0c, 0xe000 }, 93 { 0x0d, 0x0000 }, 94 { 0x0e, 0x0000 }, 95 { 0x0f, 0x0808 }, 96 { 0x14, 0x3333 }, 97 { 0x16, 0x4b00 }, 98 { 0x18, 0x018b }, 99 { 0x19, 0xafaf }, 100 { 0x1a, 0xafaf }, 101 { 0x1b, 0x0001 }, 102 { 0x1c, 0x2f2f }, 103 { 0x1d, 0x2f2f }, 104 { 0x1e, 0x0000 }, 105 { 0x20, 0x0000 }, 106 { 0x27, 0x7060 }, 107 { 0x28, 0x7070 }, 108 { 0x29, 0x8080 }, 109 { 0x2a, 0x5656 }, 110 { 0x2b, 0x5454 }, 111 { 0x2c, 0xaaa0 }, 112 { 0x2d, 0x0000 }, 113 { 0x2f, 0x1002 }, 114 { 0x31, 0x5000 }, 115 { 0x32, 0x0000 }, 116 { 0x33, 0x0000 }, 117 { 0x34, 0x0000 }, 118 { 0x35, 0x0000 }, 119 { 0x3b, 0x0000 }, 120 { 0x3c, 0x007f }, 121 { 0x3d, 0x0000 }, 122 { 0x3e, 0x007f }, 123 { 0x3f, 0x0000 }, 124 { 0x40, 0x001f }, 125 { 0x41, 0x0000 }, 126 { 0x42, 0x001f }, 127 { 0x45, 0x6000 }, 128 { 0x46, 0x003e }, 129 { 0x47, 0x003e }, 130 { 0x48, 0xf807 }, 131 { 0x4a, 0x0004 }, 132 { 0x4d, 0x0000 }, 133 { 0x4e, 0x0000 }, 134 { 0x4f, 0x01ff }, 135 { 0x50, 0x0000 }, 136 { 0x51, 0x0000 }, 137 { 0x52, 0x01ff }, 138 { 0x53, 0xf000 }, 139 { 0x56, 0x0111 }, 140 { 0x57, 0x0064 }, 141 { 0x58, 0xef0e }, 142 { 0x59, 0xf0f0 }, 143 { 0x5a, 0xef0e }, 144 { 0x5b, 0xf0f0 }, 145 { 0x5c, 0xef0e }, 146 { 0x5d, 0xf0f0 }, 147 { 0x5e, 0xf000 }, 148 { 0x5f, 0x0000 }, 149 { 0x61, 0x0300 }, 150 { 0x62, 0x0000 }, 151 { 0x63, 0x00c2 }, 152 { 0x64, 0x0000 }, 153 { 0x65, 0x0000 }, 154 { 0x66, 0x0000 }, 155 { 0x6a, 0x0000 }, 156 { 0x6c, 0x0aaa }, 157 { 0x70, 0x8000 }, 158 { 0x71, 0x8000 }, 159 { 0x72, 0x8000 }, 160 { 0x73, 0x7770 }, 161 { 0x74, 0x3e00 }, 162 { 0x75, 0x2409 }, 163 { 0x76, 0x000a }, 164 { 0x77, 0x0c00 }, 165 { 0x78, 0x0000 }, 166 { 0x79, 0x0123 }, 167 { 0x80, 0x0000 }, 168 { 0x81, 0x0000 }, 169 { 0x82, 0x0000 }, 170 { 0x83, 0x0000 }, 171 { 0x84, 0x0000 }, 172 { 0x85, 0x0000 }, 173 { 0x8a, 0x0120 }, 174 { 0x8e, 0x0004 }, 175 { 0x8f, 0x1100 }, 176 { 0x90, 0x0646 }, 177 { 0x91, 0x0c06 }, 178 { 0x93, 0x0000 }, 179 { 0x94, 0x0200 }, 180 { 0x95, 0x0000 }, 181 { 0x9a, 0x2184 }, 182 { 0x9b, 0x010a }, 183 { 0x9c, 0x0aea }, 184 { 0x9d, 0x000c }, 185 { 0x9e, 0x0400 }, 186 { 0xa0, 0xa0a8 }, 187 { 0xa1, 0x0059 }, 188 { 0xa2, 0x0001 }, 189 { 0xae, 0x6000 }, 190 { 0xaf, 0x0000 }, 191 { 0xb0, 0x6000 }, 192 { 0xb1, 0x0000 }, 193 { 0xb2, 0x0000 }, 194 { 0xb3, 0x001f }, 195 { 0xb4, 0x020c }, 196 { 0xb5, 0x1f00 }, 197 { 0xb6, 0x0000 }, 198 { 0xbb, 0x0000 }, 199 { 0xbc, 0x0000 }, 200 { 0xbd, 0x0000 }, 201 { 0xbe, 0x0000 }, 202 { 0xbf, 0x3100 }, 203 { 0xc0, 0x0000 }, 204 { 0xc1, 0x0000 }, 205 { 0xc2, 0x0000 }, 206 { 0xc3, 0x2000 }, 207 { 0xcd, 0x0000 }, 208 { 0xce, 0x0000 }, 209 { 0xcf, 0x1813 }, 210 { 0xd0, 0x0690 }, 211 { 0xd1, 0x1c17 }, 212 { 0xd3, 0xb320 }, 213 { 0xd4, 0x0000 }, 214 { 0xd6, 0x0400 }, 215 { 0xd9, 0x0809 }, 216 { 0xda, 0x0000 }, 217 { 0xdb, 0x0003 }, 218 { 0xdc, 0x0049 }, 219 { 0xdd, 0x001b }, 220 { 0xdf, 0x0008 }, 221 { 0xe0, 0x4000 }, 222 { 0xe6, 0x8000 }, 223 { 0xe7, 0x0200 }, 224 { 0xec, 0xb300 }, 225 { 0xed, 0x0000 }, 226 { 0xf0, 0x001f }, 227 { 0xf1, 0x020c }, 228 { 0xf2, 0x1f00 }, 229 { 0xf3, 0x0000 }, 230 { 0xf4, 0x4000 }, 231 { 0xf8, 0x0000 }, 232 { 0xf9, 0x0000 }, 233 { 0xfa, 0x2060 }, 234 { 0xfb, 0x4040 }, 235 { 0xfc, 0x0000 }, 236 { 0xfd, 0x0002 }, 237 { 0xfe, 0x10ec }, 238 { 0xff, 0x6308 }, 239 }; 240 241 static const struct reg_default rt5650_reg[] = { 242 { 0x00, 0x0000 }, 243 { 0x01, 0xc8c8 }, 244 { 0x02, 0xc8c8 }, 245 { 0x03, 0xc8c8 }, 246 { 0x0a, 0x0002 }, 247 { 0x0b, 0x2827 }, 248 { 0x0c, 0xe000 }, 249 { 0x0d, 0x0000 }, 250 { 0x0e, 0x0000 }, 251 { 0x0f, 0x0808 }, 252 { 0x14, 0x3333 }, 253 { 0x16, 0x4b00 }, 254 { 0x18, 0x018b }, 255 { 0x19, 0xafaf }, 256 { 0x1a, 0xafaf }, 257 { 0x1b, 0x0001 }, 258 { 0x1c, 0x2f2f }, 259 { 0x1d, 0x2f2f }, 260 { 0x1e, 0x0000 }, 261 { 0x20, 0x0000 }, 262 { 0x27, 0x7060 }, 263 { 0x28, 0x7070 }, 264 { 0x29, 0x8080 }, 265 { 0x2a, 0x5656 }, 266 { 0x2b, 0x5454 }, 267 { 0x2c, 0xaaa0 }, 268 { 0x2d, 0x0000 }, 269 { 0x2f, 0x5002 }, 270 { 0x31, 0x5000 }, 271 { 0x32, 0x0000 }, 272 { 0x33, 0x0000 }, 273 { 0x34, 0x0000 }, 274 { 0x35, 0x0000 }, 275 { 0x3b, 0x0000 }, 276 { 0x3c, 0x007f }, 277 { 0x3d, 0x0000 }, 278 { 0x3e, 0x007f }, 279 { 0x3f, 0x0000 }, 280 { 0x40, 0x001f }, 281 { 0x41, 0x0000 }, 282 { 0x42, 0x001f }, 283 { 0x45, 0x6000 }, 284 { 0x46, 0x003e }, 285 { 0x47, 0x003e }, 286 { 0x48, 0xf807 }, 287 { 0x4a, 0x0004 }, 288 { 0x4d, 0x0000 }, 289 { 0x4e, 0x0000 }, 290 { 0x4f, 0x01ff }, 291 { 0x50, 0x0000 }, 292 { 0x51, 0x0000 }, 293 { 0x52, 0x01ff }, 294 { 0x53, 0xf000 }, 295 { 0x56, 0x0111 }, 296 { 0x57, 0x0064 }, 297 { 0x58, 0xef0e }, 298 { 0x59, 0xf0f0 }, 299 { 0x5a, 0xef0e }, 300 { 0x5b, 0xf0f0 }, 301 { 0x5c, 0xef0e }, 302 { 0x5d, 0xf0f0 }, 303 { 0x5e, 0xf000 }, 304 { 0x5f, 0x0000 }, 305 { 0x61, 0x0300 }, 306 { 0x62, 0x0000 }, 307 { 0x63, 0x00c2 }, 308 { 0x64, 0x0000 }, 309 { 0x65, 0x0000 }, 310 { 0x66, 0x0000 }, 311 { 0x6a, 0x0000 }, 312 { 0x6c, 0x0aaa }, 313 { 0x70, 0x8000 }, 314 { 0x71, 0x8000 }, 315 { 0x72, 0x8000 }, 316 { 0x73, 0x7770 }, 317 { 0x74, 0x3e00 }, 318 { 0x75, 0x2409 }, 319 { 0x76, 0x000a }, 320 { 0x77, 0x0c00 }, 321 { 0x78, 0x0000 }, 322 { 0x79, 0x0123 }, 323 { 0x7a, 0x0123 }, 324 { 0x80, 0x0000 }, 325 { 0x81, 0x0000 }, 326 { 0x82, 0x0000 }, 327 { 0x83, 0x0000 }, 328 { 0x84, 0x0000 }, 329 { 0x85, 0x0000 }, 330 { 0x8a, 0x0120 }, 331 { 0x8e, 0x0004 }, 332 { 0x8f, 0x1100 }, 333 { 0x90, 0x0646 }, 334 { 0x91, 0x0c06 }, 335 { 0x93, 0x0000 }, 336 { 0x94, 0x0200 }, 337 { 0x95, 0x0000 }, 338 { 0x9a, 0x2184 }, 339 { 0x9b, 0x010a }, 340 { 0x9c, 0x0aea }, 341 { 0x9d, 0x000c }, 342 { 0x9e, 0x0400 }, 343 { 0xa0, 0xa0a8 }, 344 { 0xa1, 0x0059 }, 345 { 0xa2, 0x0001 }, 346 { 0xae, 0x6000 }, 347 { 0xaf, 0x0000 }, 348 { 0xb0, 0x6000 }, 349 { 0xb1, 0x0000 }, 350 { 0xb2, 0x0000 }, 351 { 0xb3, 0x001f }, 352 { 0xb4, 0x020c }, 353 { 0xb5, 0x1f00 }, 354 { 0xb6, 0x0000 }, 355 { 0xbb, 0x0000 }, 356 { 0xbc, 0x0000 }, 357 { 0xbd, 0x0000 }, 358 { 0xbe, 0x0000 }, 359 { 0xbf, 0x3100 }, 360 { 0xc0, 0x0000 }, 361 { 0xc1, 0x0000 }, 362 { 0xc2, 0x0000 }, 363 { 0xc3, 0x2000 }, 364 { 0xcd, 0x0000 }, 365 { 0xce, 0x0000 }, 366 { 0xcf, 0x1813 }, 367 { 0xd0, 0x0690 }, 368 { 0xd1, 0x1c17 }, 369 { 0xd3, 0xb320 }, 370 { 0xd4, 0x0000 }, 371 { 0xd6, 0x0400 }, 372 { 0xd9, 0x0809 }, 373 { 0xda, 0x0000 }, 374 { 0xdb, 0x0003 }, 375 { 0xdc, 0x0049 }, 376 { 0xdd, 0x001b }, 377 { 0xdf, 0x0008 }, 378 { 0xe0, 0x4000 }, 379 { 0xe6, 0x8000 }, 380 { 0xe7, 0x0200 }, 381 { 0xec, 0xb300 }, 382 { 0xed, 0x0000 }, 383 { 0xf0, 0x001f }, 384 { 0xf1, 0x020c }, 385 { 0xf2, 0x1f00 }, 386 { 0xf3, 0x0000 }, 387 { 0xf4, 0x4000 }, 388 { 0xf8, 0x0000 }, 389 { 0xf9, 0x0000 }, 390 { 0xfa, 0x2060 }, 391 { 0xfb, 0x4040 }, 392 { 0xfc, 0x0000 }, 393 { 0xfd, 0x0002 }, 394 { 0xfe, 0x10ec }, 395 { 0xff, 0x6308 }, 396 }; 397 398 struct rt5645_eq_param_s { 399 unsigned short reg; 400 unsigned short val; 401 }; 402 403 struct rt5645_eq_param_s_be16 { 404 __be16 reg; 405 __be16 val; 406 }; 407 408 static const char *const rt5645_supply_names[] = { 409 "avdd", 410 "cpvdd", 411 }; 412 413 struct rt5645_platform_data { 414 /* IN2 can optionally be differential */ 415 bool in2_diff; 416 417 unsigned int dmic1_data_pin; 418 /* 0 = IN2N; 1 = GPIO5; 2 = GPIO11 */ 419 unsigned int dmic2_data_pin; 420 /* 0 = IN2P; 1 = GPIO6; 2 = GPIO10; 3 = GPIO12 */ 421 422 unsigned int jd_mode; 423 /* Use level triggered irq */ 424 bool level_trigger_irq; 425 /* Invert JD1_1 status polarity */ 426 bool inv_jd1_1; 427 /* Invert HP detect status polarity */ 428 bool inv_hp_pol; 429 430 /* Value to assign to snd_soc_card.long_name */ 431 const char *long_name; 432 433 /* Some (package) variants have the headset-mic pin not-connected */ 434 bool no_headset_mic; 435 }; 436 437 struct rt5645_priv { 438 struct snd_soc_component *component; 439 struct rt5645_platform_data pdata; 440 struct regmap *regmap; 441 struct i2c_client *i2c; 442 struct gpio_desc *gpiod_hp_det; 443 struct snd_soc_jack *hp_jack; 444 struct snd_soc_jack *mic_jack; 445 struct snd_soc_jack *btn_jack; 446 struct delayed_work jack_detect_work, rcclock_work; 447 struct regulator_bulk_data supplies[ARRAY_SIZE(rt5645_supply_names)]; 448 struct rt5645_eq_param_s *eq_param; 449 struct timer_list btn_check_timer; 450 451 int codec_type; 452 int sysclk; 453 int sysclk_src; 454 int lrck[RT5645_AIFS]; 455 int bclk[RT5645_AIFS]; 456 int master[RT5645_AIFS]; 457 458 int pll_src; 459 int pll_in; 460 int pll_out; 461 462 int jack_type; 463 bool en_button_func; 464 int v_id; 465 }; 466 467 static int rt5645_reset(struct snd_soc_component *component) 468 { 469 return snd_soc_component_write(component, RT5645_RESET, 0); 470 } 471 472 static bool rt5645_volatile_register(struct device *dev, unsigned int reg) 473 { 474 int i; 475 476 for (i = 0; i < ARRAY_SIZE(rt5645_ranges); i++) { 477 if (reg >= rt5645_ranges[i].range_min && 478 reg <= rt5645_ranges[i].range_max) { 479 return true; 480 } 481 } 482 483 switch (reg) { 484 case RT5645_RESET: 485 case RT5645_PRIV_INDEX: 486 case RT5645_PRIV_DATA: 487 case RT5645_IN1_CTRL1: 488 case RT5645_IN1_CTRL2: 489 case RT5645_IN1_CTRL3: 490 case RT5645_A_JD_CTRL1: 491 case RT5645_ADC_EQ_CTRL1: 492 case RT5645_EQ_CTRL1: 493 case RT5645_ALC_CTRL_1: 494 case RT5645_IRQ_CTRL2: 495 case RT5645_IRQ_CTRL3: 496 case RT5645_INT_IRQ_ST: 497 case RT5645_IL_CMD: 498 case RT5650_4BTN_IL_CMD1: 499 case RT5645_VENDOR_ID: 500 case RT5645_VENDOR_ID1: 501 case RT5645_VENDOR_ID2: 502 return true; 503 default: 504 return false; 505 } 506 } 507 508 static bool rt5645_readable_register(struct device *dev, unsigned int reg) 509 { 510 int i; 511 512 for (i = 0; i < ARRAY_SIZE(rt5645_ranges); i++) { 513 if (reg >= rt5645_ranges[i].range_min && 514 reg <= rt5645_ranges[i].range_max) { 515 return true; 516 } 517 } 518 519 switch (reg) { 520 case RT5645_RESET: 521 case RT5645_SPK_VOL: 522 case RT5645_HP_VOL: 523 case RT5645_LOUT1: 524 case RT5645_IN1_CTRL1: 525 case RT5645_IN1_CTRL2: 526 case RT5645_IN1_CTRL3: 527 case RT5645_IN2_CTRL: 528 case RT5645_INL1_INR1_VOL: 529 case RT5645_SPK_FUNC_LIM: 530 case RT5645_ADJ_HPF_CTRL: 531 case RT5645_DAC1_DIG_VOL: 532 case RT5645_DAC2_DIG_VOL: 533 case RT5645_DAC_CTRL: 534 case RT5645_STO1_ADC_DIG_VOL: 535 case RT5645_MONO_ADC_DIG_VOL: 536 case RT5645_ADC_BST_VOL1: 537 case RT5645_ADC_BST_VOL2: 538 case RT5645_STO1_ADC_MIXER: 539 case RT5645_MONO_ADC_MIXER: 540 case RT5645_AD_DA_MIXER: 541 case RT5645_STO_DAC_MIXER: 542 case RT5645_MONO_DAC_MIXER: 543 case RT5645_DIG_MIXER: 544 case RT5650_A_DAC_SOUR: 545 case RT5645_DIG_INF1_DATA: 546 case RT5645_PDM_OUT_CTRL: 547 case RT5645_REC_L1_MIXER: 548 case RT5645_REC_L2_MIXER: 549 case RT5645_REC_R1_MIXER: 550 case RT5645_REC_R2_MIXER: 551 case RT5645_HPMIXL_CTRL: 552 case RT5645_HPOMIXL_CTRL: 553 case RT5645_HPMIXR_CTRL: 554 case RT5645_HPOMIXR_CTRL: 555 case RT5645_HPO_MIXER: 556 case RT5645_SPK_L_MIXER: 557 case RT5645_SPK_R_MIXER: 558 case RT5645_SPO_MIXER: 559 case RT5645_SPO_CLSD_RATIO: 560 case RT5645_OUT_L1_MIXER: 561 case RT5645_OUT_R1_MIXER: 562 case RT5645_OUT_L_GAIN1: 563 case RT5645_OUT_L_GAIN2: 564 case RT5645_OUT_R_GAIN1: 565 case RT5645_OUT_R_GAIN2: 566 case RT5645_LOUT_MIXER: 567 case RT5645_HAPTIC_CTRL1: 568 case RT5645_HAPTIC_CTRL2: 569 case RT5645_HAPTIC_CTRL3: 570 case RT5645_HAPTIC_CTRL4: 571 case RT5645_HAPTIC_CTRL5: 572 case RT5645_HAPTIC_CTRL6: 573 case RT5645_HAPTIC_CTRL7: 574 case RT5645_HAPTIC_CTRL8: 575 case RT5645_HAPTIC_CTRL9: 576 case RT5645_HAPTIC_CTRL10: 577 case RT5645_PWR_DIG1: 578 case RT5645_PWR_DIG2: 579 case RT5645_PWR_ANLG1: 580 case RT5645_PWR_ANLG2: 581 case RT5645_PWR_MIXER: 582 case RT5645_PWR_VOL: 583 case RT5645_PRIV_INDEX: 584 case RT5645_PRIV_DATA: 585 case RT5645_I2S1_SDP: 586 case RT5645_I2S2_SDP: 587 case RT5645_ADDA_CLK1: 588 case RT5645_ADDA_CLK2: 589 case RT5645_DMIC_CTRL1: 590 case RT5645_DMIC_CTRL2: 591 case RT5645_TDM_CTRL_1: 592 case RT5645_TDM_CTRL_2: 593 case RT5645_TDM_CTRL_3: 594 case RT5650_TDM_CTRL_4: 595 case RT5645_GLB_CLK: 596 case RT5645_PLL_CTRL1: 597 case RT5645_PLL_CTRL2: 598 case RT5645_ASRC_1: 599 case RT5645_ASRC_2: 600 case RT5645_ASRC_3: 601 case RT5645_ASRC_4: 602 case RT5645_DEPOP_M1: 603 case RT5645_DEPOP_M2: 604 case RT5645_DEPOP_M3: 605 case RT5645_CHARGE_PUMP: 606 case RT5645_MICBIAS: 607 case RT5645_A_JD_CTRL1: 608 case RT5645_VAD_CTRL4: 609 case RT5645_CLSD_OUT_CTRL: 610 case RT5645_ADC_EQ_CTRL1: 611 case RT5645_ADC_EQ_CTRL2: 612 case RT5645_EQ_CTRL1: 613 case RT5645_EQ_CTRL2: 614 case RT5645_ALC_CTRL_1: 615 case RT5645_ALC_CTRL_2: 616 case RT5645_ALC_CTRL_3: 617 case RT5645_ALC_CTRL_4: 618 case RT5645_ALC_CTRL_5: 619 case RT5645_JD_CTRL: 620 case RT5645_IRQ_CTRL1: 621 case RT5645_IRQ_CTRL2: 622 case RT5645_IRQ_CTRL3: 623 case RT5645_INT_IRQ_ST: 624 case RT5645_GPIO_CTRL1: 625 case RT5645_GPIO_CTRL2: 626 case RT5645_GPIO_CTRL3: 627 case RT5645_BASS_BACK: 628 case RT5645_MP3_PLUS1: 629 case RT5645_MP3_PLUS2: 630 case RT5645_ADJ_HPF1: 631 case RT5645_ADJ_HPF2: 632 case RT5645_HP_CALIB_AMP_DET: 633 case RT5645_SV_ZCD1: 634 case RT5645_SV_ZCD2: 635 case RT5645_IL_CMD: 636 case RT5645_IL_CMD2: 637 case RT5645_IL_CMD3: 638 case RT5650_4BTN_IL_CMD1: 639 case RT5650_4BTN_IL_CMD2: 640 case RT5645_DRC1_HL_CTRL1: 641 case RT5645_DRC2_HL_CTRL1: 642 case RT5645_ADC_MONO_HP_CTRL1: 643 case RT5645_ADC_MONO_HP_CTRL2: 644 case RT5645_DRC2_CTRL1: 645 case RT5645_DRC2_CTRL2: 646 case RT5645_DRC2_CTRL3: 647 case RT5645_DRC2_CTRL4: 648 case RT5645_DRC2_CTRL5: 649 case RT5645_JD_CTRL3: 650 case RT5645_JD_CTRL4: 651 case RT5645_GEN_CTRL1: 652 case RT5645_GEN_CTRL2: 653 case RT5645_GEN_CTRL3: 654 case RT5645_VENDOR_ID: 655 case RT5645_VENDOR_ID1: 656 case RT5645_VENDOR_ID2: 657 return true; 658 default: 659 return false; 660 } 661 } 662 663 static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -4650, 150, 0); 664 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6525, 75, 0); 665 static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -3450, 150, 0); 666 static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0); 667 static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0); 668 669 /* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */ 670 static const DECLARE_TLV_DB_RANGE(bst_tlv, 671 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0), 672 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0), 673 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0), 674 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0), 675 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0), 676 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0), 677 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0) 678 ); 679 680 /* {-6, -4.5, -3, -1.5, 0, 0.82, 1.58, 2.28} dB */ 681 static const DECLARE_TLV_DB_RANGE(spk_clsd_tlv, 682 0, 4, TLV_DB_SCALE_ITEM(-600, 150, 0), 683 5, 5, TLV_DB_SCALE_ITEM(82, 0, 0), 684 6, 6, TLV_DB_SCALE_ITEM(158, 0, 0), 685 7, 7, TLV_DB_SCALE_ITEM(228, 0, 0) 686 ); 687 688 static int rt5645_hweq_info(struct snd_kcontrol *kcontrol, 689 struct snd_ctl_elem_info *uinfo) 690 { 691 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES; 692 uinfo->count = RT5645_HWEQ_NUM * sizeof(struct rt5645_eq_param_s); 693 694 return 0; 695 } 696 697 static int rt5645_hweq_get(struct snd_kcontrol *kcontrol, 698 struct snd_ctl_elem_value *ucontrol) 699 { 700 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 701 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component); 702 struct rt5645_eq_param_s_be16 *eq_param = 703 (struct rt5645_eq_param_s_be16 *)ucontrol->value.bytes.data; 704 int i; 705 706 for (i = 0; i < RT5645_HWEQ_NUM; i++) { 707 eq_param[i].reg = cpu_to_be16(rt5645->eq_param[i].reg); 708 eq_param[i].val = cpu_to_be16(rt5645->eq_param[i].val); 709 } 710 711 return 0; 712 } 713 714 static bool rt5645_validate_hweq(unsigned short reg) 715 { 716 if ((reg >= 0x1a4 && reg <= 0x1cd) || (reg >= 0x1e5 && reg <= 0x1f8) || 717 (reg == RT5645_EQ_CTRL2)) 718 return true; 719 720 return false; 721 } 722 723 static int rt5645_hweq_put(struct snd_kcontrol *kcontrol, 724 struct snd_ctl_elem_value *ucontrol) 725 { 726 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 727 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component); 728 struct rt5645_eq_param_s_be16 *eq_param = 729 (struct rt5645_eq_param_s_be16 *)ucontrol->value.bytes.data; 730 int i; 731 732 for (i = 0; i < RT5645_HWEQ_NUM; i++) { 733 rt5645->eq_param[i].reg = be16_to_cpu(eq_param[i].reg); 734 rt5645->eq_param[i].val = be16_to_cpu(eq_param[i].val); 735 } 736 737 /* The final setting of the table should be RT5645_EQ_CTRL2 */ 738 for (i = RT5645_HWEQ_NUM - 1; i >= 0; i--) { 739 if (rt5645->eq_param[i].reg == 0) 740 continue; 741 else if (rt5645->eq_param[i].reg != RT5645_EQ_CTRL2) 742 return 0; 743 else 744 break; 745 } 746 747 for (i = 0; i < RT5645_HWEQ_NUM; i++) { 748 if (!rt5645_validate_hweq(rt5645->eq_param[i].reg) && 749 rt5645->eq_param[i].reg != 0) 750 return 0; 751 else if (rt5645->eq_param[i].reg == 0) 752 break; 753 } 754 755 return 0; 756 } 757 758 #define RT5645_HWEQ(xname) \ 759 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 760 .info = rt5645_hweq_info, \ 761 .get = rt5645_hweq_get, \ 762 .put = rt5645_hweq_put \ 763 } 764 765 static int rt5645_spk_put_volsw(struct snd_kcontrol *kcontrol, 766 struct snd_ctl_elem_value *ucontrol) 767 { 768 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 769 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component); 770 int ret; 771 772 regmap_update_bits(rt5645->regmap, RT5645_MICBIAS, 773 RT5645_PWR_CLK25M_MASK, RT5645_PWR_CLK25M_PU); 774 775 ret = snd_soc_put_volsw(kcontrol, ucontrol); 776 777 mod_delayed_work(system_power_efficient_wq, &rt5645->rcclock_work, 778 msecs_to_jiffies(200)); 779 780 return ret; 781 } 782 783 static const char * const rt5645_dac1_vol_ctrl_mode_text[] = { 784 "immediately", "zero crossing", "soft ramp" 785 }; 786 787 static SOC_ENUM_SINGLE_DECL( 788 rt5645_dac1_vol_ctrl_mode, RT5645_PR_BASE, 789 RT5645_DA1_ZDET_SFT, rt5645_dac1_vol_ctrl_mode_text); 790 791 static const struct snd_kcontrol_new rt5645_snd_controls[] = { 792 /* Speaker Output Volume */ 793 SOC_DOUBLE("Speaker Channel Switch", RT5645_SPK_VOL, 794 RT5645_VOL_L_SFT, RT5645_VOL_R_SFT, 1, 1), 795 SOC_DOUBLE_EXT_TLV("Speaker Playback Volume", RT5645_SPK_VOL, 796 RT5645_L_VOL_SFT, RT5645_R_VOL_SFT, 39, 1, snd_soc_get_volsw, 797 rt5645_spk_put_volsw, out_vol_tlv), 798 799 /* ClassD modulator Speaker Gain Ratio */ 800 SOC_SINGLE_TLV("Speaker ClassD Playback Volume", RT5645_SPO_CLSD_RATIO, 801 RT5645_SPK_G_CLSD_SFT, 7, 0, spk_clsd_tlv), 802 803 /* Headphone Output Volume */ 804 SOC_DOUBLE("Headphone Channel Switch", RT5645_HP_VOL, 805 RT5645_VOL_L_SFT, RT5645_VOL_R_SFT, 1, 1), 806 SOC_DOUBLE_TLV("Headphone Playback Volume", RT5645_HP_VOL, 807 RT5645_L_VOL_SFT, RT5645_R_VOL_SFT, 39, 1, out_vol_tlv), 808 809 /* OUTPUT Control */ 810 SOC_DOUBLE("OUT Playback Switch", RT5645_LOUT1, 811 RT5645_L_MUTE_SFT, RT5645_R_MUTE_SFT, 1, 1), 812 SOC_DOUBLE("OUT Channel Switch", RT5645_LOUT1, 813 RT5645_VOL_L_SFT, RT5645_VOL_R_SFT, 1, 1), 814 SOC_DOUBLE_TLV("OUT Playback Volume", RT5645_LOUT1, 815 RT5645_L_VOL_SFT, RT5645_R_VOL_SFT, 39, 1, out_vol_tlv), 816 817 /* DAC Digital Volume */ 818 SOC_DOUBLE("DAC2 Playback Switch", RT5645_DAC_CTRL, 819 RT5645_M_DAC_L2_VOL_SFT, RT5645_M_DAC_R2_VOL_SFT, 1, 1), 820 SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5645_DAC1_DIG_VOL, 821 RT5645_L_VOL_SFT + 1, RT5645_R_VOL_SFT + 1, 87, 0, dac_vol_tlv), 822 SOC_DOUBLE_TLV("Mono DAC Playback Volume", RT5645_DAC2_DIG_VOL, 823 RT5645_L_VOL_SFT + 1, RT5645_R_VOL_SFT + 1, 87, 0, dac_vol_tlv), 824 825 /* IN1/IN2 Control */ 826 SOC_SINGLE_TLV("IN1 Boost", RT5645_IN1_CTRL1, 827 RT5645_BST_SFT1, 12, 0, bst_tlv), 828 SOC_SINGLE_TLV("IN2 Boost", RT5645_IN2_CTRL, 829 RT5645_BST_SFT2, 8, 0, bst_tlv), 830 831 /* INL/INR Volume Control */ 832 SOC_DOUBLE_TLV("IN Capture Volume", RT5645_INL1_INR1_VOL, 833 RT5645_INL_VOL_SFT, RT5645_INR_VOL_SFT, 31, 1, in_vol_tlv), 834 835 /* ADC Digital Volume Control */ 836 SOC_DOUBLE("ADC Capture Switch", RT5645_STO1_ADC_DIG_VOL, 837 RT5645_L_MUTE_SFT, RT5645_R_MUTE_SFT, 1, 1), 838 SOC_DOUBLE_TLV("ADC Capture Volume", RT5645_STO1_ADC_DIG_VOL, 839 RT5645_L_VOL_SFT + 1, RT5645_R_VOL_SFT + 1, 63, 0, adc_vol_tlv), 840 SOC_DOUBLE("Mono ADC Capture Switch", RT5645_MONO_ADC_DIG_VOL, 841 RT5645_L_MUTE_SFT, RT5645_R_MUTE_SFT, 1, 1), 842 SOC_DOUBLE_TLV("Mono ADC Capture Volume", RT5645_MONO_ADC_DIG_VOL, 843 RT5645_L_VOL_SFT + 1, RT5645_R_VOL_SFT + 1, 63, 0, adc_vol_tlv), 844 845 /* ADC Boost Volume Control */ 846 SOC_DOUBLE_TLV("ADC Boost Capture Volume", RT5645_ADC_BST_VOL1, 847 RT5645_STO1_ADC_L_BST_SFT, RT5645_STO1_ADC_R_BST_SFT, 3, 0, 848 adc_bst_tlv), 849 SOC_DOUBLE_TLV("Mono ADC Boost Capture Volume", RT5645_ADC_BST_VOL2, 850 RT5645_MONO_ADC_L_BST_SFT, RT5645_MONO_ADC_R_BST_SFT, 3, 0, 851 adc_bst_tlv), 852 853 /* I2S2 function select */ 854 SOC_SINGLE("I2S2 Func Switch", RT5645_GPIO_CTRL1, RT5645_I2S2_SEL_SFT, 855 1, 1), 856 RT5645_HWEQ("Speaker HWEQ"), 857 858 /* Digital Soft Volume Control */ 859 SOC_ENUM("DAC1 Digital Volume Control Func", rt5645_dac1_vol_ctrl_mode), 860 }; 861 862 /** 863 * set_dmic_clk - Set parameter of dmic. 864 * 865 * @w: DAPM widget. 866 * @kcontrol: The kcontrol of this widget. 867 * @event: Event id. 868 * 869 */ 870 static int set_dmic_clk(struct snd_soc_dapm_widget *w, 871 struct snd_kcontrol *kcontrol, int event) 872 { 873 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 874 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component); 875 int idx, rate; 876 877 rate = rt5645->sysclk / rl6231_get_pre_div(rt5645->regmap, 878 RT5645_ADDA_CLK1, RT5645_I2S_PD1_SFT); 879 idx = rl6231_calc_dmic_clk(rate); 880 if (idx < 0) 881 dev_err(component->dev, "Failed to set DMIC clock\n"); 882 else 883 snd_soc_component_update_bits(component, RT5645_DMIC_CTRL1, 884 RT5645_DMIC_CLK_MASK, idx << RT5645_DMIC_CLK_SFT); 885 return idx; 886 } 887 888 static int is_sys_clk_from_pll(struct snd_soc_dapm_widget *source, 889 struct snd_soc_dapm_widget *sink) 890 { 891 struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm); 892 unsigned int val; 893 894 val = snd_soc_component_read(component, RT5645_GLB_CLK); 895 val &= RT5645_SCLK_SRC_MASK; 896 if (val == RT5645_SCLK_SRC_PLL1) 897 return 1; 898 else 899 return 0; 900 } 901 902 static int is_using_asrc(struct snd_soc_dapm_widget *source, 903 struct snd_soc_dapm_widget *sink) 904 { 905 struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm); 906 unsigned int reg, shift, val; 907 908 switch (source->shift) { 909 case 0: 910 reg = RT5645_ASRC_3; 911 shift = 0; 912 break; 913 case 1: 914 reg = RT5645_ASRC_3; 915 shift = 4; 916 break; 917 case 3: 918 reg = RT5645_ASRC_2; 919 shift = 0; 920 break; 921 case 8: 922 reg = RT5645_ASRC_2; 923 shift = 4; 924 break; 925 case 9: 926 reg = RT5645_ASRC_2; 927 shift = 8; 928 break; 929 case 10: 930 reg = RT5645_ASRC_2; 931 shift = 12; 932 break; 933 default: 934 return 0; 935 } 936 937 val = (snd_soc_component_read(component, reg) >> shift) & 0xf; 938 switch (val) { 939 case 1: 940 case 2: 941 case 3: 942 case 4: 943 return 1; 944 default: 945 return 0; 946 } 947 948 } 949 950 static int rt5645_enable_hweq(struct snd_soc_component *component) 951 { 952 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component); 953 int i; 954 955 for (i = 0; i < RT5645_HWEQ_NUM; i++) { 956 if (rt5645_validate_hweq(rt5645->eq_param[i].reg)) 957 regmap_write(rt5645->regmap, rt5645->eq_param[i].reg, 958 rt5645->eq_param[i].val); 959 else 960 break; 961 } 962 963 return 0; 964 } 965 966 /** 967 * rt5645_sel_asrc_clk_src - select ASRC clock source for a set of filters 968 * @component: SoC audio component device. 969 * @filter_mask: mask of filters. 970 * @clk_src: clock source 971 * 972 * The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5645 can 973 * only support standard 32fs or 64fs i2s format, ASRC should be enabled to 974 * support special i2s clock format such as Intel's 100fs(100 * sampling rate). 975 * ASRC function will track i2s clock and generate a corresponding system clock 976 * for codec. This function provides an API to select the clock source for a 977 * set of filters specified by the mask. And the codec driver will turn on ASRC 978 * for these filters if ASRC is selected as their clock source. 979 */ 980 int rt5645_sel_asrc_clk_src(struct snd_soc_component *component, 981 unsigned int filter_mask, unsigned int clk_src) 982 { 983 unsigned int asrc2_mask = 0; 984 unsigned int asrc2_value = 0; 985 unsigned int asrc3_mask = 0; 986 unsigned int asrc3_value = 0; 987 988 switch (clk_src) { 989 case RT5645_CLK_SEL_SYS: 990 case RT5645_CLK_SEL_I2S1_ASRC: 991 case RT5645_CLK_SEL_I2S2_ASRC: 992 case RT5645_CLK_SEL_SYS2: 993 break; 994 995 default: 996 return -EINVAL; 997 } 998 999 if (filter_mask & RT5645_DA_STEREO_FILTER) { 1000 asrc2_mask |= RT5645_DA_STO_CLK_SEL_MASK; 1001 asrc2_value = (asrc2_value & ~RT5645_DA_STO_CLK_SEL_MASK) 1002 | (clk_src << RT5645_DA_STO_CLK_SEL_SFT); 1003 } 1004 1005 if (filter_mask & RT5645_DA_MONO_L_FILTER) { 1006 asrc2_mask |= RT5645_DA_MONOL_CLK_SEL_MASK; 1007 asrc2_value = (asrc2_value & ~RT5645_DA_MONOL_CLK_SEL_MASK) 1008 | (clk_src << RT5645_DA_MONOL_CLK_SEL_SFT); 1009 } 1010 1011 if (filter_mask & RT5645_DA_MONO_R_FILTER) { 1012 asrc2_mask |= RT5645_DA_MONOR_CLK_SEL_MASK; 1013 asrc2_value = (asrc2_value & ~RT5645_DA_MONOR_CLK_SEL_MASK) 1014 | (clk_src << RT5645_DA_MONOR_CLK_SEL_SFT); 1015 } 1016 1017 if (filter_mask & RT5645_AD_STEREO_FILTER) { 1018 asrc2_mask |= RT5645_AD_STO1_CLK_SEL_MASK; 1019 asrc2_value = (asrc2_value & ~RT5645_AD_STO1_CLK_SEL_MASK) 1020 | (clk_src << RT5645_AD_STO1_CLK_SEL_SFT); 1021 } 1022 1023 if (filter_mask & RT5645_AD_MONO_L_FILTER) { 1024 asrc3_mask |= RT5645_AD_MONOL_CLK_SEL_MASK; 1025 asrc3_value = (asrc3_value & ~RT5645_AD_MONOL_CLK_SEL_MASK) 1026 | (clk_src << RT5645_AD_MONOL_CLK_SEL_SFT); 1027 } 1028 1029 if (filter_mask & RT5645_AD_MONO_R_FILTER) { 1030 asrc3_mask |= RT5645_AD_MONOR_CLK_SEL_MASK; 1031 asrc3_value = (asrc3_value & ~RT5645_AD_MONOR_CLK_SEL_MASK) 1032 | (clk_src << RT5645_AD_MONOR_CLK_SEL_SFT); 1033 } 1034 1035 if (asrc2_mask) 1036 snd_soc_component_update_bits(component, RT5645_ASRC_2, 1037 asrc2_mask, asrc2_value); 1038 1039 if (asrc3_mask) 1040 snd_soc_component_update_bits(component, RT5645_ASRC_3, 1041 asrc3_mask, asrc3_value); 1042 1043 return 0; 1044 } 1045 EXPORT_SYMBOL_GPL(rt5645_sel_asrc_clk_src); 1046 1047 /* Digital Mixer */ 1048 static const struct snd_kcontrol_new rt5645_sto1_adc_l_mix[] = { 1049 SOC_DAPM_SINGLE("ADC1 Switch", RT5645_STO1_ADC_MIXER, 1050 RT5645_M_ADC_L1_SFT, 1, 1), 1051 SOC_DAPM_SINGLE("ADC2 Switch", RT5645_STO1_ADC_MIXER, 1052 RT5645_M_ADC_L2_SFT, 1, 1), 1053 }; 1054 1055 static const struct snd_kcontrol_new rt5645_sto1_adc_r_mix[] = { 1056 SOC_DAPM_SINGLE("ADC1 Switch", RT5645_STO1_ADC_MIXER, 1057 RT5645_M_ADC_R1_SFT, 1, 1), 1058 SOC_DAPM_SINGLE("ADC2 Switch", RT5645_STO1_ADC_MIXER, 1059 RT5645_M_ADC_R2_SFT, 1, 1), 1060 }; 1061 1062 static const struct snd_kcontrol_new rt5645_mono_adc_l_mix[] = { 1063 SOC_DAPM_SINGLE("ADC1 Switch", RT5645_MONO_ADC_MIXER, 1064 RT5645_M_MONO_ADC_L1_SFT, 1, 1), 1065 SOC_DAPM_SINGLE("ADC2 Switch", RT5645_MONO_ADC_MIXER, 1066 RT5645_M_MONO_ADC_L2_SFT, 1, 1), 1067 }; 1068 1069 static const struct snd_kcontrol_new rt5645_mono_adc_r_mix[] = { 1070 SOC_DAPM_SINGLE("ADC1 Switch", RT5645_MONO_ADC_MIXER, 1071 RT5645_M_MONO_ADC_R1_SFT, 1, 1), 1072 SOC_DAPM_SINGLE("ADC2 Switch", RT5645_MONO_ADC_MIXER, 1073 RT5645_M_MONO_ADC_R2_SFT, 1, 1), 1074 }; 1075 1076 static const struct snd_kcontrol_new rt5645_dac_l_mix[] = { 1077 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5645_AD_DA_MIXER, 1078 RT5645_M_ADCMIX_L_SFT, 1, 1), 1079 SOC_DAPM_SINGLE_AUTODISABLE("DAC1 Switch", RT5645_AD_DA_MIXER, 1080 RT5645_M_DAC1_L_SFT, 1, 1), 1081 }; 1082 1083 static const struct snd_kcontrol_new rt5645_dac_r_mix[] = { 1084 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5645_AD_DA_MIXER, 1085 RT5645_M_ADCMIX_R_SFT, 1, 1), 1086 SOC_DAPM_SINGLE_AUTODISABLE("DAC1 Switch", RT5645_AD_DA_MIXER, 1087 RT5645_M_DAC1_R_SFT, 1, 1), 1088 }; 1089 1090 static const struct snd_kcontrol_new rt5645_sto_dac_l_mix[] = { 1091 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_STO_DAC_MIXER, 1092 RT5645_M_DAC_L1_SFT, 1, 1), 1093 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_STO_DAC_MIXER, 1094 RT5645_M_DAC_L2_SFT, 1, 1), 1095 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_STO_DAC_MIXER, 1096 RT5645_M_DAC_R1_STO_L_SFT, 1, 1), 1097 }; 1098 1099 static const struct snd_kcontrol_new rt5645_sto_dac_r_mix[] = { 1100 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_STO_DAC_MIXER, 1101 RT5645_M_DAC_R1_SFT, 1, 1), 1102 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_STO_DAC_MIXER, 1103 RT5645_M_DAC_R2_SFT, 1, 1), 1104 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_STO_DAC_MIXER, 1105 RT5645_M_DAC_L1_STO_R_SFT, 1, 1), 1106 }; 1107 1108 static const struct snd_kcontrol_new rt5645_mono_dac_l_mix[] = { 1109 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_MONO_DAC_MIXER, 1110 RT5645_M_DAC_L1_MONO_L_SFT, 1, 1), 1111 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_MONO_DAC_MIXER, 1112 RT5645_M_DAC_L2_MONO_L_SFT, 1, 1), 1113 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_MONO_DAC_MIXER, 1114 RT5645_M_DAC_R2_MONO_L_SFT, 1, 1), 1115 }; 1116 1117 static const struct snd_kcontrol_new rt5645_mono_dac_r_mix[] = { 1118 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_MONO_DAC_MIXER, 1119 RT5645_M_DAC_R1_MONO_R_SFT, 1, 1), 1120 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_MONO_DAC_MIXER, 1121 RT5645_M_DAC_R2_MONO_R_SFT, 1, 1), 1122 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_MONO_DAC_MIXER, 1123 RT5645_M_DAC_L2_MONO_R_SFT, 1, 1), 1124 }; 1125 1126 static const struct snd_kcontrol_new rt5645_dig_l_mix[] = { 1127 SOC_DAPM_SINGLE("Sto DAC Mix L Switch", RT5645_DIG_MIXER, 1128 RT5645_M_STO_L_DAC_L_SFT, 1, 1), 1129 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_DIG_MIXER, 1130 RT5645_M_DAC_L2_DAC_L_SFT, 1, 1), 1131 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_DIG_MIXER, 1132 RT5645_M_DAC_R2_DAC_L_SFT, 1, 1), 1133 }; 1134 1135 static const struct snd_kcontrol_new rt5645_dig_r_mix[] = { 1136 SOC_DAPM_SINGLE("Sto DAC Mix R Switch", RT5645_DIG_MIXER, 1137 RT5645_M_STO_R_DAC_R_SFT, 1, 1), 1138 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_DIG_MIXER, 1139 RT5645_M_DAC_R2_DAC_R_SFT, 1, 1), 1140 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_DIG_MIXER, 1141 RT5645_M_DAC_L2_DAC_R_SFT, 1, 1), 1142 }; 1143 1144 /* Analog Input Mixer */ 1145 static const struct snd_kcontrol_new rt5645_rec_l_mix[] = { 1146 SOC_DAPM_SINGLE("HPOL Switch", RT5645_REC_L2_MIXER, 1147 RT5645_M_HP_L_RM_L_SFT, 1, 1), 1148 SOC_DAPM_SINGLE("INL Switch", RT5645_REC_L2_MIXER, 1149 RT5645_M_IN_L_RM_L_SFT, 1, 1), 1150 SOC_DAPM_SINGLE("BST2 Switch", RT5645_REC_L2_MIXER, 1151 RT5645_M_BST2_RM_L_SFT, 1, 1), 1152 SOC_DAPM_SINGLE("BST1 Switch", RT5645_REC_L2_MIXER, 1153 RT5645_M_BST1_RM_L_SFT, 1, 1), 1154 SOC_DAPM_SINGLE("OUT MIXL Switch", RT5645_REC_L2_MIXER, 1155 RT5645_M_OM_L_RM_L_SFT, 1, 1), 1156 }; 1157 1158 static const struct snd_kcontrol_new rt5645_rec_r_mix[] = { 1159 SOC_DAPM_SINGLE("HPOR Switch", RT5645_REC_R2_MIXER, 1160 RT5645_M_HP_R_RM_R_SFT, 1, 1), 1161 SOC_DAPM_SINGLE("INR Switch", RT5645_REC_R2_MIXER, 1162 RT5645_M_IN_R_RM_R_SFT, 1, 1), 1163 SOC_DAPM_SINGLE("BST2 Switch", RT5645_REC_R2_MIXER, 1164 RT5645_M_BST2_RM_R_SFT, 1, 1), 1165 SOC_DAPM_SINGLE("BST1 Switch", RT5645_REC_R2_MIXER, 1166 RT5645_M_BST1_RM_R_SFT, 1, 1), 1167 SOC_DAPM_SINGLE("OUT MIXR Switch", RT5645_REC_R2_MIXER, 1168 RT5645_M_OM_R_RM_R_SFT, 1, 1), 1169 }; 1170 1171 static const struct snd_kcontrol_new rt5645_spk_l_mix[] = { 1172 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_SPK_L_MIXER, 1173 RT5645_M_DAC_L1_SM_L_SFT, 1, 1), 1174 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_SPK_L_MIXER, 1175 RT5645_M_DAC_L2_SM_L_SFT, 1, 1), 1176 SOC_DAPM_SINGLE("INL Switch", RT5645_SPK_L_MIXER, 1177 RT5645_M_IN_L_SM_L_SFT, 1, 1), 1178 SOC_DAPM_SINGLE("BST1 Switch", RT5645_SPK_L_MIXER, 1179 RT5645_M_BST1_L_SM_L_SFT, 1, 1), 1180 }; 1181 1182 static const struct snd_kcontrol_new rt5645_spk_r_mix[] = { 1183 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_SPK_R_MIXER, 1184 RT5645_M_DAC_R1_SM_R_SFT, 1, 1), 1185 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_SPK_R_MIXER, 1186 RT5645_M_DAC_R2_SM_R_SFT, 1, 1), 1187 SOC_DAPM_SINGLE("INR Switch", RT5645_SPK_R_MIXER, 1188 RT5645_M_IN_R_SM_R_SFT, 1, 1), 1189 SOC_DAPM_SINGLE("BST2 Switch", RT5645_SPK_R_MIXER, 1190 RT5645_M_BST2_R_SM_R_SFT, 1, 1), 1191 }; 1192 1193 static const struct snd_kcontrol_new rt5645_out_l_mix[] = { 1194 SOC_DAPM_SINGLE("BST1 Switch", RT5645_OUT_L1_MIXER, 1195 RT5645_M_BST1_OM_L_SFT, 1, 1), 1196 SOC_DAPM_SINGLE("INL Switch", RT5645_OUT_L1_MIXER, 1197 RT5645_M_IN_L_OM_L_SFT, 1, 1), 1198 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_OUT_L1_MIXER, 1199 RT5645_M_DAC_L2_OM_L_SFT, 1, 1), 1200 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_OUT_L1_MIXER, 1201 RT5645_M_DAC_L1_OM_L_SFT, 1, 1), 1202 }; 1203 1204 static const struct snd_kcontrol_new rt5645_out_r_mix[] = { 1205 SOC_DAPM_SINGLE("BST2 Switch", RT5645_OUT_R1_MIXER, 1206 RT5645_M_BST2_OM_R_SFT, 1, 1), 1207 SOC_DAPM_SINGLE("INR Switch", RT5645_OUT_R1_MIXER, 1208 RT5645_M_IN_R_OM_R_SFT, 1, 1), 1209 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_OUT_R1_MIXER, 1210 RT5645_M_DAC_R2_OM_R_SFT, 1, 1), 1211 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_OUT_R1_MIXER, 1212 RT5645_M_DAC_R1_OM_R_SFT, 1, 1), 1213 }; 1214 1215 static const struct snd_kcontrol_new rt5645_spo_l_mix[] = { 1216 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_SPO_MIXER, 1217 RT5645_M_DAC_R1_SPM_L_SFT, 1, 1), 1218 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_SPO_MIXER, 1219 RT5645_M_DAC_L1_SPM_L_SFT, 1, 1), 1220 SOC_DAPM_SINGLE("SPKVOL R Switch", RT5645_SPO_MIXER, 1221 RT5645_M_SV_R_SPM_L_SFT, 1, 1), 1222 SOC_DAPM_SINGLE("SPKVOL L Switch", RT5645_SPO_MIXER, 1223 RT5645_M_SV_L_SPM_L_SFT, 1, 1), 1224 }; 1225 1226 static const struct snd_kcontrol_new rt5645_spo_r_mix[] = { 1227 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_SPO_MIXER, 1228 RT5645_M_DAC_R1_SPM_R_SFT, 1, 1), 1229 SOC_DAPM_SINGLE("SPKVOL R Switch", RT5645_SPO_MIXER, 1230 RT5645_M_SV_R_SPM_R_SFT, 1, 1), 1231 }; 1232 1233 static const struct snd_kcontrol_new rt5645_hpo_mix[] = { 1234 SOC_DAPM_SINGLE("DAC1 Switch", RT5645_HPO_MIXER, 1235 RT5645_M_DAC1_HM_SFT, 1, 1), 1236 SOC_DAPM_SINGLE("HPVOL Switch", RT5645_HPO_MIXER, 1237 RT5645_M_HPVOL_HM_SFT, 1, 1), 1238 }; 1239 1240 static const struct snd_kcontrol_new rt5645_hpvoll_mix[] = { 1241 SOC_DAPM_SINGLE("DAC1 Switch", RT5645_HPOMIXL_CTRL, 1242 RT5645_M_DAC1_HV_SFT, 1, 1), 1243 SOC_DAPM_SINGLE("DAC2 Switch", RT5645_HPOMIXL_CTRL, 1244 RT5645_M_DAC2_HV_SFT, 1, 1), 1245 SOC_DAPM_SINGLE("INL Switch", RT5645_HPOMIXL_CTRL, 1246 RT5645_M_IN_HV_SFT, 1, 1), 1247 SOC_DAPM_SINGLE("BST1 Switch", RT5645_HPOMIXL_CTRL, 1248 RT5645_M_BST1_HV_SFT, 1, 1), 1249 }; 1250 1251 static const struct snd_kcontrol_new rt5645_hpvolr_mix[] = { 1252 SOC_DAPM_SINGLE("DAC1 Switch", RT5645_HPOMIXR_CTRL, 1253 RT5645_M_DAC1_HV_SFT, 1, 1), 1254 SOC_DAPM_SINGLE("DAC2 Switch", RT5645_HPOMIXR_CTRL, 1255 RT5645_M_DAC2_HV_SFT, 1, 1), 1256 SOC_DAPM_SINGLE("INR Switch", RT5645_HPOMIXR_CTRL, 1257 RT5645_M_IN_HV_SFT, 1, 1), 1258 SOC_DAPM_SINGLE("BST2 Switch", RT5645_HPOMIXR_CTRL, 1259 RT5645_M_BST2_HV_SFT, 1, 1), 1260 }; 1261 1262 static const struct snd_kcontrol_new rt5645_lout_mix[] = { 1263 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_LOUT_MIXER, 1264 RT5645_M_DAC_L1_LM_SFT, 1, 1), 1265 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_LOUT_MIXER, 1266 RT5645_M_DAC_R1_LM_SFT, 1, 1), 1267 SOC_DAPM_SINGLE("OUTMIX L Switch", RT5645_LOUT_MIXER, 1268 RT5645_M_OV_L_LM_SFT, 1, 1), 1269 SOC_DAPM_SINGLE("OUTMIX R Switch", RT5645_LOUT_MIXER, 1270 RT5645_M_OV_R_LM_SFT, 1, 1), 1271 }; 1272 1273 /*DAC1 L/R source*/ /* MX-29 [9:8] [11:10] */ 1274 static const char * const rt5645_dac1_src[] = { 1275 "IF1 DAC", "IF2 DAC", "IF3 DAC" 1276 }; 1277 1278 static SOC_ENUM_SINGLE_DECL( 1279 rt5645_dac1l_enum, RT5645_AD_DA_MIXER, 1280 RT5645_DAC1_L_SEL_SFT, rt5645_dac1_src); 1281 1282 static const struct snd_kcontrol_new rt5645_dac1l_mux = 1283 SOC_DAPM_ENUM("DAC1 L source", rt5645_dac1l_enum); 1284 1285 static SOC_ENUM_SINGLE_DECL( 1286 rt5645_dac1r_enum, RT5645_AD_DA_MIXER, 1287 RT5645_DAC1_R_SEL_SFT, rt5645_dac1_src); 1288 1289 static const struct snd_kcontrol_new rt5645_dac1r_mux = 1290 SOC_DAPM_ENUM("DAC1 R source", rt5645_dac1r_enum); 1291 1292 /*DAC2 L/R source*/ /* MX-1B [6:4] [2:0] */ 1293 static const char * const rt5645_dac12_src[] = { 1294 "IF1 DAC", "IF2 DAC", "IF3 DAC", "Mono ADC", "VAD_ADC" 1295 }; 1296 1297 static SOC_ENUM_SINGLE_DECL( 1298 rt5645_dac2l_enum, RT5645_DAC_CTRL, 1299 RT5645_DAC2_L_SEL_SFT, rt5645_dac12_src); 1300 1301 static const struct snd_kcontrol_new rt5645_dac_l2_mux = 1302 SOC_DAPM_ENUM("DAC2 L source", rt5645_dac2l_enum); 1303 1304 static const char * const rt5645_dacr2_src[] = { 1305 "IF1 DAC", "IF2 DAC", "IF3 DAC", "Mono ADC", "Haptic" 1306 }; 1307 1308 static SOC_ENUM_SINGLE_DECL( 1309 rt5645_dac2r_enum, RT5645_DAC_CTRL, 1310 RT5645_DAC2_R_SEL_SFT, rt5645_dacr2_src); 1311 1312 static const struct snd_kcontrol_new rt5645_dac_r2_mux = 1313 SOC_DAPM_ENUM("DAC2 R source", rt5645_dac2r_enum); 1314 1315 /* Stereo1 ADC source */ 1316 /* MX-27 [12] */ 1317 static const char * const rt5645_stereo_adc1_src[] = { 1318 "DAC MIX", "ADC" 1319 }; 1320 1321 static SOC_ENUM_SINGLE_DECL( 1322 rt5645_stereo1_adc1_enum, RT5645_STO1_ADC_MIXER, 1323 RT5645_ADC_1_SRC_SFT, rt5645_stereo_adc1_src); 1324 1325 static const struct snd_kcontrol_new rt5645_sto_adc1_mux = 1326 SOC_DAPM_ENUM("Stereo1 ADC1 Mux", rt5645_stereo1_adc1_enum); 1327 1328 /* MX-27 [11] */ 1329 static const char * const rt5645_stereo_adc2_src[] = { 1330 "DAC MIX", "DMIC" 1331 }; 1332 1333 static SOC_ENUM_SINGLE_DECL( 1334 rt5645_stereo1_adc2_enum, RT5645_STO1_ADC_MIXER, 1335 RT5645_ADC_2_SRC_SFT, rt5645_stereo_adc2_src); 1336 1337 static const struct snd_kcontrol_new rt5645_sto_adc2_mux = 1338 SOC_DAPM_ENUM("Stereo1 ADC2 Mux", rt5645_stereo1_adc2_enum); 1339 1340 /* MX-27 [8] */ 1341 static const char * const rt5645_stereo_dmic_src[] = { 1342 "DMIC1", "DMIC2" 1343 }; 1344 1345 static SOC_ENUM_SINGLE_DECL( 1346 rt5645_stereo1_dmic_enum, RT5645_STO1_ADC_MIXER, 1347 RT5645_DMIC_SRC_SFT, rt5645_stereo_dmic_src); 1348 1349 static const struct snd_kcontrol_new rt5645_sto1_dmic_mux = 1350 SOC_DAPM_ENUM("Stereo1 DMIC source", rt5645_stereo1_dmic_enum); 1351 1352 /* Mono ADC source */ 1353 /* MX-28 [12] */ 1354 static const char * const rt5645_mono_adc_l1_src[] = { 1355 "Mono DAC MIXL", "ADC" 1356 }; 1357 1358 static SOC_ENUM_SINGLE_DECL( 1359 rt5645_mono_adc_l1_enum, RT5645_MONO_ADC_MIXER, 1360 RT5645_MONO_ADC_L1_SRC_SFT, rt5645_mono_adc_l1_src); 1361 1362 static const struct snd_kcontrol_new rt5645_mono_adc_l1_mux = 1363 SOC_DAPM_ENUM("Mono ADC1 left source", rt5645_mono_adc_l1_enum); 1364 /* MX-28 [11] */ 1365 static const char * const rt5645_mono_adc_l2_src[] = { 1366 "Mono DAC MIXL", "DMIC" 1367 }; 1368 1369 static SOC_ENUM_SINGLE_DECL( 1370 rt5645_mono_adc_l2_enum, RT5645_MONO_ADC_MIXER, 1371 RT5645_MONO_ADC_L2_SRC_SFT, rt5645_mono_adc_l2_src); 1372 1373 static const struct snd_kcontrol_new rt5645_mono_adc_l2_mux = 1374 SOC_DAPM_ENUM("Mono ADC2 left source", rt5645_mono_adc_l2_enum); 1375 1376 /* MX-28 [8] */ 1377 static const char * const rt5645_mono_dmic_src[] = { 1378 "DMIC1", "DMIC2" 1379 }; 1380 1381 static SOC_ENUM_SINGLE_DECL( 1382 rt5645_mono_dmic_l_enum, RT5645_MONO_ADC_MIXER, 1383 RT5645_MONO_DMIC_L_SRC_SFT, rt5645_mono_dmic_src); 1384 1385 static const struct snd_kcontrol_new rt5645_mono_dmic_l_mux = 1386 SOC_DAPM_ENUM("Mono DMIC left source", rt5645_mono_dmic_l_enum); 1387 /* MX-28 [1:0] */ 1388 static SOC_ENUM_SINGLE_DECL( 1389 rt5645_mono_dmic_r_enum, RT5645_MONO_ADC_MIXER, 1390 RT5645_MONO_DMIC_R_SRC_SFT, rt5645_mono_dmic_src); 1391 1392 static const struct snd_kcontrol_new rt5645_mono_dmic_r_mux = 1393 SOC_DAPM_ENUM("Mono DMIC Right source", rt5645_mono_dmic_r_enum); 1394 /* MX-28 [4] */ 1395 static const char * const rt5645_mono_adc_r1_src[] = { 1396 "Mono DAC MIXR", "ADC" 1397 }; 1398 1399 static SOC_ENUM_SINGLE_DECL( 1400 rt5645_mono_adc_r1_enum, RT5645_MONO_ADC_MIXER, 1401 RT5645_MONO_ADC_R1_SRC_SFT, rt5645_mono_adc_r1_src); 1402 1403 static const struct snd_kcontrol_new rt5645_mono_adc_r1_mux = 1404 SOC_DAPM_ENUM("Mono ADC1 right source", rt5645_mono_adc_r1_enum); 1405 /* MX-28 [3] */ 1406 static const char * const rt5645_mono_adc_r2_src[] = { 1407 "Mono DAC MIXR", "DMIC" 1408 }; 1409 1410 static SOC_ENUM_SINGLE_DECL( 1411 rt5645_mono_adc_r2_enum, RT5645_MONO_ADC_MIXER, 1412 RT5645_MONO_ADC_R2_SRC_SFT, rt5645_mono_adc_r2_src); 1413 1414 static const struct snd_kcontrol_new rt5645_mono_adc_r2_mux = 1415 SOC_DAPM_ENUM("Mono ADC2 right source", rt5645_mono_adc_r2_enum); 1416 1417 /* MX-77 [9:8] */ 1418 static const char * const rt5645_if1_adc_in_src[] = { 1419 "IF_ADC1/IF_ADC2/VAD_ADC", "IF_ADC2/IF_ADC1/VAD_ADC", 1420 "VAD_ADC/IF_ADC1/IF_ADC2", "VAD_ADC/IF_ADC2/IF_ADC1" 1421 }; 1422 1423 static SOC_ENUM_SINGLE_DECL( 1424 rt5645_if1_adc_in_enum, RT5645_TDM_CTRL_1, 1425 RT5645_IF1_ADC_IN_SFT, rt5645_if1_adc_in_src); 1426 1427 static const struct snd_kcontrol_new rt5645_if1_adc_in_mux = 1428 SOC_DAPM_ENUM("IF1 ADC IN source", rt5645_if1_adc_in_enum); 1429 1430 /* MX-78 [4:0] */ 1431 static const char * const rt5650_if1_adc_in_src[] = { 1432 "IF_ADC1/IF_ADC2/DAC_REF/Null", 1433 "IF_ADC1/IF_ADC2/Null/DAC_REF", 1434 "IF_ADC1/DAC_REF/IF_ADC2/Null", 1435 "IF_ADC1/DAC_REF/Null/IF_ADC2", 1436 "IF_ADC1/Null/DAC_REF/IF_ADC2", 1437 "IF_ADC1/Null/IF_ADC2/DAC_REF", 1438 1439 "IF_ADC2/IF_ADC1/DAC_REF/Null", 1440 "IF_ADC2/IF_ADC1/Null/DAC_REF", 1441 "IF_ADC2/DAC_REF/IF_ADC1/Null", 1442 "IF_ADC2/DAC_REF/Null/IF_ADC1", 1443 "IF_ADC2/Null/DAC_REF/IF_ADC1", 1444 "IF_ADC2/Null/IF_ADC1/DAC_REF", 1445 1446 "DAC_REF/IF_ADC1/IF_ADC2/Null", 1447 "DAC_REF/IF_ADC1/Null/IF_ADC2", 1448 "DAC_REF/IF_ADC2/IF_ADC1/Null", 1449 "DAC_REF/IF_ADC2/Null/IF_ADC1", 1450 "DAC_REF/Null/IF_ADC1/IF_ADC2", 1451 "DAC_REF/Null/IF_ADC2/IF_ADC1", 1452 1453 "Null/IF_ADC1/IF_ADC2/DAC_REF", 1454 "Null/IF_ADC1/DAC_REF/IF_ADC2", 1455 "Null/IF_ADC2/IF_ADC1/DAC_REF", 1456 "Null/IF_ADC2/DAC_REF/IF_ADC1", 1457 "Null/DAC_REF/IF_ADC1/IF_ADC2", 1458 "Null/DAC_REF/IF_ADC2/IF_ADC1", 1459 }; 1460 1461 static SOC_ENUM_SINGLE_DECL( 1462 rt5650_if1_adc_in_enum, RT5645_TDM_CTRL_2, 1463 0, rt5650_if1_adc_in_src); 1464 1465 static const struct snd_kcontrol_new rt5650_if1_adc_in_mux = 1466 SOC_DAPM_ENUM("IF1 ADC IN source", rt5650_if1_adc_in_enum); 1467 1468 /* MX-78 [15:14][13:12][11:10] */ 1469 static const char * const rt5645_tdm_adc_swap_select[] = { 1470 "L/R", "R/L", "L/L", "R/R" 1471 }; 1472 1473 static SOC_ENUM_SINGLE_DECL(rt5650_tdm_adc_slot0_1_enum, 1474 RT5645_TDM_CTRL_2, 14, rt5645_tdm_adc_swap_select); 1475 1476 static const struct snd_kcontrol_new rt5650_if1_adc1_in_mux = 1477 SOC_DAPM_ENUM("IF1 ADC1 IN source", rt5650_tdm_adc_slot0_1_enum); 1478 1479 static SOC_ENUM_SINGLE_DECL(rt5650_tdm_adc_slot2_3_enum, 1480 RT5645_TDM_CTRL_2, 12, rt5645_tdm_adc_swap_select); 1481 1482 static const struct snd_kcontrol_new rt5650_if1_adc2_in_mux = 1483 SOC_DAPM_ENUM("IF1 ADC2 IN source", rt5650_tdm_adc_slot2_3_enum); 1484 1485 static SOC_ENUM_SINGLE_DECL(rt5650_tdm_adc_slot4_5_enum, 1486 RT5645_TDM_CTRL_2, 10, rt5645_tdm_adc_swap_select); 1487 1488 static const struct snd_kcontrol_new rt5650_if1_adc3_in_mux = 1489 SOC_DAPM_ENUM("IF1 ADC3 IN source", rt5650_tdm_adc_slot4_5_enum); 1490 1491 /* MX-77 [7:6][5:4][3:2] */ 1492 static SOC_ENUM_SINGLE_DECL(rt5645_tdm_adc_slot0_1_enum, 1493 RT5645_TDM_CTRL_1, 6, rt5645_tdm_adc_swap_select); 1494 1495 static const struct snd_kcontrol_new rt5645_if1_adc1_in_mux = 1496 SOC_DAPM_ENUM("IF1 ADC1 IN source", rt5645_tdm_adc_slot0_1_enum); 1497 1498 static SOC_ENUM_SINGLE_DECL(rt5645_tdm_adc_slot2_3_enum, 1499 RT5645_TDM_CTRL_1, 4, rt5645_tdm_adc_swap_select); 1500 1501 static const struct snd_kcontrol_new rt5645_if1_adc2_in_mux = 1502 SOC_DAPM_ENUM("IF1 ADC2 IN source", rt5645_tdm_adc_slot2_3_enum); 1503 1504 static SOC_ENUM_SINGLE_DECL(rt5645_tdm_adc_slot4_5_enum, 1505 RT5645_TDM_CTRL_1, 2, rt5645_tdm_adc_swap_select); 1506 1507 static const struct snd_kcontrol_new rt5645_if1_adc3_in_mux = 1508 SOC_DAPM_ENUM("IF1 ADC3 IN source", rt5645_tdm_adc_slot4_5_enum); 1509 1510 /* MX-79 [14:12][10:8][6:4][2:0] */ 1511 static const char * const rt5645_tdm_dac_swap_select[] = { 1512 "Slot0", "Slot1", "Slot2", "Slot3" 1513 }; 1514 1515 static SOC_ENUM_SINGLE_DECL(rt5645_tdm_dac0_enum, 1516 RT5645_TDM_CTRL_3, 12, rt5645_tdm_dac_swap_select); 1517 1518 static const struct snd_kcontrol_new rt5645_if1_dac0_tdm_sel_mux = 1519 SOC_DAPM_ENUM("IF1 DAC0 source", rt5645_tdm_dac0_enum); 1520 1521 static SOC_ENUM_SINGLE_DECL(rt5645_tdm_dac1_enum, 1522 RT5645_TDM_CTRL_3, 8, rt5645_tdm_dac_swap_select); 1523 1524 static const struct snd_kcontrol_new rt5645_if1_dac1_tdm_sel_mux = 1525 SOC_DAPM_ENUM("IF1 DAC1 source", rt5645_tdm_dac1_enum); 1526 1527 static SOC_ENUM_SINGLE_DECL(rt5645_tdm_dac2_enum, 1528 RT5645_TDM_CTRL_3, 4, rt5645_tdm_dac_swap_select); 1529 1530 static const struct snd_kcontrol_new rt5645_if1_dac2_tdm_sel_mux = 1531 SOC_DAPM_ENUM("IF1 DAC2 source", rt5645_tdm_dac2_enum); 1532 1533 static SOC_ENUM_SINGLE_DECL(rt5645_tdm_dac3_enum, 1534 RT5645_TDM_CTRL_3, 0, rt5645_tdm_dac_swap_select); 1535 1536 static const struct snd_kcontrol_new rt5645_if1_dac3_tdm_sel_mux = 1537 SOC_DAPM_ENUM("IF1 DAC3 source", rt5645_tdm_dac3_enum); 1538 1539 /* MX-7a [14:12][10:8][6:4][2:0] */ 1540 static SOC_ENUM_SINGLE_DECL(rt5650_tdm_dac0_enum, 1541 RT5650_TDM_CTRL_4, 12, rt5645_tdm_dac_swap_select); 1542 1543 static const struct snd_kcontrol_new rt5650_if1_dac0_tdm_sel_mux = 1544 SOC_DAPM_ENUM("IF1 DAC0 source", rt5650_tdm_dac0_enum); 1545 1546 static SOC_ENUM_SINGLE_DECL(rt5650_tdm_dac1_enum, 1547 RT5650_TDM_CTRL_4, 8, rt5645_tdm_dac_swap_select); 1548 1549 static const struct snd_kcontrol_new rt5650_if1_dac1_tdm_sel_mux = 1550 SOC_DAPM_ENUM("IF1 DAC1 source", rt5650_tdm_dac1_enum); 1551 1552 static SOC_ENUM_SINGLE_DECL(rt5650_tdm_dac2_enum, 1553 RT5650_TDM_CTRL_4, 4, rt5645_tdm_dac_swap_select); 1554 1555 static const struct snd_kcontrol_new rt5650_if1_dac2_tdm_sel_mux = 1556 SOC_DAPM_ENUM("IF1 DAC2 source", rt5650_tdm_dac2_enum); 1557 1558 static SOC_ENUM_SINGLE_DECL(rt5650_tdm_dac3_enum, 1559 RT5650_TDM_CTRL_4, 0, rt5645_tdm_dac_swap_select); 1560 1561 static const struct snd_kcontrol_new rt5650_if1_dac3_tdm_sel_mux = 1562 SOC_DAPM_ENUM("IF1 DAC3 source", rt5650_tdm_dac3_enum); 1563 1564 /* MX-2d [3] [2] */ 1565 static const char * const rt5650_a_dac1_src[] = { 1566 "DAC1", "Stereo DAC Mixer" 1567 }; 1568 1569 static SOC_ENUM_SINGLE_DECL( 1570 rt5650_a_dac1_l_enum, RT5650_A_DAC_SOUR, 1571 RT5650_A_DAC1_L_IN_SFT, rt5650_a_dac1_src); 1572 1573 static const struct snd_kcontrol_new rt5650_a_dac1_l_mux = 1574 SOC_DAPM_ENUM("A DAC1 L source", rt5650_a_dac1_l_enum); 1575 1576 static SOC_ENUM_SINGLE_DECL( 1577 rt5650_a_dac1_r_enum, RT5650_A_DAC_SOUR, 1578 RT5650_A_DAC1_R_IN_SFT, rt5650_a_dac1_src); 1579 1580 static const struct snd_kcontrol_new rt5650_a_dac1_r_mux = 1581 SOC_DAPM_ENUM("A DAC1 R source", rt5650_a_dac1_r_enum); 1582 1583 /* MX-2d [1] [0] */ 1584 static const char * const rt5650_a_dac2_src[] = { 1585 "Stereo DAC Mixer", "Mono DAC Mixer" 1586 }; 1587 1588 static SOC_ENUM_SINGLE_DECL( 1589 rt5650_a_dac2_l_enum, RT5650_A_DAC_SOUR, 1590 RT5650_A_DAC2_L_IN_SFT, rt5650_a_dac2_src); 1591 1592 static const struct snd_kcontrol_new rt5650_a_dac2_l_mux = 1593 SOC_DAPM_ENUM("A DAC2 L source", rt5650_a_dac2_l_enum); 1594 1595 static SOC_ENUM_SINGLE_DECL( 1596 rt5650_a_dac2_r_enum, RT5650_A_DAC_SOUR, 1597 RT5650_A_DAC2_R_IN_SFT, rt5650_a_dac2_src); 1598 1599 static const struct snd_kcontrol_new rt5650_a_dac2_r_mux = 1600 SOC_DAPM_ENUM("A DAC2 R source", rt5650_a_dac2_r_enum); 1601 1602 /* MX-2F [13:12] */ 1603 static const char * const rt5645_if2_adc_in_src[] = { 1604 "IF_ADC1", "IF_ADC2", "VAD_ADC" 1605 }; 1606 1607 static SOC_ENUM_SINGLE_DECL( 1608 rt5645_if2_adc_in_enum, RT5645_DIG_INF1_DATA, 1609 RT5645_IF2_ADC_IN_SFT, rt5645_if2_adc_in_src); 1610 1611 static const struct snd_kcontrol_new rt5645_if2_adc_in_mux = 1612 SOC_DAPM_ENUM("IF2 ADC IN source", rt5645_if2_adc_in_enum); 1613 1614 /* MX-31 [15] [13] [11] [9] */ 1615 static const char * const rt5645_pdm_src[] = { 1616 "Mono DAC", "Stereo DAC" 1617 }; 1618 1619 static SOC_ENUM_SINGLE_DECL( 1620 rt5645_pdm1_l_enum, RT5645_PDM_OUT_CTRL, 1621 RT5645_PDM1_L_SFT, rt5645_pdm_src); 1622 1623 static const struct snd_kcontrol_new rt5645_pdm1_l_mux = 1624 SOC_DAPM_ENUM("PDM1 L source", rt5645_pdm1_l_enum); 1625 1626 static SOC_ENUM_SINGLE_DECL( 1627 rt5645_pdm1_r_enum, RT5645_PDM_OUT_CTRL, 1628 RT5645_PDM1_R_SFT, rt5645_pdm_src); 1629 1630 static const struct snd_kcontrol_new rt5645_pdm1_r_mux = 1631 SOC_DAPM_ENUM("PDM1 R source", rt5645_pdm1_r_enum); 1632 1633 /* MX-9D [9:8] */ 1634 static const char * const rt5645_vad_adc_src[] = { 1635 "Sto1 ADC L", "Mono ADC L", "Mono ADC R" 1636 }; 1637 1638 static SOC_ENUM_SINGLE_DECL( 1639 rt5645_vad_adc_enum, RT5645_VAD_CTRL4, 1640 RT5645_VAD_SEL_SFT, rt5645_vad_adc_src); 1641 1642 static const struct snd_kcontrol_new rt5645_vad_adc_mux = 1643 SOC_DAPM_ENUM("VAD ADC source", rt5645_vad_adc_enum); 1644 1645 static const struct snd_kcontrol_new spk_l_vol_control = 1646 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_SPK_VOL, 1647 RT5645_L_MUTE_SFT, 1, 1); 1648 1649 static const struct snd_kcontrol_new spk_r_vol_control = 1650 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_SPK_VOL, 1651 RT5645_R_MUTE_SFT, 1, 1); 1652 1653 static const struct snd_kcontrol_new hp_l_vol_control = 1654 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_HP_VOL, 1655 RT5645_L_MUTE_SFT, 1, 1); 1656 1657 static const struct snd_kcontrol_new hp_r_vol_control = 1658 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_HP_VOL, 1659 RT5645_R_MUTE_SFT, 1, 1); 1660 1661 static const struct snd_kcontrol_new pdm1_l_vol_control = 1662 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_PDM_OUT_CTRL, 1663 RT5645_M_PDM1_L, 1, 1); 1664 1665 static const struct snd_kcontrol_new pdm1_r_vol_control = 1666 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_PDM_OUT_CTRL, 1667 RT5645_M_PDM1_R, 1, 1); 1668 1669 static void hp_amp_power(struct snd_soc_component *component, int on) 1670 { 1671 static int hp_amp_power_count; 1672 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component); 1673 int i, val; 1674 1675 if (on) { 1676 if (hp_amp_power_count <= 0) { 1677 if (rt5645->codec_type == CODEC_TYPE_RT5650) { 1678 snd_soc_component_write(component, RT5645_DEPOP_M2, 0x3100); 1679 snd_soc_component_write(component, RT5645_CHARGE_PUMP, 1680 0x0e06); 1681 snd_soc_component_write(component, RT5645_DEPOP_M1, 0x000d); 1682 regmap_write(rt5645->regmap, RT5645_PR_BASE + 1683 RT5645_HP_DCC_INT1, 0x9f01); 1684 for (i = 0; i < 20; i++) { 1685 usleep_range(1000, 1500); 1686 regmap_read(rt5645->regmap, RT5645_PR_BASE + 1687 RT5645_HP_DCC_INT1, &val); 1688 if (!(val & 0x8000)) 1689 break; 1690 } 1691 snd_soc_component_update_bits(component, RT5645_DEPOP_M1, 1692 RT5645_HP_CO_MASK, RT5645_HP_CO_EN); 1693 regmap_write(rt5645->regmap, RT5645_PR_BASE + 1694 0x3e, 0x7400); 1695 snd_soc_component_write(component, RT5645_DEPOP_M3, 0x0737); 1696 regmap_write(rt5645->regmap, RT5645_PR_BASE + 1697 RT5645_MAMP_INT_REG2, 0xfc00); 1698 snd_soc_component_write(component, RT5645_DEPOP_M2, 0x1140); 1699 msleep(90); 1700 } else { 1701 /* depop parameters */ 1702 snd_soc_component_update_bits(component, RT5645_DEPOP_M2, 1703 RT5645_DEPOP_MASK, RT5645_DEPOP_MAN); 1704 snd_soc_component_write(component, RT5645_DEPOP_M1, 0x000d); 1705 regmap_write(rt5645->regmap, RT5645_PR_BASE + 1706 RT5645_HP_DCC_INT1, 0x9f01); 1707 mdelay(150); 1708 /* headphone amp power on */ 1709 snd_soc_component_update_bits(component, RT5645_PWR_ANLG1, 1710 RT5645_PWR_FV1 | RT5645_PWR_FV2, 0); 1711 snd_soc_component_update_bits(component, RT5645_PWR_VOL, 1712 RT5645_PWR_HV_L | RT5645_PWR_HV_R, 1713 RT5645_PWR_HV_L | RT5645_PWR_HV_R); 1714 snd_soc_component_update_bits(component, RT5645_PWR_ANLG1, 1715 RT5645_PWR_HP_L | RT5645_PWR_HP_R | 1716 RT5645_PWR_HA, 1717 RT5645_PWR_HP_L | RT5645_PWR_HP_R | 1718 RT5645_PWR_HA); 1719 mdelay(5); 1720 snd_soc_component_update_bits(component, RT5645_PWR_ANLG1, 1721 RT5645_PWR_FV1 | RT5645_PWR_FV2, 1722 RT5645_PWR_FV1 | RT5645_PWR_FV2); 1723 1724 snd_soc_component_update_bits(component, RT5645_DEPOP_M1, 1725 RT5645_HP_CO_MASK | RT5645_HP_SG_MASK, 1726 RT5645_HP_CO_EN | RT5645_HP_SG_EN); 1727 regmap_write(rt5645->regmap, RT5645_PR_BASE + 1728 0x14, 0x1aaa); 1729 regmap_write(rt5645->regmap, RT5645_PR_BASE + 1730 0x24, 0x0430); 1731 } 1732 } 1733 hp_amp_power_count++; 1734 } else { 1735 hp_amp_power_count--; 1736 if (hp_amp_power_count <= 0) { 1737 if (rt5645->codec_type == CODEC_TYPE_RT5650) { 1738 regmap_write(rt5645->regmap, RT5645_PR_BASE + 1739 0x3e, 0x7400); 1740 snd_soc_component_write(component, RT5645_DEPOP_M3, 0x0737); 1741 regmap_write(rt5645->regmap, RT5645_PR_BASE + 1742 RT5645_MAMP_INT_REG2, 0xfc00); 1743 snd_soc_component_write(component, RT5645_DEPOP_M2, 0x1140); 1744 msleep(100); 1745 snd_soc_component_write(component, RT5645_DEPOP_M1, 0x0001); 1746 1747 } else { 1748 snd_soc_component_update_bits(component, RT5645_DEPOP_M1, 1749 RT5645_HP_SG_MASK | 1750 RT5645_HP_L_SMT_MASK | 1751 RT5645_HP_R_SMT_MASK, 1752 RT5645_HP_SG_DIS | 1753 RT5645_HP_L_SMT_DIS | 1754 RT5645_HP_R_SMT_DIS); 1755 /* headphone amp power down */ 1756 snd_soc_component_write(component, RT5645_DEPOP_M1, 0x0000); 1757 snd_soc_component_update_bits(component, RT5645_PWR_ANLG1, 1758 RT5645_PWR_HP_L | RT5645_PWR_HP_R | 1759 RT5645_PWR_HA, 0); 1760 snd_soc_component_update_bits(component, RT5645_DEPOP_M2, 1761 RT5645_DEPOP_MASK, 0); 1762 } 1763 } 1764 } 1765 } 1766 1767 static int rt5645_hp_event(struct snd_soc_dapm_widget *w, 1768 struct snd_kcontrol *kcontrol, int event) 1769 { 1770 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1771 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component); 1772 1773 switch (event) { 1774 case SND_SOC_DAPM_POST_PMU: 1775 hp_amp_power(component, 1); 1776 /* headphone unmute sequence */ 1777 if (rt5645->codec_type == CODEC_TYPE_RT5645) { 1778 snd_soc_component_update_bits(component, RT5645_DEPOP_M3, 1779 RT5645_CP_FQ1_MASK | RT5645_CP_FQ2_MASK | 1780 RT5645_CP_FQ3_MASK, 1781 (RT5645_CP_FQ_192_KHZ << RT5645_CP_FQ1_SFT) | 1782 (RT5645_CP_FQ_12_KHZ << RT5645_CP_FQ2_SFT) | 1783 (RT5645_CP_FQ_192_KHZ << RT5645_CP_FQ3_SFT)); 1784 regmap_write(rt5645->regmap, RT5645_PR_BASE + 1785 RT5645_MAMP_INT_REG2, 0xfc00); 1786 snd_soc_component_update_bits(component, RT5645_DEPOP_M1, 1787 RT5645_SMT_TRIG_MASK, RT5645_SMT_TRIG_EN); 1788 snd_soc_component_update_bits(component, RT5645_DEPOP_M1, 1789 RT5645_RSTN_MASK, RT5645_RSTN_EN); 1790 snd_soc_component_update_bits(component, RT5645_DEPOP_M1, 1791 RT5645_RSTN_MASK | RT5645_HP_L_SMT_MASK | 1792 RT5645_HP_R_SMT_MASK, RT5645_RSTN_DIS | 1793 RT5645_HP_L_SMT_EN | RT5645_HP_R_SMT_EN); 1794 msleep(40); 1795 snd_soc_component_update_bits(component, RT5645_DEPOP_M1, 1796 RT5645_HP_SG_MASK | RT5645_HP_L_SMT_MASK | 1797 RT5645_HP_R_SMT_MASK, RT5645_HP_SG_DIS | 1798 RT5645_HP_L_SMT_DIS | RT5645_HP_R_SMT_DIS); 1799 } 1800 break; 1801 1802 case SND_SOC_DAPM_PRE_PMD: 1803 /* headphone mute sequence */ 1804 if (rt5645->codec_type == CODEC_TYPE_RT5645) { 1805 snd_soc_component_update_bits(component, RT5645_DEPOP_M3, 1806 RT5645_CP_FQ1_MASK | RT5645_CP_FQ2_MASK | 1807 RT5645_CP_FQ3_MASK, 1808 (RT5645_CP_FQ_96_KHZ << RT5645_CP_FQ1_SFT) | 1809 (RT5645_CP_FQ_12_KHZ << RT5645_CP_FQ2_SFT) | 1810 (RT5645_CP_FQ_96_KHZ << RT5645_CP_FQ3_SFT)); 1811 regmap_write(rt5645->regmap, RT5645_PR_BASE + 1812 RT5645_MAMP_INT_REG2, 0xfc00); 1813 snd_soc_component_update_bits(component, RT5645_DEPOP_M1, 1814 RT5645_HP_SG_MASK, RT5645_HP_SG_EN); 1815 snd_soc_component_update_bits(component, RT5645_DEPOP_M1, 1816 RT5645_RSTP_MASK, RT5645_RSTP_EN); 1817 snd_soc_component_update_bits(component, RT5645_DEPOP_M1, 1818 RT5645_RSTP_MASK | RT5645_HP_L_SMT_MASK | 1819 RT5645_HP_R_SMT_MASK, RT5645_RSTP_DIS | 1820 RT5645_HP_L_SMT_EN | RT5645_HP_R_SMT_EN); 1821 msleep(30); 1822 } 1823 hp_amp_power(component, 0); 1824 break; 1825 1826 default: 1827 return 0; 1828 } 1829 1830 return 0; 1831 } 1832 1833 static int rt5645_spk_event(struct snd_soc_dapm_widget *w, 1834 struct snd_kcontrol *kcontrol, int event) 1835 { 1836 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1837 1838 switch (event) { 1839 case SND_SOC_DAPM_POST_PMU: 1840 rt5645_enable_hweq(component); 1841 snd_soc_component_update_bits(component, RT5645_PWR_DIG1, 1842 RT5645_PWR_CLS_D | RT5645_PWR_CLS_D_R | 1843 RT5645_PWR_CLS_D_L, 1844 RT5645_PWR_CLS_D | RT5645_PWR_CLS_D_R | 1845 RT5645_PWR_CLS_D_L); 1846 snd_soc_component_update_bits(component, RT5645_GEN_CTRL3, 1847 RT5645_DET_CLK_MASK, RT5645_DET_CLK_MODE1); 1848 break; 1849 1850 case SND_SOC_DAPM_PRE_PMD: 1851 snd_soc_component_update_bits(component, RT5645_GEN_CTRL3, 1852 RT5645_DET_CLK_MASK, RT5645_DET_CLK_DIS); 1853 snd_soc_component_write(component, RT5645_EQ_CTRL2, 0); 1854 snd_soc_component_update_bits(component, RT5645_PWR_DIG1, 1855 RT5645_PWR_CLS_D | RT5645_PWR_CLS_D_R | 1856 RT5645_PWR_CLS_D_L, 0); 1857 break; 1858 1859 default: 1860 return 0; 1861 } 1862 1863 return 0; 1864 } 1865 1866 static int rt5645_lout_event(struct snd_soc_dapm_widget *w, 1867 struct snd_kcontrol *kcontrol, int event) 1868 { 1869 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1870 1871 switch (event) { 1872 case SND_SOC_DAPM_POST_PMU: 1873 hp_amp_power(component, 1); 1874 snd_soc_component_update_bits(component, RT5645_PWR_ANLG1, 1875 RT5645_PWR_LM, RT5645_PWR_LM); 1876 snd_soc_component_update_bits(component, RT5645_LOUT1, 1877 RT5645_L_MUTE | RT5645_R_MUTE, 0); 1878 break; 1879 1880 case SND_SOC_DAPM_PRE_PMD: 1881 snd_soc_component_update_bits(component, RT5645_LOUT1, 1882 RT5645_L_MUTE | RT5645_R_MUTE, 1883 RT5645_L_MUTE | RT5645_R_MUTE); 1884 snd_soc_component_update_bits(component, RT5645_PWR_ANLG1, 1885 RT5645_PWR_LM, 0); 1886 hp_amp_power(component, 0); 1887 break; 1888 1889 default: 1890 return 0; 1891 } 1892 1893 return 0; 1894 } 1895 1896 static int rt5645_bst2_event(struct snd_soc_dapm_widget *w, 1897 struct snd_kcontrol *kcontrol, int event) 1898 { 1899 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1900 1901 switch (event) { 1902 case SND_SOC_DAPM_POST_PMU: 1903 snd_soc_component_update_bits(component, RT5645_PWR_ANLG2, 1904 RT5645_PWR_BST2_P, RT5645_PWR_BST2_P); 1905 break; 1906 1907 case SND_SOC_DAPM_PRE_PMD: 1908 snd_soc_component_update_bits(component, RT5645_PWR_ANLG2, 1909 RT5645_PWR_BST2_P, 0); 1910 break; 1911 1912 default: 1913 return 0; 1914 } 1915 1916 return 0; 1917 } 1918 1919 static int rt5645_set_micbias1_event(struct snd_soc_dapm_widget *w, 1920 struct snd_kcontrol *k, int event) 1921 { 1922 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1923 1924 switch (event) { 1925 case SND_SOC_DAPM_PRE_PMU: 1926 snd_soc_component_update_bits(component, RT5645_GEN_CTRL2, 1927 RT5645_MICBIAS1_POW_CTRL_SEL_MASK, 1928 RT5645_MICBIAS1_POW_CTRL_SEL_M); 1929 break; 1930 1931 case SND_SOC_DAPM_POST_PMD: 1932 snd_soc_component_update_bits(component, RT5645_GEN_CTRL2, 1933 RT5645_MICBIAS1_POW_CTRL_SEL_MASK, 1934 RT5645_MICBIAS1_POW_CTRL_SEL_A); 1935 break; 1936 1937 default: 1938 return 0; 1939 } 1940 1941 return 0; 1942 } 1943 1944 static int rt5645_set_micbias2_event(struct snd_soc_dapm_widget *w, 1945 struct snd_kcontrol *k, int event) 1946 { 1947 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1948 1949 switch (event) { 1950 case SND_SOC_DAPM_PRE_PMU: 1951 snd_soc_component_update_bits(component, RT5645_GEN_CTRL2, 1952 RT5645_MICBIAS2_POW_CTRL_SEL_MASK, 1953 RT5645_MICBIAS2_POW_CTRL_SEL_M); 1954 break; 1955 1956 case SND_SOC_DAPM_POST_PMD: 1957 snd_soc_component_update_bits(component, RT5645_GEN_CTRL2, 1958 RT5645_MICBIAS2_POW_CTRL_SEL_MASK, 1959 RT5645_MICBIAS2_POW_CTRL_SEL_A); 1960 break; 1961 1962 default: 1963 return 0; 1964 } 1965 1966 return 0; 1967 } 1968 1969 static const struct snd_soc_dapm_widget rt5645_dapm_widgets[] = { 1970 SND_SOC_DAPM_SUPPLY("LDO2", RT5645_PWR_MIXER, 1971 RT5645_PWR_LDO2_BIT, 0, NULL, 0), 1972 SND_SOC_DAPM_SUPPLY("PLL1", RT5645_PWR_ANLG2, 1973 RT5645_PWR_PLL_BIT, 0, NULL, 0), 1974 1975 SND_SOC_DAPM_SUPPLY("JD Power", RT5645_PWR_ANLG2, 1976 RT5645_PWR_JD1_BIT, 0, NULL, 0), 1977 SND_SOC_DAPM_SUPPLY("Mic Det Power", RT5645_PWR_VOL, 1978 RT5645_PWR_MIC_DET_BIT, 0, NULL, 0), 1979 1980 /* ASRC */ 1981 SND_SOC_DAPM_SUPPLY_S("I2S1 ASRC", 1, RT5645_ASRC_1, 1982 11, 0, NULL, 0), 1983 SND_SOC_DAPM_SUPPLY_S("I2S2 ASRC", 1, RT5645_ASRC_1, 1984 12, 0, NULL, 0), 1985 SND_SOC_DAPM_SUPPLY_S("DAC STO ASRC", 1, RT5645_ASRC_1, 1986 10, 0, NULL, 0), 1987 SND_SOC_DAPM_SUPPLY_S("DAC MONO L ASRC", 1, RT5645_ASRC_1, 1988 9, 0, NULL, 0), 1989 SND_SOC_DAPM_SUPPLY_S("DAC MONO R ASRC", 1, RT5645_ASRC_1, 1990 8, 0, NULL, 0), 1991 SND_SOC_DAPM_SUPPLY_S("DMIC STO1 ASRC", 1, RT5645_ASRC_1, 1992 7, 0, NULL, 0), 1993 SND_SOC_DAPM_SUPPLY_S("DMIC MONO L ASRC", 1, RT5645_ASRC_1, 1994 5, 0, NULL, 0), 1995 SND_SOC_DAPM_SUPPLY_S("DMIC MONO R ASRC", 1, RT5645_ASRC_1, 1996 4, 0, NULL, 0), 1997 SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5645_ASRC_1, 1998 3, 0, NULL, 0), 1999 SND_SOC_DAPM_SUPPLY_S("ADC MONO L ASRC", 1, RT5645_ASRC_1, 2000 1, 0, NULL, 0), 2001 SND_SOC_DAPM_SUPPLY_S("ADC MONO R ASRC", 1, RT5645_ASRC_1, 2002 0, 0, NULL, 0), 2003 2004 /* Input Side */ 2005 /* micbias */ 2006 SND_SOC_DAPM_SUPPLY("micbias1", RT5645_PWR_ANLG2, 2007 RT5645_PWR_MB1_BIT, 0, rt5645_set_micbias1_event, 2008 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2009 SND_SOC_DAPM_SUPPLY("micbias2", RT5645_PWR_ANLG2, 2010 RT5645_PWR_MB2_BIT, 0, rt5645_set_micbias2_event, 2011 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2012 /* Input Lines */ 2013 SND_SOC_DAPM_INPUT("DMIC L1"), 2014 SND_SOC_DAPM_INPUT("DMIC R1"), 2015 SND_SOC_DAPM_INPUT("DMIC L2"), 2016 SND_SOC_DAPM_INPUT("DMIC R2"), 2017 2018 SND_SOC_DAPM_INPUT("IN1P"), 2019 SND_SOC_DAPM_INPUT("IN1N"), 2020 SND_SOC_DAPM_INPUT("IN2P"), 2021 SND_SOC_DAPM_INPUT("IN2N"), 2022 2023 SND_SOC_DAPM_INPUT("Haptic Generator"), 2024 2025 SND_SOC_DAPM_PGA("DMIC1", SND_SOC_NOPM, 0, 0, NULL, 0), 2026 SND_SOC_DAPM_PGA("DMIC2", SND_SOC_NOPM, 0, 0, NULL, 0), 2027 SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0, 2028 set_dmic_clk, SND_SOC_DAPM_PRE_PMU), 2029 SND_SOC_DAPM_SUPPLY("DMIC1 Power", RT5645_DMIC_CTRL1, 2030 RT5645_DMIC_1_EN_SFT, 0, NULL, 0), 2031 SND_SOC_DAPM_SUPPLY("DMIC2 Power", RT5645_DMIC_CTRL1, 2032 RT5645_DMIC_2_EN_SFT, 0, NULL, 0), 2033 /* Boost */ 2034 SND_SOC_DAPM_PGA("BST1", RT5645_PWR_ANLG2, 2035 RT5645_PWR_BST1_BIT, 0, NULL, 0), 2036 SND_SOC_DAPM_PGA_E("BST2", RT5645_PWR_ANLG2, 2037 RT5645_PWR_BST2_BIT, 0, NULL, 0, rt5645_bst2_event, 2038 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU), 2039 /* Input Volume */ 2040 SND_SOC_DAPM_PGA("INL VOL", RT5645_PWR_VOL, 2041 RT5645_PWR_IN_L_BIT, 0, NULL, 0), 2042 SND_SOC_DAPM_PGA("INR VOL", RT5645_PWR_VOL, 2043 RT5645_PWR_IN_R_BIT, 0, NULL, 0), 2044 /* REC Mixer */ 2045 SND_SOC_DAPM_MIXER("RECMIXL", RT5645_PWR_MIXER, RT5645_PWR_RM_L_BIT, 2046 0, rt5645_rec_l_mix, ARRAY_SIZE(rt5645_rec_l_mix)), 2047 SND_SOC_DAPM_MIXER("RECMIXR", RT5645_PWR_MIXER, RT5645_PWR_RM_R_BIT, 2048 0, rt5645_rec_r_mix, ARRAY_SIZE(rt5645_rec_r_mix)), 2049 /* ADCs */ 2050 SND_SOC_DAPM_ADC("ADC L", NULL, SND_SOC_NOPM, 0, 0), 2051 SND_SOC_DAPM_ADC("ADC R", NULL, SND_SOC_NOPM, 0, 0), 2052 2053 SND_SOC_DAPM_SUPPLY("ADC L power", RT5645_PWR_DIG1, 2054 RT5645_PWR_ADC_L_BIT, 0, NULL, 0), 2055 SND_SOC_DAPM_SUPPLY("ADC R power", RT5645_PWR_DIG1, 2056 RT5645_PWR_ADC_R_BIT, 0, NULL, 0), 2057 2058 /* ADC Mux */ 2059 SND_SOC_DAPM_MUX("Stereo1 DMIC Mux", SND_SOC_NOPM, 0, 0, 2060 &rt5645_sto1_dmic_mux), 2061 SND_SOC_DAPM_MUX("Stereo1 ADC L2 Mux", SND_SOC_NOPM, 0, 0, 2062 &rt5645_sto_adc2_mux), 2063 SND_SOC_DAPM_MUX("Stereo1 ADC R2 Mux", SND_SOC_NOPM, 0, 0, 2064 &rt5645_sto_adc2_mux), 2065 SND_SOC_DAPM_MUX("Stereo1 ADC L1 Mux", SND_SOC_NOPM, 0, 0, 2066 &rt5645_sto_adc1_mux), 2067 SND_SOC_DAPM_MUX("Stereo1 ADC R1 Mux", SND_SOC_NOPM, 0, 0, 2068 &rt5645_sto_adc1_mux), 2069 SND_SOC_DAPM_MUX("Mono DMIC L Mux", SND_SOC_NOPM, 0, 0, 2070 &rt5645_mono_dmic_l_mux), 2071 SND_SOC_DAPM_MUX("Mono DMIC R Mux", SND_SOC_NOPM, 0, 0, 2072 &rt5645_mono_dmic_r_mux), 2073 SND_SOC_DAPM_MUX("Mono ADC L2 Mux", SND_SOC_NOPM, 0, 0, 2074 &rt5645_mono_adc_l2_mux), 2075 SND_SOC_DAPM_MUX("Mono ADC L1 Mux", SND_SOC_NOPM, 0, 0, 2076 &rt5645_mono_adc_l1_mux), 2077 SND_SOC_DAPM_MUX("Mono ADC R1 Mux", SND_SOC_NOPM, 0, 0, 2078 &rt5645_mono_adc_r1_mux), 2079 SND_SOC_DAPM_MUX("Mono ADC R2 Mux", SND_SOC_NOPM, 0, 0, 2080 &rt5645_mono_adc_r2_mux), 2081 /* ADC Mixer */ 2082 2083 SND_SOC_DAPM_SUPPLY_S("adc stereo1 filter", 1, RT5645_PWR_DIG2, 2084 RT5645_PWR_ADC_S1F_BIT, 0, NULL, 0), 2085 SND_SOC_DAPM_MIXER_E("Sto1 ADC MIXL", SND_SOC_NOPM, 0, 0, 2086 rt5645_sto1_adc_l_mix, ARRAY_SIZE(rt5645_sto1_adc_l_mix), 2087 NULL, 0), 2088 SND_SOC_DAPM_MIXER_E("Sto1 ADC MIXR", SND_SOC_NOPM, 0, 0, 2089 rt5645_sto1_adc_r_mix, ARRAY_SIZE(rt5645_sto1_adc_r_mix), 2090 NULL, 0), 2091 SND_SOC_DAPM_SUPPLY_S("adc mono left filter", 1, RT5645_PWR_DIG2, 2092 RT5645_PWR_ADC_MF_L_BIT, 0, NULL, 0), 2093 SND_SOC_DAPM_MIXER_E("Mono ADC MIXL", SND_SOC_NOPM, 0, 0, 2094 rt5645_mono_adc_l_mix, ARRAY_SIZE(rt5645_mono_adc_l_mix), 2095 NULL, 0), 2096 SND_SOC_DAPM_SUPPLY_S("adc mono right filter", 1, RT5645_PWR_DIG2, 2097 RT5645_PWR_ADC_MF_R_BIT, 0, NULL, 0), 2098 SND_SOC_DAPM_MIXER_E("Mono ADC MIXR", SND_SOC_NOPM, 0, 0, 2099 rt5645_mono_adc_r_mix, ARRAY_SIZE(rt5645_mono_adc_r_mix), 2100 NULL, 0), 2101 2102 /* ADC PGA */ 2103 SND_SOC_DAPM_PGA("Stereo1 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0), 2104 SND_SOC_DAPM_PGA("Stereo1 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0), 2105 SND_SOC_DAPM_PGA("Sto2 ADC LR MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 2106 SND_SOC_DAPM_PGA("VAD_ADC", SND_SOC_NOPM, 0, 0, NULL, 0), 2107 SND_SOC_DAPM_PGA("IF_ADC1", SND_SOC_NOPM, 0, 0, NULL, 0), 2108 SND_SOC_DAPM_PGA("IF_ADC2", SND_SOC_NOPM, 0, 0, NULL, 0), 2109 SND_SOC_DAPM_PGA("IF1_ADC1", SND_SOC_NOPM, 0, 0, NULL, 0), 2110 SND_SOC_DAPM_PGA("IF1_ADC2", SND_SOC_NOPM, 0, 0, NULL, 0), 2111 SND_SOC_DAPM_PGA("IF1_ADC3", SND_SOC_NOPM, 0, 0, NULL, 0), 2112 SND_SOC_DAPM_PGA("IF1_ADC4", SND_SOC_NOPM, 0, 0, NULL, 0), 2113 2114 /* IF1 2 Mux */ 2115 SND_SOC_DAPM_MUX("IF2 ADC Mux", SND_SOC_NOPM, 2116 0, 0, &rt5645_if2_adc_in_mux), 2117 2118 /* Digital Interface */ 2119 SND_SOC_DAPM_SUPPLY("I2S1", RT5645_PWR_DIG1, 2120 RT5645_PWR_I2S1_BIT, 0, NULL, 0), 2121 SND_SOC_DAPM_PGA("IF1 DAC0", SND_SOC_NOPM, 0, 0, NULL, 0), 2122 SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0), 2123 SND_SOC_DAPM_PGA("IF1 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0), 2124 SND_SOC_DAPM_PGA("IF1 DAC3", SND_SOC_NOPM, 0, 0, NULL, 0), 2125 SND_SOC_DAPM_PGA("IF1 ADC", SND_SOC_NOPM, 0, 0, NULL, 0), 2126 SND_SOC_DAPM_PGA("IF1 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0), 2127 SND_SOC_DAPM_PGA("IF1 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0), 2128 SND_SOC_DAPM_SUPPLY("I2S2", RT5645_PWR_DIG1, 2129 RT5645_PWR_I2S2_BIT, 0, NULL, 0), 2130 SND_SOC_DAPM_PGA("IF2 DAC", SND_SOC_NOPM, 0, 0, NULL, 0), 2131 SND_SOC_DAPM_PGA("IF2 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0), 2132 SND_SOC_DAPM_PGA("IF2 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0), 2133 SND_SOC_DAPM_PGA("IF2 ADC", SND_SOC_NOPM, 0, 0, NULL, 0), 2134 2135 /* Digital Interface Select */ 2136 SND_SOC_DAPM_MUX("VAD ADC Mux", SND_SOC_NOPM, 2137 0, 0, &rt5645_vad_adc_mux), 2138 2139 /* Audio Interface */ 2140 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0), 2141 SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0), 2142 SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0), 2143 SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0), 2144 2145 /* Output Side */ 2146 /* DAC mixer before sound effect */ 2147 SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0, 2148 rt5645_dac_l_mix, ARRAY_SIZE(rt5645_dac_l_mix)), 2149 SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0, 2150 rt5645_dac_r_mix, ARRAY_SIZE(rt5645_dac_r_mix)), 2151 2152 /* DAC2 channel Mux */ 2153 SND_SOC_DAPM_MUX("DAC L2 Mux", SND_SOC_NOPM, 0, 0, &rt5645_dac_l2_mux), 2154 SND_SOC_DAPM_MUX("DAC R2 Mux", SND_SOC_NOPM, 0, 0, &rt5645_dac_r2_mux), 2155 SND_SOC_DAPM_PGA("DAC L2 Volume", RT5645_PWR_DIG1, 2156 RT5645_PWR_DAC_L2_BIT, 0, NULL, 0), 2157 SND_SOC_DAPM_PGA("DAC R2 Volume", RT5645_PWR_DIG1, 2158 RT5645_PWR_DAC_R2_BIT, 0, NULL, 0), 2159 2160 SND_SOC_DAPM_MUX("DAC1 L Mux", SND_SOC_NOPM, 0, 0, &rt5645_dac1l_mux), 2161 SND_SOC_DAPM_MUX("DAC1 R Mux", SND_SOC_NOPM, 0, 0, &rt5645_dac1r_mux), 2162 2163 /* DAC Mixer */ 2164 SND_SOC_DAPM_SUPPLY_S("dac stereo1 filter", 1, RT5645_PWR_DIG2, 2165 RT5645_PWR_DAC_S1F_BIT, 0, NULL, 0), 2166 SND_SOC_DAPM_SUPPLY_S("dac mono left filter", 1, RT5645_PWR_DIG2, 2167 RT5645_PWR_DAC_MF_L_BIT, 0, NULL, 0), 2168 SND_SOC_DAPM_SUPPLY_S("dac mono right filter", 1, RT5645_PWR_DIG2, 2169 RT5645_PWR_DAC_MF_R_BIT, 0, NULL, 0), 2170 SND_SOC_DAPM_MIXER("Stereo DAC MIXL", SND_SOC_NOPM, 0, 0, 2171 rt5645_sto_dac_l_mix, ARRAY_SIZE(rt5645_sto_dac_l_mix)), 2172 SND_SOC_DAPM_MIXER("Stereo DAC MIXR", SND_SOC_NOPM, 0, 0, 2173 rt5645_sto_dac_r_mix, ARRAY_SIZE(rt5645_sto_dac_r_mix)), 2174 SND_SOC_DAPM_MIXER("Mono DAC MIXL", SND_SOC_NOPM, 0, 0, 2175 rt5645_mono_dac_l_mix, ARRAY_SIZE(rt5645_mono_dac_l_mix)), 2176 SND_SOC_DAPM_MIXER("Mono DAC MIXR", SND_SOC_NOPM, 0, 0, 2177 rt5645_mono_dac_r_mix, ARRAY_SIZE(rt5645_mono_dac_r_mix)), 2178 SND_SOC_DAPM_MIXER("DAC MIXL", SND_SOC_NOPM, 0, 0, 2179 rt5645_dig_l_mix, ARRAY_SIZE(rt5645_dig_l_mix)), 2180 SND_SOC_DAPM_MIXER("DAC MIXR", SND_SOC_NOPM, 0, 0, 2181 rt5645_dig_r_mix, ARRAY_SIZE(rt5645_dig_r_mix)), 2182 2183 /* DACs */ 2184 SND_SOC_DAPM_DAC("DAC L1", NULL, RT5645_PWR_DIG1, RT5645_PWR_DAC_L1_BIT, 2185 0), 2186 SND_SOC_DAPM_DAC("DAC L2", NULL, RT5645_PWR_DIG1, RT5645_PWR_DAC_L2_BIT, 2187 0), 2188 SND_SOC_DAPM_DAC("DAC R1", NULL, RT5645_PWR_DIG1, RT5645_PWR_DAC_R1_BIT, 2189 0), 2190 SND_SOC_DAPM_DAC("DAC R2", NULL, RT5645_PWR_DIG1, RT5645_PWR_DAC_R2_BIT, 2191 0), 2192 /* OUT Mixer */ 2193 SND_SOC_DAPM_MIXER("SPK MIXL", RT5645_PWR_MIXER, RT5645_PWR_SM_L_BIT, 2194 0, rt5645_spk_l_mix, ARRAY_SIZE(rt5645_spk_l_mix)), 2195 SND_SOC_DAPM_MIXER("SPK MIXR", RT5645_PWR_MIXER, RT5645_PWR_SM_R_BIT, 2196 0, rt5645_spk_r_mix, ARRAY_SIZE(rt5645_spk_r_mix)), 2197 SND_SOC_DAPM_MIXER("OUT MIXL", RT5645_PWR_MIXER, RT5645_PWR_OM_L_BIT, 2198 0, rt5645_out_l_mix, ARRAY_SIZE(rt5645_out_l_mix)), 2199 SND_SOC_DAPM_MIXER("OUT MIXR", RT5645_PWR_MIXER, RT5645_PWR_OM_R_BIT, 2200 0, rt5645_out_r_mix, ARRAY_SIZE(rt5645_out_r_mix)), 2201 /* Ouput Volume */ 2202 SND_SOC_DAPM_SWITCH("SPKVOL L", RT5645_PWR_VOL, RT5645_PWR_SV_L_BIT, 0, 2203 &spk_l_vol_control), 2204 SND_SOC_DAPM_SWITCH("SPKVOL R", RT5645_PWR_VOL, RT5645_PWR_SV_R_BIT, 0, 2205 &spk_r_vol_control), 2206 SND_SOC_DAPM_MIXER("HPOVOL MIXL", RT5645_PWR_VOL, RT5645_PWR_HV_L_BIT, 2207 0, rt5645_hpvoll_mix, ARRAY_SIZE(rt5645_hpvoll_mix)), 2208 SND_SOC_DAPM_MIXER("HPOVOL MIXR", RT5645_PWR_VOL, RT5645_PWR_HV_R_BIT, 2209 0, rt5645_hpvolr_mix, ARRAY_SIZE(rt5645_hpvolr_mix)), 2210 SND_SOC_DAPM_SUPPLY("HPOVOL MIXL Power", RT5645_PWR_MIXER, 2211 RT5645_PWR_HM_L_BIT, 0, NULL, 0), 2212 SND_SOC_DAPM_SUPPLY("HPOVOL MIXR Power", RT5645_PWR_MIXER, 2213 RT5645_PWR_HM_R_BIT, 0, NULL, 0), 2214 SND_SOC_DAPM_PGA("DAC 1", SND_SOC_NOPM, 0, 0, NULL, 0), 2215 SND_SOC_DAPM_PGA("DAC 2", SND_SOC_NOPM, 0, 0, NULL, 0), 2216 SND_SOC_DAPM_PGA("HPOVOL", SND_SOC_NOPM, 0, 0, NULL, 0), 2217 SND_SOC_DAPM_SWITCH("HPOVOL L", SND_SOC_NOPM, 0, 0, &hp_l_vol_control), 2218 SND_SOC_DAPM_SWITCH("HPOVOL R", SND_SOC_NOPM, 0, 0, &hp_r_vol_control), 2219 2220 /* HPO/LOUT/Mono Mixer */ 2221 SND_SOC_DAPM_MIXER("SPOL MIX", SND_SOC_NOPM, 0, 0, rt5645_spo_l_mix, 2222 ARRAY_SIZE(rt5645_spo_l_mix)), 2223 SND_SOC_DAPM_MIXER("SPOR MIX", SND_SOC_NOPM, 0, 0, rt5645_spo_r_mix, 2224 ARRAY_SIZE(rt5645_spo_r_mix)), 2225 SND_SOC_DAPM_MIXER("HPO MIX", SND_SOC_NOPM, 0, 0, rt5645_hpo_mix, 2226 ARRAY_SIZE(rt5645_hpo_mix)), 2227 SND_SOC_DAPM_MIXER("LOUT MIX", SND_SOC_NOPM, 0, 0, rt5645_lout_mix, 2228 ARRAY_SIZE(rt5645_lout_mix)), 2229 2230 SND_SOC_DAPM_PGA_S("HP amp", 1, SND_SOC_NOPM, 0, 0, rt5645_hp_event, 2231 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU), 2232 SND_SOC_DAPM_PGA_S("LOUT amp", 1, SND_SOC_NOPM, 0, 0, rt5645_lout_event, 2233 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU), 2234 SND_SOC_DAPM_PGA_S("SPK amp", 2, SND_SOC_NOPM, 0, 0, rt5645_spk_event, 2235 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU), 2236 2237 /* PDM */ 2238 SND_SOC_DAPM_SUPPLY("PDM1 Power", RT5645_PWR_DIG2, RT5645_PWR_PDM1_BIT, 2239 0, NULL, 0), 2240 SND_SOC_DAPM_MUX("PDM1 L Mux", SND_SOC_NOPM, 0, 0, &rt5645_pdm1_l_mux), 2241 SND_SOC_DAPM_MUX("PDM1 R Mux", SND_SOC_NOPM, 0, 0, &rt5645_pdm1_r_mux), 2242 2243 SND_SOC_DAPM_SWITCH("PDM1 L", SND_SOC_NOPM, 0, 0, &pdm1_l_vol_control), 2244 SND_SOC_DAPM_SWITCH("PDM1 R", SND_SOC_NOPM, 0, 0, &pdm1_r_vol_control), 2245 2246 /* Output Lines */ 2247 SND_SOC_DAPM_OUTPUT("HPOL"), 2248 SND_SOC_DAPM_OUTPUT("HPOR"), 2249 SND_SOC_DAPM_OUTPUT("LOUTL"), 2250 SND_SOC_DAPM_OUTPUT("LOUTR"), 2251 SND_SOC_DAPM_OUTPUT("PDM1L"), 2252 SND_SOC_DAPM_OUTPUT("PDM1R"), 2253 SND_SOC_DAPM_OUTPUT("SPOL"), 2254 SND_SOC_DAPM_OUTPUT("SPOR"), 2255 }; 2256 2257 static const struct snd_soc_dapm_widget rt5645_specific_dapm_widgets[] = { 2258 SND_SOC_DAPM_MUX("RT5645 IF1 DAC1 L Mux", SND_SOC_NOPM, 0, 0, 2259 &rt5645_if1_dac0_tdm_sel_mux), 2260 SND_SOC_DAPM_MUX("RT5645 IF1 DAC1 R Mux", SND_SOC_NOPM, 0, 0, 2261 &rt5645_if1_dac1_tdm_sel_mux), 2262 SND_SOC_DAPM_MUX("RT5645 IF1 DAC2 L Mux", SND_SOC_NOPM, 0, 0, 2263 &rt5645_if1_dac2_tdm_sel_mux), 2264 SND_SOC_DAPM_MUX("RT5645 IF1 DAC2 R Mux", SND_SOC_NOPM, 0, 0, 2265 &rt5645_if1_dac3_tdm_sel_mux), 2266 SND_SOC_DAPM_MUX("RT5645 IF1 ADC Mux", SND_SOC_NOPM, 2267 0, 0, &rt5645_if1_adc_in_mux), 2268 SND_SOC_DAPM_MUX("RT5645 IF1 ADC1 Swap Mux", SND_SOC_NOPM, 2269 0, 0, &rt5645_if1_adc1_in_mux), 2270 SND_SOC_DAPM_MUX("RT5645 IF1 ADC2 Swap Mux", SND_SOC_NOPM, 2271 0, 0, &rt5645_if1_adc2_in_mux), 2272 SND_SOC_DAPM_MUX("RT5645 IF1 ADC3 Swap Mux", SND_SOC_NOPM, 2273 0, 0, &rt5645_if1_adc3_in_mux), 2274 }; 2275 2276 static const struct snd_soc_dapm_widget rt5650_specific_dapm_widgets[] = { 2277 SND_SOC_DAPM_MUX("A DAC1 L Mux", SND_SOC_NOPM, 2278 0, 0, &rt5650_a_dac1_l_mux), 2279 SND_SOC_DAPM_MUX("A DAC1 R Mux", SND_SOC_NOPM, 2280 0, 0, &rt5650_a_dac1_r_mux), 2281 SND_SOC_DAPM_MUX("A DAC2 L Mux", SND_SOC_NOPM, 2282 0, 0, &rt5650_a_dac2_l_mux), 2283 SND_SOC_DAPM_MUX("A DAC2 R Mux", SND_SOC_NOPM, 2284 0, 0, &rt5650_a_dac2_r_mux), 2285 2286 SND_SOC_DAPM_MUX("RT5650 IF1 ADC1 Swap Mux", SND_SOC_NOPM, 2287 0, 0, &rt5650_if1_adc1_in_mux), 2288 SND_SOC_DAPM_MUX("RT5650 IF1 ADC2 Swap Mux", SND_SOC_NOPM, 2289 0, 0, &rt5650_if1_adc2_in_mux), 2290 SND_SOC_DAPM_MUX("RT5650 IF1 ADC3 Swap Mux", SND_SOC_NOPM, 2291 0, 0, &rt5650_if1_adc3_in_mux), 2292 SND_SOC_DAPM_MUX("RT5650 IF1 ADC Mux", SND_SOC_NOPM, 2293 0, 0, &rt5650_if1_adc_in_mux), 2294 2295 SND_SOC_DAPM_MUX("RT5650 IF1 DAC1 L Mux", SND_SOC_NOPM, 0, 0, 2296 &rt5650_if1_dac0_tdm_sel_mux), 2297 SND_SOC_DAPM_MUX("RT5650 IF1 DAC1 R Mux", SND_SOC_NOPM, 0, 0, 2298 &rt5650_if1_dac1_tdm_sel_mux), 2299 SND_SOC_DAPM_MUX("RT5650 IF1 DAC2 L Mux", SND_SOC_NOPM, 0, 0, 2300 &rt5650_if1_dac2_tdm_sel_mux), 2301 SND_SOC_DAPM_MUX("RT5650 IF1 DAC2 R Mux", SND_SOC_NOPM, 0, 0, 2302 &rt5650_if1_dac3_tdm_sel_mux), 2303 }; 2304 2305 static const struct snd_soc_dapm_route rt5645_dapm_routes[] = { 2306 { "adc stereo1 filter", NULL, "ADC STO1 ASRC", is_using_asrc }, 2307 { "adc mono left filter", NULL, "ADC MONO L ASRC", is_using_asrc }, 2308 { "adc mono right filter", NULL, "ADC MONO R ASRC", is_using_asrc }, 2309 { "dac mono left filter", NULL, "DAC MONO L ASRC", is_using_asrc }, 2310 { "dac mono right filter", NULL, "DAC MONO R ASRC", is_using_asrc }, 2311 { "dac stereo1 filter", NULL, "DAC STO ASRC", is_using_asrc }, 2312 2313 { "I2S1", NULL, "I2S1 ASRC" }, 2314 { "I2S2", NULL, "I2S2 ASRC" }, 2315 2316 { "IN1P", NULL, "LDO2" }, 2317 { "IN2P", NULL, "LDO2" }, 2318 2319 { "DMIC1", NULL, "DMIC L1" }, 2320 { "DMIC1", NULL, "DMIC R1" }, 2321 { "DMIC2", NULL, "DMIC L2" }, 2322 { "DMIC2", NULL, "DMIC R2" }, 2323 2324 { "BST1", NULL, "IN1P" }, 2325 { "BST1", NULL, "IN1N" }, 2326 { "BST1", NULL, "JD Power" }, 2327 { "BST1", NULL, "Mic Det Power" }, 2328 { "BST2", NULL, "IN2P" }, 2329 { "BST2", NULL, "IN2N" }, 2330 2331 { "INL VOL", NULL, "IN2P" }, 2332 { "INR VOL", NULL, "IN2N" }, 2333 2334 { "RECMIXL", "HPOL Switch", "HPOL" }, 2335 { "RECMIXL", "INL Switch", "INL VOL" }, 2336 { "RECMIXL", "BST2 Switch", "BST2" }, 2337 { "RECMIXL", "BST1 Switch", "BST1" }, 2338 { "RECMIXL", "OUT MIXL Switch", "OUT MIXL" }, 2339 2340 { "RECMIXR", "HPOR Switch", "HPOR" }, 2341 { "RECMIXR", "INR Switch", "INR VOL" }, 2342 { "RECMIXR", "BST2 Switch", "BST2" }, 2343 { "RECMIXR", "BST1 Switch", "BST1" }, 2344 { "RECMIXR", "OUT MIXR Switch", "OUT MIXR" }, 2345 2346 { "ADC L", NULL, "RECMIXL" }, 2347 { "ADC L", NULL, "ADC L power" }, 2348 { "ADC R", NULL, "RECMIXR" }, 2349 { "ADC R", NULL, "ADC R power" }, 2350 2351 {"DMIC L1", NULL, "DMIC CLK"}, 2352 {"DMIC L1", NULL, "DMIC1 Power"}, 2353 {"DMIC R1", NULL, "DMIC CLK"}, 2354 {"DMIC R1", NULL, "DMIC1 Power"}, 2355 {"DMIC L2", NULL, "DMIC CLK"}, 2356 {"DMIC L2", NULL, "DMIC2 Power"}, 2357 {"DMIC R2", NULL, "DMIC CLK"}, 2358 {"DMIC R2", NULL, "DMIC2 Power"}, 2359 2360 { "Stereo1 DMIC Mux", "DMIC1", "DMIC1" }, 2361 { "Stereo1 DMIC Mux", "DMIC2", "DMIC2" }, 2362 { "Stereo1 DMIC Mux", NULL, "DMIC STO1 ASRC" }, 2363 2364 { "Mono DMIC L Mux", "DMIC1", "DMIC L1" }, 2365 { "Mono DMIC L Mux", "DMIC2", "DMIC L2" }, 2366 { "Mono DMIC L Mux", NULL, "DMIC MONO L ASRC" }, 2367 2368 { "Mono DMIC R Mux", "DMIC1", "DMIC R1" }, 2369 { "Mono DMIC R Mux", "DMIC2", "DMIC R2" }, 2370 { "Mono DMIC R Mux", NULL, "DMIC MONO R ASRC" }, 2371 2372 { "Stereo1 ADC L2 Mux", "DMIC", "Stereo1 DMIC Mux" }, 2373 { "Stereo1 ADC L2 Mux", "DAC MIX", "DAC MIXL" }, 2374 { "Stereo1 ADC L1 Mux", "ADC", "ADC L" }, 2375 { "Stereo1 ADC L1 Mux", "DAC MIX", "DAC MIXL" }, 2376 2377 { "Stereo1 ADC R1 Mux", "ADC", "ADC R" }, 2378 { "Stereo1 ADC R1 Mux", "DAC MIX", "DAC MIXR" }, 2379 { "Stereo1 ADC R2 Mux", "DMIC", "Stereo1 DMIC Mux" }, 2380 { "Stereo1 ADC R2 Mux", "DAC MIX", "DAC MIXR" }, 2381 2382 { "Mono ADC L2 Mux", "DMIC", "Mono DMIC L Mux" }, 2383 { "Mono ADC L2 Mux", "Mono DAC MIXL", "Mono DAC MIXL" }, 2384 { "Mono ADC L1 Mux", "Mono DAC MIXL", "Mono DAC MIXL" }, 2385 { "Mono ADC L1 Mux", "ADC", "ADC L" }, 2386 2387 { "Mono ADC R1 Mux", "Mono DAC MIXR", "Mono DAC MIXR" }, 2388 { "Mono ADC R1 Mux", "ADC", "ADC R" }, 2389 { "Mono ADC R2 Mux", "DMIC", "Mono DMIC R Mux" }, 2390 { "Mono ADC R2 Mux", "Mono DAC MIXR", "Mono DAC MIXR" }, 2391 2392 { "Sto1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC L1 Mux" }, 2393 { "Sto1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC L2 Mux" }, 2394 { "Sto1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC R1 Mux" }, 2395 { "Sto1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC R2 Mux" }, 2396 2397 { "Stereo1 ADC MIXL", NULL, "Sto1 ADC MIXL" }, 2398 { "Stereo1 ADC MIXL", NULL, "adc stereo1 filter" }, 2399 { "adc stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll }, 2400 2401 { "Stereo1 ADC MIXR", NULL, "Sto1 ADC MIXR" }, 2402 { "Stereo1 ADC MIXR", NULL, "adc stereo1 filter" }, 2403 { "adc stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll }, 2404 2405 { "Mono ADC MIXL", "ADC1 Switch", "Mono ADC L1 Mux" }, 2406 { "Mono ADC MIXL", "ADC2 Switch", "Mono ADC L2 Mux" }, 2407 { "Mono ADC MIXL", NULL, "adc mono left filter" }, 2408 { "adc mono left filter", NULL, "PLL1", is_sys_clk_from_pll }, 2409 2410 { "Mono ADC MIXR", "ADC1 Switch", "Mono ADC R1 Mux" }, 2411 { "Mono ADC MIXR", "ADC2 Switch", "Mono ADC R2 Mux" }, 2412 { "Mono ADC MIXR", NULL, "adc mono right filter" }, 2413 { "adc mono right filter", NULL, "PLL1", is_sys_clk_from_pll }, 2414 2415 { "VAD ADC Mux", "Sto1 ADC L", "Stereo1 ADC MIXL" }, 2416 { "VAD ADC Mux", "Mono ADC L", "Mono ADC MIXL" }, 2417 { "VAD ADC Mux", "Mono ADC R", "Mono ADC MIXR" }, 2418 2419 { "IF_ADC1", NULL, "Stereo1 ADC MIXL" }, 2420 { "IF_ADC1", NULL, "Stereo1 ADC MIXR" }, 2421 { "IF_ADC2", NULL, "Mono ADC MIXL" }, 2422 { "IF_ADC2", NULL, "Mono ADC MIXR" }, 2423 { "VAD_ADC", NULL, "VAD ADC Mux" }, 2424 2425 { "IF2 ADC Mux", "IF_ADC1", "IF_ADC1" }, 2426 { "IF2 ADC Mux", "IF_ADC2", "IF_ADC2" }, 2427 { "IF2 ADC Mux", "VAD_ADC", "VAD_ADC" }, 2428 2429 { "IF1 ADC", NULL, "I2S1" }, 2430 { "IF2 ADC", NULL, "I2S2" }, 2431 { "IF2 ADC", NULL, "IF2 ADC Mux" }, 2432 2433 { "AIF2TX", NULL, "IF2 ADC" }, 2434 2435 { "IF1 DAC0", NULL, "AIF1RX" }, 2436 { "IF1 DAC1", NULL, "AIF1RX" }, 2437 { "IF1 DAC2", NULL, "AIF1RX" }, 2438 { "IF1 DAC3", NULL, "AIF1RX" }, 2439 { "IF2 DAC", NULL, "AIF2RX" }, 2440 2441 { "IF1 DAC0", NULL, "I2S1" }, 2442 { "IF1 DAC1", NULL, "I2S1" }, 2443 { "IF1 DAC2", NULL, "I2S1" }, 2444 { "IF1 DAC3", NULL, "I2S1" }, 2445 { "IF2 DAC", NULL, "I2S2" }, 2446 2447 { "IF2 DAC L", NULL, "IF2 DAC" }, 2448 { "IF2 DAC R", NULL, "IF2 DAC" }, 2449 2450 { "DAC1 L Mux", "IF2 DAC", "IF2 DAC L" }, 2451 { "DAC1 R Mux", "IF2 DAC", "IF2 DAC R" }, 2452 2453 { "DAC1 MIXL", "Stereo ADC Switch", "Stereo1 ADC MIXL" }, 2454 { "DAC1 MIXL", "DAC1 Switch", "DAC1 L Mux" }, 2455 { "DAC1 MIXL", NULL, "dac stereo1 filter" }, 2456 { "DAC1 MIXR", "Stereo ADC Switch", "Stereo1 ADC MIXR" }, 2457 { "DAC1 MIXR", "DAC1 Switch", "DAC1 R Mux" }, 2458 { "DAC1 MIXR", NULL, "dac stereo1 filter" }, 2459 2460 { "DAC L2 Mux", "IF2 DAC", "IF2 DAC L" }, 2461 { "DAC L2 Mux", "Mono ADC", "Mono ADC MIXL" }, 2462 { "DAC L2 Mux", "VAD_ADC", "VAD_ADC" }, 2463 { "DAC L2 Volume", NULL, "DAC L2 Mux" }, 2464 { "DAC L2 Volume", NULL, "dac mono left filter" }, 2465 2466 { "DAC R2 Mux", "IF2 DAC", "IF2 DAC R" }, 2467 { "DAC R2 Mux", "Mono ADC", "Mono ADC MIXR" }, 2468 { "DAC R2 Mux", "Haptic", "Haptic Generator" }, 2469 { "DAC R2 Volume", NULL, "DAC R2 Mux" }, 2470 { "DAC R2 Volume", NULL, "dac mono right filter" }, 2471 2472 { "Stereo DAC MIXL", "DAC L1 Switch", "DAC1 MIXL" }, 2473 { "Stereo DAC MIXL", "DAC R1 Switch", "DAC1 MIXR" }, 2474 { "Stereo DAC MIXL", "DAC L2 Switch", "DAC L2 Volume" }, 2475 { "Stereo DAC MIXL", NULL, "dac stereo1 filter" }, 2476 { "Stereo DAC MIXR", "DAC R1 Switch", "DAC1 MIXR" }, 2477 { "Stereo DAC MIXR", "DAC L1 Switch", "DAC1 MIXL" }, 2478 { "Stereo DAC MIXR", "DAC R2 Switch", "DAC R2 Volume" }, 2479 { "Stereo DAC MIXR", NULL, "dac stereo1 filter" }, 2480 2481 { "Mono DAC MIXL", "DAC L1 Switch", "DAC1 MIXL" }, 2482 { "Mono DAC MIXL", "DAC L2 Switch", "DAC L2 Volume" }, 2483 { "Mono DAC MIXL", "DAC R2 Switch", "DAC R2 Volume" }, 2484 { "Mono DAC MIXL", NULL, "dac mono left filter" }, 2485 { "Mono DAC MIXR", "DAC R1 Switch", "DAC1 MIXR" }, 2486 { "Mono DAC MIXR", "DAC R2 Switch", "DAC R2 Volume" }, 2487 { "Mono DAC MIXR", "DAC L2 Switch", "DAC L2 Volume" }, 2488 { "Mono DAC MIXR", NULL, "dac mono right filter" }, 2489 2490 { "DAC MIXL", "Sto DAC Mix L Switch", "Stereo DAC MIXL" }, 2491 { "DAC MIXL", "DAC L2 Switch", "DAC L2 Volume" }, 2492 { "DAC MIXL", "DAC R2 Switch", "DAC R2 Volume" }, 2493 { "DAC MIXR", "Sto DAC Mix R Switch", "Stereo DAC MIXR" }, 2494 { "DAC MIXR", "DAC R2 Switch", "DAC R2 Volume" }, 2495 { "DAC MIXR", "DAC L2 Switch", "DAC L2 Volume" }, 2496 2497 { "DAC L1", NULL, "PLL1", is_sys_clk_from_pll }, 2498 { "DAC R1", NULL, "PLL1", is_sys_clk_from_pll }, 2499 { "DAC L2", NULL, "PLL1", is_sys_clk_from_pll }, 2500 { "DAC R2", NULL, "PLL1", is_sys_clk_from_pll }, 2501 2502 { "SPK MIXL", "BST1 Switch", "BST1" }, 2503 { "SPK MIXL", "INL Switch", "INL VOL" }, 2504 { "SPK MIXL", "DAC L1 Switch", "DAC L1" }, 2505 { "SPK MIXL", "DAC L2 Switch", "DAC L2" }, 2506 { "SPK MIXR", "BST2 Switch", "BST2" }, 2507 { "SPK MIXR", "INR Switch", "INR VOL" }, 2508 { "SPK MIXR", "DAC R1 Switch", "DAC R1" }, 2509 { "SPK MIXR", "DAC R2 Switch", "DAC R2" }, 2510 2511 { "OUT MIXL", "BST1 Switch", "BST1" }, 2512 { "OUT MIXL", "INL Switch", "INL VOL" }, 2513 { "OUT MIXL", "DAC L2 Switch", "DAC L2" }, 2514 { "OUT MIXL", "DAC L1 Switch", "DAC L1" }, 2515 2516 { "OUT MIXR", "BST2 Switch", "BST2" }, 2517 { "OUT MIXR", "INR Switch", "INR VOL" }, 2518 { "OUT MIXR", "DAC R2 Switch", "DAC R2" }, 2519 { "OUT MIXR", "DAC R1 Switch", "DAC R1" }, 2520 2521 { "HPOVOL MIXL", "DAC1 Switch", "DAC L1" }, 2522 { "HPOVOL MIXL", "DAC2 Switch", "DAC L2" }, 2523 { "HPOVOL MIXL", "INL Switch", "INL VOL" }, 2524 { "HPOVOL MIXL", "BST1 Switch", "BST1" }, 2525 { "HPOVOL MIXL", NULL, "HPOVOL MIXL Power" }, 2526 { "HPOVOL MIXR", "DAC1 Switch", "DAC R1" }, 2527 { "HPOVOL MIXR", "DAC2 Switch", "DAC R2" }, 2528 { "HPOVOL MIXR", "INR Switch", "INR VOL" }, 2529 { "HPOVOL MIXR", "BST2 Switch", "BST2" }, 2530 { "HPOVOL MIXR", NULL, "HPOVOL MIXR Power" }, 2531 2532 { "DAC 2", NULL, "DAC L2" }, 2533 { "DAC 2", NULL, "DAC R2" }, 2534 { "DAC 1", NULL, "DAC L1" }, 2535 { "DAC 1", NULL, "DAC R1" }, 2536 { "HPOVOL L", "Switch", "HPOVOL MIXL" }, 2537 { "HPOVOL R", "Switch", "HPOVOL MIXR" }, 2538 { "HPOVOL", NULL, "HPOVOL L" }, 2539 { "HPOVOL", NULL, "HPOVOL R" }, 2540 { "HPO MIX", "DAC1 Switch", "DAC 1" }, 2541 { "HPO MIX", "HPVOL Switch", "HPOVOL" }, 2542 2543 { "SPKVOL L", "Switch", "SPK MIXL" }, 2544 { "SPKVOL R", "Switch", "SPK MIXR" }, 2545 2546 { "SPOL MIX", "DAC L1 Switch", "DAC L1" }, 2547 { "SPOL MIX", "SPKVOL L Switch", "SPKVOL L" }, 2548 { "SPOR MIX", "DAC R1 Switch", "DAC R1" }, 2549 { "SPOR MIX", "SPKVOL R Switch", "SPKVOL R" }, 2550 2551 { "LOUT MIX", "DAC L1 Switch", "DAC L1" }, 2552 { "LOUT MIX", "DAC R1 Switch", "DAC R1" }, 2553 { "LOUT MIX", "OUTMIX L Switch", "OUT MIXL" }, 2554 { "LOUT MIX", "OUTMIX R Switch", "OUT MIXR" }, 2555 2556 { "PDM1 L Mux", "Stereo DAC", "Stereo DAC MIXL" }, 2557 { "PDM1 L Mux", "Mono DAC", "Mono DAC MIXL" }, 2558 { "PDM1 L Mux", NULL, "PDM1 Power" }, 2559 { "PDM1 R Mux", "Stereo DAC", "Stereo DAC MIXR" }, 2560 { "PDM1 R Mux", "Mono DAC", "Mono DAC MIXR" }, 2561 { "PDM1 R Mux", NULL, "PDM1 Power" }, 2562 2563 { "HP amp", NULL, "HPO MIX" }, 2564 { "HP amp", NULL, "JD Power" }, 2565 { "HP amp", NULL, "Mic Det Power" }, 2566 { "HP amp", NULL, "LDO2" }, 2567 { "HPOL", NULL, "HP amp" }, 2568 { "HPOR", NULL, "HP amp" }, 2569 2570 { "LOUT amp", NULL, "LOUT MIX" }, 2571 { "LOUTL", NULL, "LOUT amp" }, 2572 { "LOUTR", NULL, "LOUT amp" }, 2573 2574 { "PDM1 L", "Switch", "PDM1 L Mux" }, 2575 { "PDM1 R", "Switch", "PDM1 R Mux" }, 2576 2577 { "PDM1L", NULL, "PDM1 L" }, 2578 { "PDM1R", NULL, "PDM1 R" }, 2579 2580 { "SPK amp", NULL, "SPOL MIX" }, 2581 { "SPK amp", NULL, "SPOR MIX" }, 2582 { "SPOL", NULL, "SPK amp" }, 2583 { "SPOR", NULL, "SPK amp" }, 2584 }; 2585 2586 static const struct snd_soc_dapm_route rt5650_specific_dapm_routes[] = { 2587 { "A DAC1 L Mux", "DAC1", "DAC1 MIXL"}, 2588 { "A DAC1 L Mux", "Stereo DAC Mixer", "Stereo DAC MIXL"}, 2589 { "A DAC1 R Mux", "DAC1", "DAC1 MIXR"}, 2590 { "A DAC1 R Mux", "Stereo DAC Mixer", "Stereo DAC MIXR"}, 2591 2592 { "A DAC2 L Mux", "Stereo DAC Mixer", "Stereo DAC MIXL"}, 2593 { "A DAC2 L Mux", "Mono DAC Mixer", "Mono DAC MIXL"}, 2594 { "A DAC2 R Mux", "Stereo DAC Mixer", "Stereo DAC MIXR"}, 2595 { "A DAC2 R Mux", "Mono DAC Mixer", "Mono DAC MIXR"}, 2596 2597 { "DAC L1", NULL, "A DAC1 L Mux" }, 2598 { "DAC R1", NULL, "A DAC1 R Mux" }, 2599 { "DAC L2", NULL, "A DAC2 L Mux" }, 2600 { "DAC R2", NULL, "A DAC2 R Mux" }, 2601 2602 { "RT5650 IF1 ADC1 Swap Mux", "L/R", "IF_ADC1" }, 2603 { "RT5650 IF1 ADC1 Swap Mux", "R/L", "IF_ADC1" }, 2604 { "RT5650 IF1 ADC1 Swap Mux", "L/L", "IF_ADC1" }, 2605 { "RT5650 IF1 ADC1 Swap Mux", "R/R", "IF_ADC1" }, 2606 2607 { "RT5650 IF1 ADC2 Swap Mux", "L/R", "IF_ADC2" }, 2608 { "RT5650 IF1 ADC2 Swap Mux", "R/L", "IF_ADC2" }, 2609 { "RT5650 IF1 ADC2 Swap Mux", "L/L", "IF_ADC2" }, 2610 { "RT5650 IF1 ADC2 Swap Mux", "R/R", "IF_ADC2" }, 2611 2612 { "RT5650 IF1 ADC3 Swap Mux", "L/R", "VAD_ADC" }, 2613 { "RT5650 IF1 ADC3 Swap Mux", "R/L", "VAD_ADC" }, 2614 { "RT5650 IF1 ADC3 Swap Mux", "L/L", "VAD_ADC" }, 2615 { "RT5650 IF1 ADC3 Swap Mux", "R/R", "VAD_ADC" }, 2616 2617 { "IF1 ADC", NULL, "RT5650 IF1 ADC1 Swap Mux" }, 2618 { "IF1 ADC", NULL, "RT5650 IF1 ADC2 Swap Mux" }, 2619 { "IF1 ADC", NULL, "RT5650 IF1 ADC3 Swap Mux" }, 2620 2621 { "RT5650 IF1 ADC Mux", "IF_ADC1/IF_ADC2/DAC_REF/Null", "IF1 ADC" }, 2622 { "RT5650 IF1 ADC Mux", "IF_ADC1/IF_ADC2/Null/DAC_REF", "IF1 ADC" }, 2623 { "RT5650 IF1 ADC Mux", "IF_ADC1/DAC_REF/IF_ADC2/Null", "IF1 ADC" }, 2624 { "RT5650 IF1 ADC Mux", "IF_ADC1/DAC_REF/Null/IF_ADC2", "IF1 ADC" }, 2625 { "RT5650 IF1 ADC Mux", "IF_ADC1/Null/DAC_REF/IF_ADC2", "IF1 ADC" }, 2626 { "RT5650 IF1 ADC Mux", "IF_ADC1/Null/IF_ADC2/DAC_REF", "IF1 ADC" }, 2627 2628 { "RT5650 IF1 ADC Mux", "IF_ADC2/IF_ADC1/DAC_REF/Null", "IF1 ADC" }, 2629 { "RT5650 IF1 ADC Mux", "IF_ADC2/IF_ADC1/Null/DAC_REF", "IF1 ADC" }, 2630 { "RT5650 IF1 ADC Mux", "IF_ADC2/DAC_REF/IF_ADC1/Null", "IF1 ADC" }, 2631 { "RT5650 IF1 ADC Mux", "IF_ADC2/DAC_REF/Null/IF_ADC1", "IF1 ADC" }, 2632 { "RT5650 IF1 ADC Mux", "IF_ADC2/Null/DAC_REF/IF_ADC1", "IF1 ADC" }, 2633 { "RT5650 IF1 ADC Mux", "IF_ADC2/Null/IF_ADC1/DAC_REF", "IF1 ADC" }, 2634 2635 { "RT5650 IF1 ADC Mux", "DAC_REF/IF_ADC1/IF_ADC2/Null", "IF1 ADC" }, 2636 { "RT5650 IF1 ADC Mux", "DAC_REF/IF_ADC1/Null/IF_ADC2", "IF1 ADC" }, 2637 { "RT5650 IF1 ADC Mux", "DAC_REF/IF_ADC2/IF_ADC1/Null", "IF1 ADC" }, 2638 { "RT5650 IF1 ADC Mux", "DAC_REF/IF_ADC2/Null/IF_ADC1", "IF1 ADC" }, 2639 { "RT5650 IF1 ADC Mux", "DAC_REF/Null/IF_ADC1/IF_ADC2", "IF1 ADC" }, 2640 { "RT5650 IF1 ADC Mux", "DAC_REF/Null/IF_ADC2/IF_ADC1", "IF1 ADC" }, 2641 2642 { "RT5650 IF1 ADC Mux", "Null/IF_ADC1/IF_ADC2/DAC_REF", "IF1 ADC" }, 2643 { "RT5650 IF1 ADC Mux", "Null/IF_ADC1/DAC_REF/IF_ADC2", "IF1 ADC" }, 2644 { "RT5650 IF1 ADC Mux", "Null/IF_ADC2/IF_ADC1/DAC_REF", "IF1 ADC" }, 2645 { "RT5650 IF1 ADC Mux", "Null/IF_ADC2/DAC_REF/IF_ADC1", "IF1 ADC" }, 2646 { "RT5650 IF1 ADC Mux", "Null/DAC_REF/IF_ADC1/IF_ADC2", "IF1 ADC" }, 2647 { "RT5650 IF1 ADC Mux", "Null/DAC_REF/IF_ADC2/IF_ADC1", "IF1 ADC" }, 2648 { "AIF1TX", NULL, "RT5650 IF1 ADC Mux" }, 2649 2650 { "RT5650 IF1 DAC1 L Mux", "Slot0", "IF1 DAC0" }, 2651 { "RT5650 IF1 DAC1 L Mux", "Slot1", "IF1 DAC1" }, 2652 { "RT5650 IF1 DAC1 L Mux", "Slot2", "IF1 DAC2" }, 2653 { "RT5650 IF1 DAC1 L Mux", "Slot3", "IF1 DAC3" }, 2654 2655 { "RT5650 IF1 DAC1 R Mux", "Slot0", "IF1 DAC0" }, 2656 { "RT5650 IF1 DAC1 R Mux", "Slot1", "IF1 DAC1" }, 2657 { "RT5650 IF1 DAC1 R Mux", "Slot2", "IF1 DAC2" }, 2658 { "RT5650 IF1 DAC1 R Mux", "Slot3", "IF1 DAC3" }, 2659 2660 { "RT5650 IF1 DAC2 L Mux", "Slot0", "IF1 DAC0" }, 2661 { "RT5650 IF1 DAC2 L Mux", "Slot1", "IF1 DAC1" }, 2662 { "RT5650 IF1 DAC2 L Mux", "Slot2", "IF1 DAC2" }, 2663 { "RT5650 IF1 DAC2 L Mux", "Slot3", "IF1 DAC3" }, 2664 2665 { "RT5650 IF1 DAC2 R Mux", "Slot0", "IF1 DAC0" }, 2666 { "RT5650 IF1 DAC2 R Mux", "Slot1", "IF1 DAC1" }, 2667 { "RT5650 IF1 DAC2 R Mux", "Slot2", "IF1 DAC2" }, 2668 { "RT5650 IF1 DAC2 R Mux", "Slot3", "IF1 DAC3" }, 2669 2670 { "DAC1 L Mux", "IF1 DAC", "RT5650 IF1 DAC1 L Mux" }, 2671 { "DAC1 R Mux", "IF1 DAC", "RT5650 IF1 DAC1 R Mux" }, 2672 2673 { "DAC L2 Mux", "IF1 DAC", "RT5650 IF1 DAC2 L Mux" }, 2674 { "DAC R2 Mux", "IF1 DAC", "RT5650 IF1 DAC2 R Mux" }, 2675 }; 2676 2677 static const struct snd_soc_dapm_route rt5645_specific_dapm_routes[] = { 2678 { "DAC L1", NULL, "Stereo DAC MIXL" }, 2679 { "DAC R1", NULL, "Stereo DAC MIXR" }, 2680 { "DAC L2", NULL, "Mono DAC MIXL" }, 2681 { "DAC R2", NULL, "Mono DAC MIXR" }, 2682 2683 { "RT5645 IF1 ADC1 Swap Mux", "L/R", "IF_ADC1" }, 2684 { "RT5645 IF1 ADC1 Swap Mux", "R/L", "IF_ADC1" }, 2685 { "RT5645 IF1 ADC1 Swap Mux", "L/L", "IF_ADC1" }, 2686 { "RT5645 IF1 ADC1 Swap Mux", "R/R", "IF_ADC1" }, 2687 2688 { "RT5645 IF1 ADC2 Swap Mux", "L/R", "IF_ADC2" }, 2689 { "RT5645 IF1 ADC2 Swap Mux", "R/L", "IF_ADC2" }, 2690 { "RT5645 IF1 ADC2 Swap Mux", "L/L", "IF_ADC2" }, 2691 { "RT5645 IF1 ADC2 Swap Mux", "R/R", "IF_ADC2" }, 2692 2693 { "RT5645 IF1 ADC3 Swap Mux", "L/R", "VAD_ADC" }, 2694 { "RT5645 IF1 ADC3 Swap Mux", "R/L", "VAD_ADC" }, 2695 { "RT5645 IF1 ADC3 Swap Mux", "L/L", "VAD_ADC" }, 2696 { "RT5645 IF1 ADC3 Swap Mux", "R/R", "VAD_ADC" }, 2697 2698 { "IF1 ADC", NULL, "RT5645 IF1 ADC1 Swap Mux" }, 2699 { "IF1 ADC", NULL, "RT5645 IF1 ADC2 Swap Mux" }, 2700 { "IF1 ADC", NULL, "RT5645 IF1 ADC3 Swap Mux" }, 2701 2702 { "RT5645 IF1 ADC Mux", "IF_ADC1/IF_ADC2/VAD_ADC", "IF1 ADC" }, 2703 { "RT5645 IF1 ADC Mux", "IF_ADC2/IF_ADC1/VAD_ADC", "IF1 ADC" }, 2704 { "RT5645 IF1 ADC Mux", "VAD_ADC/IF_ADC1/IF_ADC2", "IF1 ADC" }, 2705 { "RT5645 IF1 ADC Mux", "VAD_ADC/IF_ADC2/IF_ADC1", "IF1 ADC" }, 2706 { "AIF1TX", NULL, "RT5645 IF1 ADC Mux" }, 2707 2708 { "RT5645 IF1 DAC1 L Mux", "Slot0", "IF1 DAC0" }, 2709 { "RT5645 IF1 DAC1 L Mux", "Slot1", "IF1 DAC1" }, 2710 { "RT5645 IF1 DAC1 L Mux", "Slot2", "IF1 DAC2" }, 2711 { "RT5645 IF1 DAC1 L Mux", "Slot3", "IF1 DAC3" }, 2712 2713 { "RT5645 IF1 DAC1 R Mux", "Slot0", "IF1 DAC0" }, 2714 { "RT5645 IF1 DAC1 R Mux", "Slot1", "IF1 DAC1" }, 2715 { "RT5645 IF1 DAC1 R Mux", "Slot2", "IF1 DAC2" }, 2716 { "RT5645 IF1 DAC1 R Mux", "Slot3", "IF1 DAC3" }, 2717 2718 { "RT5645 IF1 DAC2 L Mux", "Slot0", "IF1 DAC0" }, 2719 { "RT5645 IF1 DAC2 L Mux", "Slot1", "IF1 DAC1" }, 2720 { "RT5645 IF1 DAC2 L Mux", "Slot2", "IF1 DAC2" }, 2721 { "RT5645 IF1 DAC2 L Mux", "Slot3", "IF1 DAC3" }, 2722 2723 { "RT5645 IF1 DAC2 R Mux", "Slot0", "IF1 DAC0" }, 2724 { "RT5645 IF1 DAC2 R Mux", "Slot1", "IF1 DAC1" }, 2725 { "RT5645 IF1 DAC2 R Mux", "Slot2", "IF1 DAC2" }, 2726 { "RT5645 IF1 DAC2 R Mux", "Slot3", "IF1 DAC3" }, 2727 2728 { "DAC1 L Mux", "IF1 DAC", "RT5645 IF1 DAC1 L Mux" }, 2729 { "DAC1 R Mux", "IF1 DAC", "RT5645 IF1 DAC1 R Mux" }, 2730 2731 { "DAC L2 Mux", "IF1 DAC", "RT5645 IF1 DAC2 L Mux" }, 2732 { "DAC R2 Mux", "IF1 DAC", "RT5645 IF1 DAC2 R Mux" }, 2733 }; 2734 2735 static const struct snd_soc_dapm_route rt5645_old_dapm_routes[] = { 2736 { "SPOL MIX", "DAC R1 Switch", "DAC R1" }, 2737 { "SPOL MIX", "SPKVOL R Switch", "SPKVOL R" }, 2738 }; 2739 2740 static int rt5645_hw_params(struct snd_pcm_substream *substream, 2741 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) 2742 { 2743 struct snd_soc_component *component = dai->component; 2744 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component); 2745 unsigned int val_len = 0, val_clk, mask_clk, dl_sft; 2746 int pre_div, bclk_ms, frame_size; 2747 2748 rt5645->lrck[dai->id] = params_rate(params); 2749 pre_div = rl6231_get_clk_info(rt5645->sysclk, rt5645->lrck[dai->id]); 2750 if (pre_div < 0) { 2751 dev_err(component->dev, "Unsupported clock setting\n"); 2752 return -EINVAL; 2753 } 2754 frame_size = snd_soc_params_to_frame_size(params); 2755 if (frame_size < 0) { 2756 dev_err(component->dev, "Unsupported frame size: %d\n", frame_size); 2757 return -EINVAL; 2758 } 2759 2760 switch (rt5645->codec_type) { 2761 case CODEC_TYPE_RT5650: 2762 dl_sft = 4; 2763 break; 2764 default: 2765 dl_sft = 2; 2766 break; 2767 } 2768 2769 bclk_ms = frame_size > 32; 2770 rt5645->bclk[dai->id] = rt5645->lrck[dai->id] * (32 << bclk_ms); 2771 2772 dev_dbg(dai->dev, "bclk is %dHz and lrck is %dHz\n", 2773 rt5645->bclk[dai->id], rt5645->lrck[dai->id]); 2774 dev_dbg(dai->dev, "bclk_ms is %d and pre_div is %d for iis %d\n", 2775 bclk_ms, pre_div, dai->id); 2776 2777 switch (params_width(params)) { 2778 case 16: 2779 break; 2780 case 20: 2781 val_len = 0x1; 2782 break; 2783 case 24: 2784 val_len = 0x2; 2785 break; 2786 case 8: 2787 val_len = 0x3; 2788 break; 2789 default: 2790 return -EINVAL; 2791 } 2792 2793 switch (dai->id) { 2794 case RT5645_AIF1: 2795 mask_clk = RT5645_I2S_PD1_MASK; 2796 val_clk = pre_div << RT5645_I2S_PD1_SFT; 2797 snd_soc_component_update_bits(component, RT5645_I2S1_SDP, 2798 (0x3 << dl_sft), (val_len << dl_sft)); 2799 snd_soc_component_update_bits(component, RT5645_ADDA_CLK1, mask_clk, val_clk); 2800 break; 2801 case RT5645_AIF2: 2802 mask_clk = RT5645_I2S_BCLK_MS2_MASK | RT5645_I2S_PD2_MASK; 2803 val_clk = bclk_ms << RT5645_I2S_BCLK_MS2_SFT | 2804 pre_div << RT5645_I2S_PD2_SFT; 2805 snd_soc_component_update_bits(component, RT5645_I2S2_SDP, 2806 (0x3 << dl_sft), (val_len << dl_sft)); 2807 snd_soc_component_update_bits(component, RT5645_ADDA_CLK1, mask_clk, val_clk); 2808 break; 2809 default: 2810 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id); 2811 return -EINVAL; 2812 } 2813 2814 return 0; 2815 } 2816 2817 static int rt5645_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) 2818 { 2819 struct snd_soc_component *component = dai->component; 2820 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component); 2821 unsigned int reg_val = 0, pol_sft; 2822 2823 switch (rt5645->codec_type) { 2824 case CODEC_TYPE_RT5650: 2825 pol_sft = 8; 2826 break; 2827 default: 2828 pol_sft = 7; 2829 break; 2830 } 2831 2832 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 2833 case SND_SOC_DAIFMT_CBM_CFM: 2834 rt5645->master[dai->id] = 1; 2835 break; 2836 case SND_SOC_DAIFMT_CBS_CFS: 2837 reg_val |= RT5645_I2S_MS_S; 2838 rt5645->master[dai->id] = 0; 2839 break; 2840 default: 2841 return -EINVAL; 2842 } 2843 2844 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 2845 case SND_SOC_DAIFMT_NB_NF: 2846 break; 2847 case SND_SOC_DAIFMT_IB_NF: 2848 reg_val |= (1 << pol_sft); 2849 break; 2850 default: 2851 return -EINVAL; 2852 } 2853 2854 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 2855 case SND_SOC_DAIFMT_I2S: 2856 break; 2857 case SND_SOC_DAIFMT_LEFT_J: 2858 reg_val |= RT5645_I2S_DF_LEFT; 2859 break; 2860 case SND_SOC_DAIFMT_DSP_A: 2861 reg_val |= RT5645_I2S_DF_PCM_A; 2862 break; 2863 case SND_SOC_DAIFMT_DSP_B: 2864 reg_val |= RT5645_I2S_DF_PCM_B; 2865 break; 2866 default: 2867 return -EINVAL; 2868 } 2869 switch (dai->id) { 2870 case RT5645_AIF1: 2871 snd_soc_component_update_bits(component, RT5645_I2S1_SDP, 2872 RT5645_I2S_MS_MASK | (1 << pol_sft) | 2873 RT5645_I2S_DF_MASK, reg_val); 2874 break; 2875 case RT5645_AIF2: 2876 snd_soc_component_update_bits(component, RT5645_I2S2_SDP, 2877 RT5645_I2S_MS_MASK | (1 << pol_sft) | 2878 RT5645_I2S_DF_MASK, reg_val); 2879 break; 2880 default: 2881 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id); 2882 return -EINVAL; 2883 } 2884 return 0; 2885 } 2886 2887 static int rt5645_set_dai_sysclk(struct snd_soc_dai *dai, 2888 int clk_id, unsigned int freq, int dir) 2889 { 2890 struct snd_soc_component *component = dai->component; 2891 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component); 2892 unsigned int reg_val = 0; 2893 2894 if (freq == rt5645->sysclk && clk_id == rt5645->sysclk_src) 2895 return 0; 2896 2897 switch (clk_id) { 2898 case RT5645_SCLK_S_MCLK: 2899 reg_val |= RT5645_SCLK_SRC_MCLK; 2900 break; 2901 case RT5645_SCLK_S_PLL1: 2902 reg_val |= RT5645_SCLK_SRC_PLL1; 2903 break; 2904 case RT5645_SCLK_S_RCCLK: 2905 reg_val |= RT5645_SCLK_SRC_RCCLK; 2906 break; 2907 default: 2908 dev_err(component->dev, "Invalid clock id (%d)\n", clk_id); 2909 return -EINVAL; 2910 } 2911 snd_soc_component_update_bits(component, RT5645_GLB_CLK, 2912 RT5645_SCLK_SRC_MASK, reg_val); 2913 rt5645->sysclk = freq; 2914 rt5645->sysclk_src = clk_id; 2915 2916 dev_dbg(dai->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id); 2917 2918 return 0; 2919 } 2920 2921 static int rt5645_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source, 2922 unsigned int freq_in, unsigned int freq_out) 2923 { 2924 struct snd_soc_component *component = dai->component; 2925 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component); 2926 struct rl6231_pll_code pll_code; 2927 int ret; 2928 2929 if (source == rt5645->pll_src && freq_in == rt5645->pll_in && 2930 freq_out == rt5645->pll_out) 2931 return 0; 2932 2933 if (!freq_in || !freq_out) { 2934 dev_dbg(component->dev, "PLL disabled\n"); 2935 2936 rt5645->pll_in = 0; 2937 rt5645->pll_out = 0; 2938 snd_soc_component_update_bits(component, RT5645_GLB_CLK, 2939 RT5645_SCLK_SRC_MASK, RT5645_SCLK_SRC_MCLK); 2940 return 0; 2941 } 2942 2943 switch (source) { 2944 case RT5645_PLL1_S_MCLK: 2945 snd_soc_component_update_bits(component, RT5645_GLB_CLK, 2946 RT5645_PLL1_SRC_MASK, RT5645_PLL1_SRC_MCLK); 2947 break; 2948 case RT5645_PLL1_S_BCLK1: 2949 case RT5645_PLL1_S_BCLK2: 2950 switch (dai->id) { 2951 case RT5645_AIF1: 2952 snd_soc_component_update_bits(component, RT5645_GLB_CLK, 2953 RT5645_PLL1_SRC_MASK, RT5645_PLL1_SRC_BCLK1); 2954 break; 2955 case RT5645_AIF2: 2956 snd_soc_component_update_bits(component, RT5645_GLB_CLK, 2957 RT5645_PLL1_SRC_MASK, RT5645_PLL1_SRC_BCLK2); 2958 break; 2959 default: 2960 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id); 2961 return -EINVAL; 2962 } 2963 break; 2964 default: 2965 dev_err(component->dev, "Unknown PLL source %d\n", source); 2966 return -EINVAL; 2967 } 2968 2969 ret = rl6231_pll_calc(freq_in, freq_out, &pll_code); 2970 if (ret < 0) { 2971 dev_err(component->dev, "Unsupported input clock %d\n", freq_in); 2972 return ret; 2973 } 2974 2975 dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n", 2976 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code), 2977 pll_code.n_code, pll_code.k_code); 2978 2979 snd_soc_component_write(component, RT5645_PLL_CTRL1, 2980 pll_code.n_code << RT5645_PLL_N_SFT | pll_code.k_code); 2981 snd_soc_component_write(component, RT5645_PLL_CTRL2, 2982 ((pll_code.m_bp ? 0 : pll_code.m_code) << RT5645_PLL_M_SFT) | 2983 (pll_code.m_bp << RT5645_PLL_M_BP_SFT)); 2984 2985 rt5645->pll_in = freq_in; 2986 rt5645->pll_out = freq_out; 2987 rt5645->pll_src = source; 2988 2989 return 0; 2990 } 2991 2992 static int rt5645_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask, 2993 unsigned int rx_mask, int slots, int slot_width) 2994 { 2995 struct snd_soc_component *component = dai->component; 2996 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component); 2997 unsigned int i_slot_sft, o_slot_sft, i_width_sht, o_width_sht, en_sft; 2998 unsigned int mask, val = 0; 2999 3000 switch (rt5645->codec_type) { 3001 case CODEC_TYPE_RT5650: 3002 en_sft = 15; 3003 i_slot_sft = 10; 3004 o_slot_sft = 8; 3005 i_width_sht = 6; 3006 o_width_sht = 4; 3007 mask = 0x8ff0; 3008 break; 3009 default: 3010 en_sft = 14; 3011 i_slot_sft = o_slot_sft = 12; 3012 i_width_sht = o_width_sht = 10; 3013 mask = 0x7c00; 3014 break; 3015 } 3016 if (rx_mask || tx_mask) { 3017 val |= (1 << en_sft); 3018 if (rt5645->codec_type == CODEC_TYPE_RT5645) 3019 snd_soc_component_update_bits(component, RT5645_BASS_BACK, 3020 RT5645_G_BB_BST_MASK, RT5645_G_BB_BST_25DB); 3021 } 3022 3023 switch (slots) { 3024 case 4: 3025 val |= (1 << i_slot_sft) | (1 << o_slot_sft); 3026 break; 3027 case 6: 3028 val |= (2 << i_slot_sft) | (2 << o_slot_sft); 3029 break; 3030 case 8: 3031 val |= (3 << i_slot_sft) | (3 << o_slot_sft); 3032 break; 3033 case 2: 3034 default: 3035 break; 3036 } 3037 3038 switch (slot_width) { 3039 case 20: 3040 val |= (1 << i_width_sht) | (1 << o_width_sht); 3041 break; 3042 case 24: 3043 val |= (2 << i_width_sht) | (2 << o_width_sht); 3044 break; 3045 case 32: 3046 val |= (3 << i_width_sht) | (3 << o_width_sht); 3047 break; 3048 case 16: 3049 default: 3050 break; 3051 } 3052 3053 snd_soc_component_update_bits(component, RT5645_TDM_CTRL_1, mask, val); 3054 3055 return 0; 3056 } 3057 3058 static int rt5645_set_bias_level(struct snd_soc_component *component, 3059 enum snd_soc_bias_level level) 3060 { 3061 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component); 3062 3063 switch (level) { 3064 case SND_SOC_BIAS_PREPARE: 3065 if (SND_SOC_BIAS_STANDBY == snd_soc_component_get_bias_level(component)) { 3066 snd_soc_component_update_bits(component, RT5645_PWR_ANLG1, 3067 RT5645_PWR_VREF1 | RT5645_PWR_MB | 3068 RT5645_PWR_BG | RT5645_PWR_VREF2, 3069 RT5645_PWR_VREF1 | RT5645_PWR_MB | 3070 RT5645_PWR_BG | RT5645_PWR_VREF2); 3071 mdelay(10); 3072 snd_soc_component_update_bits(component, RT5645_PWR_ANLG1, 3073 RT5645_PWR_FV1 | RT5645_PWR_FV2, 3074 RT5645_PWR_FV1 | RT5645_PWR_FV2); 3075 snd_soc_component_update_bits(component, RT5645_GEN_CTRL1, 3076 RT5645_DIG_GATE_CTRL, RT5645_DIG_GATE_CTRL); 3077 } 3078 break; 3079 3080 case SND_SOC_BIAS_STANDBY: 3081 snd_soc_component_update_bits(component, RT5645_PWR_ANLG1, 3082 RT5645_PWR_VREF1 | RT5645_PWR_MB | 3083 RT5645_PWR_BG | RT5645_PWR_VREF2, 3084 RT5645_PWR_VREF1 | RT5645_PWR_MB | 3085 RT5645_PWR_BG | RT5645_PWR_VREF2); 3086 mdelay(10); 3087 snd_soc_component_update_bits(component, RT5645_PWR_ANLG1, 3088 RT5645_PWR_FV1 | RT5645_PWR_FV2, 3089 RT5645_PWR_FV1 | RT5645_PWR_FV2); 3090 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) { 3091 snd_soc_component_write(component, RT5645_DEPOP_M2, 0x1140); 3092 msleep(40); 3093 if (rt5645->en_button_func) 3094 queue_delayed_work(system_power_efficient_wq, 3095 &rt5645->jack_detect_work, 3096 msecs_to_jiffies(0)); 3097 } 3098 break; 3099 3100 case SND_SOC_BIAS_OFF: 3101 snd_soc_component_write(component, RT5645_DEPOP_M2, 0x1100); 3102 if (!rt5645->en_button_func) 3103 snd_soc_component_update_bits(component, RT5645_GEN_CTRL1, 3104 RT5645_DIG_GATE_CTRL, 0); 3105 snd_soc_component_update_bits(component, RT5645_PWR_ANLG1, 3106 RT5645_PWR_VREF1 | RT5645_PWR_MB | 3107 RT5645_PWR_BG | RT5645_PWR_VREF2 | 3108 RT5645_PWR_FV1 | RT5645_PWR_FV2, 0x0); 3109 break; 3110 3111 default: 3112 break; 3113 } 3114 3115 return 0; 3116 } 3117 3118 static void rt5645_enable_push_button_irq(struct snd_soc_component *component, 3119 bool enable) 3120 { 3121 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); 3122 3123 if (enable) { 3124 snd_soc_dapm_force_enable_pin(dapm, "ADC L power"); 3125 snd_soc_dapm_force_enable_pin(dapm, "ADC R power"); 3126 snd_soc_dapm_sync(dapm); 3127 3128 snd_soc_component_update_bits(component, RT5650_4BTN_IL_CMD1, 0x3, 0x3); 3129 snd_soc_component_update_bits(component, 3130 RT5645_INT_IRQ_ST, 0x8, 0x8); 3131 snd_soc_component_update_bits(component, 3132 RT5650_4BTN_IL_CMD2, 0x8000, 0x8000); 3133 snd_soc_component_read(component, RT5650_4BTN_IL_CMD1); 3134 pr_debug("%s read %x = %x\n", __func__, RT5650_4BTN_IL_CMD1, 3135 snd_soc_component_read(component, RT5650_4BTN_IL_CMD1)); 3136 } else { 3137 snd_soc_component_update_bits(component, RT5650_4BTN_IL_CMD2, 0x8000, 0x0); 3138 snd_soc_component_update_bits(component, RT5645_INT_IRQ_ST, 0x8, 0x0); 3139 3140 snd_soc_dapm_disable_pin(dapm, "ADC L power"); 3141 snd_soc_dapm_disable_pin(dapm, "ADC R power"); 3142 snd_soc_dapm_sync(dapm); 3143 } 3144 } 3145 3146 static int rt5645_jack_detect(struct snd_soc_component *component, int jack_insert) 3147 { 3148 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); 3149 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component); 3150 unsigned int val; 3151 3152 if (jack_insert) { 3153 regmap_write(rt5645->regmap, RT5645_CHARGE_PUMP, 0x0e06); 3154 3155 /* for jack type detect */ 3156 snd_soc_dapm_force_enable_pin(dapm, "LDO2"); 3157 snd_soc_dapm_force_enable_pin(dapm, "Mic Det Power"); 3158 snd_soc_dapm_sync(dapm); 3159 if (!snd_soc_card_is_instantiated(dapm->card)) { 3160 /* Power up necessary bits for JD if dapm is 3161 not ready yet */ 3162 regmap_update_bits(rt5645->regmap, RT5645_PWR_ANLG1, 3163 RT5645_PWR_MB | RT5645_PWR_VREF2, 3164 RT5645_PWR_MB | RT5645_PWR_VREF2); 3165 regmap_update_bits(rt5645->regmap, RT5645_PWR_MIXER, 3166 RT5645_PWR_LDO2, RT5645_PWR_LDO2); 3167 regmap_update_bits(rt5645->regmap, RT5645_PWR_VOL, 3168 RT5645_PWR_MIC_DET, RT5645_PWR_MIC_DET); 3169 } 3170 3171 regmap_write(rt5645->regmap, RT5645_JD_CTRL3, 0x00f0); 3172 regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL2, 3173 RT5645_CBJ_MN_JD, RT5645_CBJ_MN_JD); 3174 regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL1, 3175 RT5645_CBJ_BST1_EN, RT5645_CBJ_BST1_EN); 3176 msleep(100); 3177 regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL2, 3178 RT5645_CBJ_MN_JD, 0); 3179 3180 msleep(600); 3181 regmap_read(rt5645->regmap, RT5645_IN1_CTRL3, &val); 3182 val &= 0x7; 3183 dev_dbg(component->dev, "val = %d\n", val); 3184 3185 if ((val == 1 || val == 2) && !rt5645->pdata.no_headset_mic) { 3186 rt5645->jack_type = SND_JACK_HEADSET; 3187 if (rt5645->en_button_func) { 3188 rt5645_enable_push_button_irq(component, true); 3189 } 3190 } else { 3191 snd_soc_dapm_disable_pin(dapm, "Mic Det Power"); 3192 snd_soc_dapm_sync(dapm); 3193 rt5645->jack_type = SND_JACK_HEADPHONE; 3194 } 3195 if (rt5645->pdata.level_trigger_irq) 3196 regmap_update_bits(rt5645->regmap, RT5645_IRQ_CTRL2, 3197 RT5645_JD_1_1_MASK, RT5645_JD_1_1_NOR); 3198 } else { /* jack out */ 3199 rt5645->jack_type = 0; 3200 3201 regmap_update_bits(rt5645->regmap, RT5645_HP_VOL, 3202 RT5645_L_MUTE | RT5645_R_MUTE, 3203 RT5645_L_MUTE | RT5645_R_MUTE); 3204 regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL2, 3205 RT5645_CBJ_MN_JD, RT5645_CBJ_MN_JD); 3206 regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL1, 3207 RT5645_CBJ_BST1_EN, 0); 3208 3209 if (rt5645->en_button_func) 3210 rt5645_enable_push_button_irq(component, false); 3211 3212 if (rt5645->pdata.jd_mode == 0) 3213 snd_soc_dapm_disable_pin(dapm, "LDO2"); 3214 snd_soc_dapm_disable_pin(dapm, "Mic Det Power"); 3215 snd_soc_dapm_sync(dapm); 3216 if (rt5645->pdata.level_trigger_irq) 3217 regmap_update_bits(rt5645->regmap, RT5645_IRQ_CTRL2, 3218 RT5645_JD_1_1_MASK, RT5645_JD_1_1_INV); 3219 } 3220 3221 return rt5645->jack_type; 3222 } 3223 3224 static int rt5645_button_detect(struct snd_soc_component *component) 3225 { 3226 int btn_type, val; 3227 3228 val = snd_soc_component_read(component, RT5650_4BTN_IL_CMD1); 3229 pr_debug("val=0x%x\n", val); 3230 btn_type = val & 0xfff0; 3231 snd_soc_component_write(component, RT5650_4BTN_IL_CMD1, val); 3232 3233 return btn_type; 3234 } 3235 3236 static irqreturn_t rt5645_irq(int irq, void *data); 3237 3238 int rt5645_set_jack_detect(struct snd_soc_component *component, 3239 struct snd_soc_jack *hp_jack, struct snd_soc_jack *mic_jack, 3240 struct snd_soc_jack *btn_jack) 3241 { 3242 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component); 3243 3244 rt5645->hp_jack = hp_jack; 3245 rt5645->mic_jack = mic_jack; 3246 rt5645->btn_jack = btn_jack; 3247 if (rt5645->btn_jack && rt5645->codec_type == CODEC_TYPE_RT5650) { 3248 rt5645->en_button_func = true; 3249 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1, 3250 RT5645_GP1_PIN_IRQ, RT5645_GP1_PIN_IRQ); 3251 regmap_update_bits(rt5645->regmap, RT5645_GEN_CTRL1, 3252 RT5645_DIG_GATE_CTRL, RT5645_DIG_GATE_CTRL); 3253 } 3254 rt5645_irq(0, rt5645); 3255 3256 return 0; 3257 } 3258 EXPORT_SYMBOL_GPL(rt5645_set_jack_detect); 3259 3260 static int rt5645_component_set_jack(struct snd_soc_component *component, 3261 struct snd_soc_jack *hs_jack, void *data) 3262 { 3263 struct snd_soc_jack *mic_jack = NULL; 3264 struct snd_soc_jack *btn_jack = NULL; 3265 int *type = (int *)data; 3266 3267 if (*type & SND_JACK_MICROPHONE) 3268 mic_jack = hs_jack; 3269 if (*type & (SND_JACK_BTN_0 | SND_JACK_BTN_1 | 3270 SND_JACK_BTN_2 | SND_JACK_BTN_3)) 3271 btn_jack = hs_jack; 3272 3273 return rt5645_set_jack_detect(component, hs_jack, mic_jack, btn_jack); 3274 } 3275 3276 static void rt5645_jack_detect_work(struct work_struct *work) 3277 { 3278 struct rt5645_priv *rt5645 = 3279 container_of(work, struct rt5645_priv, jack_detect_work.work); 3280 int val, btn_type, gpio_state = 0, report = 0; 3281 3282 if (!rt5645->component) 3283 return; 3284 3285 switch (rt5645->pdata.jd_mode) { 3286 case 0: /* Not using rt5645 JD */ 3287 if (rt5645->gpiod_hp_det) { 3288 gpio_state = gpiod_get_value(rt5645->gpiod_hp_det); 3289 if (rt5645->pdata.inv_hp_pol) 3290 gpio_state ^= 1; 3291 dev_dbg(rt5645->component->dev, "gpio_state = %d\n", 3292 gpio_state); 3293 report = rt5645_jack_detect(rt5645->component, gpio_state); 3294 } 3295 snd_soc_jack_report(rt5645->hp_jack, 3296 report, SND_JACK_HEADPHONE); 3297 snd_soc_jack_report(rt5645->mic_jack, 3298 report, SND_JACK_MICROPHONE); 3299 return; 3300 case 4: 3301 val = snd_soc_component_read(rt5645->component, RT5645_A_JD_CTRL1) & 0x0020; 3302 break; 3303 default: /* read rt5645 jd1_1 status */ 3304 val = snd_soc_component_read(rt5645->component, RT5645_INT_IRQ_ST) & 0x1000; 3305 break; 3306 3307 } 3308 3309 if (!val && (rt5645->jack_type == 0)) { /* jack in */ 3310 report = rt5645_jack_detect(rt5645->component, 1); 3311 } else if (!val && rt5645->jack_type != 0) { 3312 /* for push button and jack out */ 3313 btn_type = 0; 3314 if (snd_soc_component_read(rt5645->component, RT5645_INT_IRQ_ST) & 0x4) { 3315 /* button pressed */ 3316 report = SND_JACK_HEADSET; 3317 btn_type = rt5645_button_detect(rt5645->component); 3318 /* rt5650 can report three kinds of button behavior, 3319 one click, double click and hold. However, 3320 currently we will report button pressed/released 3321 event. So all the three button behaviors are 3322 treated as button pressed. */ 3323 switch (btn_type) { 3324 case 0x8000: 3325 case 0x4000: 3326 case 0x2000: 3327 report |= SND_JACK_BTN_0; 3328 break; 3329 case 0x1000: 3330 case 0x0800: 3331 case 0x0400: 3332 report |= SND_JACK_BTN_1; 3333 break; 3334 case 0x0200: 3335 case 0x0100: 3336 case 0x0080: 3337 report |= SND_JACK_BTN_2; 3338 break; 3339 case 0x0040: 3340 case 0x0020: 3341 case 0x0010: 3342 report |= SND_JACK_BTN_3; 3343 break; 3344 case 0x0000: /* unpressed */ 3345 break; 3346 default: 3347 dev_err(rt5645->component->dev, 3348 "Unexpected button code 0x%04x\n", 3349 btn_type); 3350 break; 3351 } 3352 } 3353 if (btn_type == 0)/* button release */ 3354 report = rt5645->jack_type; 3355 else { 3356 mod_timer(&rt5645->btn_check_timer, 3357 msecs_to_jiffies(100)); 3358 } 3359 } else { 3360 /* jack out */ 3361 report = 0; 3362 snd_soc_component_update_bits(rt5645->component, 3363 RT5645_INT_IRQ_ST, 0x1, 0x0); 3364 rt5645_jack_detect(rt5645->component, 0); 3365 } 3366 3367 snd_soc_jack_report(rt5645->hp_jack, report, SND_JACK_HEADPHONE); 3368 snd_soc_jack_report(rt5645->mic_jack, report, SND_JACK_MICROPHONE); 3369 if (rt5645->en_button_func) 3370 snd_soc_jack_report(rt5645->btn_jack, 3371 report, SND_JACK_BTN_0 | SND_JACK_BTN_1 | 3372 SND_JACK_BTN_2 | SND_JACK_BTN_3); 3373 } 3374 3375 static void rt5645_rcclock_work(struct work_struct *work) 3376 { 3377 struct rt5645_priv *rt5645 = 3378 container_of(work, struct rt5645_priv, rcclock_work.work); 3379 3380 regmap_update_bits(rt5645->regmap, RT5645_MICBIAS, 3381 RT5645_PWR_CLK25M_MASK, RT5645_PWR_CLK25M_PD); 3382 } 3383 3384 static irqreturn_t rt5645_irq(int irq, void *data) 3385 { 3386 struct rt5645_priv *rt5645 = data; 3387 3388 queue_delayed_work(system_power_efficient_wq, 3389 &rt5645->jack_detect_work, msecs_to_jiffies(250)); 3390 3391 return IRQ_HANDLED; 3392 } 3393 3394 static void rt5645_btn_check_callback(struct timer_list *t) 3395 { 3396 struct rt5645_priv *rt5645 = from_timer(rt5645, t, btn_check_timer); 3397 3398 queue_delayed_work(system_power_efficient_wq, 3399 &rt5645->jack_detect_work, msecs_to_jiffies(5)); 3400 } 3401 3402 static int rt5645_probe(struct snd_soc_component *component) 3403 { 3404 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); 3405 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component); 3406 3407 rt5645->component = component; 3408 3409 switch (rt5645->codec_type) { 3410 case CODEC_TYPE_RT5645: 3411 snd_soc_dapm_new_controls(dapm, 3412 rt5645_specific_dapm_widgets, 3413 ARRAY_SIZE(rt5645_specific_dapm_widgets)); 3414 snd_soc_dapm_add_routes(dapm, 3415 rt5645_specific_dapm_routes, 3416 ARRAY_SIZE(rt5645_specific_dapm_routes)); 3417 if (rt5645->v_id < 3) { 3418 snd_soc_dapm_add_routes(dapm, 3419 rt5645_old_dapm_routes, 3420 ARRAY_SIZE(rt5645_old_dapm_routes)); 3421 } 3422 break; 3423 case CODEC_TYPE_RT5650: 3424 snd_soc_dapm_new_controls(dapm, 3425 rt5650_specific_dapm_widgets, 3426 ARRAY_SIZE(rt5650_specific_dapm_widgets)); 3427 snd_soc_dapm_add_routes(dapm, 3428 rt5650_specific_dapm_routes, 3429 ARRAY_SIZE(rt5650_specific_dapm_routes)); 3430 break; 3431 } 3432 3433 snd_soc_component_force_bias_level(component, SND_SOC_BIAS_OFF); 3434 3435 /* for JD function */ 3436 if (rt5645->pdata.jd_mode) { 3437 snd_soc_dapm_force_enable_pin(dapm, "JD Power"); 3438 snd_soc_dapm_force_enable_pin(dapm, "LDO2"); 3439 snd_soc_dapm_sync(dapm); 3440 } 3441 3442 if (rt5645->pdata.long_name) 3443 component->card->long_name = rt5645->pdata.long_name; 3444 3445 rt5645->eq_param = devm_kcalloc(component->dev, 3446 RT5645_HWEQ_NUM, sizeof(struct rt5645_eq_param_s), 3447 GFP_KERNEL); 3448 3449 if (!rt5645->eq_param) 3450 return -ENOMEM; 3451 3452 return 0; 3453 } 3454 3455 static void rt5645_remove(struct snd_soc_component *component) 3456 { 3457 rt5645_reset(component); 3458 } 3459 3460 #ifdef CONFIG_PM 3461 static int rt5645_suspend(struct snd_soc_component *component) 3462 { 3463 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component); 3464 3465 regcache_cache_only(rt5645->regmap, true); 3466 regcache_mark_dirty(rt5645->regmap); 3467 3468 return 0; 3469 } 3470 3471 static int rt5645_resume(struct snd_soc_component *component) 3472 { 3473 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component); 3474 3475 regcache_cache_only(rt5645->regmap, false); 3476 regcache_sync(rt5645->regmap); 3477 3478 return 0; 3479 } 3480 #else 3481 #define rt5645_suspend NULL 3482 #define rt5645_resume NULL 3483 #endif 3484 3485 #define RT5645_STEREO_RATES SNDRV_PCM_RATE_8000_96000 3486 #define RT5645_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ 3487 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8) 3488 3489 static const struct snd_soc_dai_ops rt5645_aif_dai_ops = { 3490 .hw_params = rt5645_hw_params, 3491 .set_fmt = rt5645_set_dai_fmt, 3492 .set_sysclk = rt5645_set_dai_sysclk, 3493 .set_tdm_slot = rt5645_set_tdm_slot, 3494 .set_pll = rt5645_set_dai_pll, 3495 }; 3496 3497 static struct snd_soc_dai_driver rt5645_dai[] = { 3498 { 3499 .name = "rt5645-aif1", 3500 .id = RT5645_AIF1, 3501 .playback = { 3502 .stream_name = "AIF1 Playback", 3503 .channels_min = 1, 3504 .channels_max = 2, 3505 .rates = RT5645_STEREO_RATES, 3506 .formats = RT5645_FORMATS, 3507 }, 3508 .capture = { 3509 .stream_name = "AIF1 Capture", 3510 .channels_min = 1, 3511 .channels_max = 4, 3512 .rates = RT5645_STEREO_RATES, 3513 .formats = RT5645_FORMATS, 3514 }, 3515 .ops = &rt5645_aif_dai_ops, 3516 }, 3517 { 3518 .name = "rt5645-aif2", 3519 .id = RT5645_AIF2, 3520 .playback = { 3521 .stream_name = "AIF2 Playback", 3522 .channels_min = 1, 3523 .channels_max = 2, 3524 .rates = RT5645_STEREO_RATES, 3525 .formats = RT5645_FORMATS, 3526 }, 3527 .capture = { 3528 .stream_name = "AIF2 Capture", 3529 .channels_min = 1, 3530 .channels_max = 2, 3531 .rates = RT5645_STEREO_RATES, 3532 .formats = RT5645_FORMATS, 3533 }, 3534 .ops = &rt5645_aif_dai_ops, 3535 }, 3536 }; 3537 3538 static const struct snd_soc_component_driver soc_component_dev_rt5645 = { 3539 .probe = rt5645_probe, 3540 .remove = rt5645_remove, 3541 .suspend = rt5645_suspend, 3542 .resume = rt5645_resume, 3543 .set_bias_level = rt5645_set_bias_level, 3544 .controls = rt5645_snd_controls, 3545 .num_controls = ARRAY_SIZE(rt5645_snd_controls), 3546 .dapm_widgets = rt5645_dapm_widgets, 3547 .num_dapm_widgets = ARRAY_SIZE(rt5645_dapm_widgets), 3548 .dapm_routes = rt5645_dapm_routes, 3549 .num_dapm_routes = ARRAY_SIZE(rt5645_dapm_routes), 3550 .set_jack = rt5645_component_set_jack, 3551 .use_pmdown_time = 1, 3552 .endianness = 1, 3553 }; 3554 3555 static const struct regmap_config rt5645_regmap = { 3556 .reg_bits = 8, 3557 .val_bits = 16, 3558 .use_single_read = true, 3559 .use_single_write = true, 3560 .max_register = RT5645_VENDOR_ID2 + 1 + (ARRAY_SIZE(rt5645_ranges) * 3561 RT5645_PR_SPACING), 3562 .volatile_reg = rt5645_volatile_register, 3563 .readable_reg = rt5645_readable_register, 3564 3565 .cache_type = REGCACHE_MAPLE, 3566 .reg_defaults = rt5645_reg, 3567 .num_reg_defaults = ARRAY_SIZE(rt5645_reg), 3568 .ranges = rt5645_ranges, 3569 .num_ranges = ARRAY_SIZE(rt5645_ranges), 3570 }; 3571 3572 static const struct regmap_config rt5650_regmap = { 3573 .reg_bits = 8, 3574 .val_bits = 16, 3575 .use_single_read = true, 3576 .use_single_write = true, 3577 .max_register = RT5645_VENDOR_ID2 + 1 + (ARRAY_SIZE(rt5645_ranges) * 3578 RT5645_PR_SPACING), 3579 .volatile_reg = rt5645_volatile_register, 3580 .readable_reg = rt5645_readable_register, 3581 3582 .cache_type = REGCACHE_MAPLE, 3583 .reg_defaults = rt5650_reg, 3584 .num_reg_defaults = ARRAY_SIZE(rt5650_reg), 3585 .ranges = rt5645_ranges, 3586 .num_ranges = ARRAY_SIZE(rt5645_ranges), 3587 }; 3588 3589 static const struct regmap_config temp_regmap = { 3590 .name="nocache", 3591 .reg_bits = 8, 3592 .val_bits = 16, 3593 .use_single_read = true, 3594 .use_single_write = true, 3595 .max_register = RT5645_VENDOR_ID2 + 1, 3596 .cache_type = REGCACHE_NONE, 3597 }; 3598 3599 static const struct i2c_device_id rt5645_i2c_id[] = { 3600 { "rt5645", 0 }, 3601 { "rt5650", 0 }, 3602 { } 3603 }; 3604 MODULE_DEVICE_TABLE(i2c, rt5645_i2c_id); 3605 3606 #ifdef CONFIG_OF 3607 static const struct of_device_id rt5645_of_match[] = { 3608 { .compatible = "realtek,rt5645", }, 3609 { .compatible = "realtek,rt5650", }, 3610 { } 3611 }; 3612 MODULE_DEVICE_TABLE(of, rt5645_of_match); 3613 #endif 3614 3615 #ifdef CONFIG_ACPI 3616 static const struct acpi_device_id rt5645_acpi_match[] = { 3617 { "10EC5645", 0 }, 3618 { "10EC5648", 0 }, 3619 { "10EC5650", 0 }, 3620 { "10EC5640", 0 }, 3621 { "10EC3270", 0 }, 3622 {}, 3623 }; 3624 MODULE_DEVICE_TABLE(acpi, rt5645_acpi_match); 3625 #endif 3626 3627 static const struct rt5645_platform_data intel_braswell_platform_data = { 3628 .dmic1_data_pin = RT5645_DMIC1_DISABLE, 3629 .dmic2_data_pin = RT5645_DMIC_DATA_IN2P, 3630 .jd_mode = 3, 3631 }; 3632 3633 static const struct rt5645_platform_data buddy_platform_data = { 3634 .dmic1_data_pin = RT5645_DMIC_DATA_GPIO5, 3635 .dmic2_data_pin = RT5645_DMIC_DATA_IN2P, 3636 .jd_mode = 4, 3637 .level_trigger_irq = true, 3638 }; 3639 3640 static const struct rt5645_platform_data gpd_win_platform_data = { 3641 .jd_mode = 3, 3642 .inv_jd1_1 = true, 3643 .long_name = "gpd-win-pocket-rt5645", 3644 /* The GPD pocket has a diff. mic, for the win this does not matter. */ 3645 .in2_diff = true, 3646 }; 3647 3648 static const struct rt5645_platform_data asus_t100ha_platform_data = { 3649 .dmic1_data_pin = RT5645_DMIC_DATA_IN2N, 3650 .dmic2_data_pin = RT5645_DMIC2_DISABLE, 3651 .jd_mode = 3, 3652 .inv_jd1_1 = true, 3653 }; 3654 3655 static const struct rt5645_platform_data asus_t101ha_platform_data = { 3656 .dmic1_data_pin = RT5645_DMIC_DATA_IN2N, 3657 .dmic2_data_pin = RT5645_DMIC2_DISABLE, 3658 .jd_mode = 3, 3659 }; 3660 3661 static const struct rt5645_platform_data lenovo_ideapad_miix_310_pdata = { 3662 .jd_mode = 3, 3663 .in2_diff = true, 3664 }; 3665 3666 static const struct rt5645_platform_data jd_mode3_platform_data = { 3667 .jd_mode = 3, 3668 }; 3669 3670 static const struct rt5645_platform_data lattepanda_board_platform_data = { 3671 .jd_mode = 2, 3672 .inv_jd1_1 = true 3673 }; 3674 3675 static const struct rt5645_platform_data kahlee_platform_data = { 3676 .dmic1_data_pin = RT5645_DMIC_DATA_GPIO5, 3677 .dmic2_data_pin = RT5645_DMIC_DATA_IN2P, 3678 .jd_mode = 3, 3679 }; 3680 3681 static const struct rt5645_platform_data ecs_ef20_platform_data = { 3682 .dmic1_data_pin = RT5645_DMIC1_DISABLE, 3683 .dmic2_data_pin = RT5645_DMIC_DATA_IN2P, 3684 .inv_hp_pol = 1, 3685 }; 3686 3687 static const struct acpi_gpio_params ef20_hp_detect = { 1, 0, false }; 3688 3689 static const struct acpi_gpio_mapping cht_rt5645_ef20_gpios[] = { 3690 { "hp-detect-gpios", &ef20_hp_detect, 1 }, 3691 { }, 3692 }; 3693 3694 static int cht_rt5645_ef20_quirk_cb(const struct dmi_system_id *id) 3695 { 3696 cht_rt5645_gpios = cht_rt5645_ef20_gpios; 3697 return 1; 3698 } 3699 3700 static const struct dmi_system_id dmi_platform_data[] = { 3701 { 3702 .ident = "Chrome Buddy", 3703 .matches = { 3704 DMI_MATCH(DMI_PRODUCT_NAME, "Buddy"), 3705 }, 3706 .driver_data = (void *)&buddy_platform_data, 3707 }, 3708 { 3709 .ident = "Intel Strago", 3710 .matches = { 3711 DMI_MATCH(DMI_PRODUCT_NAME, "Strago"), 3712 }, 3713 .driver_data = (void *)&intel_braswell_platform_data, 3714 }, 3715 { 3716 .ident = "Google Chrome", 3717 .matches = { 3718 DMI_MATCH(DMI_SYS_VENDOR, "GOOGLE"), 3719 }, 3720 .driver_data = (void *)&intel_braswell_platform_data, 3721 }, 3722 { 3723 .ident = "Google Setzer", 3724 .matches = { 3725 DMI_MATCH(DMI_PRODUCT_NAME, "Setzer"), 3726 }, 3727 .driver_data = (void *)&intel_braswell_platform_data, 3728 }, 3729 { 3730 .ident = "Microsoft Surface 3", 3731 .matches = { 3732 DMI_MATCH(DMI_PRODUCT_NAME, "Surface 3"), 3733 }, 3734 .driver_data = (void *)&intel_braswell_platform_data, 3735 }, 3736 { 3737 /* 3738 * Match for the GPDwin which unfortunately uses somewhat 3739 * generic dmi strings, which is why we test for 4 strings. 3740 * Comparing against 23 other byt/cht boards, board_vendor 3741 * and board_name are unique to the GPDwin, where as only one 3742 * other board has the same board_serial and 3 others have 3743 * the same default product_name. Also the GPDwin is the 3744 * only device to have both board_ and product_name not set. 3745 */ 3746 .ident = "GPD Win / Pocket", 3747 .matches = { 3748 DMI_MATCH(DMI_BOARD_VENDOR, "AMI Corporation"), 3749 DMI_MATCH(DMI_BOARD_NAME, "Default string"), 3750 DMI_MATCH(DMI_BOARD_SERIAL, "Default string"), 3751 DMI_MATCH(DMI_PRODUCT_NAME, "Default string"), 3752 }, 3753 .driver_data = (void *)&gpd_win_platform_data, 3754 }, 3755 { 3756 .ident = "ASUS T100HAN", 3757 .matches = { 3758 DMI_EXACT_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."), 3759 DMI_MATCH(DMI_PRODUCT_NAME, "T100HAN"), 3760 }, 3761 .driver_data = (void *)&asus_t100ha_platform_data, 3762 }, 3763 { 3764 .ident = "ASUS T101HA", 3765 .matches = { 3766 DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."), 3767 DMI_MATCH(DMI_PRODUCT_NAME, "T101HA"), 3768 }, 3769 .driver_data = (void *)&asus_t101ha_platform_data, 3770 }, 3771 { 3772 .ident = "MINIX Z83-4", 3773 .matches = { 3774 DMI_EXACT_MATCH(DMI_SYS_VENDOR, "MINIX"), 3775 DMI_MATCH(DMI_PRODUCT_NAME, "Z83-4"), 3776 }, 3777 .driver_data = (void *)&jd_mode3_platform_data, 3778 }, 3779 { 3780 .ident = "Teclast X80 Pro", 3781 .matches = { 3782 DMI_MATCH(DMI_SYS_VENDOR, "TECLAST"), 3783 DMI_MATCH(DMI_PRODUCT_NAME, "X80 Pro"), 3784 }, 3785 .driver_data = (void *)&jd_mode3_platform_data, 3786 }, 3787 { 3788 .ident = "Lenovo Ideapad Miix 310", 3789 .matches = { 3790 DMI_EXACT_MATCH(DMI_SYS_VENDOR, "LENOVO"), 3791 DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "80SG"), 3792 DMI_EXACT_MATCH(DMI_PRODUCT_VERSION, "MIIX 310-10ICR"), 3793 }, 3794 .driver_data = (void *)&lenovo_ideapad_miix_310_pdata, 3795 }, 3796 { 3797 .ident = "Lenovo Ideapad Miix 320", 3798 .matches = { 3799 DMI_EXACT_MATCH(DMI_SYS_VENDOR, "LENOVO"), 3800 DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "80XF"), 3801 DMI_EXACT_MATCH(DMI_PRODUCT_VERSION, "Lenovo MIIX 320-10ICR"), 3802 }, 3803 .driver_data = (void *)&intel_braswell_platform_data, 3804 }, 3805 { 3806 .ident = "LattePanda board", 3807 .matches = { 3808 DMI_EXACT_MATCH(DMI_BOARD_VENDOR, "AMI Corporation"), 3809 DMI_EXACT_MATCH(DMI_BOARD_NAME, "Cherry Trail CR"), 3810 DMI_EXACT_MATCH(DMI_BOARD_VERSION, "Default string"), 3811 }, 3812 .driver_data = (void *)&lattepanda_board_platform_data, 3813 }, 3814 { 3815 .ident = "Chrome Kahlee", 3816 .matches = { 3817 DMI_MATCH(DMI_PRODUCT_NAME, "Kahlee"), 3818 }, 3819 .driver_data = (void *)&kahlee_platform_data, 3820 }, 3821 { 3822 .ident = "Medion E1239T", 3823 .matches = { 3824 DMI_EXACT_MATCH(DMI_SYS_VENDOR, "MEDION"), 3825 DMI_MATCH(DMI_PRODUCT_NAME, "E1239T MD60568"), 3826 }, 3827 .driver_data = (void *)&intel_braswell_platform_data, 3828 }, 3829 { 3830 .ident = "EF20", 3831 .callback = cht_rt5645_ef20_quirk_cb, 3832 .matches = { 3833 DMI_MATCH(DMI_PRODUCT_NAME, "EF20"), 3834 }, 3835 .driver_data = (void *)&ecs_ef20_platform_data, 3836 }, 3837 { 3838 .ident = "EF20EA", 3839 .callback = cht_rt5645_ef20_quirk_cb, 3840 .matches = { 3841 DMI_MATCH(DMI_PRODUCT_NAME, "EF20EA"), 3842 }, 3843 .driver_data = (void *)&ecs_ef20_platform_data, 3844 }, 3845 { } 3846 }; 3847 3848 static bool rt5645_check_dp(struct device *dev) 3849 { 3850 if (device_property_present(dev, "realtek,in2-differential") || 3851 device_property_present(dev, "realtek,dmic1-data-pin") || 3852 device_property_present(dev, "realtek,dmic2-data-pin") || 3853 device_property_present(dev, "realtek,jd-mode")) 3854 return true; 3855 3856 return false; 3857 } 3858 3859 static int rt5645_parse_dt(struct rt5645_priv *rt5645, struct device *dev) 3860 { 3861 rt5645->pdata.in2_diff = device_property_read_bool(dev, 3862 "realtek,in2-differential"); 3863 device_property_read_u32(dev, 3864 "realtek,dmic1-data-pin", &rt5645->pdata.dmic1_data_pin); 3865 device_property_read_u32(dev, 3866 "realtek,dmic2-data-pin", &rt5645->pdata.dmic2_data_pin); 3867 device_property_read_u32(dev, 3868 "realtek,jd-mode", &rt5645->pdata.jd_mode); 3869 3870 return 0; 3871 } 3872 3873 static int rt5645_i2c_probe(struct i2c_client *i2c) 3874 { 3875 struct rt5645_platform_data *pdata = NULL; 3876 const struct dmi_system_id *dmi_data; 3877 struct rt5645_priv *rt5645; 3878 int ret, i; 3879 unsigned int val; 3880 struct regmap *regmap; 3881 3882 rt5645 = devm_kzalloc(&i2c->dev, sizeof(struct rt5645_priv), 3883 GFP_KERNEL); 3884 if (rt5645 == NULL) 3885 return -ENOMEM; 3886 3887 rt5645->i2c = i2c; 3888 i2c_set_clientdata(i2c, rt5645); 3889 3890 dmi_data = dmi_first_match(dmi_platform_data); 3891 if (dmi_data) { 3892 dev_info(&i2c->dev, "Detected %s platform\n", dmi_data->ident); 3893 pdata = dmi_data->driver_data; 3894 } 3895 3896 if (pdata) 3897 rt5645->pdata = *pdata; 3898 else if (rt5645_check_dp(&i2c->dev)) 3899 rt5645_parse_dt(rt5645, &i2c->dev); 3900 else 3901 rt5645->pdata = jd_mode3_platform_data; 3902 3903 if (quirk != -1) { 3904 rt5645->pdata.in2_diff = QUIRK_IN2_DIFF(quirk); 3905 rt5645->pdata.level_trigger_irq = QUIRK_LEVEL_IRQ(quirk); 3906 rt5645->pdata.inv_jd1_1 = QUIRK_INV_JD1_1(quirk); 3907 rt5645->pdata.inv_hp_pol = QUIRK_INV_HP_POL(quirk); 3908 rt5645->pdata.jd_mode = QUIRK_JD_MODE(quirk); 3909 rt5645->pdata.dmic1_data_pin = QUIRK_DMIC1_DATA_PIN(quirk); 3910 rt5645->pdata.dmic2_data_pin = QUIRK_DMIC2_DATA_PIN(quirk); 3911 } 3912 3913 if (has_acpi_companion(&i2c->dev)) { 3914 if (cht_rt5645_gpios) { 3915 if (devm_acpi_dev_add_driver_gpios(&i2c->dev, cht_rt5645_gpios)) 3916 dev_dbg(&i2c->dev, "Failed to add driver gpios\n"); 3917 } 3918 3919 /* The ALC3270 package has the headset-mic pin not-connected */ 3920 if (acpi_dev_hid_uid_match(ACPI_COMPANION(&i2c->dev), "10EC3270", NULL)) 3921 rt5645->pdata.no_headset_mic = true; 3922 } 3923 3924 rt5645->gpiod_hp_det = devm_gpiod_get_optional(&i2c->dev, "hp-detect", 3925 GPIOD_IN); 3926 3927 if (IS_ERR(rt5645->gpiod_hp_det)) { 3928 dev_info(&i2c->dev, "failed to initialize gpiod\n"); 3929 ret = PTR_ERR(rt5645->gpiod_hp_det); 3930 /* 3931 * Continue if optional gpiod is missing, bail for all other 3932 * errors, including -EPROBE_DEFER 3933 */ 3934 if (ret != -ENOENT) 3935 return ret; 3936 } 3937 3938 for (i = 0; i < ARRAY_SIZE(rt5645->supplies); i++) 3939 rt5645->supplies[i].supply = rt5645_supply_names[i]; 3940 3941 ret = devm_regulator_bulk_get(&i2c->dev, 3942 ARRAY_SIZE(rt5645->supplies), 3943 rt5645->supplies); 3944 if (ret) { 3945 dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret); 3946 return ret; 3947 } 3948 3949 ret = regulator_bulk_enable(ARRAY_SIZE(rt5645->supplies), 3950 rt5645->supplies); 3951 if (ret) { 3952 dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret); 3953 return ret; 3954 } 3955 3956 regmap = devm_regmap_init_i2c(i2c, &temp_regmap); 3957 if (IS_ERR(regmap)) { 3958 ret = PTR_ERR(regmap); 3959 dev_err(&i2c->dev, "Failed to allocate temp register map: %d\n", 3960 ret); 3961 goto err_enable; 3962 } 3963 3964 /* 3965 * Read after 400msec, as it is the interval required between 3966 * read and power On. 3967 */ 3968 msleep(TIME_TO_POWER_MS); 3969 ret = regmap_read(regmap, RT5645_VENDOR_ID2, &val); 3970 if (ret < 0) { 3971 dev_err(&i2c->dev, "Failed to read: 0x%02X\n, ret = %d", RT5645_VENDOR_ID2, ret); 3972 goto err_enable; 3973 } 3974 3975 switch (val) { 3976 case RT5645_DEVICE_ID: 3977 rt5645->regmap = devm_regmap_init_i2c(i2c, &rt5645_regmap); 3978 rt5645->codec_type = CODEC_TYPE_RT5645; 3979 break; 3980 case RT5650_DEVICE_ID: 3981 rt5645->regmap = devm_regmap_init_i2c(i2c, &rt5650_regmap); 3982 rt5645->codec_type = CODEC_TYPE_RT5650; 3983 break; 3984 default: 3985 dev_err(&i2c->dev, 3986 "Device with ID register %#x is not rt5645 or rt5650\n", 3987 val); 3988 ret = -ENODEV; 3989 goto err_enable; 3990 } 3991 3992 if (IS_ERR(rt5645->regmap)) { 3993 ret = PTR_ERR(rt5645->regmap); 3994 dev_err(&i2c->dev, "Failed to allocate register map: %d\n", 3995 ret); 3996 goto err_enable; 3997 } 3998 3999 regmap_write(rt5645->regmap, RT5645_RESET, 0); 4000 4001 regmap_read(regmap, RT5645_VENDOR_ID, &val); 4002 rt5645->v_id = val & 0xff; 4003 4004 regmap_write(rt5645->regmap, RT5645_AD_DA_MIXER, 0x8080); 4005 4006 ret = regmap_register_patch(rt5645->regmap, init_list, 4007 ARRAY_SIZE(init_list)); 4008 if (ret != 0) 4009 dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret); 4010 4011 if (rt5645->codec_type == CODEC_TYPE_RT5650) { 4012 ret = regmap_register_patch(rt5645->regmap, rt5650_init_list, 4013 ARRAY_SIZE(rt5650_init_list)); 4014 if (ret != 0) 4015 dev_warn(&i2c->dev, "Apply rt5650 patch failed: %d\n", 4016 ret); 4017 } 4018 4019 regmap_update_bits(rt5645->regmap, RT5645_CLSD_OUT_CTRL, 0xc0, 0xc0); 4020 4021 if (rt5645->pdata.in2_diff) 4022 regmap_update_bits(rt5645->regmap, RT5645_IN2_CTRL, 4023 RT5645_IN_DF2, RT5645_IN_DF2); 4024 4025 if (rt5645->pdata.dmic1_data_pin || rt5645->pdata.dmic2_data_pin) { 4026 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1, 4027 RT5645_GP2_PIN_MASK, RT5645_GP2_PIN_DMIC1_SCL); 4028 } 4029 switch (rt5645->pdata.dmic1_data_pin) { 4030 case RT5645_DMIC_DATA_IN2N: 4031 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1, 4032 RT5645_DMIC_1_DP_MASK, RT5645_DMIC_1_DP_IN2N); 4033 break; 4034 4035 case RT5645_DMIC_DATA_GPIO5: 4036 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1, 4037 RT5645_I2S2_DAC_PIN_MASK, RT5645_I2S2_DAC_PIN_GPIO); 4038 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1, 4039 RT5645_DMIC_1_DP_MASK, RT5645_DMIC_1_DP_GPIO5); 4040 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1, 4041 RT5645_GP5_PIN_MASK, RT5645_GP5_PIN_DMIC1_SDA); 4042 break; 4043 4044 case RT5645_DMIC_DATA_GPIO11: 4045 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1, 4046 RT5645_DMIC_1_DP_MASK, RT5645_DMIC_1_DP_GPIO11); 4047 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1, 4048 RT5645_GP11_PIN_MASK, 4049 RT5645_GP11_PIN_DMIC1_SDA); 4050 break; 4051 4052 default: 4053 break; 4054 } 4055 4056 switch (rt5645->pdata.dmic2_data_pin) { 4057 case RT5645_DMIC_DATA_IN2P: 4058 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1, 4059 RT5645_DMIC_2_DP_MASK, RT5645_DMIC_2_DP_IN2P); 4060 break; 4061 4062 case RT5645_DMIC_DATA_GPIO6: 4063 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1, 4064 RT5645_DMIC_2_DP_MASK, RT5645_DMIC_2_DP_GPIO6); 4065 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1, 4066 RT5645_GP6_PIN_MASK, RT5645_GP6_PIN_DMIC2_SDA); 4067 break; 4068 4069 case RT5645_DMIC_DATA_GPIO10: 4070 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1, 4071 RT5645_DMIC_2_DP_MASK, RT5645_DMIC_2_DP_GPIO10); 4072 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1, 4073 RT5645_GP10_PIN_MASK, 4074 RT5645_GP10_PIN_DMIC2_SDA); 4075 break; 4076 4077 case RT5645_DMIC_DATA_GPIO12: 4078 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1, 4079 RT5645_DMIC_2_DP_MASK, RT5645_DMIC_2_DP_GPIO12); 4080 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1, 4081 RT5645_GP12_PIN_MASK, 4082 RT5645_GP12_PIN_DMIC2_SDA); 4083 break; 4084 4085 default: 4086 break; 4087 } 4088 4089 if (rt5645->pdata.jd_mode) { 4090 regmap_update_bits(rt5645->regmap, RT5645_GEN_CTRL3, 4091 RT5645_IRQ_CLK_GATE_CTRL, 4092 RT5645_IRQ_CLK_GATE_CTRL); 4093 regmap_update_bits(rt5645->regmap, RT5645_MICBIAS, 4094 RT5645_IRQ_CLK_INT, RT5645_IRQ_CLK_INT); 4095 regmap_update_bits(rt5645->regmap, RT5645_IRQ_CTRL2, 4096 RT5645_IRQ_JD_1_1_EN, RT5645_IRQ_JD_1_1_EN); 4097 regmap_update_bits(rt5645->regmap, RT5645_GEN_CTRL3, 4098 RT5645_JD_PSV_MODE, RT5645_JD_PSV_MODE); 4099 regmap_update_bits(rt5645->regmap, RT5645_HPO_MIXER, 4100 RT5645_IRQ_PSV_MODE, RT5645_IRQ_PSV_MODE); 4101 regmap_update_bits(rt5645->regmap, RT5645_MICBIAS, 4102 RT5645_MIC2_OVCD_EN, RT5645_MIC2_OVCD_EN); 4103 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1, 4104 RT5645_GP1_PIN_IRQ, RT5645_GP1_PIN_IRQ); 4105 switch (rt5645->pdata.jd_mode) { 4106 case 1: 4107 regmap_update_bits(rt5645->regmap, RT5645_A_JD_CTRL1, 4108 RT5645_JD1_MODE_MASK, 4109 RT5645_JD1_MODE_0); 4110 break; 4111 case 2: 4112 regmap_update_bits(rt5645->regmap, RT5645_A_JD_CTRL1, 4113 RT5645_JD1_MODE_MASK, 4114 RT5645_JD1_MODE_1); 4115 break; 4116 case 3: 4117 case 4: 4118 regmap_update_bits(rt5645->regmap, RT5645_A_JD_CTRL1, 4119 RT5645_JD1_MODE_MASK, 4120 RT5645_JD1_MODE_2); 4121 break; 4122 default: 4123 break; 4124 } 4125 if (rt5645->pdata.inv_jd1_1) { 4126 regmap_update_bits(rt5645->regmap, RT5645_IRQ_CTRL2, 4127 RT5645_JD_1_1_MASK, RT5645_JD_1_1_INV); 4128 } 4129 } 4130 4131 regmap_update_bits(rt5645->regmap, RT5645_ADDA_CLK1, 4132 RT5645_I2S_PD1_MASK, RT5645_I2S_PD1_2); 4133 4134 if (rt5645->pdata.level_trigger_irq) { 4135 regmap_update_bits(rt5645->regmap, RT5645_IRQ_CTRL2, 4136 RT5645_JD_1_1_MASK, RT5645_JD_1_1_INV); 4137 } 4138 timer_setup(&rt5645->btn_check_timer, rt5645_btn_check_callback, 0); 4139 4140 INIT_DELAYED_WORK(&rt5645->jack_detect_work, rt5645_jack_detect_work); 4141 INIT_DELAYED_WORK(&rt5645->rcclock_work, rt5645_rcclock_work); 4142 4143 if (rt5645->i2c->irq) { 4144 ret = request_threaded_irq(rt5645->i2c->irq, NULL, rt5645_irq, 4145 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING 4146 | IRQF_ONESHOT, "rt5645", rt5645); 4147 if (ret) { 4148 dev_err(&i2c->dev, "Failed to reguest IRQ: %d\n", ret); 4149 goto err_enable; 4150 } 4151 } 4152 4153 ret = devm_snd_soc_register_component(&i2c->dev, &soc_component_dev_rt5645, 4154 rt5645_dai, ARRAY_SIZE(rt5645_dai)); 4155 if (ret) 4156 goto err_irq; 4157 4158 return 0; 4159 4160 err_irq: 4161 if (rt5645->i2c->irq) 4162 free_irq(rt5645->i2c->irq, rt5645); 4163 err_enable: 4164 regulator_bulk_disable(ARRAY_SIZE(rt5645->supplies), rt5645->supplies); 4165 return ret; 4166 } 4167 4168 static void rt5645_i2c_remove(struct i2c_client *i2c) 4169 { 4170 struct rt5645_priv *rt5645 = i2c_get_clientdata(i2c); 4171 4172 if (i2c->irq) 4173 free_irq(i2c->irq, rt5645); 4174 4175 /* 4176 * Since the rt5645_btn_check_callback() can queue jack_detect_work, 4177 * the timer need to be delted first 4178 */ 4179 del_timer_sync(&rt5645->btn_check_timer); 4180 4181 cancel_delayed_work_sync(&rt5645->jack_detect_work); 4182 cancel_delayed_work_sync(&rt5645->rcclock_work); 4183 4184 regulator_bulk_disable(ARRAY_SIZE(rt5645->supplies), rt5645->supplies); 4185 } 4186 4187 static void rt5645_i2c_shutdown(struct i2c_client *i2c) 4188 { 4189 struct rt5645_priv *rt5645 = i2c_get_clientdata(i2c); 4190 4191 regmap_update_bits(rt5645->regmap, RT5645_GEN_CTRL3, 4192 RT5645_RING2_SLEEVE_GND, RT5645_RING2_SLEEVE_GND); 4193 regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL2, RT5645_CBJ_MN_JD, 4194 RT5645_CBJ_MN_JD); 4195 regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL1, RT5645_CBJ_BST1_EN, 4196 0); 4197 msleep(20); 4198 regmap_write(rt5645->regmap, RT5645_RESET, 0); 4199 } 4200 4201 static int __maybe_unused rt5645_sys_suspend(struct device *dev) 4202 { 4203 struct rt5645_priv *rt5645 = dev_get_drvdata(dev); 4204 4205 del_timer_sync(&rt5645->btn_check_timer); 4206 cancel_delayed_work_sync(&rt5645->jack_detect_work); 4207 cancel_delayed_work_sync(&rt5645->rcclock_work); 4208 4209 regcache_cache_only(rt5645->regmap, true); 4210 regcache_mark_dirty(rt5645->regmap); 4211 return 0; 4212 } 4213 4214 static int __maybe_unused rt5645_sys_resume(struct device *dev) 4215 { 4216 struct rt5645_priv *rt5645 = dev_get_drvdata(dev); 4217 4218 regcache_cache_only(rt5645->regmap, false); 4219 regcache_sync(rt5645->regmap); 4220 4221 if (rt5645->hp_jack) { 4222 rt5645->jack_type = 0; 4223 queue_delayed_work(system_power_efficient_wq, 4224 &rt5645->jack_detect_work, msecs_to_jiffies(0)); 4225 } 4226 return 0; 4227 } 4228 4229 static const struct dev_pm_ops rt5645_pm = { 4230 SET_SYSTEM_SLEEP_PM_OPS(rt5645_sys_suspend, rt5645_sys_resume) 4231 }; 4232 4233 static struct i2c_driver rt5645_i2c_driver = { 4234 .driver = { 4235 .name = "rt5645", 4236 .of_match_table = of_match_ptr(rt5645_of_match), 4237 .acpi_match_table = ACPI_PTR(rt5645_acpi_match), 4238 .pm = &rt5645_pm, 4239 }, 4240 .probe = rt5645_i2c_probe, 4241 .remove = rt5645_i2c_remove, 4242 .shutdown = rt5645_i2c_shutdown, 4243 .id_table = rt5645_i2c_id, 4244 }; 4245 module_i2c_driver(rt5645_i2c_driver); 4246 4247 MODULE_DESCRIPTION("ASoC RT5645 driver"); 4248 MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>"); 4249 MODULE_LICENSE("GPL v2"); 4250