xref: /openbmc/linux/sound/soc/codecs/rt5645.c (revision 68198dca)
1 /*
2  * rt5645.c  --  RT5645 ALSA SoC audio codec driver
3  *
4  * Copyright 2013 Realtek Semiconductor Corp.
5  * Author: Bard Liao <bardliao@realtek.com>
6  *
7  * This program is free software; you can redistribute it and/or modify
8  * it under the terms of the GNU General Public License version 2 as
9  * published by the Free Software Foundation.
10  */
11 
12 #include <linux/module.h>
13 #include <linux/moduleparam.h>
14 #include <linux/init.h>
15 #include <linux/delay.h>
16 #include <linux/pm.h>
17 #include <linux/i2c.h>
18 #include <linux/platform_device.h>
19 #include <linux/spi/spi.h>
20 #include <linux/gpio.h>
21 #include <linux/gpio/consumer.h>
22 #include <linux/acpi.h>
23 #include <linux/dmi.h>
24 #include <linux/regulator/consumer.h>
25 #include <sound/core.h>
26 #include <sound/pcm.h>
27 #include <sound/pcm_params.h>
28 #include <sound/jack.h>
29 #include <sound/soc.h>
30 #include <sound/soc-dapm.h>
31 #include <sound/initval.h>
32 #include <sound/tlv.h>
33 
34 #include "rl6231.h"
35 #include "rt5645.h"
36 
37 #define QUIRK_INV_JD1_1(q)	((q) & 1)
38 #define QUIRK_LEVEL_IRQ(q)	(((q) >> 1) & 1)
39 #define QUIRK_IN2_DIFF(q)	(((q) >> 2) & 1)
40 #define QUIRK_JD_MODE(q)	(((q) >> 4) & 7)
41 #define QUIRK_DMIC1_DATA_PIN(q)	(((q) >> 8) & 3)
42 #define QUIRK_DMIC2_DATA_PIN(q)	(((q) >> 12) & 3)
43 
44 static unsigned int quirk = -1;
45 module_param(quirk, uint, 0444);
46 MODULE_PARM_DESC(quirk, "RT5645 pdata quirk override");
47 
48 #define RT5645_DEVICE_ID 0x6308
49 #define RT5650_DEVICE_ID 0x6419
50 
51 #define RT5645_PR_RANGE_BASE (0xff + 1)
52 #define RT5645_PR_SPACING 0x100
53 
54 #define RT5645_PR_BASE (RT5645_PR_RANGE_BASE + (0 * RT5645_PR_SPACING))
55 
56 #define RT5645_HWEQ_NUM 57
57 
58 #define TIME_TO_POWER_MS 400
59 
60 static const struct regmap_range_cfg rt5645_ranges[] = {
61 	{
62 		.name = "PR",
63 		.range_min = RT5645_PR_BASE,
64 		.range_max = RT5645_PR_BASE + 0xf8,
65 		.selector_reg = RT5645_PRIV_INDEX,
66 		.selector_mask = 0xff,
67 		.selector_shift = 0x0,
68 		.window_start = RT5645_PRIV_DATA,
69 		.window_len = 0x1,
70 	},
71 };
72 
73 static const struct reg_sequence init_list[] = {
74 	{RT5645_PR_BASE + 0x3d,	0x3600},
75 	{RT5645_PR_BASE + 0x1c,	0xfd70},
76 	{RT5645_PR_BASE + 0x20,	0x611f},
77 	{RT5645_PR_BASE + 0x21,	0x4040},
78 	{RT5645_PR_BASE + 0x23,	0x0004},
79 	{RT5645_ASRC_4, 0x0120},
80 };
81 
82 static const struct reg_sequence rt5650_init_list[] = {
83 	{0xf6,	0x0100},
84 };
85 
86 static const struct reg_default rt5645_reg[] = {
87 	{ 0x00, 0x0000 },
88 	{ 0x01, 0xc8c8 },
89 	{ 0x02, 0xc8c8 },
90 	{ 0x03, 0xc8c8 },
91 	{ 0x0a, 0x0002 },
92 	{ 0x0b, 0x2827 },
93 	{ 0x0c, 0xe000 },
94 	{ 0x0d, 0x0000 },
95 	{ 0x0e, 0x0000 },
96 	{ 0x0f, 0x0808 },
97 	{ 0x14, 0x3333 },
98 	{ 0x16, 0x4b00 },
99 	{ 0x18, 0x018b },
100 	{ 0x19, 0xafaf },
101 	{ 0x1a, 0xafaf },
102 	{ 0x1b, 0x0001 },
103 	{ 0x1c, 0x2f2f },
104 	{ 0x1d, 0x2f2f },
105 	{ 0x1e, 0x0000 },
106 	{ 0x20, 0x0000 },
107 	{ 0x27, 0x7060 },
108 	{ 0x28, 0x7070 },
109 	{ 0x29, 0x8080 },
110 	{ 0x2a, 0x5656 },
111 	{ 0x2b, 0x5454 },
112 	{ 0x2c, 0xaaa0 },
113 	{ 0x2d, 0x0000 },
114 	{ 0x2f, 0x1002 },
115 	{ 0x31, 0x5000 },
116 	{ 0x32, 0x0000 },
117 	{ 0x33, 0x0000 },
118 	{ 0x34, 0x0000 },
119 	{ 0x35, 0x0000 },
120 	{ 0x3b, 0x0000 },
121 	{ 0x3c, 0x007f },
122 	{ 0x3d, 0x0000 },
123 	{ 0x3e, 0x007f },
124 	{ 0x3f, 0x0000 },
125 	{ 0x40, 0x001f },
126 	{ 0x41, 0x0000 },
127 	{ 0x42, 0x001f },
128 	{ 0x45, 0x6000 },
129 	{ 0x46, 0x003e },
130 	{ 0x47, 0x003e },
131 	{ 0x48, 0xf807 },
132 	{ 0x4a, 0x0004 },
133 	{ 0x4d, 0x0000 },
134 	{ 0x4e, 0x0000 },
135 	{ 0x4f, 0x01ff },
136 	{ 0x50, 0x0000 },
137 	{ 0x51, 0x0000 },
138 	{ 0x52, 0x01ff },
139 	{ 0x53, 0xf000 },
140 	{ 0x56, 0x0111 },
141 	{ 0x57, 0x0064 },
142 	{ 0x58, 0xef0e },
143 	{ 0x59, 0xf0f0 },
144 	{ 0x5a, 0xef0e },
145 	{ 0x5b, 0xf0f0 },
146 	{ 0x5c, 0xef0e },
147 	{ 0x5d, 0xf0f0 },
148 	{ 0x5e, 0xf000 },
149 	{ 0x5f, 0x0000 },
150 	{ 0x61, 0x0300 },
151 	{ 0x62, 0x0000 },
152 	{ 0x63, 0x00c2 },
153 	{ 0x64, 0x0000 },
154 	{ 0x65, 0x0000 },
155 	{ 0x66, 0x0000 },
156 	{ 0x6a, 0x0000 },
157 	{ 0x6c, 0x0aaa },
158 	{ 0x70, 0x8000 },
159 	{ 0x71, 0x8000 },
160 	{ 0x72, 0x8000 },
161 	{ 0x73, 0x7770 },
162 	{ 0x74, 0x3e00 },
163 	{ 0x75, 0x2409 },
164 	{ 0x76, 0x000a },
165 	{ 0x77, 0x0c00 },
166 	{ 0x78, 0x0000 },
167 	{ 0x79, 0x0123 },
168 	{ 0x80, 0x0000 },
169 	{ 0x81, 0x0000 },
170 	{ 0x82, 0x0000 },
171 	{ 0x83, 0x0000 },
172 	{ 0x84, 0x0000 },
173 	{ 0x85, 0x0000 },
174 	{ 0x8a, 0x0120 },
175 	{ 0x8e, 0x0004 },
176 	{ 0x8f, 0x1100 },
177 	{ 0x90, 0x0646 },
178 	{ 0x91, 0x0c06 },
179 	{ 0x93, 0x0000 },
180 	{ 0x94, 0x0200 },
181 	{ 0x95, 0x0000 },
182 	{ 0x9a, 0x2184 },
183 	{ 0x9b, 0x010a },
184 	{ 0x9c, 0x0aea },
185 	{ 0x9d, 0x000c },
186 	{ 0x9e, 0x0400 },
187 	{ 0xa0, 0xa0a8 },
188 	{ 0xa1, 0x0059 },
189 	{ 0xa2, 0x0001 },
190 	{ 0xae, 0x6000 },
191 	{ 0xaf, 0x0000 },
192 	{ 0xb0, 0x6000 },
193 	{ 0xb1, 0x0000 },
194 	{ 0xb2, 0x0000 },
195 	{ 0xb3, 0x001f },
196 	{ 0xb4, 0x020c },
197 	{ 0xb5, 0x1f00 },
198 	{ 0xb6, 0x0000 },
199 	{ 0xbb, 0x0000 },
200 	{ 0xbc, 0x0000 },
201 	{ 0xbd, 0x0000 },
202 	{ 0xbe, 0x0000 },
203 	{ 0xbf, 0x3100 },
204 	{ 0xc0, 0x0000 },
205 	{ 0xc1, 0x0000 },
206 	{ 0xc2, 0x0000 },
207 	{ 0xc3, 0x2000 },
208 	{ 0xcd, 0x0000 },
209 	{ 0xce, 0x0000 },
210 	{ 0xcf, 0x1813 },
211 	{ 0xd0, 0x0690 },
212 	{ 0xd1, 0x1c17 },
213 	{ 0xd3, 0xb320 },
214 	{ 0xd4, 0x0000 },
215 	{ 0xd6, 0x0400 },
216 	{ 0xd9, 0x0809 },
217 	{ 0xda, 0x0000 },
218 	{ 0xdb, 0x0003 },
219 	{ 0xdc, 0x0049 },
220 	{ 0xdd, 0x001b },
221 	{ 0xdf, 0x0008 },
222 	{ 0xe0, 0x4000 },
223 	{ 0xe6, 0x8000 },
224 	{ 0xe7, 0x0200 },
225 	{ 0xec, 0xb300 },
226 	{ 0xed, 0x0000 },
227 	{ 0xf0, 0x001f },
228 	{ 0xf1, 0x020c },
229 	{ 0xf2, 0x1f00 },
230 	{ 0xf3, 0x0000 },
231 	{ 0xf4, 0x4000 },
232 	{ 0xf8, 0x0000 },
233 	{ 0xf9, 0x0000 },
234 	{ 0xfa, 0x2060 },
235 	{ 0xfb, 0x4040 },
236 	{ 0xfc, 0x0000 },
237 	{ 0xfd, 0x0002 },
238 	{ 0xfe, 0x10ec },
239 	{ 0xff, 0x6308 },
240 };
241 
242 static const struct reg_default rt5650_reg[] = {
243 	{ 0x00, 0x0000 },
244 	{ 0x01, 0xc8c8 },
245 	{ 0x02, 0xc8c8 },
246 	{ 0x03, 0xc8c8 },
247 	{ 0x0a, 0x0002 },
248 	{ 0x0b, 0x2827 },
249 	{ 0x0c, 0xe000 },
250 	{ 0x0d, 0x0000 },
251 	{ 0x0e, 0x0000 },
252 	{ 0x0f, 0x0808 },
253 	{ 0x14, 0x3333 },
254 	{ 0x16, 0x4b00 },
255 	{ 0x18, 0x018b },
256 	{ 0x19, 0xafaf },
257 	{ 0x1a, 0xafaf },
258 	{ 0x1b, 0x0001 },
259 	{ 0x1c, 0x2f2f },
260 	{ 0x1d, 0x2f2f },
261 	{ 0x1e, 0x0000 },
262 	{ 0x20, 0x0000 },
263 	{ 0x27, 0x7060 },
264 	{ 0x28, 0x7070 },
265 	{ 0x29, 0x8080 },
266 	{ 0x2a, 0x5656 },
267 	{ 0x2b, 0x5454 },
268 	{ 0x2c, 0xaaa0 },
269 	{ 0x2d, 0x0000 },
270 	{ 0x2f, 0x5002 },
271 	{ 0x31, 0x5000 },
272 	{ 0x32, 0x0000 },
273 	{ 0x33, 0x0000 },
274 	{ 0x34, 0x0000 },
275 	{ 0x35, 0x0000 },
276 	{ 0x3b, 0x0000 },
277 	{ 0x3c, 0x007f },
278 	{ 0x3d, 0x0000 },
279 	{ 0x3e, 0x007f },
280 	{ 0x3f, 0x0000 },
281 	{ 0x40, 0x001f },
282 	{ 0x41, 0x0000 },
283 	{ 0x42, 0x001f },
284 	{ 0x45, 0x6000 },
285 	{ 0x46, 0x003e },
286 	{ 0x47, 0x003e },
287 	{ 0x48, 0xf807 },
288 	{ 0x4a, 0x0004 },
289 	{ 0x4d, 0x0000 },
290 	{ 0x4e, 0x0000 },
291 	{ 0x4f, 0x01ff },
292 	{ 0x50, 0x0000 },
293 	{ 0x51, 0x0000 },
294 	{ 0x52, 0x01ff },
295 	{ 0x53, 0xf000 },
296 	{ 0x56, 0x0111 },
297 	{ 0x57, 0x0064 },
298 	{ 0x58, 0xef0e },
299 	{ 0x59, 0xf0f0 },
300 	{ 0x5a, 0xef0e },
301 	{ 0x5b, 0xf0f0 },
302 	{ 0x5c, 0xef0e },
303 	{ 0x5d, 0xf0f0 },
304 	{ 0x5e, 0xf000 },
305 	{ 0x5f, 0x0000 },
306 	{ 0x61, 0x0300 },
307 	{ 0x62, 0x0000 },
308 	{ 0x63, 0x00c2 },
309 	{ 0x64, 0x0000 },
310 	{ 0x65, 0x0000 },
311 	{ 0x66, 0x0000 },
312 	{ 0x6a, 0x0000 },
313 	{ 0x6c, 0x0aaa },
314 	{ 0x70, 0x8000 },
315 	{ 0x71, 0x8000 },
316 	{ 0x72, 0x8000 },
317 	{ 0x73, 0x7770 },
318 	{ 0x74, 0x3e00 },
319 	{ 0x75, 0x2409 },
320 	{ 0x76, 0x000a },
321 	{ 0x77, 0x0c00 },
322 	{ 0x78, 0x0000 },
323 	{ 0x79, 0x0123 },
324 	{ 0x7a, 0x0123 },
325 	{ 0x80, 0x0000 },
326 	{ 0x81, 0x0000 },
327 	{ 0x82, 0x0000 },
328 	{ 0x83, 0x0000 },
329 	{ 0x84, 0x0000 },
330 	{ 0x85, 0x0000 },
331 	{ 0x8a, 0x0120 },
332 	{ 0x8e, 0x0004 },
333 	{ 0x8f, 0x1100 },
334 	{ 0x90, 0x0646 },
335 	{ 0x91, 0x0c06 },
336 	{ 0x93, 0x0000 },
337 	{ 0x94, 0x0200 },
338 	{ 0x95, 0x0000 },
339 	{ 0x9a, 0x2184 },
340 	{ 0x9b, 0x010a },
341 	{ 0x9c, 0x0aea },
342 	{ 0x9d, 0x000c },
343 	{ 0x9e, 0x0400 },
344 	{ 0xa0, 0xa0a8 },
345 	{ 0xa1, 0x0059 },
346 	{ 0xa2, 0x0001 },
347 	{ 0xae, 0x6000 },
348 	{ 0xaf, 0x0000 },
349 	{ 0xb0, 0x6000 },
350 	{ 0xb1, 0x0000 },
351 	{ 0xb2, 0x0000 },
352 	{ 0xb3, 0x001f },
353 	{ 0xb4, 0x020c },
354 	{ 0xb5, 0x1f00 },
355 	{ 0xb6, 0x0000 },
356 	{ 0xbb, 0x0000 },
357 	{ 0xbc, 0x0000 },
358 	{ 0xbd, 0x0000 },
359 	{ 0xbe, 0x0000 },
360 	{ 0xbf, 0x3100 },
361 	{ 0xc0, 0x0000 },
362 	{ 0xc1, 0x0000 },
363 	{ 0xc2, 0x0000 },
364 	{ 0xc3, 0x2000 },
365 	{ 0xcd, 0x0000 },
366 	{ 0xce, 0x0000 },
367 	{ 0xcf, 0x1813 },
368 	{ 0xd0, 0x0690 },
369 	{ 0xd1, 0x1c17 },
370 	{ 0xd3, 0xb320 },
371 	{ 0xd4, 0x0000 },
372 	{ 0xd6, 0x0400 },
373 	{ 0xd9, 0x0809 },
374 	{ 0xda, 0x0000 },
375 	{ 0xdb, 0x0003 },
376 	{ 0xdc, 0x0049 },
377 	{ 0xdd, 0x001b },
378 	{ 0xdf, 0x0008 },
379 	{ 0xe0, 0x4000 },
380 	{ 0xe6, 0x8000 },
381 	{ 0xe7, 0x0200 },
382 	{ 0xec, 0xb300 },
383 	{ 0xed, 0x0000 },
384 	{ 0xf0, 0x001f },
385 	{ 0xf1, 0x020c },
386 	{ 0xf2, 0x1f00 },
387 	{ 0xf3, 0x0000 },
388 	{ 0xf4, 0x4000 },
389 	{ 0xf8, 0x0000 },
390 	{ 0xf9, 0x0000 },
391 	{ 0xfa, 0x2060 },
392 	{ 0xfb, 0x4040 },
393 	{ 0xfc, 0x0000 },
394 	{ 0xfd, 0x0002 },
395 	{ 0xfe, 0x10ec },
396 	{ 0xff, 0x6308 },
397 };
398 
399 struct rt5645_eq_param_s {
400 	unsigned short reg;
401 	unsigned short val;
402 };
403 
404 static const char *const rt5645_supply_names[] = {
405 	"avdd",
406 	"cpvdd",
407 };
408 
409 struct rt5645_priv {
410 	struct snd_soc_codec *codec;
411 	struct rt5645_platform_data pdata;
412 	struct regmap *regmap;
413 	struct i2c_client *i2c;
414 	struct gpio_desc *gpiod_hp_det;
415 	struct snd_soc_jack *hp_jack;
416 	struct snd_soc_jack *mic_jack;
417 	struct snd_soc_jack *btn_jack;
418 	struct delayed_work jack_detect_work, rcclock_work;
419 	struct regulator_bulk_data supplies[ARRAY_SIZE(rt5645_supply_names)];
420 	struct rt5645_eq_param_s *eq_param;
421 	struct timer_list btn_check_timer;
422 
423 	int codec_type;
424 	int sysclk;
425 	int sysclk_src;
426 	int lrck[RT5645_AIFS];
427 	int bclk[RT5645_AIFS];
428 	int master[RT5645_AIFS];
429 
430 	int pll_src;
431 	int pll_in;
432 	int pll_out;
433 
434 	int jack_type;
435 	bool en_button_func;
436 	bool hp_on;
437 	int v_id;
438 };
439 
440 static int rt5645_reset(struct snd_soc_codec *codec)
441 {
442 	return snd_soc_write(codec, RT5645_RESET, 0);
443 }
444 
445 static bool rt5645_volatile_register(struct device *dev, unsigned int reg)
446 {
447 	int i;
448 
449 	for (i = 0; i < ARRAY_SIZE(rt5645_ranges); i++) {
450 		if (reg >= rt5645_ranges[i].range_min &&
451 			reg <= rt5645_ranges[i].range_max) {
452 			return true;
453 		}
454 	}
455 
456 	switch (reg) {
457 	case RT5645_RESET:
458 	case RT5645_PRIV_INDEX:
459 	case RT5645_PRIV_DATA:
460 	case RT5645_IN1_CTRL1:
461 	case RT5645_IN1_CTRL2:
462 	case RT5645_IN1_CTRL3:
463 	case RT5645_A_JD_CTRL1:
464 	case RT5645_ADC_EQ_CTRL1:
465 	case RT5645_EQ_CTRL1:
466 	case RT5645_ALC_CTRL_1:
467 	case RT5645_IRQ_CTRL2:
468 	case RT5645_IRQ_CTRL3:
469 	case RT5645_INT_IRQ_ST:
470 	case RT5645_IL_CMD:
471 	case RT5650_4BTN_IL_CMD1:
472 	case RT5645_VENDOR_ID:
473 	case RT5645_VENDOR_ID1:
474 	case RT5645_VENDOR_ID2:
475 		return true;
476 	default:
477 		return false;
478 	}
479 }
480 
481 static bool rt5645_readable_register(struct device *dev, unsigned int reg)
482 {
483 	int i;
484 
485 	for (i = 0; i < ARRAY_SIZE(rt5645_ranges); i++) {
486 		if (reg >= rt5645_ranges[i].range_min &&
487 			reg <= rt5645_ranges[i].range_max) {
488 			return true;
489 		}
490 	}
491 
492 	switch (reg) {
493 	case RT5645_RESET:
494 	case RT5645_SPK_VOL:
495 	case RT5645_HP_VOL:
496 	case RT5645_LOUT1:
497 	case RT5645_IN1_CTRL1:
498 	case RT5645_IN1_CTRL2:
499 	case RT5645_IN1_CTRL3:
500 	case RT5645_IN2_CTRL:
501 	case RT5645_INL1_INR1_VOL:
502 	case RT5645_SPK_FUNC_LIM:
503 	case RT5645_ADJ_HPF_CTRL:
504 	case RT5645_DAC1_DIG_VOL:
505 	case RT5645_DAC2_DIG_VOL:
506 	case RT5645_DAC_CTRL:
507 	case RT5645_STO1_ADC_DIG_VOL:
508 	case RT5645_MONO_ADC_DIG_VOL:
509 	case RT5645_ADC_BST_VOL1:
510 	case RT5645_ADC_BST_VOL2:
511 	case RT5645_STO1_ADC_MIXER:
512 	case RT5645_MONO_ADC_MIXER:
513 	case RT5645_AD_DA_MIXER:
514 	case RT5645_STO_DAC_MIXER:
515 	case RT5645_MONO_DAC_MIXER:
516 	case RT5645_DIG_MIXER:
517 	case RT5650_A_DAC_SOUR:
518 	case RT5645_DIG_INF1_DATA:
519 	case RT5645_PDM_OUT_CTRL:
520 	case RT5645_REC_L1_MIXER:
521 	case RT5645_REC_L2_MIXER:
522 	case RT5645_REC_R1_MIXER:
523 	case RT5645_REC_R2_MIXER:
524 	case RT5645_HPMIXL_CTRL:
525 	case RT5645_HPOMIXL_CTRL:
526 	case RT5645_HPMIXR_CTRL:
527 	case RT5645_HPOMIXR_CTRL:
528 	case RT5645_HPO_MIXER:
529 	case RT5645_SPK_L_MIXER:
530 	case RT5645_SPK_R_MIXER:
531 	case RT5645_SPO_MIXER:
532 	case RT5645_SPO_CLSD_RATIO:
533 	case RT5645_OUT_L1_MIXER:
534 	case RT5645_OUT_R1_MIXER:
535 	case RT5645_OUT_L_GAIN1:
536 	case RT5645_OUT_L_GAIN2:
537 	case RT5645_OUT_R_GAIN1:
538 	case RT5645_OUT_R_GAIN2:
539 	case RT5645_LOUT_MIXER:
540 	case RT5645_HAPTIC_CTRL1:
541 	case RT5645_HAPTIC_CTRL2:
542 	case RT5645_HAPTIC_CTRL3:
543 	case RT5645_HAPTIC_CTRL4:
544 	case RT5645_HAPTIC_CTRL5:
545 	case RT5645_HAPTIC_CTRL6:
546 	case RT5645_HAPTIC_CTRL7:
547 	case RT5645_HAPTIC_CTRL8:
548 	case RT5645_HAPTIC_CTRL9:
549 	case RT5645_HAPTIC_CTRL10:
550 	case RT5645_PWR_DIG1:
551 	case RT5645_PWR_DIG2:
552 	case RT5645_PWR_ANLG1:
553 	case RT5645_PWR_ANLG2:
554 	case RT5645_PWR_MIXER:
555 	case RT5645_PWR_VOL:
556 	case RT5645_PRIV_INDEX:
557 	case RT5645_PRIV_DATA:
558 	case RT5645_I2S1_SDP:
559 	case RT5645_I2S2_SDP:
560 	case RT5645_ADDA_CLK1:
561 	case RT5645_ADDA_CLK2:
562 	case RT5645_DMIC_CTRL1:
563 	case RT5645_DMIC_CTRL2:
564 	case RT5645_TDM_CTRL_1:
565 	case RT5645_TDM_CTRL_2:
566 	case RT5645_TDM_CTRL_3:
567 	case RT5650_TDM_CTRL_4:
568 	case RT5645_GLB_CLK:
569 	case RT5645_PLL_CTRL1:
570 	case RT5645_PLL_CTRL2:
571 	case RT5645_ASRC_1:
572 	case RT5645_ASRC_2:
573 	case RT5645_ASRC_3:
574 	case RT5645_ASRC_4:
575 	case RT5645_DEPOP_M1:
576 	case RT5645_DEPOP_M2:
577 	case RT5645_DEPOP_M3:
578 	case RT5645_CHARGE_PUMP:
579 	case RT5645_MICBIAS:
580 	case RT5645_A_JD_CTRL1:
581 	case RT5645_VAD_CTRL4:
582 	case RT5645_CLSD_OUT_CTRL:
583 	case RT5645_ADC_EQ_CTRL1:
584 	case RT5645_ADC_EQ_CTRL2:
585 	case RT5645_EQ_CTRL1:
586 	case RT5645_EQ_CTRL2:
587 	case RT5645_ALC_CTRL_1:
588 	case RT5645_ALC_CTRL_2:
589 	case RT5645_ALC_CTRL_3:
590 	case RT5645_ALC_CTRL_4:
591 	case RT5645_ALC_CTRL_5:
592 	case RT5645_JD_CTRL:
593 	case RT5645_IRQ_CTRL1:
594 	case RT5645_IRQ_CTRL2:
595 	case RT5645_IRQ_CTRL3:
596 	case RT5645_INT_IRQ_ST:
597 	case RT5645_GPIO_CTRL1:
598 	case RT5645_GPIO_CTRL2:
599 	case RT5645_GPIO_CTRL3:
600 	case RT5645_BASS_BACK:
601 	case RT5645_MP3_PLUS1:
602 	case RT5645_MP3_PLUS2:
603 	case RT5645_ADJ_HPF1:
604 	case RT5645_ADJ_HPF2:
605 	case RT5645_HP_CALIB_AMP_DET:
606 	case RT5645_SV_ZCD1:
607 	case RT5645_SV_ZCD2:
608 	case RT5645_IL_CMD:
609 	case RT5645_IL_CMD2:
610 	case RT5645_IL_CMD3:
611 	case RT5650_4BTN_IL_CMD1:
612 	case RT5650_4BTN_IL_CMD2:
613 	case RT5645_DRC1_HL_CTRL1:
614 	case RT5645_DRC2_HL_CTRL1:
615 	case RT5645_ADC_MONO_HP_CTRL1:
616 	case RT5645_ADC_MONO_HP_CTRL2:
617 	case RT5645_DRC2_CTRL1:
618 	case RT5645_DRC2_CTRL2:
619 	case RT5645_DRC2_CTRL3:
620 	case RT5645_DRC2_CTRL4:
621 	case RT5645_DRC2_CTRL5:
622 	case RT5645_JD_CTRL3:
623 	case RT5645_JD_CTRL4:
624 	case RT5645_GEN_CTRL1:
625 	case RT5645_GEN_CTRL2:
626 	case RT5645_GEN_CTRL3:
627 	case RT5645_VENDOR_ID:
628 	case RT5645_VENDOR_ID1:
629 	case RT5645_VENDOR_ID2:
630 		return true;
631 	default:
632 		return false;
633 	}
634 }
635 
636 static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -4650, 150, 0);
637 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6525, 75, 0);
638 static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -3450, 150, 0);
639 static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0);
640 static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
641 
642 /* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
643 static const DECLARE_TLV_DB_RANGE(bst_tlv,
644 	0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
645 	1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
646 	2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
647 	3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
648 	6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
649 	7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
650 	8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0)
651 );
652 
653 /* {-6, -4.5, -3, -1.5, 0, 0.82, 1.58, 2.28} dB */
654 static const DECLARE_TLV_DB_RANGE(spk_clsd_tlv,
655 	0, 4, TLV_DB_SCALE_ITEM(-600, 150, 0),
656 	5, 5, TLV_DB_SCALE_ITEM(82, 0, 0),
657 	6, 6, TLV_DB_SCALE_ITEM(158, 0, 0),
658 	7, 7, TLV_DB_SCALE_ITEM(228, 0, 0)
659 );
660 
661 static int rt5645_hweq_info(struct snd_kcontrol *kcontrol,
662 			 struct snd_ctl_elem_info *uinfo)
663 {
664 	uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
665 	uinfo->count = RT5645_HWEQ_NUM * sizeof(struct rt5645_eq_param_s);
666 
667 	return 0;
668 }
669 
670 static int rt5645_hweq_get(struct snd_kcontrol *kcontrol,
671 			struct snd_ctl_elem_value *ucontrol)
672 {
673 	struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
674 	struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
675 	struct rt5645_eq_param_s *eq_param =
676 		(struct rt5645_eq_param_s *)ucontrol->value.bytes.data;
677 	int i;
678 
679 	for (i = 0; i < RT5645_HWEQ_NUM; i++) {
680 		eq_param[i].reg = cpu_to_be16(rt5645->eq_param[i].reg);
681 		eq_param[i].val = cpu_to_be16(rt5645->eq_param[i].val);
682 	}
683 
684 	return 0;
685 }
686 
687 static bool rt5645_validate_hweq(unsigned short reg)
688 {
689 	if ((reg >= 0x1a4 && reg <= 0x1cd) | (reg >= 0x1e5 && reg <= 0x1f8) |
690 		(reg == RT5645_EQ_CTRL2))
691 		return true;
692 
693 	return false;
694 }
695 
696 static int rt5645_hweq_put(struct snd_kcontrol *kcontrol,
697 			struct snd_ctl_elem_value *ucontrol)
698 {
699 	struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
700 	struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
701 	struct rt5645_eq_param_s *eq_param =
702 		(struct rt5645_eq_param_s *)ucontrol->value.bytes.data;
703 	int i;
704 
705 	for (i = 0; i < RT5645_HWEQ_NUM; i++) {
706 		eq_param[i].reg = be16_to_cpu(eq_param[i].reg);
707 		eq_param[i].val = be16_to_cpu(eq_param[i].val);
708 	}
709 
710 	/* The final setting of the table should be RT5645_EQ_CTRL2 */
711 	for (i = RT5645_HWEQ_NUM - 1; i >= 0; i--) {
712 		if (eq_param[i].reg == 0)
713 			continue;
714 		else if (eq_param[i].reg != RT5645_EQ_CTRL2)
715 			return 0;
716 		else
717 			break;
718 	}
719 
720 	for (i = 0; i < RT5645_HWEQ_NUM; i++) {
721 		if (!rt5645_validate_hweq(eq_param[i].reg) &&
722 			eq_param[i].reg != 0)
723 			return 0;
724 		else if (eq_param[i].reg == 0)
725 			break;
726 	}
727 
728 	memcpy(rt5645->eq_param, eq_param,
729 		RT5645_HWEQ_NUM * sizeof(struct rt5645_eq_param_s));
730 
731 	return 0;
732 }
733 
734 #define RT5645_HWEQ(xname) \
735 {	.iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
736 	.info = rt5645_hweq_info, \
737 	.get = rt5645_hweq_get, \
738 	.put = rt5645_hweq_put \
739 }
740 
741 static int rt5645_spk_put_volsw(struct snd_kcontrol *kcontrol,
742 		struct snd_ctl_elem_value *ucontrol)
743 {
744 	struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
745 	struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
746 	int ret;
747 
748 	regmap_update_bits(rt5645->regmap, RT5645_MICBIAS,
749 		RT5645_PWR_CLK25M_MASK, RT5645_PWR_CLK25M_PU);
750 
751 	ret = snd_soc_put_volsw(kcontrol, ucontrol);
752 
753 	mod_delayed_work(system_power_efficient_wq, &rt5645->rcclock_work,
754 		msecs_to_jiffies(200));
755 
756 	return ret;
757 }
758 
759 static const char * const rt5645_dac1_vol_ctrl_mode_text[] = {
760 	"immediately", "zero crossing", "soft ramp"
761 };
762 
763 static SOC_ENUM_SINGLE_DECL(
764 	rt5645_dac1_vol_ctrl_mode, RT5645_PR_BASE,
765 	RT5645_DA1_ZDET_SFT, rt5645_dac1_vol_ctrl_mode_text);
766 
767 static const struct snd_kcontrol_new rt5645_snd_controls[] = {
768 	/* Speaker Output Volume */
769 	SOC_DOUBLE("Speaker Channel Switch", RT5645_SPK_VOL,
770 		RT5645_VOL_L_SFT, RT5645_VOL_R_SFT, 1, 1),
771 	SOC_DOUBLE_EXT_TLV("Speaker Playback Volume", RT5645_SPK_VOL,
772 		RT5645_L_VOL_SFT, RT5645_R_VOL_SFT, 39, 1, snd_soc_get_volsw,
773 		rt5645_spk_put_volsw, out_vol_tlv),
774 
775 	/* ClassD modulator Speaker Gain Ratio */
776 	SOC_SINGLE_TLV("Speaker ClassD Playback Volume", RT5645_SPO_CLSD_RATIO,
777 		RT5645_SPK_G_CLSD_SFT, 7, 0, spk_clsd_tlv),
778 
779 	/* Headphone Output Volume */
780 	SOC_DOUBLE("Headphone Channel Switch", RT5645_HP_VOL,
781 		RT5645_VOL_L_SFT, RT5645_VOL_R_SFT, 1, 1),
782 	SOC_DOUBLE_TLV("Headphone Playback Volume", RT5645_HP_VOL,
783 		RT5645_L_VOL_SFT, RT5645_R_VOL_SFT, 39, 1, out_vol_tlv),
784 
785 	/* OUTPUT Control */
786 	SOC_DOUBLE("OUT Playback Switch", RT5645_LOUT1,
787 		RT5645_L_MUTE_SFT, RT5645_R_MUTE_SFT, 1, 1),
788 	SOC_DOUBLE("OUT Channel Switch", RT5645_LOUT1,
789 		RT5645_VOL_L_SFT, RT5645_VOL_R_SFT, 1, 1),
790 	SOC_DOUBLE_TLV("OUT Playback Volume", RT5645_LOUT1,
791 		RT5645_L_VOL_SFT, RT5645_R_VOL_SFT, 39, 1, out_vol_tlv),
792 
793 	/* DAC Digital Volume */
794 	SOC_DOUBLE("DAC2 Playback Switch", RT5645_DAC_CTRL,
795 		RT5645_M_DAC_L2_VOL_SFT, RT5645_M_DAC_R2_VOL_SFT, 1, 1),
796 	SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5645_DAC1_DIG_VOL,
797 		RT5645_L_VOL_SFT + 1, RT5645_R_VOL_SFT + 1, 87, 0, dac_vol_tlv),
798 	SOC_DOUBLE_TLV("Mono DAC Playback Volume", RT5645_DAC2_DIG_VOL,
799 		RT5645_L_VOL_SFT + 1, RT5645_R_VOL_SFT + 1, 87, 0, dac_vol_tlv),
800 
801 	/* IN1/IN2 Control */
802 	SOC_SINGLE_TLV("IN1 Boost", RT5645_IN1_CTRL1,
803 		RT5645_BST_SFT1, 12, 0, bst_tlv),
804 	SOC_SINGLE_TLV("IN2 Boost", RT5645_IN2_CTRL,
805 		RT5645_BST_SFT2, 8, 0, bst_tlv),
806 
807 	/* INL/INR Volume Control */
808 	SOC_DOUBLE_TLV("IN Capture Volume", RT5645_INL1_INR1_VOL,
809 		RT5645_INL_VOL_SFT, RT5645_INR_VOL_SFT, 31, 1, in_vol_tlv),
810 
811 	/* ADC Digital Volume Control */
812 	SOC_DOUBLE("ADC Capture Switch", RT5645_STO1_ADC_DIG_VOL,
813 		RT5645_L_MUTE_SFT, RT5645_R_MUTE_SFT, 1, 1),
814 	SOC_DOUBLE_TLV("ADC Capture Volume", RT5645_STO1_ADC_DIG_VOL,
815 		RT5645_L_VOL_SFT + 1, RT5645_R_VOL_SFT + 1, 63, 0, adc_vol_tlv),
816 	SOC_DOUBLE("Mono ADC Capture Switch", RT5645_MONO_ADC_DIG_VOL,
817 		RT5645_L_MUTE_SFT, RT5645_R_MUTE_SFT, 1, 1),
818 	SOC_DOUBLE_TLV("Mono ADC Capture Volume", RT5645_MONO_ADC_DIG_VOL,
819 		RT5645_L_VOL_SFT + 1, RT5645_R_VOL_SFT + 1, 63, 0, adc_vol_tlv),
820 
821 	/* ADC Boost Volume Control */
822 	SOC_DOUBLE_TLV("ADC Boost Capture Volume", RT5645_ADC_BST_VOL1,
823 		RT5645_STO1_ADC_L_BST_SFT, RT5645_STO1_ADC_R_BST_SFT, 3, 0,
824 		adc_bst_tlv),
825 	SOC_DOUBLE_TLV("Mono ADC Boost Capture Volume", RT5645_ADC_BST_VOL2,
826 		RT5645_MONO_ADC_L_BST_SFT, RT5645_MONO_ADC_R_BST_SFT, 3, 0,
827 		adc_bst_tlv),
828 
829 	/* I2S2 function select */
830 	SOC_SINGLE("I2S2 Func Switch", RT5645_GPIO_CTRL1, RT5645_I2S2_SEL_SFT,
831 		1, 1),
832 	RT5645_HWEQ("Speaker HWEQ"),
833 
834 	/* Digital Soft Volume Control */
835 	SOC_ENUM("DAC1 Digital Volume Control Func", rt5645_dac1_vol_ctrl_mode),
836 };
837 
838 /**
839  * set_dmic_clk - Set parameter of dmic.
840  *
841  * @w: DAPM widget.
842  * @kcontrol: The kcontrol of this widget.
843  * @event: Event id.
844  *
845  */
846 static int set_dmic_clk(struct snd_soc_dapm_widget *w,
847 	struct snd_kcontrol *kcontrol, int event)
848 {
849 	struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
850 	struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
851 	int idx, rate;
852 
853 	rate = rt5645->sysclk / rl6231_get_pre_div(rt5645->regmap,
854 		RT5645_ADDA_CLK1, RT5645_I2S_PD1_SFT);
855 	idx = rl6231_calc_dmic_clk(rate);
856 	if (idx < 0)
857 		dev_err(codec->dev, "Failed to set DMIC clock\n");
858 	else
859 		snd_soc_update_bits(codec, RT5645_DMIC_CTRL1,
860 			RT5645_DMIC_CLK_MASK, idx << RT5645_DMIC_CLK_SFT);
861 	return idx;
862 }
863 
864 static int is_sys_clk_from_pll(struct snd_soc_dapm_widget *source,
865 			 struct snd_soc_dapm_widget *sink)
866 {
867 	struct snd_soc_codec *codec = snd_soc_dapm_to_codec(source->dapm);
868 	unsigned int val;
869 
870 	val = snd_soc_read(codec, RT5645_GLB_CLK);
871 	val &= RT5645_SCLK_SRC_MASK;
872 	if (val == RT5645_SCLK_SRC_PLL1)
873 		return 1;
874 	else
875 		return 0;
876 }
877 
878 static int is_using_asrc(struct snd_soc_dapm_widget *source,
879 			 struct snd_soc_dapm_widget *sink)
880 {
881 	struct snd_soc_codec *codec = snd_soc_dapm_to_codec(source->dapm);
882 	unsigned int reg, shift, val;
883 
884 	switch (source->shift) {
885 	case 0:
886 		reg = RT5645_ASRC_3;
887 		shift = 0;
888 		break;
889 	case 1:
890 		reg = RT5645_ASRC_3;
891 		shift = 4;
892 		break;
893 	case 3:
894 		reg = RT5645_ASRC_2;
895 		shift = 0;
896 		break;
897 	case 8:
898 		reg = RT5645_ASRC_2;
899 		shift = 4;
900 		break;
901 	case 9:
902 		reg = RT5645_ASRC_2;
903 		shift = 8;
904 		break;
905 	case 10:
906 		reg = RT5645_ASRC_2;
907 		shift = 12;
908 		break;
909 	default:
910 		return 0;
911 	}
912 
913 	val = (snd_soc_read(codec, reg) >> shift) & 0xf;
914 	switch (val) {
915 	case 1:
916 	case 2:
917 	case 3:
918 	case 4:
919 		return 1;
920 	default:
921 		return 0;
922 	}
923 
924 }
925 
926 static int rt5645_enable_hweq(struct snd_soc_codec *codec)
927 {
928 	struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
929 	int i;
930 
931 	for (i = 0; i < RT5645_HWEQ_NUM; i++) {
932 		if (rt5645_validate_hweq(rt5645->eq_param[i].reg))
933 			regmap_write(rt5645->regmap, rt5645->eq_param[i].reg,
934 					rt5645->eq_param[i].val);
935 		else
936 			break;
937 	}
938 
939 	return 0;
940 }
941 
942 /**
943  * rt5645_sel_asrc_clk_src - select ASRC clock source for a set of filters
944  * @codec: SoC audio codec device.
945  * @filter_mask: mask of filters.
946  * @clk_src: clock source
947  *
948  * The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5645 can
949  * only support standard 32fs or 64fs i2s format, ASRC should be enabled to
950  * support special i2s clock format such as Intel's 100fs(100 * sampling rate).
951  * ASRC function will track i2s clock and generate a corresponding system clock
952  * for codec. This function provides an API to select the clock source for a
953  * set of filters specified by the mask. And the codec driver will turn on ASRC
954  * for these filters if ASRC is selected as their clock source.
955  */
956 int rt5645_sel_asrc_clk_src(struct snd_soc_codec *codec,
957 		unsigned int filter_mask, unsigned int clk_src)
958 {
959 	unsigned int asrc2_mask = 0;
960 	unsigned int asrc2_value = 0;
961 	unsigned int asrc3_mask = 0;
962 	unsigned int asrc3_value = 0;
963 
964 	switch (clk_src) {
965 	case RT5645_CLK_SEL_SYS:
966 	case RT5645_CLK_SEL_I2S1_ASRC:
967 	case RT5645_CLK_SEL_I2S2_ASRC:
968 	case RT5645_CLK_SEL_SYS2:
969 		break;
970 
971 	default:
972 		return -EINVAL;
973 	}
974 
975 	if (filter_mask & RT5645_DA_STEREO_FILTER) {
976 		asrc2_mask |= RT5645_DA_STO_CLK_SEL_MASK;
977 		asrc2_value = (asrc2_value & ~RT5645_DA_STO_CLK_SEL_MASK)
978 			| (clk_src << RT5645_DA_STO_CLK_SEL_SFT);
979 	}
980 
981 	if (filter_mask & RT5645_DA_MONO_L_FILTER) {
982 		asrc2_mask |= RT5645_DA_MONOL_CLK_SEL_MASK;
983 		asrc2_value = (asrc2_value & ~RT5645_DA_MONOL_CLK_SEL_MASK)
984 			| (clk_src << RT5645_DA_MONOL_CLK_SEL_SFT);
985 	}
986 
987 	if (filter_mask & RT5645_DA_MONO_R_FILTER) {
988 		asrc2_mask |= RT5645_DA_MONOR_CLK_SEL_MASK;
989 		asrc2_value = (asrc2_value & ~RT5645_DA_MONOR_CLK_SEL_MASK)
990 			| (clk_src << RT5645_DA_MONOR_CLK_SEL_SFT);
991 	}
992 
993 	if (filter_mask & RT5645_AD_STEREO_FILTER) {
994 		asrc2_mask |= RT5645_AD_STO1_CLK_SEL_MASK;
995 		asrc2_value = (asrc2_value & ~RT5645_AD_STO1_CLK_SEL_MASK)
996 			| (clk_src << RT5645_AD_STO1_CLK_SEL_SFT);
997 	}
998 
999 	if (filter_mask & RT5645_AD_MONO_L_FILTER) {
1000 		asrc3_mask |= RT5645_AD_MONOL_CLK_SEL_MASK;
1001 		asrc3_value = (asrc3_value & ~RT5645_AD_MONOL_CLK_SEL_MASK)
1002 			| (clk_src << RT5645_AD_MONOL_CLK_SEL_SFT);
1003 	}
1004 
1005 	if (filter_mask & RT5645_AD_MONO_R_FILTER)  {
1006 		asrc3_mask |= RT5645_AD_MONOR_CLK_SEL_MASK;
1007 		asrc3_value = (asrc3_value & ~RT5645_AD_MONOR_CLK_SEL_MASK)
1008 			| (clk_src << RT5645_AD_MONOR_CLK_SEL_SFT);
1009 	}
1010 
1011 	if (asrc2_mask)
1012 		snd_soc_update_bits(codec, RT5645_ASRC_2,
1013 			asrc2_mask, asrc2_value);
1014 
1015 	if (asrc3_mask)
1016 		snd_soc_update_bits(codec, RT5645_ASRC_3,
1017 			asrc3_mask, asrc3_value);
1018 
1019 	return 0;
1020 }
1021 EXPORT_SYMBOL_GPL(rt5645_sel_asrc_clk_src);
1022 
1023 /* Digital Mixer */
1024 static const struct snd_kcontrol_new rt5645_sto1_adc_l_mix[] = {
1025 	SOC_DAPM_SINGLE("ADC1 Switch", RT5645_STO1_ADC_MIXER,
1026 			RT5645_M_ADC_L1_SFT, 1, 1),
1027 	SOC_DAPM_SINGLE("ADC2 Switch", RT5645_STO1_ADC_MIXER,
1028 			RT5645_M_ADC_L2_SFT, 1, 1),
1029 };
1030 
1031 static const struct snd_kcontrol_new rt5645_sto1_adc_r_mix[] = {
1032 	SOC_DAPM_SINGLE("ADC1 Switch", RT5645_STO1_ADC_MIXER,
1033 			RT5645_M_ADC_R1_SFT, 1, 1),
1034 	SOC_DAPM_SINGLE("ADC2 Switch", RT5645_STO1_ADC_MIXER,
1035 			RT5645_M_ADC_R2_SFT, 1, 1),
1036 };
1037 
1038 static const struct snd_kcontrol_new rt5645_mono_adc_l_mix[] = {
1039 	SOC_DAPM_SINGLE("ADC1 Switch", RT5645_MONO_ADC_MIXER,
1040 			RT5645_M_MONO_ADC_L1_SFT, 1, 1),
1041 	SOC_DAPM_SINGLE("ADC2 Switch", RT5645_MONO_ADC_MIXER,
1042 			RT5645_M_MONO_ADC_L2_SFT, 1, 1),
1043 };
1044 
1045 static const struct snd_kcontrol_new rt5645_mono_adc_r_mix[] = {
1046 	SOC_DAPM_SINGLE("ADC1 Switch", RT5645_MONO_ADC_MIXER,
1047 			RT5645_M_MONO_ADC_R1_SFT, 1, 1),
1048 	SOC_DAPM_SINGLE("ADC2 Switch", RT5645_MONO_ADC_MIXER,
1049 			RT5645_M_MONO_ADC_R2_SFT, 1, 1),
1050 };
1051 
1052 static const struct snd_kcontrol_new rt5645_dac_l_mix[] = {
1053 	SOC_DAPM_SINGLE("Stereo ADC Switch", RT5645_AD_DA_MIXER,
1054 			RT5645_M_ADCMIX_L_SFT, 1, 1),
1055 	SOC_DAPM_SINGLE_AUTODISABLE("DAC1 Switch", RT5645_AD_DA_MIXER,
1056 			RT5645_M_DAC1_L_SFT, 1, 1),
1057 };
1058 
1059 static const struct snd_kcontrol_new rt5645_dac_r_mix[] = {
1060 	SOC_DAPM_SINGLE("Stereo ADC Switch", RT5645_AD_DA_MIXER,
1061 			RT5645_M_ADCMIX_R_SFT, 1, 1),
1062 	SOC_DAPM_SINGLE_AUTODISABLE("DAC1 Switch", RT5645_AD_DA_MIXER,
1063 			RT5645_M_DAC1_R_SFT, 1, 1),
1064 };
1065 
1066 static const struct snd_kcontrol_new rt5645_sto_dac_l_mix[] = {
1067 	SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_STO_DAC_MIXER,
1068 			RT5645_M_DAC_L1_SFT, 1, 1),
1069 	SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_STO_DAC_MIXER,
1070 			RT5645_M_DAC_L2_SFT, 1, 1),
1071 	SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_STO_DAC_MIXER,
1072 			RT5645_M_DAC_R1_STO_L_SFT, 1, 1),
1073 };
1074 
1075 static const struct snd_kcontrol_new rt5645_sto_dac_r_mix[] = {
1076 	SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_STO_DAC_MIXER,
1077 			RT5645_M_DAC_R1_SFT, 1, 1),
1078 	SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_STO_DAC_MIXER,
1079 			RT5645_M_DAC_R2_SFT, 1, 1),
1080 	SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_STO_DAC_MIXER,
1081 			RT5645_M_DAC_L1_STO_R_SFT, 1, 1),
1082 };
1083 
1084 static const struct snd_kcontrol_new rt5645_mono_dac_l_mix[] = {
1085 	SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_MONO_DAC_MIXER,
1086 			RT5645_M_DAC_L1_MONO_L_SFT, 1, 1),
1087 	SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_MONO_DAC_MIXER,
1088 			RT5645_M_DAC_L2_MONO_L_SFT, 1, 1),
1089 	SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_MONO_DAC_MIXER,
1090 			RT5645_M_DAC_R2_MONO_L_SFT, 1, 1),
1091 };
1092 
1093 static const struct snd_kcontrol_new rt5645_mono_dac_r_mix[] = {
1094 	SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_MONO_DAC_MIXER,
1095 			RT5645_M_DAC_R1_MONO_R_SFT, 1, 1),
1096 	SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_MONO_DAC_MIXER,
1097 			RT5645_M_DAC_R2_MONO_R_SFT, 1, 1),
1098 	SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_MONO_DAC_MIXER,
1099 			RT5645_M_DAC_L2_MONO_R_SFT, 1, 1),
1100 };
1101 
1102 static const struct snd_kcontrol_new rt5645_dig_l_mix[] = {
1103 	SOC_DAPM_SINGLE("Sto DAC Mix L Switch", RT5645_DIG_MIXER,
1104 			RT5645_M_STO_L_DAC_L_SFT, 1, 1),
1105 	SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_DIG_MIXER,
1106 			RT5645_M_DAC_L2_DAC_L_SFT, 1, 1),
1107 	SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_DIG_MIXER,
1108 			RT5645_M_DAC_R2_DAC_L_SFT, 1, 1),
1109 };
1110 
1111 static const struct snd_kcontrol_new rt5645_dig_r_mix[] = {
1112 	SOC_DAPM_SINGLE("Sto DAC Mix R Switch", RT5645_DIG_MIXER,
1113 			RT5645_M_STO_R_DAC_R_SFT, 1, 1),
1114 	SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_DIG_MIXER,
1115 			RT5645_M_DAC_R2_DAC_R_SFT, 1, 1),
1116 	SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_DIG_MIXER,
1117 			RT5645_M_DAC_L2_DAC_R_SFT, 1, 1),
1118 };
1119 
1120 /* Analog Input Mixer */
1121 static const struct snd_kcontrol_new rt5645_rec_l_mix[] = {
1122 	SOC_DAPM_SINGLE("HPOL Switch", RT5645_REC_L2_MIXER,
1123 			RT5645_M_HP_L_RM_L_SFT, 1, 1),
1124 	SOC_DAPM_SINGLE("INL Switch", RT5645_REC_L2_MIXER,
1125 			RT5645_M_IN_L_RM_L_SFT, 1, 1),
1126 	SOC_DAPM_SINGLE("BST2 Switch", RT5645_REC_L2_MIXER,
1127 			RT5645_M_BST2_RM_L_SFT, 1, 1),
1128 	SOC_DAPM_SINGLE("BST1 Switch", RT5645_REC_L2_MIXER,
1129 			RT5645_M_BST1_RM_L_SFT, 1, 1),
1130 	SOC_DAPM_SINGLE("OUT MIXL Switch", RT5645_REC_L2_MIXER,
1131 			RT5645_M_OM_L_RM_L_SFT, 1, 1),
1132 };
1133 
1134 static const struct snd_kcontrol_new rt5645_rec_r_mix[] = {
1135 	SOC_DAPM_SINGLE("HPOR Switch", RT5645_REC_R2_MIXER,
1136 			RT5645_M_HP_R_RM_R_SFT, 1, 1),
1137 	SOC_DAPM_SINGLE("INR Switch", RT5645_REC_R2_MIXER,
1138 			RT5645_M_IN_R_RM_R_SFT, 1, 1),
1139 	SOC_DAPM_SINGLE("BST2 Switch", RT5645_REC_R2_MIXER,
1140 			RT5645_M_BST2_RM_R_SFT, 1, 1),
1141 	SOC_DAPM_SINGLE("BST1 Switch", RT5645_REC_R2_MIXER,
1142 			RT5645_M_BST1_RM_R_SFT, 1, 1),
1143 	SOC_DAPM_SINGLE("OUT MIXR Switch", RT5645_REC_R2_MIXER,
1144 			RT5645_M_OM_R_RM_R_SFT, 1, 1),
1145 };
1146 
1147 static const struct snd_kcontrol_new rt5645_spk_l_mix[] = {
1148 	SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_SPK_L_MIXER,
1149 			RT5645_M_DAC_L1_SM_L_SFT, 1, 1),
1150 	SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_SPK_L_MIXER,
1151 			RT5645_M_DAC_L2_SM_L_SFT, 1, 1),
1152 	SOC_DAPM_SINGLE("INL Switch", RT5645_SPK_L_MIXER,
1153 			RT5645_M_IN_L_SM_L_SFT, 1, 1),
1154 	SOC_DAPM_SINGLE("BST1 Switch", RT5645_SPK_L_MIXER,
1155 			RT5645_M_BST1_L_SM_L_SFT, 1, 1),
1156 };
1157 
1158 static const struct snd_kcontrol_new rt5645_spk_r_mix[] = {
1159 	SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_SPK_R_MIXER,
1160 			RT5645_M_DAC_R1_SM_R_SFT, 1, 1),
1161 	SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_SPK_R_MIXER,
1162 			RT5645_M_DAC_R2_SM_R_SFT, 1, 1),
1163 	SOC_DAPM_SINGLE("INR Switch", RT5645_SPK_R_MIXER,
1164 			RT5645_M_IN_R_SM_R_SFT, 1, 1),
1165 	SOC_DAPM_SINGLE("BST2 Switch", RT5645_SPK_R_MIXER,
1166 			RT5645_M_BST2_R_SM_R_SFT, 1, 1),
1167 };
1168 
1169 static const struct snd_kcontrol_new rt5645_out_l_mix[] = {
1170 	SOC_DAPM_SINGLE("BST1 Switch", RT5645_OUT_L1_MIXER,
1171 			RT5645_M_BST1_OM_L_SFT, 1, 1),
1172 	SOC_DAPM_SINGLE("INL Switch", RT5645_OUT_L1_MIXER,
1173 			RT5645_M_IN_L_OM_L_SFT, 1, 1),
1174 	SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_OUT_L1_MIXER,
1175 			RT5645_M_DAC_L2_OM_L_SFT, 1, 1),
1176 	SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_OUT_L1_MIXER,
1177 			RT5645_M_DAC_L1_OM_L_SFT, 1, 1),
1178 };
1179 
1180 static const struct snd_kcontrol_new rt5645_out_r_mix[] = {
1181 	SOC_DAPM_SINGLE("BST2 Switch", RT5645_OUT_R1_MIXER,
1182 			RT5645_M_BST2_OM_R_SFT, 1, 1),
1183 	SOC_DAPM_SINGLE("INR Switch", RT5645_OUT_R1_MIXER,
1184 			RT5645_M_IN_R_OM_R_SFT, 1, 1),
1185 	SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_OUT_R1_MIXER,
1186 			RT5645_M_DAC_R2_OM_R_SFT, 1, 1),
1187 	SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_OUT_R1_MIXER,
1188 			RT5645_M_DAC_R1_OM_R_SFT, 1, 1),
1189 };
1190 
1191 static const struct snd_kcontrol_new rt5645_spo_l_mix[] = {
1192 	SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_SPO_MIXER,
1193 			RT5645_M_DAC_R1_SPM_L_SFT, 1, 1),
1194 	SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_SPO_MIXER,
1195 			RT5645_M_DAC_L1_SPM_L_SFT, 1, 1),
1196 	SOC_DAPM_SINGLE("SPKVOL R Switch", RT5645_SPO_MIXER,
1197 			RT5645_M_SV_R_SPM_L_SFT, 1, 1),
1198 	SOC_DAPM_SINGLE("SPKVOL L Switch", RT5645_SPO_MIXER,
1199 			RT5645_M_SV_L_SPM_L_SFT, 1, 1),
1200 };
1201 
1202 static const struct snd_kcontrol_new rt5645_spo_r_mix[] = {
1203 	SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_SPO_MIXER,
1204 			RT5645_M_DAC_R1_SPM_R_SFT, 1, 1),
1205 	SOC_DAPM_SINGLE("SPKVOL R Switch", RT5645_SPO_MIXER,
1206 			RT5645_M_SV_R_SPM_R_SFT, 1, 1),
1207 };
1208 
1209 static const struct snd_kcontrol_new rt5645_hpo_mix[] = {
1210 	SOC_DAPM_SINGLE("DAC1 Switch", RT5645_HPO_MIXER,
1211 			RT5645_M_DAC1_HM_SFT, 1, 1),
1212 	SOC_DAPM_SINGLE("HPVOL Switch", RT5645_HPO_MIXER,
1213 			RT5645_M_HPVOL_HM_SFT, 1, 1),
1214 };
1215 
1216 static const struct snd_kcontrol_new rt5645_hpvoll_mix[] = {
1217 	SOC_DAPM_SINGLE("DAC1 Switch", RT5645_HPOMIXL_CTRL,
1218 			RT5645_M_DAC1_HV_SFT, 1, 1),
1219 	SOC_DAPM_SINGLE("DAC2 Switch", RT5645_HPOMIXL_CTRL,
1220 			RT5645_M_DAC2_HV_SFT, 1, 1),
1221 	SOC_DAPM_SINGLE("INL Switch", RT5645_HPOMIXL_CTRL,
1222 			RT5645_M_IN_HV_SFT, 1, 1),
1223 	SOC_DAPM_SINGLE("BST1 Switch", RT5645_HPOMIXL_CTRL,
1224 			RT5645_M_BST1_HV_SFT, 1, 1),
1225 };
1226 
1227 static const struct snd_kcontrol_new rt5645_hpvolr_mix[] = {
1228 	SOC_DAPM_SINGLE("DAC1 Switch", RT5645_HPOMIXR_CTRL,
1229 			RT5645_M_DAC1_HV_SFT, 1, 1),
1230 	SOC_DAPM_SINGLE("DAC2 Switch", RT5645_HPOMIXR_CTRL,
1231 			RT5645_M_DAC2_HV_SFT, 1, 1),
1232 	SOC_DAPM_SINGLE("INR Switch", RT5645_HPOMIXR_CTRL,
1233 			RT5645_M_IN_HV_SFT, 1, 1),
1234 	SOC_DAPM_SINGLE("BST2 Switch", RT5645_HPOMIXR_CTRL,
1235 			RT5645_M_BST2_HV_SFT, 1, 1),
1236 };
1237 
1238 static const struct snd_kcontrol_new rt5645_lout_mix[] = {
1239 	SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_LOUT_MIXER,
1240 			RT5645_M_DAC_L1_LM_SFT, 1, 1),
1241 	SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_LOUT_MIXER,
1242 			RT5645_M_DAC_R1_LM_SFT, 1, 1),
1243 	SOC_DAPM_SINGLE("OUTMIX L Switch", RT5645_LOUT_MIXER,
1244 			RT5645_M_OV_L_LM_SFT, 1, 1),
1245 	SOC_DAPM_SINGLE("OUTMIX R Switch", RT5645_LOUT_MIXER,
1246 			RT5645_M_OV_R_LM_SFT, 1, 1),
1247 };
1248 
1249 /*DAC1 L/R source*/ /* MX-29 [9:8] [11:10] */
1250 static const char * const rt5645_dac1_src[] = {
1251 	"IF1 DAC", "IF2 DAC", "IF3 DAC"
1252 };
1253 
1254 static SOC_ENUM_SINGLE_DECL(
1255 	rt5645_dac1l_enum, RT5645_AD_DA_MIXER,
1256 	RT5645_DAC1_L_SEL_SFT, rt5645_dac1_src);
1257 
1258 static const struct snd_kcontrol_new rt5645_dac1l_mux =
1259 	SOC_DAPM_ENUM("DAC1 L source", rt5645_dac1l_enum);
1260 
1261 static SOC_ENUM_SINGLE_DECL(
1262 	rt5645_dac1r_enum, RT5645_AD_DA_MIXER,
1263 	RT5645_DAC1_R_SEL_SFT, rt5645_dac1_src);
1264 
1265 static const struct snd_kcontrol_new rt5645_dac1r_mux =
1266 	SOC_DAPM_ENUM("DAC1 R source", rt5645_dac1r_enum);
1267 
1268 /*DAC2 L/R source*/ /* MX-1B [6:4] [2:0] */
1269 static const char * const rt5645_dac12_src[] = {
1270 	"IF1 DAC", "IF2 DAC", "IF3 DAC", "Mono ADC", "VAD_ADC"
1271 };
1272 
1273 static SOC_ENUM_SINGLE_DECL(
1274 	rt5645_dac2l_enum, RT5645_DAC_CTRL,
1275 	RT5645_DAC2_L_SEL_SFT, rt5645_dac12_src);
1276 
1277 static const struct snd_kcontrol_new rt5645_dac_l2_mux =
1278 	SOC_DAPM_ENUM("DAC2 L source", rt5645_dac2l_enum);
1279 
1280 static const char * const rt5645_dacr2_src[] = {
1281 	"IF1 DAC", "IF2 DAC", "IF3 DAC", "Mono ADC", "Haptic"
1282 };
1283 
1284 static SOC_ENUM_SINGLE_DECL(
1285 	rt5645_dac2r_enum, RT5645_DAC_CTRL,
1286 	RT5645_DAC2_R_SEL_SFT, rt5645_dacr2_src);
1287 
1288 static const struct snd_kcontrol_new rt5645_dac_r2_mux =
1289 	SOC_DAPM_ENUM("DAC2 R source", rt5645_dac2r_enum);
1290 
1291 
1292 /* INL/R source */
1293 static const char * const rt5645_inl_src[] = {
1294 	"IN2P", "MonoP"
1295 };
1296 
1297 static SOC_ENUM_SINGLE_DECL(
1298 	rt5645_inl_enum, RT5645_INL1_INR1_VOL,
1299 	RT5645_INL_SEL_SFT, rt5645_inl_src);
1300 
1301 static const struct snd_kcontrol_new rt5645_inl_mux =
1302 	SOC_DAPM_ENUM("INL source", rt5645_inl_enum);
1303 
1304 static const char * const rt5645_inr_src[] = {
1305 	"IN2N", "MonoN"
1306 };
1307 
1308 static SOC_ENUM_SINGLE_DECL(
1309 	rt5645_inr_enum, RT5645_INL1_INR1_VOL,
1310 	RT5645_INR_SEL_SFT, rt5645_inr_src);
1311 
1312 static const struct snd_kcontrol_new rt5645_inr_mux =
1313 	SOC_DAPM_ENUM("INR source", rt5645_inr_enum);
1314 
1315 /* Stereo1 ADC source */
1316 /* MX-27 [12] */
1317 static const char * const rt5645_stereo_adc1_src[] = {
1318 	"DAC MIX", "ADC"
1319 };
1320 
1321 static SOC_ENUM_SINGLE_DECL(
1322 	rt5645_stereo1_adc1_enum, RT5645_STO1_ADC_MIXER,
1323 	RT5645_ADC_1_SRC_SFT, rt5645_stereo_adc1_src);
1324 
1325 static const struct snd_kcontrol_new rt5645_sto_adc1_mux =
1326 	SOC_DAPM_ENUM("Stereo1 ADC1 Mux", rt5645_stereo1_adc1_enum);
1327 
1328 /* MX-27 [11] */
1329 static const char * const rt5645_stereo_adc2_src[] = {
1330 	"DAC MIX", "DMIC"
1331 };
1332 
1333 static SOC_ENUM_SINGLE_DECL(
1334 	rt5645_stereo1_adc2_enum, RT5645_STO1_ADC_MIXER,
1335 	RT5645_ADC_2_SRC_SFT, rt5645_stereo_adc2_src);
1336 
1337 static const struct snd_kcontrol_new rt5645_sto_adc2_mux =
1338 	SOC_DAPM_ENUM("Stereo1 ADC2 Mux", rt5645_stereo1_adc2_enum);
1339 
1340 /* MX-27 [8] */
1341 static const char * const rt5645_stereo_dmic_src[] = {
1342 	"DMIC1", "DMIC2"
1343 };
1344 
1345 static SOC_ENUM_SINGLE_DECL(
1346 	rt5645_stereo1_dmic_enum, RT5645_STO1_ADC_MIXER,
1347 	RT5645_DMIC_SRC_SFT, rt5645_stereo_dmic_src);
1348 
1349 static const struct snd_kcontrol_new rt5645_sto1_dmic_mux =
1350 	SOC_DAPM_ENUM("Stereo1 DMIC source", rt5645_stereo1_dmic_enum);
1351 
1352 /* Mono ADC source */
1353 /* MX-28 [12] */
1354 static const char * const rt5645_mono_adc_l1_src[] = {
1355 	"Mono DAC MIXL", "ADC"
1356 };
1357 
1358 static SOC_ENUM_SINGLE_DECL(
1359 	rt5645_mono_adc_l1_enum, RT5645_MONO_ADC_MIXER,
1360 	RT5645_MONO_ADC_L1_SRC_SFT, rt5645_mono_adc_l1_src);
1361 
1362 static const struct snd_kcontrol_new rt5645_mono_adc_l1_mux =
1363 	SOC_DAPM_ENUM("Mono ADC1 left source", rt5645_mono_adc_l1_enum);
1364 /* MX-28 [11] */
1365 static const char * const rt5645_mono_adc_l2_src[] = {
1366 	"Mono DAC MIXL", "DMIC"
1367 };
1368 
1369 static SOC_ENUM_SINGLE_DECL(
1370 	rt5645_mono_adc_l2_enum, RT5645_MONO_ADC_MIXER,
1371 	RT5645_MONO_ADC_L2_SRC_SFT, rt5645_mono_adc_l2_src);
1372 
1373 static const struct snd_kcontrol_new rt5645_mono_adc_l2_mux =
1374 	SOC_DAPM_ENUM("Mono ADC2 left source", rt5645_mono_adc_l2_enum);
1375 
1376 /* MX-28 [8] */
1377 static const char * const rt5645_mono_dmic_src[] = {
1378 	"DMIC1", "DMIC2"
1379 };
1380 
1381 static SOC_ENUM_SINGLE_DECL(
1382 	rt5645_mono_dmic_l_enum, RT5645_MONO_ADC_MIXER,
1383 	RT5645_MONO_DMIC_L_SRC_SFT, rt5645_mono_dmic_src);
1384 
1385 static const struct snd_kcontrol_new rt5645_mono_dmic_l_mux =
1386 	SOC_DAPM_ENUM("Mono DMIC left source", rt5645_mono_dmic_l_enum);
1387 /* MX-28 [1:0] */
1388 static SOC_ENUM_SINGLE_DECL(
1389 	rt5645_mono_dmic_r_enum, RT5645_MONO_ADC_MIXER,
1390 	RT5645_MONO_DMIC_R_SRC_SFT, rt5645_mono_dmic_src);
1391 
1392 static const struct snd_kcontrol_new rt5645_mono_dmic_r_mux =
1393 	SOC_DAPM_ENUM("Mono DMIC Right source", rt5645_mono_dmic_r_enum);
1394 /* MX-28 [4] */
1395 static const char * const rt5645_mono_adc_r1_src[] = {
1396 	"Mono DAC MIXR", "ADC"
1397 };
1398 
1399 static SOC_ENUM_SINGLE_DECL(
1400 	rt5645_mono_adc_r1_enum, RT5645_MONO_ADC_MIXER,
1401 	RT5645_MONO_ADC_R1_SRC_SFT, rt5645_mono_adc_r1_src);
1402 
1403 static const struct snd_kcontrol_new rt5645_mono_adc_r1_mux =
1404 	SOC_DAPM_ENUM("Mono ADC1 right source", rt5645_mono_adc_r1_enum);
1405 /* MX-28 [3] */
1406 static const char * const rt5645_mono_adc_r2_src[] = {
1407 	"Mono DAC MIXR", "DMIC"
1408 };
1409 
1410 static SOC_ENUM_SINGLE_DECL(
1411 	rt5645_mono_adc_r2_enum, RT5645_MONO_ADC_MIXER,
1412 	RT5645_MONO_ADC_R2_SRC_SFT, rt5645_mono_adc_r2_src);
1413 
1414 static const struct snd_kcontrol_new rt5645_mono_adc_r2_mux =
1415 	SOC_DAPM_ENUM("Mono ADC2 right source", rt5645_mono_adc_r2_enum);
1416 
1417 /* MX-77 [9:8] */
1418 static const char * const rt5645_if1_adc_in_src[] = {
1419 	"IF_ADC1/IF_ADC2/VAD_ADC", "IF_ADC2/IF_ADC1/VAD_ADC",
1420 	"VAD_ADC/IF_ADC1/IF_ADC2", "VAD_ADC/IF_ADC2/IF_ADC1"
1421 };
1422 
1423 static SOC_ENUM_SINGLE_DECL(
1424 	rt5645_if1_adc_in_enum, RT5645_TDM_CTRL_1,
1425 	RT5645_IF1_ADC_IN_SFT, rt5645_if1_adc_in_src);
1426 
1427 static const struct snd_kcontrol_new rt5645_if1_adc_in_mux =
1428 	SOC_DAPM_ENUM("IF1 ADC IN source", rt5645_if1_adc_in_enum);
1429 
1430 /* MX-78 [4:0] */
1431 static const char * const rt5650_if1_adc_in_src[] = {
1432 	"IF_ADC1/IF_ADC2/DAC_REF/Null",
1433 	"IF_ADC1/IF_ADC2/Null/DAC_REF",
1434 	"IF_ADC1/DAC_REF/IF_ADC2/Null",
1435 	"IF_ADC1/DAC_REF/Null/IF_ADC2",
1436 	"IF_ADC1/Null/DAC_REF/IF_ADC2",
1437 	"IF_ADC1/Null/IF_ADC2/DAC_REF",
1438 
1439 	"IF_ADC2/IF_ADC1/DAC_REF/Null",
1440 	"IF_ADC2/IF_ADC1/Null/DAC_REF",
1441 	"IF_ADC2/DAC_REF/IF_ADC1/Null",
1442 	"IF_ADC2/DAC_REF/Null/IF_ADC1",
1443 	"IF_ADC2/Null/DAC_REF/IF_ADC1",
1444 	"IF_ADC2/Null/IF_ADC1/DAC_REF",
1445 
1446 	"DAC_REF/IF_ADC1/IF_ADC2/Null",
1447 	"DAC_REF/IF_ADC1/Null/IF_ADC2",
1448 	"DAC_REF/IF_ADC2/IF_ADC1/Null",
1449 	"DAC_REF/IF_ADC2/Null/IF_ADC1",
1450 	"DAC_REF/Null/IF_ADC1/IF_ADC2",
1451 	"DAC_REF/Null/IF_ADC2/IF_ADC1",
1452 
1453 	"Null/IF_ADC1/IF_ADC2/DAC_REF",
1454 	"Null/IF_ADC1/DAC_REF/IF_ADC2",
1455 	"Null/IF_ADC2/IF_ADC1/DAC_REF",
1456 	"Null/IF_ADC2/DAC_REF/IF_ADC1",
1457 	"Null/DAC_REF/IF_ADC1/IF_ADC2",
1458 	"Null/DAC_REF/IF_ADC2/IF_ADC1",
1459 };
1460 
1461 static SOC_ENUM_SINGLE_DECL(
1462 	rt5650_if1_adc_in_enum, RT5645_TDM_CTRL_2,
1463 	0, rt5650_if1_adc_in_src);
1464 
1465 static const struct snd_kcontrol_new rt5650_if1_adc_in_mux =
1466 	SOC_DAPM_ENUM("IF1 ADC IN source", rt5650_if1_adc_in_enum);
1467 
1468 /* MX-78 [15:14][13:12][11:10] */
1469 static const char * const rt5645_tdm_adc_swap_select[] = {
1470 	"L/R", "R/L", "L/L", "R/R"
1471 };
1472 
1473 static SOC_ENUM_SINGLE_DECL(rt5650_tdm_adc_slot0_1_enum,
1474 	RT5645_TDM_CTRL_2, 14, rt5645_tdm_adc_swap_select);
1475 
1476 static const struct snd_kcontrol_new rt5650_if1_adc1_in_mux =
1477 	SOC_DAPM_ENUM("IF1 ADC1 IN source", rt5650_tdm_adc_slot0_1_enum);
1478 
1479 static SOC_ENUM_SINGLE_DECL(rt5650_tdm_adc_slot2_3_enum,
1480 	RT5645_TDM_CTRL_2, 12, rt5645_tdm_adc_swap_select);
1481 
1482 static const struct snd_kcontrol_new rt5650_if1_adc2_in_mux =
1483 	SOC_DAPM_ENUM("IF1 ADC2 IN source", rt5650_tdm_adc_slot2_3_enum);
1484 
1485 static SOC_ENUM_SINGLE_DECL(rt5650_tdm_adc_slot4_5_enum,
1486 	RT5645_TDM_CTRL_2, 10, rt5645_tdm_adc_swap_select);
1487 
1488 static const struct snd_kcontrol_new rt5650_if1_adc3_in_mux =
1489 	SOC_DAPM_ENUM("IF1 ADC3 IN source", rt5650_tdm_adc_slot4_5_enum);
1490 
1491 /* MX-77 [7:6][5:4][3:2] */
1492 static SOC_ENUM_SINGLE_DECL(rt5645_tdm_adc_slot0_1_enum,
1493 	RT5645_TDM_CTRL_1, 6, rt5645_tdm_adc_swap_select);
1494 
1495 static const struct snd_kcontrol_new rt5645_if1_adc1_in_mux =
1496 	SOC_DAPM_ENUM("IF1 ADC1 IN source", rt5645_tdm_adc_slot0_1_enum);
1497 
1498 static SOC_ENUM_SINGLE_DECL(rt5645_tdm_adc_slot2_3_enum,
1499 	RT5645_TDM_CTRL_1, 4, rt5645_tdm_adc_swap_select);
1500 
1501 static const struct snd_kcontrol_new rt5645_if1_adc2_in_mux =
1502 	SOC_DAPM_ENUM("IF1 ADC2 IN source", rt5645_tdm_adc_slot2_3_enum);
1503 
1504 static SOC_ENUM_SINGLE_DECL(rt5645_tdm_adc_slot4_5_enum,
1505 	RT5645_TDM_CTRL_1, 2, rt5645_tdm_adc_swap_select);
1506 
1507 static const struct snd_kcontrol_new rt5645_if1_adc3_in_mux =
1508 	SOC_DAPM_ENUM("IF1 ADC3 IN source", rt5645_tdm_adc_slot4_5_enum);
1509 
1510 /* MX-79 [14:12][10:8][6:4][2:0] */
1511 static const char * const rt5645_tdm_dac_swap_select[] = {
1512 	"Slot0", "Slot1", "Slot2", "Slot3"
1513 };
1514 
1515 static SOC_ENUM_SINGLE_DECL(rt5645_tdm_dac0_enum,
1516 	RT5645_TDM_CTRL_3, 12, rt5645_tdm_dac_swap_select);
1517 
1518 static const struct snd_kcontrol_new rt5645_if1_dac0_tdm_sel_mux =
1519 	SOC_DAPM_ENUM("IF1 DAC0 source", rt5645_tdm_dac0_enum);
1520 
1521 static SOC_ENUM_SINGLE_DECL(rt5645_tdm_dac1_enum,
1522 	RT5645_TDM_CTRL_3, 8, rt5645_tdm_dac_swap_select);
1523 
1524 static const struct snd_kcontrol_new rt5645_if1_dac1_tdm_sel_mux =
1525 	SOC_DAPM_ENUM("IF1 DAC1 source", rt5645_tdm_dac1_enum);
1526 
1527 static SOC_ENUM_SINGLE_DECL(rt5645_tdm_dac2_enum,
1528 	RT5645_TDM_CTRL_3, 4, rt5645_tdm_dac_swap_select);
1529 
1530 static const struct snd_kcontrol_new rt5645_if1_dac2_tdm_sel_mux =
1531 	SOC_DAPM_ENUM("IF1 DAC2 source", rt5645_tdm_dac2_enum);
1532 
1533 static SOC_ENUM_SINGLE_DECL(rt5645_tdm_dac3_enum,
1534 	RT5645_TDM_CTRL_3, 0, rt5645_tdm_dac_swap_select);
1535 
1536 static const struct snd_kcontrol_new rt5645_if1_dac3_tdm_sel_mux =
1537 	SOC_DAPM_ENUM("IF1 DAC3 source", rt5645_tdm_dac3_enum);
1538 
1539 /* MX-7a [14:12][10:8][6:4][2:0] */
1540 static SOC_ENUM_SINGLE_DECL(rt5650_tdm_dac0_enum,
1541 	RT5650_TDM_CTRL_4, 12, rt5645_tdm_dac_swap_select);
1542 
1543 static const struct snd_kcontrol_new rt5650_if1_dac0_tdm_sel_mux =
1544 	SOC_DAPM_ENUM("IF1 DAC0 source", rt5650_tdm_dac0_enum);
1545 
1546 static SOC_ENUM_SINGLE_DECL(rt5650_tdm_dac1_enum,
1547 	RT5650_TDM_CTRL_4, 8, rt5645_tdm_dac_swap_select);
1548 
1549 static const struct snd_kcontrol_new rt5650_if1_dac1_tdm_sel_mux =
1550 	SOC_DAPM_ENUM("IF1 DAC1 source", rt5650_tdm_dac1_enum);
1551 
1552 static SOC_ENUM_SINGLE_DECL(rt5650_tdm_dac2_enum,
1553 	RT5650_TDM_CTRL_4, 4, rt5645_tdm_dac_swap_select);
1554 
1555 static const struct snd_kcontrol_new rt5650_if1_dac2_tdm_sel_mux =
1556 	SOC_DAPM_ENUM("IF1 DAC2 source", rt5650_tdm_dac2_enum);
1557 
1558 static SOC_ENUM_SINGLE_DECL(rt5650_tdm_dac3_enum,
1559 	RT5650_TDM_CTRL_4, 0, rt5645_tdm_dac_swap_select);
1560 
1561 static const struct snd_kcontrol_new rt5650_if1_dac3_tdm_sel_mux =
1562 	SOC_DAPM_ENUM("IF1 DAC3 source", rt5650_tdm_dac3_enum);
1563 
1564 /* MX-2d [3] [2] */
1565 static const char * const rt5650_a_dac1_src[] = {
1566 	"DAC1", "Stereo DAC Mixer"
1567 };
1568 
1569 static SOC_ENUM_SINGLE_DECL(
1570 	rt5650_a_dac1_l_enum, RT5650_A_DAC_SOUR,
1571 	RT5650_A_DAC1_L_IN_SFT, rt5650_a_dac1_src);
1572 
1573 static const struct snd_kcontrol_new rt5650_a_dac1_l_mux =
1574 	SOC_DAPM_ENUM("A DAC1 L source", rt5650_a_dac1_l_enum);
1575 
1576 static SOC_ENUM_SINGLE_DECL(
1577 	rt5650_a_dac1_r_enum, RT5650_A_DAC_SOUR,
1578 	RT5650_A_DAC1_R_IN_SFT, rt5650_a_dac1_src);
1579 
1580 static const struct snd_kcontrol_new rt5650_a_dac1_r_mux =
1581 	SOC_DAPM_ENUM("A DAC1 R source", rt5650_a_dac1_r_enum);
1582 
1583 /* MX-2d [1] [0] */
1584 static const char * const rt5650_a_dac2_src[] = {
1585 	"Stereo DAC Mixer", "Mono DAC Mixer"
1586 };
1587 
1588 static SOC_ENUM_SINGLE_DECL(
1589 	rt5650_a_dac2_l_enum, RT5650_A_DAC_SOUR,
1590 	RT5650_A_DAC2_L_IN_SFT, rt5650_a_dac2_src);
1591 
1592 static const struct snd_kcontrol_new rt5650_a_dac2_l_mux =
1593 	SOC_DAPM_ENUM("A DAC2 L source", rt5650_a_dac2_l_enum);
1594 
1595 static SOC_ENUM_SINGLE_DECL(
1596 	rt5650_a_dac2_r_enum, RT5650_A_DAC_SOUR,
1597 	RT5650_A_DAC2_R_IN_SFT, rt5650_a_dac2_src);
1598 
1599 static const struct snd_kcontrol_new rt5650_a_dac2_r_mux =
1600 	SOC_DAPM_ENUM("A DAC2 R source", rt5650_a_dac2_r_enum);
1601 
1602 /* MX-2F [13:12] */
1603 static const char * const rt5645_if2_adc_in_src[] = {
1604 	"IF_ADC1", "IF_ADC2", "VAD_ADC"
1605 };
1606 
1607 static SOC_ENUM_SINGLE_DECL(
1608 	rt5645_if2_adc_in_enum, RT5645_DIG_INF1_DATA,
1609 	RT5645_IF2_ADC_IN_SFT, rt5645_if2_adc_in_src);
1610 
1611 static const struct snd_kcontrol_new rt5645_if2_adc_in_mux =
1612 	SOC_DAPM_ENUM("IF2 ADC IN source", rt5645_if2_adc_in_enum);
1613 
1614 /* MX-2F [1:0] */
1615 static const char * const rt5645_if3_adc_in_src[] = {
1616 	"IF_ADC1", "IF_ADC2", "VAD_ADC"
1617 };
1618 
1619 static SOC_ENUM_SINGLE_DECL(
1620 	rt5645_if3_adc_in_enum, RT5645_DIG_INF1_DATA,
1621 	RT5645_IF3_ADC_IN_SFT, rt5645_if3_adc_in_src);
1622 
1623 static const struct snd_kcontrol_new rt5645_if3_adc_in_mux =
1624 	SOC_DAPM_ENUM("IF3 ADC IN source", rt5645_if3_adc_in_enum);
1625 
1626 /* MX-31 [15] [13] [11] [9] */
1627 static const char * const rt5645_pdm_src[] = {
1628 	"Mono DAC", "Stereo DAC"
1629 };
1630 
1631 static SOC_ENUM_SINGLE_DECL(
1632 	rt5645_pdm1_l_enum, RT5645_PDM_OUT_CTRL,
1633 	RT5645_PDM1_L_SFT, rt5645_pdm_src);
1634 
1635 static const struct snd_kcontrol_new rt5645_pdm1_l_mux =
1636 	SOC_DAPM_ENUM("PDM1 L source", rt5645_pdm1_l_enum);
1637 
1638 static SOC_ENUM_SINGLE_DECL(
1639 	rt5645_pdm1_r_enum, RT5645_PDM_OUT_CTRL,
1640 	RT5645_PDM1_R_SFT, rt5645_pdm_src);
1641 
1642 static const struct snd_kcontrol_new rt5645_pdm1_r_mux =
1643 	SOC_DAPM_ENUM("PDM1 R source", rt5645_pdm1_r_enum);
1644 
1645 /* MX-9D [9:8] */
1646 static const char * const rt5645_vad_adc_src[] = {
1647 	"Sto1 ADC L", "Mono ADC L", "Mono ADC R"
1648 };
1649 
1650 static SOC_ENUM_SINGLE_DECL(
1651 	rt5645_vad_adc_enum, RT5645_VAD_CTRL4,
1652 	RT5645_VAD_SEL_SFT, rt5645_vad_adc_src);
1653 
1654 static const struct snd_kcontrol_new rt5645_vad_adc_mux =
1655 	SOC_DAPM_ENUM("VAD ADC source", rt5645_vad_adc_enum);
1656 
1657 static const struct snd_kcontrol_new spk_l_vol_control =
1658 	SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_SPK_VOL,
1659 		RT5645_L_MUTE_SFT, 1, 1);
1660 
1661 static const struct snd_kcontrol_new spk_r_vol_control =
1662 	SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_SPK_VOL,
1663 		RT5645_R_MUTE_SFT, 1, 1);
1664 
1665 static const struct snd_kcontrol_new hp_l_vol_control =
1666 	SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_HP_VOL,
1667 		RT5645_L_MUTE_SFT, 1, 1);
1668 
1669 static const struct snd_kcontrol_new hp_r_vol_control =
1670 	SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_HP_VOL,
1671 		RT5645_R_MUTE_SFT, 1, 1);
1672 
1673 static const struct snd_kcontrol_new pdm1_l_vol_control =
1674 	SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_PDM_OUT_CTRL,
1675 		RT5645_M_PDM1_L, 1, 1);
1676 
1677 static const struct snd_kcontrol_new pdm1_r_vol_control =
1678 	SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_PDM_OUT_CTRL,
1679 		RT5645_M_PDM1_R, 1, 1);
1680 
1681 static void hp_amp_power(struct snd_soc_codec *codec, int on)
1682 {
1683 	static int hp_amp_power_count;
1684 	struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
1685 
1686 	if (on) {
1687 		if (hp_amp_power_count <= 0) {
1688 			if (rt5645->codec_type == CODEC_TYPE_RT5650) {
1689 				snd_soc_write(codec, RT5645_DEPOP_M2, 0x3100);
1690 				snd_soc_write(codec, RT5645_CHARGE_PUMP,
1691 					0x0e06);
1692 				snd_soc_write(codec, RT5645_DEPOP_M1, 0x000d);
1693 				regmap_write(rt5645->regmap, RT5645_PR_BASE +
1694 					RT5645_HP_DCC_INT1, 0x9f01);
1695 				msleep(20);
1696 				snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1697 					RT5645_HP_CO_MASK, RT5645_HP_CO_EN);
1698 				regmap_write(rt5645->regmap, RT5645_PR_BASE +
1699 					0x3e, 0x7400);
1700 				snd_soc_write(codec, RT5645_DEPOP_M3, 0x0737);
1701 				regmap_write(rt5645->regmap, RT5645_PR_BASE +
1702 					RT5645_MAMP_INT_REG2, 0xfc00);
1703 				snd_soc_write(codec, RT5645_DEPOP_M2, 0x1140);
1704 				msleep(90);
1705 				rt5645->hp_on = true;
1706 			} else {
1707 				/* depop parameters */
1708 				snd_soc_update_bits(codec, RT5645_DEPOP_M2,
1709 					RT5645_DEPOP_MASK, RT5645_DEPOP_MAN);
1710 				snd_soc_write(codec, RT5645_DEPOP_M1, 0x000d);
1711 				regmap_write(rt5645->regmap, RT5645_PR_BASE +
1712 					RT5645_HP_DCC_INT1, 0x9f01);
1713 				mdelay(150);
1714 				/* headphone amp power on */
1715 				snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
1716 					RT5645_PWR_FV1 | RT5645_PWR_FV2, 0);
1717 				snd_soc_update_bits(codec, RT5645_PWR_VOL,
1718 					RT5645_PWR_HV_L | RT5645_PWR_HV_R,
1719 					RT5645_PWR_HV_L | RT5645_PWR_HV_R);
1720 				snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
1721 					RT5645_PWR_HP_L | RT5645_PWR_HP_R |
1722 					RT5645_PWR_HA,
1723 					RT5645_PWR_HP_L | RT5645_PWR_HP_R |
1724 					RT5645_PWR_HA);
1725 				mdelay(5);
1726 				snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
1727 					RT5645_PWR_FV1 | RT5645_PWR_FV2,
1728 					RT5645_PWR_FV1 | RT5645_PWR_FV2);
1729 
1730 				snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1731 					RT5645_HP_CO_MASK | RT5645_HP_SG_MASK,
1732 					RT5645_HP_CO_EN | RT5645_HP_SG_EN);
1733 				regmap_write(rt5645->regmap, RT5645_PR_BASE +
1734 					0x14, 0x1aaa);
1735 				regmap_write(rt5645->regmap, RT5645_PR_BASE +
1736 					0x24, 0x0430);
1737 			}
1738 		}
1739 		hp_amp_power_count++;
1740 	} else {
1741 		hp_amp_power_count--;
1742 		if (hp_amp_power_count <= 0) {
1743 			if (rt5645->codec_type == CODEC_TYPE_RT5650) {
1744 				regmap_write(rt5645->regmap, RT5645_PR_BASE +
1745 					0x3e, 0x7400);
1746 				snd_soc_write(codec, RT5645_DEPOP_M3, 0x0737);
1747 				regmap_write(rt5645->regmap, RT5645_PR_BASE +
1748 					RT5645_MAMP_INT_REG2, 0xfc00);
1749 				snd_soc_write(codec, RT5645_DEPOP_M2, 0x1140);
1750 				msleep(100);
1751 				snd_soc_write(codec, RT5645_DEPOP_M1, 0x0001);
1752 
1753 			} else {
1754 				snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1755 					RT5645_HP_SG_MASK |
1756 					RT5645_HP_L_SMT_MASK |
1757 					RT5645_HP_R_SMT_MASK,
1758 					RT5645_HP_SG_DIS |
1759 					RT5645_HP_L_SMT_DIS |
1760 					RT5645_HP_R_SMT_DIS);
1761 				/* headphone amp power down */
1762 				snd_soc_write(codec, RT5645_DEPOP_M1, 0x0000);
1763 				snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
1764 					RT5645_PWR_HP_L | RT5645_PWR_HP_R |
1765 					RT5645_PWR_HA, 0);
1766 				snd_soc_update_bits(codec, RT5645_DEPOP_M2,
1767 					RT5645_DEPOP_MASK, 0);
1768 			}
1769 		}
1770 	}
1771 }
1772 
1773 static int rt5645_hp_event(struct snd_soc_dapm_widget *w,
1774 	struct snd_kcontrol *kcontrol, int event)
1775 {
1776 	struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1777 	struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
1778 
1779 	switch (event) {
1780 	case SND_SOC_DAPM_POST_PMU:
1781 		hp_amp_power(codec, 1);
1782 		/* headphone unmute sequence */
1783 		if (rt5645->codec_type == CODEC_TYPE_RT5645) {
1784 			snd_soc_update_bits(codec, RT5645_DEPOP_M3,
1785 				RT5645_CP_FQ1_MASK | RT5645_CP_FQ2_MASK |
1786 				RT5645_CP_FQ3_MASK,
1787 				(RT5645_CP_FQ_192_KHZ << RT5645_CP_FQ1_SFT) |
1788 				(RT5645_CP_FQ_12_KHZ << RT5645_CP_FQ2_SFT) |
1789 				(RT5645_CP_FQ_192_KHZ << RT5645_CP_FQ3_SFT));
1790 			regmap_write(rt5645->regmap, RT5645_PR_BASE +
1791 				RT5645_MAMP_INT_REG2, 0xfc00);
1792 			snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1793 				RT5645_SMT_TRIG_MASK, RT5645_SMT_TRIG_EN);
1794 			snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1795 				RT5645_RSTN_MASK, RT5645_RSTN_EN);
1796 			snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1797 				RT5645_RSTN_MASK | RT5645_HP_L_SMT_MASK |
1798 				RT5645_HP_R_SMT_MASK, RT5645_RSTN_DIS |
1799 				RT5645_HP_L_SMT_EN | RT5645_HP_R_SMT_EN);
1800 			msleep(40);
1801 			snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1802 				RT5645_HP_SG_MASK | RT5645_HP_L_SMT_MASK |
1803 				RT5645_HP_R_SMT_MASK, RT5645_HP_SG_DIS |
1804 				RT5645_HP_L_SMT_DIS | RT5645_HP_R_SMT_DIS);
1805 		}
1806 		break;
1807 
1808 	case SND_SOC_DAPM_PRE_PMD:
1809 		/* headphone mute sequence */
1810 		if (rt5645->codec_type == CODEC_TYPE_RT5645) {
1811 			snd_soc_update_bits(codec, RT5645_DEPOP_M3,
1812 				RT5645_CP_FQ1_MASK | RT5645_CP_FQ2_MASK |
1813 				RT5645_CP_FQ3_MASK,
1814 				(RT5645_CP_FQ_96_KHZ << RT5645_CP_FQ1_SFT) |
1815 				(RT5645_CP_FQ_12_KHZ << RT5645_CP_FQ2_SFT) |
1816 				(RT5645_CP_FQ_96_KHZ << RT5645_CP_FQ3_SFT));
1817 			regmap_write(rt5645->regmap, RT5645_PR_BASE +
1818 				RT5645_MAMP_INT_REG2, 0xfc00);
1819 			snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1820 				RT5645_HP_SG_MASK, RT5645_HP_SG_EN);
1821 			snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1822 				RT5645_RSTP_MASK, RT5645_RSTP_EN);
1823 			snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1824 				RT5645_RSTP_MASK | RT5645_HP_L_SMT_MASK |
1825 				RT5645_HP_R_SMT_MASK, RT5645_RSTP_DIS |
1826 				RT5645_HP_L_SMT_EN | RT5645_HP_R_SMT_EN);
1827 			msleep(30);
1828 		}
1829 		hp_amp_power(codec, 0);
1830 		break;
1831 
1832 	default:
1833 		return 0;
1834 	}
1835 
1836 	return 0;
1837 }
1838 
1839 static int rt5645_spk_event(struct snd_soc_dapm_widget *w,
1840 	struct snd_kcontrol *kcontrol, int event)
1841 {
1842 	struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1843 
1844 	switch (event) {
1845 	case SND_SOC_DAPM_POST_PMU:
1846 		rt5645_enable_hweq(codec);
1847 		snd_soc_update_bits(codec, RT5645_PWR_DIG1,
1848 			RT5645_PWR_CLS_D | RT5645_PWR_CLS_D_R |
1849 			RT5645_PWR_CLS_D_L,
1850 			RT5645_PWR_CLS_D | RT5645_PWR_CLS_D_R |
1851 			RT5645_PWR_CLS_D_L);
1852 		snd_soc_update_bits(codec, RT5645_GEN_CTRL3,
1853 			RT5645_DET_CLK_MASK, RT5645_DET_CLK_MODE1);
1854 		break;
1855 
1856 	case SND_SOC_DAPM_PRE_PMD:
1857 		snd_soc_update_bits(codec, RT5645_GEN_CTRL3,
1858 			RT5645_DET_CLK_MASK, RT5645_DET_CLK_DIS);
1859 		snd_soc_write(codec, RT5645_EQ_CTRL2, 0);
1860 		snd_soc_update_bits(codec, RT5645_PWR_DIG1,
1861 			RT5645_PWR_CLS_D | RT5645_PWR_CLS_D_R |
1862 			RT5645_PWR_CLS_D_L, 0);
1863 		break;
1864 
1865 	default:
1866 		return 0;
1867 	}
1868 
1869 	return 0;
1870 }
1871 
1872 static int rt5645_lout_event(struct snd_soc_dapm_widget *w,
1873 	struct snd_kcontrol *kcontrol, int event)
1874 {
1875 	struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1876 
1877 	switch (event) {
1878 	case SND_SOC_DAPM_POST_PMU:
1879 		hp_amp_power(codec, 1);
1880 		snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
1881 			RT5645_PWR_LM, RT5645_PWR_LM);
1882 		snd_soc_update_bits(codec, RT5645_LOUT1,
1883 			RT5645_L_MUTE | RT5645_R_MUTE, 0);
1884 		break;
1885 
1886 	case SND_SOC_DAPM_PRE_PMD:
1887 		snd_soc_update_bits(codec, RT5645_LOUT1,
1888 			RT5645_L_MUTE | RT5645_R_MUTE,
1889 			RT5645_L_MUTE | RT5645_R_MUTE);
1890 		snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
1891 			RT5645_PWR_LM, 0);
1892 		hp_amp_power(codec, 0);
1893 		break;
1894 
1895 	default:
1896 		return 0;
1897 	}
1898 
1899 	return 0;
1900 }
1901 
1902 static int rt5645_bst2_event(struct snd_soc_dapm_widget *w,
1903 	struct snd_kcontrol *kcontrol, int event)
1904 {
1905 	struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1906 
1907 	switch (event) {
1908 	case SND_SOC_DAPM_POST_PMU:
1909 		snd_soc_update_bits(codec, RT5645_PWR_ANLG2,
1910 			RT5645_PWR_BST2_P, RT5645_PWR_BST2_P);
1911 		break;
1912 
1913 	case SND_SOC_DAPM_PRE_PMD:
1914 		snd_soc_update_bits(codec, RT5645_PWR_ANLG2,
1915 			RT5645_PWR_BST2_P, 0);
1916 		break;
1917 
1918 	default:
1919 		return 0;
1920 	}
1921 
1922 	return 0;
1923 }
1924 
1925 static int rt5650_hp_event(struct snd_soc_dapm_widget *w,
1926 		struct snd_kcontrol *k, int  event)
1927 {
1928 	struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1929 	struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
1930 
1931 	switch (event) {
1932 	case SND_SOC_DAPM_POST_PMU:
1933 		if (rt5645->hp_on) {
1934 			msleep(100);
1935 			rt5645->hp_on = false;
1936 		}
1937 		break;
1938 
1939 	default:
1940 		return 0;
1941 	}
1942 
1943 	return 0;
1944 }
1945 
1946 static const struct snd_soc_dapm_widget rt5645_dapm_widgets[] = {
1947 	SND_SOC_DAPM_SUPPLY("LDO2", RT5645_PWR_MIXER,
1948 		RT5645_PWR_LDO2_BIT, 0, NULL, 0),
1949 	SND_SOC_DAPM_SUPPLY("PLL1", RT5645_PWR_ANLG2,
1950 		RT5645_PWR_PLL_BIT, 0, NULL, 0),
1951 
1952 	SND_SOC_DAPM_SUPPLY("JD Power", RT5645_PWR_ANLG2,
1953 		RT5645_PWR_JD1_BIT, 0, NULL, 0),
1954 	SND_SOC_DAPM_SUPPLY("Mic Det Power", RT5645_PWR_VOL,
1955 		RT5645_PWR_MIC_DET_BIT, 0, NULL, 0),
1956 
1957 	/* ASRC */
1958 	SND_SOC_DAPM_SUPPLY_S("I2S1 ASRC", 1, RT5645_ASRC_1,
1959 			      11, 0, NULL, 0),
1960 	SND_SOC_DAPM_SUPPLY_S("I2S2 ASRC", 1, RT5645_ASRC_1,
1961 			      12, 0, NULL, 0),
1962 	SND_SOC_DAPM_SUPPLY_S("DAC STO ASRC", 1, RT5645_ASRC_1,
1963 			      10, 0, NULL, 0),
1964 	SND_SOC_DAPM_SUPPLY_S("DAC MONO L ASRC", 1, RT5645_ASRC_1,
1965 			      9, 0, NULL, 0),
1966 	SND_SOC_DAPM_SUPPLY_S("DAC MONO R ASRC", 1, RT5645_ASRC_1,
1967 			      8, 0, NULL, 0),
1968 	SND_SOC_DAPM_SUPPLY_S("DMIC STO1 ASRC", 1, RT5645_ASRC_1,
1969 			      7, 0, NULL, 0),
1970 	SND_SOC_DAPM_SUPPLY_S("DMIC MONO L ASRC", 1, RT5645_ASRC_1,
1971 			      5, 0, NULL, 0),
1972 	SND_SOC_DAPM_SUPPLY_S("DMIC MONO R ASRC", 1, RT5645_ASRC_1,
1973 			      4, 0, NULL, 0),
1974 	SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5645_ASRC_1,
1975 			      3, 0, NULL, 0),
1976 	SND_SOC_DAPM_SUPPLY_S("ADC MONO L ASRC", 1, RT5645_ASRC_1,
1977 			      1, 0, NULL, 0),
1978 	SND_SOC_DAPM_SUPPLY_S("ADC MONO R ASRC", 1, RT5645_ASRC_1,
1979 			      0, 0, NULL, 0),
1980 
1981 	/* Input Side */
1982 	/* micbias */
1983 	SND_SOC_DAPM_MICBIAS("micbias1", RT5645_PWR_ANLG2,
1984 			RT5645_PWR_MB1_BIT, 0),
1985 	SND_SOC_DAPM_MICBIAS("micbias2", RT5645_PWR_ANLG2,
1986 			RT5645_PWR_MB2_BIT, 0),
1987 	/* Input Lines */
1988 	SND_SOC_DAPM_INPUT("DMIC L1"),
1989 	SND_SOC_DAPM_INPUT("DMIC R1"),
1990 	SND_SOC_DAPM_INPUT("DMIC L2"),
1991 	SND_SOC_DAPM_INPUT("DMIC R2"),
1992 
1993 	SND_SOC_DAPM_INPUT("IN1P"),
1994 	SND_SOC_DAPM_INPUT("IN1N"),
1995 	SND_SOC_DAPM_INPUT("IN2P"),
1996 	SND_SOC_DAPM_INPUT("IN2N"),
1997 
1998 	SND_SOC_DAPM_INPUT("Haptic Generator"),
1999 
2000 	SND_SOC_DAPM_PGA("DMIC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2001 	SND_SOC_DAPM_PGA("DMIC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2002 	SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
2003 		set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
2004 	SND_SOC_DAPM_SUPPLY("DMIC1 Power", RT5645_DMIC_CTRL1,
2005 		RT5645_DMIC_1_EN_SFT, 0, NULL, 0),
2006 	SND_SOC_DAPM_SUPPLY("DMIC2 Power", RT5645_DMIC_CTRL1,
2007 		RT5645_DMIC_2_EN_SFT, 0, NULL, 0),
2008 	/* Boost */
2009 	SND_SOC_DAPM_PGA("BST1", RT5645_PWR_ANLG2,
2010 		RT5645_PWR_BST1_BIT, 0, NULL, 0),
2011 	SND_SOC_DAPM_PGA_E("BST2", RT5645_PWR_ANLG2,
2012 		RT5645_PWR_BST2_BIT, 0, NULL, 0, rt5645_bst2_event,
2013 		SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
2014 	/* Input Volume */
2015 	SND_SOC_DAPM_PGA("INL VOL", RT5645_PWR_VOL,
2016 		RT5645_PWR_IN_L_BIT, 0, NULL, 0),
2017 	SND_SOC_DAPM_PGA("INR VOL", RT5645_PWR_VOL,
2018 		RT5645_PWR_IN_R_BIT, 0, NULL, 0),
2019 	/* REC Mixer */
2020 	SND_SOC_DAPM_MIXER("RECMIXL", RT5645_PWR_MIXER, RT5645_PWR_RM_L_BIT,
2021 			0, rt5645_rec_l_mix, ARRAY_SIZE(rt5645_rec_l_mix)),
2022 	SND_SOC_DAPM_MIXER("RECMIXR", RT5645_PWR_MIXER, RT5645_PWR_RM_R_BIT,
2023 			0, rt5645_rec_r_mix, ARRAY_SIZE(rt5645_rec_r_mix)),
2024 	/* ADCs */
2025 	SND_SOC_DAPM_ADC("ADC L", NULL, SND_SOC_NOPM, 0, 0),
2026 	SND_SOC_DAPM_ADC("ADC R", NULL, SND_SOC_NOPM, 0, 0),
2027 
2028 	SND_SOC_DAPM_SUPPLY("ADC L power", RT5645_PWR_DIG1,
2029 		RT5645_PWR_ADC_L_BIT, 0, NULL, 0),
2030 	SND_SOC_DAPM_SUPPLY("ADC R power", RT5645_PWR_DIG1,
2031 		RT5645_PWR_ADC_R_BIT, 0, NULL, 0),
2032 
2033 	/* ADC Mux */
2034 	SND_SOC_DAPM_MUX("Stereo1 DMIC Mux", SND_SOC_NOPM, 0, 0,
2035 		&rt5645_sto1_dmic_mux),
2036 	SND_SOC_DAPM_MUX("Stereo1 ADC L2 Mux", SND_SOC_NOPM, 0, 0,
2037 		&rt5645_sto_adc2_mux),
2038 	SND_SOC_DAPM_MUX("Stereo1 ADC R2 Mux", SND_SOC_NOPM, 0, 0,
2039 		&rt5645_sto_adc2_mux),
2040 	SND_SOC_DAPM_MUX("Stereo1 ADC L1 Mux", SND_SOC_NOPM, 0, 0,
2041 		&rt5645_sto_adc1_mux),
2042 	SND_SOC_DAPM_MUX("Stereo1 ADC R1 Mux", SND_SOC_NOPM, 0, 0,
2043 		&rt5645_sto_adc1_mux),
2044 	SND_SOC_DAPM_MUX("Mono DMIC L Mux", SND_SOC_NOPM, 0, 0,
2045 		&rt5645_mono_dmic_l_mux),
2046 	SND_SOC_DAPM_MUX("Mono DMIC R Mux", SND_SOC_NOPM, 0, 0,
2047 		&rt5645_mono_dmic_r_mux),
2048 	SND_SOC_DAPM_MUX("Mono ADC L2 Mux", SND_SOC_NOPM, 0, 0,
2049 		&rt5645_mono_adc_l2_mux),
2050 	SND_SOC_DAPM_MUX("Mono ADC L1 Mux", SND_SOC_NOPM, 0, 0,
2051 		&rt5645_mono_adc_l1_mux),
2052 	SND_SOC_DAPM_MUX("Mono ADC R1 Mux", SND_SOC_NOPM, 0, 0,
2053 		&rt5645_mono_adc_r1_mux),
2054 	SND_SOC_DAPM_MUX("Mono ADC R2 Mux", SND_SOC_NOPM, 0, 0,
2055 		&rt5645_mono_adc_r2_mux),
2056 	/* ADC Mixer */
2057 
2058 	SND_SOC_DAPM_SUPPLY_S("adc stereo1 filter", 1, RT5645_PWR_DIG2,
2059 		RT5645_PWR_ADC_S1F_BIT, 0, NULL, 0),
2060 	SND_SOC_DAPM_MIXER_E("Sto1 ADC MIXL", SND_SOC_NOPM, 0, 0,
2061 		rt5645_sto1_adc_l_mix, ARRAY_SIZE(rt5645_sto1_adc_l_mix),
2062 		NULL, 0),
2063 	SND_SOC_DAPM_MIXER_E("Sto1 ADC MIXR", SND_SOC_NOPM, 0, 0,
2064 		rt5645_sto1_adc_r_mix, ARRAY_SIZE(rt5645_sto1_adc_r_mix),
2065 		NULL, 0),
2066 	SND_SOC_DAPM_SUPPLY_S("adc mono left filter", 1, RT5645_PWR_DIG2,
2067 		RT5645_PWR_ADC_MF_L_BIT, 0, NULL, 0),
2068 	SND_SOC_DAPM_MIXER_E("Mono ADC MIXL", SND_SOC_NOPM, 0, 0,
2069 		rt5645_mono_adc_l_mix, ARRAY_SIZE(rt5645_mono_adc_l_mix),
2070 		NULL, 0),
2071 	SND_SOC_DAPM_SUPPLY_S("adc mono right filter", 1, RT5645_PWR_DIG2,
2072 		RT5645_PWR_ADC_MF_R_BIT, 0, NULL, 0),
2073 	SND_SOC_DAPM_MIXER_E("Mono ADC MIXR", SND_SOC_NOPM, 0, 0,
2074 		rt5645_mono_adc_r_mix, ARRAY_SIZE(rt5645_mono_adc_r_mix),
2075 		NULL, 0),
2076 
2077 	/* ADC PGA */
2078 	SND_SOC_DAPM_PGA("Stereo1 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
2079 	SND_SOC_DAPM_PGA("Stereo1 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
2080 	SND_SOC_DAPM_PGA("Sto2 ADC LR MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2081 	SND_SOC_DAPM_PGA("VAD_ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2082 	SND_SOC_DAPM_PGA("IF_ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2083 	SND_SOC_DAPM_PGA("IF_ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2084 	SND_SOC_DAPM_PGA("IF1_ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2085 	SND_SOC_DAPM_PGA("IF1_ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2086 	SND_SOC_DAPM_PGA("IF1_ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2087 	SND_SOC_DAPM_PGA("IF1_ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2088 
2089 	/* IF1 2 Mux */
2090 	SND_SOC_DAPM_MUX("IF2 ADC Mux", SND_SOC_NOPM,
2091 		0, 0, &rt5645_if2_adc_in_mux),
2092 
2093 	/* Digital Interface */
2094 	SND_SOC_DAPM_SUPPLY("I2S1", RT5645_PWR_DIG1,
2095 		RT5645_PWR_I2S1_BIT, 0, NULL, 0),
2096 	SND_SOC_DAPM_PGA("IF1 DAC0", SND_SOC_NOPM, 0, 0, NULL, 0),
2097 	SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2098 	SND_SOC_DAPM_PGA("IF1 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2099 	SND_SOC_DAPM_PGA("IF1 DAC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2100 	SND_SOC_DAPM_PGA("IF1 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2101 	SND_SOC_DAPM_PGA("IF1 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2102 	SND_SOC_DAPM_PGA("IF1 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2103 	SND_SOC_DAPM_SUPPLY("I2S2", RT5645_PWR_DIG1,
2104 		RT5645_PWR_I2S2_BIT, 0, NULL, 0),
2105 	SND_SOC_DAPM_PGA("IF2 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
2106 	SND_SOC_DAPM_PGA("IF2 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2107 	SND_SOC_DAPM_PGA("IF2 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2108 	SND_SOC_DAPM_PGA("IF2 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2109 
2110 	/* Digital Interface Select */
2111 	SND_SOC_DAPM_MUX("VAD ADC Mux", SND_SOC_NOPM,
2112 		0, 0, &rt5645_vad_adc_mux),
2113 
2114 	/* Audio Interface */
2115 	SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
2116 	SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
2117 	SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
2118 	SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
2119 
2120 	/* Output Side */
2121 	/* DAC mixer before sound effect  */
2122 	SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0,
2123 		rt5645_dac_l_mix, ARRAY_SIZE(rt5645_dac_l_mix)),
2124 	SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0,
2125 		rt5645_dac_r_mix, ARRAY_SIZE(rt5645_dac_r_mix)),
2126 
2127 	/* DAC2 channel Mux */
2128 	SND_SOC_DAPM_MUX("DAC L2 Mux", SND_SOC_NOPM, 0, 0, &rt5645_dac_l2_mux),
2129 	SND_SOC_DAPM_MUX("DAC R2 Mux", SND_SOC_NOPM, 0, 0, &rt5645_dac_r2_mux),
2130 	SND_SOC_DAPM_PGA("DAC L2 Volume", RT5645_PWR_DIG1,
2131 		RT5645_PWR_DAC_L2_BIT, 0, NULL, 0),
2132 	SND_SOC_DAPM_PGA("DAC R2 Volume", RT5645_PWR_DIG1,
2133 		RT5645_PWR_DAC_R2_BIT, 0, NULL, 0),
2134 
2135 	SND_SOC_DAPM_MUX("DAC1 L Mux", SND_SOC_NOPM, 0, 0, &rt5645_dac1l_mux),
2136 	SND_SOC_DAPM_MUX("DAC1 R Mux", SND_SOC_NOPM, 0, 0, &rt5645_dac1r_mux),
2137 
2138 	/* DAC Mixer */
2139 	SND_SOC_DAPM_SUPPLY_S("dac stereo1 filter", 1, RT5645_PWR_DIG2,
2140 		RT5645_PWR_DAC_S1F_BIT, 0, NULL, 0),
2141 	SND_SOC_DAPM_SUPPLY_S("dac mono left filter", 1, RT5645_PWR_DIG2,
2142 		RT5645_PWR_DAC_MF_L_BIT, 0, NULL, 0),
2143 	SND_SOC_DAPM_SUPPLY_S("dac mono right filter", 1, RT5645_PWR_DIG2,
2144 		RT5645_PWR_DAC_MF_R_BIT, 0, NULL, 0),
2145 	SND_SOC_DAPM_MIXER("Stereo DAC MIXL", SND_SOC_NOPM, 0, 0,
2146 		rt5645_sto_dac_l_mix, ARRAY_SIZE(rt5645_sto_dac_l_mix)),
2147 	SND_SOC_DAPM_MIXER("Stereo DAC MIXR", SND_SOC_NOPM, 0, 0,
2148 		rt5645_sto_dac_r_mix, ARRAY_SIZE(rt5645_sto_dac_r_mix)),
2149 	SND_SOC_DAPM_MIXER("Mono DAC MIXL", SND_SOC_NOPM, 0, 0,
2150 		rt5645_mono_dac_l_mix, ARRAY_SIZE(rt5645_mono_dac_l_mix)),
2151 	SND_SOC_DAPM_MIXER("Mono DAC MIXR", SND_SOC_NOPM, 0, 0,
2152 		rt5645_mono_dac_r_mix, ARRAY_SIZE(rt5645_mono_dac_r_mix)),
2153 	SND_SOC_DAPM_MIXER("DAC MIXL", SND_SOC_NOPM, 0, 0,
2154 		rt5645_dig_l_mix, ARRAY_SIZE(rt5645_dig_l_mix)),
2155 	SND_SOC_DAPM_MIXER("DAC MIXR", SND_SOC_NOPM, 0, 0,
2156 		rt5645_dig_r_mix, ARRAY_SIZE(rt5645_dig_r_mix)),
2157 
2158 	/* DACs */
2159 	SND_SOC_DAPM_DAC("DAC L1", NULL, RT5645_PWR_DIG1, RT5645_PWR_DAC_L1_BIT,
2160 		0),
2161 	SND_SOC_DAPM_DAC("DAC L2", NULL, RT5645_PWR_DIG1, RT5645_PWR_DAC_L2_BIT,
2162 		0),
2163 	SND_SOC_DAPM_DAC("DAC R1", NULL, RT5645_PWR_DIG1, RT5645_PWR_DAC_R1_BIT,
2164 		0),
2165 	SND_SOC_DAPM_DAC("DAC R2", NULL, RT5645_PWR_DIG1, RT5645_PWR_DAC_R2_BIT,
2166 		0),
2167 	/* OUT Mixer */
2168 	SND_SOC_DAPM_MIXER("SPK MIXL", RT5645_PWR_MIXER, RT5645_PWR_SM_L_BIT,
2169 		0, rt5645_spk_l_mix, ARRAY_SIZE(rt5645_spk_l_mix)),
2170 	SND_SOC_DAPM_MIXER("SPK MIXR", RT5645_PWR_MIXER, RT5645_PWR_SM_R_BIT,
2171 		0, rt5645_spk_r_mix, ARRAY_SIZE(rt5645_spk_r_mix)),
2172 	SND_SOC_DAPM_MIXER("OUT MIXL", RT5645_PWR_MIXER, RT5645_PWR_OM_L_BIT,
2173 		0, rt5645_out_l_mix, ARRAY_SIZE(rt5645_out_l_mix)),
2174 	SND_SOC_DAPM_MIXER("OUT MIXR", RT5645_PWR_MIXER, RT5645_PWR_OM_R_BIT,
2175 		0, rt5645_out_r_mix, ARRAY_SIZE(rt5645_out_r_mix)),
2176 	/* Ouput Volume */
2177 	SND_SOC_DAPM_SWITCH("SPKVOL L", RT5645_PWR_VOL, RT5645_PWR_SV_L_BIT, 0,
2178 		&spk_l_vol_control),
2179 	SND_SOC_DAPM_SWITCH("SPKVOL R", RT5645_PWR_VOL, RT5645_PWR_SV_R_BIT, 0,
2180 		&spk_r_vol_control),
2181 	SND_SOC_DAPM_MIXER("HPOVOL MIXL", RT5645_PWR_VOL, RT5645_PWR_HV_L_BIT,
2182 		0, rt5645_hpvoll_mix, ARRAY_SIZE(rt5645_hpvoll_mix)),
2183 	SND_SOC_DAPM_MIXER("HPOVOL MIXR", RT5645_PWR_VOL, RT5645_PWR_HV_R_BIT,
2184 		0, rt5645_hpvolr_mix, ARRAY_SIZE(rt5645_hpvolr_mix)),
2185 	SND_SOC_DAPM_SUPPLY("HPOVOL MIXL Power", RT5645_PWR_MIXER,
2186 		RT5645_PWR_HM_L_BIT, 0, NULL, 0),
2187 	SND_SOC_DAPM_SUPPLY("HPOVOL MIXR Power", RT5645_PWR_MIXER,
2188 		RT5645_PWR_HM_R_BIT, 0, NULL, 0),
2189 	SND_SOC_DAPM_PGA("DAC 1", SND_SOC_NOPM, 0, 0, NULL, 0),
2190 	SND_SOC_DAPM_PGA("DAC 2", SND_SOC_NOPM, 0, 0, NULL, 0),
2191 	SND_SOC_DAPM_PGA("HPOVOL", SND_SOC_NOPM, 0, 0, NULL, 0),
2192 	SND_SOC_DAPM_SWITCH("HPOVOL L", SND_SOC_NOPM, 0, 0, &hp_l_vol_control),
2193 	SND_SOC_DAPM_SWITCH("HPOVOL R", SND_SOC_NOPM, 0, 0, &hp_r_vol_control),
2194 
2195 	/* HPO/LOUT/Mono Mixer */
2196 	SND_SOC_DAPM_MIXER("SPOL MIX", SND_SOC_NOPM, 0, 0, rt5645_spo_l_mix,
2197 		ARRAY_SIZE(rt5645_spo_l_mix)),
2198 	SND_SOC_DAPM_MIXER("SPOR MIX", SND_SOC_NOPM, 0, 0, rt5645_spo_r_mix,
2199 		ARRAY_SIZE(rt5645_spo_r_mix)),
2200 	SND_SOC_DAPM_MIXER("HPO MIX", SND_SOC_NOPM, 0, 0, rt5645_hpo_mix,
2201 		ARRAY_SIZE(rt5645_hpo_mix)),
2202 	SND_SOC_DAPM_MIXER("LOUT MIX", SND_SOC_NOPM, 0, 0, rt5645_lout_mix,
2203 		ARRAY_SIZE(rt5645_lout_mix)),
2204 
2205 	SND_SOC_DAPM_PGA_S("HP amp", 1, SND_SOC_NOPM, 0, 0, rt5645_hp_event,
2206 		SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
2207 	SND_SOC_DAPM_PGA_S("LOUT amp", 1, SND_SOC_NOPM, 0, 0, rt5645_lout_event,
2208 		SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
2209 	SND_SOC_DAPM_PGA_S("SPK amp", 2, SND_SOC_NOPM, 0, 0, rt5645_spk_event,
2210 		SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
2211 
2212 	/* PDM */
2213 	SND_SOC_DAPM_SUPPLY("PDM1 Power", RT5645_PWR_DIG2, RT5645_PWR_PDM1_BIT,
2214 		0, NULL, 0),
2215 	SND_SOC_DAPM_MUX("PDM1 L Mux", SND_SOC_NOPM, 0, 0, &rt5645_pdm1_l_mux),
2216 	SND_SOC_DAPM_MUX("PDM1 R Mux", SND_SOC_NOPM, 0, 0, &rt5645_pdm1_r_mux),
2217 
2218 	SND_SOC_DAPM_SWITCH("PDM1 L", SND_SOC_NOPM, 0, 0, &pdm1_l_vol_control),
2219 	SND_SOC_DAPM_SWITCH("PDM1 R", SND_SOC_NOPM, 0, 0, &pdm1_r_vol_control),
2220 
2221 	/* Output Lines */
2222 	SND_SOC_DAPM_OUTPUT("HPOL"),
2223 	SND_SOC_DAPM_OUTPUT("HPOR"),
2224 	SND_SOC_DAPM_OUTPUT("LOUTL"),
2225 	SND_SOC_DAPM_OUTPUT("LOUTR"),
2226 	SND_SOC_DAPM_OUTPUT("PDM1L"),
2227 	SND_SOC_DAPM_OUTPUT("PDM1R"),
2228 	SND_SOC_DAPM_OUTPUT("SPOL"),
2229 	SND_SOC_DAPM_OUTPUT("SPOR"),
2230 	SND_SOC_DAPM_POST("DAPM_POST", rt5650_hp_event),
2231 };
2232 
2233 static const struct snd_soc_dapm_widget rt5645_specific_dapm_widgets[] = {
2234 	SND_SOC_DAPM_MUX("RT5645 IF1 DAC1 L Mux", SND_SOC_NOPM, 0, 0,
2235 		&rt5645_if1_dac0_tdm_sel_mux),
2236 	SND_SOC_DAPM_MUX("RT5645 IF1 DAC1 R Mux", SND_SOC_NOPM, 0, 0,
2237 		&rt5645_if1_dac1_tdm_sel_mux),
2238 	SND_SOC_DAPM_MUX("RT5645 IF1 DAC2 L Mux", SND_SOC_NOPM, 0, 0,
2239 		&rt5645_if1_dac2_tdm_sel_mux),
2240 	SND_SOC_DAPM_MUX("RT5645 IF1 DAC2 R Mux", SND_SOC_NOPM, 0, 0,
2241 		&rt5645_if1_dac3_tdm_sel_mux),
2242 	SND_SOC_DAPM_MUX("RT5645 IF1 ADC Mux", SND_SOC_NOPM,
2243 		0, 0, &rt5645_if1_adc_in_mux),
2244 	SND_SOC_DAPM_MUX("RT5645 IF1 ADC1 Swap Mux", SND_SOC_NOPM,
2245 		0, 0, &rt5645_if1_adc1_in_mux),
2246 	SND_SOC_DAPM_MUX("RT5645 IF1 ADC2 Swap Mux", SND_SOC_NOPM,
2247 		0, 0, &rt5645_if1_adc2_in_mux),
2248 	SND_SOC_DAPM_MUX("RT5645 IF1 ADC3 Swap Mux", SND_SOC_NOPM,
2249 		0, 0, &rt5645_if1_adc3_in_mux),
2250 };
2251 
2252 static const struct snd_soc_dapm_widget rt5650_specific_dapm_widgets[] = {
2253 	SND_SOC_DAPM_MUX("A DAC1 L Mux", SND_SOC_NOPM,
2254 		0, 0, &rt5650_a_dac1_l_mux),
2255 	SND_SOC_DAPM_MUX("A DAC1 R Mux", SND_SOC_NOPM,
2256 		0, 0, &rt5650_a_dac1_r_mux),
2257 	SND_SOC_DAPM_MUX("A DAC2 L Mux", SND_SOC_NOPM,
2258 		0, 0, &rt5650_a_dac2_l_mux),
2259 	SND_SOC_DAPM_MUX("A DAC2 R Mux", SND_SOC_NOPM,
2260 		0, 0, &rt5650_a_dac2_r_mux),
2261 
2262 	SND_SOC_DAPM_MUX("RT5650 IF1 ADC1 Swap Mux", SND_SOC_NOPM,
2263 		0, 0, &rt5650_if1_adc1_in_mux),
2264 	SND_SOC_DAPM_MUX("RT5650 IF1 ADC2 Swap Mux", SND_SOC_NOPM,
2265 		0, 0, &rt5650_if1_adc2_in_mux),
2266 	SND_SOC_DAPM_MUX("RT5650 IF1 ADC3 Swap Mux", SND_SOC_NOPM,
2267 		0, 0, &rt5650_if1_adc3_in_mux),
2268 	SND_SOC_DAPM_MUX("RT5650 IF1 ADC Mux", SND_SOC_NOPM,
2269 		0, 0, &rt5650_if1_adc_in_mux),
2270 
2271 	SND_SOC_DAPM_MUX("RT5650 IF1 DAC1 L Mux", SND_SOC_NOPM, 0, 0,
2272 		&rt5650_if1_dac0_tdm_sel_mux),
2273 	SND_SOC_DAPM_MUX("RT5650 IF1 DAC1 R Mux", SND_SOC_NOPM, 0, 0,
2274 		&rt5650_if1_dac1_tdm_sel_mux),
2275 	SND_SOC_DAPM_MUX("RT5650 IF1 DAC2 L Mux", SND_SOC_NOPM, 0, 0,
2276 		&rt5650_if1_dac2_tdm_sel_mux),
2277 	SND_SOC_DAPM_MUX("RT5650 IF1 DAC2 R Mux", SND_SOC_NOPM, 0, 0,
2278 		&rt5650_if1_dac3_tdm_sel_mux),
2279 };
2280 
2281 static const struct snd_soc_dapm_route rt5645_dapm_routes[] = {
2282 	{ "adc stereo1 filter", NULL, "ADC STO1 ASRC", is_using_asrc },
2283 	{ "adc mono left filter", NULL, "ADC MONO L ASRC", is_using_asrc },
2284 	{ "adc mono right filter", NULL, "ADC MONO R ASRC", is_using_asrc },
2285 	{ "dac mono left filter", NULL, "DAC MONO L ASRC", is_using_asrc },
2286 	{ "dac mono right filter", NULL, "DAC MONO R ASRC", is_using_asrc },
2287 	{ "dac stereo1 filter", NULL, "DAC STO ASRC", is_using_asrc },
2288 
2289 	{ "I2S1", NULL, "I2S1 ASRC" },
2290 	{ "I2S2", NULL, "I2S2 ASRC" },
2291 
2292 	{ "IN1P", NULL, "LDO2" },
2293 	{ "IN2P", NULL, "LDO2" },
2294 
2295 	{ "DMIC1", NULL, "DMIC L1" },
2296 	{ "DMIC1", NULL, "DMIC R1" },
2297 	{ "DMIC2", NULL, "DMIC L2" },
2298 	{ "DMIC2", NULL, "DMIC R2" },
2299 
2300 	{ "BST1", NULL, "IN1P" },
2301 	{ "BST1", NULL, "IN1N" },
2302 	{ "BST1", NULL, "JD Power" },
2303 	{ "BST1", NULL, "Mic Det Power" },
2304 	{ "BST2", NULL, "IN2P" },
2305 	{ "BST2", NULL, "IN2N" },
2306 
2307 	{ "INL VOL", NULL, "IN2P" },
2308 	{ "INR VOL", NULL, "IN2N" },
2309 
2310 	{ "RECMIXL", "HPOL Switch", "HPOL" },
2311 	{ "RECMIXL", "INL Switch", "INL VOL" },
2312 	{ "RECMIXL", "BST2 Switch", "BST2" },
2313 	{ "RECMIXL", "BST1 Switch", "BST1" },
2314 	{ "RECMIXL", "OUT MIXL Switch", "OUT MIXL" },
2315 
2316 	{ "RECMIXR", "HPOR Switch", "HPOR" },
2317 	{ "RECMIXR", "INR Switch", "INR VOL" },
2318 	{ "RECMIXR", "BST2 Switch", "BST2" },
2319 	{ "RECMIXR", "BST1 Switch", "BST1" },
2320 	{ "RECMIXR", "OUT MIXR Switch", "OUT MIXR" },
2321 
2322 	{ "ADC L", NULL, "RECMIXL" },
2323 	{ "ADC L", NULL, "ADC L power" },
2324 	{ "ADC R", NULL, "RECMIXR" },
2325 	{ "ADC R", NULL, "ADC R power" },
2326 
2327 	{"DMIC L1", NULL, "DMIC CLK"},
2328 	{"DMIC L1", NULL, "DMIC1 Power"},
2329 	{"DMIC R1", NULL, "DMIC CLK"},
2330 	{"DMIC R1", NULL, "DMIC1 Power"},
2331 	{"DMIC L2", NULL, "DMIC CLK"},
2332 	{"DMIC L2", NULL, "DMIC2 Power"},
2333 	{"DMIC R2", NULL, "DMIC CLK"},
2334 	{"DMIC R2", NULL, "DMIC2 Power"},
2335 
2336 	{ "Stereo1 DMIC Mux", "DMIC1", "DMIC1" },
2337 	{ "Stereo1 DMIC Mux", "DMIC2", "DMIC2" },
2338 	{ "Stereo1 DMIC Mux", NULL, "DMIC STO1 ASRC" },
2339 
2340 	{ "Mono DMIC L Mux", "DMIC1", "DMIC L1" },
2341 	{ "Mono DMIC L Mux", "DMIC2", "DMIC L2" },
2342 	{ "Mono DMIC L Mux", NULL, "DMIC MONO L ASRC" },
2343 
2344 	{ "Mono DMIC R Mux", "DMIC1", "DMIC R1" },
2345 	{ "Mono DMIC R Mux", "DMIC2", "DMIC R2" },
2346 	{ "Mono DMIC R Mux", NULL, "DMIC MONO R ASRC" },
2347 
2348 	{ "Stereo1 ADC L2 Mux", "DMIC", "Stereo1 DMIC Mux" },
2349 	{ "Stereo1 ADC L2 Mux", "DAC MIX", "DAC MIXL" },
2350 	{ "Stereo1 ADC L1 Mux", "ADC", "ADC L" },
2351 	{ "Stereo1 ADC L1 Mux", "DAC MIX", "DAC MIXL" },
2352 
2353 	{ "Stereo1 ADC R1 Mux", "ADC", "ADC R" },
2354 	{ "Stereo1 ADC R1 Mux", "DAC MIX", "DAC MIXR" },
2355 	{ "Stereo1 ADC R2 Mux", "DMIC", "Stereo1 DMIC Mux" },
2356 	{ "Stereo1 ADC R2 Mux", "DAC MIX", "DAC MIXR" },
2357 
2358 	{ "Mono ADC L2 Mux", "DMIC", "Mono DMIC L Mux" },
2359 	{ "Mono ADC L2 Mux", "Mono DAC MIXL", "Mono DAC MIXL" },
2360 	{ "Mono ADC L1 Mux", "Mono DAC MIXL", "Mono DAC MIXL" },
2361 	{ "Mono ADC L1 Mux", "ADC", "ADC L" },
2362 
2363 	{ "Mono ADC R1 Mux", "Mono DAC MIXR", "Mono DAC MIXR" },
2364 	{ "Mono ADC R1 Mux", "ADC", "ADC R" },
2365 	{ "Mono ADC R2 Mux", "DMIC", "Mono DMIC R Mux" },
2366 	{ "Mono ADC R2 Mux", "Mono DAC MIXR", "Mono DAC MIXR" },
2367 
2368 	{ "Sto1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC L1 Mux" },
2369 	{ "Sto1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC L2 Mux" },
2370 	{ "Sto1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC R1 Mux" },
2371 	{ "Sto1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC R2 Mux" },
2372 
2373 	{ "Stereo1 ADC MIXL", NULL, "Sto1 ADC MIXL" },
2374 	{ "Stereo1 ADC MIXL", NULL, "adc stereo1 filter" },
2375 	{ "adc stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll },
2376 
2377 	{ "Stereo1 ADC MIXR", NULL, "Sto1 ADC MIXR" },
2378 	{ "Stereo1 ADC MIXR", NULL, "adc stereo1 filter" },
2379 	{ "adc stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll },
2380 
2381 	{ "Mono ADC MIXL", "ADC1 Switch", "Mono ADC L1 Mux" },
2382 	{ "Mono ADC MIXL", "ADC2 Switch", "Mono ADC L2 Mux" },
2383 	{ "Mono ADC MIXL", NULL, "adc mono left filter" },
2384 	{ "adc mono left filter", NULL, "PLL1", is_sys_clk_from_pll },
2385 
2386 	{ "Mono ADC MIXR", "ADC1 Switch", "Mono ADC R1 Mux" },
2387 	{ "Mono ADC MIXR", "ADC2 Switch", "Mono ADC R2 Mux" },
2388 	{ "Mono ADC MIXR", NULL, "adc mono right filter" },
2389 	{ "adc mono right filter", NULL, "PLL1", is_sys_clk_from_pll },
2390 
2391 	{ "VAD ADC Mux", "Sto1 ADC L", "Stereo1 ADC MIXL" },
2392 	{ "VAD ADC Mux", "Mono ADC L", "Mono ADC MIXL" },
2393 	{ "VAD ADC Mux", "Mono ADC R", "Mono ADC MIXR" },
2394 
2395 	{ "IF_ADC1", NULL, "Stereo1 ADC MIXL" },
2396 	{ "IF_ADC1", NULL, "Stereo1 ADC MIXR" },
2397 	{ "IF_ADC2", NULL, "Mono ADC MIXL" },
2398 	{ "IF_ADC2", NULL, "Mono ADC MIXR" },
2399 	{ "VAD_ADC", NULL, "VAD ADC Mux" },
2400 
2401 	{ "IF2 ADC Mux", "IF_ADC1", "IF_ADC1" },
2402 	{ "IF2 ADC Mux", "IF_ADC2", "IF_ADC2" },
2403 	{ "IF2 ADC Mux", "VAD_ADC", "VAD_ADC" },
2404 
2405 	{ "IF1 ADC", NULL, "I2S1" },
2406 	{ "IF2 ADC", NULL, "I2S2" },
2407 	{ "IF2 ADC", NULL, "IF2 ADC Mux" },
2408 
2409 	{ "AIF2TX", NULL, "IF2 ADC" },
2410 
2411 	{ "IF1 DAC0", NULL, "AIF1RX" },
2412 	{ "IF1 DAC1", NULL, "AIF1RX" },
2413 	{ "IF1 DAC2", NULL, "AIF1RX" },
2414 	{ "IF1 DAC3", NULL, "AIF1RX" },
2415 	{ "IF2 DAC", NULL, "AIF2RX" },
2416 
2417 	{ "IF1 DAC0", NULL, "I2S1" },
2418 	{ "IF1 DAC1", NULL, "I2S1" },
2419 	{ "IF1 DAC2", NULL, "I2S1" },
2420 	{ "IF1 DAC3", NULL, "I2S1" },
2421 	{ "IF2 DAC", NULL, "I2S2" },
2422 
2423 	{ "IF2 DAC L", NULL, "IF2 DAC" },
2424 	{ "IF2 DAC R", NULL, "IF2 DAC" },
2425 
2426 	{ "DAC1 L Mux", "IF2 DAC", "IF2 DAC L" },
2427 	{ "DAC1 R Mux", "IF2 DAC", "IF2 DAC R" },
2428 
2429 	{ "DAC1 MIXL", "Stereo ADC Switch", "Stereo1 ADC MIXL" },
2430 	{ "DAC1 MIXL", "DAC1 Switch", "DAC1 L Mux" },
2431 	{ "DAC1 MIXL", NULL, "dac stereo1 filter" },
2432 	{ "DAC1 MIXR", "Stereo ADC Switch", "Stereo1 ADC MIXR" },
2433 	{ "DAC1 MIXR", "DAC1 Switch", "DAC1 R Mux" },
2434 	{ "DAC1 MIXR", NULL, "dac stereo1 filter" },
2435 
2436 	{ "DAC L2 Mux", "IF2 DAC", "IF2 DAC L" },
2437 	{ "DAC L2 Mux", "Mono ADC", "Mono ADC MIXL" },
2438 	{ "DAC L2 Mux", "VAD_ADC", "VAD_ADC" },
2439 	{ "DAC L2 Volume", NULL, "DAC L2 Mux" },
2440 	{ "DAC L2 Volume", NULL, "dac mono left filter" },
2441 
2442 	{ "DAC R2 Mux", "IF2 DAC", "IF2 DAC R" },
2443 	{ "DAC R2 Mux", "Mono ADC", "Mono ADC MIXR" },
2444 	{ "DAC R2 Mux", "Haptic", "Haptic Generator" },
2445 	{ "DAC R2 Volume", NULL, "DAC R2 Mux" },
2446 	{ "DAC R2 Volume", NULL, "dac mono right filter" },
2447 
2448 	{ "Stereo DAC MIXL", "DAC L1 Switch", "DAC1 MIXL" },
2449 	{ "Stereo DAC MIXL", "DAC R1 Switch", "DAC1 MIXR" },
2450 	{ "Stereo DAC MIXL", "DAC L2 Switch", "DAC L2 Volume" },
2451 	{ "Stereo DAC MIXL", NULL, "dac stereo1 filter" },
2452 	{ "Stereo DAC MIXR", "DAC R1 Switch", "DAC1 MIXR" },
2453 	{ "Stereo DAC MIXR", "DAC L1 Switch", "DAC1 MIXL" },
2454 	{ "Stereo DAC MIXR", "DAC R2 Switch", "DAC R2 Volume" },
2455 	{ "Stereo DAC MIXR", NULL, "dac stereo1 filter" },
2456 
2457 	{ "Mono DAC MIXL", "DAC L1 Switch", "DAC1 MIXL" },
2458 	{ "Mono DAC MIXL", "DAC L2 Switch", "DAC L2 Volume" },
2459 	{ "Mono DAC MIXL", "DAC R2 Switch", "DAC R2 Volume" },
2460 	{ "Mono DAC MIXL", NULL, "dac mono left filter" },
2461 	{ "Mono DAC MIXR", "DAC R1 Switch", "DAC1 MIXR" },
2462 	{ "Mono DAC MIXR", "DAC R2 Switch", "DAC R2 Volume" },
2463 	{ "Mono DAC MIXR", "DAC L2 Switch", "DAC L2 Volume" },
2464 	{ "Mono DAC MIXR", NULL, "dac mono right filter" },
2465 
2466 	{ "DAC MIXL", "Sto DAC Mix L Switch", "Stereo DAC MIXL" },
2467 	{ "DAC MIXL", "DAC L2 Switch", "DAC L2 Volume" },
2468 	{ "DAC MIXL", "DAC R2 Switch", "DAC R2 Volume" },
2469 	{ "DAC MIXR", "Sto DAC Mix R Switch", "Stereo DAC MIXR" },
2470 	{ "DAC MIXR", "DAC R2 Switch", "DAC R2 Volume" },
2471 	{ "DAC MIXR", "DAC L2 Switch", "DAC L2 Volume" },
2472 
2473 	{ "DAC L1", NULL, "PLL1", is_sys_clk_from_pll },
2474 	{ "DAC R1", NULL, "PLL1", is_sys_clk_from_pll },
2475 	{ "DAC L2", NULL, "PLL1", is_sys_clk_from_pll },
2476 	{ "DAC R2", NULL, "PLL1", is_sys_clk_from_pll },
2477 
2478 	{ "SPK MIXL", "BST1 Switch", "BST1" },
2479 	{ "SPK MIXL", "INL Switch", "INL VOL" },
2480 	{ "SPK MIXL", "DAC L1 Switch", "DAC L1" },
2481 	{ "SPK MIXL", "DAC L2 Switch", "DAC L2" },
2482 	{ "SPK MIXR", "BST2 Switch", "BST2" },
2483 	{ "SPK MIXR", "INR Switch", "INR VOL" },
2484 	{ "SPK MIXR", "DAC R1 Switch", "DAC R1" },
2485 	{ "SPK MIXR", "DAC R2 Switch", "DAC R2" },
2486 
2487 	{ "OUT MIXL", "BST1 Switch", "BST1" },
2488 	{ "OUT MIXL", "INL Switch", "INL VOL" },
2489 	{ "OUT MIXL", "DAC L2 Switch", "DAC L2" },
2490 	{ "OUT MIXL", "DAC L1 Switch", "DAC L1" },
2491 
2492 	{ "OUT MIXR", "BST2 Switch", "BST2" },
2493 	{ "OUT MIXR", "INR Switch", "INR VOL" },
2494 	{ "OUT MIXR", "DAC R2 Switch", "DAC R2" },
2495 	{ "OUT MIXR", "DAC R1 Switch", "DAC R1" },
2496 
2497 	{ "HPOVOL MIXL", "DAC1 Switch", "DAC L1" },
2498 	{ "HPOVOL MIXL", "DAC2 Switch", "DAC L2" },
2499 	{ "HPOVOL MIXL", "INL Switch", "INL VOL" },
2500 	{ "HPOVOL MIXL", "BST1 Switch", "BST1" },
2501 	{ "HPOVOL MIXL", NULL, "HPOVOL MIXL Power" },
2502 	{ "HPOVOL MIXR", "DAC1 Switch", "DAC R1" },
2503 	{ "HPOVOL MIXR", "DAC2 Switch", "DAC R2" },
2504 	{ "HPOVOL MIXR", "INR Switch", "INR VOL" },
2505 	{ "HPOVOL MIXR", "BST2 Switch", "BST2" },
2506 	{ "HPOVOL MIXR", NULL, "HPOVOL MIXR Power" },
2507 
2508 	{ "DAC 2", NULL, "DAC L2" },
2509 	{ "DAC 2", NULL, "DAC R2" },
2510 	{ "DAC 1", NULL, "DAC L1" },
2511 	{ "DAC 1", NULL, "DAC R1" },
2512 	{ "HPOVOL L", "Switch", "HPOVOL MIXL" },
2513 	{ "HPOVOL R", "Switch", "HPOVOL MIXR" },
2514 	{ "HPOVOL", NULL, "HPOVOL L" },
2515 	{ "HPOVOL", NULL, "HPOVOL R" },
2516 	{ "HPO MIX", "DAC1 Switch", "DAC 1" },
2517 	{ "HPO MIX", "HPVOL Switch", "HPOVOL" },
2518 
2519 	{ "SPKVOL L", "Switch", "SPK MIXL" },
2520 	{ "SPKVOL R", "Switch", "SPK MIXR" },
2521 
2522 	{ "SPOL MIX", "DAC L1 Switch", "DAC L1" },
2523 	{ "SPOL MIX", "SPKVOL L Switch", "SPKVOL L" },
2524 	{ "SPOR MIX", "DAC R1 Switch", "DAC R1" },
2525 	{ "SPOR MIX", "SPKVOL R Switch", "SPKVOL R" },
2526 
2527 	{ "LOUT MIX", "DAC L1 Switch", "DAC L1" },
2528 	{ "LOUT MIX", "DAC R1 Switch", "DAC R1" },
2529 	{ "LOUT MIX", "OUTMIX L Switch", "OUT MIXL" },
2530 	{ "LOUT MIX", "OUTMIX R Switch", "OUT MIXR" },
2531 
2532 	{ "PDM1 L Mux", "Stereo DAC", "Stereo DAC MIXL" },
2533 	{ "PDM1 L Mux", "Mono DAC", "Mono DAC MIXL" },
2534 	{ "PDM1 L Mux", NULL, "PDM1 Power" },
2535 	{ "PDM1 R Mux", "Stereo DAC", "Stereo DAC MIXR" },
2536 	{ "PDM1 R Mux", "Mono DAC", "Mono DAC MIXR" },
2537 	{ "PDM1 R Mux", NULL, "PDM1 Power" },
2538 
2539 	{ "HP amp", NULL, "HPO MIX" },
2540 	{ "HP amp", NULL, "JD Power" },
2541 	{ "HP amp", NULL, "Mic Det Power" },
2542 	{ "HP amp", NULL, "LDO2" },
2543 	{ "HPOL", NULL, "HP amp" },
2544 	{ "HPOR", NULL, "HP amp" },
2545 
2546 	{ "LOUT amp", NULL, "LOUT MIX" },
2547 	{ "LOUTL", NULL, "LOUT amp" },
2548 	{ "LOUTR", NULL, "LOUT amp" },
2549 
2550 	{ "PDM1 L", "Switch", "PDM1 L Mux" },
2551 	{ "PDM1 R", "Switch", "PDM1 R Mux" },
2552 
2553 	{ "PDM1L", NULL, "PDM1 L" },
2554 	{ "PDM1R", NULL, "PDM1 R" },
2555 
2556 	{ "SPK amp", NULL, "SPOL MIX" },
2557 	{ "SPK amp", NULL, "SPOR MIX" },
2558 	{ "SPOL", NULL, "SPK amp" },
2559 	{ "SPOR", NULL, "SPK amp" },
2560 };
2561 
2562 static const struct snd_soc_dapm_route rt5650_specific_dapm_routes[] = {
2563 	{ "A DAC1 L Mux", "DAC1",  "DAC1 MIXL"},
2564 	{ "A DAC1 L Mux", "Stereo DAC Mixer", "Stereo DAC MIXL"},
2565 	{ "A DAC1 R Mux", "DAC1",  "DAC1 MIXR"},
2566 	{ "A DAC1 R Mux", "Stereo DAC Mixer", "Stereo DAC MIXR"},
2567 
2568 	{ "A DAC2 L Mux", "Stereo DAC Mixer", "Stereo DAC MIXL"},
2569 	{ "A DAC2 L Mux", "Mono DAC Mixer", "Mono DAC MIXL"},
2570 	{ "A DAC2 R Mux", "Stereo DAC Mixer", "Stereo DAC MIXR"},
2571 	{ "A DAC2 R Mux", "Mono DAC Mixer", "Mono DAC MIXR"},
2572 
2573 	{ "DAC L1", NULL, "A DAC1 L Mux" },
2574 	{ "DAC R1", NULL, "A DAC1 R Mux" },
2575 	{ "DAC L2", NULL, "A DAC2 L Mux" },
2576 	{ "DAC R2", NULL, "A DAC2 R Mux" },
2577 
2578 	{ "RT5650 IF1 ADC1 Swap Mux", "L/R", "IF_ADC1" },
2579 	{ "RT5650 IF1 ADC1 Swap Mux", "R/L", "IF_ADC1" },
2580 	{ "RT5650 IF1 ADC1 Swap Mux", "L/L", "IF_ADC1" },
2581 	{ "RT5650 IF1 ADC1 Swap Mux", "R/R", "IF_ADC1" },
2582 
2583 	{ "RT5650 IF1 ADC2 Swap Mux", "L/R", "IF_ADC2" },
2584 	{ "RT5650 IF1 ADC2 Swap Mux", "R/L", "IF_ADC2" },
2585 	{ "RT5650 IF1 ADC2 Swap Mux", "L/L", "IF_ADC2" },
2586 	{ "RT5650 IF1 ADC2 Swap Mux", "R/R", "IF_ADC2" },
2587 
2588 	{ "RT5650 IF1 ADC3 Swap Mux", "L/R", "VAD_ADC" },
2589 	{ "RT5650 IF1 ADC3 Swap Mux", "R/L", "VAD_ADC" },
2590 	{ "RT5650 IF1 ADC3 Swap Mux", "L/L", "VAD_ADC" },
2591 	{ "RT5650 IF1 ADC3 Swap Mux", "R/R", "VAD_ADC" },
2592 
2593 	{ "IF1 ADC", NULL, "RT5650 IF1 ADC1 Swap Mux" },
2594 	{ "IF1 ADC", NULL, "RT5650 IF1 ADC2 Swap Mux" },
2595 	{ "IF1 ADC", NULL, "RT5650 IF1 ADC3 Swap Mux" },
2596 
2597 	{ "RT5650 IF1 ADC Mux", "IF_ADC1/IF_ADC2/DAC_REF/Null", "IF1 ADC" },
2598 	{ "RT5650 IF1 ADC Mux", "IF_ADC1/IF_ADC2/Null/DAC_REF", "IF1 ADC" },
2599 	{ "RT5650 IF1 ADC Mux", "IF_ADC1/DAC_REF/IF_ADC2/Null", "IF1 ADC" },
2600 	{ "RT5650 IF1 ADC Mux", "IF_ADC1/DAC_REF/Null/IF_ADC2", "IF1 ADC" },
2601 	{ "RT5650 IF1 ADC Mux", "IF_ADC1/Null/DAC_REF/IF_ADC2", "IF1 ADC" },
2602 	{ "RT5650 IF1 ADC Mux", "IF_ADC1/Null/IF_ADC2/DAC_REF", "IF1 ADC" },
2603 
2604 	{ "RT5650 IF1 ADC Mux", "IF_ADC2/IF_ADC1/DAC_REF/Null", "IF1 ADC" },
2605 	{ "RT5650 IF1 ADC Mux", "IF_ADC2/IF_ADC1/Null/DAC_REF", "IF1 ADC" },
2606 	{ "RT5650 IF1 ADC Mux", "IF_ADC2/DAC_REF/IF_ADC1/Null", "IF1 ADC" },
2607 	{ "RT5650 IF1 ADC Mux", "IF_ADC2/DAC_REF/Null/IF_ADC1", "IF1 ADC" },
2608 	{ "RT5650 IF1 ADC Mux", "IF_ADC2/Null/DAC_REF/IF_ADC1", "IF1 ADC" },
2609 	{ "RT5650 IF1 ADC Mux", "IF_ADC2/Null/IF_ADC1/DAC_REF", "IF1 ADC" },
2610 
2611 	{ "RT5650 IF1 ADC Mux", "DAC_REF/IF_ADC1/IF_ADC2/Null", "IF1 ADC" },
2612 	{ "RT5650 IF1 ADC Mux", "DAC_REF/IF_ADC1/Null/IF_ADC2", "IF1 ADC" },
2613 	{ "RT5650 IF1 ADC Mux", "DAC_REF/IF_ADC2/IF_ADC1/Null", "IF1 ADC" },
2614 	{ "RT5650 IF1 ADC Mux", "DAC_REF/IF_ADC2/Null/IF_ADC1", "IF1 ADC" },
2615 	{ "RT5650 IF1 ADC Mux", "DAC_REF/Null/IF_ADC1/IF_ADC2", "IF1 ADC" },
2616 	{ "RT5650 IF1 ADC Mux", "DAC_REF/Null/IF_ADC2/IF_ADC1", "IF1 ADC" },
2617 
2618 	{ "RT5650 IF1 ADC Mux", "Null/IF_ADC1/IF_ADC2/DAC_REF", "IF1 ADC" },
2619 	{ "RT5650 IF1 ADC Mux", "Null/IF_ADC1/DAC_REF/IF_ADC2", "IF1 ADC" },
2620 	{ "RT5650 IF1 ADC Mux", "Null/IF_ADC2/IF_ADC1/DAC_REF", "IF1 ADC" },
2621 	{ "RT5650 IF1 ADC Mux", "Null/IF_ADC2/DAC_REF/IF_ADC1", "IF1 ADC" },
2622 	{ "RT5650 IF1 ADC Mux", "Null/DAC_REF/IF_ADC1/IF_ADC2", "IF1 ADC" },
2623 	{ "RT5650 IF1 ADC Mux", "Null/DAC_REF/IF_ADC2/IF_ADC1", "IF1 ADC" },
2624 	{ "AIF1TX", NULL, "RT5650 IF1 ADC Mux" },
2625 
2626 	{ "RT5650 IF1 DAC1 L Mux", "Slot0", "IF1 DAC0" },
2627 	{ "RT5650 IF1 DAC1 L Mux", "Slot1", "IF1 DAC1" },
2628 	{ "RT5650 IF1 DAC1 L Mux", "Slot2", "IF1 DAC2" },
2629 	{ "RT5650 IF1 DAC1 L Mux", "Slot3", "IF1 DAC3" },
2630 
2631 	{ "RT5650 IF1 DAC1 R Mux", "Slot0", "IF1 DAC0" },
2632 	{ "RT5650 IF1 DAC1 R Mux", "Slot1", "IF1 DAC1" },
2633 	{ "RT5650 IF1 DAC1 R Mux", "Slot2", "IF1 DAC2" },
2634 	{ "RT5650 IF1 DAC1 R Mux", "Slot3", "IF1 DAC3" },
2635 
2636 	{ "RT5650 IF1 DAC2 L Mux", "Slot0", "IF1 DAC0" },
2637 	{ "RT5650 IF1 DAC2 L Mux", "Slot1", "IF1 DAC1" },
2638 	{ "RT5650 IF1 DAC2 L Mux", "Slot2", "IF1 DAC2" },
2639 	{ "RT5650 IF1 DAC2 L Mux", "Slot3", "IF1 DAC3" },
2640 
2641 	{ "RT5650 IF1 DAC2 R Mux", "Slot0", "IF1 DAC0" },
2642 	{ "RT5650 IF1 DAC2 R Mux", "Slot1", "IF1 DAC1" },
2643 	{ "RT5650 IF1 DAC2 R Mux", "Slot2", "IF1 DAC2" },
2644 	{ "RT5650 IF1 DAC2 R Mux", "Slot3", "IF1 DAC3" },
2645 
2646 	{ "DAC1 L Mux", "IF1 DAC", "RT5650 IF1 DAC1 L Mux" },
2647 	{ "DAC1 R Mux", "IF1 DAC", "RT5650 IF1 DAC1 R Mux" },
2648 
2649 	{ "DAC L2 Mux", "IF1 DAC", "RT5650 IF1 DAC2 L Mux" },
2650 	{ "DAC R2 Mux", "IF1 DAC", "RT5650 IF1 DAC2 R Mux" },
2651 };
2652 
2653 static const struct snd_soc_dapm_route rt5645_specific_dapm_routes[] = {
2654 	{ "DAC L1", NULL, "Stereo DAC MIXL" },
2655 	{ "DAC R1", NULL, "Stereo DAC MIXR" },
2656 	{ "DAC L2", NULL, "Mono DAC MIXL" },
2657 	{ "DAC R2", NULL, "Mono DAC MIXR" },
2658 
2659 	{ "RT5645 IF1 ADC1 Swap Mux", "L/R", "IF_ADC1" },
2660 	{ "RT5645 IF1 ADC1 Swap Mux", "R/L", "IF_ADC1" },
2661 	{ "RT5645 IF1 ADC1 Swap Mux", "L/L", "IF_ADC1" },
2662 	{ "RT5645 IF1 ADC1 Swap Mux", "R/R", "IF_ADC1" },
2663 
2664 	{ "RT5645 IF1 ADC2 Swap Mux", "L/R", "IF_ADC2" },
2665 	{ "RT5645 IF1 ADC2 Swap Mux", "R/L", "IF_ADC2" },
2666 	{ "RT5645 IF1 ADC2 Swap Mux", "L/L", "IF_ADC2" },
2667 	{ "RT5645 IF1 ADC2 Swap Mux", "R/R", "IF_ADC2" },
2668 
2669 	{ "RT5645 IF1 ADC3 Swap Mux", "L/R", "VAD_ADC" },
2670 	{ "RT5645 IF1 ADC3 Swap Mux", "R/L", "VAD_ADC" },
2671 	{ "RT5645 IF1 ADC3 Swap Mux", "L/L", "VAD_ADC" },
2672 	{ "RT5645 IF1 ADC3 Swap Mux", "R/R", "VAD_ADC" },
2673 
2674 	{ "IF1 ADC", NULL, "RT5645 IF1 ADC1 Swap Mux" },
2675 	{ "IF1 ADC", NULL, "RT5645 IF1 ADC2 Swap Mux" },
2676 	{ "IF1 ADC", NULL, "RT5645 IF1 ADC3 Swap Mux" },
2677 
2678 	{ "RT5645 IF1 ADC Mux", "IF_ADC1/IF_ADC2/VAD_ADC", "IF1 ADC" },
2679 	{ "RT5645 IF1 ADC Mux", "IF_ADC2/IF_ADC1/VAD_ADC", "IF1 ADC" },
2680 	{ "RT5645 IF1 ADC Mux", "VAD_ADC/IF_ADC1/IF_ADC2", "IF1 ADC" },
2681 	{ "RT5645 IF1 ADC Mux", "VAD_ADC/IF_ADC2/IF_ADC1", "IF1 ADC" },
2682 	{ "AIF1TX", NULL, "RT5645 IF1 ADC Mux" },
2683 
2684 	{ "RT5645 IF1 DAC1 L Mux", "Slot0", "IF1 DAC0" },
2685 	{ "RT5645 IF1 DAC1 L Mux", "Slot1", "IF1 DAC1" },
2686 	{ "RT5645 IF1 DAC1 L Mux", "Slot2", "IF1 DAC2" },
2687 	{ "RT5645 IF1 DAC1 L Mux", "Slot3", "IF1 DAC3" },
2688 
2689 	{ "RT5645 IF1 DAC1 R Mux", "Slot0", "IF1 DAC0" },
2690 	{ "RT5645 IF1 DAC1 R Mux", "Slot1", "IF1 DAC1" },
2691 	{ "RT5645 IF1 DAC1 R Mux", "Slot2", "IF1 DAC2" },
2692 	{ "RT5645 IF1 DAC1 R Mux", "Slot3", "IF1 DAC3" },
2693 
2694 	{ "RT5645 IF1 DAC2 L Mux", "Slot0", "IF1 DAC0" },
2695 	{ "RT5645 IF1 DAC2 L Mux", "Slot1", "IF1 DAC1" },
2696 	{ "RT5645 IF1 DAC2 L Mux", "Slot2", "IF1 DAC2" },
2697 	{ "RT5645 IF1 DAC2 L Mux", "Slot3", "IF1 DAC3" },
2698 
2699 	{ "RT5645 IF1 DAC2 R Mux", "Slot0", "IF1 DAC0" },
2700 	{ "RT5645 IF1 DAC2 R Mux", "Slot1", "IF1 DAC1" },
2701 	{ "RT5645 IF1 DAC2 R Mux", "Slot2", "IF1 DAC2" },
2702 	{ "RT5645 IF1 DAC2 R Mux", "Slot3", "IF1 DAC3" },
2703 
2704 	{ "DAC1 L Mux", "IF1 DAC", "RT5645 IF1 DAC1 L Mux" },
2705 	{ "DAC1 R Mux", "IF1 DAC", "RT5645 IF1 DAC1 R Mux" },
2706 
2707 	{ "DAC L2 Mux", "IF1 DAC", "RT5645 IF1 DAC2 L Mux" },
2708 	{ "DAC R2 Mux", "IF1 DAC", "RT5645 IF1 DAC2 R Mux" },
2709 };
2710 
2711 static const struct snd_soc_dapm_route rt5645_old_dapm_routes[] = {
2712 	{ "SPOL MIX", "DAC R1 Switch", "DAC R1" },
2713 	{ "SPOL MIX", "SPKVOL R Switch", "SPKVOL R" },
2714 };
2715 
2716 static int rt5645_hw_params(struct snd_pcm_substream *substream,
2717 	struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
2718 {
2719 	struct snd_soc_codec *codec = dai->codec;
2720 	struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
2721 	unsigned int val_len = 0, val_clk, mask_clk, dl_sft;
2722 	int pre_div, bclk_ms, frame_size;
2723 
2724 	rt5645->lrck[dai->id] = params_rate(params);
2725 	pre_div = rl6231_get_clk_info(rt5645->sysclk, rt5645->lrck[dai->id]);
2726 	if (pre_div < 0) {
2727 		dev_err(codec->dev, "Unsupported clock setting\n");
2728 		return -EINVAL;
2729 	}
2730 	frame_size = snd_soc_params_to_frame_size(params);
2731 	if (frame_size < 0) {
2732 		dev_err(codec->dev, "Unsupported frame size: %d\n", frame_size);
2733 		return -EINVAL;
2734 	}
2735 
2736 	switch (rt5645->codec_type) {
2737 	case CODEC_TYPE_RT5650:
2738 		dl_sft = 4;
2739 		break;
2740 	default:
2741 		dl_sft = 2;
2742 		break;
2743 	}
2744 
2745 	bclk_ms = frame_size > 32;
2746 	rt5645->bclk[dai->id] = rt5645->lrck[dai->id] * (32 << bclk_ms);
2747 
2748 	dev_dbg(dai->dev, "bclk is %dHz and lrck is %dHz\n",
2749 		rt5645->bclk[dai->id], rt5645->lrck[dai->id]);
2750 	dev_dbg(dai->dev, "bclk_ms is %d and pre_div is %d for iis %d\n",
2751 				bclk_ms, pre_div, dai->id);
2752 
2753 	switch (params_width(params)) {
2754 	case 16:
2755 		break;
2756 	case 20:
2757 		val_len = 0x1;
2758 		break;
2759 	case 24:
2760 		val_len = 0x2;
2761 		break;
2762 	case 8:
2763 		val_len = 0x3;
2764 		break;
2765 	default:
2766 		return -EINVAL;
2767 	}
2768 
2769 	switch (dai->id) {
2770 	case RT5645_AIF1:
2771 		mask_clk = RT5645_I2S_PD1_MASK;
2772 		val_clk = pre_div << RT5645_I2S_PD1_SFT;
2773 		snd_soc_update_bits(codec, RT5645_I2S1_SDP,
2774 			(0x3 << dl_sft), (val_len << dl_sft));
2775 		snd_soc_update_bits(codec, RT5645_ADDA_CLK1, mask_clk, val_clk);
2776 		break;
2777 	case  RT5645_AIF2:
2778 		mask_clk = RT5645_I2S_BCLK_MS2_MASK | RT5645_I2S_PD2_MASK;
2779 		val_clk = bclk_ms << RT5645_I2S_BCLK_MS2_SFT |
2780 			pre_div << RT5645_I2S_PD2_SFT;
2781 		snd_soc_update_bits(codec, RT5645_I2S2_SDP,
2782 			(0x3 << dl_sft), (val_len << dl_sft));
2783 		snd_soc_update_bits(codec, RT5645_ADDA_CLK1, mask_clk, val_clk);
2784 		break;
2785 	default:
2786 		dev_err(codec->dev, "Invalid dai->id: %d\n", dai->id);
2787 		return -EINVAL;
2788 	}
2789 
2790 	return 0;
2791 }
2792 
2793 static int rt5645_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2794 {
2795 	struct snd_soc_codec *codec = dai->codec;
2796 	struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
2797 	unsigned int reg_val = 0, pol_sft;
2798 
2799 	switch (rt5645->codec_type) {
2800 	case CODEC_TYPE_RT5650:
2801 		pol_sft = 8;
2802 		break;
2803 	default:
2804 		pol_sft = 7;
2805 		break;
2806 	}
2807 
2808 	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2809 	case SND_SOC_DAIFMT_CBM_CFM:
2810 		rt5645->master[dai->id] = 1;
2811 		break;
2812 	case SND_SOC_DAIFMT_CBS_CFS:
2813 		reg_val |= RT5645_I2S_MS_S;
2814 		rt5645->master[dai->id] = 0;
2815 		break;
2816 	default:
2817 		return -EINVAL;
2818 	}
2819 
2820 	switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2821 	case SND_SOC_DAIFMT_NB_NF:
2822 		break;
2823 	case SND_SOC_DAIFMT_IB_NF:
2824 		reg_val |= (1 << pol_sft);
2825 		break;
2826 	default:
2827 		return -EINVAL;
2828 	}
2829 
2830 	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2831 	case SND_SOC_DAIFMT_I2S:
2832 		break;
2833 	case SND_SOC_DAIFMT_LEFT_J:
2834 		reg_val |= RT5645_I2S_DF_LEFT;
2835 		break;
2836 	case SND_SOC_DAIFMT_DSP_A:
2837 		reg_val |= RT5645_I2S_DF_PCM_A;
2838 		break;
2839 	case SND_SOC_DAIFMT_DSP_B:
2840 		reg_val |= RT5645_I2S_DF_PCM_B;
2841 		break;
2842 	default:
2843 		return -EINVAL;
2844 	}
2845 	switch (dai->id) {
2846 	case RT5645_AIF1:
2847 		snd_soc_update_bits(codec, RT5645_I2S1_SDP,
2848 			RT5645_I2S_MS_MASK | (1 << pol_sft) |
2849 			RT5645_I2S_DF_MASK, reg_val);
2850 		break;
2851 	case RT5645_AIF2:
2852 		snd_soc_update_bits(codec, RT5645_I2S2_SDP,
2853 			RT5645_I2S_MS_MASK | (1 << pol_sft) |
2854 			RT5645_I2S_DF_MASK, reg_val);
2855 		break;
2856 	default:
2857 		dev_err(codec->dev, "Invalid dai->id: %d\n", dai->id);
2858 		return -EINVAL;
2859 	}
2860 	return 0;
2861 }
2862 
2863 static int rt5645_set_dai_sysclk(struct snd_soc_dai *dai,
2864 		int clk_id, unsigned int freq, int dir)
2865 {
2866 	struct snd_soc_codec *codec = dai->codec;
2867 	struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
2868 	unsigned int reg_val = 0;
2869 
2870 	if (freq == rt5645->sysclk && clk_id == rt5645->sysclk_src)
2871 		return 0;
2872 
2873 	switch (clk_id) {
2874 	case RT5645_SCLK_S_MCLK:
2875 		reg_val |= RT5645_SCLK_SRC_MCLK;
2876 		break;
2877 	case RT5645_SCLK_S_PLL1:
2878 		reg_val |= RT5645_SCLK_SRC_PLL1;
2879 		break;
2880 	case RT5645_SCLK_S_RCCLK:
2881 		reg_val |= RT5645_SCLK_SRC_RCCLK;
2882 		break;
2883 	default:
2884 		dev_err(codec->dev, "Invalid clock id (%d)\n", clk_id);
2885 		return -EINVAL;
2886 	}
2887 	snd_soc_update_bits(codec, RT5645_GLB_CLK,
2888 		RT5645_SCLK_SRC_MASK, reg_val);
2889 	rt5645->sysclk = freq;
2890 	rt5645->sysclk_src = clk_id;
2891 
2892 	dev_dbg(dai->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id);
2893 
2894 	return 0;
2895 }
2896 
2897 static int rt5645_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
2898 			unsigned int freq_in, unsigned int freq_out)
2899 {
2900 	struct snd_soc_codec *codec = dai->codec;
2901 	struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
2902 	struct rl6231_pll_code pll_code;
2903 	int ret;
2904 
2905 	if (source == rt5645->pll_src && freq_in == rt5645->pll_in &&
2906 	    freq_out == rt5645->pll_out)
2907 		return 0;
2908 
2909 	if (!freq_in || !freq_out) {
2910 		dev_dbg(codec->dev, "PLL disabled\n");
2911 
2912 		rt5645->pll_in = 0;
2913 		rt5645->pll_out = 0;
2914 		snd_soc_update_bits(codec, RT5645_GLB_CLK,
2915 			RT5645_SCLK_SRC_MASK, RT5645_SCLK_SRC_MCLK);
2916 		return 0;
2917 	}
2918 
2919 	switch (source) {
2920 	case RT5645_PLL1_S_MCLK:
2921 		snd_soc_update_bits(codec, RT5645_GLB_CLK,
2922 			RT5645_PLL1_SRC_MASK, RT5645_PLL1_SRC_MCLK);
2923 		break;
2924 	case RT5645_PLL1_S_BCLK1:
2925 	case RT5645_PLL1_S_BCLK2:
2926 		switch (dai->id) {
2927 		case RT5645_AIF1:
2928 			snd_soc_update_bits(codec, RT5645_GLB_CLK,
2929 				RT5645_PLL1_SRC_MASK, RT5645_PLL1_SRC_BCLK1);
2930 			break;
2931 		case  RT5645_AIF2:
2932 			snd_soc_update_bits(codec, RT5645_GLB_CLK,
2933 				RT5645_PLL1_SRC_MASK, RT5645_PLL1_SRC_BCLK2);
2934 			break;
2935 		default:
2936 			dev_err(codec->dev, "Invalid dai->id: %d\n", dai->id);
2937 			return -EINVAL;
2938 		}
2939 		break;
2940 	default:
2941 		dev_err(codec->dev, "Unknown PLL source %d\n", source);
2942 		return -EINVAL;
2943 	}
2944 
2945 	ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
2946 	if (ret < 0) {
2947 		dev_err(codec->dev, "Unsupport input clock %d\n", freq_in);
2948 		return ret;
2949 	}
2950 
2951 	dev_dbg(codec->dev, "bypass=%d m=%d n=%d k=%d\n",
2952 		pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
2953 		pll_code.n_code, pll_code.k_code);
2954 
2955 	snd_soc_write(codec, RT5645_PLL_CTRL1,
2956 		pll_code.n_code << RT5645_PLL_N_SFT | pll_code.k_code);
2957 	snd_soc_write(codec, RT5645_PLL_CTRL2,
2958 		(pll_code.m_bp ? 0 : pll_code.m_code) << RT5645_PLL_M_SFT |
2959 		pll_code.m_bp << RT5645_PLL_M_BP_SFT);
2960 
2961 	rt5645->pll_in = freq_in;
2962 	rt5645->pll_out = freq_out;
2963 	rt5645->pll_src = source;
2964 
2965 	return 0;
2966 }
2967 
2968 static int rt5645_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
2969 			unsigned int rx_mask, int slots, int slot_width)
2970 {
2971 	struct snd_soc_codec *codec = dai->codec;
2972 	struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
2973 	unsigned int i_slot_sft, o_slot_sft, i_width_sht, o_width_sht, en_sft;
2974 	unsigned int mask, val = 0;
2975 
2976 	switch (rt5645->codec_type) {
2977 	case CODEC_TYPE_RT5650:
2978 		en_sft = 15;
2979 		i_slot_sft = 10;
2980 		o_slot_sft = 8;
2981 		i_width_sht = 6;
2982 		o_width_sht = 4;
2983 		mask = 0x8ff0;
2984 		break;
2985 	default:
2986 		en_sft = 14;
2987 		i_slot_sft = o_slot_sft = 12;
2988 		i_width_sht = o_width_sht = 10;
2989 		mask = 0x7c00;
2990 		break;
2991 	}
2992 	if (rx_mask || tx_mask) {
2993 		val |= (1 << en_sft);
2994 		if (rt5645->codec_type == CODEC_TYPE_RT5645)
2995 			snd_soc_update_bits(codec, RT5645_BASS_BACK,
2996 				RT5645_G_BB_BST_MASK, RT5645_G_BB_BST_25DB);
2997 	}
2998 
2999 	switch (slots) {
3000 	case 4:
3001 		val |= (1 << i_slot_sft) | (1 << o_slot_sft);
3002 		break;
3003 	case 6:
3004 		val |= (2 << i_slot_sft) | (2 << o_slot_sft);
3005 		break;
3006 	case 8:
3007 		val |= (3 << i_slot_sft) | (3 << o_slot_sft);
3008 		break;
3009 	case 2:
3010 	default:
3011 		break;
3012 	}
3013 
3014 	switch (slot_width) {
3015 	case 20:
3016 		val |= (1 << i_width_sht) | (1 << o_width_sht);
3017 		break;
3018 	case 24:
3019 		val |= (2 << i_width_sht) | (2 << o_width_sht);
3020 		break;
3021 	case 32:
3022 		val |= (3 << i_width_sht) | (3 << o_width_sht);
3023 		break;
3024 	case 16:
3025 	default:
3026 		break;
3027 	}
3028 
3029 	snd_soc_update_bits(codec, RT5645_TDM_CTRL_1, mask, val);
3030 
3031 	return 0;
3032 }
3033 
3034 static int rt5645_set_bias_level(struct snd_soc_codec *codec,
3035 			enum snd_soc_bias_level level)
3036 {
3037 	struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
3038 
3039 	switch (level) {
3040 	case SND_SOC_BIAS_PREPARE:
3041 		if (SND_SOC_BIAS_STANDBY == snd_soc_codec_get_bias_level(codec)) {
3042 			snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
3043 				RT5645_PWR_VREF1 | RT5645_PWR_MB |
3044 				RT5645_PWR_BG | RT5645_PWR_VREF2,
3045 				RT5645_PWR_VREF1 | RT5645_PWR_MB |
3046 				RT5645_PWR_BG | RT5645_PWR_VREF2);
3047 			mdelay(10);
3048 			snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
3049 				RT5645_PWR_FV1 | RT5645_PWR_FV2,
3050 				RT5645_PWR_FV1 | RT5645_PWR_FV2);
3051 			snd_soc_update_bits(codec, RT5645_GEN_CTRL1,
3052 				RT5645_DIG_GATE_CTRL, RT5645_DIG_GATE_CTRL);
3053 		}
3054 		break;
3055 
3056 	case SND_SOC_BIAS_STANDBY:
3057 		snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
3058 			RT5645_PWR_VREF1 | RT5645_PWR_MB |
3059 			RT5645_PWR_BG | RT5645_PWR_VREF2,
3060 			RT5645_PWR_VREF1 | RT5645_PWR_MB |
3061 			RT5645_PWR_BG | RT5645_PWR_VREF2);
3062 		mdelay(10);
3063 		snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
3064 			RT5645_PWR_FV1 | RT5645_PWR_FV2,
3065 			RT5645_PWR_FV1 | RT5645_PWR_FV2);
3066 		if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_OFF) {
3067 			snd_soc_write(codec, RT5645_DEPOP_M2, 0x1140);
3068 			msleep(40);
3069 			if (rt5645->en_button_func)
3070 				queue_delayed_work(system_power_efficient_wq,
3071 					&rt5645->jack_detect_work,
3072 					msecs_to_jiffies(0));
3073 		}
3074 		break;
3075 
3076 	case SND_SOC_BIAS_OFF:
3077 		snd_soc_write(codec, RT5645_DEPOP_M2, 0x1100);
3078 		if (!rt5645->en_button_func)
3079 			snd_soc_update_bits(codec, RT5645_GEN_CTRL1,
3080 					RT5645_DIG_GATE_CTRL, 0);
3081 		snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
3082 				RT5645_PWR_VREF1 | RT5645_PWR_MB |
3083 				RT5645_PWR_BG | RT5645_PWR_VREF2 |
3084 				RT5645_PWR_FV1 | RT5645_PWR_FV2, 0x0);
3085 		break;
3086 
3087 	default:
3088 		break;
3089 	}
3090 
3091 	return 0;
3092 }
3093 
3094 static void rt5645_enable_push_button_irq(struct snd_soc_codec *codec,
3095 	bool enable)
3096 {
3097 	struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
3098 
3099 	if (enable) {
3100 		snd_soc_dapm_force_enable_pin(dapm, "ADC L power");
3101 		snd_soc_dapm_force_enable_pin(dapm, "ADC R power");
3102 		snd_soc_dapm_sync(dapm);
3103 
3104 		snd_soc_update_bits(codec, RT5650_4BTN_IL_CMD1, 0x3, 0x3);
3105 		snd_soc_update_bits(codec,
3106 					RT5645_INT_IRQ_ST, 0x8, 0x8);
3107 		snd_soc_update_bits(codec,
3108 					RT5650_4BTN_IL_CMD2, 0x8000, 0x8000);
3109 		snd_soc_read(codec, RT5650_4BTN_IL_CMD1);
3110 		pr_debug("%s read %x = %x\n", __func__, RT5650_4BTN_IL_CMD1,
3111 			snd_soc_read(codec, RT5650_4BTN_IL_CMD1));
3112 	} else {
3113 		snd_soc_update_bits(codec, RT5650_4BTN_IL_CMD2, 0x8000, 0x0);
3114 		snd_soc_update_bits(codec, RT5645_INT_IRQ_ST, 0x8, 0x0);
3115 
3116 		snd_soc_dapm_disable_pin(dapm, "ADC L power");
3117 		snd_soc_dapm_disable_pin(dapm, "ADC R power");
3118 		snd_soc_dapm_sync(dapm);
3119 	}
3120 }
3121 
3122 static int rt5645_jack_detect(struct snd_soc_codec *codec, int jack_insert)
3123 {
3124 	struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
3125 	struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
3126 	unsigned int val;
3127 
3128 	if (jack_insert) {
3129 		regmap_write(rt5645->regmap, RT5645_CHARGE_PUMP, 0x0e06);
3130 
3131 		/* for jack type detect */
3132 		snd_soc_dapm_force_enable_pin(dapm, "LDO2");
3133 		snd_soc_dapm_force_enable_pin(dapm, "Mic Det Power");
3134 		snd_soc_dapm_sync(dapm);
3135 		if (!dapm->card->instantiated) {
3136 			/* Power up necessary bits for JD if dapm is
3137 			   not ready yet */
3138 			regmap_update_bits(rt5645->regmap, RT5645_PWR_ANLG1,
3139 				RT5645_PWR_MB | RT5645_PWR_VREF2,
3140 				RT5645_PWR_MB | RT5645_PWR_VREF2);
3141 			regmap_update_bits(rt5645->regmap, RT5645_PWR_MIXER,
3142 				RT5645_PWR_LDO2, RT5645_PWR_LDO2);
3143 			regmap_update_bits(rt5645->regmap, RT5645_PWR_VOL,
3144 				RT5645_PWR_MIC_DET, RT5645_PWR_MIC_DET);
3145 		}
3146 
3147 		regmap_write(rt5645->regmap, RT5645_JD_CTRL3, 0x00f0);
3148 		regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL2,
3149 			RT5645_CBJ_MN_JD, RT5645_CBJ_MN_JD);
3150 		regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL1,
3151 			RT5645_CBJ_BST1_EN, RT5645_CBJ_BST1_EN);
3152 		msleep(100);
3153 		regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL2,
3154 			RT5645_CBJ_MN_JD, 0);
3155 
3156 		msleep(600);
3157 		regmap_read(rt5645->regmap, RT5645_IN1_CTRL3, &val);
3158 		val &= 0x7;
3159 		dev_dbg(codec->dev, "val = %d\n", val);
3160 
3161 		if (val == 1 || val == 2) {
3162 			rt5645->jack_type = SND_JACK_HEADSET;
3163 			if (rt5645->en_button_func) {
3164 				rt5645_enable_push_button_irq(codec, true);
3165 			}
3166 		} else {
3167 			snd_soc_dapm_disable_pin(dapm, "Mic Det Power");
3168 			snd_soc_dapm_sync(dapm);
3169 			rt5645->jack_type = SND_JACK_HEADPHONE;
3170 		}
3171 		if (rt5645->pdata.level_trigger_irq)
3172 			regmap_update_bits(rt5645->regmap, RT5645_IRQ_CTRL2,
3173 				RT5645_JD_1_1_MASK, RT5645_JD_1_1_NOR);
3174 	} else { /* jack out */
3175 		rt5645->jack_type = 0;
3176 
3177 		regmap_update_bits(rt5645->regmap, RT5645_HP_VOL,
3178 			RT5645_L_MUTE | RT5645_R_MUTE,
3179 			RT5645_L_MUTE | RT5645_R_MUTE);
3180 		regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL2,
3181 			RT5645_CBJ_MN_JD, RT5645_CBJ_MN_JD);
3182 		regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL1,
3183 			RT5645_CBJ_BST1_EN, 0);
3184 
3185 		if (rt5645->en_button_func)
3186 			rt5645_enable_push_button_irq(codec, false);
3187 
3188 		if (rt5645->pdata.jd_mode == 0)
3189 			snd_soc_dapm_disable_pin(dapm, "LDO2");
3190 		snd_soc_dapm_disable_pin(dapm, "Mic Det Power");
3191 		snd_soc_dapm_sync(dapm);
3192 		if (rt5645->pdata.level_trigger_irq)
3193 			regmap_update_bits(rt5645->regmap, RT5645_IRQ_CTRL2,
3194 				RT5645_JD_1_1_MASK, RT5645_JD_1_1_INV);
3195 	}
3196 
3197 	return rt5645->jack_type;
3198 }
3199 
3200 static int rt5645_button_detect(struct snd_soc_codec *codec)
3201 {
3202 	int btn_type, val;
3203 
3204 	val = snd_soc_read(codec, RT5650_4BTN_IL_CMD1);
3205 	pr_debug("val=0x%x\n", val);
3206 	btn_type = val & 0xfff0;
3207 	snd_soc_write(codec, RT5650_4BTN_IL_CMD1, val);
3208 
3209 	return btn_type;
3210 }
3211 
3212 static irqreturn_t rt5645_irq(int irq, void *data);
3213 
3214 int rt5645_set_jack_detect(struct snd_soc_codec *codec,
3215 	struct snd_soc_jack *hp_jack, struct snd_soc_jack *mic_jack,
3216 	struct snd_soc_jack *btn_jack)
3217 {
3218 	struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
3219 
3220 	rt5645->hp_jack = hp_jack;
3221 	rt5645->mic_jack = mic_jack;
3222 	rt5645->btn_jack = btn_jack;
3223 	if (rt5645->btn_jack && rt5645->codec_type == CODEC_TYPE_RT5650) {
3224 		rt5645->en_button_func = true;
3225 		regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
3226 				RT5645_GP1_PIN_IRQ, RT5645_GP1_PIN_IRQ);
3227 		regmap_update_bits(rt5645->regmap, RT5645_GEN_CTRL1,
3228 				RT5645_DIG_GATE_CTRL, RT5645_DIG_GATE_CTRL);
3229 	}
3230 	rt5645_irq(0, rt5645);
3231 
3232 	return 0;
3233 }
3234 EXPORT_SYMBOL_GPL(rt5645_set_jack_detect);
3235 
3236 static void rt5645_jack_detect_work(struct work_struct *work)
3237 {
3238 	struct rt5645_priv *rt5645 =
3239 		container_of(work, struct rt5645_priv, jack_detect_work.work);
3240 	int val, btn_type, gpio_state = 0, report = 0;
3241 
3242 	if (!rt5645->codec)
3243 		return;
3244 
3245 	switch (rt5645->pdata.jd_mode) {
3246 	case 0: /* Not using rt5645 JD */
3247 		if (rt5645->gpiod_hp_det) {
3248 			gpio_state = gpiod_get_value(rt5645->gpiod_hp_det);
3249 			dev_dbg(rt5645->codec->dev, "gpio_state = %d\n",
3250 				gpio_state);
3251 			report = rt5645_jack_detect(rt5645->codec, gpio_state);
3252 		}
3253 		snd_soc_jack_report(rt5645->hp_jack,
3254 				    report, SND_JACK_HEADPHONE);
3255 		snd_soc_jack_report(rt5645->mic_jack,
3256 				    report, SND_JACK_MICROPHONE);
3257 		return;
3258 	default: /* read rt5645 jd1_1 status */
3259 		val = snd_soc_read(rt5645->codec, RT5645_INT_IRQ_ST) & 0x1000;
3260 		break;
3261 
3262 	}
3263 
3264 	if (!val && (rt5645->jack_type == 0)) { /* jack in */
3265 		report = rt5645_jack_detect(rt5645->codec, 1);
3266 	} else if (!val && rt5645->jack_type != 0) {
3267 		/* for push button and jack out */
3268 		btn_type = 0;
3269 		if (snd_soc_read(rt5645->codec, RT5645_INT_IRQ_ST) & 0x4) {
3270 			/* button pressed */
3271 			report = SND_JACK_HEADSET;
3272 			btn_type = rt5645_button_detect(rt5645->codec);
3273 			/* rt5650 can report three kinds of button behavior,
3274 			   one click, double click and hold. However,
3275 			   currently we will report button pressed/released
3276 			   event. So all the three button behaviors are
3277 			   treated as button pressed. */
3278 			switch (btn_type) {
3279 			case 0x8000:
3280 			case 0x4000:
3281 			case 0x2000:
3282 				report |= SND_JACK_BTN_0;
3283 				break;
3284 			case 0x1000:
3285 			case 0x0800:
3286 			case 0x0400:
3287 				report |= SND_JACK_BTN_1;
3288 				break;
3289 			case 0x0200:
3290 			case 0x0100:
3291 			case 0x0080:
3292 				report |= SND_JACK_BTN_2;
3293 				break;
3294 			case 0x0040:
3295 			case 0x0020:
3296 			case 0x0010:
3297 				report |= SND_JACK_BTN_3;
3298 				break;
3299 			case 0x0000: /* unpressed */
3300 				break;
3301 			default:
3302 				dev_err(rt5645->codec->dev,
3303 					"Unexpected button code 0x%04x\n",
3304 					btn_type);
3305 				break;
3306 			}
3307 		}
3308 		if (btn_type == 0)/* button release */
3309 			report =  rt5645->jack_type;
3310 		else {
3311 			mod_timer(&rt5645->btn_check_timer,
3312 				msecs_to_jiffies(100));
3313 		}
3314 	} else {
3315 		/* jack out */
3316 		report = 0;
3317 		snd_soc_update_bits(rt5645->codec,
3318 				    RT5645_INT_IRQ_ST, 0x1, 0x0);
3319 		rt5645_jack_detect(rt5645->codec, 0);
3320 	}
3321 
3322 	snd_soc_jack_report(rt5645->hp_jack, report, SND_JACK_HEADPHONE);
3323 	snd_soc_jack_report(rt5645->mic_jack, report, SND_JACK_MICROPHONE);
3324 	if (rt5645->en_button_func)
3325 		snd_soc_jack_report(rt5645->btn_jack,
3326 			report, SND_JACK_BTN_0 | SND_JACK_BTN_1 |
3327 				SND_JACK_BTN_2 | SND_JACK_BTN_3);
3328 }
3329 
3330 static void rt5645_rcclock_work(struct work_struct *work)
3331 {
3332 	struct rt5645_priv *rt5645 =
3333 		container_of(work, struct rt5645_priv, rcclock_work.work);
3334 
3335 	regmap_update_bits(rt5645->regmap, RT5645_MICBIAS,
3336 		RT5645_PWR_CLK25M_MASK, RT5645_PWR_CLK25M_PD);
3337 }
3338 
3339 static irqreturn_t rt5645_irq(int irq, void *data)
3340 {
3341 	struct rt5645_priv *rt5645 = data;
3342 
3343 	queue_delayed_work(system_power_efficient_wq,
3344 			   &rt5645->jack_detect_work, msecs_to_jiffies(250));
3345 
3346 	return IRQ_HANDLED;
3347 }
3348 
3349 static void rt5645_btn_check_callback(struct timer_list *t)
3350 {
3351 	struct rt5645_priv *rt5645 = from_timer(rt5645, t, btn_check_timer);
3352 
3353 	queue_delayed_work(system_power_efficient_wq,
3354 		   &rt5645->jack_detect_work, msecs_to_jiffies(5));
3355 }
3356 
3357 static int rt5645_probe(struct snd_soc_codec *codec)
3358 {
3359 	struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
3360 	struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
3361 
3362 	rt5645->codec = codec;
3363 
3364 	switch (rt5645->codec_type) {
3365 	case CODEC_TYPE_RT5645:
3366 		snd_soc_dapm_new_controls(dapm,
3367 			rt5645_specific_dapm_widgets,
3368 			ARRAY_SIZE(rt5645_specific_dapm_widgets));
3369 		snd_soc_dapm_add_routes(dapm,
3370 			rt5645_specific_dapm_routes,
3371 			ARRAY_SIZE(rt5645_specific_dapm_routes));
3372 		if (rt5645->v_id < 3) {
3373 			snd_soc_dapm_add_routes(dapm,
3374 				rt5645_old_dapm_routes,
3375 				ARRAY_SIZE(rt5645_old_dapm_routes));
3376 		}
3377 		break;
3378 	case CODEC_TYPE_RT5650:
3379 		snd_soc_dapm_new_controls(dapm,
3380 			rt5650_specific_dapm_widgets,
3381 			ARRAY_SIZE(rt5650_specific_dapm_widgets));
3382 		snd_soc_dapm_add_routes(dapm,
3383 			rt5650_specific_dapm_routes,
3384 			ARRAY_SIZE(rt5650_specific_dapm_routes));
3385 		break;
3386 	}
3387 
3388 	snd_soc_codec_force_bias_level(codec, SND_SOC_BIAS_OFF);
3389 
3390 	/* for JD function */
3391 	if (rt5645->pdata.jd_mode) {
3392 		snd_soc_dapm_force_enable_pin(dapm, "JD Power");
3393 		snd_soc_dapm_force_enable_pin(dapm, "LDO2");
3394 		snd_soc_dapm_sync(dapm);
3395 	}
3396 
3397 	rt5645->eq_param = devm_kzalloc(codec->dev,
3398 		RT5645_HWEQ_NUM * sizeof(struct rt5645_eq_param_s), GFP_KERNEL);
3399 
3400 	return 0;
3401 }
3402 
3403 static int rt5645_remove(struct snd_soc_codec *codec)
3404 {
3405 	rt5645_reset(codec);
3406 	return 0;
3407 }
3408 
3409 #ifdef CONFIG_PM
3410 static int rt5645_suspend(struct snd_soc_codec *codec)
3411 {
3412 	struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
3413 
3414 	regcache_cache_only(rt5645->regmap, true);
3415 	regcache_mark_dirty(rt5645->regmap);
3416 
3417 	return 0;
3418 }
3419 
3420 static int rt5645_resume(struct snd_soc_codec *codec)
3421 {
3422 	struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
3423 
3424 	regcache_cache_only(rt5645->regmap, false);
3425 	regcache_sync(rt5645->regmap);
3426 
3427 	return 0;
3428 }
3429 #else
3430 #define rt5645_suspend NULL
3431 #define rt5645_resume NULL
3432 #endif
3433 
3434 #define RT5645_STEREO_RATES SNDRV_PCM_RATE_8000_96000
3435 #define RT5645_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
3436 			SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
3437 
3438 static const struct snd_soc_dai_ops rt5645_aif_dai_ops = {
3439 	.hw_params = rt5645_hw_params,
3440 	.set_fmt = rt5645_set_dai_fmt,
3441 	.set_sysclk = rt5645_set_dai_sysclk,
3442 	.set_tdm_slot = rt5645_set_tdm_slot,
3443 	.set_pll = rt5645_set_dai_pll,
3444 };
3445 
3446 static struct snd_soc_dai_driver rt5645_dai[] = {
3447 	{
3448 		.name = "rt5645-aif1",
3449 		.id = RT5645_AIF1,
3450 		.playback = {
3451 			.stream_name = "AIF1 Playback",
3452 			.channels_min = 1,
3453 			.channels_max = 2,
3454 			.rates = RT5645_STEREO_RATES,
3455 			.formats = RT5645_FORMATS,
3456 		},
3457 		.capture = {
3458 			.stream_name = "AIF1 Capture",
3459 			.channels_min = 1,
3460 			.channels_max = 4,
3461 			.rates = RT5645_STEREO_RATES,
3462 			.formats = RT5645_FORMATS,
3463 		},
3464 		.ops = &rt5645_aif_dai_ops,
3465 	},
3466 	{
3467 		.name = "rt5645-aif2",
3468 		.id = RT5645_AIF2,
3469 		.playback = {
3470 			.stream_name = "AIF2 Playback",
3471 			.channels_min = 1,
3472 			.channels_max = 2,
3473 			.rates = RT5645_STEREO_RATES,
3474 			.formats = RT5645_FORMATS,
3475 		},
3476 		.capture = {
3477 			.stream_name = "AIF2 Capture",
3478 			.channels_min = 1,
3479 			.channels_max = 2,
3480 			.rates = RT5645_STEREO_RATES,
3481 			.formats = RT5645_FORMATS,
3482 		},
3483 		.ops = &rt5645_aif_dai_ops,
3484 	},
3485 };
3486 
3487 static const struct snd_soc_codec_driver soc_codec_dev_rt5645 = {
3488 	.probe = rt5645_probe,
3489 	.remove = rt5645_remove,
3490 	.suspend = rt5645_suspend,
3491 	.resume = rt5645_resume,
3492 	.set_bias_level = rt5645_set_bias_level,
3493 	.idle_bias_off = true,
3494 	.component_driver = {
3495 		.controls		= rt5645_snd_controls,
3496 		.num_controls		= ARRAY_SIZE(rt5645_snd_controls),
3497 		.dapm_widgets		= rt5645_dapm_widgets,
3498 		.num_dapm_widgets	= ARRAY_SIZE(rt5645_dapm_widgets),
3499 		.dapm_routes		= rt5645_dapm_routes,
3500 		.num_dapm_routes	= ARRAY_SIZE(rt5645_dapm_routes),
3501 	},
3502 };
3503 
3504 static const struct regmap_config rt5645_regmap = {
3505 	.reg_bits = 8,
3506 	.val_bits = 16,
3507 	.use_single_rw = true,
3508 	.max_register = RT5645_VENDOR_ID2 + 1 + (ARRAY_SIZE(rt5645_ranges) *
3509 					       RT5645_PR_SPACING),
3510 	.volatile_reg = rt5645_volatile_register,
3511 	.readable_reg = rt5645_readable_register,
3512 
3513 	.cache_type = REGCACHE_RBTREE,
3514 	.reg_defaults = rt5645_reg,
3515 	.num_reg_defaults = ARRAY_SIZE(rt5645_reg),
3516 	.ranges = rt5645_ranges,
3517 	.num_ranges = ARRAY_SIZE(rt5645_ranges),
3518 };
3519 
3520 static const struct regmap_config rt5650_regmap = {
3521 	.reg_bits = 8,
3522 	.val_bits = 16,
3523 	.use_single_rw = true,
3524 	.max_register = RT5645_VENDOR_ID2 + 1 + (ARRAY_SIZE(rt5645_ranges) *
3525 					       RT5645_PR_SPACING),
3526 	.volatile_reg = rt5645_volatile_register,
3527 	.readable_reg = rt5645_readable_register,
3528 
3529 	.cache_type = REGCACHE_RBTREE,
3530 	.reg_defaults = rt5650_reg,
3531 	.num_reg_defaults = ARRAY_SIZE(rt5650_reg),
3532 	.ranges = rt5645_ranges,
3533 	.num_ranges = ARRAY_SIZE(rt5645_ranges),
3534 };
3535 
3536 static const struct regmap_config temp_regmap = {
3537 	.name="nocache",
3538 	.reg_bits = 8,
3539 	.val_bits = 16,
3540 	.use_single_rw = true,
3541 	.max_register = RT5645_VENDOR_ID2 + 1,
3542 	.cache_type = REGCACHE_NONE,
3543 };
3544 
3545 static const struct i2c_device_id rt5645_i2c_id[] = {
3546 	{ "rt5645", 0 },
3547 	{ "rt5650", 0 },
3548 	{ }
3549 };
3550 MODULE_DEVICE_TABLE(i2c, rt5645_i2c_id);
3551 
3552 #ifdef CONFIG_OF
3553 static const struct of_device_id rt5645_of_match[] = {
3554 	{ .compatible = "realtek,rt5645", },
3555 	{ .compatible = "realtek,rt5650", },
3556 	{ }
3557 };
3558 MODULE_DEVICE_TABLE(of, rt5645_of_match);
3559 #endif
3560 
3561 #ifdef CONFIG_ACPI
3562 static const struct acpi_device_id rt5645_acpi_match[] = {
3563 	{ "10EC5645", 0 },
3564 	{ "10EC5648", 0 },
3565 	{ "10EC5650", 0 },
3566 	{ "10EC5640", 0 },
3567 	{ "10EC3270", 0 },
3568 	{},
3569 };
3570 MODULE_DEVICE_TABLE(acpi, rt5645_acpi_match);
3571 #endif
3572 
3573 static const struct rt5645_platform_data general_platform_data = {
3574 	.dmic1_data_pin = RT5645_DMIC1_DISABLE,
3575 	.dmic2_data_pin = RT5645_DMIC_DATA_IN2P,
3576 	.jd_mode = 3,
3577 };
3578 
3579 static const struct dmi_system_id dmi_platform_intel_braswell[] = {
3580 	{
3581 		.ident = "Intel Strago",
3582 		.matches = {
3583 			DMI_MATCH(DMI_PRODUCT_NAME, "Strago"),
3584 		},
3585 	},
3586 	{
3587 		.ident = "Google Chrome",
3588 		.matches = {
3589 			DMI_MATCH(DMI_SYS_VENDOR, "GOOGLE"),
3590 		},
3591 	},
3592 	{
3593 		.ident = "Google Setzer",
3594 		.matches = {
3595 			DMI_MATCH(DMI_PRODUCT_NAME, "Setzer"),
3596 		},
3597 	},
3598 	{
3599 		.ident = "Microsoft Surface 3",
3600 		.matches = {
3601 			DMI_MATCH(DMI_PRODUCT_NAME, "Surface 3"),
3602 		},
3603 	},
3604 	{ }
3605 };
3606 
3607 static const struct rt5645_platform_data buddy_platform_data = {
3608 	.dmic1_data_pin = RT5645_DMIC_DATA_GPIO5,
3609 	.dmic2_data_pin = RT5645_DMIC_DATA_IN2P,
3610 	.jd_mode = 3,
3611 	.level_trigger_irq = true,
3612 };
3613 
3614 static const struct dmi_system_id dmi_platform_intel_broadwell[] = {
3615 	{
3616 		.ident = "Chrome Buddy",
3617 		.matches = {
3618 			DMI_MATCH(DMI_PRODUCT_NAME, "Buddy"),
3619 		},
3620 	},
3621 	{ }
3622 };
3623 
3624 static const struct rt5645_platform_data gpd_win_platform_data = {
3625 	.jd_mode = 3,
3626 	.inv_jd1_1 = true,
3627 };
3628 
3629 static const struct dmi_system_id dmi_platform_gpd_win[] = {
3630 	{
3631 		/*
3632 		 * Match for the GPDwin which unfortunately uses somewhat
3633 		 * generic dmi strings, which is why we test for 4 strings.
3634 		 * Comparing against 23 other byt/cht boards, board_vendor
3635 		 * and board_name are unique to the GPDwin, where as only one
3636 		 * other board has the same board_serial and 3 others have
3637 		 * the same default product_name. Also the GPDwin is the
3638 		 * only device to have both board_ and product_name not set.
3639 		 */
3640 		.ident = "GPD Win",
3641 		.matches = {
3642 			DMI_MATCH(DMI_BOARD_VENDOR, "AMI Corporation"),
3643 			DMI_MATCH(DMI_BOARD_NAME, "Default string"),
3644 			DMI_MATCH(DMI_BOARD_SERIAL, "Default string"),
3645 			DMI_MATCH(DMI_PRODUCT_NAME, "Default string"),
3646 		},
3647 	},
3648 	{}
3649 };
3650 
3651 static const struct rt5645_platform_data general_platform_data2 = {
3652 	.dmic1_data_pin = RT5645_DMIC_DATA_IN2N,
3653 	.dmic2_data_pin = RT5645_DMIC2_DISABLE,
3654 	.jd_mode = 3,
3655 	.inv_jd1_1 = true,
3656 };
3657 
3658 static const struct dmi_system_id dmi_platform_asus_t100ha[] = {
3659 	{
3660 		.ident = "ASUS T100HAN",
3661 		.matches = {
3662 			DMI_EXACT_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."),
3663 			DMI_MATCH(DMI_PRODUCT_NAME, "T100HAN"),
3664 		},
3665 	},
3666 	{ }
3667 };
3668 
3669 static const struct rt5645_platform_data minix_z83_4_platform_data = {
3670 	.jd_mode = 3,
3671 };
3672 
3673 static const struct dmi_system_id dmi_platform_minix_z83_4[] = {
3674 	{
3675 		.ident = "MINIX Z83-4",
3676 		.matches = {
3677 			DMI_EXACT_MATCH(DMI_SYS_VENDOR, "MINIX"),
3678 			DMI_MATCH(DMI_PRODUCT_NAME, "Z83-4"),
3679 		},
3680 	},
3681 	{ }
3682 };
3683 
3684 static bool rt5645_check_dp(struct device *dev)
3685 {
3686 	if (device_property_present(dev, "realtek,in2-differential") ||
3687 		device_property_present(dev, "realtek,dmic1-data-pin") ||
3688 		device_property_present(dev, "realtek,dmic2-data-pin") ||
3689 		device_property_present(dev, "realtek,jd-mode"))
3690 		return true;
3691 
3692 	return false;
3693 }
3694 
3695 static int rt5645_parse_dt(struct rt5645_priv *rt5645, struct device *dev)
3696 {
3697 	rt5645->pdata.in2_diff = device_property_read_bool(dev,
3698 		"realtek,in2-differential");
3699 	device_property_read_u32(dev,
3700 		"realtek,dmic1-data-pin", &rt5645->pdata.dmic1_data_pin);
3701 	device_property_read_u32(dev,
3702 		"realtek,dmic2-data-pin", &rt5645->pdata.dmic2_data_pin);
3703 	device_property_read_u32(dev,
3704 		"realtek,jd-mode", &rt5645->pdata.jd_mode);
3705 
3706 	return 0;
3707 }
3708 
3709 static int rt5645_i2c_probe(struct i2c_client *i2c,
3710 		    const struct i2c_device_id *id)
3711 {
3712 	struct rt5645_platform_data *pdata = dev_get_platdata(&i2c->dev);
3713 	struct rt5645_priv *rt5645;
3714 	int ret, i;
3715 	unsigned int val;
3716 	struct regmap *regmap;
3717 
3718 	rt5645 = devm_kzalloc(&i2c->dev, sizeof(struct rt5645_priv),
3719 				GFP_KERNEL);
3720 	if (rt5645 == NULL)
3721 		return -ENOMEM;
3722 
3723 	rt5645->i2c = i2c;
3724 	i2c_set_clientdata(i2c, rt5645);
3725 
3726 	if (pdata)
3727 		rt5645->pdata = *pdata;
3728 	else if (dmi_check_system(dmi_platform_intel_broadwell))
3729 		rt5645->pdata = buddy_platform_data;
3730 	else if (rt5645_check_dp(&i2c->dev))
3731 		rt5645_parse_dt(rt5645, &i2c->dev);
3732 	else if (dmi_check_system(dmi_platform_intel_braswell))
3733 		rt5645->pdata = general_platform_data;
3734 	else if (dmi_check_system(dmi_platform_gpd_win))
3735 		rt5645->pdata = gpd_win_platform_data;
3736 	else if (dmi_check_system(dmi_platform_asus_t100ha))
3737 		rt5645->pdata = general_platform_data2;
3738 	else if (dmi_check_system(dmi_platform_minix_z83_4))
3739 		rt5645->pdata = minix_z83_4_platform_data;
3740 
3741 	if (quirk != -1) {
3742 		rt5645->pdata.in2_diff = QUIRK_IN2_DIFF(quirk);
3743 		rt5645->pdata.level_trigger_irq = QUIRK_LEVEL_IRQ(quirk);
3744 		rt5645->pdata.inv_jd1_1 = QUIRK_INV_JD1_1(quirk);
3745 		rt5645->pdata.jd_mode = QUIRK_JD_MODE(quirk);
3746 		rt5645->pdata.dmic1_data_pin = QUIRK_DMIC1_DATA_PIN(quirk);
3747 		rt5645->pdata.dmic2_data_pin = QUIRK_DMIC2_DATA_PIN(quirk);
3748 	}
3749 
3750 	rt5645->gpiod_hp_det = devm_gpiod_get_optional(&i2c->dev, "hp-detect",
3751 						       GPIOD_IN);
3752 
3753 	if (IS_ERR(rt5645->gpiod_hp_det)) {
3754 		dev_info(&i2c->dev, "failed to initialize gpiod\n");
3755 		ret = PTR_ERR(rt5645->gpiod_hp_det);
3756 		/*
3757 		 * Continue if optional gpiod is missing, bail for all other
3758 		 * errors, including -EPROBE_DEFER
3759 		 */
3760 		if (ret != -ENOENT)
3761 			return ret;
3762 	}
3763 
3764 	for (i = 0; i < ARRAY_SIZE(rt5645->supplies); i++)
3765 		rt5645->supplies[i].supply = rt5645_supply_names[i];
3766 
3767 	ret = devm_regulator_bulk_get(&i2c->dev,
3768 				      ARRAY_SIZE(rt5645->supplies),
3769 				      rt5645->supplies);
3770 	if (ret) {
3771 		dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
3772 		return ret;
3773 	}
3774 
3775 	ret = regulator_bulk_enable(ARRAY_SIZE(rt5645->supplies),
3776 				    rt5645->supplies);
3777 	if (ret) {
3778 		dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret);
3779 		return ret;
3780 	}
3781 
3782 	regmap = devm_regmap_init_i2c(i2c, &temp_regmap);
3783 	if (IS_ERR(regmap)) {
3784 		ret = PTR_ERR(regmap);
3785 		dev_err(&i2c->dev, "Failed to allocate temp register map: %d\n",
3786 			ret);
3787 		return ret;
3788 	}
3789 
3790 	/*
3791 	 * Read after 400msec, as it is the interval required between
3792 	 * read and power On.
3793 	 */
3794 	msleep(TIME_TO_POWER_MS);
3795 	regmap_read(regmap, RT5645_VENDOR_ID2, &val);
3796 
3797 	switch (val) {
3798 	case RT5645_DEVICE_ID:
3799 		rt5645->regmap = devm_regmap_init_i2c(i2c, &rt5645_regmap);
3800 		rt5645->codec_type = CODEC_TYPE_RT5645;
3801 		break;
3802 	case RT5650_DEVICE_ID:
3803 		rt5645->regmap = devm_regmap_init_i2c(i2c, &rt5650_regmap);
3804 		rt5645->codec_type = CODEC_TYPE_RT5650;
3805 		break;
3806 	default:
3807 		dev_err(&i2c->dev,
3808 			"Device with ID register %#x is not rt5645 or rt5650\n",
3809 			val);
3810 		ret = -ENODEV;
3811 		goto err_enable;
3812 	}
3813 
3814 	if (IS_ERR(rt5645->regmap)) {
3815 		ret = PTR_ERR(rt5645->regmap);
3816 		dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
3817 			ret);
3818 		return ret;
3819 	}
3820 
3821 	regmap_write(rt5645->regmap, RT5645_RESET, 0);
3822 
3823 	regmap_read(regmap, RT5645_VENDOR_ID, &val);
3824 	rt5645->v_id = val & 0xff;
3825 
3826 	ret = regmap_register_patch(rt5645->regmap, init_list,
3827 				    ARRAY_SIZE(init_list));
3828 	if (ret != 0)
3829 		dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret);
3830 
3831 	if (rt5645->codec_type == CODEC_TYPE_RT5650) {
3832 		ret = regmap_register_patch(rt5645->regmap, rt5650_init_list,
3833 				    ARRAY_SIZE(rt5650_init_list));
3834 		if (ret != 0)
3835 			dev_warn(&i2c->dev, "Apply rt5650 patch failed: %d\n",
3836 					   ret);
3837 	}
3838 
3839 	regmap_update_bits(rt5645->regmap, RT5645_CLSD_OUT_CTRL, 0xc0, 0xc0);
3840 
3841 	if (rt5645->pdata.in2_diff)
3842 		regmap_update_bits(rt5645->regmap, RT5645_IN2_CTRL,
3843 					RT5645_IN_DF2, RT5645_IN_DF2);
3844 
3845 	if (rt5645->pdata.dmic1_data_pin || rt5645->pdata.dmic2_data_pin) {
3846 		regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
3847 			RT5645_GP2_PIN_MASK, RT5645_GP2_PIN_DMIC1_SCL);
3848 	}
3849 	switch (rt5645->pdata.dmic1_data_pin) {
3850 	case RT5645_DMIC_DATA_IN2N:
3851 		regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
3852 			RT5645_DMIC_1_DP_MASK, RT5645_DMIC_1_DP_IN2N);
3853 		break;
3854 
3855 	case RT5645_DMIC_DATA_GPIO5:
3856 		regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
3857 			RT5645_I2S2_DAC_PIN_MASK, RT5645_I2S2_DAC_PIN_GPIO);
3858 		regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
3859 			RT5645_DMIC_1_DP_MASK, RT5645_DMIC_1_DP_GPIO5);
3860 		regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
3861 			RT5645_GP5_PIN_MASK, RT5645_GP5_PIN_DMIC1_SDA);
3862 		break;
3863 
3864 	case RT5645_DMIC_DATA_GPIO11:
3865 		regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
3866 			RT5645_DMIC_1_DP_MASK, RT5645_DMIC_1_DP_GPIO11);
3867 		regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
3868 			RT5645_GP11_PIN_MASK,
3869 			RT5645_GP11_PIN_DMIC1_SDA);
3870 		break;
3871 
3872 	default:
3873 		break;
3874 	}
3875 
3876 	switch (rt5645->pdata.dmic2_data_pin) {
3877 	case RT5645_DMIC_DATA_IN2P:
3878 		regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
3879 			RT5645_DMIC_2_DP_MASK, RT5645_DMIC_2_DP_IN2P);
3880 		break;
3881 
3882 	case RT5645_DMIC_DATA_GPIO6:
3883 		regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
3884 			RT5645_DMIC_2_DP_MASK, RT5645_DMIC_2_DP_GPIO6);
3885 		regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
3886 			RT5645_GP6_PIN_MASK, RT5645_GP6_PIN_DMIC2_SDA);
3887 		break;
3888 
3889 	case RT5645_DMIC_DATA_GPIO10:
3890 		regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
3891 			RT5645_DMIC_2_DP_MASK, RT5645_DMIC_2_DP_GPIO10);
3892 		regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
3893 			RT5645_GP10_PIN_MASK,
3894 			RT5645_GP10_PIN_DMIC2_SDA);
3895 		break;
3896 
3897 	case RT5645_DMIC_DATA_GPIO12:
3898 		regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
3899 			RT5645_DMIC_2_DP_MASK, RT5645_DMIC_2_DP_GPIO12);
3900 		regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
3901 			RT5645_GP12_PIN_MASK,
3902 			RT5645_GP12_PIN_DMIC2_SDA);
3903 		break;
3904 
3905 	default:
3906 		break;
3907 	}
3908 
3909 	if (rt5645->pdata.jd_mode) {
3910 		regmap_update_bits(rt5645->regmap, RT5645_GEN_CTRL3,
3911 				   RT5645_IRQ_CLK_GATE_CTRL,
3912 				   RT5645_IRQ_CLK_GATE_CTRL);
3913 		regmap_update_bits(rt5645->regmap, RT5645_MICBIAS,
3914 				   RT5645_IRQ_CLK_INT, RT5645_IRQ_CLK_INT);
3915 		regmap_update_bits(rt5645->regmap, RT5645_IRQ_CTRL2,
3916 				   RT5645_IRQ_JD_1_1_EN, RT5645_IRQ_JD_1_1_EN);
3917 		regmap_update_bits(rt5645->regmap, RT5645_GEN_CTRL3,
3918 				   RT5645_JD_PSV_MODE, RT5645_JD_PSV_MODE);
3919 		regmap_update_bits(rt5645->regmap, RT5645_HPO_MIXER,
3920 				   RT5645_IRQ_PSV_MODE, RT5645_IRQ_PSV_MODE);
3921 		regmap_update_bits(rt5645->regmap, RT5645_MICBIAS,
3922 				   RT5645_MIC2_OVCD_EN, RT5645_MIC2_OVCD_EN);
3923 		regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
3924 				   RT5645_GP1_PIN_IRQ, RT5645_GP1_PIN_IRQ);
3925 		switch (rt5645->pdata.jd_mode) {
3926 		case 1:
3927 			regmap_update_bits(rt5645->regmap, RT5645_A_JD_CTRL1,
3928 					   RT5645_JD1_MODE_MASK,
3929 					   RT5645_JD1_MODE_0);
3930 			break;
3931 		case 2:
3932 			regmap_update_bits(rt5645->regmap, RT5645_A_JD_CTRL1,
3933 					   RT5645_JD1_MODE_MASK,
3934 					   RT5645_JD1_MODE_1);
3935 			break;
3936 		case 3:
3937 			regmap_update_bits(rt5645->regmap, RT5645_A_JD_CTRL1,
3938 					   RT5645_JD1_MODE_MASK,
3939 					   RT5645_JD1_MODE_2);
3940 			break;
3941 		default:
3942 			break;
3943 		}
3944 		if (rt5645->pdata.inv_jd1_1) {
3945 			regmap_update_bits(rt5645->regmap, RT5645_IRQ_CTRL2,
3946 				RT5645_JD_1_1_MASK, RT5645_JD_1_1_INV);
3947 		}
3948 	}
3949 
3950 	regmap_update_bits(rt5645->regmap, RT5645_ADDA_CLK1,
3951 		RT5645_I2S_PD1_MASK, RT5645_I2S_PD1_2);
3952 
3953 	if (rt5645->pdata.level_trigger_irq) {
3954 		regmap_update_bits(rt5645->regmap, RT5645_IRQ_CTRL2,
3955 			RT5645_JD_1_1_MASK, RT5645_JD_1_1_INV);
3956 	}
3957 	timer_setup(&rt5645->btn_check_timer, rt5645_btn_check_callback, 0);
3958 
3959 	INIT_DELAYED_WORK(&rt5645->jack_detect_work, rt5645_jack_detect_work);
3960 	INIT_DELAYED_WORK(&rt5645->rcclock_work, rt5645_rcclock_work);
3961 
3962 	if (rt5645->i2c->irq) {
3963 		ret = request_threaded_irq(rt5645->i2c->irq, NULL, rt5645_irq,
3964 			IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING
3965 			| IRQF_ONESHOT, "rt5645", rt5645);
3966 		if (ret) {
3967 			dev_err(&i2c->dev, "Failed to reguest IRQ: %d\n", ret);
3968 			goto err_enable;
3969 		}
3970 	}
3971 
3972 	ret = snd_soc_register_codec(&i2c->dev, &soc_codec_dev_rt5645,
3973 				     rt5645_dai, ARRAY_SIZE(rt5645_dai));
3974 	if (ret)
3975 		goto err_irq;
3976 
3977 	return 0;
3978 
3979 err_irq:
3980 	if (rt5645->i2c->irq)
3981 		free_irq(rt5645->i2c->irq, rt5645);
3982 err_enable:
3983 	regulator_bulk_disable(ARRAY_SIZE(rt5645->supplies), rt5645->supplies);
3984 	return ret;
3985 }
3986 
3987 static int rt5645_i2c_remove(struct i2c_client *i2c)
3988 {
3989 	struct rt5645_priv *rt5645 = i2c_get_clientdata(i2c);
3990 
3991 	if (i2c->irq)
3992 		free_irq(i2c->irq, rt5645);
3993 
3994 	cancel_delayed_work_sync(&rt5645->jack_detect_work);
3995 	cancel_delayed_work_sync(&rt5645->rcclock_work);
3996 	del_timer_sync(&rt5645->btn_check_timer);
3997 
3998 	snd_soc_unregister_codec(&i2c->dev);
3999 	regulator_bulk_disable(ARRAY_SIZE(rt5645->supplies), rt5645->supplies);
4000 
4001 	return 0;
4002 }
4003 
4004 static void rt5645_i2c_shutdown(struct i2c_client *i2c)
4005 {
4006 	struct rt5645_priv *rt5645 = i2c_get_clientdata(i2c);
4007 
4008 	regmap_update_bits(rt5645->regmap, RT5645_GEN_CTRL3,
4009 		RT5645_RING2_SLEEVE_GND, RT5645_RING2_SLEEVE_GND);
4010 	regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL2, RT5645_CBJ_MN_JD,
4011 		RT5645_CBJ_MN_JD);
4012 	regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL1, RT5645_CBJ_BST1_EN,
4013 		0);
4014 	msleep(20);
4015 	regmap_write(rt5645->regmap, RT5645_RESET, 0);
4016 }
4017 
4018 static struct i2c_driver rt5645_i2c_driver = {
4019 	.driver = {
4020 		.name = "rt5645",
4021 		.of_match_table = of_match_ptr(rt5645_of_match),
4022 		.acpi_match_table = ACPI_PTR(rt5645_acpi_match),
4023 	},
4024 	.probe = rt5645_i2c_probe,
4025 	.remove = rt5645_i2c_remove,
4026 	.shutdown = rt5645_i2c_shutdown,
4027 	.id_table = rt5645_i2c_id,
4028 };
4029 module_i2c_driver(rt5645_i2c_driver);
4030 
4031 MODULE_DESCRIPTION("ASoC RT5645 driver");
4032 MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>");
4033 MODULE_LICENSE("GPL v2");
4034