1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * rt5645.c -- RT5645 ALSA SoC audio codec driver 4 * 5 * Copyright 2013 Realtek Semiconductor Corp. 6 * Author: Bard Liao <bardliao@realtek.com> 7 */ 8 9 #include <linux/module.h> 10 #include <linux/moduleparam.h> 11 #include <linux/init.h> 12 #include <linux/delay.h> 13 #include <linux/pm.h> 14 #include <linux/i2c.h> 15 #include <linux/platform_device.h> 16 #include <linux/spi/spi.h> 17 #include <linux/gpio/consumer.h> 18 #include <linux/acpi.h> 19 #include <linux/dmi.h> 20 #include <linux/regulator/consumer.h> 21 #include <sound/core.h> 22 #include <sound/pcm.h> 23 #include <sound/pcm_params.h> 24 #include <sound/jack.h> 25 #include <sound/soc.h> 26 #include <sound/soc-dapm.h> 27 #include <sound/initval.h> 28 #include <sound/tlv.h> 29 30 #include "rl6231.h" 31 #include "rt5645.h" 32 33 #define QUIRK_INV_JD1_1(q) ((q) & 1) 34 #define QUIRK_LEVEL_IRQ(q) (((q) >> 1) & 1) 35 #define QUIRK_IN2_DIFF(q) (((q) >> 2) & 1) 36 #define QUIRK_INV_HP_POL(q) (((q) >> 3) & 1) 37 #define QUIRK_JD_MODE(q) (((q) >> 4) & 7) 38 #define QUIRK_DMIC1_DATA_PIN(q) (((q) >> 8) & 3) 39 #define QUIRK_DMIC2_DATA_PIN(q) (((q) >> 12) & 3) 40 41 static unsigned int quirk = -1; 42 module_param(quirk, uint, 0444); 43 MODULE_PARM_DESC(quirk, "RT5645 pdata quirk override"); 44 45 static const struct acpi_gpio_mapping *cht_rt5645_gpios; 46 47 #define RT5645_DEVICE_ID 0x6308 48 #define RT5650_DEVICE_ID 0x6419 49 50 #define RT5645_PR_RANGE_BASE (0xff + 1) 51 #define RT5645_PR_SPACING 0x100 52 53 #define RT5645_PR_BASE (RT5645_PR_RANGE_BASE + (0 * RT5645_PR_SPACING)) 54 55 #define RT5645_HWEQ_NUM 57 56 57 #define TIME_TO_POWER_MS 400 58 59 static const struct regmap_range_cfg rt5645_ranges[] = { 60 { 61 .name = "PR", 62 .range_min = RT5645_PR_BASE, 63 .range_max = RT5645_PR_BASE + 0xf8, 64 .selector_reg = RT5645_PRIV_INDEX, 65 .selector_mask = 0xff, 66 .selector_shift = 0x0, 67 .window_start = RT5645_PRIV_DATA, 68 .window_len = 0x1, 69 }, 70 }; 71 72 static const struct reg_sequence init_list[] = { 73 {RT5645_PR_BASE + 0x3d, 0x3600}, 74 {RT5645_PR_BASE + 0x1c, 0xfd70}, 75 {RT5645_PR_BASE + 0x20, 0x611f}, 76 {RT5645_PR_BASE + 0x21, 0x4040}, 77 {RT5645_PR_BASE + 0x23, 0x0004}, 78 {RT5645_ASRC_4, 0x0120}, 79 }; 80 81 static const struct reg_sequence rt5650_init_list[] = { 82 {0xf6, 0x0100}, 83 {RT5645_PWR_ANLG1, 0x02}, 84 }; 85 86 static const struct reg_default rt5645_reg[] = { 87 { 0x00, 0x0000 }, 88 { 0x01, 0xc8c8 }, 89 { 0x02, 0xc8c8 }, 90 { 0x03, 0xc8c8 }, 91 { 0x0a, 0x0002 }, 92 { 0x0b, 0x2827 }, 93 { 0x0c, 0xe000 }, 94 { 0x0d, 0x0000 }, 95 { 0x0e, 0x0000 }, 96 { 0x0f, 0x0808 }, 97 { 0x14, 0x3333 }, 98 { 0x16, 0x4b00 }, 99 { 0x18, 0x018b }, 100 { 0x19, 0xafaf }, 101 { 0x1a, 0xafaf }, 102 { 0x1b, 0x0001 }, 103 { 0x1c, 0x2f2f }, 104 { 0x1d, 0x2f2f }, 105 { 0x1e, 0x0000 }, 106 { 0x20, 0x0000 }, 107 { 0x27, 0x7060 }, 108 { 0x28, 0x7070 }, 109 { 0x29, 0x8080 }, 110 { 0x2a, 0x5656 }, 111 { 0x2b, 0x5454 }, 112 { 0x2c, 0xaaa0 }, 113 { 0x2d, 0x0000 }, 114 { 0x2f, 0x1002 }, 115 { 0x31, 0x5000 }, 116 { 0x32, 0x0000 }, 117 { 0x33, 0x0000 }, 118 { 0x34, 0x0000 }, 119 { 0x35, 0x0000 }, 120 { 0x3b, 0x0000 }, 121 { 0x3c, 0x007f }, 122 { 0x3d, 0x0000 }, 123 { 0x3e, 0x007f }, 124 { 0x3f, 0x0000 }, 125 { 0x40, 0x001f }, 126 { 0x41, 0x0000 }, 127 { 0x42, 0x001f }, 128 { 0x45, 0x6000 }, 129 { 0x46, 0x003e }, 130 { 0x47, 0x003e }, 131 { 0x48, 0xf807 }, 132 { 0x4a, 0x0004 }, 133 { 0x4d, 0x0000 }, 134 { 0x4e, 0x0000 }, 135 { 0x4f, 0x01ff }, 136 { 0x50, 0x0000 }, 137 { 0x51, 0x0000 }, 138 { 0x52, 0x01ff }, 139 { 0x53, 0xf000 }, 140 { 0x56, 0x0111 }, 141 { 0x57, 0x0064 }, 142 { 0x58, 0xef0e }, 143 { 0x59, 0xf0f0 }, 144 { 0x5a, 0xef0e }, 145 { 0x5b, 0xf0f0 }, 146 { 0x5c, 0xef0e }, 147 { 0x5d, 0xf0f0 }, 148 { 0x5e, 0xf000 }, 149 { 0x5f, 0x0000 }, 150 { 0x61, 0x0300 }, 151 { 0x62, 0x0000 }, 152 { 0x63, 0x00c2 }, 153 { 0x64, 0x0000 }, 154 { 0x65, 0x0000 }, 155 { 0x66, 0x0000 }, 156 { 0x6a, 0x0000 }, 157 { 0x6c, 0x0aaa }, 158 { 0x70, 0x8000 }, 159 { 0x71, 0x8000 }, 160 { 0x72, 0x8000 }, 161 { 0x73, 0x7770 }, 162 { 0x74, 0x3e00 }, 163 { 0x75, 0x2409 }, 164 { 0x76, 0x000a }, 165 { 0x77, 0x0c00 }, 166 { 0x78, 0x0000 }, 167 { 0x79, 0x0123 }, 168 { 0x80, 0x0000 }, 169 { 0x81, 0x0000 }, 170 { 0x82, 0x0000 }, 171 { 0x83, 0x0000 }, 172 { 0x84, 0x0000 }, 173 { 0x85, 0x0000 }, 174 { 0x8a, 0x0120 }, 175 { 0x8e, 0x0004 }, 176 { 0x8f, 0x1100 }, 177 { 0x90, 0x0646 }, 178 { 0x91, 0x0c06 }, 179 { 0x93, 0x0000 }, 180 { 0x94, 0x0200 }, 181 { 0x95, 0x0000 }, 182 { 0x9a, 0x2184 }, 183 { 0x9b, 0x010a }, 184 { 0x9c, 0x0aea }, 185 { 0x9d, 0x000c }, 186 { 0x9e, 0x0400 }, 187 { 0xa0, 0xa0a8 }, 188 { 0xa1, 0x0059 }, 189 { 0xa2, 0x0001 }, 190 { 0xae, 0x6000 }, 191 { 0xaf, 0x0000 }, 192 { 0xb0, 0x6000 }, 193 { 0xb1, 0x0000 }, 194 { 0xb2, 0x0000 }, 195 { 0xb3, 0x001f }, 196 { 0xb4, 0x020c }, 197 { 0xb5, 0x1f00 }, 198 { 0xb6, 0x0000 }, 199 { 0xbb, 0x0000 }, 200 { 0xbc, 0x0000 }, 201 { 0xbd, 0x0000 }, 202 { 0xbe, 0x0000 }, 203 { 0xbf, 0x3100 }, 204 { 0xc0, 0x0000 }, 205 { 0xc1, 0x0000 }, 206 { 0xc2, 0x0000 }, 207 { 0xc3, 0x2000 }, 208 { 0xcd, 0x0000 }, 209 { 0xce, 0x0000 }, 210 { 0xcf, 0x1813 }, 211 { 0xd0, 0x0690 }, 212 { 0xd1, 0x1c17 }, 213 { 0xd3, 0xb320 }, 214 { 0xd4, 0x0000 }, 215 { 0xd6, 0x0400 }, 216 { 0xd9, 0x0809 }, 217 { 0xda, 0x0000 }, 218 { 0xdb, 0x0003 }, 219 { 0xdc, 0x0049 }, 220 { 0xdd, 0x001b }, 221 { 0xdf, 0x0008 }, 222 { 0xe0, 0x4000 }, 223 { 0xe6, 0x8000 }, 224 { 0xe7, 0x0200 }, 225 { 0xec, 0xb300 }, 226 { 0xed, 0x0000 }, 227 { 0xf0, 0x001f }, 228 { 0xf1, 0x020c }, 229 { 0xf2, 0x1f00 }, 230 { 0xf3, 0x0000 }, 231 { 0xf4, 0x4000 }, 232 { 0xf8, 0x0000 }, 233 { 0xf9, 0x0000 }, 234 { 0xfa, 0x2060 }, 235 { 0xfb, 0x4040 }, 236 { 0xfc, 0x0000 }, 237 { 0xfd, 0x0002 }, 238 { 0xfe, 0x10ec }, 239 { 0xff, 0x6308 }, 240 }; 241 242 static const struct reg_default rt5650_reg[] = { 243 { 0x00, 0x0000 }, 244 { 0x01, 0xc8c8 }, 245 { 0x02, 0xc8c8 }, 246 { 0x03, 0xc8c8 }, 247 { 0x0a, 0x0002 }, 248 { 0x0b, 0x2827 }, 249 { 0x0c, 0xe000 }, 250 { 0x0d, 0x0000 }, 251 { 0x0e, 0x0000 }, 252 { 0x0f, 0x0808 }, 253 { 0x14, 0x3333 }, 254 { 0x16, 0x4b00 }, 255 { 0x18, 0x018b }, 256 { 0x19, 0xafaf }, 257 { 0x1a, 0xafaf }, 258 { 0x1b, 0x0001 }, 259 { 0x1c, 0x2f2f }, 260 { 0x1d, 0x2f2f }, 261 { 0x1e, 0x0000 }, 262 { 0x20, 0x0000 }, 263 { 0x27, 0x7060 }, 264 { 0x28, 0x7070 }, 265 { 0x29, 0x8080 }, 266 { 0x2a, 0x5656 }, 267 { 0x2b, 0x5454 }, 268 { 0x2c, 0xaaa0 }, 269 { 0x2d, 0x0000 }, 270 { 0x2f, 0x5002 }, 271 { 0x31, 0x5000 }, 272 { 0x32, 0x0000 }, 273 { 0x33, 0x0000 }, 274 { 0x34, 0x0000 }, 275 { 0x35, 0x0000 }, 276 { 0x3b, 0x0000 }, 277 { 0x3c, 0x007f }, 278 { 0x3d, 0x0000 }, 279 { 0x3e, 0x007f }, 280 { 0x3f, 0x0000 }, 281 { 0x40, 0x001f }, 282 { 0x41, 0x0000 }, 283 { 0x42, 0x001f }, 284 { 0x45, 0x6000 }, 285 { 0x46, 0x003e }, 286 { 0x47, 0x003e }, 287 { 0x48, 0xf807 }, 288 { 0x4a, 0x0004 }, 289 { 0x4d, 0x0000 }, 290 { 0x4e, 0x0000 }, 291 { 0x4f, 0x01ff }, 292 { 0x50, 0x0000 }, 293 { 0x51, 0x0000 }, 294 { 0x52, 0x01ff }, 295 { 0x53, 0xf000 }, 296 { 0x56, 0x0111 }, 297 { 0x57, 0x0064 }, 298 { 0x58, 0xef0e }, 299 { 0x59, 0xf0f0 }, 300 { 0x5a, 0xef0e }, 301 { 0x5b, 0xf0f0 }, 302 { 0x5c, 0xef0e }, 303 { 0x5d, 0xf0f0 }, 304 { 0x5e, 0xf000 }, 305 { 0x5f, 0x0000 }, 306 { 0x61, 0x0300 }, 307 { 0x62, 0x0000 }, 308 { 0x63, 0x00c2 }, 309 { 0x64, 0x0000 }, 310 { 0x65, 0x0000 }, 311 { 0x66, 0x0000 }, 312 { 0x6a, 0x0000 }, 313 { 0x6c, 0x0aaa }, 314 { 0x70, 0x8000 }, 315 { 0x71, 0x8000 }, 316 { 0x72, 0x8000 }, 317 { 0x73, 0x7770 }, 318 { 0x74, 0x3e00 }, 319 { 0x75, 0x2409 }, 320 { 0x76, 0x000a }, 321 { 0x77, 0x0c00 }, 322 { 0x78, 0x0000 }, 323 { 0x79, 0x0123 }, 324 { 0x7a, 0x0123 }, 325 { 0x80, 0x0000 }, 326 { 0x81, 0x0000 }, 327 { 0x82, 0x0000 }, 328 { 0x83, 0x0000 }, 329 { 0x84, 0x0000 }, 330 { 0x85, 0x0000 }, 331 { 0x8a, 0x0120 }, 332 { 0x8e, 0x0004 }, 333 { 0x8f, 0x1100 }, 334 { 0x90, 0x0646 }, 335 { 0x91, 0x0c06 }, 336 { 0x93, 0x0000 }, 337 { 0x94, 0x0200 }, 338 { 0x95, 0x0000 }, 339 { 0x9a, 0x2184 }, 340 { 0x9b, 0x010a }, 341 { 0x9c, 0x0aea }, 342 { 0x9d, 0x000c }, 343 { 0x9e, 0x0400 }, 344 { 0xa0, 0xa0a8 }, 345 { 0xa1, 0x0059 }, 346 { 0xa2, 0x0001 }, 347 { 0xae, 0x6000 }, 348 { 0xaf, 0x0000 }, 349 { 0xb0, 0x6000 }, 350 { 0xb1, 0x0000 }, 351 { 0xb2, 0x0000 }, 352 { 0xb3, 0x001f }, 353 { 0xb4, 0x020c }, 354 { 0xb5, 0x1f00 }, 355 { 0xb6, 0x0000 }, 356 { 0xbb, 0x0000 }, 357 { 0xbc, 0x0000 }, 358 { 0xbd, 0x0000 }, 359 { 0xbe, 0x0000 }, 360 { 0xbf, 0x3100 }, 361 { 0xc0, 0x0000 }, 362 { 0xc1, 0x0000 }, 363 { 0xc2, 0x0000 }, 364 { 0xc3, 0x2000 }, 365 { 0xcd, 0x0000 }, 366 { 0xce, 0x0000 }, 367 { 0xcf, 0x1813 }, 368 { 0xd0, 0x0690 }, 369 { 0xd1, 0x1c17 }, 370 { 0xd3, 0xb320 }, 371 { 0xd4, 0x0000 }, 372 { 0xd6, 0x0400 }, 373 { 0xd9, 0x0809 }, 374 { 0xda, 0x0000 }, 375 { 0xdb, 0x0003 }, 376 { 0xdc, 0x0049 }, 377 { 0xdd, 0x001b }, 378 { 0xdf, 0x0008 }, 379 { 0xe0, 0x4000 }, 380 { 0xe6, 0x8000 }, 381 { 0xe7, 0x0200 }, 382 { 0xec, 0xb300 }, 383 { 0xed, 0x0000 }, 384 { 0xf0, 0x001f }, 385 { 0xf1, 0x020c }, 386 { 0xf2, 0x1f00 }, 387 { 0xf3, 0x0000 }, 388 { 0xf4, 0x4000 }, 389 { 0xf8, 0x0000 }, 390 { 0xf9, 0x0000 }, 391 { 0xfa, 0x2060 }, 392 { 0xfb, 0x4040 }, 393 { 0xfc, 0x0000 }, 394 { 0xfd, 0x0002 }, 395 { 0xfe, 0x10ec }, 396 { 0xff, 0x6308 }, 397 }; 398 399 struct rt5645_eq_param_s { 400 unsigned short reg; 401 unsigned short val; 402 }; 403 404 struct rt5645_eq_param_s_be16 { 405 __be16 reg; 406 __be16 val; 407 }; 408 409 static const char *const rt5645_supply_names[] = { 410 "avdd", 411 "cpvdd", 412 }; 413 414 struct rt5645_platform_data { 415 /* IN2 can optionally be differential */ 416 bool in2_diff; 417 418 unsigned int dmic1_data_pin; 419 /* 0 = IN2N; 1 = GPIO5; 2 = GPIO11 */ 420 unsigned int dmic2_data_pin; 421 /* 0 = IN2P; 1 = GPIO6; 2 = GPIO10; 3 = GPIO12 */ 422 423 unsigned int jd_mode; 424 /* Use level triggered irq */ 425 bool level_trigger_irq; 426 /* Invert JD1_1 status polarity */ 427 bool inv_jd1_1; 428 /* Invert HP detect status polarity */ 429 bool inv_hp_pol; 430 431 /* Value to assign to snd_soc_card.long_name */ 432 const char *long_name; 433 434 /* Some (package) variants have the headset-mic pin not-connected */ 435 bool no_headset_mic; 436 }; 437 438 struct rt5645_priv { 439 struct snd_soc_component *component; 440 struct rt5645_platform_data pdata; 441 struct regmap *regmap; 442 struct i2c_client *i2c; 443 struct gpio_desc *gpiod_hp_det; 444 struct snd_soc_jack *hp_jack; 445 struct snd_soc_jack *mic_jack; 446 struct snd_soc_jack *btn_jack; 447 struct delayed_work jack_detect_work, rcclock_work; 448 struct regulator_bulk_data supplies[ARRAY_SIZE(rt5645_supply_names)]; 449 struct rt5645_eq_param_s *eq_param; 450 struct timer_list btn_check_timer; 451 452 int codec_type; 453 int sysclk; 454 int sysclk_src; 455 int lrck[RT5645_AIFS]; 456 int bclk[RT5645_AIFS]; 457 int master[RT5645_AIFS]; 458 459 int pll_src; 460 int pll_in; 461 int pll_out; 462 463 int jack_type; 464 bool en_button_func; 465 int v_id; 466 }; 467 468 static int rt5645_reset(struct snd_soc_component *component) 469 { 470 return snd_soc_component_write(component, RT5645_RESET, 0); 471 } 472 473 static bool rt5645_volatile_register(struct device *dev, unsigned int reg) 474 { 475 int i; 476 477 for (i = 0; i < ARRAY_SIZE(rt5645_ranges); i++) { 478 if (reg >= rt5645_ranges[i].range_min && 479 reg <= rt5645_ranges[i].range_max) { 480 return true; 481 } 482 } 483 484 switch (reg) { 485 case RT5645_RESET: 486 case RT5645_PRIV_INDEX: 487 case RT5645_PRIV_DATA: 488 case RT5645_IN1_CTRL1: 489 case RT5645_IN1_CTRL2: 490 case RT5645_IN1_CTRL3: 491 case RT5645_A_JD_CTRL1: 492 case RT5645_ADC_EQ_CTRL1: 493 case RT5645_EQ_CTRL1: 494 case RT5645_ALC_CTRL_1: 495 case RT5645_IRQ_CTRL2: 496 case RT5645_IRQ_CTRL3: 497 case RT5645_INT_IRQ_ST: 498 case RT5645_IL_CMD: 499 case RT5650_4BTN_IL_CMD1: 500 case RT5645_VENDOR_ID: 501 case RT5645_VENDOR_ID1: 502 case RT5645_VENDOR_ID2: 503 return true; 504 default: 505 return false; 506 } 507 } 508 509 static bool rt5645_readable_register(struct device *dev, unsigned int reg) 510 { 511 int i; 512 513 for (i = 0; i < ARRAY_SIZE(rt5645_ranges); i++) { 514 if (reg >= rt5645_ranges[i].range_min && 515 reg <= rt5645_ranges[i].range_max) { 516 return true; 517 } 518 } 519 520 switch (reg) { 521 case RT5645_RESET: 522 case RT5645_SPK_VOL: 523 case RT5645_HP_VOL: 524 case RT5645_LOUT1: 525 case RT5645_IN1_CTRL1: 526 case RT5645_IN1_CTRL2: 527 case RT5645_IN1_CTRL3: 528 case RT5645_IN2_CTRL: 529 case RT5645_INL1_INR1_VOL: 530 case RT5645_SPK_FUNC_LIM: 531 case RT5645_ADJ_HPF_CTRL: 532 case RT5645_DAC1_DIG_VOL: 533 case RT5645_DAC2_DIG_VOL: 534 case RT5645_DAC_CTRL: 535 case RT5645_STO1_ADC_DIG_VOL: 536 case RT5645_MONO_ADC_DIG_VOL: 537 case RT5645_ADC_BST_VOL1: 538 case RT5645_ADC_BST_VOL2: 539 case RT5645_STO1_ADC_MIXER: 540 case RT5645_MONO_ADC_MIXER: 541 case RT5645_AD_DA_MIXER: 542 case RT5645_STO_DAC_MIXER: 543 case RT5645_MONO_DAC_MIXER: 544 case RT5645_DIG_MIXER: 545 case RT5650_A_DAC_SOUR: 546 case RT5645_DIG_INF1_DATA: 547 case RT5645_PDM_OUT_CTRL: 548 case RT5645_REC_L1_MIXER: 549 case RT5645_REC_L2_MIXER: 550 case RT5645_REC_R1_MIXER: 551 case RT5645_REC_R2_MIXER: 552 case RT5645_HPMIXL_CTRL: 553 case RT5645_HPOMIXL_CTRL: 554 case RT5645_HPMIXR_CTRL: 555 case RT5645_HPOMIXR_CTRL: 556 case RT5645_HPO_MIXER: 557 case RT5645_SPK_L_MIXER: 558 case RT5645_SPK_R_MIXER: 559 case RT5645_SPO_MIXER: 560 case RT5645_SPO_CLSD_RATIO: 561 case RT5645_OUT_L1_MIXER: 562 case RT5645_OUT_R1_MIXER: 563 case RT5645_OUT_L_GAIN1: 564 case RT5645_OUT_L_GAIN2: 565 case RT5645_OUT_R_GAIN1: 566 case RT5645_OUT_R_GAIN2: 567 case RT5645_LOUT_MIXER: 568 case RT5645_HAPTIC_CTRL1: 569 case RT5645_HAPTIC_CTRL2: 570 case RT5645_HAPTIC_CTRL3: 571 case RT5645_HAPTIC_CTRL4: 572 case RT5645_HAPTIC_CTRL5: 573 case RT5645_HAPTIC_CTRL6: 574 case RT5645_HAPTIC_CTRL7: 575 case RT5645_HAPTIC_CTRL8: 576 case RT5645_HAPTIC_CTRL9: 577 case RT5645_HAPTIC_CTRL10: 578 case RT5645_PWR_DIG1: 579 case RT5645_PWR_DIG2: 580 case RT5645_PWR_ANLG1: 581 case RT5645_PWR_ANLG2: 582 case RT5645_PWR_MIXER: 583 case RT5645_PWR_VOL: 584 case RT5645_PRIV_INDEX: 585 case RT5645_PRIV_DATA: 586 case RT5645_I2S1_SDP: 587 case RT5645_I2S2_SDP: 588 case RT5645_ADDA_CLK1: 589 case RT5645_ADDA_CLK2: 590 case RT5645_DMIC_CTRL1: 591 case RT5645_DMIC_CTRL2: 592 case RT5645_TDM_CTRL_1: 593 case RT5645_TDM_CTRL_2: 594 case RT5645_TDM_CTRL_3: 595 case RT5650_TDM_CTRL_4: 596 case RT5645_GLB_CLK: 597 case RT5645_PLL_CTRL1: 598 case RT5645_PLL_CTRL2: 599 case RT5645_ASRC_1: 600 case RT5645_ASRC_2: 601 case RT5645_ASRC_3: 602 case RT5645_ASRC_4: 603 case RT5645_DEPOP_M1: 604 case RT5645_DEPOP_M2: 605 case RT5645_DEPOP_M3: 606 case RT5645_CHARGE_PUMP: 607 case RT5645_MICBIAS: 608 case RT5645_A_JD_CTRL1: 609 case RT5645_VAD_CTRL4: 610 case RT5645_CLSD_OUT_CTRL: 611 case RT5645_ADC_EQ_CTRL1: 612 case RT5645_ADC_EQ_CTRL2: 613 case RT5645_EQ_CTRL1: 614 case RT5645_EQ_CTRL2: 615 case RT5645_ALC_CTRL_1: 616 case RT5645_ALC_CTRL_2: 617 case RT5645_ALC_CTRL_3: 618 case RT5645_ALC_CTRL_4: 619 case RT5645_ALC_CTRL_5: 620 case RT5645_JD_CTRL: 621 case RT5645_IRQ_CTRL1: 622 case RT5645_IRQ_CTRL2: 623 case RT5645_IRQ_CTRL3: 624 case RT5645_INT_IRQ_ST: 625 case RT5645_GPIO_CTRL1: 626 case RT5645_GPIO_CTRL2: 627 case RT5645_GPIO_CTRL3: 628 case RT5645_BASS_BACK: 629 case RT5645_MP3_PLUS1: 630 case RT5645_MP3_PLUS2: 631 case RT5645_ADJ_HPF1: 632 case RT5645_ADJ_HPF2: 633 case RT5645_HP_CALIB_AMP_DET: 634 case RT5645_SV_ZCD1: 635 case RT5645_SV_ZCD2: 636 case RT5645_IL_CMD: 637 case RT5645_IL_CMD2: 638 case RT5645_IL_CMD3: 639 case RT5650_4BTN_IL_CMD1: 640 case RT5650_4BTN_IL_CMD2: 641 case RT5645_DRC1_HL_CTRL1: 642 case RT5645_DRC2_HL_CTRL1: 643 case RT5645_ADC_MONO_HP_CTRL1: 644 case RT5645_ADC_MONO_HP_CTRL2: 645 case RT5645_DRC2_CTRL1: 646 case RT5645_DRC2_CTRL2: 647 case RT5645_DRC2_CTRL3: 648 case RT5645_DRC2_CTRL4: 649 case RT5645_DRC2_CTRL5: 650 case RT5645_JD_CTRL3: 651 case RT5645_JD_CTRL4: 652 case RT5645_GEN_CTRL1: 653 case RT5645_GEN_CTRL2: 654 case RT5645_GEN_CTRL3: 655 case RT5645_VENDOR_ID: 656 case RT5645_VENDOR_ID1: 657 case RT5645_VENDOR_ID2: 658 return true; 659 default: 660 return false; 661 } 662 } 663 664 static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -4650, 150, 0); 665 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6525, 75, 0); 666 static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -3450, 150, 0); 667 static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0); 668 static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0); 669 670 /* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */ 671 static const DECLARE_TLV_DB_RANGE(bst_tlv, 672 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0), 673 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0), 674 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0), 675 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0), 676 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0), 677 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0), 678 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0) 679 ); 680 681 /* {-6, -4.5, -3, -1.5, 0, 0.82, 1.58, 2.28} dB */ 682 static const DECLARE_TLV_DB_RANGE(spk_clsd_tlv, 683 0, 4, TLV_DB_SCALE_ITEM(-600, 150, 0), 684 5, 5, TLV_DB_SCALE_ITEM(82, 0, 0), 685 6, 6, TLV_DB_SCALE_ITEM(158, 0, 0), 686 7, 7, TLV_DB_SCALE_ITEM(228, 0, 0) 687 ); 688 689 static int rt5645_hweq_info(struct snd_kcontrol *kcontrol, 690 struct snd_ctl_elem_info *uinfo) 691 { 692 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES; 693 uinfo->count = RT5645_HWEQ_NUM * sizeof(struct rt5645_eq_param_s); 694 695 return 0; 696 } 697 698 static int rt5645_hweq_get(struct snd_kcontrol *kcontrol, 699 struct snd_ctl_elem_value *ucontrol) 700 { 701 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 702 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component); 703 struct rt5645_eq_param_s_be16 *eq_param = 704 (struct rt5645_eq_param_s_be16 *)ucontrol->value.bytes.data; 705 int i; 706 707 for (i = 0; i < RT5645_HWEQ_NUM; i++) { 708 eq_param[i].reg = cpu_to_be16(rt5645->eq_param[i].reg); 709 eq_param[i].val = cpu_to_be16(rt5645->eq_param[i].val); 710 } 711 712 return 0; 713 } 714 715 static bool rt5645_validate_hweq(unsigned short reg) 716 { 717 if ((reg >= 0x1a4 && reg <= 0x1cd) || (reg >= 0x1e5 && reg <= 0x1f8) || 718 (reg == RT5645_EQ_CTRL2)) 719 return true; 720 721 return false; 722 } 723 724 static int rt5645_hweq_put(struct snd_kcontrol *kcontrol, 725 struct snd_ctl_elem_value *ucontrol) 726 { 727 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 728 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component); 729 struct rt5645_eq_param_s_be16 *eq_param = 730 (struct rt5645_eq_param_s_be16 *)ucontrol->value.bytes.data; 731 int i; 732 733 for (i = 0; i < RT5645_HWEQ_NUM; i++) { 734 rt5645->eq_param[i].reg = be16_to_cpu(eq_param[i].reg); 735 rt5645->eq_param[i].val = be16_to_cpu(eq_param[i].val); 736 } 737 738 /* The final setting of the table should be RT5645_EQ_CTRL2 */ 739 for (i = RT5645_HWEQ_NUM - 1; i >= 0; i--) { 740 if (rt5645->eq_param[i].reg == 0) 741 continue; 742 else if (rt5645->eq_param[i].reg != RT5645_EQ_CTRL2) 743 return 0; 744 else 745 break; 746 } 747 748 for (i = 0; i < RT5645_HWEQ_NUM; i++) { 749 if (!rt5645_validate_hweq(rt5645->eq_param[i].reg) && 750 rt5645->eq_param[i].reg != 0) 751 return 0; 752 else if (rt5645->eq_param[i].reg == 0) 753 break; 754 } 755 756 return 0; 757 } 758 759 #define RT5645_HWEQ(xname) \ 760 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 761 .info = rt5645_hweq_info, \ 762 .get = rt5645_hweq_get, \ 763 .put = rt5645_hweq_put \ 764 } 765 766 static int rt5645_spk_put_volsw(struct snd_kcontrol *kcontrol, 767 struct snd_ctl_elem_value *ucontrol) 768 { 769 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 770 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component); 771 int ret; 772 773 regmap_update_bits(rt5645->regmap, RT5645_MICBIAS, 774 RT5645_PWR_CLK25M_MASK, RT5645_PWR_CLK25M_PU); 775 776 ret = snd_soc_put_volsw(kcontrol, ucontrol); 777 778 mod_delayed_work(system_power_efficient_wq, &rt5645->rcclock_work, 779 msecs_to_jiffies(200)); 780 781 return ret; 782 } 783 784 static const char * const rt5645_dac1_vol_ctrl_mode_text[] = { 785 "immediately", "zero crossing", "soft ramp" 786 }; 787 788 static SOC_ENUM_SINGLE_DECL( 789 rt5645_dac1_vol_ctrl_mode, RT5645_PR_BASE, 790 RT5645_DA1_ZDET_SFT, rt5645_dac1_vol_ctrl_mode_text); 791 792 static const struct snd_kcontrol_new rt5645_snd_controls[] = { 793 /* Speaker Output Volume */ 794 SOC_DOUBLE("Speaker Channel Switch", RT5645_SPK_VOL, 795 RT5645_VOL_L_SFT, RT5645_VOL_R_SFT, 1, 1), 796 SOC_DOUBLE_EXT_TLV("Speaker Playback Volume", RT5645_SPK_VOL, 797 RT5645_L_VOL_SFT, RT5645_R_VOL_SFT, 39, 1, snd_soc_get_volsw, 798 rt5645_spk_put_volsw, out_vol_tlv), 799 800 /* ClassD modulator Speaker Gain Ratio */ 801 SOC_SINGLE_TLV("Speaker ClassD Playback Volume", RT5645_SPO_CLSD_RATIO, 802 RT5645_SPK_G_CLSD_SFT, 7, 0, spk_clsd_tlv), 803 804 /* Headphone Output Volume */ 805 SOC_DOUBLE("Headphone Channel Switch", RT5645_HP_VOL, 806 RT5645_VOL_L_SFT, RT5645_VOL_R_SFT, 1, 1), 807 SOC_DOUBLE_TLV("Headphone Playback Volume", RT5645_HP_VOL, 808 RT5645_L_VOL_SFT, RT5645_R_VOL_SFT, 39, 1, out_vol_tlv), 809 810 /* OUTPUT Control */ 811 SOC_DOUBLE("OUT Playback Switch", RT5645_LOUT1, 812 RT5645_L_MUTE_SFT, RT5645_R_MUTE_SFT, 1, 1), 813 SOC_DOUBLE("OUT Channel Switch", RT5645_LOUT1, 814 RT5645_VOL_L_SFT, RT5645_VOL_R_SFT, 1, 1), 815 SOC_DOUBLE_TLV("OUT Playback Volume", RT5645_LOUT1, 816 RT5645_L_VOL_SFT, RT5645_R_VOL_SFT, 39, 1, out_vol_tlv), 817 818 /* DAC Digital Volume */ 819 SOC_DOUBLE("DAC2 Playback Switch", RT5645_DAC_CTRL, 820 RT5645_M_DAC_L2_VOL_SFT, RT5645_M_DAC_R2_VOL_SFT, 1, 1), 821 SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5645_DAC1_DIG_VOL, 822 RT5645_L_VOL_SFT + 1, RT5645_R_VOL_SFT + 1, 87, 0, dac_vol_tlv), 823 SOC_DOUBLE_TLV("Mono DAC Playback Volume", RT5645_DAC2_DIG_VOL, 824 RT5645_L_VOL_SFT + 1, RT5645_R_VOL_SFT + 1, 87, 0, dac_vol_tlv), 825 826 /* IN1/IN2 Control */ 827 SOC_SINGLE_TLV("IN1 Boost", RT5645_IN1_CTRL1, 828 RT5645_BST_SFT1, 12, 0, bst_tlv), 829 SOC_SINGLE_TLV("IN2 Boost", RT5645_IN2_CTRL, 830 RT5645_BST_SFT2, 8, 0, bst_tlv), 831 832 /* INL/INR Volume Control */ 833 SOC_DOUBLE_TLV("IN Capture Volume", RT5645_INL1_INR1_VOL, 834 RT5645_INL_VOL_SFT, RT5645_INR_VOL_SFT, 31, 1, in_vol_tlv), 835 836 /* ADC Digital Volume Control */ 837 SOC_DOUBLE("ADC Capture Switch", RT5645_STO1_ADC_DIG_VOL, 838 RT5645_L_MUTE_SFT, RT5645_R_MUTE_SFT, 1, 1), 839 SOC_DOUBLE_TLV("ADC Capture Volume", RT5645_STO1_ADC_DIG_VOL, 840 RT5645_L_VOL_SFT + 1, RT5645_R_VOL_SFT + 1, 63, 0, adc_vol_tlv), 841 SOC_DOUBLE("Mono ADC Capture Switch", RT5645_MONO_ADC_DIG_VOL, 842 RT5645_L_MUTE_SFT, RT5645_R_MUTE_SFT, 1, 1), 843 SOC_DOUBLE_TLV("Mono ADC Capture Volume", RT5645_MONO_ADC_DIG_VOL, 844 RT5645_L_VOL_SFT + 1, RT5645_R_VOL_SFT + 1, 63, 0, adc_vol_tlv), 845 846 /* ADC Boost Volume Control */ 847 SOC_DOUBLE_TLV("ADC Boost Capture Volume", RT5645_ADC_BST_VOL1, 848 RT5645_STO1_ADC_L_BST_SFT, RT5645_STO1_ADC_R_BST_SFT, 3, 0, 849 adc_bst_tlv), 850 SOC_DOUBLE_TLV("Mono ADC Boost Capture Volume", RT5645_ADC_BST_VOL2, 851 RT5645_MONO_ADC_L_BST_SFT, RT5645_MONO_ADC_R_BST_SFT, 3, 0, 852 adc_bst_tlv), 853 854 /* I2S2 function select */ 855 SOC_SINGLE("I2S2 Func Switch", RT5645_GPIO_CTRL1, RT5645_I2S2_SEL_SFT, 856 1, 1), 857 RT5645_HWEQ("Speaker HWEQ"), 858 859 /* Digital Soft Volume Control */ 860 SOC_ENUM("DAC1 Digital Volume Control Func", rt5645_dac1_vol_ctrl_mode), 861 }; 862 863 /** 864 * set_dmic_clk - Set parameter of dmic. 865 * 866 * @w: DAPM widget. 867 * @kcontrol: The kcontrol of this widget. 868 * @event: Event id. 869 * 870 */ 871 static int set_dmic_clk(struct snd_soc_dapm_widget *w, 872 struct snd_kcontrol *kcontrol, int event) 873 { 874 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 875 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component); 876 int idx, rate; 877 878 rate = rt5645->sysclk / rl6231_get_pre_div(rt5645->regmap, 879 RT5645_ADDA_CLK1, RT5645_I2S_PD1_SFT); 880 idx = rl6231_calc_dmic_clk(rate); 881 if (idx < 0) 882 dev_err(component->dev, "Failed to set DMIC clock\n"); 883 else 884 snd_soc_component_update_bits(component, RT5645_DMIC_CTRL1, 885 RT5645_DMIC_CLK_MASK, idx << RT5645_DMIC_CLK_SFT); 886 return idx; 887 } 888 889 static int is_sys_clk_from_pll(struct snd_soc_dapm_widget *source, 890 struct snd_soc_dapm_widget *sink) 891 { 892 struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm); 893 unsigned int val; 894 895 val = snd_soc_component_read(component, RT5645_GLB_CLK); 896 val &= RT5645_SCLK_SRC_MASK; 897 if (val == RT5645_SCLK_SRC_PLL1) 898 return 1; 899 else 900 return 0; 901 } 902 903 static int is_using_asrc(struct snd_soc_dapm_widget *source, 904 struct snd_soc_dapm_widget *sink) 905 { 906 struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm); 907 unsigned int reg, shift, val; 908 909 switch (source->shift) { 910 case 0: 911 reg = RT5645_ASRC_3; 912 shift = 0; 913 break; 914 case 1: 915 reg = RT5645_ASRC_3; 916 shift = 4; 917 break; 918 case 3: 919 reg = RT5645_ASRC_2; 920 shift = 0; 921 break; 922 case 8: 923 reg = RT5645_ASRC_2; 924 shift = 4; 925 break; 926 case 9: 927 reg = RT5645_ASRC_2; 928 shift = 8; 929 break; 930 case 10: 931 reg = RT5645_ASRC_2; 932 shift = 12; 933 break; 934 default: 935 return 0; 936 } 937 938 val = (snd_soc_component_read(component, reg) >> shift) & 0xf; 939 switch (val) { 940 case 1: 941 case 2: 942 case 3: 943 case 4: 944 return 1; 945 default: 946 return 0; 947 } 948 949 } 950 951 static int rt5645_enable_hweq(struct snd_soc_component *component) 952 { 953 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component); 954 int i; 955 956 for (i = 0; i < RT5645_HWEQ_NUM; i++) { 957 if (rt5645_validate_hweq(rt5645->eq_param[i].reg)) 958 regmap_write(rt5645->regmap, rt5645->eq_param[i].reg, 959 rt5645->eq_param[i].val); 960 else 961 break; 962 } 963 964 return 0; 965 } 966 967 /** 968 * rt5645_sel_asrc_clk_src - select ASRC clock source for a set of filters 969 * @component: SoC audio component device. 970 * @filter_mask: mask of filters. 971 * @clk_src: clock source 972 * 973 * The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5645 can 974 * only support standard 32fs or 64fs i2s format, ASRC should be enabled to 975 * support special i2s clock format such as Intel's 100fs(100 * sampling rate). 976 * ASRC function will track i2s clock and generate a corresponding system clock 977 * for codec. This function provides an API to select the clock source for a 978 * set of filters specified by the mask. And the codec driver will turn on ASRC 979 * for these filters if ASRC is selected as their clock source. 980 */ 981 int rt5645_sel_asrc_clk_src(struct snd_soc_component *component, 982 unsigned int filter_mask, unsigned int clk_src) 983 { 984 unsigned int asrc2_mask = 0; 985 unsigned int asrc2_value = 0; 986 unsigned int asrc3_mask = 0; 987 unsigned int asrc3_value = 0; 988 989 switch (clk_src) { 990 case RT5645_CLK_SEL_SYS: 991 case RT5645_CLK_SEL_I2S1_ASRC: 992 case RT5645_CLK_SEL_I2S2_ASRC: 993 case RT5645_CLK_SEL_SYS2: 994 break; 995 996 default: 997 return -EINVAL; 998 } 999 1000 if (filter_mask & RT5645_DA_STEREO_FILTER) { 1001 asrc2_mask |= RT5645_DA_STO_CLK_SEL_MASK; 1002 asrc2_value = (asrc2_value & ~RT5645_DA_STO_CLK_SEL_MASK) 1003 | (clk_src << RT5645_DA_STO_CLK_SEL_SFT); 1004 } 1005 1006 if (filter_mask & RT5645_DA_MONO_L_FILTER) { 1007 asrc2_mask |= RT5645_DA_MONOL_CLK_SEL_MASK; 1008 asrc2_value = (asrc2_value & ~RT5645_DA_MONOL_CLK_SEL_MASK) 1009 | (clk_src << RT5645_DA_MONOL_CLK_SEL_SFT); 1010 } 1011 1012 if (filter_mask & RT5645_DA_MONO_R_FILTER) { 1013 asrc2_mask |= RT5645_DA_MONOR_CLK_SEL_MASK; 1014 asrc2_value = (asrc2_value & ~RT5645_DA_MONOR_CLK_SEL_MASK) 1015 | (clk_src << RT5645_DA_MONOR_CLK_SEL_SFT); 1016 } 1017 1018 if (filter_mask & RT5645_AD_STEREO_FILTER) { 1019 asrc2_mask |= RT5645_AD_STO1_CLK_SEL_MASK; 1020 asrc2_value = (asrc2_value & ~RT5645_AD_STO1_CLK_SEL_MASK) 1021 | (clk_src << RT5645_AD_STO1_CLK_SEL_SFT); 1022 } 1023 1024 if (filter_mask & RT5645_AD_MONO_L_FILTER) { 1025 asrc3_mask |= RT5645_AD_MONOL_CLK_SEL_MASK; 1026 asrc3_value = (asrc3_value & ~RT5645_AD_MONOL_CLK_SEL_MASK) 1027 | (clk_src << RT5645_AD_MONOL_CLK_SEL_SFT); 1028 } 1029 1030 if (filter_mask & RT5645_AD_MONO_R_FILTER) { 1031 asrc3_mask |= RT5645_AD_MONOR_CLK_SEL_MASK; 1032 asrc3_value = (asrc3_value & ~RT5645_AD_MONOR_CLK_SEL_MASK) 1033 | (clk_src << RT5645_AD_MONOR_CLK_SEL_SFT); 1034 } 1035 1036 if (asrc2_mask) 1037 snd_soc_component_update_bits(component, RT5645_ASRC_2, 1038 asrc2_mask, asrc2_value); 1039 1040 if (asrc3_mask) 1041 snd_soc_component_update_bits(component, RT5645_ASRC_3, 1042 asrc3_mask, asrc3_value); 1043 1044 return 0; 1045 } 1046 EXPORT_SYMBOL_GPL(rt5645_sel_asrc_clk_src); 1047 1048 /* Digital Mixer */ 1049 static const struct snd_kcontrol_new rt5645_sto1_adc_l_mix[] = { 1050 SOC_DAPM_SINGLE("ADC1 Switch", RT5645_STO1_ADC_MIXER, 1051 RT5645_M_ADC_L1_SFT, 1, 1), 1052 SOC_DAPM_SINGLE("ADC2 Switch", RT5645_STO1_ADC_MIXER, 1053 RT5645_M_ADC_L2_SFT, 1, 1), 1054 }; 1055 1056 static const struct snd_kcontrol_new rt5645_sto1_adc_r_mix[] = { 1057 SOC_DAPM_SINGLE("ADC1 Switch", RT5645_STO1_ADC_MIXER, 1058 RT5645_M_ADC_R1_SFT, 1, 1), 1059 SOC_DAPM_SINGLE("ADC2 Switch", RT5645_STO1_ADC_MIXER, 1060 RT5645_M_ADC_R2_SFT, 1, 1), 1061 }; 1062 1063 static const struct snd_kcontrol_new rt5645_mono_adc_l_mix[] = { 1064 SOC_DAPM_SINGLE("ADC1 Switch", RT5645_MONO_ADC_MIXER, 1065 RT5645_M_MONO_ADC_L1_SFT, 1, 1), 1066 SOC_DAPM_SINGLE("ADC2 Switch", RT5645_MONO_ADC_MIXER, 1067 RT5645_M_MONO_ADC_L2_SFT, 1, 1), 1068 }; 1069 1070 static const struct snd_kcontrol_new rt5645_mono_adc_r_mix[] = { 1071 SOC_DAPM_SINGLE("ADC1 Switch", RT5645_MONO_ADC_MIXER, 1072 RT5645_M_MONO_ADC_R1_SFT, 1, 1), 1073 SOC_DAPM_SINGLE("ADC2 Switch", RT5645_MONO_ADC_MIXER, 1074 RT5645_M_MONO_ADC_R2_SFT, 1, 1), 1075 }; 1076 1077 static const struct snd_kcontrol_new rt5645_dac_l_mix[] = { 1078 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5645_AD_DA_MIXER, 1079 RT5645_M_ADCMIX_L_SFT, 1, 1), 1080 SOC_DAPM_SINGLE_AUTODISABLE("DAC1 Switch", RT5645_AD_DA_MIXER, 1081 RT5645_M_DAC1_L_SFT, 1, 1), 1082 }; 1083 1084 static const struct snd_kcontrol_new rt5645_dac_r_mix[] = { 1085 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5645_AD_DA_MIXER, 1086 RT5645_M_ADCMIX_R_SFT, 1, 1), 1087 SOC_DAPM_SINGLE_AUTODISABLE("DAC1 Switch", RT5645_AD_DA_MIXER, 1088 RT5645_M_DAC1_R_SFT, 1, 1), 1089 }; 1090 1091 static const struct snd_kcontrol_new rt5645_sto_dac_l_mix[] = { 1092 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_STO_DAC_MIXER, 1093 RT5645_M_DAC_L1_SFT, 1, 1), 1094 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_STO_DAC_MIXER, 1095 RT5645_M_DAC_L2_SFT, 1, 1), 1096 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_STO_DAC_MIXER, 1097 RT5645_M_DAC_R1_STO_L_SFT, 1, 1), 1098 }; 1099 1100 static const struct snd_kcontrol_new rt5645_sto_dac_r_mix[] = { 1101 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_STO_DAC_MIXER, 1102 RT5645_M_DAC_R1_SFT, 1, 1), 1103 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_STO_DAC_MIXER, 1104 RT5645_M_DAC_R2_SFT, 1, 1), 1105 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_STO_DAC_MIXER, 1106 RT5645_M_DAC_L1_STO_R_SFT, 1, 1), 1107 }; 1108 1109 static const struct snd_kcontrol_new rt5645_mono_dac_l_mix[] = { 1110 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_MONO_DAC_MIXER, 1111 RT5645_M_DAC_L1_MONO_L_SFT, 1, 1), 1112 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_MONO_DAC_MIXER, 1113 RT5645_M_DAC_L2_MONO_L_SFT, 1, 1), 1114 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_MONO_DAC_MIXER, 1115 RT5645_M_DAC_R2_MONO_L_SFT, 1, 1), 1116 }; 1117 1118 static const struct snd_kcontrol_new rt5645_mono_dac_r_mix[] = { 1119 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_MONO_DAC_MIXER, 1120 RT5645_M_DAC_R1_MONO_R_SFT, 1, 1), 1121 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_MONO_DAC_MIXER, 1122 RT5645_M_DAC_R2_MONO_R_SFT, 1, 1), 1123 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_MONO_DAC_MIXER, 1124 RT5645_M_DAC_L2_MONO_R_SFT, 1, 1), 1125 }; 1126 1127 static const struct snd_kcontrol_new rt5645_dig_l_mix[] = { 1128 SOC_DAPM_SINGLE("Sto DAC Mix L Switch", RT5645_DIG_MIXER, 1129 RT5645_M_STO_L_DAC_L_SFT, 1, 1), 1130 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_DIG_MIXER, 1131 RT5645_M_DAC_L2_DAC_L_SFT, 1, 1), 1132 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_DIG_MIXER, 1133 RT5645_M_DAC_R2_DAC_L_SFT, 1, 1), 1134 }; 1135 1136 static const struct snd_kcontrol_new rt5645_dig_r_mix[] = { 1137 SOC_DAPM_SINGLE("Sto DAC Mix R Switch", RT5645_DIG_MIXER, 1138 RT5645_M_STO_R_DAC_R_SFT, 1, 1), 1139 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_DIG_MIXER, 1140 RT5645_M_DAC_R2_DAC_R_SFT, 1, 1), 1141 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_DIG_MIXER, 1142 RT5645_M_DAC_L2_DAC_R_SFT, 1, 1), 1143 }; 1144 1145 /* Analog Input Mixer */ 1146 static const struct snd_kcontrol_new rt5645_rec_l_mix[] = { 1147 SOC_DAPM_SINGLE("HPOL Switch", RT5645_REC_L2_MIXER, 1148 RT5645_M_HP_L_RM_L_SFT, 1, 1), 1149 SOC_DAPM_SINGLE("INL Switch", RT5645_REC_L2_MIXER, 1150 RT5645_M_IN_L_RM_L_SFT, 1, 1), 1151 SOC_DAPM_SINGLE("BST2 Switch", RT5645_REC_L2_MIXER, 1152 RT5645_M_BST2_RM_L_SFT, 1, 1), 1153 SOC_DAPM_SINGLE("BST1 Switch", RT5645_REC_L2_MIXER, 1154 RT5645_M_BST1_RM_L_SFT, 1, 1), 1155 SOC_DAPM_SINGLE("OUT MIXL Switch", RT5645_REC_L2_MIXER, 1156 RT5645_M_OM_L_RM_L_SFT, 1, 1), 1157 }; 1158 1159 static const struct snd_kcontrol_new rt5645_rec_r_mix[] = { 1160 SOC_DAPM_SINGLE("HPOR Switch", RT5645_REC_R2_MIXER, 1161 RT5645_M_HP_R_RM_R_SFT, 1, 1), 1162 SOC_DAPM_SINGLE("INR Switch", RT5645_REC_R2_MIXER, 1163 RT5645_M_IN_R_RM_R_SFT, 1, 1), 1164 SOC_DAPM_SINGLE("BST2 Switch", RT5645_REC_R2_MIXER, 1165 RT5645_M_BST2_RM_R_SFT, 1, 1), 1166 SOC_DAPM_SINGLE("BST1 Switch", RT5645_REC_R2_MIXER, 1167 RT5645_M_BST1_RM_R_SFT, 1, 1), 1168 SOC_DAPM_SINGLE("OUT MIXR Switch", RT5645_REC_R2_MIXER, 1169 RT5645_M_OM_R_RM_R_SFT, 1, 1), 1170 }; 1171 1172 static const struct snd_kcontrol_new rt5645_spk_l_mix[] = { 1173 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_SPK_L_MIXER, 1174 RT5645_M_DAC_L1_SM_L_SFT, 1, 1), 1175 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_SPK_L_MIXER, 1176 RT5645_M_DAC_L2_SM_L_SFT, 1, 1), 1177 SOC_DAPM_SINGLE("INL Switch", RT5645_SPK_L_MIXER, 1178 RT5645_M_IN_L_SM_L_SFT, 1, 1), 1179 SOC_DAPM_SINGLE("BST1 Switch", RT5645_SPK_L_MIXER, 1180 RT5645_M_BST1_L_SM_L_SFT, 1, 1), 1181 }; 1182 1183 static const struct snd_kcontrol_new rt5645_spk_r_mix[] = { 1184 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_SPK_R_MIXER, 1185 RT5645_M_DAC_R1_SM_R_SFT, 1, 1), 1186 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_SPK_R_MIXER, 1187 RT5645_M_DAC_R2_SM_R_SFT, 1, 1), 1188 SOC_DAPM_SINGLE("INR Switch", RT5645_SPK_R_MIXER, 1189 RT5645_M_IN_R_SM_R_SFT, 1, 1), 1190 SOC_DAPM_SINGLE("BST2 Switch", RT5645_SPK_R_MIXER, 1191 RT5645_M_BST2_R_SM_R_SFT, 1, 1), 1192 }; 1193 1194 static const struct snd_kcontrol_new rt5645_out_l_mix[] = { 1195 SOC_DAPM_SINGLE("BST1 Switch", RT5645_OUT_L1_MIXER, 1196 RT5645_M_BST1_OM_L_SFT, 1, 1), 1197 SOC_DAPM_SINGLE("INL Switch", RT5645_OUT_L1_MIXER, 1198 RT5645_M_IN_L_OM_L_SFT, 1, 1), 1199 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_OUT_L1_MIXER, 1200 RT5645_M_DAC_L2_OM_L_SFT, 1, 1), 1201 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_OUT_L1_MIXER, 1202 RT5645_M_DAC_L1_OM_L_SFT, 1, 1), 1203 }; 1204 1205 static const struct snd_kcontrol_new rt5645_out_r_mix[] = { 1206 SOC_DAPM_SINGLE("BST2 Switch", RT5645_OUT_R1_MIXER, 1207 RT5645_M_BST2_OM_R_SFT, 1, 1), 1208 SOC_DAPM_SINGLE("INR Switch", RT5645_OUT_R1_MIXER, 1209 RT5645_M_IN_R_OM_R_SFT, 1, 1), 1210 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_OUT_R1_MIXER, 1211 RT5645_M_DAC_R2_OM_R_SFT, 1, 1), 1212 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_OUT_R1_MIXER, 1213 RT5645_M_DAC_R1_OM_R_SFT, 1, 1), 1214 }; 1215 1216 static const struct snd_kcontrol_new rt5645_spo_l_mix[] = { 1217 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_SPO_MIXER, 1218 RT5645_M_DAC_R1_SPM_L_SFT, 1, 1), 1219 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_SPO_MIXER, 1220 RT5645_M_DAC_L1_SPM_L_SFT, 1, 1), 1221 SOC_DAPM_SINGLE("SPKVOL R Switch", RT5645_SPO_MIXER, 1222 RT5645_M_SV_R_SPM_L_SFT, 1, 1), 1223 SOC_DAPM_SINGLE("SPKVOL L Switch", RT5645_SPO_MIXER, 1224 RT5645_M_SV_L_SPM_L_SFT, 1, 1), 1225 }; 1226 1227 static const struct snd_kcontrol_new rt5645_spo_r_mix[] = { 1228 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_SPO_MIXER, 1229 RT5645_M_DAC_R1_SPM_R_SFT, 1, 1), 1230 SOC_DAPM_SINGLE("SPKVOL R Switch", RT5645_SPO_MIXER, 1231 RT5645_M_SV_R_SPM_R_SFT, 1, 1), 1232 }; 1233 1234 static const struct snd_kcontrol_new rt5645_hpo_mix[] = { 1235 SOC_DAPM_SINGLE("DAC1 Switch", RT5645_HPO_MIXER, 1236 RT5645_M_DAC1_HM_SFT, 1, 1), 1237 SOC_DAPM_SINGLE("HPVOL Switch", RT5645_HPO_MIXER, 1238 RT5645_M_HPVOL_HM_SFT, 1, 1), 1239 }; 1240 1241 static const struct snd_kcontrol_new rt5645_hpvoll_mix[] = { 1242 SOC_DAPM_SINGLE("DAC1 Switch", RT5645_HPOMIXL_CTRL, 1243 RT5645_M_DAC1_HV_SFT, 1, 1), 1244 SOC_DAPM_SINGLE("DAC2 Switch", RT5645_HPOMIXL_CTRL, 1245 RT5645_M_DAC2_HV_SFT, 1, 1), 1246 SOC_DAPM_SINGLE("INL Switch", RT5645_HPOMIXL_CTRL, 1247 RT5645_M_IN_HV_SFT, 1, 1), 1248 SOC_DAPM_SINGLE("BST1 Switch", RT5645_HPOMIXL_CTRL, 1249 RT5645_M_BST1_HV_SFT, 1, 1), 1250 }; 1251 1252 static const struct snd_kcontrol_new rt5645_hpvolr_mix[] = { 1253 SOC_DAPM_SINGLE("DAC1 Switch", RT5645_HPOMIXR_CTRL, 1254 RT5645_M_DAC1_HV_SFT, 1, 1), 1255 SOC_DAPM_SINGLE("DAC2 Switch", RT5645_HPOMIXR_CTRL, 1256 RT5645_M_DAC2_HV_SFT, 1, 1), 1257 SOC_DAPM_SINGLE("INR Switch", RT5645_HPOMIXR_CTRL, 1258 RT5645_M_IN_HV_SFT, 1, 1), 1259 SOC_DAPM_SINGLE("BST2 Switch", RT5645_HPOMIXR_CTRL, 1260 RT5645_M_BST2_HV_SFT, 1, 1), 1261 }; 1262 1263 static const struct snd_kcontrol_new rt5645_lout_mix[] = { 1264 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_LOUT_MIXER, 1265 RT5645_M_DAC_L1_LM_SFT, 1, 1), 1266 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_LOUT_MIXER, 1267 RT5645_M_DAC_R1_LM_SFT, 1, 1), 1268 SOC_DAPM_SINGLE("OUTMIX L Switch", RT5645_LOUT_MIXER, 1269 RT5645_M_OV_L_LM_SFT, 1, 1), 1270 SOC_DAPM_SINGLE("OUTMIX R Switch", RT5645_LOUT_MIXER, 1271 RT5645_M_OV_R_LM_SFT, 1, 1), 1272 }; 1273 1274 /*DAC1 L/R source*/ /* MX-29 [9:8] [11:10] */ 1275 static const char * const rt5645_dac1_src[] = { 1276 "IF1 DAC", "IF2 DAC", "IF3 DAC" 1277 }; 1278 1279 static SOC_ENUM_SINGLE_DECL( 1280 rt5645_dac1l_enum, RT5645_AD_DA_MIXER, 1281 RT5645_DAC1_L_SEL_SFT, rt5645_dac1_src); 1282 1283 static const struct snd_kcontrol_new rt5645_dac1l_mux = 1284 SOC_DAPM_ENUM("DAC1 L source", rt5645_dac1l_enum); 1285 1286 static SOC_ENUM_SINGLE_DECL( 1287 rt5645_dac1r_enum, RT5645_AD_DA_MIXER, 1288 RT5645_DAC1_R_SEL_SFT, rt5645_dac1_src); 1289 1290 static const struct snd_kcontrol_new rt5645_dac1r_mux = 1291 SOC_DAPM_ENUM("DAC1 R source", rt5645_dac1r_enum); 1292 1293 /*DAC2 L/R source*/ /* MX-1B [6:4] [2:0] */ 1294 static const char * const rt5645_dac12_src[] = { 1295 "IF1 DAC", "IF2 DAC", "IF3 DAC", "Mono ADC", "VAD_ADC" 1296 }; 1297 1298 static SOC_ENUM_SINGLE_DECL( 1299 rt5645_dac2l_enum, RT5645_DAC_CTRL, 1300 RT5645_DAC2_L_SEL_SFT, rt5645_dac12_src); 1301 1302 static const struct snd_kcontrol_new rt5645_dac_l2_mux = 1303 SOC_DAPM_ENUM("DAC2 L source", rt5645_dac2l_enum); 1304 1305 static const char * const rt5645_dacr2_src[] = { 1306 "IF1 DAC", "IF2 DAC", "IF3 DAC", "Mono ADC", "Haptic" 1307 }; 1308 1309 static SOC_ENUM_SINGLE_DECL( 1310 rt5645_dac2r_enum, RT5645_DAC_CTRL, 1311 RT5645_DAC2_R_SEL_SFT, rt5645_dacr2_src); 1312 1313 static const struct snd_kcontrol_new rt5645_dac_r2_mux = 1314 SOC_DAPM_ENUM("DAC2 R source", rt5645_dac2r_enum); 1315 1316 /* Stereo1 ADC source */ 1317 /* MX-27 [12] */ 1318 static const char * const rt5645_stereo_adc1_src[] = { 1319 "DAC MIX", "ADC" 1320 }; 1321 1322 static SOC_ENUM_SINGLE_DECL( 1323 rt5645_stereo1_adc1_enum, RT5645_STO1_ADC_MIXER, 1324 RT5645_ADC_1_SRC_SFT, rt5645_stereo_adc1_src); 1325 1326 static const struct snd_kcontrol_new rt5645_sto_adc1_mux = 1327 SOC_DAPM_ENUM("Stereo1 ADC1 Mux", rt5645_stereo1_adc1_enum); 1328 1329 /* MX-27 [11] */ 1330 static const char * const rt5645_stereo_adc2_src[] = { 1331 "DAC MIX", "DMIC" 1332 }; 1333 1334 static SOC_ENUM_SINGLE_DECL( 1335 rt5645_stereo1_adc2_enum, RT5645_STO1_ADC_MIXER, 1336 RT5645_ADC_2_SRC_SFT, rt5645_stereo_adc2_src); 1337 1338 static const struct snd_kcontrol_new rt5645_sto_adc2_mux = 1339 SOC_DAPM_ENUM("Stereo1 ADC2 Mux", rt5645_stereo1_adc2_enum); 1340 1341 /* MX-27 [8] */ 1342 static const char * const rt5645_stereo_dmic_src[] = { 1343 "DMIC1", "DMIC2" 1344 }; 1345 1346 static SOC_ENUM_SINGLE_DECL( 1347 rt5645_stereo1_dmic_enum, RT5645_STO1_ADC_MIXER, 1348 RT5645_DMIC_SRC_SFT, rt5645_stereo_dmic_src); 1349 1350 static const struct snd_kcontrol_new rt5645_sto1_dmic_mux = 1351 SOC_DAPM_ENUM("Stereo1 DMIC source", rt5645_stereo1_dmic_enum); 1352 1353 /* Mono ADC source */ 1354 /* MX-28 [12] */ 1355 static const char * const rt5645_mono_adc_l1_src[] = { 1356 "Mono DAC MIXL", "ADC" 1357 }; 1358 1359 static SOC_ENUM_SINGLE_DECL( 1360 rt5645_mono_adc_l1_enum, RT5645_MONO_ADC_MIXER, 1361 RT5645_MONO_ADC_L1_SRC_SFT, rt5645_mono_adc_l1_src); 1362 1363 static const struct snd_kcontrol_new rt5645_mono_adc_l1_mux = 1364 SOC_DAPM_ENUM("Mono ADC1 left source", rt5645_mono_adc_l1_enum); 1365 /* MX-28 [11] */ 1366 static const char * const rt5645_mono_adc_l2_src[] = { 1367 "Mono DAC MIXL", "DMIC" 1368 }; 1369 1370 static SOC_ENUM_SINGLE_DECL( 1371 rt5645_mono_adc_l2_enum, RT5645_MONO_ADC_MIXER, 1372 RT5645_MONO_ADC_L2_SRC_SFT, rt5645_mono_adc_l2_src); 1373 1374 static const struct snd_kcontrol_new rt5645_mono_adc_l2_mux = 1375 SOC_DAPM_ENUM("Mono ADC2 left source", rt5645_mono_adc_l2_enum); 1376 1377 /* MX-28 [8] */ 1378 static const char * const rt5645_mono_dmic_src[] = { 1379 "DMIC1", "DMIC2" 1380 }; 1381 1382 static SOC_ENUM_SINGLE_DECL( 1383 rt5645_mono_dmic_l_enum, RT5645_MONO_ADC_MIXER, 1384 RT5645_MONO_DMIC_L_SRC_SFT, rt5645_mono_dmic_src); 1385 1386 static const struct snd_kcontrol_new rt5645_mono_dmic_l_mux = 1387 SOC_DAPM_ENUM("Mono DMIC left source", rt5645_mono_dmic_l_enum); 1388 /* MX-28 [1:0] */ 1389 static SOC_ENUM_SINGLE_DECL( 1390 rt5645_mono_dmic_r_enum, RT5645_MONO_ADC_MIXER, 1391 RT5645_MONO_DMIC_R_SRC_SFT, rt5645_mono_dmic_src); 1392 1393 static const struct snd_kcontrol_new rt5645_mono_dmic_r_mux = 1394 SOC_DAPM_ENUM("Mono DMIC Right source", rt5645_mono_dmic_r_enum); 1395 /* MX-28 [4] */ 1396 static const char * const rt5645_mono_adc_r1_src[] = { 1397 "Mono DAC MIXR", "ADC" 1398 }; 1399 1400 static SOC_ENUM_SINGLE_DECL( 1401 rt5645_mono_adc_r1_enum, RT5645_MONO_ADC_MIXER, 1402 RT5645_MONO_ADC_R1_SRC_SFT, rt5645_mono_adc_r1_src); 1403 1404 static const struct snd_kcontrol_new rt5645_mono_adc_r1_mux = 1405 SOC_DAPM_ENUM("Mono ADC1 right source", rt5645_mono_adc_r1_enum); 1406 /* MX-28 [3] */ 1407 static const char * const rt5645_mono_adc_r2_src[] = { 1408 "Mono DAC MIXR", "DMIC" 1409 }; 1410 1411 static SOC_ENUM_SINGLE_DECL( 1412 rt5645_mono_adc_r2_enum, RT5645_MONO_ADC_MIXER, 1413 RT5645_MONO_ADC_R2_SRC_SFT, rt5645_mono_adc_r2_src); 1414 1415 static const struct snd_kcontrol_new rt5645_mono_adc_r2_mux = 1416 SOC_DAPM_ENUM("Mono ADC2 right source", rt5645_mono_adc_r2_enum); 1417 1418 /* MX-77 [9:8] */ 1419 static const char * const rt5645_if1_adc_in_src[] = { 1420 "IF_ADC1/IF_ADC2/VAD_ADC", "IF_ADC2/IF_ADC1/VAD_ADC", 1421 "VAD_ADC/IF_ADC1/IF_ADC2", "VAD_ADC/IF_ADC2/IF_ADC1" 1422 }; 1423 1424 static SOC_ENUM_SINGLE_DECL( 1425 rt5645_if1_adc_in_enum, RT5645_TDM_CTRL_1, 1426 RT5645_IF1_ADC_IN_SFT, rt5645_if1_adc_in_src); 1427 1428 static const struct snd_kcontrol_new rt5645_if1_adc_in_mux = 1429 SOC_DAPM_ENUM("IF1 ADC IN source", rt5645_if1_adc_in_enum); 1430 1431 /* MX-78 [4:0] */ 1432 static const char * const rt5650_if1_adc_in_src[] = { 1433 "IF_ADC1/IF_ADC2/DAC_REF/Null", 1434 "IF_ADC1/IF_ADC2/Null/DAC_REF", 1435 "IF_ADC1/DAC_REF/IF_ADC2/Null", 1436 "IF_ADC1/DAC_REF/Null/IF_ADC2", 1437 "IF_ADC1/Null/DAC_REF/IF_ADC2", 1438 "IF_ADC1/Null/IF_ADC2/DAC_REF", 1439 1440 "IF_ADC2/IF_ADC1/DAC_REF/Null", 1441 "IF_ADC2/IF_ADC1/Null/DAC_REF", 1442 "IF_ADC2/DAC_REF/IF_ADC1/Null", 1443 "IF_ADC2/DAC_REF/Null/IF_ADC1", 1444 "IF_ADC2/Null/DAC_REF/IF_ADC1", 1445 "IF_ADC2/Null/IF_ADC1/DAC_REF", 1446 1447 "DAC_REF/IF_ADC1/IF_ADC2/Null", 1448 "DAC_REF/IF_ADC1/Null/IF_ADC2", 1449 "DAC_REF/IF_ADC2/IF_ADC1/Null", 1450 "DAC_REF/IF_ADC2/Null/IF_ADC1", 1451 "DAC_REF/Null/IF_ADC1/IF_ADC2", 1452 "DAC_REF/Null/IF_ADC2/IF_ADC1", 1453 1454 "Null/IF_ADC1/IF_ADC2/DAC_REF", 1455 "Null/IF_ADC1/DAC_REF/IF_ADC2", 1456 "Null/IF_ADC2/IF_ADC1/DAC_REF", 1457 "Null/IF_ADC2/DAC_REF/IF_ADC1", 1458 "Null/DAC_REF/IF_ADC1/IF_ADC2", 1459 "Null/DAC_REF/IF_ADC2/IF_ADC1", 1460 }; 1461 1462 static SOC_ENUM_SINGLE_DECL( 1463 rt5650_if1_adc_in_enum, RT5645_TDM_CTRL_2, 1464 0, rt5650_if1_adc_in_src); 1465 1466 static const struct snd_kcontrol_new rt5650_if1_adc_in_mux = 1467 SOC_DAPM_ENUM("IF1 ADC IN source", rt5650_if1_adc_in_enum); 1468 1469 /* MX-78 [15:14][13:12][11:10] */ 1470 static const char * const rt5645_tdm_adc_swap_select[] = { 1471 "L/R", "R/L", "L/L", "R/R" 1472 }; 1473 1474 static SOC_ENUM_SINGLE_DECL(rt5650_tdm_adc_slot0_1_enum, 1475 RT5645_TDM_CTRL_2, 14, rt5645_tdm_adc_swap_select); 1476 1477 static const struct snd_kcontrol_new rt5650_if1_adc1_in_mux = 1478 SOC_DAPM_ENUM("IF1 ADC1 IN source", rt5650_tdm_adc_slot0_1_enum); 1479 1480 static SOC_ENUM_SINGLE_DECL(rt5650_tdm_adc_slot2_3_enum, 1481 RT5645_TDM_CTRL_2, 12, rt5645_tdm_adc_swap_select); 1482 1483 static const struct snd_kcontrol_new rt5650_if1_adc2_in_mux = 1484 SOC_DAPM_ENUM("IF1 ADC2 IN source", rt5650_tdm_adc_slot2_3_enum); 1485 1486 static SOC_ENUM_SINGLE_DECL(rt5650_tdm_adc_slot4_5_enum, 1487 RT5645_TDM_CTRL_2, 10, rt5645_tdm_adc_swap_select); 1488 1489 static const struct snd_kcontrol_new rt5650_if1_adc3_in_mux = 1490 SOC_DAPM_ENUM("IF1 ADC3 IN source", rt5650_tdm_adc_slot4_5_enum); 1491 1492 /* MX-77 [7:6][5:4][3:2] */ 1493 static SOC_ENUM_SINGLE_DECL(rt5645_tdm_adc_slot0_1_enum, 1494 RT5645_TDM_CTRL_1, 6, rt5645_tdm_adc_swap_select); 1495 1496 static const struct snd_kcontrol_new rt5645_if1_adc1_in_mux = 1497 SOC_DAPM_ENUM("IF1 ADC1 IN source", rt5645_tdm_adc_slot0_1_enum); 1498 1499 static SOC_ENUM_SINGLE_DECL(rt5645_tdm_adc_slot2_3_enum, 1500 RT5645_TDM_CTRL_1, 4, rt5645_tdm_adc_swap_select); 1501 1502 static const struct snd_kcontrol_new rt5645_if1_adc2_in_mux = 1503 SOC_DAPM_ENUM("IF1 ADC2 IN source", rt5645_tdm_adc_slot2_3_enum); 1504 1505 static SOC_ENUM_SINGLE_DECL(rt5645_tdm_adc_slot4_5_enum, 1506 RT5645_TDM_CTRL_1, 2, rt5645_tdm_adc_swap_select); 1507 1508 static const struct snd_kcontrol_new rt5645_if1_adc3_in_mux = 1509 SOC_DAPM_ENUM("IF1 ADC3 IN source", rt5645_tdm_adc_slot4_5_enum); 1510 1511 /* MX-79 [14:12][10:8][6:4][2:0] */ 1512 static const char * const rt5645_tdm_dac_swap_select[] = { 1513 "Slot0", "Slot1", "Slot2", "Slot3" 1514 }; 1515 1516 static SOC_ENUM_SINGLE_DECL(rt5645_tdm_dac0_enum, 1517 RT5645_TDM_CTRL_3, 12, rt5645_tdm_dac_swap_select); 1518 1519 static const struct snd_kcontrol_new rt5645_if1_dac0_tdm_sel_mux = 1520 SOC_DAPM_ENUM("IF1 DAC0 source", rt5645_tdm_dac0_enum); 1521 1522 static SOC_ENUM_SINGLE_DECL(rt5645_tdm_dac1_enum, 1523 RT5645_TDM_CTRL_3, 8, rt5645_tdm_dac_swap_select); 1524 1525 static const struct snd_kcontrol_new rt5645_if1_dac1_tdm_sel_mux = 1526 SOC_DAPM_ENUM("IF1 DAC1 source", rt5645_tdm_dac1_enum); 1527 1528 static SOC_ENUM_SINGLE_DECL(rt5645_tdm_dac2_enum, 1529 RT5645_TDM_CTRL_3, 4, rt5645_tdm_dac_swap_select); 1530 1531 static const struct snd_kcontrol_new rt5645_if1_dac2_tdm_sel_mux = 1532 SOC_DAPM_ENUM("IF1 DAC2 source", rt5645_tdm_dac2_enum); 1533 1534 static SOC_ENUM_SINGLE_DECL(rt5645_tdm_dac3_enum, 1535 RT5645_TDM_CTRL_3, 0, rt5645_tdm_dac_swap_select); 1536 1537 static const struct snd_kcontrol_new rt5645_if1_dac3_tdm_sel_mux = 1538 SOC_DAPM_ENUM("IF1 DAC3 source", rt5645_tdm_dac3_enum); 1539 1540 /* MX-7a [14:12][10:8][6:4][2:0] */ 1541 static SOC_ENUM_SINGLE_DECL(rt5650_tdm_dac0_enum, 1542 RT5650_TDM_CTRL_4, 12, rt5645_tdm_dac_swap_select); 1543 1544 static const struct snd_kcontrol_new rt5650_if1_dac0_tdm_sel_mux = 1545 SOC_DAPM_ENUM("IF1 DAC0 source", rt5650_tdm_dac0_enum); 1546 1547 static SOC_ENUM_SINGLE_DECL(rt5650_tdm_dac1_enum, 1548 RT5650_TDM_CTRL_4, 8, rt5645_tdm_dac_swap_select); 1549 1550 static const struct snd_kcontrol_new rt5650_if1_dac1_tdm_sel_mux = 1551 SOC_DAPM_ENUM("IF1 DAC1 source", rt5650_tdm_dac1_enum); 1552 1553 static SOC_ENUM_SINGLE_DECL(rt5650_tdm_dac2_enum, 1554 RT5650_TDM_CTRL_4, 4, rt5645_tdm_dac_swap_select); 1555 1556 static const struct snd_kcontrol_new rt5650_if1_dac2_tdm_sel_mux = 1557 SOC_DAPM_ENUM("IF1 DAC2 source", rt5650_tdm_dac2_enum); 1558 1559 static SOC_ENUM_SINGLE_DECL(rt5650_tdm_dac3_enum, 1560 RT5650_TDM_CTRL_4, 0, rt5645_tdm_dac_swap_select); 1561 1562 static const struct snd_kcontrol_new rt5650_if1_dac3_tdm_sel_mux = 1563 SOC_DAPM_ENUM("IF1 DAC3 source", rt5650_tdm_dac3_enum); 1564 1565 /* MX-2d [3] [2] */ 1566 static const char * const rt5650_a_dac1_src[] = { 1567 "DAC1", "Stereo DAC Mixer" 1568 }; 1569 1570 static SOC_ENUM_SINGLE_DECL( 1571 rt5650_a_dac1_l_enum, RT5650_A_DAC_SOUR, 1572 RT5650_A_DAC1_L_IN_SFT, rt5650_a_dac1_src); 1573 1574 static const struct snd_kcontrol_new rt5650_a_dac1_l_mux = 1575 SOC_DAPM_ENUM("A DAC1 L source", rt5650_a_dac1_l_enum); 1576 1577 static SOC_ENUM_SINGLE_DECL( 1578 rt5650_a_dac1_r_enum, RT5650_A_DAC_SOUR, 1579 RT5650_A_DAC1_R_IN_SFT, rt5650_a_dac1_src); 1580 1581 static const struct snd_kcontrol_new rt5650_a_dac1_r_mux = 1582 SOC_DAPM_ENUM("A DAC1 R source", rt5650_a_dac1_r_enum); 1583 1584 /* MX-2d [1] [0] */ 1585 static const char * const rt5650_a_dac2_src[] = { 1586 "Stereo DAC Mixer", "Mono DAC Mixer" 1587 }; 1588 1589 static SOC_ENUM_SINGLE_DECL( 1590 rt5650_a_dac2_l_enum, RT5650_A_DAC_SOUR, 1591 RT5650_A_DAC2_L_IN_SFT, rt5650_a_dac2_src); 1592 1593 static const struct snd_kcontrol_new rt5650_a_dac2_l_mux = 1594 SOC_DAPM_ENUM("A DAC2 L source", rt5650_a_dac2_l_enum); 1595 1596 static SOC_ENUM_SINGLE_DECL( 1597 rt5650_a_dac2_r_enum, RT5650_A_DAC_SOUR, 1598 RT5650_A_DAC2_R_IN_SFT, rt5650_a_dac2_src); 1599 1600 static const struct snd_kcontrol_new rt5650_a_dac2_r_mux = 1601 SOC_DAPM_ENUM("A DAC2 R source", rt5650_a_dac2_r_enum); 1602 1603 /* MX-2F [13:12] */ 1604 static const char * const rt5645_if2_adc_in_src[] = { 1605 "IF_ADC1", "IF_ADC2", "VAD_ADC" 1606 }; 1607 1608 static SOC_ENUM_SINGLE_DECL( 1609 rt5645_if2_adc_in_enum, RT5645_DIG_INF1_DATA, 1610 RT5645_IF2_ADC_IN_SFT, rt5645_if2_adc_in_src); 1611 1612 static const struct snd_kcontrol_new rt5645_if2_adc_in_mux = 1613 SOC_DAPM_ENUM("IF2 ADC IN source", rt5645_if2_adc_in_enum); 1614 1615 /* MX-31 [15] [13] [11] [9] */ 1616 static const char * const rt5645_pdm_src[] = { 1617 "Mono DAC", "Stereo DAC" 1618 }; 1619 1620 static SOC_ENUM_SINGLE_DECL( 1621 rt5645_pdm1_l_enum, RT5645_PDM_OUT_CTRL, 1622 RT5645_PDM1_L_SFT, rt5645_pdm_src); 1623 1624 static const struct snd_kcontrol_new rt5645_pdm1_l_mux = 1625 SOC_DAPM_ENUM("PDM1 L source", rt5645_pdm1_l_enum); 1626 1627 static SOC_ENUM_SINGLE_DECL( 1628 rt5645_pdm1_r_enum, RT5645_PDM_OUT_CTRL, 1629 RT5645_PDM1_R_SFT, rt5645_pdm_src); 1630 1631 static const struct snd_kcontrol_new rt5645_pdm1_r_mux = 1632 SOC_DAPM_ENUM("PDM1 R source", rt5645_pdm1_r_enum); 1633 1634 /* MX-9D [9:8] */ 1635 static const char * const rt5645_vad_adc_src[] = { 1636 "Sto1 ADC L", "Mono ADC L", "Mono ADC R" 1637 }; 1638 1639 static SOC_ENUM_SINGLE_DECL( 1640 rt5645_vad_adc_enum, RT5645_VAD_CTRL4, 1641 RT5645_VAD_SEL_SFT, rt5645_vad_adc_src); 1642 1643 static const struct snd_kcontrol_new rt5645_vad_adc_mux = 1644 SOC_DAPM_ENUM("VAD ADC source", rt5645_vad_adc_enum); 1645 1646 static const struct snd_kcontrol_new spk_l_vol_control = 1647 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_SPK_VOL, 1648 RT5645_L_MUTE_SFT, 1, 1); 1649 1650 static const struct snd_kcontrol_new spk_r_vol_control = 1651 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_SPK_VOL, 1652 RT5645_R_MUTE_SFT, 1, 1); 1653 1654 static const struct snd_kcontrol_new hp_l_vol_control = 1655 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_HP_VOL, 1656 RT5645_L_MUTE_SFT, 1, 1); 1657 1658 static const struct snd_kcontrol_new hp_r_vol_control = 1659 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_HP_VOL, 1660 RT5645_R_MUTE_SFT, 1, 1); 1661 1662 static const struct snd_kcontrol_new pdm1_l_vol_control = 1663 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_PDM_OUT_CTRL, 1664 RT5645_M_PDM1_L, 1, 1); 1665 1666 static const struct snd_kcontrol_new pdm1_r_vol_control = 1667 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_PDM_OUT_CTRL, 1668 RT5645_M_PDM1_R, 1, 1); 1669 1670 static void hp_amp_power(struct snd_soc_component *component, int on) 1671 { 1672 static int hp_amp_power_count; 1673 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component); 1674 int i, val; 1675 1676 if (on) { 1677 if (hp_amp_power_count <= 0) { 1678 if (rt5645->codec_type == CODEC_TYPE_RT5650) { 1679 snd_soc_component_write(component, RT5645_DEPOP_M2, 0x3100); 1680 snd_soc_component_write(component, RT5645_CHARGE_PUMP, 1681 0x0e06); 1682 snd_soc_component_write(component, RT5645_DEPOP_M1, 0x000d); 1683 regmap_write(rt5645->regmap, RT5645_PR_BASE + 1684 RT5645_HP_DCC_INT1, 0x9f01); 1685 for (i = 0; i < 20; i++) { 1686 usleep_range(1000, 1500); 1687 regmap_read(rt5645->regmap, RT5645_PR_BASE + 1688 RT5645_HP_DCC_INT1, &val); 1689 if (!(val & 0x8000)) 1690 break; 1691 } 1692 snd_soc_component_update_bits(component, RT5645_DEPOP_M1, 1693 RT5645_HP_CO_MASK, RT5645_HP_CO_EN); 1694 regmap_write(rt5645->regmap, RT5645_PR_BASE + 1695 0x3e, 0x7400); 1696 snd_soc_component_write(component, RT5645_DEPOP_M3, 0x0737); 1697 regmap_write(rt5645->regmap, RT5645_PR_BASE + 1698 RT5645_MAMP_INT_REG2, 0xfc00); 1699 snd_soc_component_write(component, RT5645_DEPOP_M2, 0x1140); 1700 snd_soc_component_update_bits(component, RT5645_PWR_ANLG1, 1701 RT5645_PWR_HP_L | RT5645_PWR_HP_R, 1702 RT5645_PWR_HP_L | RT5645_PWR_HP_R); 1703 msleep(90); 1704 } else { 1705 /* depop parameters */ 1706 snd_soc_component_update_bits(component, RT5645_DEPOP_M2, 1707 RT5645_DEPOP_MASK, RT5645_DEPOP_MAN); 1708 snd_soc_component_write(component, RT5645_DEPOP_M1, 0x000d); 1709 regmap_write(rt5645->regmap, RT5645_PR_BASE + 1710 RT5645_HP_DCC_INT1, 0x9f01); 1711 mdelay(150); 1712 /* headphone amp power on */ 1713 snd_soc_component_update_bits(component, RT5645_PWR_ANLG1, 1714 RT5645_PWR_FV1 | RT5645_PWR_FV2, 0); 1715 snd_soc_component_update_bits(component, RT5645_PWR_VOL, 1716 RT5645_PWR_HV_L | RT5645_PWR_HV_R, 1717 RT5645_PWR_HV_L | RT5645_PWR_HV_R); 1718 snd_soc_component_update_bits(component, RT5645_PWR_ANLG1, 1719 RT5645_PWR_HP_L | RT5645_PWR_HP_R | 1720 RT5645_PWR_HA, 1721 RT5645_PWR_HP_L | RT5645_PWR_HP_R | 1722 RT5645_PWR_HA); 1723 mdelay(5); 1724 snd_soc_component_update_bits(component, RT5645_PWR_ANLG1, 1725 RT5645_PWR_FV1 | RT5645_PWR_FV2, 1726 RT5645_PWR_FV1 | RT5645_PWR_FV2); 1727 1728 snd_soc_component_update_bits(component, RT5645_DEPOP_M1, 1729 RT5645_HP_CO_MASK | RT5645_HP_SG_MASK, 1730 RT5645_HP_CO_EN | RT5645_HP_SG_EN); 1731 regmap_write(rt5645->regmap, RT5645_PR_BASE + 1732 0x14, 0x1aaa); 1733 regmap_write(rt5645->regmap, RT5645_PR_BASE + 1734 0x24, 0x0430); 1735 } 1736 } 1737 hp_amp_power_count++; 1738 } else { 1739 hp_amp_power_count--; 1740 if (hp_amp_power_count <= 0) { 1741 if (rt5645->codec_type == CODEC_TYPE_RT5650) { 1742 regmap_write(rt5645->regmap, RT5645_PR_BASE + 1743 0x3e, 0x7400); 1744 snd_soc_component_write(component, RT5645_DEPOP_M3, 0x0737); 1745 regmap_write(rt5645->regmap, RT5645_PR_BASE + 1746 RT5645_MAMP_INT_REG2, 0xfc00); 1747 snd_soc_component_write(component, RT5645_DEPOP_M2, 0x1140); 1748 msleep(100); 1749 snd_soc_component_write(component, RT5645_DEPOP_M1, 0x0001); 1750 snd_soc_component_update_bits(component, RT5645_PWR_ANLG1, 1751 RT5645_PWR_HP_L | RT5645_PWR_HP_R, 0); 1752 } else { 1753 snd_soc_component_update_bits(component, RT5645_DEPOP_M1, 1754 RT5645_HP_SG_MASK | 1755 RT5645_HP_L_SMT_MASK | 1756 RT5645_HP_R_SMT_MASK, 1757 RT5645_HP_SG_DIS | 1758 RT5645_HP_L_SMT_DIS | 1759 RT5645_HP_R_SMT_DIS); 1760 /* headphone amp power down */ 1761 snd_soc_component_write(component, RT5645_DEPOP_M1, 0x0000); 1762 snd_soc_component_update_bits(component, RT5645_PWR_ANLG1, 1763 RT5645_PWR_HP_L | RT5645_PWR_HP_R | 1764 RT5645_PWR_HA, 0); 1765 snd_soc_component_update_bits(component, RT5645_DEPOP_M2, 1766 RT5645_DEPOP_MASK, 0); 1767 } 1768 } 1769 } 1770 } 1771 1772 static int rt5645_hp_event(struct snd_soc_dapm_widget *w, 1773 struct snd_kcontrol *kcontrol, int event) 1774 { 1775 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1776 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component); 1777 1778 switch (event) { 1779 case SND_SOC_DAPM_POST_PMU: 1780 hp_amp_power(component, 1); 1781 /* headphone unmute sequence */ 1782 if (rt5645->codec_type == CODEC_TYPE_RT5645) { 1783 snd_soc_component_update_bits(component, RT5645_DEPOP_M3, 1784 RT5645_CP_FQ1_MASK | RT5645_CP_FQ2_MASK | 1785 RT5645_CP_FQ3_MASK, 1786 (RT5645_CP_FQ_192_KHZ << RT5645_CP_FQ1_SFT) | 1787 (RT5645_CP_FQ_12_KHZ << RT5645_CP_FQ2_SFT) | 1788 (RT5645_CP_FQ_192_KHZ << RT5645_CP_FQ3_SFT)); 1789 regmap_write(rt5645->regmap, RT5645_PR_BASE + 1790 RT5645_MAMP_INT_REG2, 0xfc00); 1791 snd_soc_component_update_bits(component, RT5645_DEPOP_M1, 1792 RT5645_SMT_TRIG_MASK, RT5645_SMT_TRIG_EN); 1793 snd_soc_component_update_bits(component, RT5645_DEPOP_M1, 1794 RT5645_RSTN_MASK, RT5645_RSTN_EN); 1795 snd_soc_component_update_bits(component, RT5645_DEPOP_M1, 1796 RT5645_RSTN_MASK | RT5645_HP_L_SMT_MASK | 1797 RT5645_HP_R_SMT_MASK, RT5645_RSTN_DIS | 1798 RT5645_HP_L_SMT_EN | RT5645_HP_R_SMT_EN); 1799 msleep(40); 1800 snd_soc_component_update_bits(component, RT5645_DEPOP_M1, 1801 RT5645_HP_SG_MASK | RT5645_HP_L_SMT_MASK | 1802 RT5645_HP_R_SMT_MASK, RT5645_HP_SG_DIS | 1803 RT5645_HP_L_SMT_DIS | RT5645_HP_R_SMT_DIS); 1804 } 1805 break; 1806 1807 case SND_SOC_DAPM_PRE_PMD: 1808 /* headphone mute sequence */ 1809 if (rt5645->codec_type == CODEC_TYPE_RT5645) { 1810 snd_soc_component_update_bits(component, RT5645_DEPOP_M3, 1811 RT5645_CP_FQ1_MASK | RT5645_CP_FQ2_MASK | 1812 RT5645_CP_FQ3_MASK, 1813 (RT5645_CP_FQ_96_KHZ << RT5645_CP_FQ1_SFT) | 1814 (RT5645_CP_FQ_12_KHZ << RT5645_CP_FQ2_SFT) | 1815 (RT5645_CP_FQ_96_KHZ << RT5645_CP_FQ3_SFT)); 1816 regmap_write(rt5645->regmap, RT5645_PR_BASE + 1817 RT5645_MAMP_INT_REG2, 0xfc00); 1818 snd_soc_component_update_bits(component, RT5645_DEPOP_M1, 1819 RT5645_HP_SG_MASK, RT5645_HP_SG_EN); 1820 snd_soc_component_update_bits(component, RT5645_DEPOP_M1, 1821 RT5645_RSTP_MASK, RT5645_RSTP_EN); 1822 snd_soc_component_update_bits(component, RT5645_DEPOP_M1, 1823 RT5645_RSTP_MASK | RT5645_HP_L_SMT_MASK | 1824 RT5645_HP_R_SMT_MASK, RT5645_RSTP_DIS | 1825 RT5645_HP_L_SMT_EN | RT5645_HP_R_SMT_EN); 1826 msleep(30); 1827 } 1828 hp_amp_power(component, 0); 1829 break; 1830 1831 default: 1832 return 0; 1833 } 1834 1835 return 0; 1836 } 1837 1838 static int rt5645_spk_event(struct snd_soc_dapm_widget *w, 1839 struct snd_kcontrol *kcontrol, int event) 1840 { 1841 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1842 1843 switch (event) { 1844 case SND_SOC_DAPM_POST_PMU: 1845 rt5645_enable_hweq(component); 1846 snd_soc_component_update_bits(component, RT5645_PWR_DIG1, 1847 RT5645_PWR_CLS_D | RT5645_PWR_CLS_D_R | 1848 RT5645_PWR_CLS_D_L, 1849 RT5645_PWR_CLS_D | RT5645_PWR_CLS_D_R | 1850 RT5645_PWR_CLS_D_L); 1851 snd_soc_component_update_bits(component, RT5645_GEN_CTRL3, 1852 RT5645_DET_CLK_MASK, RT5645_DET_CLK_MODE1); 1853 break; 1854 1855 case SND_SOC_DAPM_PRE_PMD: 1856 snd_soc_component_update_bits(component, RT5645_GEN_CTRL3, 1857 RT5645_DET_CLK_MASK, RT5645_DET_CLK_DIS); 1858 snd_soc_component_write(component, RT5645_EQ_CTRL2, 0); 1859 snd_soc_component_update_bits(component, RT5645_PWR_DIG1, 1860 RT5645_PWR_CLS_D | RT5645_PWR_CLS_D_R | 1861 RT5645_PWR_CLS_D_L, 0); 1862 break; 1863 1864 default: 1865 return 0; 1866 } 1867 1868 return 0; 1869 } 1870 1871 static int rt5645_lout_event(struct snd_soc_dapm_widget *w, 1872 struct snd_kcontrol *kcontrol, int event) 1873 { 1874 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1875 1876 switch (event) { 1877 case SND_SOC_DAPM_POST_PMU: 1878 hp_amp_power(component, 1); 1879 snd_soc_component_update_bits(component, RT5645_PWR_ANLG1, 1880 RT5645_PWR_LM, RT5645_PWR_LM); 1881 snd_soc_component_update_bits(component, RT5645_LOUT1, 1882 RT5645_L_MUTE | RT5645_R_MUTE, 0); 1883 break; 1884 1885 case SND_SOC_DAPM_PRE_PMD: 1886 snd_soc_component_update_bits(component, RT5645_LOUT1, 1887 RT5645_L_MUTE | RT5645_R_MUTE, 1888 RT5645_L_MUTE | RT5645_R_MUTE); 1889 snd_soc_component_update_bits(component, RT5645_PWR_ANLG1, 1890 RT5645_PWR_LM, 0); 1891 hp_amp_power(component, 0); 1892 break; 1893 1894 default: 1895 return 0; 1896 } 1897 1898 return 0; 1899 } 1900 1901 static int rt5645_bst2_event(struct snd_soc_dapm_widget *w, 1902 struct snd_kcontrol *kcontrol, int event) 1903 { 1904 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1905 1906 switch (event) { 1907 case SND_SOC_DAPM_POST_PMU: 1908 snd_soc_component_update_bits(component, RT5645_PWR_ANLG2, 1909 RT5645_PWR_BST2_P, RT5645_PWR_BST2_P); 1910 break; 1911 1912 case SND_SOC_DAPM_PRE_PMD: 1913 snd_soc_component_update_bits(component, RT5645_PWR_ANLG2, 1914 RT5645_PWR_BST2_P, 0); 1915 break; 1916 1917 default: 1918 return 0; 1919 } 1920 1921 return 0; 1922 } 1923 1924 static int rt5645_set_micbias1_event(struct snd_soc_dapm_widget *w, 1925 struct snd_kcontrol *k, int event) 1926 { 1927 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1928 1929 switch (event) { 1930 case SND_SOC_DAPM_PRE_PMU: 1931 snd_soc_component_update_bits(component, RT5645_GEN_CTRL2, 1932 RT5645_MICBIAS1_POW_CTRL_SEL_MASK, 1933 RT5645_MICBIAS1_POW_CTRL_SEL_M); 1934 break; 1935 1936 case SND_SOC_DAPM_POST_PMD: 1937 snd_soc_component_update_bits(component, RT5645_GEN_CTRL2, 1938 RT5645_MICBIAS1_POW_CTRL_SEL_MASK, 1939 RT5645_MICBIAS1_POW_CTRL_SEL_A); 1940 break; 1941 1942 default: 1943 return 0; 1944 } 1945 1946 return 0; 1947 } 1948 1949 static int rt5645_set_micbias2_event(struct snd_soc_dapm_widget *w, 1950 struct snd_kcontrol *k, int event) 1951 { 1952 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1953 1954 switch (event) { 1955 case SND_SOC_DAPM_PRE_PMU: 1956 snd_soc_component_update_bits(component, RT5645_GEN_CTRL2, 1957 RT5645_MICBIAS2_POW_CTRL_SEL_MASK, 1958 RT5645_MICBIAS2_POW_CTRL_SEL_M); 1959 break; 1960 1961 case SND_SOC_DAPM_POST_PMD: 1962 snd_soc_component_update_bits(component, RT5645_GEN_CTRL2, 1963 RT5645_MICBIAS2_POW_CTRL_SEL_MASK, 1964 RT5645_MICBIAS2_POW_CTRL_SEL_A); 1965 break; 1966 1967 default: 1968 return 0; 1969 } 1970 1971 return 0; 1972 } 1973 1974 static const struct snd_soc_dapm_widget rt5645_dapm_widgets[] = { 1975 SND_SOC_DAPM_SUPPLY("LDO2", RT5645_PWR_MIXER, 1976 RT5645_PWR_LDO2_BIT, 0, NULL, 0), 1977 SND_SOC_DAPM_SUPPLY("PLL1", RT5645_PWR_ANLG2, 1978 RT5645_PWR_PLL_BIT, 0, NULL, 0), 1979 1980 SND_SOC_DAPM_SUPPLY("JD Power", RT5645_PWR_ANLG2, 1981 RT5645_PWR_JD1_BIT, 0, NULL, 0), 1982 SND_SOC_DAPM_SUPPLY("Mic Det Power", RT5645_PWR_VOL, 1983 RT5645_PWR_MIC_DET_BIT, 0, NULL, 0), 1984 1985 /* ASRC */ 1986 SND_SOC_DAPM_SUPPLY_S("I2S1 ASRC", 1, RT5645_ASRC_1, 1987 11, 0, NULL, 0), 1988 SND_SOC_DAPM_SUPPLY_S("I2S2 ASRC", 1, RT5645_ASRC_1, 1989 12, 0, NULL, 0), 1990 SND_SOC_DAPM_SUPPLY_S("DAC STO ASRC", 1, RT5645_ASRC_1, 1991 10, 0, NULL, 0), 1992 SND_SOC_DAPM_SUPPLY_S("DAC MONO L ASRC", 1, RT5645_ASRC_1, 1993 9, 0, NULL, 0), 1994 SND_SOC_DAPM_SUPPLY_S("DAC MONO R ASRC", 1, RT5645_ASRC_1, 1995 8, 0, NULL, 0), 1996 SND_SOC_DAPM_SUPPLY_S("DMIC STO1 ASRC", 1, RT5645_ASRC_1, 1997 7, 0, NULL, 0), 1998 SND_SOC_DAPM_SUPPLY_S("DMIC MONO L ASRC", 1, RT5645_ASRC_1, 1999 5, 0, NULL, 0), 2000 SND_SOC_DAPM_SUPPLY_S("DMIC MONO R ASRC", 1, RT5645_ASRC_1, 2001 4, 0, NULL, 0), 2002 SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5645_ASRC_1, 2003 3, 0, NULL, 0), 2004 SND_SOC_DAPM_SUPPLY_S("ADC MONO L ASRC", 1, RT5645_ASRC_1, 2005 1, 0, NULL, 0), 2006 SND_SOC_DAPM_SUPPLY_S("ADC MONO R ASRC", 1, RT5645_ASRC_1, 2007 0, 0, NULL, 0), 2008 2009 /* Input Side */ 2010 /* micbias */ 2011 SND_SOC_DAPM_SUPPLY("micbias1", RT5645_PWR_ANLG2, 2012 RT5645_PWR_MB1_BIT, 0, rt5645_set_micbias1_event, 2013 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2014 SND_SOC_DAPM_SUPPLY("micbias2", RT5645_PWR_ANLG2, 2015 RT5645_PWR_MB2_BIT, 0, rt5645_set_micbias2_event, 2016 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2017 /* Input Lines */ 2018 SND_SOC_DAPM_INPUT("DMIC L1"), 2019 SND_SOC_DAPM_INPUT("DMIC R1"), 2020 SND_SOC_DAPM_INPUT("DMIC L2"), 2021 SND_SOC_DAPM_INPUT("DMIC R2"), 2022 2023 SND_SOC_DAPM_INPUT("IN1P"), 2024 SND_SOC_DAPM_INPUT("IN1N"), 2025 SND_SOC_DAPM_INPUT("IN2P"), 2026 SND_SOC_DAPM_INPUT("IN2N"), 2027 2028 SND_SOC_DAPM_INPUT("Haptic Generator"), 2029 2030 SND_SOC_DAPM_PGA("DMIC1", SND_SOC_NOPM, 0, 0, NULL, 0), 2031 SND_SOC_DAPM_PGA("DMIC2", SND_SOC_NOPM, 0, 0, NULL, 0), 2032 SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0, 2033 set_dmic_clk, SND_SOC_DAPM_PRE_PMU), 2034 SND_SOC_DAPM_SUPPLY("DMIC1 Power", RT5645_DMIC_CTRL1, 2035 RT5645_DMIC_1_EN_SFT, 0, NULL, 0), 2036 SND_SOC_DAPM_SUPPLY("DMIC2 Power", RT5645_DMIC_CTRL1, 2037 RT5645_DMIC_2_EN_SFT, 0, NULL, 0), 2038 /* Boost */ 2039 SND_SOC_DAPM_PGA("BST1", RT5645_PWR_ANLG2, 2040 RT5645_PWR_BST1_BIT, 0, NULL, 0), 2041 SND_SOC_DAPM_PGA_E("BST2", RT5645_PWR_ANLG2, 2042 RT5645_PWR_BST2_BIT, 0, NULL, 0, rt5645_bst2_event, 2043 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU), 2044 /* Input Volume */ 2045 SND_SOC_DAPM_PGA("INL VOL", RT5645_PWR_VOL, 2046 RT5645_PWR_IN_L_BIT, 0, NULL, 0), 2047 SND_SOC_DAPM_PGA("INR VOL", RT5645_PWR_VOL, 2048 RT5645_PWR_IN_R_BIT, 0, NULL, 0), 2049 /* REC Mixer */ 2050 SND_SOC_DAPM_MIXER("RECMIXL", RT5645_PWR_MIXER, RT5645_PWR_RM_L_BIT, 2051 0, rt5645_rec_l_mix, ARRAY_SIZE(rt5645_rec_l_mix)), 2052 SND_SOC_DAPM_MIXER("RECMIXR", RT5645_PWR_MIXER, RT5645_PWR_RM_R_BIT, 2053 0, rt5645_rec_r_mix, ARRAY_SIZE(rt5645_rec_r_mix)), 2054 /* ADCs */ 2055 SND_SOC_DAPM_ADC("ADC L", NULL, SND_SOC_NOPM, 0, 0), 2056 SND_SOC_DAPM_ADC("ADC R", NULL, SND_SOC_NOPM, 0, 0), 2057 2058 SND_SOC_DAPM_SUPPLY("ADC L power", RT5645_PWR_DIG1, 2059 RT5645_PWR_ADC_L_BIT, 0, NULL, 0), 2060 SND_SOC_DAPM_SUPPLY("ADC R power", RT5645_PWR_DIG1, 2061 RT5645_PWR_ADC_R_BIT, 0, NULL, 0), 2062 2063 /* ADC Mux */ 2064 SND_SOC_DAPM_MUX("Stereo1 DMIC Mux", SND_SOC_NOPM, 0, 0, 2065 &rt5645_sto1_dmic_mux), 2066 SND_SOC_DAPM_MUX("Stereo1 ADC L2 Mux", SND_SOC_NOPM, 0, 0, 2067 &rt5645_sto_adc2_mux), 2068 SND_SOC_DAPM_MUX("Stereo1 ADC R2 Mux", SND_SOC_NOPM, 0, 0, 2069 &rt5645_sto_adc2_mux), 2070 SND_SOC_DAPM_MUX("Stereo1 ADC L1 Mux", SND_SOC_NOPM, 0, 0, 2071 &rt5645_sto_adc1_mux), 2072 SND_SOC_DAPM_MUX("Stereo1 ADC R1 Mux", SND_SOC_NOPM, 0, 0, 2073 &rt5645_sto_adc1_mux), 2074 SND_SOC_DAPM_MUX("Mono DMIC L Mux", SND_SOC_NOPM, 0, 0, 2075 &rt5645_mono_dmic_l_mux), 2076 SND_SOC_DAPM_MUX("Mono DMIC R Mux", SND_SOC_NOPM, 0, 0, 2077 &rt5645_mono_dmic_r_mux), 2078 SND_SOC_DAPM_MUX("Mono ADC L2 Mux", SND_SOC_NOPM, 0, 0, 2079 &rt5645_mono_adc_l2_mux), 2080 SND_SOC_DAPM_MUX("Mono ADC L1 Mux", SND_SOC_NOPM, 0, 0, 2081 &rt5645_mono_adc_l1_mux), 2082 SND_SOC_DAPM_MUX("Mono ADC R1 Mux", SND_SOC_NOPM, 0, 0, 2083 &rt5645_mono_adc_r1_mux), 2084 SND_SOC_DAPM_MUX("Mono ADC R2 Mux", SND_SOC_NOPM, 0, 0, 2085 &rt5645_mono_adc_r2_mux), 2086 /* ADC Mixer */ 2087 2088 SND_SOC_DAPM_SUPPLY_S("adc stereo1 filter", 1, RT5645_PWR_DIG2, 2089 RT5645_PWR_ADC_S1F_BIT, 0, NULL, 0), 2090 SND_SOC_DAPM_MIXER_E("Sto1 ADC MIXL", SND_SOC_NOPM, 0, 0, 2091 rt5645_sto1_adc_l_mix, ARRAY_SIZE(rt5645_sto1_adc_l_mix), 2092 NULL, 0), 2093 SND_SOC_DAPM_MIXER_E("Sto1 ADC MIXR", SND_SOC_NOPM, 0, 0, 2094 rt5645_sto1_adc_r_mix, ARRAY_SIZE(rt5645_sto1_adc_r_mix), 2095 NULL, 0), 2096 SND_SOC_DAPM_SUPPLY_S("adc mono left filter", 1, RT5645_PWR_DIG2, 2097 RT5645_PWR_ADC_MF_L_BIT, 0, NULL, 0), 2098 SND_SOC_DAPM_MIXER_E("Mono ADC MIXL", SND_SOC_NOPM, 0, 0, 2099 rt5645_mono_adc_l_mix, ARRAY_SIZE(rt5645_mono_adc_l_mix), 2100 NULL, 0), 2101 SND_SOC_DAPM_SUPPLY_S("adc mono right filter", 1, RT5645_PWR_DIG2, 2102 RT5645_PWR_ADC_MF_R_BIT, 0, NULL, 0), 2103 SND_SOC_DAPM_MIXER_E("Mono ADC MIXR", SND_SOC_NOPM, 0, 0, 2104 rt5645_mono_adc_r_mix, ARRAY_SIZE(rt5645_mono_adc_r_mix), 2105 NULL, 0), 2106 2107 /* ADC PGA */ 2108 SND_SOC_DAPM_PGA("Stereo1 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0), 2109 SND_SOC_DAPM_PGA("Stereo1 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0), 2110 SND_SOC_DAPM_PGA("Sto2 ADC LR MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 2111 SND_SOC_DAPM_PGA("VAD_ADC", SND_SOC_NOPM, 0, 0, NULL, 0), 2112 SND_SOC_DAPM_PGA("IF_ADC1", SND_SOC_NOPM, 0, 0, NULL, 0), 2113 SND_SOC_DAPM_PGA("IF_ADC2", SND_SOC_NOPM, 0, 0, NULL, 0), 2114 SND_SOC_DAPM_PGA("IF1_ADC1", SND_SOC_NOPM, 0, 0, NULL, 0), 2115 SND_SOC_DAPM_PGA("IF1_ADC2", SND_SOC_NOPM, 0, 0, NULL, 0), 2116 SND_SOC_DAPM_PGA("IF1_ADC3", SND_SOC_NOPM, 0, 0, NULL, 0), 2117 SND_SOC_DAPM_PGA("IF1_ADC4", SND_SOC_NOPM, 0, 0, NULL, 0), 2118 2119 /* IF1 2 Mux */ 2120 SND_SOC_DAPM_MUX("IF2 ADC Mux", SND_SOC_NOPM, 2121 0, 0, &rt5645_if2_adc_in_mux), 2122 2123 /* Digital Interface */ 2124 SND_SOC_DAPM_SUPPLY("I2S1", RT5645_PWR_DIG1, 2125 RT5645_PWR_I2S1_BIT, 0, NULL, 0), 2126 SND_SOC_DAPM_PGA("IF1 DAC0", SND_SOC_NOPM, 0, 0, NULL, 0), 2127 SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0), 2128 SND_SOC_DAPM_PGA("IF1 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0), 2129 SND_SOC_DAPM_PGA("IF1 DAC3", SND_SOC_NOPM, 0, 0, NULL, 0), 2130 SND_SOC_DAPM_PGA("IF1 ADC", SND_SOC_NOPM, 0, 0, NULL, 0), 2131 SND_SOC_DAPM_PGA("IF1 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0), 2132 SND_SOC_DAPM_PGA("IF1 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0), 2133 SND_SOC_DAPM_SUPPLY("I2S2", RT5645_PWR_DIG1, 2134 RT5645_PWR_I2S2_BIT, 0, NULL, 0), 2135 SND_SOC_DAPM_PGA("IF2 DAC", SND_SOC_NOPM, 0, 0, NULL, 0), 2136 SND_SOC_DAPM_PGA("IF2 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0), 2137 SND_SOC_DAPM_PGA("IF2 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0), 2138 SND_SOC_DAPM_PGA("IF2 ADC", SND_SOC_NOPM, 0, 0, NULL, 0), 2139 2140 /* Digital Interface Select */ 2141 SND_SOC_DAPM_MUX("VAD ADC Mux", SND_SOC_NOPM, 2142 0, 0, &rt5645_vad_adc_mux), 2143 2144 /* Audio Interface */ 2145 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0), 2146 SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0), 2147 SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0), 2148 SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0), 2149 2150 /* Output Side */ 2151 /* DAC mixer before sound effect */ 2152 SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0, 2153 rt5645_dac_l_mix, ARRAY_SIZE(rt5645_dac_l_mix)), 2154 SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0, 2155 rt5645_dac_r_mix, ARRAY_SIZE(rt5645_dac_r_mix)), 2156 2157 /* DAC2 channel Mux */ 2158 SND_SOC_DAPM_MUX("DAC L2 Mux", SND_SOC_NOPM, 0, 0, &rt5645_dac_l2_mux), 2159 SND_SOC_DAPM_MUX("DAC R2 Mux", SND_SOC_NOPM, 0, 0, &rt5645_dac_r2_mux), 2160 SND_SOC_DAPM_PGA("DAC L2 Volume", RT5645_PWR_DIG1, 2161 RT5645_PWR_DAC_L2_BIT, 0, NULL, 0), 2162 SND_SOC_DAPM_PGA("DAC R2 Volume", RT5645_PWR_DIG1, 2163 RT5645_PWR_DAC_R2_BIT, 0, NULL, 0), 2164 2165 SND_SOC_DAPM_MUX("DAC1 L Mux", SND_SOC_NOPM, 0, 0, &rt5645_dac1l_mux), 2166 SND_SOC_DAPM_MUX("DAC1 R Mux", SND_SOC_NOPM, 0, 0, &rt5645_dac1r_mux), 2167 2168 /* DAC Mixer */ 2169 SND_SOC_DAPM_SUPPLY_S("dac stereo1 filter", 1, RT5645_PWR_DIG2, 2170 RT5645_PWR_DAC_S1F_BIT, 0, NULL, 0), 2171 SND_SOC_DAPM_SUPPLY_S("dac mono left filter", 1, RT5645_PWR_DIG2, 2172 RT5645_PWR_DAC_MF_L_BIT, 0, NULL, 0), 2173 SND_SOC_DAPM_SUPPLY_S("dac mono right filter", 1, RT5645_PWR_DIG2, 2174 RT5645_PWR_DAC_MF_R_BIT, 0, NULL, 0), 2175 SND_SOC_DAPM_MIXER("Stereo DAC MIXL", SND_SOC_NOPM, 0, 0, 2176 rt5645_sto_dac_l_mix, ARRAY_SIZE(rt5645_sto_dac_l_mix)), 2177 SND_SOC_DAPM_MIXER("Stereo DAC MIXR", SND_SOC_NOPM, 0, 0, 2178 rt5645_sto_dac_r_mix, ARRAY_SIZE(rt5645_sto_dac_r_mix)), 2179 SND_SOC_DAPM_MIXER("Mono DAC MIXL", SND_SOC_NOPM, 0, 0, 2180 rt5645_mono_dac_l_mix, ARRAY_SIZE(rt5645_mono_dac_l_mix)), 2181 SND_SOC_DAPM_MIXER("Mono DAC MIXR", SND_SOC_NOPM, 0, 0, 2182 rt5645_mono_dac_r_mix, ARRAY_SIZE(rt5645_mono_dac_r_mix)), 2183 SND_SOC_DAPM_MIXER("DAC MIXL", SND_SOC_NOPM, 0, 0, 2184 rt5645_dig_l_mix, ARRAY_SIZE(rt5645_dig_l_mix)), 2185 SND_SOC_DAPM_MIXER("DAC MIXR", SND_SOC_NOPM, 0, 0, 2186 rt5645_dig_r_mix, ARRAY_SIZE(rt5645_dig_r_mix)), 2187 2188 /* DACs */ 2189 SND_SOC_DAPM_DAC("DAC L1", NULL, RT5645_PWR_DIG1, RT5645_PWR_DAC_L1_BIT, 2190 0), 2191 SND_SOC_DAPM_DAC("DAC L2", NULL, RT5645_PWR_DIG1, RT5645_PWR_DAC_L2_BIT, 2192 0), 2193 SND_SOC_DAPM_DAC("DAC R1", NULL, RT5645_PWR_DIG1, RT5645_PWR_DAC_R1_BIT, 2194 0), 2195 SND_SOC_DAPM_DAC("DAC R2", NULL, RT5645_PWR_DIG1, RT5645_PWR_DAC_R2_BIT, 2196 0), 2197 /* OUT Mixer */ 2198 SND_SOC_DAPM_MIXER("SPK MIXL", RT5645_PWR_MIXER, RT5645_PWR_SM_L_BIT, 2199 0, rt5645_spk_l_mix, ARRAY_SIZE(rt5645_spk_l_mix)), 2200 SND_SOC_DAPM_MIXER("SPK MIXR", RT5645_PWR_MIXER, RT5645_PWR_SM_R_BIT, 2201 0, rt5645_spk_r_mix, ARRAY_SIZE(rt5645_spk_r_mix)), 2202 SND_SOC_DAPM_MIXER("OUT MIXL", RT5645_PWR_MIXER, RT5645_PWR_OM_L_BIT, 2203 0, rt5645_out_l_mix, ARRAY_SIZE(rt5645_out_l_mix)), 2204 SND_SOC_DAPM_MIXER("OUT MIXR", RT5645_PWR_MIXER, RT5645_PWR_OM_R_BIT, 2205 0, rt5645_out_r_mix, ARRAY_SIZE(rt5645_out_r_mix)), 2206 /* Ouput Volume */ 2207 SND_SOC_DAPM_SWITCH("SPKVOL L", RT5645_PWR_VOL, RT5645_PWR_SV_L_BIT, 0, 2208 &spk_l_vol_control), 2209 SND_SOC_DAPM_SWITCH("SPKVOL R", RT5645_PWR_VOL, RT5645_PWR_SV_R_BIT, 0, 2210 &spk_r_vol_control), 2211 SND_SOC_DAPM_MIXER("HPOVOL MIXL", RT5645_PWR_VOL, RT5645_PWR_HV_L_BIT, 2212 0, rt5645_hpvoll_mix, ARRAY_SIZE(rt5645_hpvoll_mix)), 2213 SND_SOC_DAPM_MIXER("HPOVOL MIXR", RT5645_PWR_VOL, RT5645_PWR_HV_R_BIT, 2214 0, rt5645_hpvolr_mix, ARRAY_SIZE(rt5645_hpvolr_mix)), 2215 SND_SOC_DAPM_SUPPLY("HPOVOL MIXL Power", RT5645_PWR_MIXER, 2216 RT5645_PWR_HM_L_BIT, 0, NULL, 0), 2217 SND_SOC_DAPM_SUPPLY("HPOVOL MIXR Power", RT5645_PWR_MIXER, 2218 RT5645_PWR_HM_R_BIT, 0, NULL, 0), 2219 SND_SOC_DAPM_PGA("DAC 1", SND_SOC_NOPM, 0, 0, NULL, 0), 2220 SND_SOC_DAPM_PGA("DAC 2", SND_SOC_NOPM, 0, 0, NULL, 0), 2221 SND_SOC_DAPM_PGA("HPOVOL", SND_SOC_NOPM, 0, 0, NULL, 0), 2222 SND_SOC_DAPM_SWITCH("HPOVOL L", SND_SOC_NOPM, 0, 0, &hp_l_vol_control), 2223 SND_SOC_DAPM_SWITCH("HPOVOL R", SND_SOC_NOPM, 0, 0, &hp_r_vol_control), 2224 2225 /* HPO/LOUT/Mono Mixer */ 2226 SND_SOC_DAPM_MIXER("SPOL MIX", SND_SOC_NOPM, 0, 0, rt5645_spo_l_mix, 2227 ARRAY_SIZE(rt5645_spo_l_mix)), 2228 SND_SOC_DAPM_MIXER("SPOR MIX", SND_SOC_NOPM, 0, 0, rt5645_spo_r_mix, 2229 ARRAY_SIZE(rt5645_spo_r_mix)), 2230 SND_SOC_DAPM_MIXER("HPO MIX", SND_SOC_NOPM, 0, 0, rt5645_hpo_mix, 2231 ARRAY_SIZE(rt5645_hpo_mix)), 2232 SND_SOC_DAPM_MIXER("LOUT MIX", SND_SOC_NOPM, 0, 0, rt5645_lout_mix, 2233 ARRAY_SIZE(rt5645_lout_mix)), 2234 2235 SND_SOC_DAPM_PGA_S("HP amp", 1, SND_SOC_NOPM, 0, 0, rt5645_hp_event, 2236 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU), 2237 SND_SOC_DAPM_PGA_S("LOUT amp", 1, SND_SOC_NOPM, 0, 0, rt5645_lout_event, 2238 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU), 2239 SND_SOC_DAPM_PGA_S("SPK amp", 2, SND_SOC_NOPM, 0, 0, rt5645_spk_event, 2240 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU), 2241 2242 /* PDM */ 2243 SND_SOC_DAPM_SUPPLY("PDM1 Power", RT5645_PWR_DIG2, RT5645_PWR_PDM1_BIT, 2244 0, NULL, 0), 2245 SND_SOC_DAPM_MUX("PDM1 L Mux", SND_SOC_NOPM, 0, 0, &rt5645_pdm1_l_mux), 2246 SND_SOC_DAPM_MUX("PDM1 R Mux", SND_SOC_NOPM, 0, 0, &rt5645_pdm1_r_mux), 2247 2248 SND_SOC_DAPM_SWITCH("PDM1 L", SND_SOC_NOPM, 0, 0, &pdm1_l_vol_control), 2249 SND_SOC_DAPM_SWITCH("PDM1 R", SND_SOC_NOPM, 0, 0, &pdm1_r_vol_control), 2250 2251 /* Output Lines */ 2252 SND_SOC_DAPM_OUTPUT("HPOL"), 2253 SND_SOC_DAPM_OUTPUT("HPOR"), 2254 SND_SOC_DAPM_OUTPUT("LOUTL"), 2255 SND_SOC_DAPM_OUTPUT("LOUTR"), 2256 SND_SOC_DAPM_OUTPUT("PDM1L"), 2257 SND_SOC_DAPM_OUTPUT("PDM1R"), 2258 SND_SOC_DAPM_OUTPUT("SPOL"), 2259 SND_SOC_DAPM_OUTPUT("SPOR"), 2260 }; 2261 2262 static const struct snd_soc_dapm_widget rt5645_specific_dapm_widgets[] = { 2263 SND_SOC_DAPM_MUX("RT5645 IF1 DAC1 L Mux", SND_SOC_NOPM, 0, 0, 2264 &rt5645_if1_dac0_tdm_sel_mux), 2265 SND_SOC_DAPM_MUX("RT5645 IF1 DAC1 R Mux", SND_SOC_NOPM, 0, 0, 2266 &rt5645_if1_dac1_tdm_sel_mux), 2267 SND_SOC_DAPM_MUX("RT5645 IF1 DAC2 L Mux", SND_SOC_NOPM, 0, 0, 2268 &rt5645_if1_dac2_tdm_sel_mux), 2269 SND_SOC_DAPM_MUX("RT5645 IF1 DAC2 R Mux", SND_SOC_NOPM, 0, 0, 2270 &rt5645_if1_dac3_tdm_sel_mux), 2271 SND_SOC_DAPM_MUX("RT5645 IF1 ADC Mux", SND_SOC_NOPM, 2272 0, 0, &rt5645_if1_adc_in_mux), 2273 SND_SOC_DAPM_MUX("RT5645 IF1 ADC1 Swap Mux", SND_SOC_NOPM, 2274 0, 0, &rt5645_if1_adc1_in_mux), 2275 SND_SOC_DAPM_MUX("RT5645 IF1 ADC2 Swap Mux", SND_SOC_NOPM, 2276 0, 0, &rt5645_if1_adc2_in_mux), 2277 SND_SOC_DAPM_MUX("RT5645 IF1 ADC3 Swap Mux", SND_SOC_NOPM, 2278 0, 0, &rt5645_if1_adc3_in_mux), 2279 }; 2280 2281 static const struct snd_soc_dapm_widget rt5650_specific_dapm_widgets[] = { 2282 SND_SOC_DAPM_MUX("A DAC1 L Mux", SND_SOC_NOPM, 2283 0, 0, &rt5650_a_dac1_l_mux), 2284 SND_SOC_DAPM_MUX("A DAC1 R Mux", SND_SOC_NOPM, 2285 0, 0, &rt5650_a_dac1_r_mux), 2286 SND_SOC_DAPM_MUX("A DAC2 L Mux", SND_SOC_NOPM, 2287 0, 0, &rt5650_a_dac2_l_mux), 2288 SND_SOC_DAPM_MUX("A DAC2 R Mux", SND_SOC_NOPM, 2289 0, 0, &rt5650_a_dac2_r_mux), 2290 2291 SND_SOC_DAPM_MUX("RT5650 IF1 ADC1 Swap Mux", SND_SOC_NOPM, 2292 0, 0, &rt5650_if1_adc1_in_mux), 2293 SND_SOC_DAPM_MUX("RT5650 IF1 ADC2 Swap Mux", SND_SOC_NOPM, 2294 0, 0, &rt5650_if1_adc2_in_mux), 2295 SND_SOC_DAPM_MUX("RT5650 IF1 ADC3 Swap Mux", SND_SOC_NOPM, 2296 0, 0, &rt5650_if1_adc3_in_mux), 2297 SND_SOC_DAPM_MUX("RT5650 IF1 ADC Mux", SND_SOC_NOPM, 2298 0, 0, &rt5650_if1_adc_in_mux), 2299 2300 SND_SOC_DAPM_MUX("RT5650 IF1 DAC1 L Mux", SND_SOC_NOPM, 0, 0, 2301 &rt5650_if1_dac0_tdm_sel_mux), 2302 SND_SOC_DAPM_MUX("RT5650 IF1 DAC1 R Mux", SND_SOC_NOPM, 0, 0, 2303 &rt5650_if1_dac1_tdm_sel_mux), 2304 SND_SOC_DAPM_MUX("RT5650 IF1 DAC2 L Mux", SND_SOC_NOPM, 0, 0, 2305 &rt5650_if1_dac2_tdm_sel_mux), 2306 SND_SOC_DAPM_MUX("RT5650 IF1 DAC2 R Mux", SND_SOC_NOPM, 0, 0, 2307 &rt5650_if1_dac3_tdm_sel_mux), 2308 }; 2309 2310 static const struct snd_soc_dapm_route rt5645_dapm_routes[] = { 2311 { "adc stereo1 filter", NULL, "ADC STO1 ASRC", is_using_asrc }, 2312 { "adc mono left filter", NULL, "ADC MONO L ASRC", is_using_asrc }, 2313 { "adc mono right filter", NULL, "ADC MONO R ASRC", is_using_asrc }, 2314 { "dac mono left filter", NULL, "DAC MONO L ASRC", is_using_asrc }, 2315 { "dac mono right filter", NULL, "DAC MONO R ASRC", is_using_asrc }, 2316 { "dac stereo1 filter", NULL, "DAC STO ASRC", is_using_asrc }, 2317 2318 { "I2S1", NULL, "I2S1 ASRC" }, 2319 { "I2S2", NULL, "I2S2 ASRC" }, 2320 2321 { "IN1P", NULL, "LDO2" }, 2322 { "IN2P", NULL, "LDO2" }, 2323 2324 { "DMIC1", NULL, "DMIC L1" }, 2325 { "DMIC1", NULL, "DMIC R1" }, 2326 { "DMIC2", NULL, "DMIC L2" }, 2327 { "DMIC2", NULL, "DMIC R2" }, 2328 2329 { "BST1", NULL, "IN1P" }, 2330 { "BST1", NULL, "IN1N" }, 2331 { "BST1", NULL, "JD Power" }, 2332 { "BST1", NULL, "Mic Det Power" }, 2333 { "BST2", NULL, "IN2P" }, 2334 { "BST2", NULL, "IN2N" }, 2335 2336 { "INL VOL", NULL, "IN2P" }, 2337 { "INR VOL", NULL, "IN2N" }, 2338 2339 { "RECMIXL", "HPOL Switch", "HPOL" }, 2340 { "RECMIXL", "INL Switch", "INL VOL" }, 2341 { "RECMIXL", "BST2 Switch", "BST2" }, 2342 { "RECMIXL", "BST1 Switch", "BST1" }, 2343 { "RECMIXL", "OUT MIXL Switch", "OUT MIXL" }, 2344 2345 { "RECMIXR", "HPOR Switch", "HPOR" }, 2346 { "RECMIXR", "INR Switch", "INR VOL" }, 2347 { "RECMIXR", "BST2 Switch", "BST2" }, 2348 { "RECMIXR", "BST1 Switch", "BST1" }, 2349 { "RECMIXR", "OUT MIXR Switch", "OUT MIXR" }, 2350 2351 { "ADC L", NULL, "RECMIXL" }, 2352 { "ADC L", NULL, "ADC L power" }, 2353 { "ADC R", NULL, "RECMIXR" }, 2354 { "ADC R", NULL, "ADC R power" }, 2355 2356 {"DMIC L1", NULL, "DMIC CLK"}, 2357 {"DMIC L1", NULL, "DMIC1 Power"}, 2358 {"DMIC R1", NULL, "DMIC CLK"}, 2359 {"DMIC R1", NULL, "DMIC1 Power"}, 2360 {"DMIC L2", NULL, "DMIC CLK"}, 2361 {"DMIC L2", NULL, "DMIC2 Power"}, 2362 {"DMIC R2", NULL, "DMIC CLK"}, 2363 {"DMIC R2", NULL, "DMIC2 Power"}, 2364 2365 { "Stereo1 DMIC Mux", "DMIC1", "DMIC1" }, 2366 { "Stereo1 DMIC Mux", "DMIC2", "DMIC2" }, 2367 { "Stereo1 DMIC Mux", NULL, "DMIC STO1 ASRC" }, 2368 2369 { "Mono DMIC L Mux", "DMIC1", "DMIC L1" }, 2370 { "Mono DMIC L Mux", "DMIC2", "DMIC L2" }, 2371 { "Mono DMIC L Mux", NULL, "DMIC MONO L ASRC" }, 2372 2373 { "Mono DMIC R Mux", "DMIC1", "DMIC R1" }, 2374 { "Mono DMIC R Mux", "DMIC2", "DMIC R2" }, 2375 { "Mono DMIC R Mux", NULL, "DMIC MONO R ASRC" }, 2376 2377 { "Stereo1 ADC L2 Mux", "DMIC", "Stereo1 DMIC Mux" }, 2378 { "Stereo1 ADC L2 Mux", "DAC MIX", "DAC MIXL" }, 2379 { "Stereo1 ADC L1 Mux", "ADC", "ADC L" }, 2380 { "Stereo1 ADC L1 Mux", "DAC MIX", "DAC MIXL" }, 2381 2382 { "Stereo1 ADC R1 Mux", "ADC", "ADC R" }, 2383 { "Stereo1 ADC R1 Mux", "DAC MIX", "DAC MIXR" }, 2384 { "Stereo1 ADC R2 Mux", "DMIC", "Stereo1 DMIC Mux" }, 2385 { "Stereo1 ADC R2 Mux", "DAC MIX", "DAC MIXR" }, 2386 2387 { "Mono ADC L2 Mux", "DMIC", "Mono DMIC L Mux" }, 2388 { "Mono ADC L2 Mux", "Mono DAC MIXL", "Mono DAC MIXL" }, 2389 { "Mono ADC L1 Mux", "Mono DAC MIXL", "Mono DAC MIXL" }, 2390 { "Mono ADC L1 Mux", "ADC", "ADC L" }, 2391 2392 { "Mono ADC R1 Mux", "Mono DAC MIXR", "Mono DAC MIXR" }, 2393 { "Mono ADC R1 Mux", "ADC", "ADC R" }, 2394 { "Mono ADC R2 Mux", "DMIC", "Mono DMIC R Mux" }, 2395 { "Mono ADC R2 Mux", "Mono DAC MIXR", "Mono DAC MIXR" }, 2396 2397 { "Sto1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC L1 Mux" }, 2398 { "Sto1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC L2 Mux" }, 2399 { "Sto1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC R1 Mux" }, 2400 { "Sto1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC R2 Mux" }, 2401 2402 { "Stereo1 ADC MIXL", NULL, "Sto1 ADC MIXL" }, 2403 { "Stereo1 ADC MIXL", NULL, "adc stereo1 filter" }, 2404 { "adc stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll }, 2405 2406 { "Stereo1 ADC MIXR", NULL, "Sto1 ADC MIXR" }, 2407 { "Stereo1 ADC MIXR", NULL, "adc stereo1 filter" }, 2408 { "adc stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll }, 2409 2410 { "Mono ADC MIXL", "ADC1 Switch", "Mono ADC L1 Mux" }, 2411 { "Mono ADC MIXL", "ADC2 Switch", "Mono ADC L2 Mux" }, 2412 { "Mono ADC MIXL", NULL, "adc mono left filter" }, 2413 { "adc mono left filter", NULL, "PLL1", is_sys_clk_from_pll }, 2414 2415 { "Mono ADC MIXR", "ADC1 Switch", "Mono ADC R1 Mux" }, 2416 { "Mono ADC MIXR", "ADC2 Switch", "Mono ADC R2 Mux" }, 2417 { "Mono ADC MIXR", NULL, "adc mono right filter" }, 2418 { "adc mono right filter", NULL, "PLL1", is_sys_clk_from_pll }, 2419 2420 { "VAD ADC Mux", "Sto1 ADC L", "Stereo1 ADC MIXL" }, 2421 { "VAD ADC Mux", "Mono ADC L", "Mono ADC MIXL" }, 2422 { "VAD ADC Mux", "Mono ADC R", "Mono ADC MIXR" }, 2423 2424 { "IF_ADC1", NULL, "Stereo1 ADC MIXL" }, 2425 { "IF_ADC1", NULL, "Stereo1 ADC MIXR" }, 2426 { "IF_ADC2", NULL, "Mono ADC MIXL" }, 2427 { "IF_ADC2", NULL, "Mono ADC MIXR" }, 2428 { "VAD_ADC", NULL, "VAD ADC Mux" }, 2429 2430 { "IF2 ADC Mux", "IF_ADC1", "IF_ADC1" }, 2431 { "IF2 ADC Mux", "IF_ADC2", "IF_ADC2" }, 2432 { "IF2 ADC Mux", "VAD_ADC", "VAD_ADC" }, 2433 2434 { "IF1 ADC", NULL, "I2S1" }, 2435 { "IF2 ADC", NULL, "I2S2" }, 2436 { "IF2 ADC", NULL, "IF2 ADC Mux" }, 2437 2438 { "AIF2TX", NULL, "IF2 ADC" }, 2439 2440 { "IF1 DAC0", NULL, "AIF1RX" }, 2441 { "IF1 DAC1", NULL, "AIF1RX" }, 2442 { "IF1 DAC2", NULL, "AIF1RX" }, 2443 { "IF1 DAC3", NULL, "AIF1RX" }, 2444 { "IF2 DAC", NULL, "AIF2RX" }, 2445 2446 { "IF1 DAC0", NULL, "I2S1" }, 2447 { "IF1 DAC1", NULL, "I2S1" }, 2448 { "IF1 DAC2", NULL, "I2S1" }, 2449 { "IF1 DAC3", NULL, "I2S1" }, 2450 { "IF2 DAC", NULL, "I2S2" }, 2451 2452 { "IF2 DAC L", NULL, "IF2 DAC" }, 2453 { "IF2 DAC R", NULL, "IF2 DAC" }, 2454 2455 { "DAC1 L Mux", "IF2 DAC", "IF2 DAC L" }, 2456 { "DAC1 R Mux", "IF2 DAC", "IF2 DAC R" }, 2457 2458 { "DAC1 MIXL", "Stereo ADC Switch", "Stereo1 ADC MIXL" }, 2459 { "DAC1 MIXL", "DAC1 Switch", "DAC1 L Mux" }, 2460 { "DAC1 MIXL", NULL, "dac stereo1 filter" }, 2461 { "DAC1 MIXR", "Stereo ADC Switch", "Stereo1 ADC MIXR" }, 2462 { "DAC1 MIXR", "DAC1 Switch", "DAC1 R Mux" }, 2463 { "DAC1 MIXR", NULL, "dac stereo1 filter" }, 2464 2465 { "DAC L2 Mux", "IF2 DAC", "IF2 DAC L" }, 2466 { "DAC L2 Mux", "Mono ADC", "Mono ADC MIXL" }, 2467 { "DAC L2 Mux", "VAD_ADC", "VAD_ADC" }, 2468 { "DAC L2 Volume", NULL, "DAC L2 Mux" }, 2469 { "DAC L2 Volume", NULL, "dac mono left filter" }, 2470 2471 { "DAC R2 Mux", "IF2 DAC", "IF2 DAC R" }, 2472 { "DAC R2 Mux", "Mono ADC", "Mono ADC MIXR" }, 2473 { "DAC R2 Mux", "Haptic", "Haptic Generator" }, 2474 { "DAC R2 Volume", NULL, "DAC R2 Mux" }, 2475 { "DAC R2 Volume", NULL, "dac mono right filter" }, 2476 2477 { "Stereo DAC MIXL", "DAC L1 Switch", "DAC1 MIXL" }, 2478 { "Stereo DAC MIXL", "DAC R1 Switch", "DAC1 MIXR" }, 2479 { "Stereo DAC MIXL", "DAC L2 Switch", "DAC L2 Volume" }, 2480 { "Stereo DAC MIXL", NULL, "dac stereo1 filter" }, 2481 { "Stereo DAC MIXR", "DAC R1 Switch", "DAC1 MIXR" }, 2482 { "Stereo DAC MIXR", "DAC L1 Switch", "DAC1 MIXL" }, 2483 { "Stereo DAC MIXR", "DAC R2 Switch", "DAC R2 Volume" }, 2484 { "Stereo DAC MIXR", NULL, "dac stereo1 filter" }, 2485 2486 { "Mono DAC MIXL", "DAC L1 Switch", "DAC1 MIXL" }, 2487 { "Mono DAC MIXL", "DAC L2 Switch", "DAC L2 Volume" }, 2488 { "Mono DAC MIXL", "DAC R2 Switch", "DAC R2 Volume" }, 2489 { "Mono DAC MIXL", NULL, "dac mono left filter" }, 2490 { "Mono DAC MIXR", "DAC R1 Switch", "DAC1 MIXR" }, 2491 { "Mono DAC MIXR", "DAC R2 Switch", "DAC R2 Volume" }, 2492 { "Mono DAC MIXR", "DAC L2 Switch", "DAC L2 Volume" }, 2493 { "Mono DAC MIXR", NULL, "dac mono right filter" }, 2494 2495 { "DAC MIXL", "Sto DAC Mix L Switch", "Stereo DAC MIXL" }, 2496 { "DAC MIXL", "DAC L2 Switch", "DAC L2 Volume" }, 2497 { "DAC MIXL", "DAC R2 Switch", "DAC R2 Volume" }, 2498 { "DAC MIXR", "Sto DAC Mix R Switch", "Stereo DAC MIXR" }, 2499 { "DAC MIXR", "DAC R2 Switch", "DAC R2 Volume" }, 2500 { "DAC MIXR", "DAC L2 Switch", "DAC L2 Volume" }, 2501 2502 { "DAC L1", NULL, "PLL1", is_sys_clk_from_pll }, 2503 { "DAC R1", NULL, "PLL1", is_sys_clk_from_pll }, 2504 { "DAC L2", NULL, "PLL1", is_sys_clk_from_pll }, 2505 { "DAC R2", NULL, "PLL1", is_sys_clk_from_pll }, 2506 2507 { "SPK MIXL", "BST1 Switch", "BST1" }, 2508 { "SPK MIXL", "INL Switch", "INL VOL" }, 2509 { "SPK MIXL", "DAC L1 Switch", "DAC L1" }, 2510 { "SPK MIXL", "DAC L2 Switch", "DAC L2" }, 2511 { "SPK MIXR", "BST2 Switch", "BST2" }, 2512 { "SPK MIXR", "INR Switch", "INR VOL" }, 2513 { "SPK MIXR", "DAC R1 Switch", "DAC R1" }, 2514 { "SPK MIXR", "DAC R2 Switch", "DAC R2" }, 2515 2516 { "OUT MIXL", "BST1 Switch", "BST1" }, 2517 { "OUT MIXL", "INL Switch", "INL VOL" }, 2518 { "OUT MIXL", "DAC L2 Switch", "DAC L2" }, 2519 { "OUT MIXL", "DAC L1 Switch", "DAC L1" }, 2520 2521 { "OUT MIXR", "BST2 Switch", "BST2" }, 2522 { "OUT MIXR", "INR Switch", "INR VOL" }, 2523 { "OUT MIXR", "DAC R2 Switch", "DAC R2" }, 2524 { "OUT MIXR", "DAC R1 Switch", "DAC R1" }, 2525 2526 { "HPOVOL MIXL", "DAC1 Switch", "DAC L1" }, 2527 { "HPOVOL MIXL", "DAC2 Switch", "DAC L2" }, 2528 { "HPOVOL MIXL", "INL Switch", "INL VOL" }, 2529 { "HPOVOL MIXL", "BST1 Switch", "BST1" }, 2530 { "HPOVOL MIXL", NULL, "HPOVOL MIXL Power" }, 2531 { "HPOVOL MIXR", "DAC1 Switch", "DAC R1" }, 2532 { "HPOVOL MIXR", "DAC2 Switch", "DAC R2" }, 2533 { "HPOVOL MIXR", "INR Switch", "INR VOL" }, 2534 { "HPOVOL MIXR", "BST2 Switch", "BST2" }, 2535 { "HPOVOL MIXR", NULL, "HPOVOL MIXR Power" }, 2536 2537 { "DAC 2", NULL, "DAC L2" }, 2538 { "DAC 2", NULL, "DAC R2" }, 2539 { "DAC 1", NULL, "DAC L1" }, 2540 { "DAC 1", NULL, "DAC R1" }, 2541 { "HPOVOL L", "Switch", "HPOVOL MIXL" }, 2542 { "HPOVOL R", "Switch", "HPOVOL MIXR" }, 2543 { "HPOVOL", NULL, "HPOVOL L" }, 2544 { "HPOVOL", NULL, "HPOVOL R" }, 2545 { "HPO MIX", "DAC1 Switch", "DAC 1" }, 2546 { "HPO MIX", "HPVOL Switch", "HPOVOL" }, 2547 2548 { "SPKVOL L", "Switch", "SPK MIXL" }, 2549 { "SPKVOL R", "Switch", "SPK MIXR" }, 2550 2551 { "SPOL MIX", "DAC L1 Switch", "DAC L1" }, 2552 { "SPOL MIX", "SPKVOL L Switch", "SPKVOL L" }, 2553 { "SPOR MIX", "DAC R1 Switch", "DAC R1" }, 2554 { "SPOR MIX", "SPKVOL R Switch", "SPKVOL R" }, 2555 2556 { "LOUT MIX", "DAC L1 Switch", "DAC L1" }, 2557 { "LOUT MIX", "DAC R1 Switch", "DAC R1" }, 2558 { "LOUT MIX", "OUTMIX L Switch", "OUT MIXL" }, 2559 { "LOUT MIX", "OUTMIX R Switch", "OUT MIXR" }, 2560 2561 { "PDM1 L Mux", "Stereo DAC", "Stereo DAC MIXL" }, 2562 { "PDM1 L Mux", "Mono DAC", "Mono DAC MIXL" }, 2563 { "PDM1 L Mux", NULL, "PDM1 Power" }, 2564 { "PDM1 R Mux", "Stereo DAC", "Stereo DAC MIXR" }, 2565 { "PDM1 R Mux", "Mono DAC", "Mono DAC MIXR" }, 2566 { "PDM1 R Mux", NULL, "PDM1 Power" }, 2567 2568 { "HP amp", NULL, "HPO MIX" }, 2569 { "HP amp", NULL, "JD Power" }, 2570 { "HP amp", NULL, "Mic Det Power" }, 2571 { "HP amp", NULL, "LDO2" }, 2572 { "HPOL", NULL, "HP amp" }, 2573 { "HPOR", NULL, "HP amp" }, 2574 2575 { "LOUT amp", NULL, "LOUT MIX" }, 2576 { "LOUTL", NULL, "LOUT amp" }, 2577 { "LOUTR", NULL, "LOUT amp" }, 2578 2579 { "PDM1 L", "Switch", "PDM1 L Mux" }, 2580 { "PDM1 R", "Switch", "PDM1 R Mux" }, 2581 2582 { "PDM1L", NULL, "PDM1 L" }, 2583 { "PDM1R", NULL, "PDM1 R" }, 2584 2585 { "SPK amp", NULL, "SPOL MIX" }, 2586 { "SPK amp", NULL, "SPOR MIX" }, 2587 { "SPOL", NULL, "SPK amp" }, 2588 { "SPOR", NULL, "SPK amp" }, 2589 }; 2590 2591 static const struct snd_soc_dapm_route rt5650_specific_dapm_routes[] = { 2592 { "A DAC1 L Mux", "DAC1", "DAC1 MIXL"}, 2593 { "A DAC1 L Mux", "Stereo DAC Mixer", "Stereo DAC MIXL"}, 2594 { "A DAC1 R Mux", "DAC1", "DAC1 MIXR"}, 2595 { "A DAC1 R Mux", "Stereo DAC Mixer", "Stereo DAC MIXR"}, 2596 2597 { "A DAC2 L Mux", "Stereo DAC Mixer", "Stereo DAC MIXL"}, 2598 { "A DAC2 L Mux", "Mono DAC Mixer", "Mono DAC MIXL"}, 2599 { "A DAC2 R Mux", "Stereo DAC Mixer", "Stereo DAC MIXR"}, 2600 { "A DAC2 R Mux", "Mono DAC Mixer", "Mono DAC MIXR"}, 2601 2602 { "DAC L1", NULL, "A DAC1 L Mux" }, 2603 { "DAC R1", NULL, "A DAC1 R Mux" }, 2604 { "DAC L2", NULL, "A DAC2 L Mux" }, 2605 { "DAC R2", NULL, "A DAC2 R Mux" }, 2606 2607 { "RT5650 IF1 ADC1 Swap Mux", "L/R", "IF_ADC1" }, 2608 { "RT5650 IF1 ADC1 Swap Mux", "R/L", "IF_ADC1" }, 2609 { "RT5650 IF1 ADC1 Swap Mux", "L/L", "IF_ADC1" }, 2610 { "RT5650 IF1 ADC1 Swap Mux", "R/R", "IF_ADC1" }, 2611 2612 { "RT5650 IF1 ADC2 Swap Mux", "L/R", "IF_ADC2" }, 2613 { "RT5650 IF1 ADC2 Swap Mux", "R/L", "IF_ADC2" }, 2614 { "RT5650 IF1 ADC2 Swap Mux", "L/L", "IF_ADC2" }, 2615 { "RT5650 IF1 ADC2 Swap Mux", "R/R", "IF_ADC2" }, 2616 2617 { "RT5650 IF1 ADC3 Swap Mux", "L/R", "VAD_ADC" }, 2618 { "RT5650 IF1 ADC3 Swap Mux", "R/L", "VAD_ADC" }, 2619 { "RT5650 IF1 ADC3 Swap Mux", "L/L", "VAD_ADC" }, 2620 { "RT5650 IF1 ADC3 Swap Mux", "R/R", "VAD_ADC" }, 2621 2622 { "IF1 ADC", NULL, "RT5650 IF1 ADC1 Swap Mux" }, 2623 { "IF1 ADC", NULL, "RT5650 IF1 ADC2 Swap Mux" }, 2624 { "IF1 ADC", NULL, "RT5650 IF1 ADC3 Swap Mux" }, 2625 2626 { "RT5650 IF1 ADC Mux", "IF_ADC1/IF_ADC2/DAC_REF/Null", "IF1 ADC" }, 2627 { "RT5650 IF1 ADC Mux", "IF_ADC1/IF_ADC2/Null/DAC_REF", "IF1 ADC" }, 2628 { "RT5650 IF1 ADC Mux", "IF_ADC1/DAC_REF/IF_ADC2/Null", "IF1 ADC" }, 2629 { "RT5650 IF1 ADC Mux", "IF_ADC1/DAC_REF/Null/IF_ADC2", "IF1 ADC" }, 2630 { "RT5650 IF1 ADC Mux", "IF_ADC1/Null/DAC_REF/IF_ADC2", "IF1 ADC" }, 2631 { "RT5650 IF1 ADC Mux", "IF_ADC1/Null/IF_ADC2/DAC_REF", "IF1 ADC" }, 2632 2633 { "RT5650 IF1 ADC Mux", "IF_ADC2/IF_ADC1/DAC_REF/Null", "IF1 ADC" }, 2634 { "RT5650 IF1 ADC Mux", "IF_ADC2/IF_ADC1/Null/DAC_REF", "IF1 ADC" }, 2635 { "RT5650 IF1 ADC Mux", "IF_ADC2/DAC_REF/IF_ADC1/Null", "IF1 ADC" }, 2636 { "RT5650 IF1 ADC Mux", "IF_ADC2/DAC_REF/Null/IF_ADC1", "IF1 ADC" }, 2637 { "RT5650 IF1 ADC Mux", "IF_ADC2/Null/DAC_REF/IF_ADC1", "IF1 ADC" }, 2638 { "RT5650 IF1 ADC Mux", "IF_ADC2/Null/IF_ADC1/DAC_REF", "IF1 ADC" }, 2639 2640 { "RT5650 IF1 ADC Mux", "DAC_REF/IF_ADC1/IF_ADC2/Null", "IF1 ADC" }, 2641 { "RT5650 IF1 ADC Mux", "DAC_REF/IF_ADC1/Null/IF_ADC2", "IF1 ADC" }, 2642 { "RT5650 IF1 ADC Mux", "DAC_REF/IF_ADC2/IF_ADC1/Null", "IF1 ADC" }, 2643 { "RT5650 IF1 ADC Mux", "DAC_REF/IF_ADC2/Null/IF_ADC1", "IF1 ADC" }, 2644 { "RT5650 IF1 ADC Mux", "DAC_REF/Null/IF_ADC1/IF_ADC2", "IF1 ADC" }, 2645 { "RT5650 IF1 ADC Mux", "DAC_REF/Null/IF_ADC2/IF_ADC1", "IF1 ADC" }, 2646 2647 { "RT5650 IF1 ADC Mux", "Null/IF_ADC1/IF_ADC2/DAC_REF", "IF1 ADC" }, 2648 { "RT5650 IF1 ADC Mux", "Null/IF_ADC1/DAC_REF/IF_ADC2", "IF1 ADC" }, 2649 { "RT5650 IF1 ADC Mux", "Null/IF_ADC2/IF_ADC1/DAC_REF", "IF1 ADC" }, 2650 { "RT5650 IF1 ADC Mux", "Null/IF_ADC2/DAC_REF/IF_ADC1", "IF1 ADC" }, 2651 { "RT5650 IF1 ADC Mux", "Null/DAC_REF/IF_ADC1/IF_ADC2", "IF1 ADC" }, 2652 { "RT5650 IF1 ADC Mux", "Null/DAC_REF/IF_ADC2/IF_ADC1", "IF1 ADC" }, 2653 { "AIF1TX", NULL, "RT5650 IF1 ADC Mux" }, 2654 2655 { "RT5650 IF1 DAC1 L Mux", "Slot0", "IF1 DAC0" }, 2656 { "RT5650 IF1 DAC1 L Mux", "Slot1", "IF1 DAC1" }, 2657 { "RT5650 IF1 DAC1 L Mux", "Slot2", "IF1 DAC2" }, 2658 { "RT5650 IF1 DAC1 L Mux", "Slot3", "IF1 DAC3" }, 2659 2660 { "RT5650 IF1 DAC1 R Mux", "Slot0", "IF1 DAC0" }, 2661 { "RT5650 IF1 DAC1 R Mux", "Slot1", "IF1 DAC1" }, 2662 { "RT5650 IF1 DAC1 R Mux", "Slot2", "IF1 DAC2" }, 2663 { "RT5650 IF1 DAC1 R Mux", "Slot3", "IF1 DAC3" }, 2664 2665 { "RT5650 IF1 DAC2 L Mux", "Slot0", "IF1 DAC0" }, 2666 { "RT5650 IF1 DAC2 L Mux", "Slot1", "IF1 DAC1" }, 2667 { "RT5650 IF1 DAC2 L Mux", "Slot2", "IF1 DAC2" }, 2668 { "RT5650 IF1 DAC2 L Mux", "Slot3", "IF1 DAC3" }, 2669 2670 { "RT5650 IF1 DAC2 R Mux", "Slot0", "IF1 DAC0" }, 2671 { "RT5650 IF1 DAC2 R Mux", "Slot1", "IF1 DAC1" }, 2672 { "RT5650 IF1 DAC2 R Mux", "Slot2", "IF1 DAC2" }, 2673 { "RT5650 IF1 DAC2 R Mux", "Slot3", "IF1 DAC3" }, 2674 2675 { "DAC1 L Mux", "IF1 DAC", "RT5650 IF1 DAC1 L Mux" }, 2676 { "DAC1 R Mux", "IF1 DAC", "RT5650 IF1 DAC1 R Mux" }, 2677 2678 { "DAC L2 Mux", "IF1 DAC", "RT5650 IF1 DAC2 L Mux" }, 2679 { "DAC R2 Mux", "IF1 DAC", "RT5650 IF1 DAC2 R Mux" }, 2680 }; 2681 2682 static const struct snd_soc_dapm_route rt5645_specific_dapm_routes[] = { 2683 { "DAC L1", NULL, "Stereo DAC MIXL" }, 2684 { "DAC R1", NULL, "Stereo DAC MIXR" }, 2685 { "DAC L2", NULL, "Mono DAC MIXL" }, 2686 { "DAC R2", NULL, "Mono DAC MIXR" }, 2687 2688 { "RT5645 IF1 ADC1 Swap Mux", "L/R", "IF_ADC1" }, 2689 { "RT5645 IF1 ADC1 Swap Mux", "R/L", "IF_ADC1" }, 2690 { "RT5645 IF1 ADC1 Swap Mux", "L/L", "IF_ADC1" }, 2691 { "RT5645 IF1 ADC1 Swap Mux", "R/R", "IF_ADC1" }, 2692 2693 { "RT5645 IF1 ADC2 Swap Mux", "L/R", "IF_ADC2" }, 2694 { "RT5645 IF1 ADC2 Swap Mux", "R/L", "IF_ADC2" }, 2695 { "RT5645 IF1 ADC2 Swap Mux", "L/L", "IF_ADC2" }, 2696 { "RT5645 IF1 ADC2 Swap Mux", "R/R", "IF_ADC2" }, 2697 2698 { "RT5645 IF1 ADC3 Swap Mux", "L/R", "VAD_ADC" }, 2699 { "RT5645 IF1 ADC3 Swap Mux", "R/L", "VAD_ADC" }, 2700 { "RT5645 IF1 ADC3 Swap Mux", "L/L", "VAD_ADC" }, 2701 { "RT5645 IF1 ADC3 Swap Mux", "R/R", "VAD_ADC" }, 2702 2703 { "IF1 ADC", NULL, "RT5645 IF1 ADC1 Swap Mux" }, 2704 { "IF1 ADC", NULL, "RT5645 IF1 ADC2 Swap Mux" }, 2705 { "IF1 ADC", NULL, "RT5645 IF1 ADC3 Swap Mux" }, 2706 2707 { "RT5645 IF1 ADC Mux", "IF_ADC1/IF_ADC2/VAD_ADC", "IF1 ADC" }, 2708 { "RT5645 IF1 ADC Mux", "IF_ADC2/IF_ADC1/VAD_ADC", "IF1 ADC" }, 2709 { "RT5645 IF1 ADC Mux", "VAD_ADC/IF_ADC1/IF_ADC2", "IF1 ADC" }, 2710 { "RT5645 IF1 ADC Mux", "VAD_ADC/IF_ADC2/IF_ADC1", "IF1 ADC" }, 2711 { "AIF1TX", NULL, "RT5645 IF1 ADC Mux" }, 2712 2713 { "RT5645 IF1 DAC1 L Mux", "Slot0", "IF1 DAC0" }, 2714 { "RT5645 IF1 DAC1 L Mux", "Slot1", "IF1 DAC1" }, 2715 { "RT5645 IF1 DAC1 L Mux", "Slot2", "IF1 DAC2" }, 2716 { "RT5645 IF1 DAC1 L Mux", "Slot3", "IF1 DAC3" }, 2717 2718 { "RT5645 IF1 DAC1 R Mux", "Slot0", "IF1 DAC0" }, 2719 { "RT5645 IF1 DAC1 R Mux", "Slot1", "IF1 DAC1" }, 2720 { "RT5645 IF1 DAC1 R Mux", "Slot2", "IF1 DAC2" }, 2721 { "RT5645 IF1 DAC1 R Mux", "Slot3", "IF1 DAC3" }, 2722 2723 { "RT5645 IF1 DAC2 L Mux", "Slot0", "IF1 DAC0" }, 2724 { "RT5645 IF1 DAC2 L Mux", "Slot1", "IF1 DAC1" }, 2725 { "RT5645 IF1 DAC2 L Mux", "Slot2", "IF1 DAC2" }, 2726 { "RT5645 IF1 DAC2 L Mux", "Slot3", "IF1 DAC3" }, 2727 2728 { "RT5645 IF1 DAC2 R Mux", "Slot0", "IF1 DAC0" }, 2729 { "RT5645 IF1 DAC2 R Mux", "Slot1", "IF1 DAC1" }, 2730 { "RT5645 IF1 DAC2 R Mux", "Slot2", "IF1 DAC2" }, 2731 { "RT5645 IF1 DAC2 R Mux", "Slot3", "IF1 DAC3" }, 2732 2733 { "DAC1 L Mux", "IF1 DAC", "RT5645 IF1 DAC1 L Mux" }, 2734 { "DAC1 R Mux", "IF1 DAC", "RT5645 IF1 DAC1 R Mux" }, 2735 2736 { "DAC L2 Mux", "IF1 DAC", "RT5645 IF1 DAC2 L Mux" }, 2737 { "DAC R2 Mux", "IF1 DAC", "RT5645 IF1 DAC2 R Mux" }, 2738 }; 2739 2740 static const struct snd_soc_dapm_route rt5645_old_dapm_routes[] = { 2741 { "SPOL MIX", "DAC R1 Switch", "DAC R1" }, 2742 { "SPOL MIX", "SPKVOL R Switch", "SPKVOL R" }, 2743 }; 2744 2745 static int rt5645_hw_params(struct snd_pcm_substream *substream, 2746 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) 2747 { 2748 struct snd_soc_component *component = dai->component; 2749 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component); 2750 unsigned int val_len = 0, val_clk, mask_clk, dl_sft; 2751 int pre_div, bclk_ms, frame_size; 2752 2753 rt5645->lrck[dai->id] = params_rate(params); 2754 pre_div = rl6231_get_clk_info(rt5645->sysclk, rt5645->lrck[dai->id]); 2755 if (pre_div < 0) { 2756 dev_err(component->dev, "Unsupported clock setting\n"); 2757 return -EINVAL; 2758 } 2759 frame_size = snd_soc_params_to_frame_size(params); 2760 if (frame_size < 0) { 2761 dev_err(component->dev, "Unsupported frame size: %d\n", frame_size); 2762 return -EINVAL; 2763 } 2764 2765 switch (rt5645->codec_type) { 2766 case CODEC_TYPE_RT5650: 2767 dl_sft = 4; 2768 break; 2769 default: 2770 dl_sft = 2; 2771 break; 2772 } 2773 2774 bclk_ms = frame_size > 32; 2775 rt5645->bclk[dai->id] = rt5645->lrck[dai->id] * (32 << bclk_ms); 2776 2777 dev_dbg(dai->dev, "bclk is %dHz and lrck is %dHz\n", 2778 rt5645->bclk[dai->id], rt5645->lrck[dai->id]); 2779 dev_dbg(dai->dev, "bclk_ms is %d and pre_div is %d for iis %d\n", 2780 bclk_ms, pre_div, dai->id); 2781 2782 switch (params_width(params)) { 2783 case 16: 2784 break; 2785 case 20: 2786 val_len = 0x1; 2787 break; 2788 case 24: 2789 val_len = 0x2; 2790 break; 2791 case 8: 2792 val_len = 0x3; 2793 break; 2794 default: 2795 return -EINVAL; 2796 } 2797 2798 switch (dai->id) { 2799 case RT5645_AIF1: 2800 mask_clk = RT5645_I2S_PD1_MASK; 2801 val_clk = pre_div << RT5645_I2S_PD1_SFT; 2802 snd_soc_component_update_bits(component, RT5645_I2S1_SDP, 2803 (0x3 << dl_sft), (val_len << dl_sft)); 2804 snd_soc_component_update_bits(component, RT5645_ADDA_CLK1, mask_clk, val_clk); 2805 break; 2806 case RT5645_AIF2: 2807 mask_clk = RT5645_I2S_BCLK_MS2_MASK | RT5645_I2S_PD2_MASK; 2808 val_clk = bclk_ms << RT5645_I2S_BCLK_MS2_SFT | 2809 pre_div << RT5645_I2S_PD2_SFT; 2810 snd_soc_component_update_bits(component, RT5645_I2S2_SDP, 2811 (0x3 << dl_sft), (val_len << dl_sft)); 2812 snd_soc_component_update_bits(component, RT5645_ADDA_CLK1, mask_clk, val_clk); 2813 break; 2814 default: 2815 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id); 2816 return -EINVAL; 2817 } 2818 2819 return 0; 2820 } 2821 2822 static int rt5645_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) 2823 { 2824 struct snd_soc_component *component = dai->component; 2825 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component); 2826 unsigned int reg_val = 0, pol_sft; 2827 2828 switch (rt5645->codec_type) { 2829 case CODEC_TYPE_RT5650: 2830 pol_sft = 8; 2831 break; 2832 default: 2833 pol_sft = 7; 2834 break; 2835 } 2836 2837 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 2838 case SND_SOC_DAIFMT_CBM_CFM: 2839 rt5645->master[dai->id] = 1; 2840 break; 2841 case SND_SOC_DAIFMT_CBS_CFS: 2842 reg_val |= RT5645_I2S_MS_S; 2843 rt5645->master[dai->id] = 0; 2844 break; 2845 default: 2846 return -EINVAL; 2847 } 2848 2849 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 2850 case SND_SOC_DAIFMT_NB_NF: 2851 break; 2852 case SND_SOC_DAIFMT_IB_NF: 2853 reg_val |= (1 << pol_sft); 2854 break; 2855 default: 2856 return -EINVAL; 2857 } 2858 2859 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 2860 case SND_SOC_DAIFMT_I2S: 2861 break; 2862 case SND_SOC_DAIFMT_LEFT_J: 2863 reg_val |= RT5645_I2S_DF_LEFT; 2864 break; 2865 case SND_SOC_DAIFMT_DSP_A: 2866 reg_val |= RT5645_I2S_DF_PCM_A; 2867 break; 2868 case SND_SOC_DAIFMT_DSP_B: 2869 reg_val |= RT5645_I2S_DF_PCM_B; 2870 break; 2871 default: 2872 return -EINVAL; 2873 } 2874 switch (dai->id) { 2875 case RT5645_AIF1: 2876 snd_soc_component_update_bits(component, RT5645_I2S1_SDP, 2877 RT5645_I2S_MS_MASK | (1 << pol_sft) | 2878 RT5645_I2S_DF_MASK, reg_val); 2879 break; 2880 case RT5645_AIF2: 2881 snd_soc_component_update_bits(component, RT5645_I2S2_SDP, 2882 RT5645_I2S_MS_MASK | (1 << pol_sft) | 2883 RT5645_I2S_DF_MASK, reg_val); 2884 break; 2885 default: 2886 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id); 2887 return -EINVAL; 2888 } 2889 return 0; 2890 } 2891 2892 static int rt5645_set_dai_sysclk(struct snd_soc_dai *dai, 2893 int clk_id, unsigned int freq, int dir) 2894 { 2895 struct snd_soc_component *component = dai->component; 2896 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component); 2897 unsigned int reg_val = 0; 2898 2899 if (freq == rt5645->sysclk && clk_id == rt5645->sysclk_src) 2900 return 0; 2901 2902 switch (clk_id) { 2903 case RT5645_SCLK_S_MCLK: 2904 reg_val |= RT5645_SCLK_SRC_MCLK; 2905 break; 2906 case RT5645_SCLK_S_PLL1: 2907 reg_val |= RT5645_SCLK_SRC_PLL1; 2908 break; 2909 case RT5645_SCLK_S_RCCLK: 2910 reg_val |= RT5645_SCLK_SRC_RCCLK; 2911 break; 2912 default: 2913 dev_err(component->dev, "Invalid clock id (%d)\n", clk_id); 2914 return -EINVAL; 2915 } 2916 snd_soc_component_update_bits(component, RT5645_GLB_CLK, 2917 RT5645_SCLK_SRC_MASK, reg_val); 2918 rt5645->sysclk = freq; 2919 rt5645->sysclk_src = clk_id; 2920 2921 dev_dbg(dai->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id); 2922 2923 return 0; 2924 } 2925 2926 static int rt5645_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source, 2927 unsigned int freq_in, unsigned int freq_out) 2928 { 2929 struct snd_soc_component *component = dai->component; 2930 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component); 2931 struct rl6231_pll_code pll_code; 2932 int ret; 2933 2934 if (source == rt5645->pll_src && freq_in == rt5645->pll_in && 2935 freq_out == rt5645->pll_out) 2936 return 0; 2937 2938 if (!freq_in || !freq_out) { 2939 dev_dbg(component->dev, "PLL disabled\n"); 2940 2941 rt5645->pll_in = 0; 2942 rt5645->pll_out = 0; 2943 snd_soc_component_update_bits(component, RT5645_GLB_CLK, 2944 RT5645_SCLK_SRC_MASK, RT5645_SCLK_SRC_MCLK); 2945 return 0; 2946 } 2947 2948 switch (source) { 2949 case RT5645_PLL1_S_MCLK: 2950 snd_soc_component_update_bits(component, RT5645_GLB_CLK, 2951 RT5645_PLL1_SRC_MASK, RT5645_PLL1_SRC_MCLK); 2952 break; 2953 case RT5645_PLL1_S_BCLK1: 2954 case RT5645_PLL1_S_BCLK2: 2955 switch (dai->id) { 2956 case RT5645_AIF1: 2957 snd_soc_component_update_bits(component, RT5645_GLB_CLK, 2958 RT5645_PLL1_SRC_MASK, RT5645_PLL1_SRC_BCLK1); 2959 break; 2960 case RT5645_AIF2: 2961 snd_soc_component_update_bits(component, RT5645_GLB_CLK, 2962 RT5645_PLL1_SRC_MASK, RT5645_PLL1_SRC_BCLK2); 2963 break; 2964 default: 2965 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id); 2966 return -EINVAL; 2967 } 2968 break; 2969 default: 2970 dev_err(component->dev, "Unknown PLL source %d\n", source); 2971 return -EINVAL; 2972 } 2973 2974 ret = rl6231_pll_calc(freq_in, freq_out, &pll_code); 2975 if (ret < 0) { 2976 dev_err(component->dev, "Unsupported input clock %d\n", freq_in); 2977 return ret; 2978 } 2979 2980 dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n", 2981 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code), 2982 pll_code.n_code, pll_code.k_code); 2983 2984 snd_soc_component_write(component, RT5645_PLL_CTRL1, 2985 pll_code.n_code << RT5645_PLL_N_SFT | pll_code.k_code); 2986 snd_soc_component_write(component, RT5645_PLL_CTRL2, 2987 ((pll_code.m_bp ? 0 : pll_code.m_code) << RT5645_PLL_M_SFT) | 2988 (pll_code.m_bp << RT5645_PLL_M_BP_SFT)); 2989 2990 rt5645->pll_in = freq_in; 2991 rt5645->pll_out = freq_out; 2992 rt5645->pll_src = source; 2993 2994 return 0; 2995 } 2996 2997 static int rt5645_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask, 2998 unsigned int rx_mask, int slots, int slot_width) 2999 { 3000 struct snd_soc_component *component = dai->component; 3001 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component); 3002 unsigned int i_slot_sft, o_slot_sft, i_width_sht, o_width_sht, en_sft; 3003 unsigned int mask, val = 0; 3004 3005 switch (rt5645->codec_type) { 3006 case CODEC_TYPE_RT5650: 3007 en_sft = 15; 3008 i_slot_sft = 10; 3009 o_slot_sft = 8; 3010 i_width_sht = 6; 3011 o_width_sht = 4; 3012 mask = 0x8ff0; 3013 break; 3014 default: 3015 en_sft = 14; 3016 i_slot_sft = o_slot_sft = 12; 3017 i_width_sht = o_width_sht = 10; 3018 mask = 0x7c00; 3019 break; 3020 } 3021 if (rx_mask || tx_mask) { 3022 val |= (1 << en_sft); 3023 if (rt5645->codec_type == CODEC_TYPE_RT5645) 3024 snd_soc_component_update_bits(component, RT5645_BASS_BACK, 3025 RT5645_G_BB_BST_MASK, RT5645_G_BB_BST_25DB); 3026 } 3027 3028 switch (slots) { 3029 case 4: 3030 val |= (1 << i_slot_sft) | (1 << o_slot_sft); 3031 break; 3032 case 6: 3033 val |= (2 << i_slot_sft) | (2 << o_slot_sft); 3034 break; 3035 case 8: 3036 val |= (3 << i_slot_sft) | (3 << o_slot_sft); 3037 break; 3038 case 2: 3039 default: 3040 break; 3041 } 3042 3043 switch (slot_width) { 3044 case 20: 3045 val |= (1 << i_width_sht) | (1 << o_width_sht); 3046 break; 3047 case 24: 3048 val |= (2 << i_width_sht) | (2 << o_width_sht); 3049 break; 3050 case 32: 3051 val |= (3 << i_width_sht) | (3 << o_width_sht); 3052 break; 3053 case 16: 3054 default: 3055 break; 3056 } 3057 3058 snd_soc_component_update_bits(component, RT5645_TDM_CTRL_1, mask, val); 3059 3060 return 0; 3061 } 3062 3063 static int rt5645_set_bias_level(struct snd_soc_component *component, 3064 enum snd_soc_bias_level level) 3065 { 3066 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component); 3067 3068 switch (level) { 3069 case SND_SOC_BIAS_PREPARE: 3070 if (SND_SOC_BIAS_STANDBY == snd_soc_component_get_bias_level(component)) { 3071 snd_soc_component_update_bits(component, RT5645_PWR_ANLG1, 3072 RT5645_PWR_VREF1 | RT5645_PWR_MB | 3073 RT5645_PWR_BG | RT5645_PWR_VREF2, 3074 RT5645_PWR_VREF1 | RT5645_PWR_MB | 3075 RT5645_PWR_BG | RT5645_PWR_VREF2); 3076 mdelay(10); 3077 snd_soc_component_update_bits(component, RT5645_PWR_ANLG1, 3078 RT5645_PWR_FV1 | RT5645_PWR_FV2, 3079 RT5645_PWR_FV1 | RT5645_PWR_FV2); 3080 snd_soc_component_update_bits(component, RT5645_GEN_CTRL1, 3081 RT5645_DIG_GATE_CTRL, RT5645_DIG_GATE_CTRL); 3082 } 3083 break; 3084 3085 case SND_SOC_BIAS_STANDBY: 3086 snd_soc_component_update_bits(component, RT5645_PWR_ANLG1, 3087 RT5645_PWR_VREF1 | RT5645_PWR_MB | 3088 RT5645_PWR_BG | RT5645_PWR_VREF2, 3089 RT5645_PWR_VREF1 | RT5645_PWR_MB | 3090 RT5645_PWR_BG | RT5645_PWR_VREF2); 3091 mdelay(10); 3092 snd_soc_component_update_bits(component, RT5645_PWR_ANLG1, 3093 RT5645_PWR_FV1 | RT5645_PWR_FV2, 3094 RT5645_PWR_FV1 | RT5645_PWR_FV2); 3095 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) { 3096 snd_soc_component_write(component, RT5645_DEPOP_M2, 0x1140); 3097 msleep(40); 3098 if (rt5645->en_button_func) 3099 queue_delayed_work(system_power_efficient_wq, 3100 &rt5645->jack_detect_work, 3101 msecs_to_jiffies(0)); 3102 } 3103 break; 3104 3105 case SND_SOC_BIAS_OFF: 3106 snd_soc_component_write(component, RT5645_DEPOP_M2, 0x1100); 3107 if (!rt5645->en_button_func) 3108 snd_soc_component_update_bits(component, RT5645_GEN_CTRL1, 3109 RT5645_DIG_GATE_CTRL, 0); 3110 snd_soc_component_update_bits(component, RT5645_PWR_ANLG1, 3111 RT5645_PWR_VREF1 | RT5645_PWR_MB | 3112 RT5645_PWR_BG | RT5645_PWR_VREF2 | 3113 RT5645_PWR_FV1 | RT5645_PWR_FV2, 0x0); 3114 break; 3115 3116 default: 3117 break; 3118 } 3119 3120 return 0; 3121 } 3122 3123 static void rt5645_enable_push_button_irq(struct snd_soc_component *component, 3124 bool enable) 3125 { 3126 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); 3127 3128 if (enable) { 3129 snd_soc_dapm_force_enable_pin(dapm, "ADC L power"); 3130 snd_soc_dapm_force_enable_pin(dapm, "ADC R power"); 3131 snd_soc_dapm_sync(dapm); 3132 3133 snd_soc_component_update_bits(component, RT5650_4BTN_IL_CMD1, 0x3, 0x3); 3134 snd_soc_component_update_bits(component, 3135 RT5645_INT_IRQ_ST, 0x8, 0x8); 3136 snd_soc_component_update_bits(component, 3137 RT5650_4BTN_IL_CMD2, 0x8000, 0x8000); 3138 snd_soc_component_read(component, RT5650_4BTN_IL_CMD1); 3139 pr_debug("%s read %x = %x\n", __func__, RT5650_4BTN_IL_CMD1, 3140 snd_soc_component_read(component, RT5650_4BTN_IL_CMD1)); 3141 } else { 3142 snd_soc_component_update_bits(component, RT5650_4BTN_IL_CMD2, 0x8000, 0x0); 3143 snd_soc_component_update_bits(component, RT5645_INT_IRQ_ST, 0x8, 0x0); 3144 3145 snd_soc_dapm_disable_pin(dapm, "ADC L power"); 3146 snd_soc_dapm_disable_pin(dapm, "ADC R power"); 3147 snd_soc_dapm_sync(dapm); 3148 } 3149 } 3150 3151 static int rt5645_jack_detect(struct snd_soc_component *component, int jack_insert) 3152 { 3153 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); 3154 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component); 3155 unsigned int val; 3156 3157 if (jack_insert) { 3158 regmap_write(rt5645->regmap, RT5645_CHARGE_PUMP, 0x0206); 3159 3160 /* for jack type detect */ 3161 snd_soc_dapm_force_enable_pin(dapm, "LDO2"); 3162 snd_soc_dapm_force_enable_pin(dapm, "Mic Det Power"); 3163 snd_soc_dapm_sync(dapm); 3164 if (!snd_soc_card_is_instantiated(dapm->card)) { 3165 /* Power up necessary bits for JD if dapm is 3166 not ready yet */ 3167 regmap_update_bits(rt5645->regmap, RT5645_PWR_ANLG1, 3168 RT5645_PWR_MB | RT5645_PWR_VREF2, 3169 RT5645_PWR_MB | RT5645_PWR_VREF2); 3170 regmap_update_bits(rt5645->regmap, RT5645_PWR_MIXER, 3171 RT5645_PWR_LDO2, RT5645_PWR_LDO2); 3172 regmap_update_bits(rt5645->regmap, RT5645_PWR_VOL, 3173 RT5645_PWR_MIC_DET, RT5645_PWR_MIC_DET); 3174 } 3175 3176 regmap_write(rt5645->regmap, RT5645_JD_CTRL3, 0x00f0); 3177 regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL2, 3178 RT5645_CBJ_MN_JD, RT5645_CBJ_MN_JD); 3179 regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL1, 3180 RT5645_CBJ_BST1_EN, RT5645_CBJ_BST1_EN); 3181 msleep(100); 3182 regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL2, 3183 RT5645_CBJ_MN_JD, 0); 3184 3185 msleep(600); 3186 regmap_read(rt5645->regmap, RT5645_IN1_CTRL3, &val); 3187 val &= 0x7; 3188 dev_dbg(component->dev, "val = %d\n", val); 3189 3190 if ((val == 1 || val == 2) && !rt5645->pdata.no_headset_mic) { 3191 rt5645->jack_type = SND_JACK_HEADSET; 3192 if (rt5645->en_button_func) { 3193 rt5645_enable_push_button_irq(component, true); 3194 } 3195 } else { 3196 snd_soc_dapm_disable_pin(dapm, "Mic Det Power"); 3197 snd_soc_dapm_sync(dapm); 3198 rt5645->jack_type = SND_JACK_HEADPHONE; 3199 } 3200 if (rt5645->pdata.level_trigger_irq) 3201 regmap_update_bits(rt5645->regmap, RT5645_IRQ_CTRL2, 3202 RT5645_JD_1_1_MASK, RT5645_JD_1_1_NOR); 3203 3204 regmap_write(rt5645->regmap, RT5645_CHARGE_PUMP, 0x0e06); 3205 } else { /* jack out */ 3206 rt5645->jack_type = 0; 3207 3208 regmap_update_bits(rt5645->regmap, RT5645_HP_VOL, 3209 RT5645_L_MUTE | RT5645_R_MUTE, 3210 RT5645_L_MUTE | RT5645_R_MUTE); 3211 regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL2, 3212 RT5645_CBJ_MN_JD, RT5645_CBJ_MN_JD); 3213 regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL1, 3214 RT5645_CBJ_BST1_EN, 0); 3215 3216 if (rt5645->en_button_func) 3217 rt5645_enable_push_button_irq(component, false); 3218 3219 if (rt5645->pdata.jd_mode == 0) 3220 snd_soc_dapm_disable_pin(dapm, "LDO2"); 3221 snd_soc_dapm_disable_pin(dapm, "Mic Det Power"); 3222 snd_soc_dapm_sync(dapm); 3223 if (rt5645->pdata.level_trigger_irq) 3224 regmap_update_bits(rt5645->regmap, RT5645_IRQ_CTRL2, 3225 RT5645_JD_1_1_MASK, RT5645_JD_1_1_INV); 3226 } 3227 3228 return rt5645->jack_type; 3229 } 3230 3231 static int rt5645_button_detect(struct snd_soc_component *component) 3232 { 3233 int btn_type, val; 3234 3235 val = snd_soc_component_read(component, RT5650_4BTN_IL_CMD1); 3236 pr_debug("val=0x%x\n", val); 3237 btn_type = val & 0xfff0; 3238 snd_soc_component_write(component, RT5650_4BTN_IL_CMD1, val); 3239 3240 return btn_type; 3241 } 3242 3243 static irqreturn_t rt5645_irq(int irq, void *data); 3244 3245 int rt5645_set_jack_detect(struct snd_soc_component *component, 3246 struct snd_soc_jack *hp_jack, struct snd_soc_jack *mic_jack, 3247 struct snd_soc_jack *btn_jack) 3248 { 3249 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component); 3250 3251 rt5645->hp_jack = hp_jack; 3252 rt5645->mic_jack = mic_jack; 3253 rt5645->btn_jack = btn_jack; 3254 if (rt5645->btn_jack && rt5645->codec_type == CODEC_TYPE_RT5650) { 3255 rt5645->en_button_func = true; 3256 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1, 3257 RT5645_GP1_PIN_IRQ, RT5645_GP1_PIN_IRQ); 3258 regmap_update_bits(rt5645->regmap, RT5645_GEN_CTRL1, 3259 RT5645_DIG_GATE_CTRL, RT5645_DIG_GATE_CTRL); 3260 regmap_update_bits(rt5645->regmap, RT5645_DEPOP_M1, 3261 RT5645_HP_CB_MASK, RT5645_HP_CB_PU); 3262 } 3263 rt5645_irq(0, rt5645); 3264 3265 return 0; 3266 } 3267 EXPORT_SYMBOL_GPL(rt5645_set_jack_detect); 3268 3269 static int rt5645_component_set_jack(struct snd_soc_component *component, 3270 struct snd_soc_jack *hs_jack, void *data) 3271 { 3272 struct snd_soc_jack *mic_jack = NULL; 3273 struct snd_soc_jack *btn_jack = NULL; 3274 int type; 3275 3276 if (hs_jack) { 3277 type = *(int *)data; 3278 3279 if (type & SND_JACK_MICROPHONE) 3280 mic_jack = hs_jack; 3281 if (type & (SND_JACK_BTN_0 | SND_JACK_BTN_1 | 3282 SND_JACK_BTN_2 | SND_JACK_BTN_3)) 3283 btn_jack = hs_jack; 3284 } 3285 3286 return rt5645_set_jack_detect(component, hs_jack, mic_jack, btn_jack); 3287 } 3288 3289 static void rt5645_jack_detect_work(struct work_struct *work) 3290 { 3291 struct rt5645_priv *rt5645 = 3292 container_of(work, struct rt5645_priv, jack_detect_work.work); 3293 int val, btn_type, gpio_state = 0, report = 0; 3294 3295 if (!rt5645->component) 3296 return; 3297 3298 switch (rt5645->pdata.jd_mode) { 3299 case 0: /* Not using rt5645 JD */ 3300 if (rt5645->gpiod_hp_det) { 3301 gpio_state = gpiod_get_value(rt5645->gpiod_hp_det); 3302 if (rt5645->pdata.inv_hp_pol) 3303 gpio_state ^= 1; 3304 dev_dbg(rt5645->component->dev, "gpio_state = %d\n", 3305 gpio_state); 3306 report = rt5645_jack_detect(rt5645->component, gpio_state); 3307 } 3308 snd_soc_jack_report(rt5645->hp_jack, 3309 report, SND_JACK_HEADPHONE); 3310 snd_soc_jack_report(rt5645->mic_jack, 3311 report, SND_JACK_MICROPHONE); 3312 return; 3313 case 4: 3314 val = snd_soc_component_read(rt5645->component, RT5645_A_JD_CTRL1) & 0x0020; 3315 break; 3316 default: /* read rt5645 jd1_1 status */ 3317 val = snd_soc_component_read(rt5645->component, RT5645_INT_IRQ_ST) & 0x1000; 3318 break; 3319 3320 } 3321 3322 if (!val && (rt5645->jack_type == 0)) { /* jack in */ 3323 report = rt5645_jack_detect(rt5645->component, 1); 3324 } else if (!val && rt5645->jack_type != 0) { 3325 /* for push button and jack out */ 3326 btn_type = 0; 3327 if (snd_soc_component_read(rt5645->component, RT5645_INT_IRQ_ST) & 0x4) { 3328 /* button pressed */ 3329 report = SND_JACK_HEADSET; 3330 btn_type = rt5645_button_detect(rt5645->component); 3331 /* rt5650 can report three kinds of button behavior, 3332 one click, double click and hold. However, 3333 currently we will report button pressed/released 3334 event. So all the three button behaviors are 3335 treated as button pressed. */ 3336 switch (btn_type) { 3337 case 0x8000: 3338 case 0x4000: 3339 case 0x2000: 3340 report |= SND_JACK_BTN_0; 3341 break; 3342 case 0x1000: 3343 case 0x0800: 3344 case 0x0400: 3345 report |= SND_JACK_BTN_1; 3346 break; 3347 case 0x0200: 3348 case 0x0100: 3349 case 0x0080: 3350 report |= SND_JACK_BTN_2; 3351 break; 3352 case 0x0040: 3353 case 0x0020: 3354 case 0x0010: 3355 report |= SND_JACK_BTN_3; 3356 break; 3357 case 0x0000: /* unpressed */ 3358 break; 3359 default: 3360 dev_err(rt5645->component->dev, 3361 "Unexpected button code 0x%04x\n", 3362 btn_type); 3363 break; 3364 } 3365 } 3366 if (btn_type == 0)/* button release */ 3367 report = rt5645->jack_type; 3368 else { 3369 mod_timer(&rt5645->btn_check_timer, 3370 msecs_to_jiffies(100)); 3371 } 3372 } else { 3373 /* jack out */ 3374 report = 0; 3375 snd_soc_component_update_bits(rt5645->component, 3376 RT5645_INT_IRQ_ST, 0x1, 0x0); 3377 rt5645_jack_detect(rt5645->component, 0); 3378 } 3379 3380 snd_soc_jack_report(rt5645->hp_jack, report, SND_JACK_HEADPHONE); 3381 snd_soc_jack_report(rt5645->mic_jack, report, SND_JACK_MICROPHONE); 3382 if (rt5645->en_button_func) 3383 snd_soc_jack_report(rt5645->btn_jack, 3384 report, SND_JACK_BTN_0 | SND_JACK_BTN_1 | 3385 SND_JACK_BTN_2 | SND_JACK_BTN_3); 3386 } 3387 3388 static void rt5645_rcclock_work(struct work_struct *work) 3389 { 3390 struct rt5645_priv *rt5645 = 3391 container_of(work, struct rt5645_priv, rcclock_work.work); 3392 3393 regmap_update_bits(rt5645->regmap, RT5645_MICBIAS, 3394 RT5645_PWR_CLK25M_MASK, RT5645_PWR_CLK25M_PD); 3395 } 3396 3397 static irqreturn_t rt5645_irq(int irq, void *data) 3398 { 3399 struct rt5645_priv *rt5645 = data; 3400 3401 queue_delayed_work(system_power_efficient_wq, 3402 &rt5645->jack_detect_work, msecs_to_jiffies(250)); 3403 3404 return IRQ_HANDLED; 3405 } 3406 3407 static void rt5645_btn_check_callback(struct timer_list *t) 3408 { 3409 struct rt5645_priv *rt5645 = from_timer(rt5645, t, btn_check_timer); 3410 3411 queue_delayed_work(system_power_efficient_wq, 3412 &rt5645->jack_detect_work, msecs_to_jiffies(5)); 3413 } 3414 3415 static int rt5645_probe(struct snd_soc_component *component) 3416 { 3417 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); 3418 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component); 3419 3420 rt5645->component = component; 3421 3422 switch (rt5645->codec_type) { 3423 case CODEC_TYPE_RT5645: 3424 snd_soc_dapm_new_controls(dapm, 3425 rt5645_specific_dapm_widgets, 3426 ARRAY_SIZE(rt5645_specific_dapm_widgets)); 3427 snd_soc_dapm_add_routes(dapm, 3428 rt5645_specific_dapm_routes, 3429 ARRAY_SIZE(rt5645_specific_dapm_routes)); 3430 if (rt5645->v_id < 3) { 3431 snd_soc_dapm_add_routes(dapm, 3432 rt5645_old_dapm_routes, 3433 ARRAY_SIZE(rt5645_old_dapm_routes)); 3434 } 3435 break; 3436 case CODEC_TYPE_RT5650: 3437 snd_soc_dapm_new_controls(dapm, 3438 rt5650_specific_dapm_widgets, 3439 ARRAY_SIZE(rt5650_specific_dapm_widgets)); 3440 snd_soc_dapm_add_routes(dapm, 3441 rt5650_specific_dapm_routes, 3442 ARRAY_SIZE(rt5650_specific_dapm_routes)); 3443 break; 3444 } 3445 3446 snd_soc_component_force_bias_level(component, SND_SOC_BIAS_OFF); 3447 3448 /* for JD function */ 3449 if (rt5645->pdata.jd_mode) { 3450 snd_soc_dapm_force_enable_pin(dapm, "JD Power"); 3451 snd_soc_dapm_force_enable_pin(dapm, "LDO2"); 3452 snd_soc_dapm_sync(dapm); 3453 } 3454 3455 if (rt5645->pdata.long_name) 3456 component->card->long_name = rt5645->pdata.long_name; 3457 3458 rt5645->eq_param = devm_kcalloc(component->dev, 3459 RT5645_HWEQ_NUM, sizeof(struct rt5645_eq_param_s), 3460 GFP_KERNEL); 3461 3462 if (!rt5645->eq_param) 3463 return -ENOMEM; 3464 3465 return 0; 3466 } 3467 3468 static void rt5645_remove(struct snd_soc_component *component) 3469 { 3470 rt5645_reset(component); 3471 } 3472 3473 #ifdef CONFIG_PM 3474 static int rt5645_suspend(struct snd_soc_component *component) 3475 { 3476 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component); 3477 3478 regcache_cache_only(rt5645->regmap, true); 3479 regcache_mark_dirty(rt5645->regmap); 3480 3481 return 0; 3482 } 3483 3484 static int rt5645_resume(struct snd_soc_component *component) 3485 { 3486 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component); 3487 3488 regcache_cache_only(rt5645->regmap, false); 3489 regcache_sync(rt5645->regmap); 3490 3491 return 0; 3492 } 3493 #else 3494 #define rt5645_suspend NULL 3495 #define rt5645_resume NULL 3496 #endif 3497 3498 #define RT5645_STEREO_RATES SNDRV_PCM_RATE_8000_96000 3499 #define RT5645_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ 3500 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8) 3501 3502 static const struct snd_soc_dai_ops rt5645_aif_dai_ops = { 3503 .hw_params = rt5645_hw_params, 3504 .set_fmt = rt5645_set_dai_fmt, 3505 .set_sysclk = rt5645_set_dai_sysclk, 3506 .set_tdm_slot = rt5645_set_tdm_slot, 3507 .set_pll = rt5645_set_dai_pll, 3508 }; 3509 3510 static struct snd_soc_dai_driver rt5645_dai[] = { 3511 { 3512 .name = "rt5645-aif1", 3513 .id = RT5645_AIF1, 3514 .playback = { 3515 .stream_name = "AIF1 Playback", 3516 .channels_min = 1, 3517 .channels_max = 2, 3518 .rates = RT5645_STEREO_RATES, 3519 .formats = RT5645_FORMATS, 3520 }, 3521 .capture = { 3522 .stream_name = "AIF1 Capture", 3523 .channels_min = 1, 3524 .channels_max = 4, 3525 .rates = RT5645_STEREO_RATES, 3526 .formats = RT5645_FORMATS, 3527 }, 3528 .ops = &rt5645_aif_dai_ops, 3529 }, 3530 { 3531 .name = "rt5645-aif2", 3532 .id = RT5645_AIF2, 3533 .playback = { 3534 .stream_name = "AIF2 Playback", 3535 .channels_min = 1, 3536 .channels_max = 2, 3537 .rates = RT5645_STEREO_RATES, 3538 .formats = RT5645_FORMATS, 3539 }, 3540 .capture = { 3541 .stream_name = "AIF2 Capture", 3542 .channels_min = 1, 3543 .channels_max = 2, 3544 .rates = RT5645_STEREO_RATES, 3545 .formats = RT5645_FORMATS, 3546 }, 3547 .ops = &rt5645_aif_dai_ops, 3548 }, 3549 }; 3550 3551 static const struct snd_soc_component_driver soc_component_dev_rt5645 = { 3552 .probe = rt5645_probe, 3553 .remove = rt5645_remove, 3554 .suspend = rt5645_suspend, 3555 .resume = rt5645_resume, 3556 .set_bias_level = rt5645_set_bias_level, 3557 .controls = rt5645_snd_controls, 3558 .num_controls = ARRAY_SIZE(rt5645_snd_controls), 3559 .dapm_widgets = rt5645_dapm_widgets, 3560 .num_dapm_widgets = ARRAY_SIZE(rt5645_dapm_widgets), 3561 .dapm_routes = rt5645_dapm_routes, 3562 .num_dapm_routes = ARRAY_SIZE(rt5645_dapm_routes), 3563 .set_jack = rt5645_component_set_jack, 3564 .use_pmdown_time = 1, 3565 .endianness = 1, 3566 }; 3567 3568 static const struct regmap_config rt5645_regmap = { 3569 .reg_bits = 8, 3570 .val_bits = 16, 3571 .use_single_read = true, 3572 .use_single_write = true, 3573 .max_register = RT5645_VENDOR_ID2 + 1 + (ARRAY_SIZE(rt5645_ranges) * 3574 RT5645_PR_SPACING), 3575 .volatile_reg = rt5645_volatile_register, 3576 .readable_reg = rt5645_readable_register, 3577 3578 .cache_type = REGCACHE_MAPLE, 3579 .reg_defaults = rt5645_reg, 3580 .num_reg_defaults = ARRAY_SIZE(rt5645_reg), 3581 .ranges = rt5645_ranges, 3582 .num_ranges = ARRAY_SIZE(rt5645_ranges), 3583 }; 3584 3585 static const struct regmap_config rt5650_regmap = { 3586 .reg_bits = 8, 3587 .val_bits = 16, 3588 .use_single_read = true, 3589 .use_single_write = true, 3590 .max_register = RT5645_VENDOR_ID2 + 1 + (ARRAY_SIZE(rt5645_ranges) * 3591 RT5645_PR_SPACING), 3592 .volatile_reg = rt5645_volatile_register, 3593 .readable_reg = rt5645_readable_register, 3594 3595 .cache_type = REGCACHE_MAPLE, 3596 .reg_defaults = rt5650_reg, 3597 .num_reg_defaults = ARRAY_SIZE(rt5650_reg), 3598 .ranges = rt5645_ranges, 3599 .num_ranges = ARRAY_SIZE(rt5645_ranges), 3600 }; 3601 3602 static const struct regmap_config temp_regmap = { 3603 .name="nocache", 3604 .reg_bits = 8, 3605 .val_bits = 16, 3606 .use_single_read = true, 3607 .use_single_write = true, 3608 .max_register = RT5645_VENDOR_ID2 + 1, 3609 .cache_type = REGCACHE_NONE, 3610 }; 3611 3612 static const struct i2c_device_id rt5645_i2c_id[] = { 3613 { "rt5645", 0 }, 3614 { "rt5650", 0 }, 3615 { } 3616 }; 3617 MODULE_DEVICE_TABLE(i2c, rt5645_i2c_id); 3618 3619 #ifdef CONFIG_OF 3620 static const struct of_device_id rt5645_of_match[] = { 3621 { .compatible = "realtek,rt5645", }, 3622 { .compatible = "realtek,rt5650", }, 3623 { } 3624 }; 3625 MODULE_DEVICE_TABLE(of, rt5645_of_match); 3626 #endif 3627 3628 #ifdef CONFIG_ACPI 3629 static const struct acpi_device_id rt5645_acpi_match[] = { 3630 { "10EC5645", 0 }, 3631 { "10EC5648", 0 }, 3632 { "10EC5650", 0 }, 3633 { "10EC5640", 0 }, 3634 { "10EC3270", 0 }, 3635 {}, 3636 }; 3637 MODULE_DEVICE_TABLE(acpi, rt5645_acpi_match); 3638 #endif 3639 3640 static const struct rt5645_platform_data intel_braswell_platform_data = { 3641 .dmic1_data_pin = RT5645_DMIC1_DISABLE, 3642 .dmic2_data_pin = RT5645_DMIC_DATA_IN2P, 3643 .jd_mode = 3, 3644 }; 3645 3646 static const struct rt5645_platform_data buddy_platform_data = { 3647 .dmic1_data_pin = RT5645_DMIC_DATA_GPIO5, 3648 .dmic2_data_pin = RT5645_DMIC_DATA_IN2P, 3649 .jd_mode = 4, 3650 .level_trigger_irq = true, 3651 }; 3652 3653 static const struct rt5645_platform_data gpd_win_platform_data = { 3654 .jd_mode = 3, 3655 .inv_jd1_1 = true, 3656 .long_name = "gpd-win-pocket-rt5645", 3657 /* The GPD pocket has a diff. mic, for the win this does not matter. */ 3658 .in2_diff = true, 3659 }; 3660 3661 static const struct rt5645_platform_data asus_t100ha_platform_data = { 3662 .dmic1_data_pin = RT5645_DMIC_DATA_IN2N, 3663 .dmic2_data_pin = RT5645_DMIC2_DISABLE, 3664 .jd_mode = 3, 3665 .inv_jd1_1 = true, 3666 }; 3667 3668 static const struct rt5645_platform_data asus_t101ha_platform_data = { 3669 .dmic1_data_pin = RT5645_DMIC_DATA_IN2N, 3670 .dmic2_data_pin = RT5645_DMIC2_DISABLE, 3671 .jd_mode = 3, 3672 }; 3673 3674 static const struct rt5645_platform_data lenovo_ideapad_miix_310_pdata = { 3675 .jd_mode = 3, 3676 .in2_diff = true, 3677 }; 3678 3679 static const struct rt5645_platform_data jd_mode3_platform_data = { 3680 .jd_mode = 3, 3681 }; 3682 3683 static const struct rt5645_platform_data lattepanda_board_platform_data = { 3684 .jd_mode = 2, 3685 .inv_jd1_1 = true 3686 }; 3687 3688 static const struct rt5645_platform_data kahlee_platform_data = { 3689 .dmic1_data_pin = RT5645_DMIC_DATA_GPIO5, 3690 .dmic2_data_pin = RT5645_DMIC_DATA_IN2P, 3691 .jd_mode = 3, 3692 }; 3693 3694 static const struct rt5645_platform_data ecs_ef20_platform_data = { 3695 .dmic1_data_pin = RT5645_DMIC1_DISABLE, 3696 .dmic2_data_pin = RT5645_DMIC_DATA_IN2P, 3697 .inv_hp_pol = 1, 3698 }; 3699 3700 static const struct acpi_gpio_params ef20_hp_detect = { 1, 0, false }; 3701 3702 static const struct acpi_gpio_mapping cht_rt5645_ef20_gpios[] = { 3703 { "hp-detect-gpios", &ef20_hp_detect, 1 }, 3704 { }, 3705 }; 3706 3707 static int cht_rt5645_ef20_quirk_cb(const struct dmi_system_id *id) 3708 { 3709 cht_rt5645_gpios = cht_rt5645_ef20_gpios; 3710 return 1; 3711 } 3712 3713 static const struct dmi_system_id dmi_platform_data[] = { 3714 { 3715 .ident = "Chrome Buddy", 3716 .matches = { 3717 DMI_MATCH(DMI_PRODUCT_NAME, "Buddy"), 3718 }, 3719 .driver_data = (void *)&buddy_platform_data, 3720 }, 3721 { 3722 .ident = "Intel Strago", 3723 .matches = { 3724 DMI_MATCH(DMI_PRODUCT_NAME, "Strago"), 3725 }, 3726 .driver_data = (void *)&intel_braswell_platform_data, 3727 }, 3728 { 3729 .ident = "Google Chrome", 3730 .matches = { 3731 DMI_MATCH(DMI_SYS_VENDOR, "GOOGLE"), 3732 }, 3733 .driver_data = (void *)&intel_braswell_platform_data, 3734 }, 3735 { 3736 .ident = "Google Setzer", 3737 .matches = { 3738 DMI_MATCH(DMI_PRODUCT_NAME, "Setzer"), 3739 }, 3740 .driver_data = (void *)&intel_braswell_platform_data, 3741 }, 3742 { 3743 .ident = "Microsoft Surface 3", 3744 .matches = { 3745 DMI_MATCH(DMI_PRODUCT_NAME, "Surface 3"), 3746 }, 3747 .driver_data = (void *)&intel_braswell_platform_data, 3748 }, 3749 { 3750 /* 3751 * Match for the GPDwin which unfortunately uses somewhat 3752 * generic dmi strings, which is why we test for 4 strings. 3753 * Comparing against 23 other byt/cht boards, board_vendor 3754 * and board_name are unique to the GPDwin, where as only one 3755 * other board has the same board_serial and 3 others have 3756 * the same default product_name. Also the GPDwin is the 3757 * only device to have both board_ and product_name not set. 3758 */ 3759 .ident = "GPD Win / Pocket", 3760 .matches = { 3761 DMI_MATCH(DMI_BOARD_VENDOR, "AMI Corporation"), 3762 DMI_MATCH(DMI_BOARD_NAME, "Default string"), 3763 DMI_MATCH(DMI_BOARD_SERIAL, "Default string"), 3764 DMI_MATCH(DMI_PRODUCT_NAME, "Default string"), 3765 }, 3766 .driver_data = (void *)&gpd_win_platform_data, 3767 }, 3768 { 3769 .ident = "ASUS T100HAN", 3770 .matches = { 3771 DMI_EXACT_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."), 3772 DMI_MATCH(DMI_PRODUCT_NAME, "T100HAN"), 3773 }, 3774 .driver_data = (void *)&asus_t100ha_platform_data, 3775 }, 3776 { 3777 .ident = "ASUS T101HA", 3778 .matches = { 3779 DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."), 3780 DMI_MATCH(DMI_PRODUCT_NAME, "T101HA"), 3781 }, 3782 .driver_data = (void *)&asus_t101ha_platform_data, 3783 }, 3784 { 3785 .ident = "MINIX Z83-4", 3786 .matches = { 3787 DMI_EXACT_MATCH(DMI_SYS_VENDOR, "MINIX"), 3788 DMI_MATCH(DMI_PRODUCT_NAME, "Z83-4"), 3789 }, 3790 .driver_data = (void *)&jd_mode3_platform_data, 3791 }, 3792 { 3793 .ident = "Teclast X80 Pro", 3794 .matches = { 3795 DMI_MATCH(DMI_SYS_VENDOR, "TECLAST"), 3796 DMI_MATCH(DMI_PRODUCT_NAME, "X80 Pro"), 3797 }, 3798 .driver_data = (void *)&jd_mode3_platform_data, 3799 }, 3800 { 3801 .ident = "Lenovo Ideapad Miix 310", 3802 .matches = { 3803 DMI_EXACT_MATCH(DMI_SYS_VENDOR, "LENOVO"), 3804 DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "80SG"), 3805 DMI_EXACT_MATCH(DMI_PRODUCT_VERSION, "MIIX 310-10ICR"), 3806 }, 3807 .driver_data = (void *)&lenovo_ideapad_miix_310_pdata, 3808 }, 3809 { 3810 .ident = "Lenovo Ideapad Miix 320", 3811 .matches = { 3812 DMI_EXACT_MATCH(DMI_SYS_VENDOR, "LENOVO"), 3813 DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "80XF"), 3814 DMI_EXACT_MATCH(DMI_PRODUCT_VERSION, "Lenovo MIIX 320-10ICR"), 3815 }, 3816 .driver_data = (void *)&intel_braswell_platform_data, 3817 }, 3818 { 3819 .ident = "LattePanda board", 3820 .matches = { 3821 DMI_EXACT_MATCH(DMI_BOARD_VENDOR, "AMI Corporation"), 3822 DMI_EXACT_MATCH(DMI_BOARD_NAME, "Cherry Trail CR"), 3823 DMI_EXACT_MATCH(DMI_BOARD_VERSION, "Default string"), 3824 }, 3825 .driver_data = (void *)&lattepanda_board_platform_data, 3826 }, 3827 { 3828 .ident = "Chrome Kahlee", 3829 .matches = { 3830 DMI_MATCH(DMI_PRODUCT_NAME, "Kahlee"), 3831 }, 3832 .driver_data = (void *)&kahlee_platform_data, 3833 }, 3834 { 3835 .ident = "Medion E1239T", 3836 .matches = { 3837 DMI_EXACT_MATCH(DMI_SYS_VENDOR, "MEDION"), 3838 DMI_MATCH(DMI_PRODUCT_NAME, "E1239T MD60568"), 3839 }, 3840 .driver_data = (void *)&intel_braswell_platform_data, 3841 }, 3842 { 3843 .ident = "EF20", 3844 .callback = cht_rt5645_ef20_quirk_cb, 3845 .matches = { 3846 DMI_MATCH(DMI_PRODUCT_NAME, "EF20"), 3847 }, 3848 .driver_data = (void *)&ecs_ef20_platform_data, 3849 }, 3850 { 3851 .ident = "EF20EA", 3852 .callback = cht_rt5645_ef20_quirk_cb, 3853 .matches = { 3854 DMI_MATCH(DMI_PRODUCT_NAME, "EF20EA"), 3855 }, 3856 .driver_data = (void *)&ecs_ef20_platform_data, 3857 }, 3858 { } 3859 }; 3860 3861 static bool rt5645_check_dp(struct device *dev) 3862 { 3863 if (device_property_present(dev, "realtek,in2-differential") || 3864 device_property_present(dev, "realtek,dmic1-data-pin") || 3865 device_property_present(dev, "realtek,dmic2-data-pin") || 3866 device_property_present(dev, "realtek,jd-mode")) 3867 return true; 3868 3869 return false; 3870 } 3871 3872 static int rt5645_parse_dt(struct rt5645_priv *rt5645, struct device *dev) 3873 { 3874 rt5645->pdata.in2_diff = device_property_read_bool(dev, 3875 "realtek,in2-differential"); 3876 device_property_read_u32(dev, 3877 "realtek,dmic1-data-pin", &rt5645->pdata.dmic1_data_pin); 3878 device_property_read_u32(dev, 3879 "realtek,dmic2-data-pin", &rt5645->pdata.dmic2_data_pin); 3880 device_property_read_u32(dev, 3881 "realtek,jd-mode", &rt5645->pdata.jd_mode); 3882 3883 return 0; 3884 } 3885 3886 static int rt5645_i2c_probe(struct i2c_client *i2c) 3887 { 3888 struct rt5645_platform_data *pdata = NULL; 3889 const struct dmi_system_id *dmi_data; 3890 struct rt5645_priv *rt5645; 3891 int ret, i; 3892 unsigned int val; 3893 struct regmap *regmap; 3894 3895 rt5645 = devm_kzalloc(&i2c->dev, sizeof(struct rt5645_priv), 3896 GFP_KERNEL); 3897 if (rt5645 == NULL) 3898 return -ENOMEM; 3899 3900 rt5645->i2c = i2c; 3901 i2c_set_clientdata(i2c, rt5645); 3902 3903 dmi_data = dmi_first_match(dmi_platform_data); 3904 if (dmi_data) { 3905 dev_info(&i2c->dev, "Detected %s platform\n", dmi_data->ident); 3906 pdata = dmi_data->driver_data; 3907 } 3908 3909 if (pdata) 3910 rt5645->pdata = *pdata; 3911 else if (rt5645_check_dp(&i2c->dev)) 3912 rt5645_parse_dt(rt5645, &i2c->dev); 3913 else 3914 rt5645->pdata = jd_mode3_platform_data; 3915 3916 if (quirk != -1) { 3917 rt5645->pdata.in2_diff = QUIRK_IN2_DIFF(quirk); 3918 rt5645->pdata.level_trigger_irq = QUIRK_LEVEL_IRQ(quirk); 3919 rt5645->pdata.inv_jd1_1 = QUIRK_INV_JD1_1(quirk); 3920 rt5645->pdata.inv_hp_pol = QUIRK_INV_HP_POL(quirk); 3921 rt5645->pdata.jd_mode = QUIRK_JD_MODE(quirk); 3922 rt5645->pdata.dmic1_data_pin = QUIRK_DMIC1_DATA_PIN(quirk); 3923 rt5645->pdata.dmic2_data_pin = QUIRK_DMIC2_DATA_PIN(quirk); 3924 } 3925 3926 if (has_acpi_companion(&i2c->dev)) { 3927 if (cht_rt5645_gpios) { 3928 if (devm_acpi_dev_add_driver_gpios(&i2c->dev, cht_rt5645_gpios)) 3929 dev_dbg(&i2c->dev, "Failed to add driver gpios\n"); 3930 } 3931 3932 /* The ALC3270 package has the headset-mic pin not-connected */ 3933 if (acpi_dev_hid_uid_match(ACPI_COMPANION(&i2c->dev), "10EC3270", NULL)) 3934 rt5645->pdata.no_headset_mic = true; 3935 } 3936 3937 rt5645->gpiod_hp_det = devm_gpiod_get_optional(&i2c->dev, "hp-detect", 3938 GPIOD_IN); 3939 3940 if (IS_ERR(rt5645->gpiod_hp_det)) { 3941 dev_info(&i2c->dev, "failed to initialize gpiod\n"); 3942 ret = PTR_ERR(rt5645->gpiod_hp_det); 3943 /* 3944 * Continue if optional gpiod is missing, bail for all other 3945 * errors, including -EPROBE_DEFER 3946 */ 3947 if (ret != -ENOENT) 3948 return ret; 3949 } 3950 3951 for (i = 0; i < ARRAY_SIZE(rt5645->supplies); i++) 3952 rt5645->supplies[i].supply = rt5645_supply_names[i]; 3953 3954 ret = devm_regulator_bulk_get(&i2c->dev, 3955 ARRAY_SIZE(rt5645->supplies), 3956 rt5645->supplies); 3957 if (ret) { 3958 dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret); 3959 return ret; 3960 } 3961 3962 ret = regulator_bulk_enable(ARRAY_SIZE(rt5645->supplies), 3963 rt5645->supplies); 3964 if (ret) { 3965 dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret); 3966 return ret; 3967 } 3968 3969 regmap = devm_regmap_init_i2c(i2c, &temp_regmap); 3970 if (IS_ERR(regmap)) { 3971 ret = PTR_ERR(regmap); 3972 dev_err(&i2c->dev, "Failed to allocate temp register map: %d\n", 3973 ret); 3974 goto err_enable; 3975 } 3976 3977 /* 3978 * Read after 400msec, as it is the interval required between 3979 * read and power On. 3980 */ 3981 msleep(TIME_TO_POWER_MS); 3982 ret = regmap_read(regmap, RT5645_VENDOR_ID2, &val); 3983 if (ret < 0) { 3984 dev_err(&i2c->dev, "Failed to read: 0x%02X\n, ret = %d", RT5645_VENDOR_ID2, ret); 3985 goto err_enable; 3986 } 3987 3988 switch (val) { 3989 case RT5645_DEVICE_ID: 3990 rt5645->regmap = devm_regmap_init_i2c(i2c, &rt5645_regmap); 3991 rt5645->codec_type = CODEC_TYPE_RT5645; 3992 break; 3993 case RT5650_DEVICE_ID: 3994 rt5645->regmap = devm_regmap_init_i2c(i2c, &rt5650_regmap); 3995 rt5645->codec_type = CODEC_TYPE_RT5650; 3996 break; 3997 default: 3998 dev_err(&i2c->dev, 3999 "Device with ID register %#x is not rt5645 or rt5650\n", 4000 val); 4001 ret = -ENODEV; 4002 goto err_enable; 4003 } 4004 4005 if (IS_ERR(rt5645->regmap)) { 4006 ret = PTR_ERR(rt5645->regmap); 4007 dev_err(&i2c->dev, "Failed to allocate register map: %d\n", 4008 ret); 4009 goto err_enable; 4010 } 4011 4012 regmap_write(rt5645->regmap, RT5645_RESET, 0); 4013 4014 regmap_read(regmap, RT5645_VENDOR_ID, &val); 4015 rt5645->v_id = val & 0xff; 4016 4017 regmap_write(rt5645->regmap, RT5645_AD_DA_MIXER, 0x8080); 4018 4019 ret = regmap_multi_reg_write(rt5645->regmap, init_list, 4020 ARRAY_SIZE(init_list)); 4021 if (ret != 0) 4022 dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret); 4023 4024 if (rt5645->codec_type == CODEC_TYPE_RT5650) { 4025 ret = regmap_multi_reg_write(rt5645->regmap, rt5650_init_list, 4026 ARRAY_SIZE(rt5650_init_list)); 4027 if (ret != 0) 4028 dev_warn(&i2c->dev, "Apply rt5650 patch failed: %d\n", 4029 ret); 4030 } 4031 4032 regmap_update_bits(rt5645->regmap, RT5645_CLSD_OUT_CTRL, 0xc0, 0xc0); 4033 4034 if (rt5645->pdata.in2_diff) 4035 regmap_update_bits(rt5645->regmap, RT5645_IN2_CTRL, 4036 RT5645_IN_DF2, RT5645_IN_DF2); 4037 4038 if (rt5645->pdata.dmic1_data_pin || rt5645->pdata.dmic2_data_pin) { 4039 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1, 4040 RT5645_GP2_PIN_MASK, RT5645_GP2_PIN_DMIC1_SCL); 4041 } 4042 switch (rt5645->pdata.dmic1_data_pin) { 4043 case RT5645_DMIC_DATA_IN2N: 4044 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1, 4045 RT5645_DMIC_1_DP_MASK, RT5645_DMIC_1_DP_IN2N); 4046 break; 4047 4048 case RT5645_DMIC_DATA_GPIO5: 4049 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1, 4050 RT5645_I2S2_DAC_PIN_MASK, RT5645_I2S2_DAC_PIN_GPIO); 4051 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1, 4052 RT5645_DMIC_1_DP_MASK, RT5645_DMIC_1_DP_GPIO5); 4053 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1, 4054 RT5645_GP5_PIN_MASK, RT5645_GP5_PIN_DMIC1_SDA); 4055 break; 4056 4057 case RT5645_DMIC_DATA_GPIO11: 4058 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1, 4059 RT5645_DMIC_1_DP_MASK, RT5645_DMIC_1_DP_GPIO11); 4060 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1, 4061 RT5645_GP11_PIN_MASK, 4062 RT5645_GP11_PIN_DMIC1_SDA); 4063 break; 4064 4065 default: 4066 break; 4067 } 4068 4069 switch (rt5645->pdata.dmic2_data_pin) { 4070 case RT5645_DMIC_DATA_IN2P: 4071 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1, 4072 RT5645_DMIC_2_DP_MASK, RT5645_DMIC_2_DP_IN2P); 4073 break; 4074 4075 case RT5645_DMIC_DATA_GPIO6: 4076 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1, 4077 RT5645_DMIC_2_DP_MASK, RT5645_DMIC_2_DP_GPIO6); 4078 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1, 4079 RT5645_GP6_PIN_MASK, RT5645_GP6_PIN_DMIC2_SDA); 4080 break; 4081 4082 case RT5645_DMIC_DATA_GPIO10: 4083 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1, 4084 RT5645_DMIC_2_DP_MASK, RT5645_DMIC_2_DP_GPIO10); 4085 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1, 4086 RT5645_GP10_PIN_MASK, 4087 RT5645_GP10_PIN_DMIC2_SDA); 4088 break; 4089 4090 case RT5645_DMIC_DATA_GPIO12: 4091 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1, 4092 RT5645_DMIC_2_DP_MASK, RT5645_DMIC_2_DP_GPIO12); 4093 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1, 4094 RT5645_GP12_PIN_MASK, 4095 RT5645_GP12_PIN_DMIC2_SDA); 4096 break; 4097 4098 default: 4099 break; 4100 } 4101 4102 if (rt5645->pdata.jd_mode) { 4103 regmap_update_bits(rt5645->regmap, RT5645_GEN_CTRL3, 4104 RT5645_IRQ_CLK_GATE_CTRL, 4105 RT5645_IRQ_CLK_GATE_CTRL); 4106 regmap_update_bits(rt5645->regmap, RT5645_MICBIAS, 4107 RT5645_IRQ_CLK_INT, RT5645_IRQ_CLK_INT); 4108 regmap_update_bits(rt5645->regmap, RT5645_IRQ_CTRL2, 4109 RT5645_IRQ_JD_1_1_EN, RT5645_IRQ_JD_1_1_EN); 4110 regmap_update_bits(rt5645->regmap, RT5645_GEN_CTRL3, 4111 RT5645_JD_PSV_MODE, RT5645_JD_PSV_MODE); 4112 regmap_update_bits(rt5645->regmap, RT5645_HPO_MIXER, 4113 RT5645_IRQ_PSV_MODE, RT5645_IRQ_PSV_MODE); 4114 regmap_update_bits(rt5645->regmap, RT5645_MICBIAS, 4115 RT5645_MIC2_OVCD_EN, RT5645_MIC2_OVCD_EN); 4116 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1, 4117 RT5645_GP1_PIN_IRQ, RT5645_GP1_PIN_IRQ); 4118 switch (rt5645->pdata.jd_mode) { 4119 case 1: 4120 regmap_update_bits(rt5645->regmap, RT5645_A_JD_CTRL1, 4121 RT5645_JD1_MODE_MASK, 4122 RT5645_JD1_MODE_0); 4123 break; 4124 case 2: 4125 regmap_update_bits(rt5645->regmap, RT5645_A_JD_CTRL1, 4126 RT5645_JD1_MODE_MASK, 4127 RT5645_JD1_MODE_1); 4128 break; 4129 case 3: 4130 case 4: 4131 regmap_update_bits(rt5645->regmap, RT5645_A_JD_CTRL1, 4132 RT5645_JD1_MODE_MASK, 4133 RT5645_JD1_MODE_2); 4134 break; 4135 default: 4136 break; 4137 } 4138 if (rt5645->pdata.inv_jd1_1) { 4139 regmap_update_bits(rt5645->regmap, RT5645_IRQ_CTRL2, 4140 RT5645_JD_1_1_MASK, RT5645_JD_1_1_INV); 4141 } 4142 } 4143 4144 regmap_update_bits(rt5645->regmap, RT5645_ADDA_CLK1, 4145 RT5645_I2S_PD1_MASK, RT5645_I2S_PD1_2); 4146 4147 if (rt5645->pdata.level_trigger_irq) { 4148 regmap_update_bits(rt5645->regmap, RT5645_IRQ_CTRL2, 4149 RT5645_JD_1_1_MASK, RT5645_JD_1_1_INV); 4150 } 4151 timer_setup(&rt5645->btn_check_timer, rt5645_btn_check_callback, 0); 4152 4153 INIT_DELAYED_WORK(&rt5645->jack_detect_work, rt5645_jack_detect_work); 4154 INIT_DELAYED_WORK(&rt5645->rcclock_work, rt5645_rcclock_work); 4155 4156 if (rt5645->i2c->irq) { 4157 ret = request_threaded_irq(rt5645->i2c->irq, NULL, rt5645_irq, 4158 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING 4159 | IRQF_ONESHOT, "rt5645", rt5645); 4160 if (ret) { 4161 dev_err(&i2c->dev, "Failed to reguest IRQ: %d\n", ret); 4162 goto err_enable; 4163 } 4164 } 4165 4166 ret = devm_snd_soc_register_component(&i2c->dev, &soc_component_dev_rt5645, 4167 rt5645_dai, ARRAY_SIZE(rt5645_dai)); 4168 if (ret) 4169 goto err_irq; 4170 4171 return 0; 4172 4173 err_irq: 4174 if (rt5645->i2c->irq) 4175 free_irq(rt5645->i2c->irq, rt5645); 4176 err_enable: 4177 regulator_bulk_disable(ARRAY_SIZE(rt5645->supplies), rt5645->supplies); 4178 return ret; 4179 } 4180 4181 static void rt5645_i2c_remove(struct i2c_client *i2c) 4182 { 4183 struct rt5645_priv *rt5645 = i2c_get_clientdata(i2c); 4184 4185 if (i2c->irq) 4186 free_irq(i2c->irq, rt5645); 4187 4188 /* 4189 * Since the rt5645_btn_check_callback() can queue jack_detect_work, 4190 * the timer need to be delted first 4191 */ 4192 del_timer_sync(&rt5645->btn_check_timer); 4193 4194 cancel_delayed_work_sync(&rt5645->jack_detect_work); 4195 cancel_delayed_work_sync(&rt5645->rcclock_work); 4196 4197 regulator_bulk_disable(ARRAY_SIZE(rt5645->supplies), rt5645->supplies); 4198 } 4199 4200 static void rt5645_i2c_shutdown(struct i2c_client *i2c) 4201 { 4202 struct rt5645_priv *rt5645 = i2c_get_clientdata(i2c); 4203 4204 regmap_update_bits(rt5645->regmap, RT5645_GEN_CTRL3, 4205 RT5645_RING2_SLEEVE_GND, RT5645_RING2_SLEEVE_GND); 4206 regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL2, RT5645_CBJ_MN_JD, 4207 RT5645_CBJ_MN_JD); 4208 regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL1, RT5645_CBJ_BST1_EN, 4209 0); 4210 msleep(20); 4211 regmap_write(rt5645->regmap, RT5645_RESET, 0); 4212 } 4213 4214 static int __maybe_unused rt5645_sys_suspend(struct device *dev) 4215 { 4216 struct rt5645_priv *rt5645 = dev_get_drvdata(dev); 4217 4218 del_timer_sync(&rt5645->btn_check_timer); 4219 cancel_delayed_work_sync(&rt5645->jack_detect_work); 4220 cancel_delayed_work_sync(&rt5645->rcclock_work); 4221 4222 regcache_cache_only(rt5645->regmap, true); 4223 regcache_mark_dirty(rt5645->regmap); 4224 return 0; 4225 } 4226 4227 static int __maybe_unused rt5645_sys_resume(struct device *dev) 4228 { 4229 struct rt5645_priv *rt5645 = dev_get_drvdata(dev); 4230 4231 regcache_cache_only(rt5645->regmap, false); 4232 regcache_sync(rt5645->regmap); 4233 4234 if (rt5645->hp_jack) { 4235 rt5645->jack_type = 0; 4236 rt5645_jack_detect_work(&rt5645->jack_detect_work.work); 4237 } 4238 return 0; 4239 } 4240 4241 static const struct dev_pm_ops rt5645_pm = { 4242 SET_SYSTEM_SLEEP_PM_OPS(rt5645_sys_suspend, rt5645_sys_resume) 4243 }; 4244 4245 static struct i2c_driver rt5645_i2c_driver = { 4246 .driver = { 4247 .name = "rt5645", 4248 .of_match_table = of_match_ptr(rt5645_of_match), 4249 .acpi_match_table = ACPI_PTR(rt5645_acpi_match), 4250 .pm = &rt5645_pm, 4251 }, 4252 .probe = rt5645_i2c_probe, 4253 .remove = rt5645_i2c_remove, 4254 .shutdown = rt5645_i2c_shutdown, 4255 .id_table = rt5645_i2c_id, 4256 }; 4257 module_i2c_driver(rt5645_i2c_driver); 4258 4259 MODULE_DESCRIPTION("ASoC RT5645 driver"); 4260 MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>"); 4261 MODULE_LICENSE("GPL v2"); 4262