1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * rt5645.c -- RT5645 ALSA SoC audio codec driver
4 *
5 * Copyright 2013 Realtek Semiconductor Corp.
6 * Author: Bard Liao <bardliao@realtek.com>
7 */
8
9 #include <linux/module.h>
10 #include <linux/moduleparam.h>
11 #include <linux/init.h>
12 #include <linux/delay.h>
13 #include <linux/pm.h>
14 #include <linux/i2c.h>
15 #include <linux/platform_device.h>
16 #include <linux/spi/spi.h>
17 #include <linux/gpio/consumer.h>
18 #include <linux/acpi.h>
19 #include <linux/dmi.h>
20 #include <linux/regulator/consumer.h>
21 #include <sound/core.h>
22 #include <sound/pcm.h>
23 #include <sound/pcm_params.h>
24 #include <sound/jack.h>
25 #include <sound/soc.h>
26 #include <sound/soc-dapm.h>
27 #include <sound/initval.h>
28 #include <sound/tlv.h>
29
30 #include "rl6231.h"
31 #include "rt5645.h"
32
33 #define QUIRK_INV_JD1_1(q) ((q) & 1)
34 #define QUIRK_LEVEL_IRQ(q) (((q) >> 1) & 1)
35 #define QUIRK_IN2_DIFF(q) (((q) >> 2) & 1)
36 #define QUIRK_INV_HP_POL(q) (((q) >> 3) & 1)
37 #define QUIRK_JD_MODE(q) (((q) >> 4) & 7)
38 #define QUIRK_DMIC1_DATA_PIN(q) (((q) >> 8) & 3)
39 #define QUIRK_DMIC2_DATA_PIN(q) (((q) >> 12) & 3)
40
41 static unsigned int quirk = -1;
42 module_param(quirk, uint, 0444);
43 MODULE_PARM_DESC(quirk, "RT5645 pdata quirk override");
44
45 static const struct acpi_gpio_mapping *cht_rt5645_gpios;
46
47 #define RT5645_DEVICE_ID 0x6308
48 #define RT5650_DEVICE_ID 0x6419
49
50 #define RT5645_PR_RANGE_BASE (0xff + 1)
51 #define RT5645_PR_SPACING 0x100
52
53 #define RT5645_PR_BASE (RT5645_PR_RANGE_BASE + (0 * RT5645_PR_SPACING))
54
55 #define RT5645_HWEQ_NUM 57
56
57 #define TIME_TO_POWER_MS 400
58
59 static const struct regmap_range_cfg rt5645_ranges[] = {
60 {
61 .name = "PR",
62 .range_min = RT5645_PR_BASE,
63 .range_max = RT5645_PR_BASE + 0xf8,
64 .selector_reg = RT5645_PRIV_INDEX,
65 .selector_mask = 0xff,
66 .selector_shift = 0x0,
67 .window_start = RT5645_PRIV_DATA,
68 .window_len = 0x1,
69 },
70 };
71
72 static const struct reg_sequence init_list[] = {
73 {RT5645_PR_BASE + 0x3d, 0x3600},
74 {RT5645_PR_BASE + 0x1c, 0xfd70},
75 {RT5645_PR_BASE + 0x20, 0x611f},
76 {RT5645_PR_BASE + 0x21, 0x4040},
77 {RT5645_PR_BASE + 0x23, 0x0004},
78 {RT5645_ASRC_4, 0x0120},
79 };
80
81 static const struct reg_sequence rt5650_init_list[] = {
82 {0xf6, 0x0100},
83 {RT5645_PWR_ANLG1, 0x02},
84 };
85
86 static const struct reg_default rt5645_reg[] = {
87 { 0x00, 0x0000 },
88 { 0x01, 0xc8c8 },
89 { 0x02, 0xc8c8 },
90 { 0x03, 0xc8c8 },
91 { 0x0a, 0x0002 },
92 { 0x0b, 0x2827 },
93 { 0x0c, 0xe000 },
94 { 0x0d, 0x0000 },
95 { 0x0e, 0x0000 },
96 { 0x0f, 0x0808 },
97 { 0x14, 0x3333 },
98 { 0x16, 0x4b00 },
99 { 0x18, 0x018b },
100 { 0x19, 0xafaf },
101 { 0x1a, 0xafaf },
102 { 0x1b, 0x0001 },
103 { 0x1c, 0x2f2f },
104 { 0x1d, 0x2f2f },
105 { 0x1e, 0x0000 },
106 { 0x20, 0x0000 },
107 { 0x27, 0x7060 },
108 { 0x28, 0x7070 },
109 { 0x29, 0x8080 },
110 { 0x2a, 0x5656 },
111 { 0x2b, 0x5454 },
112 { 0x2c, 0xaaa0 },
113 { 0x2d, 0x0000 },
114 { 0x2f, 0x1002 },
115 { 0x31, 0x5000 },
116 { 0x32, 0x0000 },
117 { 0x33, 0x0000 },
118 { 0x34, 0x0000 },
119 { 0x35, 0x0000 },
120 { 0x3b, 0x0000 },
121 { 0x3c, 0x007f },
122 { 0x3d, 0x0000 },
123 { 0x3e, 0x007f },
124 { 0x3f, 0x0000 },
125 { 0x40, 0x001f },
126 { 0x41, 0x0000 },
127 { 0x42, 0x001f },
128 { 0x45, 0x6000 },
129 { 0x46, 0x003e },
130 { 0x47, 0x003e },
131 { 0x48, 0xf807 },
132 { 0x4a, 0x0004 },
133 { 0x4d, 0x0000 },
134 { 0x4e, 0x0000 },
135 { 0x4f, 0x01ff },
136 { 0x50, 0x0000 },
137 { 0x51, 0x0000 },
138 { 0x52, 0x01ff },
139 { 0x53, 0xf000 },
140 { 0x56, 0x0111 },
141 { 0x57, 0x0064 },
142 { 0x58, 0xef0e },
143 { 0x59, 0xf0f0 },
144 { 0x5a, 0xef0e },
145 { 0x5b, 0xf0f0 },
146 { 0x5c, 0xef0e },
147 { 0x5d, 0xf0f0 },
148 { 0x5e, 0xf000 },
149 { 0x5f, 0x0000 },
150 { 0x61, 0x0300 },
151 { 0x62, 0x0000 },
152 { 0x63, 0x00c2 },
153 { 0x64, 0x0000 },
154 { 0x65, 0x0000 },
155 { 0x66, 0x0000 },
156 { 0x6a, 0x0000 },
157 { 0x6c, 0x0aaa },
158 { 0x70, 0x8000 },
159 { 0x71, 0x8000 },
160 { 0x72, 0x8000 },
161 { 0x73, 0x7770 },
162 { 0x74, 0x3e00 },
163 { 0x75, 0x2409 },
164 { 0x76, 0x000a },
165 { 0x77, 0x0c00 },
166 { 0x78, 0x0000 },
167 { 0x79, 0x0123 },
168 { 0x80, 0x0000 },
169 { 0x81, 0x0000 },
170 { 0x82, 0x0000 },
171 { 0x83, 0x0000 },
172 { 0x84, 0x0000 },
173 { 0x85, 0x0000 },
174 { 0x8a, 0x0120 },
175 { 0x8e, 0x0004 },
176 { 0x8f, 0x1100 },
177 { 0x90, 0x0646 },
178 { 0x91, 0x0c06 },
179 { 0x93, 0x0000 },
180 { 0x94, 0x0200 },
181 { 0x95, 0x0000 },
182 { 0x9a, 0x2184 },
183 { 0x9b, 0x010a },
184 { 0x9c, 0x0aea },
185 { 0x9d, 0x000c },
186 { 0x9e, 0x0400 },
187 { 0xa0, 0xa0a8 },
188 { 0xa1, 0x0059 },
189 { 0xa2, 0x0001 },
190 { 0xae, 0x6000 },
191 { 0xaf, 0x0000 },
192 { 0xb0, 0x6000 },
193 { 0xb1, 0x0000 },
194 { 0xb2, 0x0000 },
195 { 0xb3, 0x001f },
196 { 0xb4, 0x020c },
197 { 0xb5, 0x1f00 },
198 { 0xb6, 0x0000 },
199 { 0xbb, 0x0000 },
200 { 0xbc, 0x0000 },
201 { 0xbd, 0x0000 },
202 { 0xbe, 0x0000 },
203 { 0xbf, 0x3100 },
204 { 0xc0, 0x0000 },
205 { 0xc1, 0x0000 },
206 { 0xc2, 0x0000 },
207 { 0xc3, 0x2000 },
208 { 0xcd, 0x0000 },
209 { 0xce, 0x0000 },
210 { 0xcf, 0x1813 },
211 { 0xd0, 0x0690 },
212 { 0xd1, 0x1c17 },
213 { 0xd3, 0xb320 },
214 { 0xd4, 0x0000 },
215 { 0xd6, 0x0400 },
216 { 0xd9, 0x0809 },
217 { 0xda, 0x0000 },
218 { 0xdb, 0x0003 },
219 { 0xdc, 0x0049 },
220 { 0xdd, 0x001b },
221 { 0xdf, 0x0008 },
222 { 0xe0, 0x4000 },
223 { 0xe6, 0x8000 },
224 { 0xe7, 0x0200 },
225 { 0xec, 0xb300 },
226 { 0xed, 0x0000 },
227 { 0xf0, 0x001f },
228 { 0xf1, 0x020c },
229 { 0xf2, 0x1f00 },
230 { 0xf3, 0x0000 },
231 { 0xf4, 0x4000 },
232 { 0xf8, 0x0000 },
233 { 0xf9, 0x0000 },
234 { 0xfa, 0x2060 },
235 { 0xfb, 0x4040 },
236 { 0xfc, 0x0000 },
237 { 0xfd, 0x0002 },
238 { 0xfe, 0x10ec },
239 { 0xff, 0x6308 },
240 };
241
242 static const struct reg_default rt5650_reg[] = {
243 { 0x00, 0x0000 },
244 { 0x01, 0xc8c8 },
245 { 0x02, 0xc8c8 },
246 { 0x03, 0xc8c8 },
247 { 0x0a, 0x0002 },
248 { 0x0b, 0x2827 },
249 { 0x0c, 0xe000 },
250 { 0x0d, 0x0000 },
251 { 0x0e, 0x0000 },
252 { 0x0f, 0x0808 },
253 { 0x14, 0x3333 },
254 { 0x16, 0x4b00 },
255 { 0x18, 0x018b },
256 { 0x19, 0xafaf },
257 { 0x1a, 0xafaf },
258 { 0x1b, 0x0001 },
259 { 0x1c, 0x2f2f },
260 { 0x1d, 0x2f2f },
261 { 0x1e, 0x0000 },
262 { 0x20, 0x0000 },
263 { 0x27, 0x7060 },
264 { 0x28, 0x7070 },
265 { 0x29, 0x8080 },
266 { 0x2a, 0x5656 },
267 { 0x2b, 0x5454 },
268 { 0x2c, 0xaaa0 },
269 { 0x2d, 0x0000 },
270 { 0x2f, 0x5002 },
271 { 0x31, 0x5000 },
272 { 0x32, 0x0000 },
273 { 0x33, 0x0000 },
274 { 0x34, 0x0000 },
275 { 0x35, 0x0000 },
276 { 0x3b, 0x0000 },
277 { 0x3c, 0x007f },
278 { 0x3d, 0x0000 },
279 { 0x3e, 0x007f },
280 { 0x3f, 0x0000 },
281 { 0x40, 0x001f },
282 { 0x41, 0x0000 },
283 { 0x42, 0x001f },
284 { 0x45, 0x6000 },
285 { 0x46, 0x003e },
286 { 0x47, 0x003e },
287 { 0x48, 0xf807 },
288 { 0x4a, 0x0004 },
289 { 0x4d, 0x0000 },
290 { 0x4e, 0x0000 },
291 { 0x4f, 0x01ff },
292 { 0x50, 0x0000 },
293 { 0x51, 0x0000 },
294 { 0x52, 0x01ff },
295 { 0x53, 0xf000 },
296 { 0x56, 0x0111 },
297 { 0x57, 0x0064 },
298 { 0x58, 0xef0e },
299 { 0x59, 0xf0f0 },
300 { 0x5a, 0xef0e },
301 { 0x5b, 0xf0f0 },
302 { 0x5c, 0xef0e },
303 { 0x5d, 0xf0f0 },
304 { 0x5e, 0xf000 },
305 { 0x5f, 0x0000 },
306 { 0x61, 0x0300 },
307 { 0x62, 0x0000 },
308 { 0x63, 0x00c2 },
309 { 0x64, 0x0000 },
310 { 0x65, 0x0000 },
311 { 0x66, 0x0000 },
312 { 0x6a, 0x0000 },
313 { 0x6c, 0x0aaa },
314 { 0x70, 0x8000 },
315 { 0x71, 0x8000 },
316 { 0x72, 0x8000 },
317 { 0x73, 0x7770 },
318 { 0x74, 0x3e00 },
319 { 0x75, 0x2409 },
320 { 0x76, 0x000a },
321 { 0x77, 0x0c00 },
322 { 0x78, 0x0000 },
323 { 0x79, 0x0123 },
324 { 0x7a, 0x0123 },
325 { 0x80, 0x0000 },
326 { 0x81, 0x0000 },
327 { 0x82, 0x0000 },
328 { 0x83, 0x0000 },
329 { 0x84, 0x0000 },
330 { 0x85, 0x0000 },
331 { 0x8a, 0x0120 },
332 { 0x8e, 0x0004 },
333 { 0x8f, 0x1100 },
334 { 0x90, 0x0646 },
335 { 0x91, 0x0c06 },
336 { 0x93, 0x0000 },
337 { 0x94, 0x0200 },
338 { 0x95, 0x0000 },
339 { 0x9a, 0x2184 },
340 { 0x9b, 0x010a },
341 { 0x9c, 0x0aea },
342 { 0x9d, 0x000c },
343 { 0x9e, 0x0400 },
344 { 0xa0, 0xa0a8 },
345 { 0xa1, 0x0059 },
346 { 0xa2, 0x0001 },
347 { 0xae, 0x6000 },
348 { 0xaf, 0x0000 },
349 { 0xb0, 0x6000 },
350 { 0xb1, 0x0000 },
351 { 0xb2, 0x0000 },
352 { 0xb3, 0x001f },
353 { 0xb4, 0x020c },
354 { 0xb5, 0x1f00 },
355 { 0xb6, 0x0000 },
356 { 0xbb, 0x0000 },
357 { 0xbc, 0x0000 },
358 { 0xbd, 0x0000 },
359 { 0xbe, 0x0000 },
360 { 0xbf, 0x3100 },
361 { 0xc0, 0x0000 },
362 { 0xc1, 0x0000 },
363 { 0xc2, 0x0000 },
364 { 0xc3, 0x2000 },
365 { 0xcd, 0x0000 },
366 { 0xce, 0x0000 },
367 { 0xcf, 0x1813 },
368 { 0xd0, 0x0690 },
369 { 0xd1, 0x1c17 },
370 { 0xd3, 0xb320 },
371 { 0xd4, 0x0000 },
372 { 0xd6, 0x0400 },
373 { 0xd9, 0x0809 },
374 { 0xda, 0x0000 },
375 { 0xdb, 0x0003 },
376 { 0xdc, 0x0049 },
377 { 0xdd, 0x001b },
378 { 0xdf, 0x0008 },
379 { 0xe0, 0x4000 },
380 { 0xe6, 0x8000 },
381 { 0xe7, 0x0200 },
382 { 0xec, 0xb300 },
383 { 0xed, 0x0000 },
384 { 0xf0, 0x001f },
385 { 0xf1, 0x020c },
386 { 0xf2, 0x1f00 },
387 { 0xf3, 0x0000 },
388 { 0xf4, 0x4000 },
389 { 0xf8, 0x0000 },
390 { 0xf9, 0x0000 },
391 { 0xfa, 0x2060 },
392 { 0xfb, 0x4040 },
393 { 0xfc, 0x0000 },
394 { 0xfd, 0x0002 },
395 { 0xfe, 0x10ec },
396 { 0xff, 0x6308 },
397 };
398
399 struct rt5645_eq_param_s {
400 unsigned short reg;
401 unsigned short val;
402 };
403
404 struct rt5645_eq_param_s_be16 {
405 __be16 reg;
406 __be16 val;
407 };
408
409 static const char *const rt5645_supply_names[] = {
410 "avdd",
411 "cpvdd",
412 };
413
414 struct rt5645_platform_data {
415 /* IN2 can optionally be differential */
416 bool in2_diff;
417
418 unsigned int dmic1_data_pin;
419 /* 0 = IN2N; 1 = GPIO5; 2 = GPIO11 */
420 unsigned int dmic2_data_pin;
421 /* 0 = IN2P; 1 = GPIO6; 2 = GPIO10; 3 = GPIO12 */
422
423 unsigned int jd_mode;
424 /* Use level triggered irq */
425 bool level_trigger_irq;
426 /* Invert JD1_1 status polarity */
427 bool inv_jd1_1;
428 /* Invert HP detect status polarity */
429 bool inv_hp_pol;
430
431 /* Value to assign to snd_soc_card.long_name */
432 const char *long_name;
433
434 /* Some (package) variants have the headset-mic pin not-connected */
435 bool no_headset_mic;
436 };
437
438 struct rt5645_priv {
439 struct snd_soc_component *component;
440 struct rt5645_platform_data pdata;
441 struct regmap *regmap;
442 struct i2c_client *i2c;
443 struct gpio_desc *gpiod_hp_det;
444 struct gpio_desc *gpiod_cbj_sleeve;
445 struct snd_soc_jack *hp_jack;
446 struct snd_soc_jack *mic_jack;
447 struct snd_soc_jack *btn_jack;
448 struct delayed_work jack_detect_work, rcclock_work;
449 struct regulator_bulk_data supplies[ARRAY_SIZE(rt5645_supply_names)];
450 struct rt5645_eq_param_s *eq_param;
451 struct timer_list btn_check_timer;
452 struct mutex jd_mutex;
453
454 int codec_type;
455 int sysclk;
456 int sysclk_src;
457 int lrck[RT5645_AIFS];
458 int bclk[RT5645_AIFS];
459 int master[RT5645_AIFS];
460
461 int pll_src;
462 int pll_in;
463 int pll_out;
464
465 int jack_type;
466 bool en_button_func;
467 int v_id;
468 };
469
rt5645_reset(struct snd_soc_component * component)470 static int rt5645_reset(struct snd_soc_component *component)
471 {
472 return snd_soc_component_write(component, RT5645_RESET, 0);
473 }
474
rt5645_volatile_register(struct device * dev,unsigned int reg)475 static bool rt5645_volatile_register(struct device *dev, unsigned int reg)
476 {
477 int i;
478
479 for (i = 0; i < ARRAY_SIZE(rt5645_ranges); i++) {
480 if (reg >= rt5645_ranges[i].range_min &&
481 reg <= rt5645_ranges[i].range_max) {
482 return true;
483 }
484 }
485
486 switch (reg) {
487 case RT5645_RESET:
488 case RT5645_PRIV_INDEX:
489 case RT5645_PRIV_DATA:
490 case RT5645_IN1_CTRL1:
491 case RT5645_IN1_CTRL2:
492 case RT5645_IN1_CTRL3:
493 case RT5645_A_JD_CTRL1:
494 case RT5645_ADC_EQ_CTRL1:
495 case RT5645_EQ_CTRL1:
496 case RT5645_ALC_CTRL_1:
497 case RT5645_IRQ_CTRL2:
498 case RT5645_IRQ_CTRL3:
499 case RT5645_INT_IRQ_ST:
500 case RT5645_IL_CMD:
501 case RT5650_4BTN_IL_CMD1:
502 case RT5645_VENDOR_ID:
503 case RT5645_VENDOR_ID1:
504 case RT5645_VENDOR_ID2:
505 return true;
506 default:
507 return false;
508 }
509 }
510
rt5645_readable_register(struct device * dev,unsigned int reg)511 static bool rt5645_readable_register(struct device *dev, unsigned int reg)
512 {
513 int i;
514
515 for (i = 0; i < ARRAY_SIZE(rt5645_ranges); i++) {
516 if (reg >= rt5645_ranges[i].range_min &&
517 reg <= rt5645_ranges[i].range_max) {
518 return true;
519 }
520 }
521
522 switch (reg) {
523 case RT5645_RESET:
524 case RT5645_SPK_VOL:
525 case RT5645_HP_VOL:
526 case RT5645_LOUT1:
527 case RT5645_IN1_CTRL1:
528 case RT5645_IN1_CTRL2:
529 case RT5645_IN1_CTRL3:
530 case RT5645_IN2_CTRL:
531 case RT5645_INL1_INR1_VOL:
532 case RT5645_SPK_FUNC_LIM:
533 case RT5645_ADJ_HPF_CTRL:
534 case RT5645_DAC1_DIG_VOL:
535 case RT5645_DAC2_DIG_VOL:
536 case RT5645_DAC_CTRL:
537 case RT5645_STO1_ADC_DIG_VOL:
538 case RT5645_MONO_ADC_DIG_VOL:
539 case RT5645_ADC_BST_VOL1:
540 case RT5645_ADC_BST_VOL2:
541 case RT5645_STO1_ADC_MIXER:
542 case RT5645_MONO_ADC_MIXER:
543 case RT5645_AD_DA_MIXER:
544 case RT5645_STO_DAC_MIXER:
545 case RT5645_MONO_DAC_MIXER:
546 case RT5645_DIG_MIXER:
547 case RT5650_A_DAC_SOUR:
548 case RT5645_DIG_INF1_DATA:
549 case RT5645_PDM_OUT_CTRL:
550 case RT5645_REC_L1_MIXER:
551 case RT5645_REC_L2_MIXER:
552 case RT5645_REC_R1_MIXER:
553 case RT5645_REC_R2_MIXER:
554 case RT5645_HPMIXL_CTRL:
555 case RT5645_HPOMIXL_CTRL:
556 case RT5645_HPMIXR_CTRL:
557 case RT5645_HPOMIXR_CTRL:
558 case RT5645_HPO_MIXER:
559 case RT5645_SPK_L_MIXER:
560 case RT5645_SPK_R_MIXER:
561 case RT5645_SPO_MIXER:
562 case RT5645_SPO_CLSD_RATIO:
563 case RT5645_OUT_L1_MIXER:
564 case RT5645_OUT_R1_MIXER:
565 case RT5645_OUT_L_GAIN1:
566 case RT5645_OUT_L_GAIN2:
567 case RT5645_OUT_R_GAIN1:
568 case RT5645_OUT_R_GAIN2:
569 case RT5645_LOUT_MIXER:
570 case RT5645_HAPTIC_CTRL1:
571 case RT5645_HAPTIC_CTRL2:
572 case RT5645_HAPTIC_CTRL3:
573 case RT5645_HAPTIC_CTRL4:
574 case RT5645_HAPTIC_CTRL5:
575 case RT5645_HAPTIC_CTRL6:
576 case RT5645_HAPTIC_CTRL7:
577 case RT5645_HAPTIC_CTRL8:
578 case RT5645_HAPTIC_CTRL9:
579 case RT5645_HAPTIC_CTRL10:
580 case RT5645_PWR_DIG1:
581 case RT5645_PWR_DIG2:
582 case RT5645_PWR_ANLG1:
583 case RT5645_PWR_ANLG2:
584 case RT5645_PWR_MIXER:
585 case RT5645_PWR_VOL:
586 case RT5645_PRIV_INDEX:
587 case RT5645_PRIV_DATA:
588 case RT5645_I2S1_SDP:
589 case RT5645_I2S2_SDP:
590 case RT5645_ADDA_CLK1:
591 case RT5645_ADDA_CLK2:
592 case RT5645_DMIC_CTRL1:
593 case RT5645_DMIC_CTRL2:
594 case RT5645_TDM_CTRL_1:
595 case RT5645_TDM_CTRL_2:
596 case RT5645_TDM_CTRL_3:
597 case RT5650_TDM_CTRL_4:
598 case RT5645_GLB_CLK:
599 case RT5645_PLL_CTRL1:
600 case RT5645_PLL_CTRL2:
601 case RT5645_ASRC_1:
602 case RT5645_ASRC_2:
603 case RT5645_ASRC_3:
604 case RT5645_ASRC_4:
605 case RT5645_DEPOP_M1:
606 case RT5645_DEPOP_M2:
607 case RT5645_DEPOP_M3:
608 case RT5645_CHARGE_PUMP:
609 case RT5645_MICBIAS:
610 case RT5645_A_JD_CTRL1:
611 case RT5645_VAD_CTRL4:
612 case RT5645_CLSD_OUT_CTRL:
613 case RT5645_ADC_EQ_CTRL1:
614 case RT5645_ADC_EQ_CTRL2:
615 case RT5645_EQ_CTRL1:
616 case RT5645_EQ_CTRL2:
617 case RT5645_ALC_CTRL_1:
618 case RT5645_ALC_CTRL_2:
619 case RT5645_ALC_CTRL_3:
620 case RT5645_ALC_CTRL_4:
621 case RT5645_ALC_CTRL_5:
622 case RT5645_JD_CTRL:
623 case RT5645_IRQ_CTRL1:
624 case RT5645_IRQ_CTRL2:
625 case RT5645_IRQ_CTRL3:
626 case RT5645_INT_IRQ_ST:
627 case RT5645_GPIO_CTRL1:
628 case RT5645_GPIO_CTRL2:
629 case RT5645_GPIO_CTRL3:
630 case RT5645_BASS_BACK:
631 case RT5645_MP3_PLUS1:
632 case RT5645_MP3_PLUS2:
633 case RT5645_ADJ_HPF1:
634 case RT5645_ADJ_HPF2:
635 case RT5645_HP_CALIB_AMP_DET:
636 case RT5645_SV_ZCD1:
637 case RT5645_SV_ZCD2:
638 case RT5645_IL_CMD:
639 case RT5645_IL_CMD2:
640 case RT5645_IL_CMD3:
641 case RT5650_4BTN_IL_CMD1:
642 case RT5650_4BTN_IL_CMD2:
643 case RT5645_DRC1_HL_CTRL1:
644 case RT5645_DRC2_HL_CTRL1:
645 case RT5645_ADC_MONO_HP_CTRL1:
646 case RT5645_ADC_MONO_HP_CTRL2:
647 case RT5645_DRC2_CTRL1:
648 case RT5645_DRC2_CTRL2:
649 case RT5645_DRC2_CTRL3:
650 case RT5645_DRC2_CTRL4:
651 case RT5645_DRC2_CTRL5:
652 case RT5645_JD_CTRL3:
653 case RT5645_JD_CTRL4:
654 case RT5645_GEN_CTRL1:
655 case RT5645_GEN_CTRL2:
656 case RT5645_GEN_CTRL3:
657 case RT5645_VENDOR_ID:
658 case RT5645_VENDOR_ID1:
659 case RT5645_VENDOR_ID2:
660 return true;
661 default:
662 return false;
663 }
664 }
665
666 static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -4650, 150, 0);
667 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6525, 75, 0);
668 static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -3450, 150, 0);
669 static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0);
670 static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
671
672 /* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
673 static const DECLARE_TLV_DB_RANGE(bst_tlv,
674 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
675 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
676 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
677 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
678 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
679 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
680 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0)
681 );
682
683 /* {-6, -4.5, -3, -1.5, 0, 0.82, 1.58, 2.28} dB */
684 static const DECLARE_TLV_DB_RANGE(spk_clsd_tlv,
685 0, 4, TLV_DB_SCALE_ITEM(-600, 150, 0),
686 5, 5, TLV_DB_SCALE_ITEM(82, 0, 0),
687 6, 6, TLV_DB_SCALE_ITEM(158, 0, 0),
688 7, 7, TLV_DB_SCALE_ITEM(228, 0, 0)
689 );
690
rt5645_hweq_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)691 static int rt5645_hweq_info(struct snd_kcontrol *kcontrol,
692 struct snd_ctl_elem_info *uinfo)
693 {
694 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
695 uinfo->count = RT5645_HWEQ_NUM * sizeof(struct rt5645_eq_param_s);
696
697 return 0;
698 }
699
rt5645_hweq_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)700 static int rt5645_hweq_get(struct snd_kcontrol *kcontrol,
701 struct snd_ctl_elem_value *ucontrol)
702 {
703 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
704 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
705 struct rt5645_eq_param_s_be16 *eq_param =
706 (struct rt5645_eq_param_s_be16 *)ucontrol->value.bytes.data;
707 int i;
708
709 for (i = 0; i < RT5645_HWEQ_NUM; i++) {
710 eq_param[i].reg = cpu_to_be16(rt5645->eq_param[i].reg);
711 eq_param[i].val = cpu_to_be16(rt5645->eq_param[i].val);
712 }
713
714 return 0;
715 }
716
rt5645_validate_hweq(unsigned short reg)717 static bool rt5645_validate_hweq(unsigned short reg)
718 {
719 if ((reg >= 0x1a4 && reg <= 0x1cd) || (reg >= 0x1e5 && reg <= 0x1f8) ||
720 (reg == RT5645_EQ_CTRL2))
721 return true;
722
723 return false;
724 }
725
rt5645_hweq_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)726 static int rt5645_hweq_put(struct snd_kcontrol *kcontrol,
727 struct snd_ctl_elem_value *ucontrol)
728 {
729 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
730 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
731 struct rt5645_eq_param_s_be16 *eq_param =
732 (struct rt5645_eq_param_s_be16 *)ucontrol->value.bytes.data;
733 int i;
734
735 for (i = 0; i < RT5645_HWEQ_NUM; i++) {
736 rt5645->eq_param[i].reg = be16_to_cpu(eq_param[i].reg);
737 rt5645->eq_param[i].val = be16_to_cpu(eq_param[i].val);
738 }
739
740 /* The final setting of the table should be RT5645_EQ_CTRL2 */
741 for (i = RT5645_HWEQ_NUM - 1; i >= 0; i--) {
742 if (rt5645->eq_param[i].reg == 0)
743 continue;
744 else if (rt5645->eq_param[i].reg != RT5645_EQ_CTRL2)
745 return 0;
746 else
747 break;
748 }
749
750 for (i = 0; i < RT5645_HWEQ_NUM; i++) {
751 if (!rt5645_validate_hweq(rt5645->eq_param[i].reg) &&
752 rt5645->eq_param[i].reg != 0)
753 return 0;
754 else if (rt5645->eq_param[i].reg == 0)
755 break;
756 }
757
758 return 0;
759 }
760
761 #define RT5645_HWEQ(xname) \
762 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
763 .info = rt5645_hweq_info, \
764 .get = rt5645_hweq_get, \
765 .put = rt5645_hweq_put \
766 }
767
rt5645_spk_put_volsw(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)768 static int rt5645_spk_put_volsw(struct snd_kcontrol *kcontrol,
769 struct snd_ctl_elem_value *ucontrol)
770 {
771 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
772 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
773 int ret;
774
775 regmap_update_bits(rt5645->regmap, RT5645_MICBIAS,
776 RT5645_PWR_CLK25M_MASK, RT5645_PWR_CLK25M_PU);
777
778 ret = snd_soc_put_volsw(kcontrol, ucontrol);
779
780 mod_delayed_work(system_power_efficient_wq, &rt5645->rcclock_work,
781 msecs_to_jiffies(200));
782
783 return ret;
784 }
785
786 static const char * const rt5645_dac1_vol_ctrl_mode_text[] = {
787 "immediately", "zero crossing", "soft ramp"
788 };
789
790 static SOC_ENUM_SINGLE_DECL(
791 rt5645_dac1_vol_ctrl_mode, RT5645_PR_BASE,
792 RT5645_DA1_ZDET_SFT, rt5645_dac1_vol_ctrl_mode_text);
793
794 static const struct snd_kcontrol_new rt5645_snd_controls[] = {
795 /* Speaker Output Volume */
796 SOC_DOUBLE("Speaker Channel Switch", RT5645_SPK_VOL,
797 RT5645_VOL_L_SFT, RT5645_VOL_R_SFT, 1, 1),
798 SOC_DOUBLE_EXT_TLV("Speaker Playback Volume", RT5645_SPK_VOL,
799 RT5645_L_VOL_SFT, RT5645_R_VOL_SFT, 39, 1, snd_soc_get_volsw,
800 rt5645_spk_put_volsw, out_vol_tlv),
801
802 /* ClassD modulator Speaker Gain Ratio */
803 SOC_SINGLE_TLV("Speaker ClassD Playback Volume", RT5645_SPO_CLSD_RATIO,
804 RT5645_SPK_G_CLSD_SFT, 7, 0, spk_clsd_tlv),
805
806 /* Headphone Output Volume */
807 SOC_DOUBLE("Headphone Channel Switch", RT5645_HP_VOL,
808 RT5645_VOL_L_SFT, RT5645_VOL_R_SFT, 1, 1),
809 SOC_DOUBLE_TLV("Headphone Playback Volume", RT5645_HP_VOL,
810 RT5645_L_VOL_SFT, RT5645_R_VOL_SFT, 39, 1, out_vol_tlv),
811
812 /* OUTPUT Control */
813 SOC_DOUBLE("OUT Playback Switch", RT5645_LOUT1,
814 RT5645_L_MUTE_SFT, RT5645_R_MUTE_SFT, 1, 1),
815 SOC_DOUBLE("OUT Channel Switch", RT5645_LOUT1,
816 RT5645_VOL_L_SFT, RT5645_VOL_R_SFT, 1, 1),
817 SOC_DOUBLE_TLV("OUT Playback Volume", RT5645_LOUT1,
818 RT5645_L_VOL_SFT, RT5645_R_VOL_SFT, 39, 1, out_vol_tlv),
819
820 /* DAC Digital Volume */
821 SOC_DOUBLE("DAC2 Playback Switch", RT5645_DAC_CTRL,
822 RT5645_M_DAC_L2_VOL_SFT, RT5645_M_DAC_R2_VOL_SFT, 1, 1),
823 SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5645_DAC1_DIG_VOL,
824 RT5645_L_VOL_SFT + 1, RT5645_R_VOL_SFT + 1, 87, 0, dac_vol_tlv),
825 SOC_DOUBLE_TLV("Mono DAC Playback Volume", RT5645_DAC2_DIG_VOL,
826 RT5645_L_VOL_SFT + 1, RT5645_R_VOL_SFT + 1, 87, 0, dac_vol_tlv),
827
828 /* IN1/IN2 Control */
829 SOC_SINGLE_TLV("IN1 Boost", RT5645_IN1_CTRL1,
830 RT5645_BST_SFT1, 12, 0, bst_tlv),
831 SOC_SINGLE_TLV("IN2 Boost", RT5645_IN2_CTRL,
832 RT5645_BST_SFT2, 8, 0, bst_tlv),
833
834 /* INL/INR Volume Control */
835 SOC_DOUBLE_TLV("IN Capture Volume", RT5645_INL1_INR1_VOL,
836 RT5645_INL_VOL_SFT, RT5645_INR_VOL_SFT, 31, 1, in_vol_tlv),
837
838 /* ADC Digital Volume Control */
839 SOC_DOUBLE("ADC Capture Switch", RT5645_STO1_ADC_DIG_VOL,
840 RT5645_L_MUTE_SFT, RT5645_R_MUTE_SFT, 1, 1),
841 SOC_DOUBLE_TLV("ADC Capture Volume", RT5645_STO1_ADC_DIG_VOL,
842 RT5645_L_VOL_SFT + 1, RT5645_R_VOL_SFT + 1, 63, 0, adc_vol_tlv),
843 SOC_DOUBLE("Mono ADC Capture Switch", RT5645_MONO_ADC_DIG_VOL,
844 RT5645_L_MUTE_SFT, RT5645_R_MUTE_SFT, 1, 1),
845 SOC_DOUBLE_TLV("Mono ADC Capture Volume", RT5645_MONO_ADC_DIG_VOL,
846 RT5645_L_VOL_SFT + 1, RT5645_R_VOL_SFT + 1, 63, 0, adc_vol_tlv),
847
848 /* ADC Boost Volume Control */
849 SOC_DOUBLE_TLV("ADC Boost Capture Volume", RT5645_ADC_BST_VOL1,
850 RT5645_STO1_ADC_L_BST_SFT, RT5645_STO1_ADC_R_BST_SFT, 3, 0,
851 adc_bst_tlv),
852 SOC_DOUBLE_TLV("Mono ADC Boost Capture Volume", RT5645_ADC_BST_VOL2,
853 RT5645_MONO_ADC_L_BST_SFT, RT5645_MONO_ADC_R_BST_SFT, 3, 0,
854 adc_bst_tlv),
855
856 /* I2S2 function select */
857 SOC_SINGLE("I2S2 Func Switch", RT5645_GPIO_CTRL1, RT5645_I2S2_SEL_SFT,
858 1, 1),
859 RT5645_HWEQ("Speaker HWEQ"),
860
861 /* Digital Soft Volume Control */
862 SOC_ENUM("DAC1 Digital Volume Control Func", rt5645_dac1_vol_ctrl_mode),
863 };
864
865 /**
866 * set_dmic_clk - Set parameter of dmic.
867 *
868 * @w: DAPM widget.
869 * @kcontrol: The kcontrol of this widget.
870 * @event: Event id.
871 *
872 */
set_dmic_clk(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)873 static int set_dmic_clk(struct snd_soc_dapm_widget *w,
874 struct snd_kcontrol *kcontrol, int event)
875 {
876 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
877 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
878 int idx, rate;
879
880 rate = rt5645->sysclk / rl6231_get_pre_div(rt5645->regmap,
881 RT5645_ADDA_CLK1, RT5645_I2S_PD1_SFT);
882 idx = rl6231_calc_dmic_clk(rate);
883 if (idx < 0)
884 dev_err(component->dev, "Failed to set DMIC clock\n");
885 else
886 snd_soc_component_update_bits(component, RT5645_DMIC_CTRL1,
887 RT5645_DMIC_CLK_MASK, idx << RT5645_DMIC_CLK_SFT);
888 return idx;
889 }
890
is_sys_clk_from_pll(struct snd_soc_dapm_widget * source,struct snd_soc_dapm_widget * sink)891 static int is_sys_clk_from_pll(struct snd_soc_dapm_widget *source,
892 struct snd_soc_dapm_widget *sink)
893 {
894 struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm);
895 unsigned int val;
896
897 val = snd_soc_component_read(component, RT5645_GLB_CLK);
898 val &= RT5645_SCLK_SRC_MASK;
899 if (val == RT5645_SCLK_SRC_PLL1)
900 return 1;
901 else
902 return 0;
903 }
904
is_using_asrc(struct snd_soc_dapm_widget * source,struct snd_soc_dapm_widget * sink)905 static int is_using_asrc(struct snd_soc_dapm_widget *source,
906 struct snd_soc_dapm_widget *sink)
907 {
908 struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm);
909 unsigned int reg, shift, val;
910
911 switch (source->shift) {
912 case 0:
913 reg = RT5645_ASRC_3;
914 shift = 0;
915 break;
916 case 1:
917 reg = RT5645_ASRC_3;
918 shift = 4;
919 break;
920 case 3:
921 reg = RT5645_ASRC_2;
922 shift = 0;
923 break;
924 case 8:
925 reg = RT5645_ASRC_2;
926 shift = 4;
927 break;
928 case 9:
929 reg = RT5645_ASRC_2;
930 shift = 8;
931 break;
932 case 10:
933 reg = RT5645_ASRC_2;
934 shift = 12;
935 break;
936 default:
937 return 0;
938 }
939
940 val = (snd_soc_component_read(component, reg) >> shift) & 0xf;
941 switch (val) {
942 case 1:
943 case 2:
944 case 3:
945 case 4:
946 return 1;
947 default:
948 return 0;
949 }
950
951 }
952
rt5645_enable_hweq(struct snd_soc_component * component)953 static int rt5645_enable_hweq(struct snd_soc_component *component)
954 {
955 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
956 int i;
957
958 for (i = 0; i < RT5645_HWEQ_NUM; i++) {
959 if (rt5645_validate_hweq(rt5645->eq_param[i].reg))
960 regmap_write(rt5645->regmap, rt5645->eq_param[i].reg,
961 rt5645->eq_param[i].val);
962 else
963 break;
964 }
965
966 return 0;
967 }
968
969 /**
970 * rt5645_sel_asrc_clk_src - select ASRC clock source for a set of filters
971 * @component: SoC audio component device.
972 * @filter_mask: mask of filters.
973 * @clk_src: clock source
974 *
975 * The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5645 can
976 * only support standard 32fs or 64fs i2s format, ASRC should be enabled to
977 * support special i2s clock format such as Intel's 100fs(100 * sampling rate).
978 * ASRC function will track i2s clock and generate a corresponding system clock
979 * for codec. This function provides an API to select the clock source for a
980 * set of filters specified by the mask. And the codec driver will turn on ASRC
981 * for these filters if ASRC is selected as their clock source.
982 */
rt5645_sel_asrc_clk_src(struct snd_soc_component * component,unsigned int filter_mask,unsigned int clk_src)983 int rt5645_sel_asrc_clk_src(struct snd_soc_component *component,
984 unsigned int filter_mask, unsigned int clk_src)
985 {
986 unsigned int asrc2_mask = 0;
987 unsigned int asrc2_value = 0;
988 unsigned int asrc3_mask = 0;
989 unsigned int asrc3_value = 0;
990
991 switch (clk_src) {
992 case RT5645_CLK_SEL_SYS:
993 case RT5645_CLK_SEL_I2S1_ASRC:
994 case RT5645_CLK_SEL_I2S2_ASRC:
995 case RT5645_CLK_SEL_SYS2:
996 break;
997
998 default:
999 return -EINVAL;
1000 }
1001
1002 if (filter_mask & RT5645_DA_STEREO_FILTER) {
1003 asrc2_mask |= RT5645_DA_STO_CLK_SEL_MASK;
1004 asrc2_value = (asrc2_value & ~RT5645_DA_STO_CLK_SEL_MASK)
1005 | (clk_src << RT5645_DA_STO_CLK_SEL_SFT);
1006 }
1007
1008 if (filter_mask & RT5645_DA_MONO_L_FILTER) {
1009 asrc2_mask |= RT5645_DA_MONOL_CLK_SEL_MASK;
1010 asrc2_value = (asrc2_value & ~RT5645_DA_MONOL_CLK_SEL_MASK)
1011 | (clk_src << RT5645_DA_MONOL_CLK_SEL_SFT);
1012 }
1013
1014 if (filter_mask & RT5645_DA_MONO_R_FILTER) {
1015 asrc2_mask |= RT5645_DA_MONOR_CLK_SEL_MASK;
1016 asrc2_value = (asrc2_value & ~RT5645_DA_MONOR_CLK_SEL_MASK)
1017 | (clk_src << RT5645_DA_MONOR_CLK_SEL_SFT);
1018 }
1019
1020 if (filter_mask & RT5645_AD_STEREO_FILTER) {
1021 asrc2_mask |= RT5645_AD_STO1_CLK_SEL_MASK;
1022 asrc2_value = (asrc2_value & ~RT5645_AD_STO1_CLK_SEL_MASK)
1023 | (clk_src << RT5645_AD_STO1_CLK_SEL_SFT);
1024 }
1025
1026 if (filter_mask & RT5645_AD_MONO_L_FILTER) {
1027 asrc3_mask |= RT5645_AD_MONOL_CLK_SEL_MASK;
1028 asrc3_value = (asrc3_value & ~RT5645_AD_MONOL_CLK_SEL_MASK)
1029 | (clk_src << RT5645_AD_MONOL_CLK_SEL_SFT);
1030 }
1031
1032 if (filter_mask & RT5645_AD_MONO_R_FILTER) {
1033 asrc3_mask |= RT5645_AD_MONOR_CLK_SEL_MASK;
1034 asrc3_value = (asrc3_value & ~RT5645_AD_MONOR_CLK_SEL_MASK)
1035 | (clk_src << RT5645_AD_MONOR_CLK_SEL_SFT);
1036 }
1037
1038 if (asrc2_mask)
1039 snd_soc_component_update_bits(component, RT5645_ASRC_2,
1040 asrc2_mask, asrc2_value);
1041
1042 if (asrc3_mask)
1043 snd_soc_component_update_bits(component, RT5645_ASRC_3,
1044 asrc3_mask, asrc3_value);
1045
1046 return 0;
1047 }
1048 EXPORT_SYMBOL_GPL(rt5645_sel_asrc_clk_src);
1049
1050 /* Digital Mixer */
1051 static const struct snd_kcontrol_new rt5645_sto1_adc_l_mix[] = {
1052 SOC_DAPM_SINGLE("ADC1 Switch", RT5645_STO1_ADC_MIXER,
1053 RT5645_M_ADC_L1_SFT, 1, 1),
1054 SOC_DAPM_SINGLE("ADC2 Switch", RT5645_STO1_ADC_MIXER,
1055 RT5645_M_ADC_L2_SFT, 1, 1),
1056 };
1057
1058 static const struct snd_kcontrol_new rt5645_sto1_adc_r_mix[] = {
1059 SOC_DAPM_SINGLE("ADC1 Switch", RT5645_STO1_ADC_MIXER,
1060 RT5645_M_ADC_R1_SFT, 1, 1),
1061 SOC_DAPM_SINGLE("ADC2 Switch", RT5645_STO1_ADC_MIXER,
1062 RT5645_M_ADC_R2_SFT, 1, 1),
1063 };
1064
1065 static const struct snd_kcontrol_new rt5645_mono_adc_l_mix[] = {
1066 SOC_DAPM_SINGLE("ADC1 Switch", RT5645_MONO_ADC_MIXER,
1067 RT5645_M_MONO_ADC_L1_SFT, 1, 1),
1068 SOC_DAPM_SINGLE("ADC2 Switch", RT5645_MONO_ADC_MIXER,
1069 RT5645_M_MONO_ADC_L2_SFT, 1, 1),
1070 };
1071
1072 static const struct snd_kcontrol_new rt5645_mono_adc_r_mix[] = {
1073 SOC_DAPM_SINGLE("ADC1 Switch", RT5645_MONO_ADC_MIXER,
1074 RT5645_M_MONO_ADC_R1_SFT, 1, 1),
1075 SOC_DAPM_SINGLE("ADC2 Switch", RT5645_MONO_ADC_MIXER,
1076 RT5645_M_MONO_ADC_R2_SFT, 1, 1),
1077 };
1078
1079 static const struct snd_kcontrol_new rt5645_dac_l_mix[] = {
1080 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5645_AD_DA_MIXER,
1081 RT5645_M_ADCMIX_L_SFT, 1, 1),
1082 SOC_DAPM_SINGLE_AUTODISABLE("DAC1 Switch", RT5645_AD_DA_MIXER,
1083 RT5645_M_DAC1_L_SFT, 1, 1),
1084 };
1085
1086 static const struct snd_kcontrol_new rt5645_dac_r_mix[] = {
1087 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5645_AD_DA_MIXER,
1088 RT5645_M_ADCMIX_R_SFT, 1, 1),
1089 SOC_DAPM_SINGLE_AUTODISABLE("DAC1 Switch", RT5645_AD_DA_MIXER,
1090 RT5645_M_DAC1_R_SFT, 1, 1),
1091 };
1092
1093 static const struct snd_kcontrol_new rt5645_sto_dac_l_mix[] = {
1094 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_STO_DAC_MIXER,
1095 RT5645_M_DAC_L1_SFT, 1, 1),
1096 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_STO_DAC_MIXER,
1097 RT5645_M_DAC_L2_SFT, 1, 1),
1098 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_STO_DAC_MIXER,
1099 RT5645_M_DAC_R1_STO_L_SFT, 1, 1),
1100 };
1101
1102 static const struct snd_kcontrol_new rt5645_sto_dac_r_mix[] = {
1103 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_STO_DAC_MIXER,
1104 RT5645_M_DAC_R1_SFT, 1, 1),
1105 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_STO_DAC_MIXER,
1106 RT5645_M_DAC_R2_SFT, 1, 1),
1107 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_STO_DAC_MIXER,
1108 RT5645_M_DAC_L1_STO_R_SFT, 1, 1),
1109 };
1110
1111 static const struct snd_kcontrol_new rt5645_mono_dac_l_mix[] = {
1112 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_MONO_DAC_MIXER,
1113 RT5645_M_DAC_L1_MONO_L_SFT, 1, 1),
1114 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_MONO_DAC_MIXER,
1115 RT5645_M_DAC_L2_MONO_L_SFT, 1, 1),
1116 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_MONO_DAC_MIXER,
1117 RT5645_M_DAC_R2_MONO_L_SFT, 1, 1),
1118 };
1119
1120 static const struct snd_kcontrol_new rt5645_mono_dac_r_mix[] = {
1121 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_MONO_DAC_MIXER,
1122 RT5645_M_DAC_R1_MONO_R_SFT, 1, 1),
1123 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_MONO_DAC_MIXER,
1124 RT5645_M_DAC_R2_MONO_R_SFT, 1, 1),
1125 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_MONO_DAC_MIXER,
1126 RT5645_M_DAC_L2_MONO_R_SFT, 1, 1),
1127 };
1128
1129 static const struct snd_kcontrol_new rt5645_dig_l_mix[] = {
1130 SOC_DAPM_SINGLE("Sto DAC Mix L Switch", RT5645_DIG_MIXER,
1131 RT5645_M_STO_L_DAC_L_SFT, 1, 1),
1132 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_DIG_MIXER,
1133 RT5645_M_DAC_L2_DAC_L_SFT, 1, 1),
1134 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_DIG_MIXER,
1135 RT5645_M_DAC_R2_DAC_L_SFT, 1, 1),
1136 };
1137
1138 static const struct snd_kcontrol_new rt5645_dig_r_mix[] = {
1139 SOC_DAPM_SINGLE("Sto DAC Mix R Switch", RT5645_DIG_MIXER,
1140 RT5645_M_STO_R_DAC_R_SFT, 1, 1),
1141 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_DIG_MIXER,
1142 RT5645_M_DAC_R2_DAC_R_SFT, 1, 1),
1143 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_DIG_MIXER,
1144 RT5645_M_DAC_L2_DAC_R_SFT, 1, 1),
1145 };
1146
1147 /* Analog Input Mixer */
1148 static const struct snd_kcontrol_new rt5645_rec_l_mix[] = {
1149 SOC_DAPM_SINGLE("HPOL Switch", RT5645_REC_L2_MIXER,
1150 RT5645_M_HP_L_RM_L_SFT, 1, 1),
1151 SOC_DAPM_SINGLE("INL Switch", RT5645_REC_L2_MIXER,
1152 RT5645_M_IN_L_RM_L_SFT, 1, 1),
1153 SOC_DAPM_SINGLE("BST2 Switch", RT5645_REC_L2_MIXER,
1154 RT5645_M_BST2_RM_L_SFT, 1, 1),
1155 SOC_DAPM_SINGLE("BST1 Switch", RT5645_REC_L2_MIXER,
1156 RT5645_M_BST1_RM_L_SFT, 1, 1),
1157 SOC_DAPM_SINGLE("OUT MIXL Switch", RT5645_REC_L2_MIXER,
1158 RT5645_M_OM_L_RM_L_SFT, 1, 1),
1159 };
1160
1161 static const struct snd_kcontrol_new rt5645_rec_r_mix[] = {
1162 SOC_DAPM_SINGLE("HPOR Switch", RT5645_REC_R2_MIXER,
1163 RT5645_M_HP_R_RM_R_SFT, 1, 1),
1164 SOC_DAPM_SINGLE("INR Switch", RT5645_REC_R2_MIXER,
1165 RT5645_M_IN_R_RM_R_SFT, 1, 1),
1166 SOC_DAPM_SINGLE("BST2 Switch", RT5645_REC_R2_MIXER,
1167 RT5645_M_BST2_RM_R_SFT, 1, 1),
1168 SOC_DAPM_SINGLE("BST1 Switch", RT5645_REC_R2_MIXER,
1169 RT5645_M_BST1_RM_R_SFT, 1, 1),
1170 SOC_DAPM_SINGLE("OUT MIXR Switch", RT5645_REC_R2_MIXER,
1171 RT5645_M_OM_R_RM_R_SFT, 1, 1),
1172 };
1173
1174 static const struct snd_kcontrol_new rt5645_spk_l_mix[] = {
1175 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_SPK_L_MIXER,
1176 RT5645_M_DAC_L1_SM_L_SFT, 1, 1),
1177 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_SPK_L_MIXER,
1178 RT5645_M_DAC_L2_SM_L_SFT, 1, 1),
1179 SOC_DAPM_SINGLE("INL Switch", RT5645_SPK_L_MIXER,
1180 RT5645_M_IN_L_SM_L_SFT, 1, 1),
1181 SOC_DAPM_SINGLE("BST1 Switch", RT5645_SPK_L_MIXER,
1182 RT5645_M_BST1_L_SM_L_SFT, 1, 1),
1183 };
1184
1185 static const struct snd_kcontrol_new rt5645_spk_r_mix[] = {
1186 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_SPK_R_MIXER,
1187 RT5645_M_DAC_R1_SM_R_SFT, 1, 1),
1188 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_SPK_R_MIXER,
1189 RT5645_M_DAC_R2_SM_R_SFT, 1, 1),
1190 SOC_DAPM_SINGLE("INR Switch", RT5645_SPK_R_MIXER,
1191 RT5645_M_IN_R_SM_R_SFT, 1, 1),
1192 SOC_DAPM_SINGLE("BST2 Switch", RT5645_SPK_R_MIXER,
1193 RT5645_M_BST2_R_SM_R_SFT, 1, 1),
1194 };
1195
1196 static const struct snd_kcontrol_new rt5645_out_l_mix[] = {
1197 SOC_DAPM_SINGLE("BST1 Switch", RT5645_OUT_L1_MIXER,
1198 RT5645_M_BST1_OM_L_SFT, 1, 1),
1199 SOC_DAPM_SINGLE("INL Switch", RT5645_OUT_L1_MIXER,
1200 RT5645_M_IN_L_OM_L_SFT, 1, 1),
1201 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_OUT_L1_MIXER,
1202 RT5645_M_DAC_L2_OM_L_SFT, 1, 1),
1203 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_OUT_L1_MIXER,
1204 RT5645_M_DAC_L1_OM_L_SFT, 1, 1),
1205 };
1206
1207 static const struct snd_kcontrol_new rt5645_out_r_mix[] = {
1208 SOC_DAPM_SINGLE("BST2 Switch", RT5645_OUT_R1_MIXER,
1209 RT5645_M_BST2_OM_R_SFT, 1, 1),
1210 SOC_DAPM_SINGLE("INR Switch", RT5645_OUT_R1_MIXER,
1211 RT5645_M_IN_R_OM_R_SFT, 1, 1),
1212 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_OUT_R1_MIXER,
1213 RT5645_M_DAC_R2_OM_R_SFT, 1, 1),
1214 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_OUT_R1_MIXER,
1215 RT5645_M_DAC_R1_OM_R_SFT, 1, 1),
1216 };
1217
1218 static const struct snd_kcontrol_new rt5645_spo_l_mix[] = {
1219 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_SPO_MIXER,
1220 RT5645_M_DAC_R1_SPM_L_SFT, 1, 1),
1221 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_SPO_MIXER,
1222 RT5645_M_DAC_L1_SPM_L_SFT, 1, 1),
1223 SOC_DAPM_SINGLE("SPKVOL R Switch", RT5645_SPO_MIXER,
1224 RT5645_M_SV_R_SPM_L_SFT, 1, 1),
1225 SOC_DAPM_SINGLE("SPKVOL L Switch", RT5645_SPO_MIXER,
1226 RT5645_M_SV_L_SPM_L_SFT, 1, 1),
1227 };
1228
1229 static const struct snd_kcontrol_new rt5645_spo_r_mix[] = {
1230 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_SPO_MIXER,
1231 RT5645_M_DAC_R1_SPM_R_SFT, 1, 1),
1232 SOC_DAPM_SINGLE("SPKVOL R Switch", RT5645_SPO_MIXER,
1233 RT5645_M_SV_R_SPM_R_SFT, 1, 1),
1234 };
1235
1236 static const struct snd_kcontrol_new rt5645_hpo_mix[] = {
1237 SOC_DAPM_SINGLE("DAC1 Switch", RT5645_HPO_MIXER,
1238 RT5645_M_DAC1_HM_SFT, 1, 1),
1239 SOC_DAPM_SINGLE("HPVOL Switch", RT5645_HPO_MIXER,
1240 RT5645_M_HPVOL_HM_SFT, 1, 1),
1241 };
1242
1243 static const struct snd_kcontrol_new rt5645_hpvoll_mix[] = {
1244 SOC_DAPM_SINGLE("DAC1 Switch", RT5645_HPOMIXL_CTRL,
1245 RT5645_M_DAC1_HV_SFT, 1, 1),
1246 SOC_DAPM_SINGLE("DAC2 Switch", RT5645_HPOMIXL_CTRL,
1247 RT5645_M_DAC2_HV_SFT, 1, 1),
1248 SOC_DAPM_SINGLE("INL Switch", RT5645_HPOMIXL_CTRL,
1249 RT5645_M_IN_HV_SFT, 1, 1),
1250 SOC_DAPM_SINGLE("BST1 Switch", RT5645_HPOMIXL_CTRL,
1251 RT5645_M_BST1_HV_SFT, 1, 1),
1252 };
1253
1254 static const struct snd_kcontrol_new rt5645_hpvolr_mix[] = {
1255 SOC_DAPM_SINGLE("DAC1 Switch", RT5645_HPOMIXR_CTRL,
1256 RT5645_M_DAC1_HV_SFT, 1, 1),
1257 SOC_DAPM_SINGLE("DAC2 Switch", RT5645_HPOMIXR_CTRL,
1258 RT5645_M_DAC2_HV_SFT, 1, 1),
1259 SOC_DAPM_SINGLE("INR Switch", RT5645_HPOMIXR_CTRL,
1260 RT5645_M_IN_HV_SFT, 1, 1),
1261 SOC_DAPM_SINGLE("BST2 Switch", RT5645_HPOMIXR_CTRL,
1262 RT5645_M_BST2_HV_SFT, 1, 1),
1263 };
1264
1265 static const struct snd_kcontrol_new rt5645_lout_mix[] = {
1266 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_LOUT_MIXER,
1267 RT5645_M_DAC_L1_LM_SFT, 1, 1),
1268 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_LOUT_MIXER,
1269 RT5645_M_DAC_R1_LM_SFT, 1, 1),
1270 SOC_DAPM_SINGLE("OUTMIX L Switch", RT5645_LOUT_MIXER,
1271 RT5645_M_OV_L_LM_SFT, 1, 1),
1272 SOC_DAPM_SINGLE("OUTMIX R Switch", RT5645_LOUT_MIXER,
1273 RT5645_M_OV_R_LM_SFT, 1, 1),
1274 };
1275
1276 /*DAC1 L/R source*/ /* MX-29 [9:8] [11:10] */
1277 static const char * const rt5645_dac1_src[] = {
1278 "IF1 DAC", "IF2 DAC", "IF3 DAC"
1279 };
1280
1281 static SOC_ENUM_SINGLE_DECL(
1282 rt5645_dac1l_enum, RT5645_AD_DA_MIXER,
1283 RT5645_DAC1_L_SEL_SFT, rt5645_dac1_src);
1284
1285 static const struct snd_kcontrol_new rt5645_dac1l_mux =
1286 SOC_DAPM_ENUM("DAC1 L source", rt5645_dac1l_enum);
1287
1288 static SOC_ENUM_SINGLE_DECL(
1289 rt5645_dac1r_enum, RT5645_AD_DA_MIXER,
1290 RT5645_DAC1_R_SEL_SFT, rt5645_dac1_src);
1291
1292 static const struct snd_kcontrol_new rt5645_dac1r_mux =
1293 SOC_DAPM_ENUM("DAC1 R source", rt5645_dac1r_enum);
1294
1295 /*DAC2 L/R source*/ /* MX-1B [6:4] [2:0] */
1296 static const char * const rt5645_dac12_src[] = {
1297 "IF1 DAC", "IF2 DAC", "IF3 DAC", "Mono ADC", "VAD_ADC"
1298 };
1299
1300 static SOC_ENUM_SINGLE_DECL(
1301 rt5645_dac2l_enum, RT5645_DAC_CTRL,
1302 RT5645_DAC2_L_SEL_SFT, rt5645_dac12_src);
1303
1304 static const struct snd_kcontrol_new rt5645_dac_l2_mux =
1305 SOC_DAPM_ENUM("DAC2 L source", rt5645_dac2l_enum);
1306
1307 static const char * const rt5645_dacr2_src[] = {
1308 "IF1 DAC", "IF2 DAC", "IF3 DAC", "Mono ADC", "Haptic"
1309 };
1310
1311 static SOC_ENUM_SINGLE_DECL(
1312 rt5645_dac2r_enum, RT5645_DAC_CTRL,
1313 RT5645_DAC2_R_SEL_SFT, rt5645_dacr2_src);
1314
1315 static const struct snd_kcontrol_new rt5645_dac_r2_mux =
1316 SOC_DAPM_ENUM("DAC2 R source", rt5645_dac2r_enum);
1317
1318 /* Stereo1 ADC source */
1319 /* MX-27 [12] */
1320 static const char * const rt5645_stereo_adc1_src[] = {
1321 "DAC MIX", "ADC"
1322 };
1323
1324 static SOC_ENUM_SINGLE_DECL(
1325 rt5645_stereo1_adc1_enum, RT5645_STO1_ADC_MIXER,
1326 RT5645_ADC_1_SRC_SFT, rt5645_stereo_adc1_src);
1327
1328 static const struct snd_kcontrol_new rt5645_sto_adc1_mux =
1329 SOC_DAPM_ENUM("Stereo1 ADC1 Mux", rt5645_stereo1_adc1_enum);
1330
1331 /* MX-27 [11] */
1332 static const char * const rt5645_stereo_adc2_src[] = {
1333 "DAC MIX", "DMIC"
1334 };
1335
1336 static SOC_ENUM_SINGLE_DECL(
1337 rt5645_stereo1_adc2_enum, RT5645_STO1_ADC_MIXER,
1338 RT5645_ADC_2_SRC_SFT, rt5645_stereo_adc2_src);
1339
1340 static const struct snd_kcontrol_new rt5645_sto_adc2_mux =
1341 SOC_DAPM_ENUM("Stereo1 ADC2 Mux", rt5645_stereo1_adc2_enum);
1342
1343 /* MX-27 [8] */
1344 static const char * const rt5645_stereo_dmic_src[] = {
1345 "DMIC1", "DMIC2"
1346 };
1347
1348 static SOC_ENUM_SINGLE_DECL(
1349 rt5645_stereo1_dmic_enum, RT5645_STO1_ADC_MIXER,
1350 RT5645_DMIC_SRC_SFT, rt5645_stereo_dmic_src);
1351
1352 static const struct snd_kcontrol_new rt5645_sto1_dmic_mux =
1353 SOC_DAPM_ENUM("Stereo1 DMIC source", rt5645_stereo1_dmic_enum);
1354
1355 /* Mono ADC source */
1356 /* MX-28 [12] */
1357 static const char * const rt5645_mono_adc_l1_src[] = {
1358 "Mono DAC MIXL", "ADC"
1359 };
1360
1361 static SOC_ENUM_SINGLE_DECL(
1362 rt5645_mono_adc_l1_enum, RT5645_MONO_ADC_MIXER,
1363 RT5645_MONO_ADC_L1_SRC_SFT, rt5645_mono_adc_l1_src);
1364
1365 static const struct snd_kcontrol_new rt5645_mono_adc_l1_mux =
1366 SOC_DAPM_ENUM("Mono ADC1 left source", rt5645_mono_adc_l1_enum);
1367 /* MX-28 [11] */
1368 static const char * const rt5645_mono_adc_l2_src[] = {
1369 "Mono DAC MIXL", "DMIC"
1370 };
1371
1372 static SOC_ENUM_SINGLE_DECL(
1373 rt5645_mono_adc_l2_enum, RT5645_MONO_ADC_MIXER,
1374 RT5645_MONO_ADC_L2_SRC_SFT, rt5645_mono_adc_l2_src);
1375
1376 static const struct snd_kcontrol_new rt5645_mono_adc_l2_mux =
1377 SOC_DAPM_ENUM("Mono ADC2 left source", rt5645_mono_adc_l2_enum);
1378
1379 /* MX-28 [8] */
1380 static const char * const rt5645_mono_dmic_src[] = {
1381 "DMIC1", "DMIC2"
1382 };
1383
1384 static SOC_ENUM_SINGLE_DECL(
1385 rt5645_mono_dmic_l_enum, RT5645_MONO_ADC_MIXER,
1386 RT5645_MONO_DMIC_L_SRC_SFT, rt5645_mono_dmic_src);
1387
1388 static const struct snd_kcontrol_new rt5645_mono_dmic_l_mux =
1389 SOC_DAPM_ENUM("Mono DMIC left source", rt5645_mono_dmic_l_enum);
1390 /* MX-28 [1:0] */
1391 static SOC_ENUM_SINGLE_DECL(
1392 rt5645_mono_dmic_r_enum, RT5645_MONO_ADC_MIXER,
1393 RT5645_MONO_DMIC_R_SRC_SFT, rt5645_mono_dmic_src);
1394
1395 static const struct snd_kcontrol_new rt5645_mono_dmic_r_mux =
1396 SOC_DAPM_ENUM("Mono DMIC Right source", rt5645_mono_dmic_r_enum);
1397 /* MX-28 [4] */
1398 static const char * const rt5645_mono_adc_r1_src[] = {
1399 "Mono DAC MIXR", "ADC"
1400 };
1401
1402 static SOC_ENUM_SINGLE_DECL(
1403 rt5645_mono_adc_r1_enum, RT5645_MONO_ADC_MIXER,
1404 RT5645_MONO_ADC_R1_SRC_SFT, rt5645_mono_adc_r1_src);
1405
1406 static const struct snd_kcontrol_new rt5645_mono_adc_r1_mux =
1407 SOC_DAPM_ENUM("Mono ADC1 right source", rt5645_mono_adc_r1_enum);
1408 /* MX-28 [3] */
1409 static const char * const rt5645_mono_adc_r2_src[] = {
1410 "Mono DAC MIXR", "DMIC"
1411 };
1412
1413 static SOC_ENUM_SINGLE_DECL(
1414 rt5645_mono_adc_r2_enum, RT5645_MONO_ADC_MIXER,
1415 RT5645_MONO_ADC_R2_SRC_SFT, rt5645_mono_adc_r2_src);
1416
1417 static const struct snd_kcontrol_new rt5645_mono_adc_r2_mux =
1418 SOC_DAPM_ENUM("Mono ADC2 right source", rt5645_mono_adc_r2_enum);
1419
1420 /* MX-77 [9:8] */
1421 static const char * const rt5645_if1_adc_in_src[] = {
1422 "IF_ADC1/IF_ADC2/VAD_ADC", "IF_ADC2/IF_ADC1/VAD_ADC",
1423 "VAD_ADC/IF_ADC1/IF_ADC2", "VAD_ADC/IF_ADC2/IF_ADC1"
1424 };
1425
1426 static SOC_ENUM_SINGLE_DECL(
1427 rt5645_if1_adc_in_enum, RT5645_TDM_CTRL_1,
1428 RT5645_IF1_ADC_IN_SFT, rt5645_if1_adc_in_src);
1429
1430 static const struct snd_kcontrol_new rt5645_if1_adc_in_mux =
1431 SOC_DAPM_ENUM("IF1 ADC IN source", rt5645_if1_adc_in_enum);
1432
1433 /* MX-78 [4:0] */
1434 static const char * const rt5650_if1_adc_in_src[] = {
1435 "IF_ADC1/IF_ADC2/DAC_REF/Null",
1436 "IF_ADC1/IF_ADC2/Null/DAC_REF",
1437 "IF_ADC1/DAC_REF/IF_ADC2/Null",
1438 "IF_ADC1/DAC_REF/Null/IF_ADC2",
1439 "IF_ADC1/Null/DAC_REF/IF_ADC2",
1440 "IF_ADC1/Null/IF_ADC2/DAC_REF",
1441
1442 "IF_ADC2/IF_ADC1/DAC_REF/Null",
1443 "IF_ADC2/IF_ADC1/Null/DAC_REF",
1444 "IF_ADC2/DAC_REF/IF_ADC1/Null",
1445 "IF_ADC2/DAC_REF/Null/IF_ADC1",
1446 "IF_ADC2/Null/DAC_REF/IF_ADC1",
1447 "IF_ADC2/Null/IF_ADC1/DAC_REF",
1448
1449 "DAC_REF/IF_ADC1/IF_ADC2/Null",
1450 "DAC_REF/IF_ADC1/Null/IF_ADC2",
1451 "DAC_REF/IF_ADC2/IF_ADC1/Null",
1452 "DAC_REF/IF_ADC2/Null/IF_ADC1",
1453 "DAC_REF/Null/IF_ADC1/IF_ADC2",
1454 "DAC_REF/Null/IF_ADC2/IF_ADC1",
1455
1456 "Null/IF_ADC1/IF_ADC2/DAC_REF",
1457 "Null/IF_ADC1/DAC_REF/IF_ADC2",
1458 "Null/IF_ADC2/IF_ADC1/DAC_REF",
1459 "Null/IF_ADC2/DAC_REF/IF_ADC1",
1460 "Null/DAC_REF/IF_ADC1/IF_ADC2",
1461 "Null/DAC_REF/IF_ADC2/IF_ADC1",
1462 };
1463
1464 static SOC_ENUM_SINGLE_DECL(
1465 rt5650_if1_adc_in_enum, RT5645_TDM_CTRL_2,
1466 0, rt5650_if1_adc_in_src);
1467
1468 static const struct snd_kcontrol_new rt5650_if1_adc_in_mux =
1469 SOC_DAPM_ENUM("IF1 ADC IN source", rt5650_if1_adc_in_enum);
1470
1471 /* MX-78 [15:14][13:12][11:10] */
1472 static const char * const rt5645_tdm_adc_swap_select[] = {
1473 "L/R", "R/L", "L/L", "R/R"
1474 };
1475
1476 static SOC_ENUM_SINGLE_DECL(rt5650_tdm_adc_slot0_1_enum,
1477 RT5645_TDM_CTRL_2, 14, rt5645_tdm_adc_swap_select);
1478
1479 static const struct snd_kcontrol_new rt5650_if1_adc1_in_mux =
1480 SOC_DAPM_ENUM("IF1 ADC1 IN source", rt5650_tdm_adc_slot0_1_enum);
1481
1482 static SOC_ENUM_SINGLE_DECL(rt5650_tdm_adc_slot2_3_enum,
1483 RT5645_TDM_CTRL_2, 12, rt5645_tdm_adc_swap_select);
1484
1485 static const struct snd_kcontrol_new rt5650_if1_adc2_in_mux =
1486 SOC_DAPM_ENUM("IF1 ADC2 IN source", rt5650_tdm_adc_slot2_3_enum);
1487
1488 static SOC_ENUM_SINGLE_DECL(rt5650_tdm_adc_slot4_5_enum,
1489 RT5645_TDM_CTRL_2, 10, rt5645_tdm_adc_swap_select);
1490
1491 static const struct snd_kcontrol_new rt5650_if1_adc3_in_mux =
1492 SOC_DAPM_ENUM("IF1 ADC3 IN source", rt5650_tdm_adc_slot4_5_enum);
1493
1494 /* MX-77 [7:6][5:4][3:2] */
1495 static SOC_ENUM_SINGLE_DECL(rt5645_tdm_adc_slot0_1_enum,
1496 RT5645_TDM_CTRL_1, 6, rt5645_tdm_adc_swap_select);
1497
1498 static const struct snd_kcontrol_new rt5645_if1_adc1_in_mux =
1499 SOC_DAPM_ENUM("IF1 ADC1 IN source", rt5645_tdm_adc_slot0_1_enum);
1500
1501 static SOC_ENUM_SINGLE_DECL(rt5645_tdm_adc_slot2_3_enum,
1502 RT5645_TDM_CTRL_1, 4, rt5645_tdm_adc_swap_select);
1503
1504 static const struct snd_kcontrol_new rt5645_if1_adc2_in_mux =
1505 SOC_DAPM_ENUM("IF1 ADC2 IN source", rt5645_tdm_adc_slot2_3_enum);
1506
1507 static SOC_ENUM_SINGLE_DECL(rt5645_tdm_adc_slot4_5_enum,
1508 RT5645_TDM_CTRL_1, 2, rt5645_tdm_adc_swap_select);
1509
1510 static const struct snd_kcontrol_new rt5645_if1_adc3_in_mux =
1511 SOC_DAPM_ENUM("IF1 ADC3 IN source", rt5645_tdm_adc_slot4_5_enum);
1512
1513 /* MX-79 [14:12][10:8][6:4][2:0] */
1514 static const char * const rt5645_tdm_dac_swap_select[] = {
1515 "Slot0", "Slot1", "Slot2", "Slot3"
1516 };
1517
1518 static SOC_ENUM_SINGLE_DECL(rt5645_tdm_dac0_enum,
1519 RT5645_TDM_CTRL_3, 12, rt5645_tdm_dac_swap_select);
1520
1521 static const struct snd_kcontrol_new rt5645_if1_dac0_tdm_sel_mux =
1522 SOC_DAPM_ENUM("IF1 DAC0 source", rt5645_tdm_dac0_enum);
1523
1524 static SOC_ENUM_SINGLE_DECL(rt5645_tdm_dac1_enum,
1525 RT5645_TDM_CTRL_3, 8, rt5645_tdm_dac_swap_select);
1526
1527 static const struct snd_kcontrol_new rt5645_if1_dac1_tdm_sel_mux =
1528 SOC_DAPM_ENUM("IF1 DAC1 source", rt5645_tdm_dac1_enum);
1529
1530 static SOC_ENUM_SINGLE_DECL(rt5645_tdm_dac2_enum,
1531 RT5645_TDM_CTRL_3, 4, rt5645_tdm_dac_swap_select);
1532
1533 static const struct snd_kcontrol_new rt5645_if1_dac2_tdm_sel_mux =
1534 SOC_DAPM_ENUM("IF1 DAC2 source", rt5645_tdm_dac2_enum);
1535
1536 static SOC_ENUM_SINGLE_DECL(rt5645_tdm_dac3_enum,
1537 RT5645_TDM_CTRL_3, 0, rt5645_tdm_dac_swap_select);
1538
1539 static const struct snd_kcontrol_new rt5645_if1_dac3_tdm_sel_mux =
1540 SOC_DAPM_ENUM("IF1 DAC3 source", rt5645_tdm_dac3_enum);
1541
1542 /* MX-7a [14:12][10:8][6:4][2:0] */
1543 static SOC_ENUM_SINGLE_DECL(rt5650_tdm_dac0_enum,
1544 RT5650_TDM_CTRL_4, 12, rt5645_tdm_dac_swap_select);
1545
1546 static const struct snd_kcontrol_new rt5650_if1_dac0_tdm_sel_mux =
1547 SOC_DAPM_ENUM("IF1 DAC0 source", rt5650_tdm_dac0_enum);
1548
1549 static SOC_ENUM_SINGLE_DECL(rt5650_tdm_dac1_enum,
1550 RT5650_TDM_CTRL_4, 8, rt5645_tdm_dac_swap_select);
1551
1552 static const struct snd_kcontrol_new rt5650_if1_dac1_tdm_sel_mux =
1553 SOC_DAPM_ENUM("IF1 DAC1 source", rt5650_tdm_dac1_enum);
1554
1555 static SOC_ENUM_SINGLE_DECL(rt5650_tdm_dac2_enum,
1556 RT5650_TDM_CTRL_4, 4, rt5645_tdm_dac_swap_select);
1557
1558 static const struct snd_kcontrol_new rt5650_if1_dac2_tdm_sel_mux =
1559 SOC_DAPM_ENUM("IF1 DAC2 source", rt5650_tdm_dac2_enum);
1560
1561 static SOC_ENUM_SINGLE_DECL(rt5650_tdm_dac3_enum,
1562 RT5650_TDM_CTRL_4, 0, rt5645_tdm_dac_swap_select);
1563
1564 static const struct snd_kcontrol_new rt5650_if1_dac3_tdm_sel_mux =
1565 SOC_DAPM_ENUM("IF1 DAC3 source", rt5650_tdm_dac3_enum);
1566
1567 /* MX-2d [3] [2] */
1568 static const char * const rt5650_a_dac1_src[] = {
1569 "DAC1", "Stereo DAC Mixer"
1570 };
1571
1572 static SOC_ENUM_SINGLE_DECL(
1573 rt5650_a_dac1_l_enum, RT5650_A_DAC_SOUR,
1574 RT5650_A_DAC1_L_IN_SFT, rt5650_a_dac1_src);
1575
1576 static const struct snd_kcontrol_new rt5650_a_dac1_l_mux =
1577 SOC_DAPM_ENUM("A DAC1 L source", rt5650_a_dac1_l_enum);
1578
1579 static SOC_ENUM_SINGLE_DECL(
1580 rt5650_a_dac1_r_enum, RT5650_A_DAC_SOUR,
1581 RT5650_A_DAC1_R_IN_SFT, rt5650_a_dac1_src);
1582
1583 static const struct snd_kcontrol_new rt5650_a_dac1_r_mux =
1584 SOC_DAPM_ENUM("A DAC1 R source", rt5650_a_dac1_r_enum);
1585
1586 /* MX-2d [1] [0] */
1587 static const char * const rt5650_a_dac2_src[] = {
1588 "Stereo DAC Mixer", "Mono DAC Mixer"
1589 };
1590
1591 static SOC_ENUM_SINGLE_DECL(
1592 rt5650_a_dac2_l_enum, RT5650_A_DAC_SOUR,
1593 RT5650_A_DAC2_L_IN_SFT, rt5650_a_dac2_src);
1594
1595 static const struct snd_kcontrol_new rt5650_a_dac2_l_mux =
1596 SOC_DAPM_ENUM("A DAC2 L source", rt5650_a_dac2_l_enum);
1597
1598 static SOC_ENUM_SINGLE_DECL(
1599 rt5650_a_dac2_r_enum, RT5650_A_DAC_SOUR,
1600 RT5650_A_DAC2_R_IN_SFT, rt5650_a_dac2_src);
1601
1602 static const struct snd_kcontrol_new rt5650_a_dac2_r_mux =
1603 SOC_DAPM_ENUM("A DAC2 R source", rt5650_a_dac2_r_enum);
1604
1605 /* MX-2F [13:12] */
1606 static const char * const rt5645_if2_adc_in_src[] = {
1607 "IF_ADC1", "IF_ADC2", "VAD_ADC"
1608 };
1609
1610 static SOC_ENUM_SINGLE_DECL(
1611 rt5645_if2_adc_in_enum, RT5645_DIG_INF1_DATA,
1612 RT5645_IF2_ADC_IN_SFT, rt5645_if2_adc_in_src);
1613
1614 static const struct snd_kcontrol_new rt5645_if2_adc_in_mux =
1615 SOC_DAPM_ENUM("IF2 ADC IN source", rt5645_if2_adc_in_enum);
1616
1617 /* MX-31 [15] [13] [11] [9] */
1618 static const char * const rt5645_pdm_src[] = {
1619 "Mono DAC", "Stereo DAC"
1620 };
1621
1622 static SOC_ENUM_SINGLE_DECL(
1623 rt5645_pdm1_l_enum, RT5645_PDM_OUT_CTRL,
1624 RT5645_PDM1_L_SFT, rt5645_pdm_src);
1625
1626 static const struct snd_kcontrol_new rt5645_pdm1_l_mux =
1627 SOC_DAPM_ENUM("PDM1 L source", rt5645_pdm1_l_enum);
1628
1629 static SOC_ENUM_SINGLE_DECL(
1630 rt5645_pdm1_r_enum, RT5645_PDM_OUT_CTRL,
1631 RT5645_PDM1_R_SFT, rt5645_pdm_src);
1632
1633 static const struct snd_kcontrol_new rt5645_pdm1_r_mux =
1634 SOC_DAPM_ENUM("PDM1 R source", rt5645_pdm1_r_enum);
1635
1636 /* MX-9D [9:8] */
1637 static const char * const rt5645_vad_adc_src[] = {
1638 "Sto1 ADC L", "Mono ADC L", "Mono ADC R"
1639 };
1640
1641 static SOC_ENUM_SINGLE_DECL(
1642 rt5645_vad_adc_enum, RT5645_VAD_CTRL4,
1643 RT5645_VAD_SEL_SFT, rt5645_vad_adc_src);
1644
1645 static const struct snd_kcontrol_new rt5645_vad_adc_mux =
1646 SOC_DAPM_ENUM("VAD ADC source", rt5645_vad_adc_enum);
1647
1648 static const struct snd_kcontrol_new spk_l_vol_control =
1649 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_SPK_VOL,
1650 RT5645_L_MUTE_SFT, 1, 1);
1651
1652 static const struct snd_kcontrol_new spk_r_vol_control =
1653 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_SPK_VOL,
1654 RT5645_R_MUTE_SFT, 1, 1);
1655
1656 static const struct snd_kcontrol_new hp_l_vol_control =
1657 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_HP_VOL,
1658 RT5645_L_MUTE_SFT, 1, 1);
1659
1660 static const struct snd_kcontrol_new hp_r_vol_control =
1661 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_HP_VOL,
1662 RT5645_R_MUTE_SFT, 1, 1);
1663
1664 static const struct snd_kcontrol_new pdm1_l_vol_control =
1665 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_PDM_OUT_CTRL,
1666 RT5645_M_PDM1_L, 1, 1);
1667
1668 static const struct snd_kcontrol_new pdm1_r_vol_control =
1669 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_PDM_OUT_CTRL,
1670 RT5645_M_PDM1_R, 1, 1);
1671
hp_amp_power(struct snd_soc_component * component,int on)1672 static void hp_amp_power(struct snd_soc_component *component, int on)
1673 {
1674 static int hp_amp_power_count;
1675 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
1676 int i, val;
1677
1678 if (on) {
1679 if (hp_amp_power_count <= 0) {
1680 if (rt5645->codec_type == CODEC_TYPE_RT5650) {
1681 snd_soc_component_write(component, RT5645_DEPOP_M2, 0x3100);
1682 snd_soc_component_write(component, RT5645_CHARGE_PUMP,
1683 0x0e06);
1684 snd_soc_component_write(component, RT5645_DEPOP_M1, 0x000d);
1685 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1686 RT5645_HP_DCC_INT1, 0x9f01);
1687 for (i = 0; i < 20; i++) {
1688 usleep_range(1000, 1500);
1689 regmap_read(rt5645->regmap, RT5645_PR_BASE +
1690 RT5645_HP_DCC_INT1, &val);
1691 if (!(val & 0x8000))
1692 break;
1693 }
1694 snd_soc_component_update_bits(component, RT5645_DEPOP_M1,
1695 RT5645_HP_CO_MASK, RT5645_HP_CO_EN);
1696 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1697 0x3e, 0x7400);
1698 snd_soc_component_write(component, RT5645_DEPOP_M3, 0x0737);
1699 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1700 RT5645_MAMP_INT_REG2, 0xfc00);
1701 snd_soc_component_write(component, RT5645_DEPOP_M2, 0x1140);
1702 snd_soc_component_update_bits(component, RT5645_PWR_ANLG1,
1703 RT5645_PWR_HP_L | RT5645_PWR_HP_R,
1704 RT5645_PWR_HP_L | RT5645_PWR_HP_R);
1705 msleep(90);
1706 } else {
1707 /* depop parameters */
1708 snd_soc_component_update_bits(component, RT5645_DEPOP_M2,
1709 RT5645_DEPOP_MASK, RT5645_DEPOP_MAN);
1710 snd_soc_component_write(component, RT5645_DEPOP_M1, 0x000d);
1711 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1712 RT5645_HP_DCC_INT1, 0x9f01);
1713 mdelay(150);
1714 /* headphone amp power on */
1715 snd_soc_component_update_bits(component, RT5645_PWR_ANLG1,
1716 RT5645_PWR_FV1 | RT5645_PWR_FV2, 0);
1717 snd_soc_component_update_bits(component, RT5645_PWR_VOL,
1718 RT5645_PWR_HV_L | RT5645_PWR_HV_R,
1719 RT5645_PWR_HV_L | RT5645_PWR_HV_R);
1720 snd_soc_component_update_bits(component, RT5645_PWR_ANLG1,
1721 RT5645_PWR_HP_L | RT5645_PWR_HP_R |
1722 RT5645_PWR_HA,
1723 RT5645_PWR_HP_L | RT5645_PWR_HP_R |
1724 RT5645_PWR_HA);
1725 mdelay(5);
1726 snd_soc_component_update_bits(component, RT5645_PWR_ANLG1,
1727 RT5645_PWR_FV1 | RT5645_PWR_FV2,
1728 RT5645_PWR_FV1 | RT5645_PWR_FV2);
1729
1730 snd_soc_component_update_bits(component, RT5645_DEPOP_M1,
1731 RT5645_HP_CO_MASK | RT5645_HP_SG_MASK,
1732 RT5645_HP_CO_EN | RT5645_HP_SG_EN);
1733 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1734 0x14, 0x1aaa);
1735 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1736 0x24, 0x0430);
1737 }
1738 }
1739 hp_amp_power_count++;
1740 } else {
1741 hp_amp_power_count--;
1742 if (hp_amp_power_count <= 0) {
1743 if (rt5645->codec_type == CODEC_TYPE_RT5650) {
1744 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1745 0x3e, 0x7400);
1746 snd_soc_component_write(component, RT5645_DEPOP_M3, 0x0737);
1747 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1748 RT5645_MAMP_INT_REG2, 0xfc00);
1749 snd_soc_component_write(component, RT5645_DEPOP_M2, 0x1140);
1750 msleep(100);
1751 snd_soc_component_write(component, RT5645_DEPOP_M1, 0x0001);
1752 snd_soc_component_update_bits(component, RT5645_PWR_ANLG1,
1753 RT5645_PWR_HP_L | RT5645_PWR_HP_R, 0);
1754 } else {
1755 snd_soc_component_update_bits(component, RT5645_DEPOP_M1,
1756 RT5645_HP_SG_MASK |
1757 RT5645_HP_L_SMT_MASK |
1758 RT5645_HP_R_SMT_MASK,
1759 RT5645_HP_SG_DIS |
1760 RT5645_HP_L_SMT_DIS |
1761 RT5645_HP_R_SMT_DIS);
1762 /* headphone amp power down */
1763 snd_soc_component_write(component, RT5645_DEPOP_M1, 0x0000);
1764 snd_soc_component_update_bits(component, RT5645_PWR_ANLG1,
1765 RT5645_PWR_HP_L | RT5645_PWR_HP_R |
1766 RT5645_PWR_HA, 0);
1767 snd_soc_component_update_bits(component, RT5645_DEPOP_M2,
1768 RT5645_DEPOP_MASK, 0);
1769 }
1770 }
1771 }
1772 }
1773
rt5645_hp_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)1774 static int rt5645_hp_event(struct snd_soc_dapm_widget *w,
1775 struct snd_kcontrol *kcontrol, int event)
1776 {
1777 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1778 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
1779
1780 switch (event) {
1781 case SND_SOC_DAPM_POST_PMU:
1782 hp_amp_power(component, 1);
1783 /* headphone unmute sequence */
1784 if (rt5645->codec_type == CODEC_TYPE_RT5645) {
1785 snd_soc_component_update_bits(component, RT5645_DEPOP_M3,
1786 RT5645_CP_FQ1_MASK | RT5645_CP_FQ2_MASK |
1787 RT5645_CP_FQ3_MASK,
1788 (RT5645_CP_FQ_192_KHZ << RT5645_CP_FQ1_SFT) |
1789 (RT5645_CP_FQ_12_KHZ << RT5645_CP_FQ2_SFT) |
1790 (RT5645_CP_FQ_192_KHZ << RT5645_CP_FQ3_SFT));
1791 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1792 RT5645_MAMP_INT_REG2, 0xfc00);
1793 snd_soc_component_update_bits(component, RT5645_DEPOP_M1,
1794 RT5645_SMT_TRIG_MASK, RT5645_SMT_TRIG_EN);
1795 snd_soc_component_update_bits(component, RT5645_DEPOP_M1,
1796 RT5645_RSTN_MASK, RT5645_RSTN_EN);
1797 snd_soc_component_update_bits(component, RT5645_DEPOP_M1,
1798 RT5645_RSTN_MASK | RT5645_HP_L_SMT_MASK |
1799 RT5645_HP_R_SMT_MASK, RT5645_RSTN_DIS |
1800 RT5645_HP_L_SMT_EN | RT5645_HP_R_SMT_EN);
1801 msleep(40);
1802 snd_soc_component_update_bits(component, RT5645_DEPOP_M1,
1803 RT5645_HP_SG_MASK | RT5645_HP_L_SMT_MASK |
1804 RT5645_HP_R_SMT_MASK, RT5645_HP_SG_DIS |
1805 RT5645_HP_L_SMT_DIS | RT5645_HP_R_SMT_DIS);
1806 }
1807 break;
1808
1809 case SND_SOC_DAPM_PRE_PMD:
1810 /* headphone mute sequence */
1811 if (rt5645->codec_type == CODEC_TYPE_RT5645) {
1812 snd_soc_component_update_bits(component, RT5645_DEPOP_M3,
1813 RT5645_CP_FQ1_MASK | RT5645_CP_FQ2_MASK |
1814 RT5645_CP_FQ3_MASK,
1815 (RT5645_CP_FQ_96_KHZ << RT5645_CP_FQ1_SFT) |
1816 (RT5645_CP_FQ_12_KHZ << RT5645_CP_FQ2_SFT) |
1817 (RT5645_CP_FQ_96_KHZ << RT5645_CP_FQ3_SFT));
1818 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1819 RT5645_MAMP_INT_REG2, 0xfc00);
1820 snd_soc_component_update_bits(component, RT5645_DEPOP_M1,
1821 RT5645_HP_SG_MASK, RT5645_HP_SG_EN);
1822 snd_soc_component_update_bits(component, RT5645_DEPOP_M1,
1823 RT5645_RSTP_MASK, RT5645_RSTP_EN);
1824 snd_soc_component_update_bits(component, RT5645_DEPOP_M1,
1825 RT5645_RSTP_MASK | RT5645_HP_L_SMT_MASK |
1826 RT5645_HP_R_SMT_MASK, RT5645_RSTP_DIS |
1827 RT5645_HP_L_SMT_EN | RT5645_HP_R_SMT_EN);
1828 msleep(30);
1829 }
1830 hp_amp_power(component, 0);
1831 break;
1832
1833 default:
1834 return 0;
1835 }
1836
1837 return 0;
1838 }
1839
rt5645_spk_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)1840 static int rt5645_spk_event(struct snd_soc_dapm_widget *w,
1841 struct snd_kcontrol *kcontrol, int event)
1842 {
1843 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1844
1845 switch (event) {
1846 case SND_SOC_DAPM_POST_PMU:
1847 rt5645_enable_hweq(component);
1848 snd_soc_component_update_bits(component, RT5645_PWR_DIG1,
1849 RT5645_PWR_CLS_D | RT5645_PWR_CLS_D_R |
1850 RT5645_PWR_CLS_D_L,
1851 RT5645_PWR_CLS_D | RT5645_PWR_CLS_D_R |
1852 RT5645_PWR_CLS_D_L);
1853 snd_soc_component_update_bits(component, RT5645_GEN_CTRL3,
1854 RT5645_DET_CLK_MASK, RT5645_DET_CLK_MODE1);
1855 break;
1856
1857 case SND_SOC_DAPM_PRE_PMD:
1858 snd_soc_component_update_bits(component, RT5645_GEN_CTRL3,
1859 RT5645_DET_CLK_MASK, RT5645_DET_CLK_DIS);
1860 snd_soc_component_write(component, RT5645_EQ_CTRL2, 0);
1861 snd_soc_component_update_bits(component, RT5645_PWR_DIG1,
1862 RT5645_PWR_CLS_D | RT5645_PWR_CLS_D_R |
1863 RT5645_PWR_CLS_D_L, 0);
1864 break;
1865
1866 default:
1867 return 0;
1868 }
1869
1870 return 0;
1871 }
1872
rt5645_lout_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)1873 static int rt5645_lout_event(struct snd_soc_dapm_widget *w,
1874 struct snd_kcontrol *kcontrol, int event)
1875 {
1876 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1877
1878 switch (event) {
1879 case SND_SOC_DAPM_POST_PMU:
1880 hp_amp_power(component, 1);
1881 snd_soc_component_update_bits(component, RT5645_PWR_ANLG1,
1882 RT5645_PWR_LM, RT5645_PWR_LM);
1883 snd_soc_component_update_bits(component, RT5645_LOUT1,
1884 RT5645_L_MUTE | RT5645_R_MUTE, 0);
1885 break;
1886
1887 case SND_SOC_DAPM_PRE_PMD:
1888 snd_soc_component_update_bits(component, RT5645_LOUT1,
1889 RT5645_L_MUTE | RT5645_R_MUTE,
1890 RT5645_L_MUTE | RT5645_R_MUTE);
1891 snd_soc_component_update_bits(component, RT5645_PWR_ANLG1,
1892 RT5645_PWR_LM, 0);
1893 hp_amp_power(component, 0);
1894 break;
1895
1896 default:
1897 return 0;
1898 }
1899
1900 return 0;
1901 }
1902
rt5645_bst2_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)1903 static int rt5645_bst2_event(struct snd_soc_dapm_widget *w,
1904 struct snd_kcontrol *kcontrol, int event)
1905 {
1906 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1907
1908 switch (event) {
1909 case SND_SOC_DAPM_POST_PMU:
1910 snd_soc_component_update_bits(component, RT5645_PWR_ANLG2,
1911 RT5645_PWR_BST2_P, RT5645_PWR_BST2_P);
1912 break;
1913
1914 case SND_SOC_DAPM_PRE_PMD:
1915 snd_soc_component_update_bits(component, RT5645_PWR_ANLG2,
1916 RT5645_PWR_BST2_P, 0);
1917 break;
1918
1919 default:
1920 return 0;
1921 }
1922
1923 return 0;
1924 }
1925
rt5645_set_micbias1_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * k,int event)1926 static int rt5645_set_micbias1_event(struct snd_soc_dapm_widget *w,
1927 struct snd_kcontrol *k, int event)
1928 {
1929 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1930
1931 switch (event) {
1932 case SND_SOC_DAPM_PRE_PMU:
1933 snd_soc_component_update_bits(component, RT5645_GEN_CTRL2,
1934 RT5645_MICBIAS1_POW_CTRL_SEL_MASK,
1935 RT5645_MICBIAS1_POW_CTRL_SEL_M);
1936 break;
1937
1938 case SND_SOC_DAPM_POST_PMD:
1939 snd_soc_component_update_bits(component, RT5645_GEN_CTRL2,
1940 RT5645_MICBIAS1_POW_CTRL_SEL_MASK,
1941 RT5645_MICBIAS1_POW_CTRL_SEL_A);
1942 break;
1943
1944 default:
1945 return 0;
1946 }
1947
1948 return 0;
1949 }
1950
rt5645_set_micbias2_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * k,int event)1951 static int rt5645_set_micbias2_event(struct snd_soc_dapm_widget *w,
1952 struct snd_kcontrol *k, int event)
1953 {
1954 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1955
1956 switch (event) {
1957 case SND_SOC_DAPM_PRE_PMU:
1958 snd_soc_component_update_bits(component, RT5645_GEN_CTRL2,
1959 RT5645_MICBIAS2_POW_CTRL_SEL_MASK,
1960 RT5645_MICBIAS2_POW_CTRL_SEL_M);
1961 break;
1962
1963 case SND_SOC_DAPM_POST_PMD:
1964 snd_soc_component_update_bits(component, RT5645_GEN_CTRL2,
1965 RT5645_MICBIAS2_POW_CTRL_SEL_MASK,
1966 RT5645_MICBIAS2_POW_CTRL_SEL_A);
1967 break;
1968
1969 default:
1970 return 0;
1971 }
1972
1973 return 0;
1974 }
1975
1976 static const struct snd_soc_dapm_widget rt5645_dapm_widgets[] = {
1977 SND_SOC_DAPM_SUPPLY("LDO2", RT5645_PWR_MIXER,
1978 RT5645_PWR_LDO2_BIT, 0, NULL, 0),
1979 SND_SOC_DAPM_SUPPLY("PLL1", RT5645_PWR_ANLG2,
1980 RT5645_PWR_PLL_BIT, 0, NULL, 0),
1981
1982 SND_SOC_DAPM_SUPPLY("JD Power", RT5645_PWR_ANLG2,
1983 RT5645_PWR_JD1_BIT, 0, NULL, 0),
1984 SND_SOC_DAPM_SUPPLY("Mic Det Power", RT5645_PWR_VOL,
1985 RT5645_PWR_MIC_DET_BIT, 0, NULL, 0),
1986
1987 /* ASRC */
1988 SND_SOC_DAPM_SUPPLY_S("I2S1 ASRC", 1, RT5645_ASRC_1,
1989 11, 0, NULL, 0),
1990 SND_SOC_DAPM_SUPPLY_S("I2S2 ASRC", 1, RT5645_ASRC_1,
1991 12, 0, NULL, 0),
1992 SND_SOC_DAPM_SUPPLY_S("DAC STO ASRC", 1, RT5645_ASRC_1,
1993 10, 0, NULL, 0),
1994 SND_SOC_DAPM_SUPPLY_S("DAC MONO L ASRC", 1, RT5645_ASRC_1,
1995 9, 0, NULL, 0),
1996 SND_SOC_DAPM_SUPPLY_S("DAC MONO R ASRC", 1, RT5645_ASRC_1,
1997 8, 0, NULL, 0),
1998 SND_SOC_DAPM_SUPPLY_S("DMIC STO1 ASRC", 1, RT5645_ASRC_1,
1999 7, 0, NULL, 0),
2000 SND_SOC_DAPM_SUPPLY_S("DMIC MONO L ASRC", 1, RT5645_ASRC_1,
2001 5, 0, NULL, 0),
2002 SND_SOC_DAPM_SUPPLY_S("DMIC MONO R ASRC", 1, RT5645_ASRC_1,
2003 4, 0, NULL, 0),
2004 SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5645_ASRC_1,
2005 3, 0, NULL, 0),
2006 SND_SOC_DAPM_SUPPLY_S("ADC MONO L ASRC", 1, RT5645_ASRC_1,
2007 1, 0, NULL, 0),
2008 SND_SOC_DAPM_SUPPLY_S("ADC MONO R ASRC", 1, RT5645_ASRC_1,
2009 0, 0, NULL, 0),
2010
2011 /* Input Side */
2012 /* micbias */
2013 SND_SOC_DAPM_SUPPLY("micbias1", RT5645_PWR_ANLG2,
2014 RT5645_PWR_MB1_BIT, 0, rt5645_set_micbias1_event,
2015 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2016 SND_SOC_DAPM_SUPPLY("micbias2", RT5645_PWR_ANLG2,
2017 RT5645_PWR_MB2_BIT, 0, rt5645_set_micbias2_event,
2018 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2019 /* Input Lines */
2020 SND_SOC_DAPM_INPUT("DMIC L1"),
2021 SND_SOC_DAPM_INPUT("DMIC R1"),
2022 SND_SOC_DAPM_INPUT("DMIC L2"),
2023 SND_SOC_DAPM_INPUT("DMIC R2"),
2024
2025 SND_SOC_DAPM_INPUT("IN1P"),
2026 SND_SOC_DAPM_INPUT("IN1N"),
2027 SND_SOC_DAPM_INPUT("IN2P"),
2028 SND_SOC_DAPM_INPUT("IN2N"),
2029
2030 SND_SOC_DAPM_INPUT("Haptic Generator"),
2031
2032 SND_SOC_DAPM_PGA("DMIC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2033 SND_SOC_DAPM_PGA("DMIC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2034 SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
2035 set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
2036 SND_SOC_DAPM_SUPPLY("DMIC1 Power", RT5645_DMIC_CTRL1,
2037 RT5645_DMIC_1_EN_SFT, 0, NULL, 0),
2038 SND_SOC_DAPM_SUPPLY("DMIC2 Power", RT5645_DMIC_CTRL1,
2039 RT5645_DMIC_2_EN_SFT, 0, NULL, 0),
2040 /* Boost */
2041 SND_SOC_DAPM_PGA("BST1", RT5645_PWR_ANLG2,
2042 RT5645_PWR_BST1_BIT, 0, NULL, 0),
2043 SND_SOC_DAPM_PGA_E("BST2", RT5645_PWR_ANLG2,
2044 RT5645_PWR_BST2_BIT, 0, NULL, 0, rt5645_bst2_event,
2045 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
2046 /* Input Volume */
2047 SND_SOC_DAPM_PGA("INL VOL", RT5645_PWR_VOL,
2048 RT5645_PWR_IN_L_BIT, 0, NULL, 0),
2049 SND_SOC_DAPM_PGA("INR VOL", RT5645_PWR_VOL,
2050 RT5645_PWR_IN_R_BIT, 0, NULL, 0),
2051 /* REC Mixer */
2052 SND_SOC_DAPM_MIXER("RECMIXL", RT5645_PWR_MIXER, RT5645_PWR_RM_L_BIT,
2053 0, rt5645_rec_l_mix, ARRAY_SIZE(rt5645_rec_l_mix)),
2054 SND_SOC_DAPM_MIXER("RECMIXR", RT5645_PWR_MIXER, RT5645_PWR_RM_R_BIT,
2055 0, rt5645_rec_r_mix, ARRAY_SIZE(rt5645_rec_r_mix)),
2056 /* ADCs */
2057 SND_SOC_DAPM_ADC("ADC L", NULL, SND_SOC_NOPM, 0, 0),
2058 SND_SOC_DAPM_ADC("ADC R", NULL, SND_SOC_NOPM, 0, 0),
2059
2060 SND_SOC_DAPM_SUPPLY("ADC L power", RT5645_PWR_DIG1,
2061 RT5645_PWR_ADC_L_BIT, 0, NULL, 0),
2062 SND_SOC_DAPM_SUPPLY("ADC R power", RT5645_PWR_DIG1,
2063 RT5645_PWR_ADC_R_BIT, 0, NULL, 0),
2064
2065 /* ADC Mux */
2066 SND_SOC_DAPM_MUX("Stereo1 DMIC Mux", SND_SOC_NOPM, 0, 0,
2067 &rt5645_sto1_dmic_mux),
2068 SND_SOC_DAPM_MUX("Stereo1 ADC L2 Mux", SND_SOC_NOPM, 0, 0,
2069 &rt5645_sto_adc2_mux),
2070 SND_SOC_DAPM_MUX("Stereo1 ADC R2 Mux", SND_SOC_NOPM, 0, 0,
2071 &rt5645_sto_adc2_mux),
2072 SND_SOC_DAPM_MUX("Stereo1 ADC L1 Mux", SND_SOC_NOPM, 0, 0,
2073 &rt5645_sto_adc1_mux),
2074 SND_SOC_DAPM_MUX("Stereo1 ADC R1 Mux", SND_SOC_NOPM, 0, 0,
2075 &rt5645_sto_adc1_mux),
2076 SND_SOC_DAPM_MUX("Mono DMIC L Mux", SND_SOC_NOPM, 0, 0,
2077 &rt5645_mono_dmic_l_mux),
2078 SND_SOC_DAPM_MUX("Mono DMIC R Mux", SND_SOC_NOPM, 0, 0,
2079 &rt5645_mono_dmic_r_mux),
2080 SND_SOC_DAPM_MUX("Mono ADC L2 Mux", SND_SOC_NOPM, 0, 0,
2081 &rt5645_mono_adc_l2_mux),
2082 SND_SOC_DAPM_MUX("Mono ADC L1 Mux", SND_SOC_NOPM, 0, 0,
2083 &rt5645_mono_adc_l1_mux),
2084 SND_SOC_DAPM_MUX("Mono ADC R1 Mux", SND_SOC_NOPM, 0, 0,
2085 &rt5645_mono_adc_r1_mux),
2086 SND_SOC_DAPM_MUX("Mono ADC R2 Mux", SND_SOC_NOPM, 0, 0,
2087 &rt5645_mono_adc_r2_mux),
2088 /* ADC Mixer */
2089
2090 SND_SOC_DAPM_SUPPLY_S("adc stereo1 filter", 1, RT5645_PWR_DIG2,
2091 RT5645_PWR_ADC_S1F_BIT, 0, NULL, 0),
2092 SND_SOC_DAPM_MIXER_E("Sto1 ADC MIXL", SND_SOC_NOPM, 0, 0,
2093 rt5645_sto1_adc_l_mix, ARRAY_SIZE(rt5645_sto1_adc_l_mix),
2094 NULL, 0),
2095 SND_SOC_DAPM_MIXER_E("Sto1 ADC MIXR", SND_SOC_NOPM, 0, 0,
2096 rt5645_sto1_adc_r_mix, ARRAY_SIZE(rt5645_sto1_adc_r_mix),
2097 NULL, 0),
2098 SND_SOC_DAPM_SUPPLY_S("adc mono left filter", 1, RT5645_PWR_DIG2,
2099 RT5645_PWR_ADC_MF_L_BIT, 0, NULL, 0),
2100 SND_SOC_DAPM_MIXER_E("Mono ADC MIXL", SND_SOC_NOPM, 0, 0,
2101 rt5645_mono_adc_l_mix, ARRAY_SIZE(rt5645_mono_adc_l_mix),
2102 NULL, 0),
2103 SND_SOC_DAPM_SUPPLY_S("adc mono right filter", 1, RT5645_PWR_DIG2,
2104 RT5645_PWR_ADC_MF_R_BIT, 0, NULL, 0),
2105 SND_SOC_DAPM_MIXER_E("Mono ADC MIXR", SND_SOC_NOPM, 0, 0,
2106 rt5645_mono_adc_r_mix, ARRAY_SIZE(rt5645_mono_adc_r_mix),
2107 NULL, 0),
2108
2109 /* ADC PGA */
2110 SND_SOC_DAPM_PGA("Stereo1 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
2111 SND_SOC_DAPM_PGA("Stereo1 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
2112 SND_SOC_DAPM_PGA("Sto2 ADC LR MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2113 SND_SOC_DAPM_PGA("VAD_ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2114 SND_SOC_DAPM_PGA("IF_ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2115 SND_SOC_DAPM_PGA("IF_ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2116 SND_SOC_DAPM_PGA("IF1_ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2117 SND_SOC_DAPM_PGA("IF1_ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2118 SND_SOC_DAPM_PGA("IF1_ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2119 SND_SOC_DAPM_PGA("IF1_ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2120
2121 /* IF1 2 Mux */
2122 SND_SOC_DAPM_MUX("IF2 ADC Mux", SND_SOC_NOPM,
2123 0, 0, &rt5645_if2_adc_in_mux),
2124
2125 /* Digital Interface */
2126 SND_SOC_DAPM_SUPPLY("I2S1", RT5645_PWR_DIG1,
2127 RT5645_PWR_I2S1_BIT, 0, NULL, 0),
2128 SND_SOC_DAPM_PGA("IF1 DAC0", SND_SOC_NOPM, 0, 0, NULL, 0),
2129 SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2130 SND_SOC_DAPM_PGA("IF1 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2131 SND_SOC_DAPM_PGA("IF1 DAC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2132 SND_SOC_DAPM_PGA("IF1 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2133 SND_SOC_DAPM_PGA("IF1 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2134 SND_SOC_DAPM_PGA("IF1 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2135 SND_SOC_DAPM_SUPPLY("I2S2", RT5645_PWR_DIG1,
2136 RT5645_PWR_I2S2_BIT, 0, NULL, 0),
2137 SND_SOC_DAPM_PGA("IF2 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
2138 SND_SOC_DAPM_PGA("IF2 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2139 SND_SOC_DAPM_PGA("IF2 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2140 SND_SOC_DAPM_PGA("IF2 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2141
2142 /* Digital Interface Select */
2143 SND_SOC_DAPM_MUX("VAD ADC Mux", SND_SOC_NOPM,
2144 0, 0, &rt5645_vad_adc_mux),
2145
2146 /* Audio Interface */
2147 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
2148 SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
2149 SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
2150 SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
2151
2152 /* Output Side */
2153 /* DAC mixer before sound effect */
2154 SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0,
2155 rt5645_dac_l_mix, ARRAY_SIZE(rt5645_dac_l_mix)),
2156 SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0,
2157 rt5645_dac_r_mix, ARRAY_SIZE(rt5645_dac_r_mix)),
2158
2159 /* DAC2 channel Mux */
2160 SND_SOC_DAPM_MUX("DAC L2 Mux", SND_SOC_NOPM, 0, 0, &rt5645_dac_l2_mux),
2161 SND_SOC_DAPM_MUX("DAC R2 Mux", SND_SOC_NOPM, 0, 0, &rt5645_dac_r2_mux),
2162 SND_SOC_DAPM_PGA("DAC L2 Volume", RT5645_PWR_DIG1,
2163 RT5645_PWR_DAC_L2_BIT, 0, NULL, 0),
2164 SND_SOC_DAPM_PGA("DAC R2 Volume", RT5645_PWR_DIG1,
2165 RT5645_PWR_DAC_R2_BIT, 0, NULL, 0),
2166
2167 SND_SOC_DAPM_MUX("DAC1 L Mux", SND_SOC_NOPM, 0, 0, &rt5645_dac1l_mux),
2168 SND_SOC_DAPM_MUX("DAC1 R Mux", SND_SOC_NOPM, 0, 0, &rt5645_dac1r_mux),
2169
2170 /* DAC Mixer */
2171 SND_SOC_DAPM_SUPPLY_S("dac stereo1 filter", 1, RT5645_PWR_DIG2,
2172 RT5645_PWR_DAC_S1F_BIT, 0, NULL, 0),
2173 SND_SOC_DAPM_SUPPLY_S("dac mono left filter", 1, RT5645_PWR_DIG2,
2174 RT5645_PWR_DAC_MF_L_BIT, 0, NULL, 0),
2175 SND_SOC_DAPM_SUPPLY_S("dac mono right filter", 1, RT5645_PWR_DIG2,
2176 RT5645_PWR_DAC_MF_R_BIT, 0, NULL, 0),
2177 SND_SOC_DAPM_MIXER("Stereo DAC MIXL", SND_SOC_NOPM, 0, 0,
2178 rt5645_sto_dac_l_mix, ARRAY_SIZE(rt5645_sto_dac_l_mix)),
2179 SND_SOC_DAPM_MIXER("Stereo DAC MIXR", SND_SOC_NOPM, 0, 0,
2180 rt5645_sto_dac_r_mix, ARRAY_SIZE(rt5645_sto_dac_r_mix)),
2181 SND_SOC_DAPM_MIXER("Mono DAC MIXL", SND_SOC_NOPM, 0, 0,
2182 rt5645_mono_dac_l_mix, ARRAY_SIZE(rt5645_mono_dac_l_mix)),
2183 SND_SOC_DAPM_MIXER("Mono DAC MIXR", SND_SOC_NOPM, 0, 0,
2184 rt5645_mono_dac_r_mix, ARRAY_SIZE(rt5645_mono_dac_r_mix)),
2185 SND_SOC_DAPM_MIXER("DAC MIXL", SND_SOC_NOPM, 0, 0,
2186 rt5645_dig_l_mix, ARRAY_SIZE(rt5645_dig_l_mix)),
2187 SND_SOC_DAPM_MIXER("DAC MIXR", SND_SOC_NOPM, 0, 0,
2188 rt5645_dig_r_mix, ARRAY_SIZE(rt5645_dig_r_mix)),
2189
2190 /* DACs */
2191 SND_SOC_DAPM_DAC("DAC L1", NULL, RT5645_PWR_DIG1, RT5645_PWR_DAC_L1_BIT,
2192 0),
2193 SND_SOC_DAPM_DAC("DAC L2", NULL, RT5645_PWR_DIG1, RT5645_PWR_DAC_L2_BIT,
2194 0),
2195 SND_SOC_DAPM_DAC("DAC R1", NULL, RT5645_PWR_DIG1, RT5645_PWR_DAC_R1_BIT,
2196 0),
2197 SND_SOC_DAPM_DAC("DAC R2", NULL, RT5645_PWR_DIG1, RT5645_PWR_DAC_R2_BIT,
2198 0),
2199 /* OUT Mixer */
2200 SND_SOC_DAPM_MIXER("SPK MIXL", RT5645_PWR_MIXER, RT5645_PWR_SM_L_BIT,
2201 0, rt5645_spk_l_mix, ARRAY_SIZE(rt5645_spk_l_mix)),
2202 SND_SOC_DAPM_MIXER("SPK MIXR", RT5645_PWR_MIXER, RT5645_PWR_SM_R_BIT,
2203 0, rt5645_spk_r_mix, ARRAY_SIZE(rt5645_spk_r_mix)),
2204 SND_SOC_DAPM_MIXER("OUT MIXL", RT5645_PWR_MIXER, RT5645_PWR_OM_L_BIT,
2205 0, rt5645_out_l_mix, ARRAY_SIZE(rt5645_out_l_mix)),
2206 SND_SOC_DAPM_MIXER("OUT MIXR", RT5645_PWR_MIXER, RT5645_PWR_OM_R_BIT,
2207 0, rt5645_out_r_mix, ARRAY_SIZE(rt5645_out_r_mix)),
2208 /* Ouput Volume */
2209 SND_SOC_DAPM_SWITCH("SPKVOL L", RT5645_PWR_VOL, RT5645_PWR_SV_L_BIT, 0,
2210 &spk_l_vol_control),
2211 SND_SOC_DAPM_SWITCH("SPKVOL R", RT5645_PWR_VOL, RT5645_PWR_SV_R_BIT, 0,
2212 &spk_r_vol_control),
2213 SND_SOC_DAPM_MIXER("HPOVOL MIXL", RT5645_PWR_VOL, RT5645_PWR_HV_L_BIT,
2214 0, rt5645_hpvoll_mix, ARRAY_SIZE(rt5645_hpvoll_mix)),
2215 SND_SOC_DAPM_MIXER("HPOVOL MIXR", RT5645_PWR_VOL, RT5645_PWR_HV_R_BIT,
2216 0, rt5645_hpvolr_mix, ARRAY_SIZE(rt5645_hpvolr_mix)),
2217 SND_SOC_DAPM_SUPPLY("HPOVOL MIXL Power", RT5645_PWR_MIXER,
2218 RT5645_PWR_HM_L_BIT, 0, NULL, 0),
2219 SND_SOC_DAPM_SUPPLY("HPOVOL MIXR Power", RT5645_PWR_MIXER,
2220 RT5645_PWR_HM_R_BIT, 0, NULL, 0),
2221 SND_SOC_DAPM_PGA("DAC 1", SND_SOC_NOPM, 0, 0, NULL, 0),
2222 SND_SOC_DAPM_PGA("DAC 2", SND_SOC_NOPM, 0, 0, NULL, 0),
2223 SND_SOC_DAPM_PGA("HPOVOL", SND_SOC_NOPM, 0, 0, NULL, 0),
2224 SND_SOC_DAPM_SWITCH("HPOVOL L", SND_SOC_NOPM, 0, 0, &hp_l_vol_control),
2225 SND_SOC_DAPM_SWITCH("HPOVOL R", SND_SOC_NOPM, 0, 0, &hp_r_vol_control),
2226
2227 /* HPO/LOUT/Mono Mixer */
2228 SND_SOC_DAPM_MIXER("SPOL MIX", SND_SOC_NOPM, 0, 0, rt5645_spo_l_mix,
2229 ARRAY_SIZE(rt5645_spo_l_mix)),
2230 SND_SOC_DAPM_MIXER("SPOR MIX", SND_SOC_NOPM, 0, 0, rt5645_spo_r_mix,
2231 ARRAY_SIZE(rt5645_spo_r_mix)),
2232 SND_SOC_DAPM_MIXER("HPO MIX", SND_SOC_NOPM, 0, 0, rt5645_hpo_mix,
2233 ARRAY_SIZE(rt5645_hpo_mix)),
2234 SND_SOC_DAPM_MIXER("LOUT MIX", SND_SOC_NOPM, 0, 0, rt5645_lout_mix,
2235 ARRAY_SIZE(rt5645_lout_mix)),
2236
2237 SND_SOC_DAPM_PGA_S("HP amp", 1, SND_SOC_NOPM, 0, 0, rt5645_hp_event,
2238 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
2239 SND_SOC_DAPM_PGA_S("LOUT amp", 1, SND_SOC_NOPM, 0, 0, rt5645_lout_event,
2240 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
2241 SND_SOC_DAPM_PGA_S("SPK amp", 2, SND_SOC_NOPM, 0, 0, rt5645_spk_event,
2242 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
2243
2244 /* PDM */
2245 SND_SOC_DAPM_SUPPLY("PDM1 Power", RT5645_PWR_DIG2, RT5645_PWR_PDM1_BIT,
2246 0, NULL, 0),
2247 SND_SOC_DAPM_MUX("PDM1 L Mux", SND_SOC_NOPM, 0, 0, &rt5645_pdm1_l_mux),
2248 SND_SOC_DAPM_MUX("PDM1 R Mux", SND_SOC_NOPM, 0, 0, &rt5645_pdm1_r_mux),
2249
2250 SND_SOC_DAPM_SWITCH("PDM1 L", SND_SOC_NOPM, 0, 0, &pdm1_l_vol_control),
2251 SND_SOC_DAPM_SWITCH("PDM1 R", SND_SOC_NOPM, 0, 0, &pdm1_r_vol_control),
2252
2253 /* Output Lines */
2254 SND_SOC_DAPM_OUTPUT("HPOL"),
2255 SND_SOC_DAPM_OUTPUT("HPOR"),
2256 SND_SOC_DAPM_OUTPUT("LOUTL"),
2257 SND_SOC_DAPM_OUTPUT("LOUTR"),
2258 SND_SOC_DAPM_OUTPUT("PDM1L"),
2259 SND_SOC_DAPM_OUTPUT("PDM1R"),
2260 SND_SOC_DAPM_OUTPUT("SPOL"),
2261 SND_SOC_DAPM_OUTPUT("SPOR"),
2262 };
2263
2264 static const struct snd_soc_dapm_widget rt5645_specific_dapm_widgets[] = {
2265 SND_SOC_DAPM_MUX("RT5645 IF1 DAC1 L Mux", SND_SOC_NOPM, 0, 0,
2266 &rt5645_if1_dac0_tdm_sel_mux),
2267 SND_SOC_DAPM_MUX("RT5645 IF1 DAC1 R Mux", SND_SOC_NOPM, 0, 0,
2268 &rt5645_if1_dac1_tdm_sel_mux),
2269 SND_SOC_DAPM_MUX("RT5645 IF1 DAC2 L Mux", SND_SOC_NOPM, 0, 0,
2270 &rt5645_if1_dac2_tdm_sel_mux),
2271 SND_SOC_DAPM_MUX("RT5645 IF1 DAC2 R Mux", SND_SOC_NOPM, 0, 0,
2272 &rt5645_if1_dac3_tdm_sel_mux),
2273 SND_SOC_DAPM_MUX("RT5645 IF1 ADC Mux", SND_SOC_NOPM,
2274 0, 0, &rt5645_if1_adc_in_mux),
2275 SND_SOC_DAPM_MUX("RT5645 IF1 ADC1 Swap Mux", SND_SOC_NOPM,
2276 0, 0, &rt5645_if1_adc1_in_mux),
2277 SND_SOC_DAPM_MUX("RT5645 IF1 ADC2 Swap Mux", SND_SOC_NOPM,
2278 0, 0, &rt5645_if1_adc2_in_mux),
2279 SND_SOC_DAPM_MUX("RT5645 IF1 ADC3 Swap Mux", SND_SOC_NOPM,
2280 0, 0, &rt5645_if1_adc3_in_mux),
2281 };
2282
2283 static const struct snd_soc_dapm_widget rt5650_specific_dapm_widgets[] = {
2284 SND_SOC_DAPM_MUX("A DAC1 L Mux", SND_SOC_NOPM,
2285 0, 0, &rt5650_a_dac1_l_mux),
2286 SND_SOC_DAPM_MUX("A DAC1 R Mux", SND_SOC_NOPM,
2287 0, 0, &rt5650_a_dac1_r_mux),
2288 SND_SOC_DAPM_MUX("A DAC2 L Mux", SND_SOC_NOPM,
2289 0, 0, &rt5650_a_dac2_l_mux),
2290 SND_SOC_DAPM_MUX("A DAC2 R Mux", SND_SOC_NOPM,
2291 0, 0, &rt5650_a_dac2_r_mux),
2292
2293 SND_SOC_DAPM_MUX("RT5650 IF1 ADC1 Swap Mux", SND_SOC_NOPM,
2294 0, 0, &rt5650_if1_adc1_in_mux),
2295 SND_SOC_DAPM_MUX("RT5650 IF1 ADC2 Swap Mux", SND_SOC_NOPM,
2296 0, 0, &rt5650_if1_adc2_in_mux),
2297 SND_SOC_DAPM_MUX("RT5650 IF1 ADC3 Swap Mux", SND_SOC_NOPM,
2298 0, 0, &rt5650_if1_adc3_in_mux),
2299 SND_SOC_DAPM_MUX("RT5650 IF1 ADC Mux", SND_SOC_NOPM,
2300 0, 0, &rt5650_if1_adc_in_mux),
2301
2302 SND_SOC_DAPM_MUX("RT5650 IF1 DAC1 L Mux", SND_SOC_NOPM, 0, 0,
2303 &rt5650_if1_dac0_tdm_sel_mux),
2304 SND_SOC_DAPM_MUX("RT5650 IF1 DAC1 R Mux", SND_SOC_NOPM, 0, 0,
2305 &rt5650_if1_dac1_tdm_sel_mux),
2306 SND_SOC_DAPM_MUX("RT5650 IF1 DAC2 L Mux", SND_SOC_NOPM, 0, 0,
2307 &rt5650_if1_dac2_tdm_sel_mux),
2308 SND_SOC_DAPM_MUX("RT5650 IF1 DAC2 R Mux", SND_SOC_NOPM, 0, 0,
2309 &rt5650_if1_dac3_tdm_sel_mux),
2310 };
2311
2312 static const struct snd_soc_dapm_route rt5645_dapm_routes[] = {
2313 { "adc stereo1 filter", NULL, "ADC STO1 ASRC", is_using_asrc },
2314 { "adc mono left filter", NULL, "ADC MONO L ASRC", is_using_asrc },
2315 { "adc mono right filter", NULL, "ADC MONO R ASRC", is_using_asrc },
2316 { "dac mono left filter", NULL, "DAC MONO L ASRC", is_using_asrc },
2317 { "dac mono right filter", NULL, "DAC MONO R ASRC", is_using_asrc },
2318 { "dac stereo1 filter", NULL, "DAC STO ASRC", is_using_asrc },
2319
2320 { "I2S1", NULL, "I2S1 ASRC" },
2321 { "I2S2", NULL, "I2S2 ASRC" },
2322
2323 { "IN1P", NULL, "LDO2" },
2324 { "IN2P", NULL, "LDO2" },
2325
2326 { "DMIC1", NULL, "DMIC L1" },
2327 { "DMIC1", NULL, "DMIC R1" },
2328 { "DMIC2", NULL, "DMIC L2" },
2329 { "DMIC2", NULL, "DMIC R2" },
2330
2331 { "BST1", NULL, "IN1P" },
2332 { "BST1", NULL, "IN1N" },
2333 { "BST1", NULL, "JD Power" },
2334 { "BST1", NULL, "Mic Det Power" },
2335 { "BST2", NULL, "IN2P" },
2336 { "BST2", NULL, "IN2N" },
2337
2338 { "INL VOL", NULL, "IN2P" },
2339 { "INR VOL", NULL, "IN2N" },
2340
2341 { "RECMIXL", "HPOL Switch", "HPOL" },
2342 { "RECMIXL", "INL Switch", "INL VOL" },
2343 { "RECMIXL", "BST2 Switch", "BST2" },
2344 { "RECMIXL", "BST1 Switch", "BST1" },
2345 { "RECMIXL", "OUT MIXL Switch", "OUT MIXL" },
2346
2347 { "RECMIXR", "HPOR Switch", "HPOR" },
2348 { "RECMIXR", "INR Switch", "INR VOL" },
2349 { "RECMIXR", "BST2 Switch", "BST2" },
2350 { "RECMIXR", "BST1 Switch", "BST1" },
2351 { "RECMIXR", "OUT MIXR Switch", "OUT MIXR" },
2352
2353 { "ADC L", NULL, "RECMIXL" },
2354 { "ADC L", NULL, "ADC L power" },
2355 { "ADC R", NULL, "RECMIXR" },
2356 { "ADC R", NULL, "ADC R power" },
2357
2358 {"DMIC L1", NULL, "DMIC CLK"},
2359 {"DMIC L1", NULL, "DMIC1 Power"},
2360 {"DMIC R1", NULL, "DMIC CLK"},
2361 {"DMIC R1", NULL, "DMIC1 Power"},
2362 {"DMIC L2", NULL, "DMIC CLK"},
2363 {"DMIC L2", NULL, "DMIC2 Power"},
2364 {"DMIC R2", NULL, "DMIC CLK"},
2365 {"DMIC R2", NULL, "DMIC2 Power"},
2366
2367 { "Stereo1 DMIC Mux", "DMIC1", "DMIC1" },
2368 { "Stereo1 DMIC Mux", "DMIC2", "DMIC2" },
2369 { "Stereo1 DMIC Mux", NULL, "DMIC STO1 ASRC" },
2370
2371 { "Mono DMIC L Mux", "DMIC1", "DMIC L1" },
2372 { "Mono DMIC L Mux", "DMIC2", "DMIC L2" },
2373 { "Mono DMIC L Mux", NULL, "DMIC MONO L ASRC" },
2374
2375 { "Mono DMIC R Mux", "DMIC1", "DMIC R1" },
2376 { "Mono DMIC R Mux", "DMIC2", "DMIC R2" },
2377 { "Mono DMIC R Mux", NULL, "DMIC MONO R ASRC" },
2378
2379 { "Stereo1 ADC L2 Mux", "DMIC", "Stereo1 DMIC Mux" },
2380 { "Stereo1 ADC L2 Mux", "DAC MIX", "DAC MIXL" },
2381 { "Stereo1 ADC L1 Mux", "ADC", "ADC L" },
2382 { "Stereo1 ADC L1 Mux", "DAC MIX", "DAC MIXL" },
2383
2384 { "Stereo1 ADC R1 Mux", "ADC", "ADC R" },
2385 { "Stereo1 ADC R1 Mux", "DAC MIX", "DAC MIXR" },
2386 { "Stereo1 ADC R2 Mux", "DMIC", "Stereo1 DMIC Mux" },
2387 { "Stereo1 ADC R2 Mux", "DAC MIX", "DAC MIXR" },
2388
2389 { "Mono ADC L2 Mux", "DMIC", "Mono DMIC L Mux" },
2390 { "Mono ADC L2 Mux", "Mono DAC MIXL", "Mono DAC MIXL" },
2391 { "Mono ADC L1 Mux", "Mono DAC MIXL", "Mono DAC MIXL" },
2392 { "Mono ADC L1 Mux", "ADC", "ADC L" },
2393
2394 { "Mono ADC R1 Mux", "Mono DAC MIXR", "Mono DAC MIXR" },
2395 { "Mono ADC R1 Mux", "ADC", "ADC R" },
2396 { "Mono ADC R2 Mux", "DMIC", "Mono DMIC R Mux" },
2397 { "Mono ADC R2 Mux", "Mono DAC MIXR", "Mono DAC MIXR" },
2398
2399 { "Sto1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC L1 Mux" },
2400 { "Sto1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC L2 Mux" },
2401 { "Sto1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC R1 Mux" },
2402 { "Sto1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC R2 Mux" },
2403
2404 { "Stereo1 ADC MIXL", NULL, "Sto1 ADC MIXL" },
2405 { "Stereo1 ADC MIXL", NULL, "adc stereo1 filter" },
2406 { "adc stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll },
2407
2408 { "Stereo1 ADC MIXR", NULL, "Sto1 ADC MIXR" },
2409 { "Stereo1 ADC MIXR", NULL, "adc stereo1 filter" },
2410 { "adc stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll },
2411
2412 { "Mono ADC MIXL", "ADC1 Switch", "Mono ADC L1 Mux" },
2413 { "Mono ADC MIXL", "ADC2 Switch", "Mono ADC L2 Mux" },
2414 { "Mono ADC MIXL", NULL, "adc mono left filter" },
2415 { "adc mono left filter", NULL, "PLL1", is_sys_clk_from_pll },
2416
2417 { "Mono ADC MIXR", "ADC1 Switch", "Mono ADC R1 Mux" },
2418 { "Mono ADC MIXR", "ADC2 Switch", "Mono ADC R2 Mux" },
2419 { "Mono ADC MIXR", NULL, "adc mono right filter" },
2420 { "adc mono right filter", NULL, "PLL1", is_sys_clk_from_pll },
2421
2422 { "VAD ADC Mux", "Sto1 ADC L", "Stereo1 ADC MIXL" },
2423 { "VAD ADC Mux", "Mono ADC L", "Mono ADC MIXL" },
2424 { "VAD ADC Mux", "Mono ADC R", "Mono ADC MIXR" },
2425
2426 { "IF_ADC1", NULL, "Stereo1 ADC MIXL" },
2427 { "IF_ADC1", NULL, "Stereo1 ADC MIXR" },
2428 { "IF_ADC2", NULL, "Mono ADC MIXL" },
2429 { "IF_ADC2", NULL, "Mono ADC MIXR" },
2430 { "VAD_ADC", NULL, "VAD ADC Mux" },
2431
2432 { "IF2 ADC Mux", "IF_ADC1", "IF_ADC1" },
2433 { "IF2 ADC Mux", "IF_ADC2", "IF_ADC2" },
2434 { "IF2 ADC Mux", "VAD_ADC", "VAD_ADC" },
2435
2436 { "IF1 ADC", NULL, "I2S1" },
2437 { "IF2 ADC", NULL, "I2S2" },
2438 { "IF2 ADC", NULL, "IF2 ADC Mux" },
2439
2440 { "AIF2TX", NULL, "IF2 ADC" },
2441
2442 { "IF1 DAC0", NULL, "AIF1RX" },
2443 { "IF1 DAC1", NULL, "AIF1RX" },
2444 { "IF1 DAC2", NULL, "AIF1RX" },
2445 { "IF1 DAC3", NULL, "AIF1RX" },
2446 { "IF2 DAC", NULL, "AIF2RX" },
2447
2448 { "IF1 DAC0", NULL, "I2S1" },
2449 { "IF1 DAC1", NULL, "I2S1" },
2450 { "IF1 DAC2", NULL, "I2S1" },
2451 { "IF1 DAC3", NULL, "I2S1" },
2452 { "IF2 DAC", NULL, "I2S2" },
2453
2454 { "IF2 DAC L", NULL, "IF2 DAC" },
2455 { "IF2 DAC R", NULL, "IF2 DAC" },
2456
2457 { "DAC1 L Mux", "IF2 DAC", "IF2 DAC L" },
2458 { "DAC1 R Mux", "IF2 DAC", "IF2 DAC R" },
2459
2460 { "DAC1 MIXL", "Stereo ADC Switch", "Stereo1 ADC MIXL" },
2461 { "DAC1 MIXL", "DAC1 Switch", "DAC1 L Mux" },
2462 { "DAC1 MIXL", NULL, "dac stereo1 filter" },
2463 { "DAC1 MIXR", "Stereo ADC Switch", "Stereo1 ADC MIXR" },
2464 { "DAC1 MIXR", "DAC1 Switch", "DAC1 R Mux" },
2465 { "DAC1 MIXR", NULL, "dac stereo1 filter" },
2466
2467 { "DAC L2 Mux", "IF2 DAC", "IF2 DAC L" },
2468 { "DAC L2 Mux", "Mono ADC", "Mono ADC MIXL" },
2469 { "DAC L2 Mux", "VAD_ADC", "VAD_ADC" },
2470 { "DAC L2 Volume", NULL, "DAC L2 Mux" },
2471 { "DAC L2 Volume", NULL, "dac mono left filter" },
2472
2473 { "DAC R2 Mux", "IF2 DAC", "IF2 DAC R" },
2474 { "DAC R2 Mux", "Mono ADC", "Mono ADC MIXR" },
2475 { "DAC R2 Mux", "Haptic", "Haptic Generator" },
2476 { "DAC R2 Volume", NULL, "DAC R2 Mux" },
2477 { "DAC R2 Volume", NULL, "dac mono right filter" },
2478
2479 { "Stereo DAC MIXL", "DAC L1 Switch", "DAC1 MIXL" },
2480 { "Stereo DAC MIXL", "DAC R1 Switch", "DAC1 MIXR" },
2481 { "Stereo DAC MIXL", "DAC L2 Switch", "DAC L2 Volume" },
2482 { "Stereo DAC MIXL", NULL, "dac stereo1 filter" },
2483 { "Stereo DAC MIXR", "DAC R1 Switch", "DAC1 MIXR" },
2484 { "Stereo DAC MIXR", "DAC L1 Switch", "DAC1 MIXL" },
2485 { "Stereo DAC MIXR", "DAC R2 Switch", "DAC R2 Volume" },
2486 { "Stereo DAC MIXR", NULL, "dac stereo1 filter" },
2487
2488 { "Mono DAC MIXL", "DAC L1 Switch", "DAC1 MIXL" },
2489 { "Mono DAC MIXL", "DAC L2 Switch", "DAC L2 Volume" },
2490 { "Mono DAC MIXL", "DAC R2 Switch", "DAC R2 Volume" },
2491 { "Mono DAC MIXL", NULL, "dac mono left filter" },
2492 { "Mono DAC MIXR", "DAC R1 Switch", "DAC1 MIXR" },
2493 { "Mono DAC MIXR", "DAC R2 Switch", "DAC R2 Volume" },
2494 { "Mono DAC MIXR", "DAC L2 Switch", "DAC L2 Volume" },
2495 { "Mono DAC MIXR", NULL, "dac mono right filter" },
2496
2497 { "DAC MIXL", "Sto DAC Mix L Switch", "Stereo DAC MIXL" },
2498 { "DAC MIXL", "DAC L2 Switch", "DAC L2 Volume" },
2499 { "DAC MIXL", "DAC R2 Switch", "DAC R2 Volume" },
2500 { "DAC MIXR", "Sto DAC Mix R Switch", "Stereo DAC MIXR" },
2501 { "DAC MIXR", "DAC R2 Switch", "DAC R2 Volume" },
2502 { "DAC MIXR", "DAC L2 Switch", "DAC L2 Volume" },
2503
2504 { "DAC L1", NULL, "PLL1", is_sys_clk_from_pll },
2505 { "DAC R1", NULL, "PLL1", is_sys_clk_from_pll },
2506 { "DAC L2", NULL, "PLL1", is_sys_clk_from_pll },
2507 { "DAC R2", NULL, "PLL1", is_sys_clk_from_pll },
2508
2509 { "SPK MIXL", "BST1 Switch", "BST1" },
2510 { "SPK MIXL", "INL Switch", "INL VOL" },
2511 { "SPK MIXL", "DAC L1 Switch", "DAC L1" },
2512 { "SPK MIXL", "DAC L2 Switch", "DAC L2" },
2513 { "SPK MIXR", "BST2 Switch", "BST2" },
2514 { "SPK MIXR", "INR Switch", "INR VOL" },
2515 { "SPK MIXR", "DAC R1 Switch", "DAC R1" },
2516 { "SPK MIXR", "DAC R2 Switch", "DAC R2" },
2517
2518 { "OUT MIXL", "BST1 Switch", "BST1" },
2519 { "OUT MIXL", "INL Switch", "INL VOL" },
2520 { "OUT MIXL", "DAC L2 Switch", "DAC L2" },
2521 { "OUT MIXL", "DAC L1 Switch", "DAC L1" },
2522
2523 { "OUT MIXR", "BST2 Switch", "BST2" },
2524 { "OUT MIXR", "INR Switch", "INR VOL" },
2525 { "OUT MIXR", "DAC R2 Switch", "DAC R2" },
2526 { "OUT MIXR", "DAC R1 Switch", "DAC R1" },
2527
2528 { "HPOVOL MIXL", "DAC1 Switch", "DAC L1" },
2529 { "HPOVOL MIXL", "DAC2 Switch", "DAC L2" },
2530 { "HPOVOL MIXL", "INL Switch", "INL VOL" },
2531 { "HPOVOL MIXL", "BST1 Switch", "BST1" },
2532 { "HPOVOL MIXL", NULL, "HPOVOL MIXL Power" },
2533 { "HPOVOL MIXR", "DAC1 Switch", "DAC R1" },
2534 { "HPOVOL MIXR", "DAC2 Switch", "DAC R2" },
2535 { "HPOVOL MIXR", "INR Switch", "INR VOL" },
2536 { "HPOVOL MIXR", "BST2 Switch", "BST2" },
2537 { "HPOVOL MIXR", NULL, "HPOVOL MIXR Power" },
2538
2539 { "DAC 2", NULL, "DAC L2" },
2540 { "DAC 2", NULL, "DAC R2" },
2541 { "DAC 1", NULL, "DAC L1" },
2542 { "DAC 1", NULL, "DAC R1" },
2543 { "HPOVOL L", "Switch", "HPOVOL MIXL" },
2544 { "HPOVOL R", "Switch", "HPOVOL MIXR" },
2545 { "HPOVOL", NULL, "HPOVOL L" },
2546 { "HPOVOL", NULL, "HPOVOL R" },
2547 { "HPO MIX", "DAC1 Switch", "DAC 1" },
2548 { "HPO MIX", "HPVOL Switch", "HPOVOL" },
2549
2550 { "SPKVOL L", "Switch", "SPK MIXL" },
2551 { "SPKVOL R", "Switch", "SPK MIXR" },
2552
2553 { "SPOL MIX", "DAC L1 Switch", "DAC L1" },
2554 { "SPOL MIX", "SPKVOL L Switch", "SPKVOL L" },
2555 { "SPOR MIX", "DAC R1 Switch", "DAC R1" },
2556 { "SPOR MIX", "SPKVOL R Switch", "SPKVOL R" },
2557
2558 { "LOUT MIX", "DAC L1 Switch", "DAC L1" },
2559 { "LOUT MIX", "DAC R1 Switch", "DAC R1" },
2560 { "LOUT MIX", "OUTMIX L Switch", "OUT MIXL" },
2561 { "LOUT MIX", "OUTMIX R Switch", "OUT MIXR" },
2562
2563 { "PDM1 L Mux", "Stereo DAC", "Stereo DAC MIXL" },
2564 { "PDM1 L Mux", "Mono DAC", "Mono DAC MIXL" },
2565 { "PDM1 L Mux", NULL, "PDM1 Power" },
2566 { "PDM1 R Mux", "Stereo DAC", "Stereo DAC MIXR" },
2567 { "PDM1 R Mux", "Mono DAC", "Mono DAC MIXR" },
2568 { "PDM1 R Mux", NULL, "PDM1 Power" },
2569
2570 { "HP amp", NULL, "HPO MIX" },
2571 { "HP amp", NULL, "JD Power" },
2572 { "HP amp", NULL, "Mic Det Power" },
2573 { "HP amp", NULL, "LDO2" },
2574 { "HPOL", NULL, "HP amp" },
2575 { "HPOR", NULL, "HP amp" },
2576
2577 { "LOUT amp", NULL, "LOUT MIX" },
2578 { "LOUTL", NULL, "LOUT amp" },
2579 { "LOUTR", NULL, "LOUT amp" },
2580
2581 { "PDM1 L", "Switch", "PDM1 L Mux" },
2582 { "PDM1 R", "Switch", "PDM1 R Mux" },
2583
2584 { "PDM1L", NULL, "PDM1 L" },
2585 { "PDM1R", NULL, "PDM1 R" },
2586
2587 { "SPK amp", NULL, "SPOL MIX" },
2588 { "SPK amp", NULL, "SPOR MIX" },
2589 { "SPOL", NULL, "SPK amp" },
2590 { "SPOR", NULL, "SPK amp" },
2591 };
2592
2593 static const struct snd_soc_dapm_route rt5650_specific_dapm_routes[] = {
2594 { "A DAC1 L Mux", "DAC1", "DAC1 MIXL"},
2595 { "A DAC1 L Mux", "Stereo DAC Mixer", "Stereo DAC MIXL"},
2596 { "A DAC1 R Mux", "DAC1", "DAC1 MIXR"},
2597 { "A DAC1 R Mux", "Stereo DAC Mixer", "Stereo DAC MIXR"},
2598
2599 { "A DAC2 L Mux", "Stereo DAC Mixer", "Stereo DAC MIXL"},
2600 { "A DAC2 L Mux", "Mono DAC Mixer", "Mono DAC MIXL"},
2601 { "A DAC2 R Mux", "Stereo DAC Mixer", "Stereo DAC MIXR"},
2602 { "A DAC2 R Mux", "Mono DAC Mixer", "Mono DAC MIXR"},
2603
2604 { "DAC L1", NULL, "A DAC1 L Mux" },
2605 { "DAC R1", NULL, "A DAC1 R Mux" },
2606 { "DAC L2", NULL, "A DAC2 L Mux" },
2607 { "DAC R2", NULL, "A DAC2 R Mux" },
2608
2609 { "RT5650 IF1 ADC1 Swap Mux", "L/R", "IF_ADC1" },
2610 { "RT5650 IF1 ADC1 Swap Mux", "R/L", "IF_ADC1" },
2611 { "RT5650 IF1 ADC1 Swap Mux", "L/L", "IF_ADC1" },
2612 { "RT5650 IF1 ADC1 Swap Mux", "R/R", "IF_ADC1" },
2613
2614 { "RT5650 IF1 ADC2 Swap Mux", "L/R", "IF_ADC2" },
2615 { "RT5650 IF1 ADC2 Swap Mux", "R/L", "IF_ADC2" },
2616 { "RT5650 IF1 ADC2 Swap Mux", "L/L", "IF_ADC2" },
2617 { "RT5650 IF1 ADC2 Swap Mux", "R/R", "IF_ADC2" },
2618
2619 { "RT5650 IF1 ADC3 Swap Mux", "L/R", "VAD_ADC" },
2620 { "RT5650 IF1 ADC3 Swap Mux", "R/L", "VAD_ADC" },
2621 { "RT5650 IF1 ADC3 Swap Mux", "L/L", "VAD_ADC" },
2622 { "RT5650 IF1 ADC3 Swap Mux", "R/R", "VAD_ADC" },
2623
2624 { "IF1 ADC", NULL, "RT5650 IF1 ADC1 Swap Mux" },
2625 { "IF1 ADC", NULL, "RT5650 IF1 ADC2 Swap Mux" },
2626 { "IF1 ADC", NULL, "RT5650 IF1 ADC3 Swap Mux" },
2627
2628 { "RT5650 IF1 ADC Mux", "IF_ADC1/IF_ADC2/DAC_REF/Null", "IF1 ADC" },
2629 { "RT5650 IF1 ADC Mux", "IF_ADC1/IF_ADC2/Null/DAC_REF", "IF1 ADC" },
2630 { "RT5650 IF1 ADC Mux", "IF_ADC1/DAC_REF/IF_ADC2/Null", "IF1 ADC" },
2631 { "RT5650 IF1 ADC Mux", "IF_ADC1/DAC_REF/Null/IF_ADC2", "IF1 ADC" },
2632 { "RT5650 IF1 ADC Mux", "IF_ADC1/Null/DAC_REF/IF_ADC2", "IF1 ADC" },
2633 { "RT5650 IF1 ADC Mux", "IF_ADC1/Null/IF_ADC2/DAC_REF", "IF1 ADC" },
2634
2635 { "RT5650 IF1 ADC Mux", "IF_ADC2/IF_ADC1/DAC_REF/Null", "IF1 ADC" },
2636 { "RT5650 IF1 ADC Mux", "IF_ADC2/IF_ADC1/Null/DAC_REF", "IF1 ADC" },
2637 { "RT5650 IF1 ADC Mux", "IF_ADC2/DAC_REF/IF_ADC1/Null", "IF1 ADC" },
2638 { "RT5650 IF1 ADC Mux", "IF_ADC2/DAC_REF/Null/IF_ADC1", "IF1 ADC" },
2639 { "RT5650 IF1 ADC Mux", "IF_ADC2/Null/DAC_REF/IF_ADC1", "IF1 ADC" },
2640 { "RT5650 IF1 ADC Mux", "IF_ADC2/Null/IF_ADC1/DAC_REF", "IF1 ADC" },
2641
2642 { "RT5650 IF1 ADC Mux", "DAC_REF/IF_ADC1/IF_ADC2/Null", "IF1 ADC" },
2643 { "RT5650 IF1 ADC Mux", "DAC_REF/IF_ADC1/Null/IF_ADC2", "IF1 ADC" },
2644 { "RT5650 IF1 ADC Mux", "DAC_REF/IF_ADC2/IF_ADC1/Null", "IF1 ADC" },
2645 { "RT5650 IF1 ADC Mux", "DAC_REF/IF_ADC2/Null/IF_ADC1", "IF1 ADC" },
2646 { "RT5650 IF1 ADC Mux", "DAC_REF/Null/IF_ADC1/IF_ADC2", "IF1 ADC" },
2647 { "RT5650 IF1 ADC Mux", "DAC_REF/Null/IF_ADC2/IF_ADC1", "IF1 ADC" },
2648
2649 { "RT5650 IF1 ADC Mux", "Null/IF_ADC1/IF_ADC2/DAC_REF", "IF1 ADC" },
2650 { "RT5650 IF1 ADC Mux", "Null/IF_ADC1/DAC_REF/IF_ADC2", "IF1 ADC" },
2651 { "RT5650 IF1 ADC Mux", "Null/IF_ADC2/IF_ADC1/DAC_REF", "IF1 ADC" },
2652 { "RT5650 IF1 ADC Mux", "Null/IF_ADC2/DAC_REF/IF_ADC1", "IF1 ADC" },
2653 { "RT5650 IF1 ADC Mux", "Null/DAC_REF/IF_ADC1/IF_ADC2", "IF1 ADC" },
2654 { "RT5650 IF1 ADC Mux", "Null/DAC_REF/IF_ADC2/IF_ADC1", "IF1 ADC" },
2655 { "AIF1TX", NULL, "RT5650 IF1 ADC Mux" },
2656
2657 { "RT5650 IF1 DAC1 L Mux", "Slot0", "IF1 DAC0" },
2658 { "RT5650 IF1 DAC1 L Mux", "Slot1", "IF1 DAC1" },
2659 { "RT5650 IF1 DAC1 L Mux", "Slot2", "IF1 DAC2" },
2660 { "RT5650 IF1 DAC1 L Mux", "Slot3", "IF1 DAC3" },
2661
2662 { "RT5650 IF1 DAC1 R Mux", "Slot0", "IF1 DAC0" },
2663 { "RT5650 IF1 DAC1 R Mux", "Slot1", "IF1 DAC1" },
2664 { "RT5650 IF1 DAC1 R Mux", "Slot2", "IF1 DAC2" },
2665 { "RT5650 IF1 DAC1 R Mux", "Slot3", "IF1 DAC3" },
2666
2667 { "RT5650 IF1 DAC2 L Mux", "Slot0", "IF1 DAC0" },
2668 { "RT5650 IF1 DAC2 L Mux", "Slot1", "IF1 DAC1" },
2669 { "RT5650 IF1 DAC2 L Mux", "Slot2", "IF1 DAC2" },
2670 { "RT5650 IF1 DAC2 L Mux", "Slot3", "IF1 DAC3" },
2671
2672 { "RT5650 IF1 DAC2 R Mux", "Slot0", "IF1 DAC0" },
2673 { "RT5650 IF1 DAC2 R Mux", "Slot1", "IF1 DAC1" },
2674 { "RT5650 IF1 DAC2 R Mux", "Slot2", "IF1 DAC2" },
2675 { "RT5650 IF1 DAC2 R Mux", "Slot3", "IF1 DAC3" },
2676
2677 { "DAC1 L Mux", "IF1 DAC", "RT5650 IF1 DAC1 L Mux" },
2678 { "DAC1 R Mux", "IF1 DAC", "RT5650 IF1 DAC1 R Mux" },
2679
2680 { "DAC L2 Mux", "IF1 DAC", "RT5650 IF1 DAC2 L Mux" },
2681 { "DAC R2 Mux", "IF1 DAC", "RT5650 IF1 DAC2 R Mux" },
2682 };
2683
2684 static const struct snd_soc_dapm_route rt5645_specific_dapm_routes[] = {
2685 { "DAC L1", NULL, "Stereo DAC MIXL" },
2686 { "DAC R1", NULL, "Stereo DAC MIXR" },
2687 { "DAC L2", NULL, "Mono DAC MIXL" },
2688 { "DAC R2", NULL, "Mono DAC MIXR" },
2689
2690 { "RT5645 IF1 ADC1 Swap Mux", "L/R", "IF_ADC1" },
2691 { "RT5645 IF1 ADC1 Swap Mux", "R/L", "IF_ADC1" },
2692 { "RT5645 IF1 ADC1 Swap Mux", "L/L", "IF_ADC1" },
2693 { "RT5645 IF1 ADC1 Swap Mux", "R/R", "IF_ADC1" },
2694
2695 { "RT5645 IF1 ADC2 Swap Mux", "L/R", "IF_ADC2" },
2696 { "RT5645 IF1 ADC2 Swap Mux", "R/L", "IF_ADC2" },
2697 { "RT5645 IF1 ADC2 Swap Mux", "L/L", "IF_ADC2" },
2698 { "RT5645 IF1 ADC2 Swap Mux", "R/R", "IF_ADC2" },
2699
2700 { "RT5645 IF1 ADC3 Swap Mux", "L/R", "VAD_ADC" },
2701 { "RT5645 IF1 ADC3 Swap Mux", "R/L", "VAD_ADC" },
2702 { "RT5645 IF1 ADC3 Swap Mux", "L/L", "VAD_ADC" },
2703 { "RT5645 IF1 ADC3 Swap Mux", "R/R", "VAD_ADC" },
2704
2705 { "IF1 ADC", NULL, "RT5645 IF1 ADC1 Swap Mux" },
2706 { "IF1 ADC", NULL, "RT5645 IF1 ADC2 Swap Mux" },
2707 { "IF1 ADC", NULL, "RT5645 IF1 ADC3 Swap Mux" },
2708
2709 { "RT5645 IF1 ADC Mux", "IF_ADC1/IF_ADC2/VAD_ADC", "IF1 ADC" },
2710 { "RT5645 IF1 ADC Mux", "IF_ADC2/IF_ADC1/VAD_ADC", "IF1 ADC" },
2711 { "RT5645 IF1 ADC Mux", "VAD_ADC/IF_ADC1/IF_ADC2", "IF1 ADC" },
2712 { "RT5645 IF1 ADC Mux", "VAD_ADC/IF_ADC2/IF_ADC1", "IF1 ADC" },
2713 { "AIF1TX", NULL, "RT5645 IF1 ADC Mux" },
2714
2715 { "RT5645 IF1 DAC1 L Mux", "Slot0", "IF1 DAC0" },
2716 { "RT5645 IF1 DAC1 L Mux", "Slot1", "IF1 DAC1" },
2717 { "RT5645 IF1 DAC1 L Mux", "Slot2", "IF1 DAC2" },
2718 { "RT5645 IF1 DAC1 L Mux", "Slot3", "IF1 DAC3" },
2719
2720 { "RT5645 IF1 DAC1 R Mux", "Slot0", "IF1 DAC0" },
2721 { "RT5645 IF1 DAC1 R Mux", "Slot1", "IF1 DAC1" },
2722 { "RT5645 IF1 DAC1 R Mux", "Slot2", "IF1 DAC2" },
2723 { "RT5645 IF1 DAC1 R Mux", "Slot3", "IF1 DAC3" },
2724
2725 { "RT5645 IF1 DAC2 L Mux", "Slot0", "IF1 DAC0" },
2726 { "RT5645 IF1 DAC2 L Mux", "Slot1", "IF1 DAC1" },
2727 { "RT5645 IF1 DAC2 L Mux", "Slot2", "IF1 DAC2" },
2728 { "RT5645 IF1 DAC2 L Mux", "Slot3", "IF1 DAC3" },
2729
2730 { "RT5645 IF1 DAC2 R Mux", "Slot0", "IF1 DAC0" },
2731 { "RT5645 IF1 DAC2 R Mux", "Slot1", "IF1 DAC1" },
2732 { "RT5645 IF1 DAC2 R Mux", "Slot2", "IF1 DAC2" },
2733 { "RT5645 IF1 DAC2 R Mux", "Slot3", "IF1 DAC3" },
2734
2735 { "DAC1 L Mux", "IF1 DAC", "RT5645 IF1 DAC1 L Mux" },
2736 { "DAC1 R Mux", "IF1 DAC", "RT5645 IF1 DAC1 R Mux" },
2737
2738 { "DAC L2 Mux", "IF1 DAC", "RT5645 IF1 DAC2 L Mux" },
2739 { "DAC R2 Mux", "IF1 DAC", "RT5645 IF1 DAC2 R Mux" },
2740 };
2741
2742 static const struct snd_soc_dapm_route rt5645_old_dapm_routes[] = {
2743 { "SPOL MIX", "DAC R1 Switch", "DAC R1" },
2744 { "SPOL MIX", "SPKVOL R Switch", "SPKVOL R" },
2745 };
2746
rt5645_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)2747 static int rt5645_hw_params(struct snd_pcm_substream *substream,
2748 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
2749 {
2750 struct snd_soc_component *component = dai->component;
2751 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
2752 unsigned int val_len = 0, val_clk, mask_clk, dl_sft;
2753 int pre_div, bclk_ms, frame_size;
2754
2755 rt5645->lrck[dai->id] = params_rate(params);
2756 pre_div = rl6231_get_clk_info(rt5645->sysclk, rt5645->lrck[dai->id]);
2757 if (pre_div < 0) {
2758 dev_err(component->dev, "Unsupported clock setting\n");
2759 return -EINVAL;
2760 }
2761 frame_size = snd_soc_params_to_frame_size(params);
2762 if (frame_size < 0) {
2763 dev_err(component->dev, "Unsupported frame size: %d\n", frame_size);
2764 return -EINVAL;
2765 }
2766
2767 switch (rt5645->codec_type) {
2768 case CODEC_TYPE_RT5650:
2769 dl_sft = 4;
2770 break;
2771 default:
2772 dl_sft = 2;
2773 break;
2774 }
2775
2776 bclk_ms = frame_size > 32;
2777 rt5645->bclk[dai->id] = rt5645->lrck[dai->id] * (32 << bclk_ms);
2778
2779 dev_dbg(dai->dev, "bclk is %dHz and lrck is %dHz\n",
2780 rt5645->bclk[dai->id], rt5645->lrck[dai->id]);
2781 dev_dbg(dai->dev, "bclk_ms is %d and pre_div is %d for iis %d\n",
2782 bclk_ms, pre_div, dai->id);
2783
2784 switch (params_width(params)) {
2785 case 16:
2786 break;
2787 case 20:
2788 val_len = 0x1;
2789 break;
2790 case 24:
2791 val_len = 0x2;
2792 break;
2793 case 8:
2794 val_len = 0x3;
2795 break;
2796 default:
2797 return -EINVAL;
2798 }
2799
2800 switch (dai->id) {
2801 case RT5645_AIF1:
2802 mask_clk = RT5645_I2S_PD1_MASK;
2803 val_clk = pre_div << RT5645_I2S_PD1_SFT;
2804 snd_soc_component_update_bits(component, RT5645_I2S1_SDP,
2805 (0x3 << dl_sft), (val_len << dl_sft));
2806 snd_soc_component_update_bits(component, RT5645_ADDA_CLK1, mask_clk, val_clk);
2807 break;
2808 case RT5645_AIF2:
2809 mask_clk = RT5645_I2S_BCLK_MS2_MASK | RT5645_I2S_PD2_MASK;
2810 val_clk = bclk_ms << RT5645_I2S_BCLK_MS2_SFT |
2811 pre_div << RT5645_I2S_PD2_SFT;
2812 snd_soc_component_update_bits(component, RT5645_I2S2_SDP,
2813 (0x3 << dl_sft), (val_len << dl_sft));
2814 snd_soc_component_update_bits(component, RT5645_ADDA_CLK1, mask_clk, val_clk);
2815 break;
2816 default:
2817 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
2818 return -EINVAL;
2819 }
2820
2821 return 0;
2822 }
2823
rt5645_set_dai_fmt(struct snd_soc_dai * dai,unsigned int fmt)2824 static int rt5645_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2825 {
2826 struct snd_soc_component *component = dai->component;
2827 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
2828 unsigned int reg_val = 0, pol_sft;
2829
2830 switch (rt5645->codec_type) {
2831 case CODEC_TYPE_RT5650:
2832 pol_sft = 8;
2833 break;
2834 default:
2835 pol_sft = 7;
2836 break;
2837 }
2838
2839 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2840 case SND_SOC_DAIFMT_CBM_CFM:
2841 rt5645->master[dai->id] = 1;
2842 break;
2843 case SND_SOC_DAIFMT_CBS_CFS:
2844 reg_val |= RT5645_I2S_MS_S;
2845 rt5645->master[dai->id] = 0;
2846 break;
2847 default:
2848 return -EINVAL;
2849 }
2850
2851 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2852 case SND_SOC_DAIFMT_NB_NF:
2853 break;
2854 case SND_SOC_DAIFMT_IB_NF:
2855 reg_val |= (1 << pol_sft);
2856 break;
2857 default:
2858 return -EINVAL;
2859 }
2860
2861 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2862 case SND_SOC_DAIFMT_I2S:
2863 break;
2864 case SND_SOC_DAIFMT_LEFT_J:
2865 reg_val |= RT5645_I2S_DF_LEFT;
2866 break;
2867 case SND_SOC_DAIFMT_DSP_A:
2868 reg_val |= RT5645_I2S_DF_PCM_A;
2869 break;
2870 case SND_SOC_DAIFMT_DSP_B:
2871 reg_val |= RT5645_I2S_DF_PCM_B;
2872 break;
2873 default:
2874 return -EINVAL;
2875 }
2876 switch (dai->id) {
2877 case RT5645_AIF1:
2878 snd_soc_component_update_bits(component, RT5645_I2S1_SDP,
2879 RT5645_I2S_MS_MASK | (1 << pol_sft) |
2880 RT5645_I2S_DF_MASK, reg_val);
2881 break;
2882 case RT5645_AIF2:
2883 snd_soc_component_update_bits(component, RT5645_I2S2_SDP,
2884 RT5645_I2S_MS_MASK | (1 << pol_sft) |
2885 RT5645_I2S_DF_MASK, reg_val);
2886 break;
2887 default:
2888 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
2889 return -EINVAL;
2890 }
2891 return 0;
2892 }
2893
rt5645_set_dai_sysclk(struct snd_soc_dai * dai,int clk_id,unsigned int freq,int dir)2894 static int rt5645_set_dai_sysclk(struct snd_soc_dai *dai,
2895 int clk_id, unsigned int freq, int dir)
2896 {
2897 struct snd_soc_component *component = dai->component;
2898 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
2899 unsigned int reg_val = 0;
2900
2901 if (freq == rt5645->sysclk && clk_id == rt5645->sysclk_src)
2902 return 0;
2903
2904 switch (clk_id) {
2905 case RT5645_SCLK_S_MCLK:
2906 reg_val |= RT5645_SCLK_SRC_MCLK;
2907 break;
2908 case RT5645_SCLK_S_PLL1:
2909 reg_val |= RT5645_SCLK_SRC_PLL1;
2910 break;
2911 case RT5645_SCLK_S_RCCLK:
2912 reg_val |= RT5645_SCLK_SRC_RCCLK;
2913 break;
2914 default:
2915 dev_err(component->dev, "Invalid clock id (%d)\n", clk_id);
2916 return -EINVAL;
2917 }
2918 snd_soc_component_update_bits(component, RT5645_GLB_CLK,
2919 RT5645_SCLK_SRC_MASK, reg_val);
2920 rt5645->sysclk = freq;
2921 rt5645->sysclk_src = clk_id;
2922
2923 dev_dbg(dai->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id);
2924
2925 return 0;
2926 }
2927
rt5645_set_dai_pll(struct snd_soc_dai * dai,int pll_id,int source,unsigned int freq_in,unsigned int freq_out)2928 static int rt5645_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
2929 unsigned int freq_in, unsigned int freq_out)
2930 {
2931 struct snd_soc_component *component = dai->component;
2932 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
2933 struct rl6231_pll_code pll_code;
2934 int ret;
2935
2936 if (source == rt5645->pll_src && freq_in == rt5645->pll_in &&
2937 freq_out == rt5645->pll_out)
2938 return 0;
2939
2940 if (!freq_in || !freq_out) {
2941 dev_dbg(component->dev, "PLL disabled\n");
2942
2943 rt5645->pll_in = 0;
2944 rt5645->pll_out = 0;
2945 snd_soc_component_update_bits(component, RT5645_GLB_CLK,
2946 RT5645_SCLK_SRC_MASK, RT5645_SCLK_SRC_MCLK);
2947 return 0;
2948 }
2949
2950 switch (source) {
2951 case RT5645_PLL1_S_MCLK:
2952 snd_soc_component_update_bits(component, RT5645_GLB_CLK,
2953 RT5645_PLL1_SRC_MASK, RT5645_PLL1_SRC_MCLK);
2954 break;
2955 case RT5645_PLL1_S_BCLK1:
2956 case RT5645_PLL1_S_BCLK2:
2957 switch (dai->id) {
2958 case RT5645_AIF1:
2959 snd_soc_component_update_bits(component, RT5645_GLB_CLK,
2960 RT5645_PLL1_SRC_MASK, RT5645_PLL1_SRC_BCLK1);
2961 break;
2962 case RT5645_AIF2:
2963 snd_soc_component_update_bits(component, RT5645_GLB_CLK,
2964 RT5645_PLL1_SRC_MASK, RT5645_PLL1_SRC_BCLK2);
2965 break;
2966 default:
2967 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
2968 return -EINVAL;
2969 }
2970 break;
2971 default:
2972 dev_err(component->dev, "Unknown PLL source %d\n", source);
2973 return -EINVAL;
2974 }
2975
2976 ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
2977 if (ret < 0) {
2978 dev_err(component->dev, "Unsupported input clock %d\n", freq_in);
2979 return ret;
2980 }
2981
2982 dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n",
2983 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
2984 pll_code.n_code, pll_code.k_code);
2985
2986 snd_soc_component_write(component, RT5645_PLL_CTRL1,
2987 pll_code.n_code << RT5645_PLL_N_SFT | pll_code.k_code);
2988 snd_soc_component_write(component, RT5645_PLL_CTRL2,
2989 ((pll_code.m_bp ? 0 : pll_code.m_code) << RT5645_PLL_M_SFT) |
2990 (pll_code.m_bp << RT5645_PLL_M_BP_SFT));
2991
2992 rt5645->pll_in = freq_in;
2993 rt5645->pll_out = freq_out;
2994 rt5645->pll_src = source;
2995
2996 return 0;
2997 }
2998
rt5645_set_tdm_slot(struct snd_soc_dai * dai,unsigned int tx_mask,unsigned int rx_mask,int slots,int slot_width)2999 static int rt5645_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
3000 unsigned int rx_mask, int slots, int slot_width)
3001 {
3002 struct snd_soc_component *component = dai->component;
3003 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
3004 unsigned int i_slot_sft, o_slot_sft, i_width_sht, o_width_sht, en_sft;
3005 unsigned int mask, val = 0;
3006
3007 switch (rt5645->codec_type) {
3008 case CODEC_TYPE_RT5650:
3009 en_sft = 15;
3010 i_slot_sft = 10;
3011 o_slot_sft = 8;
3012 i_width_sht = 6;
3013 o_width_sht = 4;
3014 mask = 0x8ff0;
3015 break;
3016 default:
3017 en_sft = 14;
3018 i_slot_sft = o_slot_sft = 12;
3019 i_width_sht = o_width_sht = 10;
3020 mask = 0x7c00;
3021 break;
3022 }
3023 if (rx_mask || tx_mask) {
3024 val |= (1 << en_sft);
3025 if (rt5645->codec_type == CODEC_TYPE_RT5645)
3026 snd_soc_component_update_bits(component, RT5645_BASS_BACK,
3027 RT5645_G_BB_BST_MASK, RT5645_G_BB_BST_25DB);
3028 }
3029
3030 switch (slots) {
3031 case 4:
3032 val |= (1 << i_slot_sft) | (1 << o_slot_sft);
3033 break;
3034 case 6:
3035 val |= (2 << i_slot_sft) | (2 << o_slot_sft);
3036 break;
3037 case 8:
3038 val |= (3 << i_slot_sft) | (3 << o_slot_sft);
3039 break;
3040 case 2:
3041 default:
3042 break;
3043 }
3044
3045 switch (slot_width) {
3046 case 20:
3047 val |= (1 << i_width_sht) | (1 << o_width_sht);
3048 break;
3049 case 24:
3050 val |= (2 << i_width_sht) | (2 << o_width_sht);
3051 break;
3052 case 32:
3053 val |= (3 << i_width_sht) | (3 << o_width_sht);
3054 break;
3055 case 16:
3056 default:
3057 break;
3058 }
3059
3060 snd_soc_component_update_bits(component, RT5645_TDM_CTRL_1, mask, val);
3061
3062 return 0;
3063 }
3064
rt5645_set_bias_level(struct snd_soc_component * component,enum snd_soc_bias_level level)3065 static int rt5645_set_bias_level(struct snd_soc_component *component,
3066 enum snd_soc_bias_level level)
3067 {
3068 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
3069
3070 switch (level) {
3071 case SND_SOC_BIAS_PREPARE:
3072 if (SND_SOC_BIAS_STANDBY == snd_soc_component_get_bias_level(component)) {
3073 snd_soc_component_update_bits(component, RT5645_PWR_ANLG1,
3074 RT5645_PWR_VREF1 | RT5645_PWR_MB |
3075 RT5645_PWR_BG | RT5645_PWR_VREF2,
3076 RT5645_PWR_VREF1 | RT5645_PWR_MB |
3077 RT5645_PWR_BG | RT5645_PWR_VREF2);
3078 mdelay(10);
3079 snd_soc_component_update_bits(component, RT5645_PWR_ANLG1,
3080 RT5645_PWR_FV1 | RT5645_PWR_FV2,
3081 RT5645_PWR_FV1 | RT5645_PWR_FV2);
3082 snd_soc_component_update_bits(component, RT5645_GEN_CTRL1,
3083 RT5645_DIG_GATE_CTRL, RT5645_DIG_GATE_CTRL);
3084 }
3085 break;
3086
3087 case SND_SOC_BIAS_STANDBY:
3088 snd_soc_component_update_bits(component, RT5645_PWR_ANLG1,
3089 RT5645_PWR_VREF1 | RT5645_PWR_MB |
3090 RT5645_PWR_BG | RT5645_PWR_VREF2,
3091 RT5645_PWR_VREF1 | RT5645_PWR_MB |
3092 RT5645_PWR_BG | RT5645_PWR_VREF2);
3093 mdelay(10);
3094 snd_soc_component_update_bits(component, RT5645_PWR_ANLG1,
3095 RT5645_PWR_FV1 | RT5645_PWR_FV2,
3096 RT5645_PWR_FV1 | RT5645_PWR_FV2);
3097 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
3098 snd_soc_component_write(component, RT5645_DEPOP_M2, 0x1140);
3099 msleep(40);
3100 if (rt5645->en_button_func)
3101 queue_delayed_work(system_power_efficient_wq,
3102 &rt5645->jack_detect_work,
3103 msecs_to_jiffies(0));
3104 }
3105 break;
3106
3107 case SND_SOC_BIAS_OFF:
3108 snd_soc_component_write(component, RT5645_DEPOP_M2, 0x1100);
3109 if (!rt5645->en_button_func)
3110 snd_soc_component_update_bits(component, RT5645_GEN_CTRL1,
3111 RT5645_DIG_GATE_CTRL, 0);
3112 snd_soc_component_update_bits(component, RT5645_PWR_ANLG1,
3113 RT5645_PWR_VREF1 | RT5645_PWR_MB |
3114 RT5645_PWR_BG | RT5645_PWR_VREF2 |
3115 RT5645_PWR_FV1 | RT5645_PWR_FV2, 0x0);
3116 break;
3117
3118 default:
3119 break;
3120 }
3121
3122 return 0;
3123 }
3124
rt5645_enable_push_button_irq(struct snd_soc_component * component,bool enable)3125 static void rt5645_enable_push_button_irq(struct snd_soc_component *component,
3126 bool enable)
3127 {
3128 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
3129
3130 if (enable) {
3131 snd_soc_dapm_force_enable_pin(dapm, "ADC L power");
3132 snd_soc_dapm_force_enable_pin(dapm, "ADC R power");
3133 snd_soc_dapm_sync(dapm);
3134
3135 snd_soc_component_update_bits(component, RT5650_4BTN_IL_CMD1, 0x3, 0x3);
3136 snd_soc_component_update_bits(component,
3137 RT5645_INT_IRQ_ST, 0x8, 0x8);
3138 snd_soc_component_update_bits(component,
3139 RT5650_4BTN_IL_CMD2, 0x8000, 0x8000);
3140 snd_soc_component_read(component, RT5650_4BTN_IL_CMD1);
3141 pr_debug("%s read %x = %x\n", __func__, RT5650_4BTN_IL_CMD1,
3142 snd_soc_component_read(component, RT5650_4BTN_IL_CMD1));
3143 } else {
3144 snd_soc_component_update_bits(component, RT5650_4BTN_IL_CMD2, 0x8000, 0x0);
3145 snd_soc_component_update_bits(component, RT5645_INT_IRQ_ST, 0x8, 0x0);
3146
3147 snd_soc_dapm_disable_pin(dapm, "ADC L power");
3148 snd_soc_dapm_disable_pin(dapm, "ADC R power");
3149 snd_soc_dapm_sync(dapm);
3150 }
3151 }
3152
rt5645_jack_detect(struct snd_soc_component * component,int jack_insert)3153 static int rt5645_jack_detect(struct snd_soc_component *component, int jack_insert)
3154 {
3155 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
3156 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
3157 unsigned int val;
3158
3159 if (jack_insert) {
3160 regmap_write(rt5645->regmap, RT5645_CHARGE_PUMP, 0x0206);
3161
3162 /* for jack type detect */
3163 snd_soc_dapm_force_enable_pin(dapm, "LDO2");
3164 snd_soc_dapm_force_enable_pin(dapm, "Mic Det Power");
3165 snd_soc_dapm_sync(dapm);
3166 if (!snd_soc_card_is_instantiated(dapm->card)) {
3167 /* Power up necessary bits for JD if dapm is
3168 not ready yet */
3169 regmap_update_bits(rt5645->regmap, RT5645_PWR_ANLG1,
3170 RT5645_PWR_MB | RT5645_PWR_VREF2,
3171 RT5645_PWR_MB | RT5645_PWR_VREF2);
3172 regmap_update_bits(rt5645->regmap, RT5645_PWR_MIXER,
3173 RT5645_PWR_LDO2, RT5645_PWR_LDO2);
3174 regmap_update_bits(rt5645->regmap, RT5645_PWR_VOL,
3175 RT5645_PWR_MIC_DET, RT5645_PWR_MIC_DET);
3176 }
3177
3178 regmap_write(rt5645->regmap, RT5645_JD_CTRL3, 0x00f0);
3179 regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL2,
3180 RT5645_CBJ_MN_JD, RT5645_CBJ_MN_JD);
3181 regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL1,
3182 RT5645_CBJ_BST1_EN, RT5645_CBJ_BST1_EN);
3183 msleep(100);
3184 regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL2,
3185 RT5645_CBJ_MN_JD, 0);
3186
3187 if (rt5645->gpiod_cbj_sleeve)
3188 gpiod_set_value(rt5645->gpiod_cbj_sleeve, 1);
3189
3190 msleep(600);
3191 regmap_read(rt5645->regmap, RT5645_IN1_CTRL3, &val);
3192 val &= 0x7;
3193 dev_dbg(component->dev, "val = %d\n", val);
3194
3195 if ((val == 1 || val == 2) && !rt5645->pdata.no_headset_mic) {
3196 rt5645->jack_type = SND_JACK_HEADSET;
3197 if (rt5645->en_button_func) {
3198 rt5645_enable_push_button_irq(component, true);
3199 }
3200 } else {
3201 if (rt5645->en_button_func)
3202 rt5645_enable_push_button_irq(component, false);
3203 snd_soc_dapm_disable_pin(dapm, "Mic Det Power");
3204 snd_soc_dapm_sync(dapm);
3205 rt5645->jack_type = SND_JACK_HEADPHONE;
3206 if (rt5645->gpiod_cbj_sleeve)
3207 gpiod_set_value(rt5645->gpiod_cbj_sleeve, 0);
3208 }
3209 if (rt5645->pdata.level_trigger_irq)
3210 regmap_update_bits(rt5645->regmap, RT5645_IRQ_CTRL2,
3211 RT5645_JD_1_1_MASK, RT5645_JD_1_1_NOR);
3212
3213 regmap_write(rt5645->regmap, RT5645_CHARGE_PUMP, 0x0e06);
3214 } else { /* jack out */
3215 rt5645->jack_type = 0;
3216
3217 regmap_update_bits(rt5645->regmap, RT5645_HP_VOL,
3218 RT5645_L_MUTE | RT5645_R_MUTE,
3219 RT5645_L_MUTE | RT5645_R_MUTE);
3220 regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL2,
3221 RT5645_CBJ_MN_JD, RT5645_CBJ_MN_JD);
3222 regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL1,
3223 RT5645_CBJ_BST1_EN, 0);
3224
3225 if (rt5645->en_button_func)
3226 rt5645_enable_push_button_irq(component, false);
3227
3228 if (rt5645->pdata.jd_mode == 0)
3229 snd_soc_dapm_disable_pin(dapm, "LDO2");
3230 snd_soc_dapm_disable_pin(dapm, "Mic Det Power");
3231 snd_soc_dapm_sync(dapm);
3232 if (rt5645->pdata.level_trigger_irq)
3233 regmap_update_bits(rt5645->regmap, RT5645_IRQ_CTRL2,
3234 RT5645_JD_1_1_MASK, RT5645_JD_1_1_INV);
3235
3236 if (rt5645->gpiod_cbj_sleeve)
3237 gpiod_set_value(rt5645->gpiod_cbj_sleeve, 0);
3238 }
3239
3240 return rt5645->jack_type;
3241 }
3242
rt5645_button_detect(struct snd_soc_component * component)3243 static int rt5645_button_detect(struct snd_soc_component *component)
3244 {
3245 int btn_type, val;
3246
3247 val = snd_soc_component_read(component, RT5650_4BTN_IL_CMD1);
3248 pr_debug("val=0x%x\n", val);
3249 btn_type = val & 0xfff0;
3250 snd_soc_component_write(component, RT5650_4BTN_IL_CMD1, val);
3251
3252 return btn_type;
3253 }
3254
3255 static irqreturn_t rt5645_irq(int irq, void *data);
3256
rt5645_set_jack_detect(struct snd_soc_component * component,struct snd_soc_jack * hp_jack,struct snd_soc_jack * mic_jack,struct snd_soc_jack * btn_jack)3257 int rt5645_set_jack_detect(struct snd_soc_component *component,
3258 struct snd_soc_jack *hp_jack, struct snd_soc_jack *mic_jack,
3259 struct snd_soc_jack *btn_jack)
3260 {
3261 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
3262
3263 rt5645->hp_jack = hp_jack;
3264 rt5645->mic_jack = mic_jack;
3265 rt5645->btn_jack = btn_jack;
3266 if (rt5645->btn_jack && rt5645->codec_type == CODEC_TYPE_RT5650) {
3267 rt5645->en_button_func = true;
3268 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
3269 RT5645_GP1_PIN_IRQ, RT5645_GP1_PIN_IRQ);
3270 regmap_update_bits(rt5645->regmap, RT5645_GEN_CTRL1,
3271 RT5645_DIG_GATE_CTRL, RT5645_DIG_GATE_CTRL);
3272 regmap_update_bits(rt5645->regmap, RT5645_DEPOP_M1,
3273 RT5645_HP_CB_MASK, RT5645_HP_CB_PU);
3274 }
3275 rt5645_irq(0, rt5645);
3276
3277 return 0;
3278 }
3279 EXPORT_SYMBOL_GPL(rt5645_set_jack_detect);
3280
rt5645_component_set_jack(struct snd_soc_component * component,struct snd_soc_jack * hs_jack,void * data)3281 static int rt5645_component_set_jack(struct snd_soc_component *component,
3282 struct snd_soc_jack *hs_jack, void *data)
3283 {
3284 struct snd_soc_jack *mic_jack = NULL;
3285 struct snd_soc_jack *btn_jack = NULL;
3286 int type;
3287
3288 if (hs_jack) {
3289 type = *(int *)data;
3290
3291 if (type & SND_JACK_MICROPHONE)
3292 mic_jack = hs_jack;
3293 if (type & (SND_JACK_BTN_0 | SND_JACK_BTN_1 |
3294 SND_JACK_BTN_2 | SND_JACK_BTN_3))
3295 btn_jack = hs_jack;
3296 }
3297
3298 return rt5645_set_jack_detect(component, hs_jack, mic_jack, btn_jack);
3299 }
3300
rt5645_jack_detect_work(struct work_struct * work)3301 static void rt5645_jack_detect_work(struct work_struct *work)
3302 {
3303 struct rt5645_priv *rt5645 =
3304 container_of(work, struct rt5645_priv, jack_detect_work.work);
3305 int val, btn_type, gpio_state = 0, report = 0;
3306
3307 if (!rt5645->component)
3308 return;
3309
3310 mutex_lock(&rt5645->jd_mutex);
3311
3312 switch (rt5645->pdata.jd_mode) {
3313 case 0: /* Not using rt5645 JD */
3314 if (rt5645->gpiod_hp_det) {
3315 gpio_state = gpiod_get_value(rt5645->gpiod_hp_det);
3316 if (rt5645->pdata.inv_hp_pol)
3317 gpio_state ^= 1;
3318 dev_dbg(rt5645->component->dev, "gpio_state = %d\n",
3319 gpio_state);
3320 report = rt5645_jack_detect(rt5645->component, gpio_state);
3321 }
3322 snd_soc_jack_report(rt5645->hp_jack,
3323 report, SND_JACK_HEADPHONE);
3324 snd_soc_jack_report(rt5645->mic_jack,
3325 report, SND_JACK_MICROPHONE);
3326 mutex_unlock(&rt5645->jd_mutex);
3327 return;
3328 case 4:
3329 val = snd_soc_component_read(rt5645->component, RT5645_A_JD_CTRL1) & 0x0020;
3330 break;
3331 default: /* read rt5645 jd1_1 status */
3332 val = snd_soc_component_read(rt5645->component, RT5645_INT_IRQ_ST) & 0x1000;
3333 break;
3334
3335 }
3336
3337 if (!val && (rt5645->jack_type == 0)) { /* jack in */
3338 report = rt5645_jack_detect(rt5645->component, 1);
3339 } else if (!val && rt5645->jack_type == SND_JACK_HEADSET) {
3340 /* for push button and jack out */
3341 btn_type = 0;
3342 if (snd_soc_component_read(rt5645->component, RT5645_INT_IRQ_ST) & 0x4) {
3343 /* button pressed */
3344 report = SND_JACK_HEADSET;
3345 btn_type = rt5645_button_detect(rt5645->component);
3346 /* rt5650 can report three kinds of button behavior,
3347 one click, double click and hold. However,
3348 currently we will report button pressed/released
3349 event. So all the three button behaviors are
3350 treated as button pressed. */
3351 switch (btn_type) {
3352 case 0x8000:
3353 case 0x4000:
3354 case 0x2000:
3355 report |= SND_JACK_BTN_0;
3356 break;
3357 case 0x1000:
3358 case 0x0800:
3359 case 0x0400:
3360 report |= SND_JACK_BTN_1;
3361 break;
3362 case 0x0200:
3363 case 0x0100:
3364 case 0x0080:
3365 report |= SND_JACK_BTN_2;
3366 break;
3367 case 0x0040:
3368 case 0x0020:
3369 case 0x0010:
3370 report |= SND_JACK_BTN_3;
3371 break;
3372 case 0x0000: /* unpressed */
3373 break;
3374 default:
3375 dev_err(rt5645->component->dev,
3376 "Unexpected button code 0x%04x\n",
3377 btn_type);
3378 break;
3379 }
3380 }
3381 if (btn_type == 0)/* button release */
3382 report = rt5645->jack_type;
3383 else {
3384 mod_timer(&rt5645->btn_check_timer,
3385 msecs_to_jiffies(100));
3386 }
3387 } else {
3388 /* jack out */
3389 report = 0;
3390 snd_soc_component_update_bits(rt5645->component,
3391 RT5645_INT_IRQ_ST, 0x1, 0x0);
3392 rt5645_jack_detect(rt5645->component, 0);
3393 }
3394
3395 mutex_unlock(&rt5645->jd_mutex);
3396
3397 snd_soc_jack_report(rt5645->hp_jack, report, SND_JACK_HEADPHONE);
3398 snd_soc_jack_report(rt5645->mic_jack, report, SND_JACK_MICROPHONE);
3399 if (rt5645->en_button_func)
3400 snd_soc_jack_report(rt5645->btn_jack,
3401 report, SND_JACK_BTN_0 | SND_JACK_BTN_1 |
3402 SND_JACK_BTN_2 | SND_JACK_BTN_3);
3403 }
3404
rt5645_rcclock_work(struct work_struct * work)3405 static void rt5645_rcclock_work(struct work_struct *work)
3406 {
3407 struct rt5645_priv *rt5645 =
3408 container_of(work, struct rt5645_priv, rcclock_work.work);
3409
3410 regmap_update_bits(rt5645->regmap, RT5645_MICBIAS,
3411 RT5645_PWR_CLK25M_MASK, RT5645_PWR_CLK25M_PD);
3412 }
3413
rt5645_irq(int irq,void * data)3414 static irqreturn_t rt5645_irq(int irq, void *data)
3415 {
3416 struct rt5645_priv *rt5645 = data;
3417
3418 queue_delayed_work(system_power_efficient_wq,
3419 &rt5645->jack_detect_work, msecs_to_jiffies(250));
3420
3421 return IRQ_HANDLED;
3422 }
3423
rt5645_btn_check_callback(struct timer_list * t)3424 static void rt5645_btn_check_callback(struct timer_list *t)
3425 {
3426 struct rt5645_priv *rt5645 = from_timer(rt5645, t, btn_check_timer);
3427
3428 queue_delayed_work(system_power_efficient_wq,
3429 &rt5645->jack_detect_work, msecs_to_jiffies(5));
3430 }
3431
rt5645_probe(struct snd_soc_component * component)3432 static int rt5645_probe(struct snd_soc_component *component)
3433 {
3434 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
3435 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
3436
3437 rt5645->component = component;
3438
3439 switch (rt5645->codec_type) {
3440 case CODEC_TYPE_RT5645:
3441 snd_soc_dapm_new_controls(dapm,
3442 rt5645_specific_dapm_widgets,
3443 ARRAY_SIZE(rt5645_specific_dapm_widgets));
3444 snd_soc_dapm_add_routes(dapm,
3445 rt5645_specific_dapm_routes,
3446 ARRAY_SIZE(rt5645_specific_dapm_routes));
3447 if (rt5645->v_id < 3) {
3448 snd_soc_dapm_add_routes(dapm,
3449 rt5645_old_dapm_routes,
3450 ARRAY_SIZE(rt5645_old_dapm_routes));
3451 }
3452 break;
3453 case CODEC_TYPE_RT5650:
3454 snd_soc_dapm_new_controls(dapm,
3455 rt5650_specific_dapm_widgets,
3456 ARRAY_SIZE(rt5650_specific_dapm_widgets));
3457 snd_soc_dapm_add_routes(dapm,
3458 rt5650_specific_dapm_routes,
3459 ARRAY_SIZE(rt5650_specific_dapm_routes));
3460 break;
3461 }
3462
3463 snd_soc_component_force_bias_level(component, SND_SOC_BIAS_OFF);
3464
3465 /* for JD function */
3466 if (rt5645->pdata.jd_mode) {
3467 snd_soc_dapm_force_enable_pin(dapm, "JD Power");
3468 snd_soc_dapm_force_enable_pin(dapm, "LDO2");
3469 snd_soc_dapm_sync(dapm);
3470 }
3471
3472 if (rt5645->pdata.long_name)
3473 component->card->long_name = rt5645->pdata.long_name;
3474
3475 rt5645->eq_param = devm_kcalloc(component->dev,
3476 RT5645_HWEQ_NUM, sizeof(struct rt5645_eq_param_s),
3477 GFP_KERNEL);
3478
3479 if (!rt5645->eq_param)
3480 return -ENOMEM;
3481
3482 return 0;
3483 }
3484
rt5645_remove(struct snd_soc_component * component)3485 static void rt5645_remove(struct snd_soc_component *component)
3486 {
3487 rt5645_reset(component);
3488 }
3489
3490 #ifdef CONFIG_PM
rt5645_suspend(struct snd_soc_component * component)3491 static int rt5645_suspend(struct snd_soc_component *component)
3492 {
3493 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
3494
3495 regcache_cache_only(rt5645->regmap, true);
3496 regcache_mark_dirty(rt5645->regmap);
3497
3498 return 0;
3499 }
3500
rt5645_resume(struct snd_soc_component * component)3501 static int rt5645_resume(struct snd_soc_component *component)
3502 {
3503 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
3504
3505 regcache_cache_only(rt5645->regmap, false);
3506 regcache_sync(rt5645->regmap);
3507
3508 return 0;
3509 }
3510 #else
3511 #define rt5645_suspend NULL
3512 #define rt5645_resume NULL
3513 #endif
3514
3515 #define RT5645_STEREO_RATES SNDRV_PCM_RATE_8000_96000
3516 #define RT5645_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
3517 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
3518
3519 static const struct snd_soc_dai_ops rt5645_aif_dai_ops = {
3520 .hw_params = rt5645_hw_params,
3521 .set_fmt = rt5645_set_dai_fmt,
3522 .set_sysclk = rt5645_set_dai_sysclk,
3523 .set_tdm_slot = rt5645_set_tdm_slot,
3524 .set_pll = rt5645_set_dai_pll,
3525 };
3526
3527 static struct snd_soc_dai_driver rt5645_dai[] = {
3528 {
3529 .name = "rt5645-aif1",
3530 .id = RT5645_AIF1,
3531 .playback = {
3532 .stream_name = "AIF1 Playback",
3533 .channels_min = 1,
3534 .channels_max = 2,
3535 .rates = RT5645_STEREO_RATES,
3536 .formats = RT5645_FORMATS,
3537 },
3538 .capture = {
3539 .stream_name = "AIF1 Capture",
3540 .channels_min = 1,
3541 .channels_max = 4,
3542 .rates = RT5645_STEREO_RATES,
3543 .formats = RT5645_FORMATS,
3544 },
3545 .ops = &rt5645_aif_dai_ops,
3546 },
3547 {
3548 .name = "rt5645-aif2",
3549 .id = RT5645_AIF2,
3550 .playback = {
3551 .stream_name = "AIF2 Playback",
3552 .channels_min = 1,
3553 .channels_max = 2,
3554 .rates = RT5645_STEREO_RATES,
3555 .formats = RT5645_FORMATS,
3556 },
3557 .capture = {
3558 .stream_name = "AIF2 Capture",
3559 .channels_min = 1,
3560 .channels_max = 2,
3561 .rates = RT5645_STEREO_RATES,
3562 .formats = RT5645_FORMATS,
3563 },
3564 .ops = &rt5645_aif_dai_ops,
3565 },
3566 };
3567
3568 static const struct snd_soc_component_driver soc_component_dev_rt5645 = {
3569 .probe = rt5645_probe,
3570 .remove = rt5645_remove,
3571 .suspend = rt5645_suspend,
3572 .resume = rt5645_resume,
3573 .set_bias_level = rt5645_set_bias_level,
3574 .controls = rt5645_snd_controls,
3575 .num_controls = ARRAY_SIZE(rt5645_snd_controls),
3576 .dapm_widgets = rt5645_dapm_widgets,
3577 .num_dapm_widgets = ARRAY_SIZE(rt5645_dapm_widgets),
3578 .dapm_routes = rt5645_dapm_routes,
3579 .num_dapm_routes = ARRAY_SIZE(rt5645_dapm_routes),
3580 .set_jack = rt5645_component_set_jack,
3581 .use_pmdown_time = 1,
3582 .endianness = 1,
3583 };
3584
3585 static const struct regmap_config rt5645_regmap = {
3586 .reg_bits = 8,
3587 .val_bits = 16,
3588 .use_single_read = true,
3589 .use_single_write = true,
3590 .max_register = RT5645_VENDOR_ID2 + 1 + (ARRAY_SIZE(rt5645_ranges) *
3591 RT5645_PR_SPACING),
3592 .volatile_reg = rt5645_volatile_register,
3593 .readable_reg = rt5645_readable_register,
3594
3595 .cache_type = REGCACHE_MAPLE,
3596 .reg_defaults = rt5645_reg,
3597 .num_reg_defaults = ARRAY_SIZE(rt5645_reg),
3598 .ranges = rt5645_ranges,
3599 .num_ranges = ARRAY_SIZE(rt5645_ranges),
3600 };
3601
3602 static const struct regmap_config rt5650_regmap = {
3603 .reg_bits = 8,
3604 .val_bits = 16,
3605 .use_single_read = true,
3606 .use_single_write = true,
3607 .max_register = RT5645_VENDOR_ID2 + 1 + (ARRAY_SIZE(rt5645_ranges) *
3608 RT5645_PR_SPACING),
3609 .volatile_reg = rt5645_volatile_register,
3610 .readable_reg = rt5645_readable_register,
3611
3612 .cache_type = REGCACHE_MAPLE,
3613 .reg_defaults = rt5650_reg,
3614 .num_reg_defaults = ARRAY_SIZE(rt5650_reg),
3615 .ranges = rt5645_ranges,
3616 .num_ranges = ARRAY_SIZE(rt5645_ranges),
3617 };
3618
3619 static const struct regmap_config temp_regmap = {
3620 .name="nocache",
3621 .reg_bits = 8,
3622 .val_bits = 16,
3623 .use_single_read = true,
3624 .use_single_write = true,
3625 .max_register = RT5645_VENDOR_ID2 + 1,
3626 .cache_type = REGCACHE_NONE,
3627 };
3628
3629 static const struct i2c_device_id rt5645_i2c_id[] = {
3630 { "rt5645", 0 },
3631 { "rt5650", 0 },
3632 { }
3633 };
3634 MODULE_DEVICE_TABLE(i2c, rt5645_i2c_id);
3635
3636 #ifdef CONFIG_OF
3637 static const struct of_device_id rt5645_of_match[] = {
3638 { .compatible = "realtek,rt5645", },
3639 { .compatible = "realtek,rt5650", },
3640 { }
3641 };
3642 MODULE_DEVICE_TABLE(of, rt5645_of_match);
3643 #endif
3644
3645 #ifdef CONFIG_ACPI
3646 static const struct acpi_device_id rt5645_acpi_match[] = {
3647 { "10EC5645", 0 },
3648 { "10EC5648", 0 },
3649 { "10EC5650", 0 },
3650 { "10EC5640", 0 },
3651 { "10EC3270", 0 },
3652 {},
3653 };
3654 MODULE_DEVICE_TABLE(acpi, rt5645_acpi_match);
3655 #endif
3656
3657 static const struct rt5645_platform_data intel_braswell_platform_data = {
3658 .dmic1_data_pin = RT5645_DMIC1_DISABLE,
3659 .dmic2_data_pin = RT5645_DMIC_DATA_IN2P,
3660 .jd_mode = 3,
3661 };
3662
3663 static const struct rt5645_platform_data buddy_platform_data = {
3664 .dmic1_data_pin = RT5645_DMIC_DATA_GPIO5,
3665 .dmic2_data_pin = RT5645_DMIC_DATA_IN2P,
3666 .jd_mode = 4,
3667 .level_trigger_irq = true,
3668 };
3669
3670 static const struct rt5645_platform_data gpd_win_platform_data = {
3671 .jd_mode = 3,
3672 .inv_jd1_1 = true,
3673 .long_name = "gpd-win-pocket-rt5645",
3674 /* The GPD pocket has a diff. mic, for the win this does not matter. */
3675 .in2_diff = true,
3676 };
3677
3678 static const struct rt5645_platform_data asus_t100ha_platform_data = {
3679 .dmic1_data_pin = RT5645_DMIC_DATA_IN2N,
3680 .dmic2_data_pin = RT5645_DMIC2_DISABLE,
3681 .jd_mode = 3,
3682 .inv_jd1_1 = true,
3683 };
3684
3685 static const struct rt5645_platform_data asus_t101ha_platform_data = {
3686 .dmic1_data_pin = RT5645_DMIC_DATA_IN2N,
3687 .dmic2_data_pin = RT5645_DMIC2_DISABLE,
3688 .jd_mode = 3,
3689 };
3690
3691 static const struct rt5645_platform_data lenovo_ideapad_miix_310_pdata = {
3692 .jd_mode = 3,
3693 .in2_diff = true,
3694 };
3695
3696 static const struct rt5645_platform_data jd_mode3_platform_data = {
3697 .jd_mode = 3,
3698 };
3699
3700 static const struct rt5645_platform_data lattepanda_board_platform_data = {
3701 .jd_mode = 2,
3702 .inv_jd1_1 = true
3703 };
3704
3705 static const struct rt5645_platform_data kahlee_platform_data = {
3706 .dmic1_data_pin = RT5645_DMIC_DATA_GPIO5,
3707 .dmic2_data_pin = RT5645_DMIC_DATA_IN2P,
3708 .jd_mode = 3,
3709 };
3710
3711 static const struct rt5645_platform_data ecs_ef20_platform_data = {
3712 .dmic1_data_pin = RT5645_DMIC1_DISABLE,
3713 .dmic2_data_pin = RT5645_DMIC_DATA_IN2P,
3714 .inv_hp_pol = 1,
3715 };
3716
3717 static const struct acpi_gpio_params ef20_hp_detect = { 1, 0, false };
3718
3719 static const struct acpi_gpio_mapping cht_rt5645_ef20_gpios[] = {
3720 { "hp-detect-gpios", &ef20_hp_detect, 1 },
3721 { },
3722 };
3723
cht_rt5645_ef20_quirk_cb(const struct dmi_system_id * id)3724 static int cht_rt5645_ef20_quirk_cb(const struct dmi_system_id *id)
3725 {
3726 cht_rt5645_gpios = cht_rt5645_ef20_gpios;
3727 return 1;
3728 }
3729
3730 static const struct dmi_system_id dmi_platform_data[] = {
3731 {
3732 .ident = "Chrome Buddy",
3733 .matches = {
3734 DMI_MATCH(DMI_PRODUCT_NAME, "Buddy"),
3735 },
3736 .driver_data = (void *)&buddy_platform_data,
3737 },
3738 {
3739 .ident = "Intel Strago",
3740 .matches = {
3741 DMI_MATCH(DMI_PRODUCT_NAME, "Strago"),
3742 },
3743 .driver_data = (void *)&intel_braswell_platform_data,
3744 },
3745 {
3746 .ident = "Google Chrome",
3747 .matches = {
3748 DMI_MATCH(DMI_SYS_VENDOR, "GOOGLE"),
3749 },
3750 .driver_data = (void *)&intel_braswell_platform_data,
3751 },
3752 {
3753 .ident = "Google Setzer",
3754 .matches = {
3755 DMI_MATCH(DMI_PRODUCT_NAME, "Setzer"),
3756 },
3757 .driver_data = (void *)&intel_braswell_platform_data,
3758 },
3759 {
3760 .ident = "Microsoft Surface 3",
3761 .matches = {
3762 DMI_MATCH(DMI_PRODUCT_NAME, "Surface 3"),
3763 },
3764 .driver_data = (void *)&intel_braswell_platform_data,
3765 },
3766 {
3767 /*
3768 * Match for the GPDwin which unfortunately uses somewhat
3769 * generic dmi strings, which is why we test for 4 strings.
3770 * Comparing against 23 other byt/cht boards, board_vendor
3771 * and board_name are unique to the GPDwin, where as only one
3772 * other board has the same board_serial and 3 others have
3773 * the same default product_name. Also the GPDwin is the
3774 * only device to have both board_ and product_name not set.
3775 */
3776 .ident = "GPD Win / Pocket",
3777 .matches = {
3778 DMI_MATCH(DMI_BOARD_VENDOR, "AMI Corporation"),
3779 DMI_MATCH(DMI_BOARD_NAME, "Default string"),
3780 DMI_MATCH(DMI_BOARD_SERIAL, "Default string"),
3781 DMI_MATCH(DMI_PRODUCT_NAME, "Default string"),
3782 },
3783 .driver_data = (void *)&gpd_win_platform_data,
3784 },
3785 {
3786 .ident = "ASUS T100HAN",
3787 .matches = {
3788 DMI_EXACT_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."),
3789 DMI_MATCH(DMI_PRODUCT_NAME, "T100HAN"),
3790 },
3791 .driver_data = (void *)&asus_t100ha_platform_data,
3792 },
3793 {
3794 .ident = "ASUS T101HA",
3795 .matches = {
3796 DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."),
3797 DMI_MATCH(DMI_PRODUCT_NAME, "T101HA"),
3798 },
3799 .driver_data = (void *)&asus_t101ha_platform_data,
3800 },
3801 {
3802 .ident = "MINIX Z83-4",
3803 .matches = {
3804 DMI_EXACT_MATCH(DMI_SYS_VENDOR, "MINIX"),
3805 DMI_MATCH(DMI_PRODUCT_NAME, "Z83-4"),
3806 },
3807 .driver_data = (void *)&jd_mode3_platform_data,
3808 },
3809 {
3810 .ident = "Teclast X80 Pro",
3811 .matches = {
3812 DMI_MATCH(DMI_SYS_VENDOR, "TECLAST"),
3813 DMI_MATCH(DMI_PRODUCT_NAME, "X80 Pro"),
3814 },
3815 .driver_data = (void *)&jd_mode3_platform_data,
3816 },
3817 {
3818 .ident = "Lenovo Ideapad Miix 310",
3819 .matches = {
3820 DMI_EXACT_MATCH(DMI_SYS_VENDOR, "LENOVO"),
3821 DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "80SG"),
3822 DMI_EXACT_MATCH(DMI_PRODUCT_VERSION, "MIIX 310-10ICR"),
3823 },
3824 .driver_data = (void *)&lenovo_ideapad_miix_310_pdata,
3825 },
3826 {
3827 .ident = "Lenovo Ideapad Miix 320",
3828 .matches = {
3829 DMI_EXACT_MATCH(DMI_SYS_VENDOR, "LENOVO"),
3830 DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "80XF"),
3831 DMI_EXACT_MATCH(DMI_PRODUCT_VERSION, "Lenovo MIIX 320-10ICR"),
3832 },
3833 .driver_data = (void *)&intel_braswell_platform_data,
3834 },
3835 {
3836 .ident = "LattePanda board",
3837 .matches = {
3838 DMI_EXACT_MATCH(DMI_BOARD_VENDOR, "AMI Corporation"),
3839 DMI_EXACT_MATCH(DMI_BOARD_NAME, "Cherry Trail CR"),
3840 DMI_EXACT_MATCH(DMI_BOARD_VERSION, "Default string"),
3841 /*
3842 * Above strings are too generic, LattePanda BIOS versions for
3843 * all 4 hw revisions are:
3844 * DF-BI-7-S70CR100-*
3845 * DF-BI-7-S70CR110-*
3846 * DF-BI-7-S70CR200-*
3847 * LP-BS-7-S70CR700-*
3848 * Do a partial match for S70CR to avoid false positive matches.
3849 */
3850 DMI_MATCH(DMI_BIOS_VERSION, "S70CR"),
3851 },
3852 .driver_data = (void *)&lattepanda_board_platform_data,
3853 },
3854 {
3855 .ident = "Chrome Kahlee",
3856 .matches = {
3857 DMI_MATCH(DMI_PRODUCT_NAME, "Kahlee"),
3858 },
3859 .driver_data = (void *)&kahlee_platform_data,
3860 },
3861 {
3862 .ident = "Medion E1239T",
3863 .matches = {
3864 DMI_EXACT_MATCH(DMI_SYS_VENDOR, "MEDION"),
3865 DMI_MATCH(DMI_PRODUCT_NAME, "E1239T MD60568"),
3866 },
3867 .driver_data = (void *)&intel_braswell_platform_data,
3868 },
3869 {
3870 .ident = "EF20",
3871 .callback = cht_rt5645_ef20_quirk_cb,
3872 .matches = {
3873 DMI_MATCH(DMI_PRODUCT_NAME, "EF20"),
3874 },
3875 .driver_data = (void *)&ecs_ef20_platform_data,
3876 },
3877 { }
3878 };
3879
rt5645_check_dp(struct device * dev)3880 static bool rt5645_check_dp(struct device *dev)
3881 {
3882 if (device_property_present(dev, "realtek,in2-differential") ||
3883 device_property_present(dev, "realtek,dmic1-data-pin") ||
3884 device_property_present(dev, "realtek,dmic2-data-pin") ||
3885 device_property_present(dev, "realtek,jd-mode"))
3886 return true;
3887
3888 return false;
3889 }
3890
rt5645_parse_dt(struct rt5645_priv * rt5645,struct device * dev)3891 static int rt5645_parse_dt(struct rt5645_priv *rt5645, struct device *dev)
3892 {
3893 rt5645->pdata.in2_diff = device_property_read_bool(dev,
3894 "realtek,in2-differential");
3895 device_property_read_u32(dev,
3896 "realtek,dmic1-data-pin", &rt5645->pdata.dmic1_data_pin);
3897 device_property_read_u32(dev,
3898 "realtek,dmic2-data-pin", &rt5645->pdata.dmic2_data_pin);
3899 device_property_read_u32(dev,
3900 "realtek,jd-mode", &rt5645->pdata.jd_mode);
3901
3902 return 0;
3903 }
3904
rt5645_i2c_probe(struct i2c_client * i2c)3905 static int rt5645_i2c_probe(struct i2c_client *i2c)
3906 {
3907 struct rt5645_platform_data *pdata = NULL;
3908 const struct dmi_system_id *dmi_data;
3909 struct rt5645_priv *rt5645;
3910 int ret, i;
3911 unsigned int val;
3912 struct regmap *regmap;
3913
3914 rt5645 = devm_kzalloc(&i2c->dev, sizeof(struct rt5645_priv),
3915 GFP_KERNEL);
3916 if (rt5645 == NULL)
3917 return -ENOMEM;
3918
3919 rt5645->i2c = i2c;
3920 i2c_set_clientdata(i2c, rt5645);
3921
3922 dmi_data = dmi_first_match(dmi_platform_data);
3923 if (dmi_data) {
3924 dev_info(&i2c->dev, "Detected %s platform\n", dmi_data->ident);
3925 pdata = dmi_data->driver_data;
3926 }
3927
3928 if (pdata)
3929 rt5645->pdata = *pdata;
3930 else if (rt5645_check_dp(&i2c->dev))
3931 rt5645_parse_dt(rt5645, &i2c->dev);
3932 else
3933 rt5645->pdata = jd_mode3_platform_data;
3934
3935 if (quirk != -1) {
3936 rt5645->pdata.in2_diff = QUIRK_IN2_DIFF(quirk);
3937 rt5645->pdata.level_trigger_irq = QUIRK_LEVEL_IRQ(quirk);
3938 rt5645->pdata.inv_jd1_1 = QUIRK_INV_JD1_1(quirk);
3939 rt5645->pdata.inv_hp_pol = QUIRK_INV_HP_POL(quirk);
3940 rt5645->pdata.jd_mode = QUIRK_JD_MODE(quirk);
3941 rt5645->pdata.dmic1_data_pin = QUIRK_DMIC1_DATA_PIN(quirk);
3942 rt5645->pdata.dmic2_data_pin = QUIRK_DMIC2_DATA_PIN(quirk);
3943 }
3944
3945 if (has_acpi_companion(&i2c->dev)) {
3946 if (cht_rt5645_gpios) {
3947 if (devm_acpi_dev_add_driver_gpios(&i2c->dev, cht_rt5645_gpios))
3948 dev_dbg(&i2c->dev, "Failed to add driver gpios\n");
3949 }
3950
3951 /* The ALC3270 package has the headset-mic pin not-connected */
3952 if (acpi_dev_hid_uid_match(ACPI_COMPANION(&i2c->dev), "10EC3270", NULL))
3953 rt5645->pdata.no_headset_mic = true;
3954 }
3955
3956 rt5645->gpiod_hp_det = devm_gpiod_get_optional(&i2c->dev, "hp-detect",
3957 GPIOD_IN);
3958
3959 if (IS_ERR(rt5645->gpiod_hp_det)) {
3960 dev_info(&i2c->dev, "failed to initialize gpiod\n");
3961 ret = PTR_ERR(rt5645->gpiod_hp_det);
3962 /*
3963 * Continue if optional gpiod is missing, bail for all other
3964 * errors, including -EPROBE_DEFER
3965 */
3966 if (ret != -ENOENT)
3967 return ret;
3968 }
3969
3970 rt5645->gpiod_cbj_sleeve = devm_gpiod_get_optional(&i2c->dev, "cbj-sleeve",
3971 GPIOD_OUT_LOW);
3972
3973 if (IS_ERR(rt5645->gpiod_cbj_sleeve)) {
3974 ret = PTR_ERR(rt5645->gpiod_cbj_sleeve);
3975 dev_info(&i2c->dev, "failed to initialize gpiod, ret=%d\n", ret);
3976 if (ret != -ENOENT)
3977 return ret;
3978 }
3979
3980 for (i = 0; i < ARRAY_SIZE(rt5645->supplies); i++)
3981 rt5645->supplies[i].supply = rt5645_supply_names[i];
3982
3983 ret = devm_regulator_bulk_get(&i2c->dev,
3984 ARRAY_SIZE(rt5645->supplies),
3985 rt5645->supplies);
3986 if (ret) {
3987 dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
3988 return ret;
3989 }
3990
3991 ret = regulator_bulk_enable(ARRAY_SIZE(rt5645->supplies),
3992 rt5645->supplies);
3993 if (ret) {
3994 dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret);
3995 return ret;
3996 }
3997
3998 regmap = devm_regmap_init_i2c(i2c, &temp_regmap);
3999 if (IS_ERR(regmap)) {
4000 ret = PTR_ERR(regmap);
4001 dev_err(&i2c->dev, "Failed to allocate temp register map: %d\n",
4002 ret);
4003 goto err_enable;
4004 }
4005
4006 /*
4007 * Read after 400msec, as it is the interval required between
4008 * read and power On.
4009 */
4010 msleep(TIME_TO_POWER_MS);
4011 ret = regmap_read(regmap, RT5645_VENDOR_ID2, &val);
4012 if (ret < 0) {
4013 dev_err(&i2c->dev, "Failed to read: 0x%02X\n, ret = %d", RT5645_VENDOR_ID2, ret);
4014 goto err_enable;
4015 }
4016
4017 switch (val) {
4018 case RT5645_DEVICE_ID:
4019 rt5645->regmap = devm_regmap_init_i2c(i2c, &rt5645_regmap);
4020 rt5645->codec_type = CODEC_TYPE_RT5645;
4021 break;
4022 case RT5650_DEVICE_ID:
4023 rt5645->regmap = devm_regmap_init_i2c(i2c, &rt5650_regmap);
4024 rt5645->codec_type = CODEC_TYPE_RT5650;
4025 break;
4026 default:
4027 dev_err(&i2c->dev,
4028 "Device with ID register %#x is not rt5645 or rt5650\n",
4029 val);
4030 ret = -ENODEV;
4031 goto err_enable;
4032 }
4033
4034 if (IS_ERR(rt5645->regmap)) {
4035 ret = PTR_ERR(rt5645->regmap);
4036 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
4037 ret);
4038 goto err_enable;
4039 }
4040
4041 regmap_write(rt5645->regmap, RT5645_RESET, 0);
4042
4043 regmap_read(regmap, RT5645_VENDOR_ID, &val);
4044 rt5645->v_id = val & 0xff;
4045
4046 regmap_write(rt5645->regmap, RT5645_AD_DA_MIXER, 0x8080);
4047
4048 ret = regmap_multi_reg_write(rt5645->regmap, init_list,
4049 ARRAY_SIZE(init_list));
4050 if (ret != 0)
4051 dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret);
4052
4053 if (rt5645->codec_type == CODEC_TYPE_RT5650) {
4054 ret = regmap_multi_reg_write(rt5645->regmap, rt5650_init_list,
4055 ARRAY_SIZE(rt5650_init_list));
4056 if (ret != 0)
4057 dev_warn(&i2c->dev, "Apply rt5650 patch failed: %d\n",
4058 ret);
4059 }
4060
4061 regmap_update_bits(rt5645->regmap, RT5645_CLSD_OUT_CTRL, 0xc0, 0xc0);
4062
4063 if (rt5645->pdata.in2_diff)
4064 regmap_update_bits(rt5645->regmap, RT5645_IN2_CTRL,
4065 RT5645_IN_DF2, RT5645_IN_DF2);
4066
4067 if (rt5645->pdata.dmic1_data_pin || rt5645->pdata.dmic2_data_pin) {
4068 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
4069 RT5645_GP2_PIN_MASK, RT5645_GP2_PIN_DMIC1_SCL);
4070 }
4071 switch (rt5645->pdata.dmic1_data_pin) {
4072 case RT5645_DMIC_DATA_IN2N:
4073 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
4074 RT5645_DMIC_1_DP_MASK, RT5645_DMIC_1_DP_IN2N);
4075 break;
4076
4077 case RT5645_DMIC_DATA_GPIO5:
4078 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
4079 RT5645_I2S2_DAC_PIN_MASK, RT5645_I2S2_DAC_PIN_GPIO);
4080 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
4081 RT5645_DMIC_1_DP_MASK, RT5645_DMIC_1_DP_GPIO5);
4082 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
4083 RT5645_GP5_PIN_MASK, RT5645_GP5_PIN_DMIC1_SDA);
4084 break;
4085
4086 case RT5645_DMIC_DATA_GPIO11:
4087 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
4088 RT5645_DMIC_1_DP_MASK, RT5645_DMIC_1_DP_GPIO11);
4089 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
4090 RT5645_GP11_PIN_MASK,
4091 RT5645_GP11_PIN_DMIC1_SDA);
4092 break;
4093
4094 default:
4095 break;
4096 }
4097
4098 switch (rt5645->pdata.dmic2_data_pin) {
4099 case RT5645_DMIC_DATA_IN2P:
4100 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
4101 RT5645_DMIC_2_DP_MASK, RT5645_DMIC_2_DP_IN2P);
4102 break;
4103
4104 case RT5645_DMIC_DATA_GPIO6:
4105 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
4106 RT5645_DMIC_2_DP_MASK, RT5645_DMIC_2_DP_GPIO6);
4107 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
4108 RT5645_GP6_PIN_MASK, RT5645_GP6_PIN_DMIC2_SDA);
4109 break;
4110
4111 case RT5645_DMIC_DATA_GPIO10:
4112 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
4113 RT5645_DMIC_2_DP_MASK, RT5645_DMIC_2_DP_GPIO10);
4114 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
4115 RT5645_GP10_PIN_MASK,
4116 RT5645_GP10_PIN_DMIC2_SDA);
4117 break;
4118
4119 case RT5645_DMIC_DATA_GPIO12:
4120 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
4121 RT5645_DMIC_2_DP_MASK, RT5645_DMIC_2_DP_GPIO12);
4122 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
4123 RT5645_GP12_PIN_MASK,
4124 RT5645_GP12_PIN_DMIC2_SDA);
4125 break;
4126
4127 default:
4128 break;
4129 }
4130
4131 if (rt5645->pdata.jd_mode) {
4132 regmap_update_bits(rt5645->regmap, RT5645_GEN_CTRL3,
4133 RT5645_IRQ_CLK_GATE_CTRL,
4134 RT5645_IRQ_CLK_GATE_CTRL);
4135 regmap_update_bits(rt5645->regmap, RT5645_MICBIAS,
4136 RT5645_IRQ_CLK_INT, RT5645_IRQ_CLK_INT);
4137 regmap_update_bits(rt5645->regmap, RT5645_IRQ_CTRL2,
4138 RT5645_IRQ_JD_1_1_EN, RT5645_IRQ_JD_1_1_EN);
4139 regmap_update_bits(rt5645->regmap, RT5645_GEN_CTRL3,
4140 RT5645_JD_PSV_MODE, RT5645_JD_PSV_MODE);
4141 regmap_update_bits(rt5645->regmap, RT5645_HPO_MIXER,
4142 RT5645_IRQ_PSV_MODE, RT5645_IRQ_PSV_MODE);
4143 regmap_update_bits(rt5645->regmap, RT5645_MICBIAS,
4144 RT5645_MIC2_OVCD_EN, RT5645_MIC2_OVCD_EN);
4145 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
4146 RT5645_GP1_PIN_IRQ, RT5645_GP1_PIN_IRQ);
4147 switch (rt5645->pdata.jd_mode) {
4148 case 1:
4149 regmap_update_bits(rt5645->regmap, RT5645_A_JD_CTRL1,
4150 RT5645_JD1_MODE_MASK,
4151 RT5645_JD1_MODE_0);
4152 break;
4153 case 2:
4154 regmap_update_bits(rt5645->regmap, RT5645_A_JD_CTRL1,
4155 RT5645_JD1_MODE_MASK,
4156 RT5645_JD1_MODE_1);
4157 break;
4158 case 3:
4159 case 4:
4160 regmap_update_bits(rt5645->regmap, RT5645_A_JD_CTRL1,
4161 RT5645_JD1_MODE_MASK,
4162 RT5645_JD1_MODE_2);
4163 break;
4164 default:
4165 break;
4166 }
4167 if (rt5645->pdata.inv_jd1_1) {
4168 regmap_update_bits(rt5645->regmap, RT5645_IRQ_CTRL2,
4169 RT5645_JD_1_1_MASK, RT5645_JD_1_1_INV);
4170 }
4171 }
4172
4173 regmap_update_bits(rt5645->regmap, RT5645_ADDA_CLK1,
4174 RT5645_I2S_PD1_MASK, RT5645_I2S_PD1_2);
4175
4176 if (rt5645->pdata.level_trigger_irq) {
4177 regmap_update_bits(rt5645->regmap, RT5645_IRQ_CTRL2,
4178 RT5645_JD_1_1_MASK, RT5645_JD_1_1_INV);
4179 }
4180 timer_setup(&rt5645->btn_check_timer, rt5645_btn_check_callback, 0);
4181
4182 mutex_init(&rt5645->jd_mutex);
4183 INIT_DELAYED_WORK(&rt5645->jack_detect_work, rt5645_jack_detect_work);
4184 INIT_DELAYED_WORK(&rt5645->rcclock_work, rt5645_rcclock_work);
4185
4186 if (rt5645->i2c->irq) {
4187 ret = request_threaded_irq(rt5645->i2c->irq, NULL, rt5645_irq,
4188 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING
4189 | IRQF_ONESHOT, "rt5645", rt5645);
4190 if (ret) {
4191 dev_err(&i2c->dev, "Failed to reguest IRQ: %d\n", ret);
4192 goto err_enable;
4193 }
4194 }
4195
4196 ret = devm_snd_soc_register_component(&i2c->dev, &soc_component_dev_rt5645,
4197 rt5645_dai, ARRAY_SIZE(rt5645_dai));
4198 if (ret)
4199 goto err_irq;
4200
4201 return 0;
4202
4203 err_irq:
4204 if (rt5645->i2c->irq)
4205 free_irq(rt5645->i2c->irq, rt5645);
4206 err_enable:
4207 regulator_bulk_disable(ARRAY_SIZE(rt5645->supplies), rt5645->supplies);
4208 return ret;
4209 }
4210
rt5645_i2c_remove(struct i2c_client * i2c)4211 static void rt5645_i2c_remove(struct i2c_client *i2c)
4212 {
4213 struct rt5645_priv *rt5645 = i2c_get_clientdata(i2c);
4214
4215 if (i2c->irq)
4216 free_irq(i2c->irq, rt5645);
4217
4218 /*
4219 * Since the rt5645_btn_check_callback() can queue jack_detect_work,
4220 * the timer need to be delted first
4221 */
4222 del_timer_sync(&rt5645->btn_check_timer);
4223
4224 cancel_delayed_work_sync(&rt5645->jack_detect_work);
4225 cancel_delayed_work_sync(&rt5645->rcclock_work);
4226
4227 if (rt5645->gpiod_cbj_sleeve)
4228 gpiod_set_value(rt5645->gpiod_cbj_sleeve, 0);
4229
4230 regulator_bulk_disable(ARRAY_SIZE(rt5645->supplies), rt5645->supplies);
4231 }
4232
rt5645_i2c_shutdown(struct i2c_client * i2c)4233 static void rt5645_i2c_shutdown(struct i2c_client *i2c)
4234 {
4235 struct rt5645_priv *rt5645 = i2c_get_clientdata(i2c);
4236
4237 regmap_update_bits(rt5645->regmap, RT5645_GEN_CTRL3,
4238 RT5645_RING2_SLEEVE_GND, RT5645_RING2_SLEEVE_GND);
4239 regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL2, RT5645_CBJ_MN_JD,
4240 RT5645_CBJ_MN_JD);
4241 regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL1, RT5645_CBJ_BST1_EN,
4242 0);
4243 msleep(20);
4244 regmap_write(rt5645->regmap, RT5645_RESET, 0);
4245
4246 if (rt5645->gpiod_cbj_sleeve)
4247 gpiod_set_value(rt5645->gpiod_cbj_sleeve, 0);
4248 }
4249
rt5645_sys_suspend(struct device * dev)4250 static int __maybe_unused rt5645_sys_suspend(struct device *dev)
4251 {
4252 struct rt5645_priv *rt5645 = dev_get_drvdata(dev);
4253
4254 del_timer_sync(&rt5645->btn_check_timer);
4255 cancel_delayed_work_sync(&rt5645->jack_detect_work);
4256 cancel_delayed_work_sync(&rt5645->rcclock_work);
4257
4258 regcache_cache_only(rt5645->regmap, true);
4259 regcache_mark_dirty(rt5645->regmap);
4260 return 0;
4261 }
4262
rt5645_sys_resume(struct device * dev)4263 static int __maybe_unused rt5645_sys_resume(struct device *dev)
4264 {
4265 struct rt5645_priv *rt5645 = dev_get_drvdata(dev);
4266
4267 regcache_cache_only(rt5645->regmap, false);
4268 regcache_sync(rt5645->regmap);
4269
4270 if (rt5645->hp_jack) {
4271 rt5645->jack_type = 0;
4272 rt5645_jack_detect_work(&rt5645->jack_detect_work.work);
4273 }
4274 return 0;
4275 }
4276
4277 static const struct dev_pm_ops rt5645_pm = {
4278 SET_SYSTEM_SLEEP_PM_OPS(rt5645_sys_suspend, rt5645_sys_resume)
4279 };
4280
4281 static struct i2c_driver rt5645_i2c_driver = {
4282 .driver = {
4283 .name = "rt5645",
4284 .of_match_table = of_match_ptr(rt5645_of_match),
4285 .acpi_match_table = ACPI_PTR(rt5645_acpi_match),
4286 .pm = &rt5645_pm,
4287 },
4288 .probe = rt5645_i2c_probe,
4289 .remove = rt5645_i2c_remove,
4290 .shutdown = rt5645_i2c_shutdown,
4291 .id_table = rt5645_i2c_id,
4292 };
4293 module_i2c_driver(rt5645_i2c_driver);
4294
4295 MODULE_DESCRIPTION("ASoC RT5645 driver");
4296 MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>");
4297 MODULE_LICENSE("GPL v2");
4298