1d2912cb1SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 2997b0520SBard Liao /* 3997b0520SBard Liao * rt5640.h -- RT5640 ALSA SoC audio driver 4997b0520SBard Liao * 5997b0520SBard Liao * Copyright 2011 Realtek Microelectronics 6997b0520SBard Liao * Author: Johnny Hsu <johnnyhsu@realtek.com> 7997b0520SBard Liao */ 8997b0520SBard Liao 9997b0520SBard Liao #ifndef _RT5640_H 10997b0520SBard Liao #define _RT5640_H 11997b0520SBard Liao 126049af00SSugar Zhang #include <linux/clk.h> 13d21213b4SHans de Goede #include <linux/gpio/consumer.h> 148210804bSHans de Goede #include <linux/workqueue.h> 158210804bSHans de Goede #include <dt-bindings/sound/rt5640.h> 16997b0520SBard Liao 17997b0520SBard Liao /* Info */ 18997b0520SBard Liao #define RT5640_RESET 0x00 19997b0520SBard Liao #define RT5640_VENDOR_ID 0xfd 20997b0520SBard Liao #define RT5640_VENDOR_ID1 0xfe 21997b0520SBard Liao #define RT5640_VENDOR_ID2 0xff 22997b0520SBard Liao /* I/O - Output */ 23997b0520SBard Liao #define RT5640_SPK_VOL 0x01 24997b0520SBard Liao #define RT5640_HP_VOL 0x02 25997b0520SBard Liao #define RT5640_OUTPUT 0x03 26997b0520SBard Liao #define RT5640_MONO_OUT 0x04 27997b0520SBard Liao /* I/O - Input */ 28997b0520SBard Liao #define RT5640_IN1_IN2 0x0d 29997b0520SBard Liao #define RT5640_IN3_IN4 0x0e 30997b0520SBard Liao #define RT5640_INL_INR_VOL 0x0f 31997b0520SBard Liao /* I/O - ADC/DAC/DMIC */ 32997b0520SBard Liao #define RT5640_DAC1_DIG_VOL 0x19 33997b0520SBard Liao #define RT5640_DAC2_DIG_VOL 0x1a 34997b0520SBard Liao #define RT5640_DAC2_CTRL 0x1b 35997b0520SBard Liao #define RT5640_ADC_DIG_VOL 0x1c 36997b0520SBard Liao #define RT5640_ADC_DATA 0x1d 37997b0520SBard Liao #define RT5640_ADC_BST_VOL 0x1e 38997b0520SBard Liao /* Mixer - D-D */ 39997b0520SBard Liao #define RT5640_STO_ADC_MIXER 0x27 40997b0520SBard Liao #define RT5640_MONO_ADC_MIXER 0x28 41997b0520SBard Liao #define RT5640_AD_DA_MIXER 0x29 42997b0520SBard Liao #define RT5640_STO_DAC_MIXER 0x2a 43997b0520SBard Liao #define RT5640_MONO_DAC_MIXER 0x2b 44997b0520SBard Liao #define RT5640_DIG_MIXER 0x2c 45997b0520SBard Liao #define RT5640_DSP_PATH1 0x2d 46997b0520SBard Liao #define RT5640_DSP_PATH2 0x2e 47997b0520SBard Liao #define RT5640_DIG_INF_DATA 0x2f 48997b0520SBard Liao /* Mixer - ADC */ 49997b0520SBard Liao #define RT5640_REC_L1_MIXER 0x3b 50997b0520SBard Liao #define RT5640_REC_L2_MIXER 0x3c 51997b0520SBard Liao #define RT5640_REC_R1_MIXER 0x3d 52997b0520SBard Liao #define RT5640_REC_R2_MIXER 0x3e 53997b0520SBard Liao /* Mixer - DAC */ 54997b0520SBard Liao #define RT5640_HPO_MIXER 0x45 55997b0520SBard Liao #define RT5640_SPK_L_MIXER 0x46 56997b0520SBard Liao #define RT5640_SPK_R_MIXER 0x47 57997b0520SBard Liao #define RT5640_SPO_L_MIXER 0x48 58997b0520SBard Liao #define RT5640_SPO_R_MIXER 0x49 59997b0520SBard Liao #define RT5640_SPO_CLSD_RATIO 0x4a 60997b0520SBard Liao #define RT5640_MONO_MIXER 0x4c 61997b0520SBard Liao #define RT5640_OUT_L1_MIXER 0x4d 62997b0520SBard Liao #define RT5640_OUT_L2_MIXER 0x4e 63997b0520SBard Liao #define RT5640_OUT_L3_MIXER 0x4f 64997b0520SBard Liao #define RT5640_OUT_R1_MIXER 0x50 65997b0520SBard Liao #define RT5640_OUT_R2_MIXER 0x51 66997b0520SBard Liao #define RT5640_OUT_R3_MIXER 0x52 67997b0520SBard Liao #define RT5640_LOUT_MIXER 0x53 68997b0520SBard Liao /* Power */ 69997b0520SBard Liao #define RT5640_PWR_DIG1 0x61 70997b0520SBard Liao #define RT5640_PWR_DIG2 0x62 71997b0520SBard Liao #define RT5640_PWR_ANLG1 0x63 72997b0520SBard Liao #define RT5640_PWR_ANLG2 0x64 73997b0520SBard Liao #define RT5640_PWR_MIXER 0x65 74997b0520SBard Liao #define RT5640_PWR_VOL 0x66 75997b0520SBard Liao /* Private Register Control */ 76997b0520SBard Liao #define RT5640_PRIV_INDEX 0x6a 77997b0520SBard Liao #define RT5640_PRIV_DATA 0x6c 78997b0520SBard Liao /* Format - ADC/DAC */ 79997b0520SBard Liao #define RT5640_I2S1_SDP 0x70 80997b0520SBard Liao #define RT5640_I2S2_SDP 0x71 81997b0520SBard Liao #define RT5640_ADDA_CLK1 0x73 82997b0520SBard Liao #define RT5640_ADDA_CLK2 0x74 83997b0520SBard Liao #define RT5640_DMIC 0x75 84997b0520SBard Liao /* Function - Analog */ 85997b0520SBard Liao #define RT5640_GLB_CLK 0x80 86997b0520SBard Liao #define RT5640_PLL_CTRL1 0x81 87997b0520SBard Liao #define RT5640_PLL_CTRL2 0x82 88997b0520SBard Liao #define RT5640_ASRC_1 0x83 89997b0520SBard Liao #define RT5640_ASRC_2 0x84 90997b0520SBard Liao #define RT5640_ASRC_3 0x85 91997b0520SBard Liao #define RT5640_ASRC_4 0x89 92997b0520SBard Liao #define RT5640_ASRC_5 0x8a 93997b0520SBard Liao #define RT5640_HP_OVCD 0x8b 94997b0520SBard Liao #define RT5640_CLS_D_OVCD 0x8c 95997b0520SBard Liao #define RT5640_CLS_D_OUT 0x8d 96997b0520SBard Liao #define RT5640_DEPOP_M1 0x8e 97997b0520SBard Liao #define RT5640_DEPOP_M2 0x8f 98997b0520SBard Liao #define RT5640_DEPOP_M3 0x90 99997b0520SBard Liao #define RT5640_CHARGE_PUMP 0x91 100997b0520SBard Liao #define RT5640_PV_DET_SPK_G 0x92 101997b0520SBard Liao #define RT5640_MICBIAS 0x93 102997b0520SBard Liao /* Function - Digital */ 103997b0520SBard Liao #define RT5640_EQ_CTRL1 0xb0 104997b0520SBard Liao #define RT5640_EQ_CTRL2 0xb1 105997b0520SBard Liao #define RT5640_WIND_FILTER 0xb2 106997b0520SBard Liao #define RT5640_DRC_AGC_1 0xb4 107997b0520SBard Liao #define RT5640_DRC_AGC_2 0xb5 108997b0520SBard Liao #define RT5640_DRC_AGC_3 0xb6 109997b0520SBard Liao #define RT5640_SVOL_ZC 0xb7 110997b0520SBard Liao #define RT5640_ANC_CTRL1 0xb8 111997b0520SBard Liao #define RT5640_ANC_CTRL2 0xb9 112997b0520SBard Liao #define RT5640_ANC_CTRL3 0xba 113997b0520SBard Liao #define RT5640_JD_CTRL 0xbb 114997b0520SBard Liao #define RT5640_ANC_JD 0xbc 115997b0520SBard Liao #define RT5640_IRQ_CTRL1 0xbd 116997b0520SBard Liao #define RT5640_IRQ_CTRL2 0xbe 117997b0520SBard Liao #define RT5640_INT_IRQ_ST 0xbf 118997b0520SBard Liao #define RT5640_GPIO_CTRL1 0xc0 119997b0520SBard Liao #define RT5640_GPIO_CTRL2 0xc1 120997b0520SBard Liao #define RT5640_GPIO_CTRL3 0xc2 121997b0520SBard Liao #define RT5640_DSP_CTRL1 0xc4 122997b0520SBard Liao #define RT5640_DSP_CTRL2 0xc5 123997b0520SBard Liao #define RT5640_DSP_CTRL3 0xc6 124997b0520SBard Liao #define RT5640_DSP_CTRL4 0xc7 125997b0520SBard Liao #define RT5640_PGM_REG_ARR1 0xc8 126997b0520SBard Liao #define RT5640_PGM_REG_ARR2 0xc9 127997b0520SBard Liao #define RT5640_PGM_REG_ARR3 0xca 128997b0520SBard Liao #define RT5640_PGM_REG_ARR4 0xcb 129997b0520SBard Liao #define RT5640_PGM_REG_ARR5 0xcc 130997b0520SBard Liao #define RT5640_SCB_FUNC 0xcd 131997b0520SBard Liao #define RT5640_SCB_CTRL 0xce 132997b0520SBard Liao #define RT5640_BASE_BACK 0xcf 133997b0520SBard Liao #define RT5640_MP3_PLUS1 0xd0 134997b0520SBard Liao #define RT5640_MP3_PLUS2 0xd1 135997b0520SBard Liao #define RT5640_3D_HP 0xd2 136997b0520SBard Liao #define RT5640_ADJ_HPF 0xd3 137997b0520SBard Liao #define RT5640_HP_CALIB_AMP_DET 0xd6 138997b0520SBard Liao #define RT5640_HP_CALIB2 0xd7 139997b0520SBard Liao #define RT5640_SV_ZCD1 0xd9 140997b0520SBard Liao #define RT5640_SV_ZCD2 0xda 141997b0520SBard Liao /* Dummy Register */ 142997b0520SBard Liao #define RT5640_DUMMY1 0xfa 143997b0520SBard Liao #define RT5640_DUMMY2 0xfb 144997b0520SBard Liao #define RT5640_DUMMY3 0xfc 145997b0520SBard Liao 146997b0520SBard Liao 147997b0520SBard Liao /* Index of Codec Private Register definition */ 1488210804bSHans de Goede #define RT5640_BIAS_CUR4 0x15 149246693baSBard Liao #define RT5640_CHPUMP_INT_REG1 0x24 150246693baSBard Liao #define RT5640_MAMP_INT_REG2 0x37 151997b0520SBard Liao #define RT5640_3D_SPK 0x63 152997b0520SBard Liao #define RT5640_WND_1 0x6c 153997b0520SBard Liao #define RT5640_WND_2 0x6d 154997b0520SBard Liao #define RT5640_WND_3 0x6e 155997b0520SBard Liao #define RT5640_WND_4 0x6f 156997b0520SBard Liao #define RT5640_WND_5 0x70 157997b0520SBard Liao #define RT5640_WND_8 0x73 158997b0520SBard Liao #define RT5640_DIP_SPK_INF 0x75 159246693baSBard Liao #define RT5640_HP_DCC_INT1 0x77 160997b0520SBard Liao #define RT5640_EQ_BW_LOP 0xa0 161997b0520SBard Liao #define RT5640_EQ_GN_LOP 0xa1 162997b0520SBard Liao #define RT5640_EQ_FC_BP1 0xa2 163997b0520SBard Liao #define RT5640_EQ_BW_BP1 0xa3 164997b0520SBard Liao #define RT5640_EQ_GN_BP1 0xa4 165997b0520SBard Liao #define RT5640_EQ_FC_BP2 0xa5 166997b0520SBard Liao #define RT5640_EQ_BW_BP2 0xa6 167997b0520SBard Liao #define RT5640_EQ_GN_BP2 0xa7 168997b0520SBard Liao #define RT5640_EQ_FC_BP3 0xa8 169997b0520SBard Liao #define RT5640_EQ_BW_BP3 0xa9 170997b0520SBard Liao #define RT5640_EQ_GN_BP3 0xaa 171997b0520SBard Liao #define RT5640_EQ_FC_BP4 0xab 172997b0520SBard Liao #define RT5640_EQ_BW_BP4 0xac 173997b0520SBard Liao #define RT5640_EQ_GN_BP4 0xad 174997b0520SBard Liao #define RT5640_EQ_FC_HIP1 0xae 175997b0520SBard Liao #define RT5640_EQ_GN_HIP1 0xaf 176997b0520SBard Liao #define RT5640_EQ_FC_HIP2 0xb0 177997b0520SBard Liao #define RT5640_EQ_BW_HIP2 0xb1 178997b0520SBard Liao #define RT5640_EQ_GN_HIP2 0xb2 179997b0520SBard Liao #define RT5640_EQ_PRE_VOL 0xb3 180997b0520SBard Liao #define RT5640_EQ_PST_VOL 0xb4 181997b0520SBard Liao 182997b0520SBard Liao /* global definition */ 183997b0520SBard Liao #define RT5640_L_MUTE (0x1 << 15) 184997b0520SBard Liao #define RT5640_L_MUTE_SFT 15 185997b0520SBard Liao #define RT5640_VOL_L_MUTE (0x1 << 14) 186997b0520SBard Liao #define RT5640_VOL_L_SFT 14 187997b0520SBard Liao #define RT5640_R_MUTE (0x1 << 7) 188997b0520SBard Liao #define RT5640_R_MUTE_SFT 7 189997b0520SBard Liao #define RT5640_VOL_R_MUTE (0x1 << 6) 190997b0520SBard Liao #define RT5640_VOL_R_SFT 6 191997b0520SBard Liao #define RT5640_L_VOL_MASK (0x3f << 8) 192997b0520SBard Liao #define RT5640_L_VOL_SFT 8 193997b0520SBard Liao #define RT5640_R_VOL_MASK (0x3f) 194997b0520SBard Liao #define RT5640_R_VOL_SFT 0 195997b0520SBard Liao 1968bfc6d2dSBard Liao /* SW Reset & Device ID (0x00) */ 1978bfc6d2dSBard Liao #define RT5640_ID_MASK (0x3 << 1) 1988bfc6d2dSBard Liao #define RT5640_ID_5639 (0x0 << 1) 1994eefa0d8SBard Liao #define RT5640_ID_5640 (0x2 << 1) 2008bfc6d2dSBard Liao #define RT5640_ID_5642 (0x3 << 1) 2018bfc6d2dSBard Liao 2028bfc6d2dSBard Liao 203997b0520SBard Liao /* IN1 and IN2 Control (0x0d) */ 204997b0520SBard Liao /* IN3 and IN4 Control (0x0e) */ 205997b0520SBard Liao #define RT5640_BST_SFT1 12 206997b0520SBard Liao #define RT5640_BST_SFT2 8 207997b0520SBard Liao #define RT5640_IN_DF1 (0x1 << 7) 208997b0520SBard Liao #define RT5640_IN_SFT1 7 209997b0520SBard Liao #define RT5640_IN_DF2 (0x1 << 6) 210997b0520SBard Liao #define RT5640_IN_SFT2 6 211997b0520SBard Liao 212997b0520SBard Liao /* INL and INR Volume Control (0x0f) */ 213997b0520SBard Liao #define RT5640_INL_SEL_MASK (0x1 << 15) 214997b0520SBard Liao #define RT5640_INL_SEL_SFT 15 215997b0520SBard Liao #define RT5640_INL_SEL_IN4P (0x0 << 15) 216997b0520SBard Liao #define RT5640_INL_SEL_MONOP (0x1 << 15) 217997b0520SBard Liao #define RT5640_INL_VOL_MASK (0x1f << 8) 218997b0520SBard Liao #define RT5640_INL_VOL_SFT 8 219997b0520SBard Liao #define RT5640_INR_SEL_MASK (0x1 << 7) 220997b0520SBard Liao #define RT5640_INR_SEL_SFT 7 221997b0520SBard Liao #define RT5640_INR_SEL_IN4N (0x0 << 7) 222997b0520SBard Liao #define RT5640_INR_SEL_MONON (0x1 << 7) 223997b0520SBard Liao #define RT5640_INR_VOL_MASK (0x1f) 224997b0520SBard Liao #define RT5640_INR_VOL_SFT 0 225997b0520SBard Liao 226997b0520SBard Liao /* DAC1 Digital Volume (0x19) */ 227997b0520SBard Liao #define RT5640_DAC_L1_VOL_MASK (0xff << 8) 228997b0520SBard Liao #define RT5640_DAC_L1_VOL_SFT 8 229997b0520SBard Liao #define RT5640_DAC_R1_VOL_MASK (0xff) 230997b0520SBard Liao #define RT5640_DAC_R1_VOL_SFT 0 231997b0520SBard Liao 232997b0520SBard Liao /* DAC2 Digital Volume (0x1a) */ 233997b0520SBard Liao #define RT5640_DAC_L2_VOL_MASK (0xff << 8) 234997b0520SBard Liao #define RT5640_DAC_L2_VOL_SFT 8 235997b0520SBard Liao #define RT5640_DAC_R2_VOL_MASK (0xff) 236997b0520SBard Liao #define RT5640_DAC_R2_VOL_SFT 0 237997b0520SBard Liao 238997b0520SBard Liao /* DAC2 Control (0x1b) */ 239997b0520SBard Liao #define RT5640_M_DAC_L2_VOL (0x1 << 13) 240997b0520SBard Liao #define RT5640_M_DAC_L2_VOL_SFT 13 241997b0520SBard Liao #define RT5640_M_DAC_R2_VOL (0x1 << 12) 242997b0520SBard Liao #define RT5640_M_DAC_R2_VOL_SFT 12 243997b0520SBard Liao 244997b0520SBard Liao /* ADC Digital Volume Control (0x1c) */ 245997b0520SBard Liao #define RT5640_ADC_L_VOL_MASK (0x7f << 8) 246997b0520SBard Liao #define RT5640_ADC_L_VOL_SFT 8 247997b0520SBard Liao #define RT5640_ADC_R_VOL_MASK (0x7f) 248997b0520SBard Liao #define RT5640_ADC_R_VOL_SFT 0 249997b0520SBard Liao 250997b0520SBard Liao /* Mono ADC Digital Volume Control (0x1d) */ 251997b0520SBard Liao #define RT5640_MONO_ADC_L_VOL_MASK (0x7f << 8) 252997b0520SBard Liao #define RT5640_MONO_ADC_L_VOL_SFT 8 253997b0520SBard Liao #define RT5640_MONO_ADC_R_VOL_MASK (0x7f) 254997b0520SBard Liao #define RT5640_MONO_ADC_R_VOL_SFT 0 255997b0520SBard Liao 256997b0520SBard Liao /* ADC Boost Volume Control (0x1e) */ 257997b0520SBard Liao #define RT5640_ADC_L_BST_MASK (0x3 << 14) 258997b0520SBard Liao #define RT5640_ADC_L_BST_SFT 14 259997b0520SBard Liao #define RT5640_ADC_R_BST_MASK (0x3 << 12) 260997b0520SBard Liao #define RT5640_ADC_R_BST_SFT 12 261997b0520SBard Liao #define RT5640_ADC_COMP_MASK (0x3 << 10) 262997b0520SBard Liao #define RT5640_ADC_COMP_SFT 10 263997b0520SBard Liao 264997b0520SBard Liao /* Stereo ADC Mixer Control (0x27) */ 265997b0520SBard Liao #define RT5640_M_ADC_L1 (0x1 << 14) 266997b0520SBard Liao #define RT5640_M_ADC_L1_SFT 14 267997b0520SBard Liao #define RT5640_M_ADC_L2 (0x1 << 13) 268997b0520SBard Liao #define RT5640_M_ADC_L2_SFT 13 269997b0520SBard Liao #define RT5640_ADC_1_SRC_MASK (0x1 << 12) 270997b0520SBard Liao #define RT5640_ADC_1_SRC_SFT 12 271997b0520SBard Liao #define RT5640_ADC_1_SRC_ADC (0x1 << 12) 272997b0520SBard Liao #define RT5640_ADC_1_SRC_DACMIX (0x0 << 12) 273997b0520SBard Liao #define RT5640_ADC_2_SRC_MASK (0x3 << 10) 274997b0520SBard Liao #define RT5640_ADC_2_SRC_SFT 10 275997b0520SBard Liao #define RT5640_ADC_2_SRC_DMIC1 (0x0 << 10) 276997b0520SBard Liao #define RT5640_ADC_2_SRC_DMIC2 (0x1 << 10) 277997b0520SBard Liao #define RT5640_ADC_2_SRC_DACMIX (0x2 << 10) 278997b0520SBard Liao #define RT5640_M_ADC_R1 (0x1 << 6) 279997b0520SBard Liao #define RT5640_M_ADC_R1_SFT 6 280997b0520SBard Liao #define RT5640_M_ADC_R2 (0x1 << 5) 281997b0520SBard Liao #define RT5640_M_ADC_R2_SFT 5 282997b0520SBard Liao 283997b0520SBard Liao /* Mono ADC Mixer Control (0x28) */ 284997b0520SBard Liao #define RT5640_M_MONO_ADC_L1 (0x1 << 14) 285997b0520SBard Liao #define RT5640_M_MONO_ADC_L1_SFT 14 286997b0520SBard Liao #define RT5640_M_MONO_ADC_L2 (0x1 << 13) 287997b0520SBard Liao #define RT5640_M_MONO_ADC_L2_SFT 13 288997b0520SBard Liao #define RT5640_MONO_ADC_L1_SRC_MASK (0x1 << 12) 289997b0520SBard Liao #define RT5640_MONO_ADC_L1_SRC_SFT 12 290997b0520SBard Liao #define RT5640_MONO_ADC_L1_SRC_DACMIXL (0x0 << 12) 291997b0520SBard Liao #define RT5640_MONO_ADC_L1_SRC_ADCL (0x1 << 12) 292997b0520SBard Liao #define RT5640_MONO_ADC_L2_SRC_MASK (0x3 << 10) 293997b0520SBard Liao #define RT5640_MONO_ADC_L2_SRC_SFT 10 294997b0520SBard Liao #define RT5640_MONO_ADC_L2_SRC_DMIC_L1 (0x0 << 10) 295997b0520SBard Liao #define RT5640_MONO_ADC_L2_SRC_DMIC_L2 (0x1 << 10) 296997b0520SBard Liao #define RT5640_MONO_ADC_L2_SRC_DACMIXL (0x2 << 10) 297997b0520SBard Liao #define RT5640_M_MONO_ADC_R1 (0x1 << 6) 298997b0520SBard Liao #define RT5640_M_MONO_ADC_R1_SFT 6 299997b0520SBard Liao #define RT5640_M_MONO_ADC_R2 (0x1 << 5) 300997b0520SBard Liao #define RT5640_M_MONO_ADC_R2_SFT 5 301997b0520SBard Liao #define RT5640_MONO_ADC_R1_SRC_MASK (0x1 << 4) 302997b0520SBard Liao #define RT5640_MONO_ADC_R1_SRC_SFT 4 303997b0520SBard Liao #define RT5640_MONO_ADC_R1_SRC_ADCR (0x1 << 4) 304997b0520SBard Liao #define RT5640_MONO_ADC_R1_SRC_DACMIXR (0x0 << 4) 305997b0520SBard Liao #define RT5640_MONO_ADC_R2_SRC_MASK (0x3 << 2) 306997b0520SBard Liao #define RT5640_MONO_ADC_R2_SRC_SFT 2 307997b0520SBard Liao #define RT5640_MONO_ADC_R2_SRC_DMIC_R1 (0x0 << 2) 308997b0520SBard Liao #define RT5640_MONO_ADC_R2_SRC_DMIC_R2 (0x1 << 2) 309997b0520SBard Liao #define RT5640_MONO_ADC_R2_SRC_DACMIXR (0x2 << 2) 310997b0520SBard Liao 311997b0520SBard Liao /* ADC Mixer to DAC Mixer Control (0x29) */ 312997b0520SBard Liao #define RT5640_M_ADCMIX_L (0x1 << 15) 313997b0520SBard Liao #define RT5640_M_ADCMIX_L_SFT 15 314997b0520SBard Liao #define RT5640_M_IF1_DAC_L (0x1 << 14) 315997b0520SBard Liao #define RT5640_M_IF1_DAC_L_SFT 14 316997b0520SBard Liao #define RT5640_M_ADCMIX_R (0x1 << 7) 317997b0520SBard Liao #define RT5640_M_ADCMIX_R_SFT 7 318997b0520SBard Liao #define RT5640_M_IF1_DAC_R (0x1 << 6) 319997b0520SBard Liao #define RT5640_M_IF1_DAC_R_SFT 6 320997b0520SBard Liao 321997b0520SBard Liao /* Stereo DAC Mixer Control (0x2a) */ 322997b0520SBard Liao #define RT5640_M_DAC_L1 (0x1 << 14) 323997b0520SBard Liao #define RT5640_M_DAC_L1_SFT 14 324997b0520SBard Liao #define RT5640_DAC_L1_STO_L_VOL_MASK (0x1 << 13) 325997b0520SBard Liao #define RT5640_DAC_L1_STO_L_VOL_SFT 13 326997b0520SBard Liao #define RT5640_M_DAC_L2 (0x1 << 12) 327997b0520SBard Liao #define RT5640_M_DAC_L2_SFT 12 328997b0520SBard Liao #define RT5640_DAC_L2_STO_L_VOL_MASK (0x1 << 11) 329997b0520SBard Liao #define RT5640_DAC_L2_STO_L_VOL_SFT 11 330997b0520SBard Liao #define RT5640_M_ANC_DAC_L (0x1 << 10) 331997b0520SBard Liao #define RT5640_M_ANC_DAC_L_SFT 10 332997b0520SBard Liao #define RT5640_M_DAC_R1 (0x1 << 6) 333997b0520SBard Liao #define RT5640_M_DAC_R1_SFT 6 334997b0520SBard Liao #define RT5640_DAC_R1_STO_R_VOL_MASK (0x1 << 5) 335997b0520SBard Liao #define RT5640_DAC_R1_STO_R_VOL_SFT 5 336997b0520SBard Liao #define RT5640_M_DAC_R2 (0x1 << 4) 337997b0520SBard Liao #define RT5640_M_DAC_R2_SFT 4 338997b0520SBard Liao #define RT5640_DAC_R2_STO_R_VOL_MASK (0x1 << 3) 339997b0520SBard Liao #define RT5640_DAC_R2_STO_R_VOL_SFT 3 340997b0520SBard Liao #define RT5640_M_ANC_DAC_R (0x1 << 2) 341997b0520SBard Liao #define RT5640_M_ANC_DAC_R_SFT 2 342997b0520SBard Liao 343997b0520SBard Liao /* Mono DAC Mixer Control (0x2b) */ 344997b0520SBard Liao #define RT5640_M_DAC_L1_MONO_L (0x1 << 14) 345997b0520SBard Liao #define RT5640_M_DAC_L1_MONO_L_SFT 14 346997b0520SBard Liao #define RT5640_DAC_L1_MONO_L_VOL_MASK (0x1 << 13) 347997b0520SBard Liao #define RT5640_DAC_L1_MONO_L_VOL_SFT 13 348997b0520SBard Liao #define RT5640_M_DAC_L2_MONO_L (0x1 << 12) 349997b0520SBard Liao #define RT5640_M_DAC_L2_MONO_L_SFT 12 350997b0520SBard Liao #define RT5640_DAC_L2_MONO_L_VOL_MASK (0x1 << 11) 351997b0520SBard Liao #define RT5640_DAC_L2_MONO_L_VOL_SFT 11 352997b0520SBard Liao #define RT5640_M_DAC_R2_MONO_L (0x1 << 10) 353997b0520SBard Liao #define RT5640_M_DAC_R2_MONO_L_SFT 10 354997b0520SBard Liao #define RT5640_DAC_R2_MONO_L_VOL_MASK (0x1 << 9) 355997b0520SBard Liao #define RT5640_DAC_R2_MONO_L_VOL_SFT 9 356997b0520SBard Liao #define RT5640_M_DAC_R1_MONO_R (0x1 << 6) 357997b0520SBard Liao #define RT5640_M_DAC_R1_MONO_R_SFT 6 358997b0520SBard Liao #define RT5640_DAC_R1_MONO_R_VOL_MASK (0x1 << 5) 359997b0520SBard Liao #define RT5640_DAC_R1_MONO_R_VOL_SFT 5 360997b0520SBard Liao #define RT5640_M_DAC_R2_MONO_R (0x1 << 4) 361997b0520SBard Liao #define RT5640_M_DAC_R2_MONO_R_SFT 4 362997b0520SBard Liao #define RT5640_DAC_R2_MONO_R_VOL_MASK (0x1 << 3) 363997b0520SBard Liao #define RT5640_DAC_R2_MONO_R_VOL_SFT 3 364997b0520SBard Liao #define RT5640_M_DAC_L2_MONO_R (0x1 << 2) 365997b0520SBard Liao #define RT5640_M_DAC_L2_MONO_R_SFT 2 366997b0520SBard Liao #define RT5640_DAC_L2_MONO_R_VOL_MASK (0x1 << 1) 367997b0520SBard Liao #define RT5640_DAC_L2_MONO_R_VOL_SFT 1 368997b0520SBard Liao 369997b0520SBard Liao /* Digital Mixer Control (0x2c) */ 370997b0520SBard Liao #define RT5640_M_STO_L_DAC_L (0x1 << 15) 371997b0520SBard Liao #define RT5640_M_STO_L_DAC_L_SFT 15 372997b0520SBard Liao #define RT5640_STO_L_DAC_L_VOL_MASK (0x1 << 14) 373997b0520SBard Liao #define RT5640_STO_L_DAC_L_VOL_SFT 14 374997b0520SBard Liao #define RT5640_M_DAC_L2_DAC_L (0x1 << 13) 375997b0520SBard Liao #define RT5640_M_DAC_L2_DAC_L_SFT 13 376997b0520SBard Liao #define RT5640_DAC_L2_DAC_L_VOL_MASK (0x1 << 12) 377997b0520SBard Liao #define RT5640_DAC_L2_DAC_L_VOL_SFT 12 378997b0520SBard Liao #define RT5640_M_STO_R_DAC_R (0x1 << 11) 379997b0520SBard Liao #define RT5640_M_STO_R_DAC_R_SFT 11 380997b0520SBard Liao #define RT5640_STO_R_DAC_R_VOL_MASK (0x1 << 10) 381997b0520SBard Liao #define RT5640_STO_R_DAC_R_VOL_SFT 10 382997b0520SBard Liao #define RT5640_M_DAC_R2_DAC_R (0x1 << 9) 383997b0520SBard Liao #define RT5640_M_DAC_R2_DAC_R_SFT 9 384997b0520SBard Liao #define RT5640_DAC_R2_DAC_R_VOL_MASK (0x1 << 8) 385997b0520SBard Liao #define RT5640_DAC_R2_DAC_R_VOL_SFT 8 386997b0520SBard Liao 387997b0520SBard Liao /* DSP Path Control 1 (0x2d) */ 388997b0520SBard Liao #define RT5640_RXDP_SRC_MASK (0x1 << 15) 389997b0520SBard Liao #define RT5640_RXDP_SRC_SFT 15 390997b0520SBard Liao #define RT5640_RXDP_SRC_NOR (0x0 << 15) 391997b0520SBard Liao #define RT5640_RXDP_SRC_DIV3 (0x1 << 15) 392997b0520SBard Liao #define RT5640_TXDP_SRC_MASK (0x1 << 14) 393997b0520SBard Liao #define RT5640_TXDP_SRC_SFT 14 394997b0520SBard Liao #define RT5640_TXDP_SRC_NOR (0x0 << 14) 395997b0520SBard Liao #define RT5640_TXDP_SRC_DIV3 (0x1 << 14) 396997b0520SBard Liao 397997b0520SBard Liao /* DSP Path Control 2 (0x2e) */ 398997b0520SBard Liao #define RT5640_DAC_L2_SEL_MASK (0x3 << 14) 399997b0520SBard Liao #define RT5640_DAC_L2_SEL_SFT 14 400997b0520SBard Liao #define RT5640_DAC_L2_SEL_IF2 (0x0 << 14) 401997b0520SBard Liao #define RT5640_DAC_L2_SEL_IF3 (0x1 << 14) 402997b0520SBard Liao #define RT5640_DAC_L2_SEL_TXDC (0x2 << 14) 403997b0520SBard Liao #define RT5640_DAC_L2_SEL_BASS (0x3 << 14) 404997b0520SBard Liao #define RT5640_DAC_R2_SEL_MASK (0x3 << 12) 405997b0520SBard Liao #define RT5640_DAC_R2_SEL_SFT 12 406997b0520SBard Liao #define RT5640_DAC_R2_SEL_IF2 (0x0 << 12) 407997b0520SBard Liao #define RT5640_DAC_R2_SEL_IF3 (0x1 << 12) 408997b0520SBard Liao #define RT5640_DAC_R2_SEL_TXDC (0x2 << 12) 409997b0520SBard Liao #define RT5640_IF2_ADC_L_SEL_MASK (0x1 << 11) 410997b0520SBard Liao #define RT5640_IF2_ADC_L_SEL_SFT 11 411997b0520SBard Liao #define RT5640_IF2_ADC_L_SEL_TXDP (0x0 << 11) 412997b0520SBard Liao #define RT5640_IF2_ADC_L_SEL_PASS (0x1 << 11) 413997b0520SBard Liao #define RT5640_IF2_ADC_R_SEL_MASK (0x1 << 10) 414997b0520SBard Liao #define RT5640_IF2_ADC_R_SEL_SFT 10 415997b0520SBard Liao #define RT5640_IF2_ADC_R_SEL_TXDP (0x0 << 10) 416997b0520SBard Liao #define RT5640_IF2_ADC_R_SEL_PASS (0x1 << 10) 417997b0520SBard Liao #define RT5640_RXDC_SEL_MASK (0x3 << 8) 418997b0520SBard Liao #define RT5640_RXDC_SEL_SFT 8 419997b0520SBard Liao #define RT5640_RXDC_SEL_NOR (0x0 << 8) 420997b0520SBard Liao #define RT5640_RXDC_SEL_L2R (0x1 << 8) 421997b0520SBard Liao #define RT5640_RXDC_SEL_R2L (0x2 << 8) 422997b0520SBard Liao #define RT5640_RXDC_SEL_SWAP (0x3 << 8) 423997b0520SBard Liao #define RT5640_RXDP_SEL_MASK (0x3 << 6) 424997b0520SBard Liao #define RT5640_RXDP_SEL_SFT 6 425997b0520SBard Liao #define RT5640_RXDP_SEL_NOR (0x0 << 6) 426997b0520SBard Liao #define RT5640_RXDP_SEL_L2R (0x1 << 6) 427997b0520SBard Liao #define RT5640_RXDP_SEL_R2L (0x2 << 6) 428997b0520SBard Liao #define RT5640_RXDP_SEL_SWAP (0x3 << 6) 429997b0520SBard Liao #define RT5640_TXDC_SEL_MASK (0x3 << 4) 430997b0520SBard Liao #define RT5640_TXDC_SEL_SFT 4 431997b0520SBard Liao #define RT5640_TXDC_SEL_NOR (0x0 << 4) 432997b0520SBard Liao #define RT5640_TXDC_SEL_L2R (0x1 << 4) 433997b0520SBard Liao #define RT5640_TXDC_SEL_R2L (0x2 << 4) 434997b0520SBard Liao #define RT5640_TXDC_SEL_SWAP (0x3 << 4) 435997b0520SBard Liao #define RT5640_TXDP_SEL_MASK (0x3 << 2) 436997b0520SBard Liao #define RT5640_TXDP_SEL_SFT 2 437997b0520SBard Liao #define RT5640_TXDP_SEL_NOR (0x0 << 2) 438997b0520SBard Liao #define RT5640_TXDP_SEL_L2R (0x1 << 2) 439997b0520SBard Liao #define RT5640_TXDP_SEL_R2L (0x2 << 2) 440997b0520SBard Liao #define RT5640_TRXDP_SEL_SWAP (0x3 << 2) 441997b0520SBard Liao 442997b0520SBard Liao /* Digital Interface Data Control (0x2f) */ 443997b0520SBard Liao #define RT5640_IF1_DAC_SEL_MASK (0x3 << 14) 444997b0520SBard Liao #define RT5640_IF1_DAC_SEL_SFT 14 445997b0520SBard Liao #define RT5640_IF1_DAC_SEL_NOR (0x0 << 14) 446653aa464SSugar Zhang #define RT5640_IF1_DAC_SEL_SWAP (0x1 << 14) 447653aa464SSugar Zhang #define RT5640_IF1_DAC_SEL_L2R (0x2 << 14) 448653aa464SSugar Zhang #define RT5640_IF1_DAC_SEL_R2L (0x3 << 14) 449997b0520SBard Liao #define RT5640_IF1_ADC_SEL_MASK (0x3 << 12) 450997b0520SBard Liao #define RT5640_IF1_ADC_SEL_SFT 12 451997b0520SBard Liao #define RT5640_IF1_ADC_SEL_NOR (0x0 << 12) 452653aa464SSugar Zhang #define RT5640_IF1_ADC_SEL_SWAP (0x1 << 12) 453653aa464SSugar Zhang #define RT5640_IF1_ADC_SEL_L2R (0x2 << 12) 454653aa464SSugar Zhang #define RT5640_IF1_ADC_SEL_R2L (0x3 << 12) 455997b0520SBard Liao #define RT5640_IF2_DAC_SEL_MASK (0x3 << 10) 456997b0520SBard Liao #define RT5640_IF2_DAC_SEL_SFT 10 457997b0520SBard Liao #define RT5640_IF2_DAC_SEL_NOR (0x0 << 10) 458653aa464SSugar Zhang #define RT5640_IF2_DAC_SEL_SWAP (0x1 << 10) 459653aa464SSugar Zhang #define RT5640_IF2_DAC_SEL_L2R (0x2 << 10) 460653aa464SSugar Zhang #define RT5640_IF2_DAC_SEL_R2L (0x3 << 10) 461997b0520SBard Liao #define RT5640_IF2_ADC_SEL_MASK (0x3 << 8) 462997b0520SBard Liao #define RT5640_IF2_ADC_SEL_SFT 8 463997b0520SBard Liao #define RT5640_IF2_ADC_SEL_NOR (0x0 << 8) 464653aa464SSugar Zhang #define RT5640_IF2_ADC_SEL_SWAP (0x1 << 8) 465653aa464SSugar Zhang #define RT5640_IF2_ADC_SEL_L2R (0x2 << 8) 466653aa464SSugar Zhang #define RT5640_IF2_ADC_SEL_R2L (0x3 << 8) 467997b0520SBard Liao #define RT5640_IF3_DAC_SEL_MASK (0x3 << 6) 468997b0520SBard Liao #define RT5640_IF3_DAC_SEL_SFT 6 469997b0520SBard Liao #define RT5640_IF3_DAC_SEL_NOR (0x0 << 6) 470653aa464SSugar Zhang #define RT5640_IF3_DAC_SEL_SWAP (0x1 << 6) 471653aa464SSugar Zhang #define RT5640_IF3_DAC_SEL_L2R (0x2 << 6) 472653aa464SSugar Zhang #define RT5640_IF3_DAC_SEL_R2L (0x3 << 6) 473997b0520SBard Liao #define RT5640_IF3_ADC_SEL_MASK (0x3 << 4) 474997b0520SBard Liao #define RT5640_IF3_ADC_SEL_SFT 4 475997b0520SBard Liao #define RT5640_IF3_ADC_SEL_NOR (0x0 << 4) 476653aa464SSugar Zhang #define RT5640_IF3_ADC_SEL_SWAP (0x1 << 4) 477653aa464SSugar Zhang #define RT5640_IF3_ADC_SEL_L2R (0x2 << 4) 478653aa464SSugar Zhang #define RT5640_IF3_ADC_SEL_R2L (0x3 << 4) 479997b0520SBard Liao 480997b0520SBard Liao /* REC Left Mixer Control 1 (0x3b) */ 481997b0520SBard Liao #define RT5640_G_HP_L_RM_L_MASK (0x7 << 13) 482997b0520SBard Liao #define RT5640_G_HP_L_RM_L_SFT 13 483997b0520SBard Liao #define RT5640_G_IN_L_RM_L_MASK (0x7 << 10) 484997b0520SBard Liao #define RT5640_G_IN_L_RM_L_SFT 10 485997b0520SBard Liao #define RT5640_G_BST4_RM_L_MASK (0x7 << 7) 486997b0520SBard Liao #define RT5640_G_BST4_RM_L_SFT 7 487997b0520SBard Liao #define RT5640_G_BST3_RM_L_MASK (0x7 << 4) 488997b0520SBard Liao #define RT5640_G_BST3_RM_L_SFT 4 489997b0520SBard Liao #define RT5640_G_BST2_RM_L_MASK (0x7 << 1) 490997b0520SBard Liao #define RT5640_G_BST2_RM_L_SFT 1 491997b0520SBard Liao 492997b0520SBard Liao /* REC Left Mixer Control 2 (0x3c) */ 493997b0520SBard Liao #define RT5640_G_BST1_RM_L_MASK (0x7 << 13) 494997b0520SBard Liao #define RT5640_G_BST1_RM_L_SFT 13 495997b0520SBard Liao #define RT5640_G_OM_L_RM_L_MASK (0x7 << 10) 496997b0520SBard Liao #define RT5640_G_OM_L_RM_L_SFT 10 497997b0520SBard Liao #define RT5640_M_HP_L_RM_L (0x1 << 6) 498997b0520SBard Liao #define RT5640_M_HP_L_RM_L_SFT 6 499997b0520SBard Liao #define RT5640_M_IN_L_RM_L (0x1 << 5) 500997b0520SBard Liao #define RT5640_M_IN_L_RM_L_SFT 5 501997b0520SBard Liao #define RT5640_M_BST4_RM_L (0x1 << 4) 502997b0520SBard Liao #define RT5640_M_BST4_RM_L_SFT 4 503997b0520SBard Liao #define RT5640_M_BST3_RM_L (0x1 << 3) 504997b0520SBard Liao #define RT5640_M_BST3_RM_L_SFT 3 505997b0520SBard Liao #define RT5640_M_BST2_RM_L (0x1 << 2) 506997b0520SBard Liao #define RT5640_M_BST2_RM_L_SFT 2 507997b0520SBard Liao #define RT5640_M_BST1_RM_L (0x1 << 1) 508997b0520SBard Liao #define RT5640_M_BST1_RM_L_SFT 1 509997b0520SBard Liao #define RT5640_M_OM_L_RM_L (0x1) 510997b0520SBard Liao #define RT5640_M_OM_L_RM_L_SFT 0 511997b0520SBard Liao 512997b0520SBard Liao /* REC Right Mixer Control 1 (0x3d) */ 513997b0520SBard Liao #define RT5640_G_HP_R_RM_R_MASK (0x7 << 13) 514997b0520SBard Liao #define RT5640_G_HP_R_RM_R_SFT 13 515997b0520SBard Liao #define RT5640_G_IN_R_RM_R_MASK (0x7 << 10) 516997b0520SBard Liao #define RT5640_G_IN_R_RM_R_SFT 10 517997b0520SBard Liao #define RT5640_G_BST4_RM_R_MASK (0x7 << 7) 518997b0520SBard Liao #define RT5640_G_BST4_RM_R_SFT 7 519997b0520SBard Liao #define RT5640_G_BST3_RM_R_MASK (0x7 << 4) 520997b0520SBard Liao #define RT5640_G_BST3_RM_R_SFT 4 521997b0520SBard Liao #define RT5640_G_BST2_RM_R_MASK (0x7 << 1) 522997b0520SBard Liao #define RT5640_G_BST2_RM_R_SFT 1 523997b0520SBard Liao 524997b0520SBard Liao /* REC Right Mixer Control 2 (0x3e) */ 525997b0520SBard Liao #define RT5640_G_BST1_RM_R_MASK (0x7 << 13) 526997b0520SBard Liao #define RT5640_G_BST1_RM_R_SFT 13 527997b0520SBard Liao #define RT5640_G_OM_R_RM_R_MASK (0x7 << 10) 528997b0520SBard Liao #define RT5640_G_OM_R_RM_R_SFT 10 529997b0520SBard Liao #define RT5640_M_HP_R_RM_R (0x1 << 6) 530997b0520SBard Liao #define RT5640_M_HP_R_RM_R_SFT 6 531997b0520SBard Liao #define RT5640_M_IN_R_RM_R (0x1 << 5) 532997b0520SBard Liao #define RT5640_M_IN_R_RM_R_SFT 5 533997b0520SBard Liao #define RT5640_M_BST4_RM_R (0x1 << 4) 534997b0520SBard Liao #define RT5640_M_BST4_RM_R_SFT 4 535997b0520SBard Liao #define RT5640_M_BST3_RM_R (0x1 << 3) 536997b0520SBard Liao #define RT5640_M_BST3_RM_R_SFT 3 537997b0520SBard Liao #define RT5640_M_BST2_RM_R (0x1 << 2) 538997b0520SBard Liao #define RT5640_M_BST2_RM_R_SFT 2 539997b0520SBard Liao #define RT5640_M_BST1_RM_R (0x1 << 1) 540997b0520SBard Liao #define RT5640_M_BST1_RM_R_SFT 1 541997b0520SBard Liao #define RT5640_M_OM_R_RM_R (0x1) 542997b0520SBard Liao #define RT5640_M_OM_R_RM_R_SFT 0 543997b0520SBard Liao 544997b0520SBard Liao /* HPMIX Control (0x45) */ 545997b0520SBard Liao #define RT5640_M_DAC2_HM (0x1 << 15) 546997b0520SBard Liao #define RT5640_M_DAC2_HM_SFT 15 547997b0520SBard Liao #define RT5640_M_DAC1_HM (0x1 << 14) 548997b0520SBard Liao #define RT5640_M_DAC1_HM_SFT 14 549997b0520SBard Liao #define RT5640_M_HPVOL_HM (0x1 << 13) 550997b0520SBard Liao #define RT5640_M_HPVOL_HM_SFT 13 551997b0520SBard Liao #define RT5640_G_HPOMIX_MASK (0x1 << 12) 552997b0520SBard Liao #define RT5640_G_HPOMIX_SFT 12 553997b0520SBard Liao 554997b0520SBard Liao /* SPK Left Mixer Control (0x46) */ 555997b0520SBard Liao #define RT5640_G_RM_L_SM_L_MASK (0x3 << 14) 556997b0520SBard Liao #define RT5640_G_RM_L_SM_L_SFT 14 557997b0520SBard Liao #define RT5640_G_IN_L_SM_L_MASK (0x3 << 12) 558997b0520SBard Liao #define RT5640_G_IN_L_SM_L_SFT 12 559997b0520SBard Liao #define RT5640_G_DAC_L1_SM_L_MASK (0x3 << 10) 560997b0520SBard Liao #define RT5640_G_DAC_L1_SM_L_SFT 10 561997b0520SBard Liao #define RT5640_G_DAC_L2_SM_L_MASK (0x3 << 8) 562997b0520SBard Liao #define RT5640_G_DAC_L2_SM_L_SFT 8 563997b0520SBard Liao #define RT5640_G_OM_L_SM_L_MASK (0x3 << 6) 564997b0520SBard Liao #define RT5640_G_OM_L_SM_L_SFT 6 565997b0520SBard Liao #define RT5640_M_RM_L_SM_L (0x1 << 5) 566997b0520SBard Liao #define RT5640_M_RM_L_SM_L_SFT 5 567997b0520SBard Liao #define RT5640_M_IN_L_SM_L (0x1 << 4) 568997b0520SBard Liao #define RT5640_M_IN_L_SM_L_SFT 4 569997b0520SBard Liao #define RT5640_M_DAC_L1_SM_L (0x1 << 3) 570997b0520SBard Liao #define RT5640_M_DAC_L1_SM_L_SFT 3 571997b0520SBard Liao #define RT5640_M_DAC_L2_SM_L (0x1 << 2) 572997b0520SBard Liao #define RT5640_M_DAC_L2_SM_L_SFT 2 573997b0520SBard Liao #define RT5640_M_OM_L_SM_L (0x1 << 1) 574997b0520SBard Liao #define RT5640_M_OM_L_SM_L_SFT 1 575997b0520SBard Liao 576997b0520SBard Liao /* SPK Right Mixer Control (0x47) */ 577997b0520SBard Liao #define RT5640_G_RM_R_SM_R_MASK (0x3 << 14) 578997b0520SBard Liao #define RT5640_G_RM_R_SM_R_SFT 14 579997b0520SBard Liao #define RT5640_G_IN_R_SM_R_MASK (0x3 << 12) 580997b0520SBard Liao #define RT5640_G_IN_R_SM_R_SFT 12 581997b0520SBard Liao #define RT5640_G_DAC_R1_SM_R_MASK (0x3 << 10) 582997b0520SBard Liao #define RT5640_G_DAC_R1_SM_R_SFT 10 583997b0520SBard Liao #define RT5640_G_DAC_R2_SM_R_MASK (0x3 << 8) 584997b0520SBard Liao #define RT5640_G_DAC_R2_SM_R_SFT 8 585997b0520SBard Liao #define RT5640_G_OM_R_SM_R_MASK (0x3 << 6) 586997b0520SBard Liao #define RT5640_G_OM_R_SM_R_SFT 6 587997b0520SBard Liao #define RT5640_M_RM_R_SM_R (0x1 << 5) 588997b0520SBard Liao #define RT5640_M_RM_R_SM_R_SFT 5 589997b0520SBard Liao #define RT5640_M_IN_R_SM_R (0x1 << 4) 590997b0520SBard Liao #define RT5640_M_IN_R_SM_R_SFT 4 591997b0520SBard Liao #define RT5640_M_DAC_R1_SM_R (0x1 << 3) 592997b0520SBard Liao #define RT5640_M_DAC_R1_SM_R_SFT 3 593997b0520SBard Liao #define RT5640_M_DAC_R2_SM_R (0x1 << 2) 594997b0520SBard Liao #define RT5640_M_DAC_R2_SM_R_SFT 2 595997b0520SBard Liao #define RT5640_M_OM_R_SM_R (0x1 << 1) 596997b0520SBard Liao #define RT5640_M_OM_R_SM_R_SFT 1 597997b0520SBard Liao 598997b0520SBard Liao /* SPOLMIX Control (0x48) */ 599997b0520SBard Liao #define RT5640_M_DAC_R1_SPM_L (0x1 << 15) 600997b0520SBard Liao #define RT5640_M_DAC_R1_SPM_L_SFT 15 601997b0520SBard Liao #define RT5640_M_DAC_L1_SPM_L (0x1 << 14) 602997b0520SBard Liao #define RT5640_M_DAC_L1_SPM_L_SFT 14 603997b0520SBard Liao #define RT5640_M_SV_R_SPM_L (0x1 << 13) 604997b0520SBard Liao #define RT5640_M_SV_R_SPM_L_SFT 13 605997b0520SBard Liao #define RT5640_M_SV_L_SPM_L (0x1 << 12) 606997b0520SBard Liao #define RT5640_M_SV_L_SPM_L_SFT 12 607997b0520SBard Liao #define RT5640_M_BST1_SPM_L (0x1 << 11) 608997b0520SBard Liao #define RT5640_M_BST1_SPM_L_SFT 11 609997b0520SBard Liao 610997b0520SBard Liao /* SPORMIX Control (0x49) */ 611997b0520SBard Liao #define RT5640_M_DAC_R1_SPM_R (0x1 << 13) 612997b0520SBard Liao #define RT5640_M_DAC_R1_SPM_R_SFT 13 613997b0520SBard Liao #define RT5640_M_SV_R_SPM_R (0x1 << 12) 614997b0520SBard Liao #define RT5640_M_SV_R_SPM_R_SFT 12 615997b0520SBard Liao #define RT5640_M_BST1_SPM_R (0x1 << 11) 616997b0520SBard Liao #define RT5640_M_BST1_SPM_R_SFT 11 617997b0520SBard Liao 618997b0520SBard Liao /* SPOLMIX / SPORMIX Ratio Control (0x4a) */ 619997b0520SBard Liao #define RT5640_SPO_CLSD_RATIO_MASK (0x7) 620997b0520SBard Liao #define RT5640_SPO_CLSD_RATIO_SFT 0 621997b0520SBard Liao 622997b0520SBard Liao /* Mono Output Mixer Control (0x4c) */ 623997b0520SBard Liao #define RT5640_M_DAC_R2_MM (0x1 << 15) 624997b0520SBard Liao #define RT5640_M_DAC_R2_MM_SFT 15 625997b0520SBard Liao #define RT5640_M_DAC_L2_MM (0x1 << 14) 626997b0520SBard Liao #define RT5640_M_DAC_L2_MM_SFT 14 627997b0520SBard Liao #define RT5640_M_OV_R_MM (0x1 << 13) 628997b0520SBard Liao #define RT5640_M_OV_R_MM_SFT 13 629997b0520SBard Liao #define RT5640_M_OV_L_MM (0x1 << 12) 630997b0520SBard Liao #define RT5640_M_OV_L_MM_SFT 12 631997b0520SBard Liao #define RT5640_M_BST1_MM (0x1 << 11) 632997b0520SBard Liao #define RT5640_M_BST1_MM_SFT 11 633997b0520SBard Liao #define RT5640_G_MONOMIX_MASK (0x1 << 10) 634997b0520SBard Liao #define RT5640_G_MONOMIX_SFT 10 635997b0520SBard Liao 636997b0520SBard Liao /* Output Left Mixer Control 1 (0x4d) */ 637997b0520SBard Liao #define RT5640_G_BST3_OM_L_MASK (0x7 << 13) 638997b0520SBard Liao #define RT5640_G_BST3_OM_L_SFT 13 639997b0520SBard Liao #define RT5640_G_BST2_OM_L_MASK (0x7 << 10) 640997b0520SBard Liao #define RT5640_G_BST2_OM_L_SFT 10 641997b0520SBard Liao #define RT5640_G_BST1_OM_L_MASK (0x7 << 7) 642997b0520SBard Liao #define RT5640_G_BST1_OM_L_SFT 7 643997b0520SBard Liao #define RT5640_G_IN_L_OM_L_MASK (0x7 << 4) 644997b0520SBard Liao #define RT5640_G_IN_L_OM_L_SFT 4 645997b0520SBard Liao #define RT5640_G_RM_L_OM_L_MASK (0x7 << 1) 646997b0520SBard Liao #define RT5640_G_RM_L_OM_L_SFT 1 647997b0520SBard Liao 648997b0520SBard Liao /* Output Left Mixer Control 2 (0x4e) */ 649997b0520SBard Liao #define RT5640_G_DAC_R2_OM_L_MASK (0x7 << 13) 650997b0520SBard Liao #define RT5640_G_DAC_R2_OM_L_SFT 13 651997b0520SBard Liao #define RT5640_G_DAC_L2_OM_L_MASK (0x7 << 10) 652997b0520SBard Liao #define RT5640_G_DAC_L2_OM_L_SFT 10 653997b0520SBard Liao #define RT5640_G_DAC_L1_OM_L_MASK (0x7 << 7) 654997b0520SBard Liao #define RT5640_G_DAC_L1_OM_L_SFT 7 655997b0520SBard Liao 656997b0520SBard Liao /* Output Left Mixer Control 3 (0x4f) */ 657997b0520SBard Liao #define RT5640_M_SM_L_OM_L (0x1 << 8) 658997b0520SBard Liao #define RT5640_M_SM_L_OM_L_SFT 8 659997b0520SBard Liao #define RT5640_M_BST3_OM_L (0x1 << 7) 660997b0520SBard Liao #define RT5640_M_BST3_OM_L_SFT 7 661997b0520SBard Liao #define RT5640_M_BST2_OM_L (0x1 << 6) 662997b0520SBard Liao #define RT5640_M_BST2_OM_L_SFT 6 663997b0520SBard Liao #define RT5640_M_BST1_OM_L (0x1 << 5) 664997b0520SBard Liao #define RT5640_M_BST1_OM_L_SFT 5 665997b0520SBard Liao #define RT5640_M_IN_L_OM_L (0x1 << 4) 666997b0520SBard Liao #define RT5640_M_IN_L_OM_L_SFT 4 667997b0520SBard Liao #define RT5640_M_RM_L_OM_L (0x1 << 3) 668997b0520SBard Liao #define RT5640_M_RM_L_OM_L_SFT 3 669997b0520SBard Liao #define RT5640_M_DAC_R2_OM_L (0x1 << 2) 670997b0520SBard Liao #define RT5640_M_DAC_R2_OM_L_SFT 2 671997b0520SBard Liao #define RT5640_M_DAC_L2_OM_L (0x1 << 1) 672997b0520SBard Liao #define RT5640_M_DAC_L2_OM_L_SFT 1 673997b0520SBard Liao #define RT5640_M_DAC_L1_OM_L (0x1) 674997b0520SBard Liao #define RT5640_M_DAC_L1_OM_L_SFT 0 675997b0520SBard Liao 676997b0520SBard Liao /* Output Right Mixer Control 1 (0x50) */ 677997b0520SBard Liao #define RT5640_G_BST4_OM_R_MASK (0x7 << 13) 678997b0520SBard Liao #define RT5640_G_BST4_OM_R_SFT 13 679997b0520SBard Liao #define RT5640_G_BST2_OM_R_MASK (0x7 << 10) 680997b0520SBard Liao #define RT5640_G_BST2_OM_R_SFT 10 681997b0520SBard Liao #define RT5640_G_BST1_OM_R_MASK (0x7 << 7) 682997b0520SBard Liao #define RT5640_G_BST1_OM_R_SFT 7 683997b0520SBard Liao #define RT5640_G_IN_R_OM_R_MASK (0x7 << 4) 684997b0520SBard Liao #define RT5640_G_IN_R_OM_R_SFT 4 685997b0520SBard Liao #define RT5640_G_RM_R_OM_R_MASK (0x7 << 1) 686997b0520SBard Liao #define RT5640_G_RM_R_OM_R_SFT 1 687997b0520SBard Liao 688997b0520SBard Liao /* Output Right Mixer Control 2 (0x51) */ 689997b0520SBard Liao #define RT5640_G_DAC_L2_OM_R_MASK (0x7 << 13) 690997b0520SBard Liao #define RT5640_G_DAC_L2_OM_R_SFT 13 691997b0520SBard Liao #define RT5640_G_DAC_R2_OM_R_MASK (0x7 << 10) 692997b0520SBard Liao #define RT5640_G_DAC_R2_OM_R_SFT 10 693997b0520SBard Liao #define RT5640_G_DAC_R1_OM_R_MASK (0x7 << 7) 694997b0520SBard Liao #define RT5640_G_DAC_R1_OM_R_SFT 7 695997b0520SBard Liao 696997b0520SBard Liao /* Output Right Mixer Control 3 (0x52) */ 697997b0520SBard Liao #define RT5640_M_SM_L_OM_R (0x1 << 8) 698997b0520SBard Liao #define RT5640_M_SM_L_OM_R_SFT 8 699997b0520SBard Liao #define RT5640_M_BST4_OM_R (0x1 << 7) 700997b0520SBard Liao #define RT5640_M_BST4_OM_R_SFT 7 701997b0520SBard Liao #define RT5640_M_BST2_OM_R (0x1 << 6) 702997b0520SBard Liao #define RT5640_M_BST2_OM_R_SFT 6 703997b0520SBard Liao #define RT5640_M_BST1_OM_R (0x1 << 5) 704997b0520SBard Liao #define RT5640_M_BST1_OM_R_SFT 5 705997b0520SBard Liao #define RT5640_M_IN_R_OM_R (0x1 << 4) 706997b0520SBard Liao #define RT5640_M_IN_R_OM_R_SFT 4 707997b0520SBard Liao #define RT5640_M_RM_R_OM_R (0x1 << 3) 708997b0520SBard Liao #define RT5640_M_RM_R_OM_R_SFT 3 709997b0520SBard Liao #define RT5640_M_DAC_L2_OM_R (0x1 << 2) 710997b0520SBard Liao #define RT5640_M_DAC_L2_OM_R_SFT 2 711997b0520SBard Liao #define RT5640_M_DAC_R2_OM_R (0x1 << 1) 712997b0520SBard Liao #define RT5640_M_DAC_R2_OM_R_SFT 1 713997b0520SBard Liao #define RT5640_M_DAC_R1_OM_R (0x1) 714997b0520SBard Liao #define RT5640_M_DAC_R1_OM_R_SFT 0 715997b0520SBard Liao 716997b0520SBard Liao /* LOUT Mixer Control (0x53) */ 717997b0520SBard Liao #define RT5640_M_DAC_L1_LM (0x1 << 15) 718997b0520SBard Liao #define RT5640_M_DAC_L1_LM_SFT 15 719997b0520SBard Liao #define RT5640_M_DAC_R1_LM (0x1 << 14) 720997b0520SBard Liao #define RT5640_M_DAC_R1_LM_SFT 14 721997b0520SBard Liao #define RT5640_M_OV_L_LM (0x1 << 13) 722997b0520SBard Liao #define RT5640_M_OV_L_LM_SFT 13 723997b0520SBard Liao #define RT5640_M_OV_R_LM (0x1 << 12) 724997b0520SBard Liao #define RT5640_M_OV_R_LM_SFT 12 725997b0520SBard Liao #define RT5640_G_LOUTMIX_MASK (0x1 << 11) 726997b0520SBard Liao #define RT5640_G_LOUTMIX_SFT 11 727997b0520SBard Liao 728997b0520SBard Liao /* Power Management for Digital 1 (0x61) */ 729997b0520SBard Liao #define RT5640_PWR_I2S1 (0x1 << 15) 730997b0520SBard Liao #define RT5640_PWR_I2S1_BIT 15 731997b0520SBard Liao #define RT5640_PWR_I2S2 (0x1 << 14) 732997b0520SBard Liao #define RT5640_PWR_I2S2_BIT 14 733997b0520SBard Liao #define RT5640_PWR_DAC_L1 (0x1 << 12) 734997b0520SBard Liao #define RT5640_PWR_DAC_L1_BIT 12 735997b0520SBard Liao #define RT5640_PWR_DAC_R1 (0x1 << 11) 736997b0520SBard Liao #define RT5640_PWR_DAC_R1_BIT 11 737997b0520SBard Liao #define RT5640_PWR_DAC_L2 (0x1 << 7) 738997b0520SBard Liao #define RT5640_PWR_DAC_L2_BIT 7 739997b0520SBard Liao #define RT5640_PWR_DAC_R2 (0x1 << 6) 740997b0520SBard Liao #define RT5640_PWR_DAC_R2_BIT 6 741997b0520SBard Liao #define RT5640_PWR_ADC_L (0x1 << 2) 742997b0520SBard Liao #define RT5640_PWR_ADC_L_BIT 2 743997b0520SBard Liao #define RT5640_PWR_ADC_R (0x1 << 1) 744997b0520SBard Liao #define RT5640_PWR_ADC_R_BIT 1 745997b0520SBard Liao #define RT5640_PWR_CLS_D (0x1) 746997b0520SBard Liao #define RT5640_PWR_CLS_D_BIT 0 747997b0520SBard Liao 748997b0520SBard Liao /* Power Management for Digital 2 (0x62) */ 749997b0520SBard Liao #define RT5640_PWR_ADC_SF (0x1 << 15) 750997b0520SBard Liao #define RT5640_PWR_ADC_SF_BIT 15 751997b0520SBard Liao #define RT5640_PWR_ADC_MF_L (0x1 << 14) 752997b0520SBard Liao #define RT5640_PWR_ADC_MF_L_BIT 14 753997b0520SBard Liao #define RT5640_PWR_ADC_MF_R (0x1 << 13) 754997b0520SBard Liao #define RT5640_PWR_ADC_MF_R_BIT 13 755997b0520SBard Liao #define RT5640_PWR_I2S_DSP (0x1 << 12) 756997b0520SBard Liao #define RT5640_PWR_I2S_DSP_BIT 12 757997b0520SBard Liao 758997b0520SBard Liao /* Power Management for Analog 1 (0x63) */ 759997b0520SBard Liao #define RT5640_PWR_VREF1 (0x1 << 15) 760997b0520SBard Liao #define RT5640_PWR_VREF1_BIT 15 761997b0520SBard Liao #define RT5640_PWR_FV1 (0x1 << 14) 762997b0520SBard Liao #define RT5640_PWR_FV1_BIT 14 763997b0520SBard Liao #define RT5640_PWR_MB (0x1 << 13) 764997b0520SBard Liao #define RT5640_PWR_MB_BIT 13 765997b0520SBard Liao #define RT5640_PWR_LM (0x1 << 12) 766997b0520SBard Liao #define RT5640_PWR_LM_BIT 12 767997b0520SBard Liao #define RT5640_PWR_BG (0x1 << 11) 768997b0520SBard Liao #define RT5640_PWR_BG_BIT 11 769997b0520SBard Liao #define RT5640_PWR_MM (0x1 << 10) 770997b0520SBard Liao #define RT5640_PWR_MM_BIT 10 771997b0520SBard Liao #define RT5640_PWR_MA (0x1 << 8) 772997b0520SBard Liao #define RT5640_PWR_MA_BIT 8 773997b0520SBard Liao #define RT5640_PWR_HP_L (0x1 << 7) 774997b0520SBard Liao #define RT5640_PWR_HP_L_BIT 7 775997b0520SBard Liao #define RT5640_PWR_HP_R (0x1 << 6) 776997b0520SBard Liao #define RT5640_PWR_HP_R_BIT 6 777997b0520SBard Liao #define RT5640_PWR_HA (0x1 << 5) 778997b0520SBard Liao #define RT5640_PWR_HA_BIT 5 779997b0520SBard Liao #define RT5640_PWR_VREF2 (0x1 << 4) 780997b0520SBard Liao #define RT5640_PWR_VREF2_BIT 4 781997b0520SBard Liao #define RT5640_PWR_FV2 (0x1 << 3) 782997b0520SBard Liao #define RT5640_PWR_FV2_BIT 3 783997b0520SBard Liao #define RT5640_PWR_LDO2 (0x1 << 2) 784997b0520SBard Liao #define RT5640_PWR_LDO2_BIT 2 785997b0520SBard Liao 786997b0520SBard Liao /* Power Management for Analog 2 (0x64) */ 787997b0520SBard Liao #define RT5640_PWR_BST1 (0x1 << 15) 788997b0520SBard Liao #define RT5640_PWR_BST1_BIT 15 789997b0520SBard Liao #define RT5640_PWR_BST2 (0x1 << 14) 790997b0520SBard Liao #define RT5640_PWR_BST2_BIT 14 791997b0520SBard Liao #define RT5640_PWR_BST3 (0x1 << 13) 792997b0520SBard Liao #define RT5640_PWR_BST3_BIT 13 793997b0520SBard Liao #define RT5640_PWR_BST4 (0x1 << 12) 794997b0520SBard Liao #define RT5640_PWR_BST4_BIT 12 795997b0520SBard Liao #define RT5640_PWR_MB1 (0x1 << 11) 796997b0520SBard Liao #define RT5640_PWR_MB1_BIT 11 797997b0520SBard Liao #define RT5640_PWR_PLL (0x1 << 9) 798997b0520SBard Liao #define RT5640_PWR_PLL_BIT 9 799997b0520SBard Liao 800997b0520SBard Liao /* Power Management for Mixer (0x65) */ 801997b0520SBard Liao #define RT5640_PWR_OM_L (0x1 << 15) 802997b0520SBard Liao #define RT5640_PWR_OM_L_BIT 15 803997b0520SBard Liao #define RT5640_PWR_OM_R (0x1 << 14) 804997b0520SBard Liao #define RT5640_PWR_OM_R_BIT 14 805997b0520SBard Liao #define RT5640_PWR_SM_L (0x1 << 13) 806997b0520SBard Liao #define RT5640_PWR_SM_L_BIT 13 807997b0520SBard Liao #define RT5640_PWR_SM_R (0x1 << 12) 808997b0520SBard Liao #define RT5640_PWR_SM_R_BIT 12 809997b0520SBard Liao #define RT5640_PWR_RM_L (0x1 << 11) 810997b0520SBard Liao #define RT5640_PWR_RM_L_BIT 11 811997b0520SBard Liao #define RT5640_PWR_RM_R (0x1 << 10) 812997b0520SBard Liao #define RT5640_PWR_RM_R_BIT 10 813997b0520SBard Liao 814997b0520SBard Liao /* Power Management for Volume (0x66) */ 815997b0520SBard Liao #define RT5640_PWR_SV_L (0x1 << 15) 816997b0520SBard Liao #define RT5640_PWR_SV_L_BIT 15 817997b0520SBard Liao #define RT5640_PWR_SV_R (0x1 << 14) 818997b0520SBard Liao #define RT5640_PWR_SV_R_BIT 14 819997b0520SBard Liao #define RT5640_PWR_OV_L (0x1 << 13) 820997b0520SBard Liao #define RT5640_PWR_OV_L_BIT 13 821997b0520SBard Liao #define RT5640_PWR_OV_R (0x1 << 12) 822997b0520SBard Liao #define RT5640_PWR_OV_R_BIT 12 823997b0520SBard Liao #define RT5640_PWR_HV_L (0x1 << 11) 824997b0520SBard Liao #define RT5640_PWR_HV_L_BIT 11 825997b0520SBard Liao #define RT5640_PWR_HV_R (0x1 << 10) 826997b0520SBard Liao #define RT5640_PWR_HV_R_BIT 10 827997b0520SBard Liao #define RT5640_PWR_IN_L (0x1 << 9) 828997b0520SBard Liao #define RT5640_PWR_IN_L_BIT 9 829997b0520SBard Liao #define RT5640_PWR_IN_R (0x1 << 8) 830997b0520SBard Liao #define RT5640_PWR_IN_R_BIT 8 831997b0520SBard Liao 832997b0520SBard Liao /* I2S1/2/3 Audio Serial Data Port Control (0x70 0x71 0x72) */ 833997b0520SBard Liao #define RT5640_I2S_MS_MASK (0x1 << 15) 834997b0520SBard Liao #define RT5640_I2S_MS_SFT 15 835997b0520SBard Liao #define RT5640_I2S_MS_M (0x0 << 15) 836997b0520SBard Liao #define RT5640_I2S_MS_S (0x1 << 15) 837997b0520SBard Liao #define RT5640_I2S_IF_MASK (0x7 << 12) 838997b0520SBard Liao #define RT5640_I2S_IF_SFT 12 839997b0520SBard Liao #define RT5640_I2S_O_CP_MASK (0x3 << 10) 840997b0520SBard Liao #define RT5640_I2S_O_CP_SFT 10 841997b0520SBard Liao #define RT5640_I2S_O_CP_OFF (0x0 << 10) 842997b0520SBard Liao #define RT5640_I2S_O_CP_U_LAW (0x1 << 10) 843997b0520SBard Liao #define RT5640_I2S_O_CP_A_LAW (0x2 << 10) 844997b0520SBard Liao #define RT5640_I2S_I_CP_MASK (0x3 << 8) 845997b0520SBard Liao #define RT5640_I2S_I_CP_SFT 8 846997b0520SBard Liao #define RT5640_I2S_I_CP_OFF (0x0 << 8) 847997b0520SBard Liao #define RT5640_I2S_I_CP_U_LAW (0x1 << 8) 848997b0520SBard Liao #define RT5640_I2S_I_CP_A_LAW (0x2 << 8) 849997b0520SBard Liao #define RT5640_I2S_BP_MASK (0x1 << 7) 850997b0520SBard Liao #define RT5640_I2S_BP_SFT 7 851997b0520SBard Liao #define RT5640_I2S_BP_NOR (0x0 << 7) 852997b0520SBard Liao #define RT5640_I2S_BP_INV (0x1 << 7) 853997b0520SBard Liao #define RT5640_I2S_DL_MASK (0x3 << 2) 854997b0520SBard Liao #define RT5640_I2S_DL_SFT 2 855997b0520SBard Liao #define RT5640_I2S_DL_16 (0x0 << 2) 856997b0520SBard Liao #define RT5640_I2S_DL_20 (0x1 << 2) 857997b0520SBard Liao #define RT5640_I2S_DL_24 (0x2 << 2) 858997b0520SBard Liao #define RT5640_I2S_DL_8 (0x3 << 2) 859997b0520SBard Liao #define RT5640_I2S_DF_MASK (0x3) 860997b0520SBard Liao #define RT5640_I2S_DF_SFT 0 861997b0520SBard Liao #define RT5640_I2S_DF_I2S (0x0) 862997b0520SBard Liao #define RT5640_I2S_DF_LEFT (0x1) 863997b0520SBard Liao #define RT5640_I2S_DF_PCM_A (0x2) 864997b0520SBard Liao #define RT5640_I2S_DF_PCM_B (0x3) 865997b0520SBard Liao 866997b0520SBard Liao /* I2S2 Audio Serial Data Port Control (0x71) */ 867997b0520SBard Liao #define RT5640_I2S2_SDI_MASK (0x1 << 6) 868997b0520SBard Liao #define RT5640_I2S2_SDI_SFT 6 869997b0520SBard Liao #define RT5640_I2S2_SDI_I2S1 (0x0 << 6) 870997b0520SBard Liao #define RT5640_I2S2_SDI_I2S2 (0x1 << 6) 871997b0520SBard Liao 872997b0520SBard Liao /* ADC/DAC Clock Control 1 (0x73) */ 873997b0520SBard Liao #define RT5640_I2S_BCLK_MS1_MASK (0x1 << 15) 874997b0520SBard Liao #define RT5640_I2S_BCLK_MS1_SFT 15 875997b0520SBard Liao #define RT5640_I2S_BCLK_MS1_32 (0x0 << 15) 876997b0520SBard Liao #define RT5640_I2S_BCLK_MS1_64 (0x1 << 15) 877997b0520SBard Liao #define RT5640_I2S_PD1_MASK (0x7 << 12) 878997b0520SBard Liao #define RT5640_I2S_PD1_SFT 12 879997b0520SBard Liao #define RT5640_I2S_PD1_1 (0x0 << 12) 880997b0520SBard Liao #define RT5640_I2S_PD1_2 (0x1 << 12) 881997b0520SBard Liao #define RT5640_I2S_PD1_3 (0x2 << 12) 882997b0520SBard Liao #define RT5640_I2S_PD1_4 (0x3 << 12) 883997b0520SBard Liao #define RT5640_I2S_PD1_6 (0x4 << 12) 884997b0520SBard Liao #define RT5640_I2S_PD1_8 (0x5 << 12) 885997b0520SBard Liao #define RT5640_I2S_PD1_12 (0x6 << 12) 886997b0520SBard Liao #define RT5640_I2S_PD1_16 (0x7 << 12) 887997b0520SBard Liao #define RT5640_I2S_BCLK_MS2_MASK (0x1 << 11) 888997b0520SBard Liao #define RT5640_I2S_BCLK_MS2_SFT 11 889997b0520SBard Liao #define RT5640_I2S_BCLK_MS2_32 (0x0 << 11) 890997b0520SBard Liao #define RT5640_I2S_BCLK_MS2_64 (0x1 << 11) 891997b0520SBard Liao #define RT5640_I2S_PD2_MASK (0x7 << 8) 892997b0520SBard Liao #define RT5640_I2S_PD2_SFT 8 893997b0520SBard Liao #define RT5640_I2S_PD2_1 (0x0 << 8) 894997b0520SBard Liao #define RT5640_I2S_PD2_2 (0x1 << 8) 895997b0520SBard Liao #define RT5640_I2S_PD2_3 (0x2 << 8) 896997b0520SBard Liao #define RT5640_I2S_PD2_4 (0x3 << 8) 897997b0520SBard Liao #define RT5640_I2S_PD2_6 (0x4 << 8) 898997b0520SBard Liao #define RT5640_I2S_PD2_8 (0x5 << 8) 899997b0520SBard Liao #define RT5640_I2S_PD2_12 (0x6 << 8) 900997b0520SBard Liao #define RT5640_I2S_PD2_16 (0x7 << 8) 901997b0520SBard Liao #define RT5640_I2S_BCLK_MS3_MASK (0x1 << 7) 902997b0520SBard Liao #define RT5640_I2S_BCLK_MS3_SFT 7 903997b0520SBard Liao #define RT5640_I2S_BCLK_MS3_32 (0x0 << 7) 904997b0520SBard Liao #define RT5640_I2S_BCLK_MS3_64 (0x1 << 7) 905997b0520SBard Liao #define RT5640_I2S_PD3_MASK (0x7 << 4) 906997b0520SBard Liao #define RT5640_I2S_PD3_SFT 4 907997b0520SBard Liao #define RT5640_I2S_PD3_1 (0x0 << 4) 908997b0520SBard Liao #define RT5640_I2S_PD3_2 (0x1 << 4) 909997b0520SBard Liao #define RT5640_I2S_PD3_3 (0x2 << 4) 910997b0520SBard Liao #define RT5640_I2S_PD3_4 (0x3 << 4) 911997b0520SBard Liao #define RT5640_I2S_PD3_6 (0x4 << 4) 912997b0520SBard Liao #define RT5640_I2S_PD3_8 (0x5 << 4) 913997b0520SBard Liao #define RT5640_I2S_PD3_12 (0x6 << 4) 914997b0520SBard Liao #define RT5640_I2S_PD3_16 (0x7 << 4) 915997b0520SBard Liao #define RT5640_DAC_OSR_MASK (0x3 << 2) 916997b0520SBard Liao #define RT5640_DAC_OSR_SFT 2 917997b0520SBard Liao #define RT5640_DAC_OSR_128 (0x0 << 2) 918997b0520SBard Liao #define RT5640_DAC_OSR_64 (0x1 << 2) 919997b0520SBard Liao #define RT5640_DAC_OSR_32 (0x2 << 2) 920997b0520SBard Liao #define RT5640_DAC_OSR_16 (0x3 << 2) 921997b0520SBard Liao #define RT5640_ADC_OSR_MASK (0x3) 922997b0520SBard Liao #define RT5640_ADC_OSR_SFT 0 923997b0520SBard Liao #define RT5640_ADC_OSR_128 (0x0) 924997b0520SBard Liao #define RT5640_ADC_OSR_64 (0x1) 925997b0520SBard Liao #define RT5640_ADC_OSR_32 (0x2) 926997b0520SBard Liao #define RT5640_ADC_OSR_16 (0x3) 927997b0520SBard Liao 928997b0520SBard Liao /* ADC/DAC Clock Control 2 (0x74) */ 929997b0520SBard Liao #define RT5640_DAC_L_OSR_MASK (0x3 << 14) 930997b0520SBard Liao #define RT5640_DAC_L_OSR_SFT 14 931997b0520SBard Liao #define RT5640_DAC_L_OSR_128 (0x0 << 14) 932997b0520SBard Liao #define RT5640_DAC_L_OSR_64 (0x1 << 14) 933997b0520SBard Liao #define RT5640_DAC_L_OSR_32 (0x2 << 14) 934997b0520SBard Liao #define RT5640_DAC_L_OSR_16 (0x3 << 14) 935997b0520SBard Liao #define RT5640_ADC_R_OSR_MASK (0x3 << 12) 936997b0520SBard Liao #define RT5640_ADC_R_OSR_SFT 12 937997b0520SBard Liao #define RT5640_ADC_R_OSR_128 (0x0 << 12) 938997b0520SBard Liao #define RT5640_ADC_R_OSR_64 (0x1 << 12) 939997b0520SBard Liao #define RT5640_ADC_R_OSR_32 (0x2 << 12) 940997b0520SBard Liao #define RT5640_ADC_R_OSR_16 (0x3 << 12) 941997b0520SBard Liao #define RT5640_DAHPF_EN (0x1 << 11) 942997b0520SBard Liao #define RT5640_DAHPF_EN_SFT 11 943997b0520SBard Liao #define RT5640_ADHPF_EN (0x1 << 10) 944997b0520SBard Liao #define RT5640_ADHPF_EN_SFT 10 945997b0520SBard Liao 946997b0520SBard Liao /* Digital Microphone Control (0x75) */ 947997b0520SBard Liao #define RT5640_DMIC_1_EN_MASK (0x1 << 15) 948997b0520SBard Liao #define RT5640_DMIC_1_EN_SFT 15 949997b0520SBard Liao #define RT5640_DMIC_1_DIS (0x0 << 15) 950997b0520SBard Liao #define RT5640_DMIC_1_EN (0x1 << 15) 951997b0520SBard Liao #define RT5640_DMIC_2_EN_MASK (0x1 << 14) 952997b0520SBard Liao #define RT5640_DMIC_2_EN_SFT 14 953997b0520SBard Liao #define RT5640_DMIC_2_DIS (0x0 << 14) 954997b0520SBard Liao #define RT5640_DMIC_2_EN (0x1 << 14) 955997b0520SBard Liao #define RT5640_DMIC_1L_LH_MASK (0x1 << 13) 956997b0520SBard Liao #define RT5640_DMIC_1L_LH_SFT 13 957997b0520SBard Liao #define RT5640_DMIC_1L_LH_FALLING (0x0 << 13) 958997b0520SBard Liao #define RT5640_DMIC_1L_LH_RISING (0x1 << 13) 959997b0520SBard Liao #define RT5640_DMIC_1R_LH_MASK (0x1 << 12) 960997b0520SBard Liao #define RT5640_DMIC_1R_LH_SFT 12 961997b0520SBard Liao #define RT5640_DMIC_1R_LH_FALLING (0x0 << 12) 962997b0520SBard Liao #define RT5640_DMIC_1R_LH_RISING (0x1 << 12) 963997b0520SBard Liao #define RT5640_DMIC_1_DP_MASK (0x1 << 11) 964997b0520SBard Liao #define RT5640_DMIC_1_DP_SFT 11 965997b0520SBard Liao #define RT5640_DMIC_1_DP_GPIO3 (0x0 << 11) 966997b0520SBard Liao #define RT5640_DMIC_1_DP_IN1P (0x1 << 11) 967997b0520SBard Liao #define RT5640_DMIC_2_DP_MASK (0x1 << 10) 968997b0520SBard Liao #define RT5640_DMIC_2_DP_SFT 10 969997b0520SBard Liao #define RT5640_DMIC_2_DP_GPIO4 (0x0 << 10) 970997b0520SBard Liao #define RT5640_DMIC_2_DP_IN1N (0x1 << 10) 971997b0520SBard Liao #define RT5640_DMIC_2L_LH_MASK (0x1 << 9) 972997b0520SBard Liao #define RT5640_DMIC_2L_LH_SFT 9 973997b0520SBard Liao #define RT5640_DMIC_2L_LH_FALLING (0x0 << 9) 974997b0520SBard Liao #define RT5640_DMIC_2L_LH_RISING (0x1 << 9) 975997b0520SBard Liao #define RT5640_DMIC_2R_LH_MASK (0x1 << 8) 976997b0520SBard Liao #define RT5640_DMIC_2R_LH_SFT 8 977997b0520SBard Liao #define RT5640_DMIC_2R_LH_FALLING (0x0 << 8) 978997b0520SBard Liao #define RT5640_DMIC_2R_LH_RISING (0x1 << 8) 979997b0520SBard Liao #define RT5640_DMIC_CLK_MASK (0x7 << 5) 980997b0520SBard Liao #define RT5640_DMIC_CLK_SFT 5 981997b0520SBard Liao 982997b0520SBard Liao /* Global Clock Control (0x80) */ 983997b0520SBard Liao #define RT5640_SCLK_SRC_MASK (0x3 << 14) 984997b0520SBard Liao #define RT5640_SCLK_SRC_SFT 14 985997b0520SBard Liao #define RT5640_SCLK_SRC_MCLK (0x0 << 14) 986997b0520SBard Liao #define RT5640_SCLK_SRC_PLL1 (0x1 << 14) 987c49aed77SPierre-Louis Bossart #define RT5640_SCLK_SRC_RCCLK (0x2 << 14) 988997b0520SBard Liao #define RT5640_PLL1_SRC_MASK (0x3 << 12) 989997b0520SBard Liao #define RT5640_PLL1_SRC_SFT 12 990997b0520SBard Liao #define RT5640_PLL1_SRC_MCLK (0x0 << 12) 991997b0520SBard Liao #define RT5640_PLL1_SRC_BCLK1 (0x1 << 12) 992997b0520SBard Liao #define RT5640_PLL1_SRC_BCLK2 (0x2 << 12) 993997b0520SBard Liao #define RT5640_PLL1_SRC_BCLK3 (0x3 << 12) 994997b0520SBard Liao #define RT5640_PLL1_PD_MASK (0x1 << 3) 995997b0520SBard Liao #define RT5640_PLL1_PD_SFT 3 996997b0520SBard Liao #define RT5640_PLL1_PD_1 (0x0 << 3) 997997b0520SBard Liao #define RT5640_PLL1_PD_2 (0x1 << 3) 998997b0520SBard Liao 999997b0520SBard Liao #define RT5640_PLL_INP_MAX 40000000 1000997b0520SBard Liao #define RT5640_PLL_INP_MIN 256000 1001997b0520SBard Liao /* PLL M/N/K Code Control 1 (0x81) */ 1002997b0520SBard Liao #define RT5640_PLL_N_MAX 0x1ff 1003997b0520SBard Liao #define RT5640_PLL_N_MASK (RT5640_PLL_N_MAX << 7) 1004997b0520SBard Liao #define RT5640_PLL_N_SFT 7 1005997b0520SBard Liao #define RT5640_PLL_K_MAX 0x1f 1006997b0520SBard Liao #define RT5640_PLL_K_MASK (RT5640_PLL_K_MAX) 1007997b0520SBard Liao #define RT5640_PLL_K_SFT 0 1008997b0520SBard Liao 1009997b0520SBard Liao /* PLL M/N/K Code Control 2 (0x82) */ 1010997b0520SBard Liao #define RT5640_PLL_M_MAX 0xf 1011997b0520SBard Liao #define RT5640_PLL_M_MASK (RT5640_PLL_M_MAX << 12) 1012997b0520SBard Liao #define RT5640_PLL_M_SFT 12 1013997b0520SBard Liao #define RT5640_PLL_M_BP (0x1 << 11) 1014997b0520SBard Liao #define RT5640_PLL_M_BP_SFT 11 1015997b0520SBard Liao 1016997b0520SBard Liao /* ASRC Control 1 (0x83) */ 1017997b0520SBard Liao #define RT5640_STO_T_MASK (0x1 << 15) 1018997b0520SBard Liao #define RT5640_STO_T_SFT 15 1019997b0520SBard Liao #define RT5640_STO_T_SCLK (0x0 << 15) 1020997b0520SBard Liao #define RT5640_STO_T_LRCK1 (0x1 << 15) 1021997b0520SBard Liao #define RT5640_M1_T_MASK (0x1 << 14) 1022997b0520SBard Liao #define RT5640_M1_T_SFT 14 1023997b0520SBard Liao #define RT5640_M1_T_I2S2 (0x0 << 14) 1024997b0520SBard Liao #define RT5640_M1_T_I2S2_D3 (0x1 << 14) 1025997b0520SBard Liao #define RT5640_I2S2_F_MASK (0x1 << 12) 1026997b0520SBard Liao #define RT5640_I2S2_F_SFT 12 1027997b0520SBard Liao #define RT5640_I2S2_F_I2S2_D2 (0x0 << 12) 1028997b0520SBard Liao #define RT5640_I2S2_F_I2S1_TCLK (0x1 << 12) 1029997b0520SBard Liao #define RT5640_DMIC_1_M_MASK (0x1 << 9) 1030997b0520SBard Liao #define RT5640_DMIC_1_M_SFT 9 1031997b0520SBard Liao #define RT5640_DMIC_1_M_NOR (0x0 << 9) 1032997b0520SBard Liao #define RT5640_DMIC_1_M_ASYN (0x1 << 9) 1033997b0520SBard Liao #define RT5640_DMIC_2_M_MASK (0x1 << 8) 1034997b0520SBard Liao #define RT5640_DMIC_2_M_SFT 8 1035997b0520SBard Liao #define RT5640_DMIC_2_M_NOR (0x0 << 8) 1036997b0520SBard Liao #define RT5640_DMIC_2_M_ASYN (0x1 << 8) 1037997b0520SBard Liao 1038bee3e020SJack Yu /* ASRC clock source selection (0x84) */ 1039bee3e020SJack Yu #define RT5640_CLK_SEL_SYS (0x0) 1040bee3e020SJack Yu #define RT5640_CLK_SEL_ASRC (0x1) 1041bee3e020SJack Yu 1042997b0520SBard Liao /* ASRC Control 2 (0x84) */ 1043997b0520SBard Liao #define RT5640_MDA_L_M_MASK (0x1 << 15) 1044997b0520SBard Liao #define RT5640_MDA_L_M_SFT 15 1045997b0520SBard Liao #define RT5640_MDA_L_M_NOR (0x0 << 15) 1046997b0520SBard Liao #define RT5640_MDA_L_M_ASYN (0x1 << 15) 1047997b0520SBard Liao #define RT5640_MDA_R_M_MASK (0x1 << 14) 1048997b0520SBard Liao #define RT5640_MDA_R_M_SFT 14 1049997b0520SBard Liao #define RT5640_MDA_R_M_NOR (0x0 << 14) 1050997b0520SBard Liao #define RT5640_MDA_R_M_ASYN (0x1 << 14) 1051997b0520SBard Liao #define RT5640_MAD_L_M_MASK (0x1 << 13) 1052997b0520SBard Liao #define RT5640_MAD_L_M_SFT 13 1053997b0520SBard Liao #define RT5640_MAD_L_M_NOR (0x0 << 13) 1054997b0520SBard Liao #define RT5640_MAD_L_M_ASYN (0x1 << 13) 1055997b0520SBard Liao #define RT5640_MAD_R_M_MASK (0x1 << 12) 1056997b0520SBard Liao #define RT5640_MAD_R_M_SFT 12 1057997b0520SBard Liao #define RT5640_MAD_R_M_NOR (0x0 << 12) 1058997b0520SBard Liao #define RT5640_MAD_R_M_ASYN (0x1 << 12) 1059997b0520SBard Liao #define RT5640_ADC_M_MASK (0x1 << 11) 1060997b0520SBard Liao #define RT5640_ADC_M_SFT 11 1061997b0520SBard Liao #define RT5640_ADC_M_NOR (0x0 << 11) 1062997b0520SBard Liao #define RT5640_ADC_M_ASYN (0x1 << 11) 1063997b0520SBard Liao #define RT5640_STO_DAC_M_MASK (0x1 << 5) 1064997b0520SBard Liao #define RT5640_STO_DAC_M_SFT 5 1065997b0520SBard Liao #define RT5640_STO_DAC_M_NOR (0x0 << 5) 1066997b0520SBard Liao #define RT5640_STO_DAC_M_ASYN (0x1 << 5) 1067997b0520SBard Liao #define RT5640_I2S1_R_D_MASK (0x1 << 4) 1068997b0520SBard Liao #define RT5640_I2S1_R_D_SFT 4 1069997b0520SBard Liao #define RT5640_I2S1_R_D_DIS (0x0 << 4) 1070997b0520SBard Liao #define RT5640_I2S1_R_D_EN (0x1 << 4) 1071997b0520SBard Liao #define RT5640_I2S2_R_D_MASK (0x1 << 3) 1072997b0520SBard Liao #define RT5640_I2S2_R_D_SFT 3 1073997b0520SBard Liao #define RT5640_I2S2_R_D_DIS (0x0 << 3) 1074997b0520SBard Liao #define RT5640_I2S2_R_D_EN (0x1 << 3) 1075997b0520SBard Liao #define RT5640_PRE_SCLK_MASK (0x3) 1076997b0520SBard Liao #define RT5640_PRE_SCLK_SFT 0 1077997b0520SBard Liao #define RT5640_PRE_SCLK_512 (0x0) 1078997b0520SBard Liao #define RT5640_PRE_SCLK_1024 (0x1) 1079997b0520SBard Liao #define RT5640_PRE_SCLK_2048 (0x2) 1080997b0520SBard Liao 1081997b0520SBard Liao /* ASRC Control 3 (0x85) */ 1082997b0520SBard Liao #define RT5640_I2S1_RATE_MASK (0xf << 12) 1083997b0520SBard Liao #define RT5640_I2S1_RATE_SFT 12 1084997b0520SBard Liao #define RT5640_I2S2_RATE_MASK (0xf << 8) 1085997b0520SBard Liao #define RT5640_I2S2_RATE_SFT 8 1086997b0520SBard Liao 1087997b0520SBard Liao /* ASRC Control 4 (0x89) */ 1088997b0520SBard Liao #define RT5640_I2S1_PD_MASK (0x7 << 12) 1089997b0520SBard Liao #define RT5640_I2S1_PD_SFT 12 1090997b0520SBard Liao #define RT5640_I2S2_PD_MASK (0x7 << 8) 1091997b0520SBard Liao #define RT5640_I2S2_PD_SFT 8 1092997b0520SBard Liao 1093997b0520SBard Liao /* HPOUT Over Current Detection (0x8b) */ 1094997b0520SBard Liao #define RT5640_HP_OVCD_MASK (0x1 << 10) 1095997b0520SBard Liao #define RT5640_HP_OVCD_SFT 10 1096997b0520SBard Liao #define RT5640_HP_OVCD_DIS (0x0 << 10) 1097997b0520SBard Liao #define RT5640_HP_OVCD_EN (0x1 << 10) 1098997b0520SBard Liao #define RT5640_HP_OC_TH_MASK (0x3 << 8) 1099997b0520SBard Liao #define RT5640_HP_OC_TH_SFT 8 1100997b0520SBard Liao #define RT5640_HP_OC_TH_90 (0x0 << 8) 1101997b0520SBard Liao #define RT5640_HP_OC_TH_105 (0x1 << 8) 1102997b0520SBard Liao #define RT5640_HP_OC_TH_120 (0x2 << 8) 1103997b0520SBard Liao #define RT5640_HP_OC_TH_135 (0x3 << 8) 1104997b0520SBard Liao 1105997b0520SBard Liao /* Class D Over Current Control (0x8c) */ 1106997b0520SBard Liao #define RT5640_CLSD_OC_MASK (0x1 << 9) 1107997b0520SBard Liao #define RT5640_CLSD_OC_SFT 9 1108997b0520SBard Liao #define RT5640_CLSD_OC_PU (0x0 << 9) 1109997b0520SBard Liao #define RT5640_CLSD_OC_PD (0x1 << 9) 1110997b0520SBard Liao #define RT5640_AUTO_PD_MASK (0x1 << 8) 1111997b0520SBard Liao #define RT5640_AUTO_PD_SFT 8 1112997b0520SBard Liao #define RT5640_AUTO_PD_DIS (0x0 << 8) 1113997b0520SBard Liao #define RT5640_AUTO_PD_EN (0x1 << 8) 1114997b0520SBard Liao #define RT5640_CLSD_OC_TH_MASK (0x3f) 1115997b0520SBard Liao #define RT5640_CLSD_OC_TH_SFT 0 1116997b0520SBard Liao 1117997b0520SBard Liao /* Class D Output Control (0x8d) */ 1118997b0520SBard Liao #define RT5640_CLSD_RATIO_MASK (0xf << 12) 1119997b0520SBard Liao #define RT5640_CLSD_RATIO_SFT 12 1120997b0520SBard Liao #define RT5640_CLSD_OM_MASK (0x1 << 11) 1121997b0520SBard Liao #define RT5640_CLSD_OM_SFT 11 1122997b0520SBard Liao #define RT5640_CLSD_OM_MONO (0x0 << 11) 1123997b0520SBard Liao #define RT5640_CLSD_OM_STO (0x1 << 11) 1124997b0520SBard Liao #define RT5640_CLSD_SCH_MASK (0x1 << 10) 1125997b0520SBard Liao #define RT5640_CLSD_SCH_SFT 10 1126997b0520SBard Liao #define RT5640_CLSD_SCH_L (0x0 << 10) 1127997b0520SBard Liao #define RT5640_CLSD_SCH_S (0x1 << 10) 1128997b0520SBard Liao 1129997b0520SBard Liao /* Depop Mode Control 1 (0x8e) */ 1130997b0520SBard Liao #define RT5640_SMT_TRIG_MASK (0x1 << 15) 1131997b0520SBard Liao #define RT5640_SMT_TRIG_SFT 15 1132997b0520SBard Liao #define RT5640_SMT_TRIG_DIS (0x0 << 15) 1133997b0520SBard Liao #define RT5640_SMT_TRIG_EN (0x1 << 15) 1134997b0520SBard Liao #define RT5640_HP_L_SMT_MASK (0x1 << 9) 1135997b0520SBard Liao #define RT5640_HP_L_SMT_SFT 9 1136997b0520SBard Liao #define RT5640_HP_L_SMT_DIS (0x0 << 9) 1137997b0520SBard Liao #define RT5640_HP_L_SMT_EN (0x1 << 9) 1138997b0520SBard Liao #define RT5640_HP_R_SMT_MASK (0x1 << 8) 1139997b0520SBard Liao #define RT5640_HP_R_SMT_SFT 8 1140997b0520SBard Liao #define RT5640_HP_R_SMT_DIS (0x0 << 8) 1141997b0520SBard Liao #define RT5640_HP_R_SMT_EN (0x1 << 8) 1142997b0520SBard Liao #define RT5640_HP_CD_PD_MASK (0x1 << 7) 1143997b0520SBard Liao #define RT5640_HP_CD_PD_SFT 7 1144997b0520SBard Liao #define RT5640_HP_CD_PD_DIS (0x0 << 7) 1145997b0520SBard Liao #define RT5640_HP_CD_PD_EN (0x1 << 7) 1146997b0520SBard Liao #define RT5640_RSTN_MASK (0x1 << 6) 1147997b0520SBard Liao #define RT5640_RSTN_SFT 6 1148997b0520SBard Liao #define RT5640_RSTN_DIS (0x0 << 6) 1149997b0520SBard Liao #define RT5640_RSTN_EN (0x1 << 6) 1150997b0520SBard Liao #define RT5640_RSTP_MASK (0x1 << 5) 1151997b0520SBard Liao #define RT5640_RSTP_SFT 5 1152997b0520SBard Liao #define RT5640_RSTP_DIS (0x0 << 5) 1153997b0520SBard Liao #define RT5640_RSTP_EN (0x1 << 5) 1154997b0520SBard Liao #define RT5640_HP_CO_MASK (0x1 << 4) 1155997b0520SBard Liao #define RT5640_HP_CO_SFT 4 1156997b0520SBard Liao #define RT5640_HP_CO_DIS (0x0 << 4) 1157997b0520SBard Liao #define RT5640_HP_CO_EN (0x1 << 4) 1158997b0520SBard Liao #define RT5640_HP_CP_MASK (0x1 << 3) 1159997b0520SBard Liao #define RT5640_HP_CP_SFT 3 1160997b0520SBard Liao #define RT5640_HP_CP_PD (0x0 << 3) 1161997b0520SBard Liao #define RT5640_HP_CP_PU (0x1 << 3) 1162997b0520SBard Liao #define RT5640_HP_SG_MASK (0x1 << 2) 1163997b0520SBard Liao #define RT5640_HP_SG_SFT 2 1164997b0520SBard Liao #define RT5640_HP_SG_DIS (0x0 << 2) 1165997b0520SBard Liao #define RT5640_HP_SG_EN (0x1 << 2) 1166997b0520SBard Liao #define RT5640_HP_DP_MASK (0x1 << 1) 1167997b0520SBard Liao #define RT5640_HP_DP_SFT 1 1168997b0520SBard Liao #define RT5640_HP_DP_PD (0x0 << 1) 1169997b0520SBard Liao #define RT5640_HP_DP_PU (0x1 << 1) 1170997b0520SBard Liao #define RT5640_HP_CB_MASK (0x1) 1171997b0520SBard Liao #define RT5640_HP_CB_SFT 0 1172997b0520SBard Liao #define RT5640_HP_CB_PD (0x0) 1173997b0520SBard Liao #define RT5640_HP_CB_PU (0x1) 1174997b0520SBard Liao 1175997b0520SBard Liao /* Depop Mode Control 2 (0x8f) */ 1176997b0520SBard Liao #define RT5640_DEPOP_MASK (0x1 << 13) 1177997b0520SBard Liao #define RT5640_DEPOP_SFT 13 1178997b0520SBard Liao #define RT5640_DEPOP_AUTO (0x0 << 13) 1179997b0520SBard Liao #define RT5640_DEPOP_MAN (0x1 << 13) 1180997b0520SBard Liao #define RT5640_RAMP_MASK (0x1 << 12) 1181997b0520SBard Liao #define RT5640_RAMP_SFT 12 1182997b0520SBard Liao #define RT5640_RAMP_DIS (0x0 << 12) 1183997b0520SBard Liao #define RT5640_RAMP_EN (0x1 << 12) 1184997b0520SBard Liao #define RT5640_BPS_MASK (0x1 << 11) 1185997b0520SBard Liao #define RT5640_BPS_SFT 11 1186997b0520SBard Liao #define RT5640_BPS_DIS (0x0 << 11) 1187997b0520SBard Liao #define RT5640_BPS_EN (0x1 << 11) 1188997b0520SBard Liao #define RT5640_FAST_UPDN_MASK (0x1 << 10) 1189997b0520SBard Liao #define RT5640_FAST_UPDN_SFT 10 1190997b0520SBard Liao #define RT5640_FAST_UPDN_DIS (0x0 << 10) 1191997b0520SBard Liao #define RT5640_FAST_UPDN_EN (0x1 << 10) 1192997b0520SBard Liao #define RT5640_MRES_MASK (0x3 << 8) 1193997b0520SBard Liao #define RT5640_MRES_SFT 8 1194997b0520SBard Liao #define RT5640_MRES_15MO (0x0 << 8) 1195997b0520SBard Liao #define RT5640_MRES_25MO (0x1 << 8) 1196997b0520SBard Liao #define RT5640_MRES_35MO (0x2 << 8) 1197997b0520SBard Liao #define RT5640_MRES_45MO (0x3 << 8) 1198997b0520SBard Liao #define RT5640_VLO_MASK (0x1 << 7) 1199997b0520SBard Liao #define RT5640_VLO_SFT 7 1200997b0520SBard Liao #define RT5640_VLO_3V (0x0 << 7) 1201997b0520SBard Liao #define RT5640_VLO_32V (0x1 << 7) 1202997b0520SBard Liao #define RT5640_DIG_DP_MASK (0x1 << 6) 1203997b0520SBard Liao #define RT5640_DIG_DP_SFT 6 1204997b0520SBard Liao #define RT5640_DIG_DP_DIS (0x0 << 6) 1205997b0520SBard Liao #define RT5640_DIG_DP_EN (0x1 << 6) 1206997b0520SBard Liao #define RT5640_DP_TH_MASK (0x3 << 4) 1207997b0520SBard Liao #define RT5640_DP_TH_SFT 4 1208997b0520SBard Liao 1209997b0520SBard Liao /* Depop Mode Control 3 (0x90) */ 1210997b0520SBard Liao #define RT5640_CP_SYS_MASK (0x7 << 12) 1211997b0520SBard Liao #define RT5640_CP_SYS_SFT 12 1212997b0520SBard Liao #define RT5640_CP_FQ1_MASK (0x7 << 8) 1213997b0520SBard Liao #define RT5640_CP_FQ1_SFT 8 1214997b0520SBard Liao #define RT5640_CP_FQ2_MASK (0x7 << 4) 1215997b0520SBard Liao #define RT5640_CP_FQ2_SFT 4 1216997b0520SBard Liao #define RT5640_CP_FQ3_MASK (0x7) 1217997b0520SBard Liao #define RT5640_CP_FQ3_SFT 0 1218246693baSBard Liao #define RT5640_CP_FQ_1_5_KHZ 0 1219246693baSBard Liao #define RT5640_CP_FQ_3_KHZ 1 1220246693baSBard Liao #define RT5640_CP_FQ_6_KHZ 2 1221246693baSBard Liao #define RT5640_CP_FQ_12_KHZ 3 1222246693baSBard Liao #define RT5640_CP_FQ_24_KHZ 4 1223246693baSBard Liao #define RT5640_CP_FQ_48_KHZ 5 1224246693baSBard Liao #define RT5640_CP_FQ_96_KHZ 6 1225246693baSBard Liao #define RT5640_CP_FQ_192_KHZ 7 1226997b0520SBard Liao 1227997b0520SBard Liao /* HPOUT charge pump (0x91) */ 1228997b0520SBard Liao #define RT5640_OSW_L_MASK (0x1 << 11) 1229997b0520SBard Liao #define RT5640_OSW_L_SFT 11 1230997b0520SBard Liao #define RT5640_OSW_L_DIS (0x0 << 11) 1231997b0520SBard Liao #define RT5640_OSW_L_EN (0x1 << 11) 1232997b0520SBard Liao #define RT5640_OSW_R_MASK (0x1 << 10) 1233997b0520SBard Liao #define RT5640_OSW_R_SFT 10 1234997b0520SBard Liao #define RT5640_OSW_R_DIS (0x0 << 10) 1235997b0520SBard Liao #define RT5640_OSW_R_EN (0x1 << 10) 1236997b0520SBard Liao #define RT5640_PM_HP_MASK (0x3 << 8) 1237997b0520SBard Liao #define RT5640_PM_HP_SFT 8 1238997b0520SBard Liao #define RT5640_PM_HP_LV (0x0 << 8) 1239997b0520SBard Liao #define RT5640_PM_HP_MV (0x1 << 8) 1240997b0520SBard Liao #define RT5640_PM_HP_HV (0x2 << 8) 1241997b0520SBard Liao #define RT5640_IB_HP_MASK (0x3 << 6) 1242997b0520SBard Liao #define RT5640_IB_HP_SFT 6 1243997b0520SBard Liao #define RT5640_IB_HP_125IL (0x0 << 6) 1244997b0520SBard Liao #define RT5640_IB_HP_25IL (0x1 << 6) 1245997b0520SBard Liao #define RT5640_IB_HP_5IL (0x2 << 6) 1246997b0520SBard Liao #define RT5640_IB_HP_1IL (0x3 << 6) 1247997b0520SBard Liao 1248997b0520SBard Liao /* PV detection and SPK gain control (0x92) */ 1249997b0520SBard Liao #define RT5640_PVDD_DET_MASK (0x1 << 15) 1250997b0520SBard Liao #define RT5640_PVDD_DET_SFT 15 1251997b0520SBard Liao #define RT5640_PVDD_DET_DIS (0x0 << 15) 1252997b0520SBard Liao #define RT5640_PVDD_DET_EN (0x1 << 15) 1253997b0520SBard Liao #define RT5640_SPK_AG_MASK (0x1 << 14) 1254997b0520SBard Liao #define RT5640_SPK_AG_SFT 14 1255997b0520SBard Liao #define RT5640_SPK_AG_DIS (0x0 << 14) 1256997b0520SBard Liao #define RT5640_SPK_AG_EN (0x1 << 14) 1257997b0520SBard Liao 1258997b0520SBard Liao /* Micbias Control (0x93) */ 1259997b0520SBard Liao #define RT5640_MIC1_BS_MASK (0x1 << 15) 1260997b0520SBard Liao #define RT5640_MIC1_BS_SFT 15 1261997b0520SBard Liao #define RT5640_MIC1_BS_9AV (0x0 << 15) 1262997b0520SBard Liao #define RT5640_MIC1_BS_75AV (0x1 << 15) 1263997b0520SBard Liao #define RT5640_MIC2_BS_MASK (0x1 << 14) 1264997b0520SBard Liao #define RT5640_MIC2_BS_SFT 14 1265997b0520SBard Liao #define RT5640_MIC2_BS_9AV (0x0 << 14) 1266997b0520SBard Liao #define RT5640_MIC2_BS_75AV (0x1 << 14) 1267997b0520SBard Liao #define RT5640_MIC1_CLK_MASK (0x1 << 13) 1268997b0520SBard Liao #define RT5640_MIC1_CLK_SFT 13 1269997b0520SBard Liao #define RT5640_MIC1_CLK_DIS (0x0 << 13) 1270997b0520SBard Liao #define RT5640_MIC1_CLK_EN (0x1 << 13) 1271997b0520SBard Liao #define RT5640_MIC2_CLK_MASK (0x1 << 12) 1272997b0520SBard Liao #define RT5640_MIC2_CLK_SFT 12 1273997b0520SBard Liao #define RT5640_MIC2_CLK_DIS (0x0 << 12) 1274997b0520SBard Liao #define RT5640_MIC2_CLK_EN (0x1 << 12) 1275997b0520SBard Liao #define RT5640_MIC1_OVCD_MASK (0x1 << 11) 1276997b0520SBard Liao #define RT5640_MIC1_OVCD_SFT 11 1277997b0520SBard Liao #define RT5640_MIC1_OVCD_DIS (0x0 << 11) 1278997b0520SBard Liao #define RT5640_MIC1_OVCD_EN (0x1 << 11) 1279997b0520SBard Liao #define RT5640_MIC1_OVTH_MASK (0x3 << 9) 1280997b0520SBard Liao #define RT5640_MIC1_OVTH_SFT 9 1281997b0520SBard Liao #define RT5640_MIC1_OVTH_600UA (0x0 << 9) 1282997b0520SBard Liao #define RT5640_MIC1_OVTH_1500UA (0x1 << 9) 1283997b0520SBard Liao #define RT5640_MIC1_OVTH_2000UA (0x2 << 9) 1284997b0520SBard Liao #define RT5640_MIC2_OVCD_MASK (0x1 << 8) 1285997b0520SBard Liao #define RT5640_MIC2_OVCD_SFT 8 1286997b0520SBard Liao #define RT5640_MIC2_OVCD_DIS (0x0 << 8) 1287997b0520SBard Liao #define RT5640_MIC2_OVCD_EN (0x1 << 8) 1288997b0520SBard Liao #define RT5640_MIC2_OVTH_MASK (0x3 << 6) 1289997b0520SBard Liao #define RT5640_MIC2_OVTH_SFT 6 1290997b0520SBard Liao #define RT5640_MIC2_OVTH_600UA (0x0 << 6) 1291997b0520SBard Liao #define RT5640_MIC2_OVTH_1500UA (0x1 << 6) 1292997b0520SBard Liao #define RT5640_MIC2_OVTH_2000UA (0x2 << 6) 1293997b0520SBard Liao #define RT5640_PWR_MB_MASK (0x1 << 5) 1294997b0520SBard Liao #define RT5640_PWR_MB_SFT 5 1295997b0520SBard Liao #define RT5640_PWR_MB_PD (0x0 << 5) 1296997b0520SBard Liao #define RT5640_PWR_MB_PU (0x1 << 5) 1297997b0520SBard Liao #define RT5640_PWR_CLK25M_MASK (0x1 << 4) 1298997b0520SBard Liao #define RT5640_PWR_CLK25M_SFT 4 1299997b0520SBard Liao #define RT5640_PWR_CLK25M_PD (0x0 << 4) 1300997b0520SBard Liao #define RT5640_PWR_CLK25M_PU (0x1 << 4) 1301997b0520SBard Liao 1302997b0520SBard Liao /* EQ Control 1 (0xb0) */ 1303997b0520SBard Liao #define RT5640_EQ_SRC_MASK (0x1 << 15) 1304997b0520SBard Liao #define RT5640_EQ_SRC_SFT 15 1305997b0520SBard Liao #define RT5640_EQ_SRC_DAC (0x0 << 15) 1306997b0520SBard Liao #define RT5640_EQ_SRC_ADC (0x1 << 15) 1307997b0520SBard Liao #define RT5640_EQ_UPD (0x1 << 14) 1308997b0520SBard Liao #define RT5640_EQ_UPD_BIT 14 1309997b0520SBard Liao #define RT5640_EQ_CD_MASK (0x1 << 13) 1310997b0520SBard Liao #define RT5640_EQ_CD_SFT 13 1311997b0520SBard Liao #define RT5640_EQ_CD_DIS (0x0 << 13) 1312997b0520SBard Liao #define RT5640_EQ_CD_EN (0x1 << 13) 1313997b0520SBard Liao #define RT5640_EQ_DITH_MASK (0x3 << 8) 1314997b0520SBard Liao #define RT5640_EQ_DITH_SFT 8 1315997b0520SBard Liao #define RT5640_EQ_DITH_NOR (0x0 << 8) 1316997b0520SBard Liao #define RT5640_EQ_DITH_LSB (0x1 << 8) 1317997b0520SBard Liao #define RT5640_EQ_DITH_LSB_1 (0x2 << 8) 1318997b0520SBard Liao #define RT5640_EQ_DITH_LSB_2 (0x3 << 8) 1319997b0520SBard Liao 1320997b0520SBard Liao /* EQ Control 2 (0xb1) */ 1321997b0520SBard Liao #define RT5640_EQ_HPF1_M_MASK (0x1 << 8) 1322997b0520SBard Liao #define RT5640_EQ_HPF1_M_SFT 8 1323997b0520SBard Liao #define RT5640_EQ_HPF1_M_HI (0x0 << 8) 1324997b0520SBard Liao #define RT5640_EQ_HPF1_M_1ST (0x1 << 8) 1325997b0520SBard Liao #define RT5640_EQ_LPF1_M_MASK (0x1 << 7) 1326997b0520SBard Liao #define RT5640_EQ_LPF1_M_SFT 7 1327997b0520SBard Liao #define RT5640_EQ_LPF1_M_LO (0x0 << 7) 1328997b0520SBard Liao #define RT5640_EQ_LPF1_M_1ST (0x1 << 7) 1329997b0520SBard Liao #define RT5640_EQ_HPF2_MASK (0x1 << 6) 1330997b0520SBard Liao #define RT5640_EQ_HPF2_SFT 6 1331997b0520SBard Liao #define RT5640_EQ_HPF2_DIS (0x0 << 6) 1332997b0520SBard Liao #define RT5640_EQ_HPF2_EN (0x1 << 6) 1333997b0520SBard Liao #define RT5640_EQ_HPF1_MASK (0x1 << 5) 1334997b0520SBard Liao #define RT5640_EQ_HPF1_SFT 5 1335997b0520SBard Liao #define RT5640_EQ_HPF1_DIS (0x0 << 5) 1336997b0520SBard Liao #define RT5640_EQ_HPF1_EN (0x1 << 5) 1337997b0520SBard Liao #define RT5640_EQ_BPF4_MASK (0x1 << 4) 1338997b0520SBard Liao #define RT5640_EQ_BPF4_SFT 4 1339997b0520SBard Liao #define RT5640_EQ_BPF4_DIS (0x0 << 4) 1340997b0520SBard Liao #define RT5640_EQ_BPF4_EN (0x1 << 4) 1341997b0520SBard Liao #define RT5640_EQ_BPF3_MASK (0x1 << 3) 1342997b0520SBard Liao #define RT5640_EQ_BPF3_SFT 3 1343997b0520SBard Liao #define RT5640_EQ_BPF3_DIS (0x0 << 3) 1344997b0520SBard Liao #define RT5640_EQ_BPF3_EN (0x1 << 3) 1345997b0520SBard Liao #define RT5640_EQ_BPF2_MASK (0x1 << 2) 1346997b0520SBard Liao #define RT5640_EQ_BPF2_SFT 2 1347997b0520SBard Liao #define RT5640_EQ_BPF2_DIS (0x0 << 2) 1348997b0520SBard Liao #define RT5640_EQ_BPF2_EN (0x1 << 2) 1349997b0520SBard Liao #define RT5640_EQ_BPF1_MASK (0x1 << 1) 1350997b0520SBard Liao #define RT5640_EQ_BPF1_SFT 1 1351997b0520SBard Liao #define RT5640_EQ_BPF1_DIS (0x0 << 1) 1352997b0520SBard Liao #define RT5640_EQ_BPF1_EN (0x1 << 1) 1353997b0520SBard Liao #define RT5640_EQ_LPF_MASK (0x1) 1354997b0520SBard Liao #define RT5640_EQ_LPF_SFT 0 1355997b0520SBard Liao #define RT5640_EQ_LPF_DIS (0x0) 1356997b0520SBard Liao #define RT5640_EQ_LPF_EN (0x1) 1357997b0520SBard Liao 1358997b0520SBard Liao /* Memory Test (0xb2) */ 1359997b0520SBard Liao #define RT5640_MT_MASK (0x1 << 15) 1360997b0520SBard Liao #define RT5640_MT_SFT 15 1361997b0520SBard Liao #define RT5640_MT_DIS (0x0 << 15) 1362997b0520SBard Liao #define RT5640_MT_EN (0x1 << 15) 1363997b0520SBard Liao 1364997b0520SBard Liao /* DRC/AGC Control 1 (0xb4) */ 1365997b0520SBard Liao #define RT5640_DRC_AGC_P_MASK (0x1 << 15) 1366997b0520SBard Liao #define RT5640_DRC_AGC_P_SFT 15 1367997b0520SBard Liao #define RT5640_DRC_AGC_P_DAC (0x0 << 15) 1368997b0520SBard Liao #define RT5640_DRC_AGC_P_ADC (0x1 << 15) 1369997b0520SBard Liao #define RT5640_DRC_AGC_MASK (0x1 << 14) 1370997b0520SBard Liao #define RT5640_DRC_AGC_SFT 14 1371997b0520SBard Liao #define RT5640_DRC_AGC_DIS (0x0 << 14) 1372997b0520SBard Liao #define RT5640_DRC_AGC_EN (0x1 << 14) 1373997b0520SBard Liao #define RT5640_DRC_AGC_UPD (0x1 << 13) 1374997b0520SBard Liao #define RT5640_DRC_AGC_UPD_BIT 13 1375997b0520SBard Liao #define RT5640_DRC_AGC_AR_MASK (0x1f << 8) 1376997b0520SBard Liao #define RT5640_DRC_AGC_AR_SFT 8 1377997b0520SBard Liao #define RT5640_DRC_AGC_R_MASK (0x7 << 5) 1378997b0520SBard Liao #define RT5640_DRC_AGC_R_SFT 5 1379997b0520SBard Liao #define RT5640_DRC_AGC_R_48K (0x1 << 5) 1380997b0520SBard Liao #define RT5640_DRC_AGC_R_96K (0x2 << 5) 1381997b0520SBard Liao #define RT5640_DRC_AGC_R_192K (0x3 << 5) 1382997b0520SBard Liao #define RT5640_DRC_AGC_R_441K (0x5 << 5) 1383997b0520SBard Liao #define RT5640_DRC_AGC_R_882K (0x6 << 5) 1384997b0520SBard Liao #define RT5640_DRC_AGC_R_1764K (0x7 << 5) 1385997b0520SBard Liao #define RT5640_DRC_AGC_RC_MASK (0x1f) 1386997b0520SBard Liao #define RT5640_DRC_AGC_RC_SFT 0 1387997b0520SBard Liao 1388997b0520SBard Liao /* DRC/AGC Control 2 (0xb5) */ 1389997b0520SBard Liao #define RT5640_DRC_AGC_POB_MASK (0x3f << 8) 1390997b0520SBard Liao #define RT5640_DRC_AGC_POB_SFT 8 1391997b0520SBard Liao #define RT5640_DRC_AGC_CP_MASK (0x1 << 7) 1392997b0520SBard Liao #define RT5640_DRC_AGC_CP_SFT 7 1393997b0520SBard Liao #define RT5640_DRC_AGC_CP_DIS (0x0 << 7) 1394997b0520SBard Liao #define RT5640_DRC_AGC_CP_EN (0x1 << 7) 1395997b0520SBard Liao #define RT5640_DRC_AGC_CPR_MASK (0x3 << 5) 1396997b0520SBard Liao #define RT5640_DRC_AGC_CPR_SFT 5 1397997b0520SBard Liao #define RT5640_DRC_AGC_CPR_1_1 (0x0 << 5) 1398997b0520SBard Liao #define RT5640_DRC_AGC_CPR_1_2 (0x1 << 5) 1399997b0520SBard Liao #define RT5640_DRC_AGC_CPR_1_3 (0x2 << 5) 1400997b0520SBard Liao #define RT5640_DRC_AGC_CPR_1_4 (0x3 << 5) 1401997b0520SBard Liao #define RT5640_DRC_AGC_PRB_MASK (0x1f) 1402997b0520SBard Liao #define RT5640_DRC_AGC_PRB_SFT 0 1403997b0520SBard Liao 1404997b0520SBard Liao /* DRC/AGC Control 3 (0xb6) */ 1405997b0520SBard Liao #define RT5640_DRC_AGC_NGB_MASK (0xf << 12) 1406997b0520SBard Liao #define RT5640_DRC_AGC_NGB_SFT 12 1407997b0520SBard Liao #define RT5640_DRC_AGC_TAR_MASK (0x1f << 7) 1408997b0520SBard Liao #define RT5640_DRC_AGC_TAR_SFT 7 1409997b0520SBard Liao #define RT5640_DRC_AGC_NG_MASK (0x1 << 6) 1410997b0520SBard Liao #define RT5640_DRC_AGC_NG_SFT 6 1411997b0520SBard Liao #define RT5640_DRC_AGC_NG_DIS (0x0 << 6) 1412997b0520SBard Liao #define RT5640_DRC_AGC_NG_EN (0x1 << 6) 1413997b0520SBard Liao #define RT5640_DRC_AGC_NGH_MASK (0x1 << 5) 1414997b0520SBard Liao #define RT5640_DRC_AGC_NGH_SFT 5 1415997b0520SBard Liao #define RT5640_DRC_AGC_NGH_DIS (0x0 << 5) 1416997b0520SBard Liao #define RT5640_DRC_AGC_NGH_EN (0x1 << 5) 1417997b0520SBard Liao #define RT5640_DRC_AGC_NGT_MASK (0x1f) 1418997b0520SBard Liao #define RT5640_DRC_AGC_NGT_SFT 0 1419997b0520SBard Liao 1420997b0520SBard Liao /* ANC Control 1 (0xb8) */ 1421997b0520SBard Liao #define RT5640_ANC_M_MASK (0x1 << 15) 1422997b0520SBard Liao #define RT5640_ANC_M_SFT 15 1423997b0520SBard Liao #define RT5640_ANC_M_NOR (0x0 << 15) 1424997b0520SBard Liao #define RT5640_ANC_M_REV (0x1 << 15) 1425997b0520SBard Liao #define RT5640_ANC_MASK (0x1 << 14) 1426997b0520SBard Liao #define RT5640_ANC_SFT 14 1427997b0520SBard Liao #define RT5640_ANC_DIS (0x0 << 14) 1428997b0520SBard Liao #define RT5640_ANC_EN (0x1 << 14) 1429997b0520SBard Liao #define RT5640_ANC_MD_MASK (0x3 << 12) 1430997b0520SBard Liao #define RT5640_ANC_MD_SFT 12 1431997b0520SBard Liao #define RT5640_ANC_MD_DIS (0x0 << 12) 1432997b0520SBard Liao #define RT5640_ANC_MD_67MS (0x1 << 12) 1433997b0520SBard Liao #define RT5640_ANC_MD_267MS (0x2 << 12) 1434997b0520SBard Liao #define RT5640_ANC_MD_1067MS (0x3 << 12) 1435997b0520SBard Liao #define RT5640_ANC_SN_MASK (0x1 << 11) 1436997b0520SBard Liao #define RT5640_ANC_SN_SFT 11 1437997b0520SBard Liao #define RT5640_ANC_SN_DIS (0x0 << 11) 1438997b0520SBard Liao #define RT5640_ANC_SN_EN (0x1 << 11) 1439997b0520SBard Liao #define RT5640_ANC_CLK_MASK (0x1 << 10) 1440997b0520SBard Liao #define RT5640_ANC_CLK_SFT 10 1441997b0520SBard Liao #define RT5640_ANC_CLK_ANC (0x0 << 10) 1442997b0520SBard Liao #define RT5640_ANC_CLK_REG (0x1 << 10) 1443997b0520SBard Liao #define RT5640_ANC_ZCD_MASK (0x3 << 8) 1444997b0520SBard Liao #define RT5640_ANC_ZCD_SFT 8 1445997b0520SBard Liao #define RT5640_ANC_ZCD_DIS (0x0 << 8) 1446997b0520SBard Liao #define RT5640_ANC_ZCD_T1 (0x1 << 8) 1447997b0520SBard Liao #define RT5640_ANC_ZCD_T2 (0x2 << 8) 1448997b0520SBard Liao #define RT5640_ANC_ZCD_WT (0x3 << 8) 1449997b0520SBard Liao #define RT5640_ANC_CS_MASK (0x1 << 7) 1450997b0520SBard Liao #define RT5640_ANC_CS_SFT 7 1451997b0520SBard Liao #define RT5640_ANC_CS_DIS (0x0 << 7) 1452997b0520SBard Liao #define RT5640_ANC_CS_EN (0x1 << 7) 1453997b0520SBard Liao #define RT5640_ANC_SW_MASK (0x1 << 6) 1454997b0520SBard Liao #define RT5640_ANC_SW_SFT 6 1455997b0520SBard Liao #define RT5640_ANC_SW_NOR (0x0 << 6) 1456997b0520SBard Liao #define RT5640_ANC_SW_AUTO (0x1 << 6) 1457997b0520SBard Liao #define RT5640_ANC_CO_L_MASK (0x3f) 1458997b0520SBard Liao #define RT5640_ANC_CO_L_SFT 0 1459997b0520SBard Liao 1460997b0520SBard Liao /* ANC Control 2 (0xb6) */ 1461997b0520SBard Liao #define RT5640_ANC_FG_R_MASK (0xf << 12) 1462997b0520SBard Liao #define RT5640_ANC_FG_R_SFT 12 1463997b0520SBard Liao #define RT5640_ANC_FG_L_MASK (0xf << 8) 1464997b0520SBard Liao #define RT5640_ANC_FG_L_SFT 8 1465997b0520SBard Liao #define RT5640_ANC_CG_R_MASK (0xf << 4) 1466997b0520SBard Liao #define RT5640_ANC_CG_R_SFT 4 1467997b0520SBard Liao #define RT5640_ANC_CG_L_MASK (0xf) 1468997b0520SBard Liao #define RT5640_ANC_CG_L_SFT 0 1469997b0520SBard Liao 1470997b0520SBard Liao /* ANC Control 3 (0xb6) */ 1471997b0520SBard Liao #define RT5640_ANC_CD_MASK (0x1 << 6) 1472997b0520SBard Liao #define RT5640_ANC_CD_SFT 6 1473997b0520SBard Liao #define RT5640_ANC_CD_BOTH (0x0 << 6) 1474997b0520SBard Liao #define RT5640_ANC_CD_IND (0x1 << 6) 1475997b0520SBard Liao #define RT5640_ANC_CO_R_MASK (0x3f) 1476997b0520SBard Liao #define RT5640_ANC_CO_R_SFT 0 1477997b0520SBard Liao 1478997b0520SBard Liao /* Jack Detect Control (0xbb) */ 1479997b0520SBard Liao #define RT5640_JD_MASK (0x7 << 13) 1480997b0520SBard Liao #define RT5640_JD_SFT 13 1481997b0520SBard Liao #define RT5640_JD_DIS (0x0 << 13) 1482997b0520SBard Liao #define RT5640_JD_GPIO1 (0x1 << 13) 1483997b0520SBard Liao #define RT5640_JD_JD1_IN4P (0x2 << 13) 1484997b0520SBard Liao #define RT5640_JD_JD2_IN4N (0x3 << 13) 1485997b0520SBard Liao #define RT5640_JD_GPIO2 (0x4 << 13) 1486997b0520SBard Liao #define RT5640_JD_GPIO3 (0x5 << 13) 1487997b0520SBard Liao #define RT5640_JD_GPIO4 (0x6 << 13) 1488997b0520SBard Liao #define RT5640_JD_HP_MASK (0x1 << 11) 1489997b0520SBard Liao #define RT5640_JD_HP_SFT 11 1490997b0520SBard Liao #define RT5640_JD_HP_DIS (0x0 << 11) 1491997b0520SBard Liao #define RT5640_JD_HP_EN (0x1 << 11) 1492997b0520SBard Liao #define RT5640_JD_HP_TRG_MASK (0x1 << 10) 1493997b0520SBard Liao #define RT5640_JD_HP_TRG_SFT 10 1494997b0520SBard Liao #define RT5640_JD_HP_TRG_LO (0x0 << 10) 1495997b0520SBard Liao #define RT5640_JD_HP_TRG_HI (0x1 << 10) 1496997b0520SBard Liao #define RT5640_JD_SPL_MASK (0x1 << 9) 1497997b0520SBard Liao #define RT5640_JD_SPL_SFT 9 1498997b0520SBard Liao #define RT5640_JD_SPL_DIS (0x0 << 9) 1499997b0520SBard Liao #define RT5640_JD_SPL_EN (0x1 << 9) 1500997b0520SBard Liao #define RT5640_JD_SPL_TRG_MASK (0x1 << 8) 1501997b0520SBard Liao #define RT5640_JD_SPL_TRG_SFT 8 1502997b0520SBard Liao #define RT5640_JD_SPL_TRG_LO (0x0 << 8) 1503997b0520SBard Liao #define RT5640_JD_SPL_TRG_HI (0x1 << 8) 1504997b0520SBard Liao #define RT5640_JD_SPR_MASK (0x1 << 7) 1505997b0520SBard Liao #define RT5640_JD_SPR_SFT 7 1506997b0520SBard Liao #define RT5640_JD_SPR_DIS (0x0 << 7) 1507997b0520SBard Liao #define RT5640_JD_SPR_EN (0x1 << 7) 1508997b0520SBard Liao #define RT5640_JD_SPR_TRG_MASK (0x1 << 6) 1509997b0520SBard Liao #define RT5640_JD_SPR_TRG_SFT 6 1510997b0520SBard Liao #define RT5640_JD_SPR_TRG_LO (0x0 << 6) 1511997b0520SBard Liao #define RT5640_JD_SPR_TRG_HI (0x1 << 6) 1512997b0520SBard Liao #define RT5640_JD_MO_MASK (0x1 << 5) 1513997b0520SBard Liao #define RT5640_JD_MO_SFT 5 1514997b0520SBard Liao #define RT5640_JD_MO_DIS (0x0 << 5) 1515997b0520SBard Liao #define RT5640_JD_MO_EN (0x1 << 5) 1516997b0520SBard Liao #define RT5640_JD_MO_TRG_MASK (0x1 << 4) 1517997b0520SBard Liao #define RT5640_JD_MO_TRG_SFT 4 1518997b0520SBard Liao #define RT5640_JD_MO_TRG_LO (0x0 << 4) 1519997b0520SBard Liao #define RT5640_JD_MO_TRG_HI (0x1 << 4) 1520997b0520SBard Liao #define RT5640_JD_LO_MASK (0x1 << 3) 1521997b0520SBard Liao #define RT5640_JD_LO_SFT 3 1522997b0520SBard Liao #define RT5640_JD_LO_DIS (0x0 << 3) 1523997b0520SBard Liao #define RT5640_JD_LO_EN (0x1 << 3) 1524997b0520SBard Liao #define RT5640_JD_LO_TRG_MASK (0x1 << 2) 1525997b0520SBard Liao #define RT5640_JD_LO_TRG_SFT 2 1526997b0520SBard Liao #define RT5640_JD_LO_TRG_LO (0x0 << 2) 1527997b0520SBard Liao #define RT5640_JD_LO_TRG_HI (0x1 << 2) 1528997b0520SBard Liao #define RT5640_JD1_IN4P_MASK (0x1 << 1) 1529997b0520SBard Liao #define RT5640_JD1_IN4P_SFT 1 1530997b0520SBard Liao #define RT5640_JD1_IN4P_DIS (0x0 << 1) 1531997b0520SBard Liao #define RT5640_JD1_IN4P_EN (0x1 << 1) 1532997b0520SBard Liao #define RT5640_JD2_IN4N_MASK (0x1) 1533997b0520SBard Liao #define RT5640_JD2_IN4N_SFT 0 1534997b0520SBard Liao #define RT5640_JD2_IN4N_DIS (0x0) 1535997b0520SBard Liao #define RT5640_JD2_IN4N_EN (0x1) 1536997b0520SBard Liao 1537997b0520SBard Liao /* Jack detect for ANC (0xbc) */ 1538997b0520SBard Liao #define RT5640_ANC_DET_MASK (0x3 << 4) 1539997b0520SBard Liao #define RT5640_ANC_DET_SFT 4 1540997b0520SBard Liao #define RT5640_ANC_DET_DIS (0x0 << 4) 1541997b0520SBard Liao #define RT5640_ANC_DET_MB1 (0x1 << 4) 1542997b0520SBard Liao #define RT5640_ANC_DET_MB2 (0x2 << 4) 1543997b0520SBard Liao #define RT5640_ANC_DET_JD (0x3 << 4) 1544997b0520SBard Liao #define RT5640_AD_TRG_MASK (0x1 << 3) 1545997b0520SBard Liao #define RT5640_AD_TRG_SFT 3 1546997b0520SBard Liao #define RT5640_AD_TRG_LO (0x0 << 3) 1547997b0520SBard Liao #define RT5640_AD_TRG_HI (0x1 << 3) 1548997b0520SBard Liao #define RT5640_ANCM_DET_MASK (0x3 << 4) 1549997b0520SBard Liao #define RT5640_ANCM_DET_SFT 4 1550997b0520SBard Liao #define RT5640_ANCM_DET_DIS (0x0 << 4) 1551997b0520SBard Liao #define RT5640_ANCM_DET_MB1 (0x1 << 4) 1552997b0520SBard Liao #define RT5640_ANCM_DET_MB2 (0x2 << 4) 1553997b0520SBard Liao #define RT5640_ANCM_DET_JD (0x3 << 4) 1554997b0520SBard Liao #define RT5640_AMD_TRG_MASK (0x1 << 3) 1555997b0520SBard Liao #define RT5640_AMD_TRG_SFT 3 1556997b0520SBard Liao #define RT5640_AMD_TRG_LO (0x0 << 3) 1557997b0520SBard Liao #define RT5640_AMD_TRG_HI (0x1 << 3) 1558997b0520SBard Liao 1559997b0520SBard Liao /* IRQ Control 1 (0xbd) */ 1560997b0520SBard Liao #define RT5640_IRQ_JD_MASK (0x1 << 15) 1561997b0520SBard Liao #define RT5640_IRQ_JD_SFT 15 1562997b0520SBard Liao #define RT5640_IRQ_JD_BP (0x0 << 15) 1563997b0520SBard Liao #define RT5640_IRQ_JD_NOR (0x1 << 15) 1564997b0520SBard Liao #define RT5640_IRQ_OT_MASK (0x1 << 14) 1565997b0520SBard Liao #define RT5640_IRQ_OT_SFT 14 1566997b0520SBard Liao #define RT5640_IRQ_OT_BP (0x0 << 14) 1567997b0520SBard Liao #define RT5640_IRQ_OT_NOR (0x1 << 14) 1568997b0520SBard Liao #define RT5640_JD_STKY_MASK (0x1 << 13) 1569997b0520SBard Liao #define RT5640_JD_STKY_SFT 13 1570997b0520SBard Liao #define RT5640_JD_STKY_DIS (0x0 << 13) 1571997b0520SBard Liao #define RT5640_JD_STKY_EN (0x1 << 13) 1572997b0520SBard Liao #define RT5640_OT_STKY_MASK (0x1 << 12) 1573997b0520SBard Liao #define RT5640_OT_STKY_SFT 12 1574997b0520SBard Liao #define RT5640_OT_STKY_DIS (0x0 << 12) 1575997b0520SBard Liao #define RT5640_OT_STKY_EN (0x1 << 12) 1576997b0520SBard Liao #define RT5640_JD_P_MASK (0x1 << 11) 1577997b0520SBard Liao #define RT5640_JD_P_SFT 11 1578997b0520SBard Liao #define RT5640_JD_P_NOR (0x0 << 11) 1579997b0520SBard Liao #define RT5640_JD_P_INV (0x1 << 11) 1580997b0520SBard Liao #define RT5640_OT_P_MASK (0x1 << 10) 1581997b0520SBard Liao #define RT5640_OT_P_SFT 10 1582997b0520SBard Liao #define RT5640_OT_P_NOR (0x0 << 10) 1583997b0520SBard Liao #define RT5640_OT_P_INV (0x1 << 10) 1584997b0520SBard Liao 1585997b0520SBard Liao /* IRQ Control 2 (0xbe) */ 1586997b0520SBard Liao #define RT5640_IRQ_MB1_OC_MASK (0x1 << 15) 1587997b0520SBard Liao #define RT5640_IRQ_MB1_OC_SFT 15 1588997b0520SBard Liao #define RT5640_IRQ_MB1_OC_BP (0x0 << 15) 1589997b0520SBard Liao #define RT5640_IRQ_MB1_OC_NOR (0x1 << 15) 1590997b0520SBard Liao #define RT5640_IRQ_MB2_OC_MASK (0x1 << 14) 1591997b0520SBard Liao #define RT5640_IRQ_MB2_OC_SFT 14 1592997b0520SBard Liao #define RT5640_IRQ_MB2_OC_BP (0x0 << 14) 1593997b0520SBard Liao #define RT5640_IRQ_MB2_OC_NOR (0x1 << 14) 1594997b0520SBard Liao #define RT5640_MB1_OC_STKY_MASK (0x1 << 11) 1595997b0520SBard Liao #define RT5640_MB1_OC_STKY_SFT 11 1596997b0520SBard Liao #define RT5640_MB1_OC_STKY_DIS (0x0 << 11) 1597997b0520SBard Liao #define RT5640_MB1_OC_STKY_EN (0x1 << 11) 1598997b0520SBard Liao #define RT5640_MB2_OC_STKY_MASK (0x1 << 10) 1599997b0520SBard Liao #define RT5640_MB2_OC_STKY_SFT 10 1600997b0520SBard Liao #define RT5640_MB2_OC_STKY_DIS (0x0 << 10) 1601997b0520SBard Liao #define RT5640_MB2_OC_STKY_EN (0x1 << 10) 1602997b0520SBard Liao #define RT5640_MB1_OC_P_MASK (0x1 << 7) 1603997b0520SBard Liao #define RT5640_MB1_OC_P_SFT 7 1604997b0520SBard Liao #define RT5640_MB1_OC_P_NOR (0x0 << 7) 1605997b0520SBard Liao #define RT5640_MB1_OC_P_INV (0x1 << 7) 1606997b0520SBard Liao #define RT5640_MB2_OC_P_MASK (0x1 << 6) 1607997b0520SBard Liao #define RT5640_MB2_OC_P_SFT 6 1608997b0520SBard Liao #define RT5640_MB2_OC_P_NOR (0x0 << 6) 1609997b0520SBard Liao #define RT5640_MB2_OC_P_INV (0x1 << 6) 16108210804bSHans de Goede #define RT5640_MB1_OC_STATUS (0x1 << 3) 16118210804bSHans de Goede #define RT5640_MB1_OC_STATUS_SFT 3 16128210804bSHans de Goede #define RT5640_MB2_OC_STATUS (0x1 << 2) 16138210804bSHans de Goede #define RT5640_MB2_OC_STATUS_SFT 2 16148210804bSHans de Goede 16158210804bSHans de Goede /* GPIO and Internal Status (0xbf) */ 16168210804bSHans de Goede #define RT5640_GPIO1_STATUS (0x1 << 8) 16178210804bSHans de Goede #define RT5640_GPIO2_STATUS (0x1 << 7) 16188210804bSHans de Goede #define RT5640_JD_STATUS (0x1 << 4) 16198210804bSHans de Goede #define RT5640_OVT_STATUS (0x1 << 3) 16208210804bSHans de Goede #define RT5640_CLS_D_OVCD_STATUS (0x1 << 0) 1621997b0520SBard Liao 1622997b0520SBard Liao /* GPIO Control 1 (0xc0) */ 1623997b0520SBard Liao #define RT5640_GP1_PIN_MASK (0x1 << 15) 1624997b0520SBard Liao #define RT5640_GP1_PIN_SFT 15 1625997b0520SBard Liao #define RT5640_GP1_PIN_GPIO1 (0x0 << 15) 1626997b0520SBard Liao #define RT5640_GP1_PIN_IRQ (0x1 << 15) 1627997b0520SBard Liao #define RT5640_GP2_PIN_MASK (0x1 << 14) 1628997b0520SBard Liao #define RT5640_GP2_PIN_SFT 14 1629997b0520SBard Liao #define RT5640_GP2_PIN_GPIO2 (0x0 << 14) 1630997b0520SBard Liao #define RT5640_GP2_PIN_DMIC1_SCL (0x1 << 14) 1631997b0520SBard Liao #define RT5640_GP3_PIN_MASK (0x3 << 12) 1632997b0520SBard Liao #define RT5640_GP3_PIN_SFT 12 1633997b0520SBard Liao #define RT5640_GP3_PIN_GPIO3 (0x0 << 12) 1634997b0520SBard Liao #define RT5640_GP3_PIN_DMIC1_SDA (0x1 << 12) 1635997b0520SBard Liao #define RT5640_GP3_PIN_IRQ (0x2 << 12) 1636997b0520SBard Liao #define RT5640_GP4_PIN_MASK (0x1 << 11) 1637997b0520SBard Liao #define RT5640_GP4_PIN_SFT 11 1638997b0520SBard Liao #define RT5640_GP4_PIN_GPIO4 (0x0 << 11) 1639997b0520SBard Liao #define RT5640_GP4_PIN_DMIC2_SDA (0x1 << 11) 1640997b0520SBard Liao #define RT5640_DP_SIG_MASK (0x1 << 10) 1641997b0520SBard Liao #define RT5640_DP_SIG_SFT 10 1642997b0520SBard Liao #define RT5640_DP_SIG_TEST (0x0 << 10) 1643997b0520SBard Liao #define RT5640_DP_SIG_AP (0x1 << 10) 1644997b0520SBard Liao #define RT5640_GPIO_M_MASK (0x1 << 9) 1645997b0520SBard Liao #define RT5640_GPIO_M_SFT 9 1646997b0520SBard Liao #define RT5640_GPIO_M_FLT (0x0 << 9) 1647997b0520SBard Liao #define RT5640_GPIO_M_PH (0x1 << 9) 1648997b0520SBard Liao 1649997b0520SBard Liao /* GPIO Control 3 (0xc2) */ 1650997b0520SBard Liao #define RT5640_GP4_PF_MASK (0x1 << 11) 1651997b0520SBard Liao #define RT5640_GP4_PF_SFT 11 1652997b0520SBard Liao #define RT5640_GP4_PF_IN (0x0 << 11) 1653997b0520SBard Liao #define RT5640_GP4_PF_OUT (0x1 << 11) 1654997b0520SBard Liao #define RT5640_GP4_OUT_MASK (0x1 << 10) 1655997b0520SBard Liao #define RT5640_GP4_OUT_SFT 10 1656997b0520SBard Liao #define RT5640_GP4_OUT_LO (0x0 << 10) 1657997b0520SBard Liao #define RT5640_GP4_OUT_HI (0x1 << 10) 1658997b0520SBard Liao #define RT5640_GP4_P_MASK (0x1 << 9) 1659997b0520SBard Liao #define RT5640_GP4_P_SFT 9 1660997b0520SBard Liao #define RT5640_GP4_P_NOR (0x0 << 9) 1661997b0520SBard Liao #define RT5640_GP4_P_INV (0x1 << 9) 1662997b0520SBard Liao #define RT5640_GP3_PF_MASK (0x1 << 8) 1663997b0520SBard Liao #define RT5640_GP3_PF_SFT 8 1664997b0520SBard Liao #define RT5640_GP3_PF_IN (0x0 << 8) 1665997b0520SBard Liao #define RT5640_GP3_PF_OUT (0x1 << 8) 1666997b0520SBard Liao #define RT5640_GP3_OUT_MASK (0x1 << 7) 1667997b0520SBard Liao #define RT5640_GP3_OUT_SFT 7 1668997b0520SBard Liao #define RT5640_GP3_OUT_LO (0x0 << 7) 1669997b0520SBard Liao #define RT5640_GP3_OUT_HI (0x1 << 7) 1670997b0520SBard Liao #define RT5640_GP3_P_MASK (0x1 << 6) 1671997b0520SBard Liao #define RT5640_GP3_P_SFT 6 1672997b0520SBard Liao #define RT5640_GP3_P_NOR (0x0 << 6) 1673997b0520SBard Liao #define RT5640_GP3_P_INV (0x1 << 6) 1674997b0520SBard Liao #define RT5640_GP2_PF_MASK (0x1 << 5) 1675997b0520SBard Liao #define RT5640_GP2_PF_SFT 5 1676997b0520SBard Liao #define RT5640_GP2_PF_IN (0x0 << 5) 1677997b0520SBard Liao #define RT5640_GP2_PF_OUT (0x1 << 5) 1678997b0520SBard Liao #define RT5640_GP2_OUT_MASK (0x1 << 4) 1679997b0520SBard Liao #define RT5640_GP2_OUT_SFT 4 1680997b0520SBard Liao #define RT5640_GP2_OUT_LO (0x0 << 4) 1681997b0520SBard Liao #define RT5640_GP2_OUT_HI (0x1 << 4) 1682997b0520SBard Liao #define RT5640_GP2_P_MASK (0x1 << 3) 1683997b0520SBard Liao #define RT5640_GP2_P_SFT 3 1684997b0520SBard Liao #define RT5640_GP2_P_NOR (0x0 << 3) 1685997b0520SBard Liao #define RT5640_GP2_P_INV (0x1 << 3) 1686997b0520SBard Liao #define RT5640_GP1_PF_MASK (0x1 << 2) 1687997b0520SBard Liao #define RT5640_GP1_PF_SFT 2 1688997b0520SBard Liao #define RT5640_GP1_PF_IN (0x0 << 2) 1689997b0520SBard Liao #define RT5640_GP1_PF_OUT (0x1 << 2) 1690997b0520SBard Liao #define RT5640_GP1_OUT_MASK (0x1 << 1) 1691997b0520SBard Liao #define RT5640_GP1_OUT_SFT 1 1692997b0520SBard Liao #define RT5640_GP1_OUT_LO (0x0 << 1) 1693997b0520SBard Liao #define RT5640_GP1_OUT_HI (0x1 << 1) 1694997b0520SBard Liao #define RT5640_GP1_P_MASK (0x1) 1695997b0520SBard Liao #define RT5640_GP1_P_SFT 0 1696997b0520SBard Liao #define RT5640_GP1_P_NOR (0x0) 1697997b0520SBard Liao #define RT5640_GP1_P_INV (0x1) 1698997b0520SBard Liao 1699997b0520SBard Liao /* FM34-500 Register Control 1 (0xc4) */ 1700997b0520SBard Liao #define RT5640_DSP_ADD_SFT 0 1701997b0520SBard Liao 1702997b0520SBard Liao /* FM34-500 Register Control 2 (0xc5) */ 1703997b0520SBard Liao #define RT5640_DSP_DAT_SFT 0 1704997b0520SBard Liao 1705997b0520SBard Liao /* FM34-500 Register Control 3 (0xc6) */ 1706997b0520SBard Liao #define RT5640_DSP_BUSY_MASK (0x1 << 15) 1707997b0520SBard Liao #define RT5640_DSP_BUSY_BIT 15 1708997b0520SBard Liao #define RT5640_DSP_DS_MASK (0x1 << 14) 1709997b0520SBard Liao #define RT5640_DSP_DS_SFT 14 1710997b0520SBard Liao #define RT5640_DSP_DS_FM3010 (0x1 << 14) 1711997b0520SBard Liao #define RT5640_DSP_DS_TEMP (0x1 << 14) 1712997b0520SBard Liao #define RT5640_DSP_CLK_MASK (0x3 << 12) 1713997b0520SBard Liao #define RT5640_DSP_CLK_SFT 12 1714997b0520SBard Liao #define RT5640_DSP_CLK_384K (0x0 << 12) 1715997b0520SBard Liao #define RT5640_DSP_CLK_192K (0x1 << 12) 1716997b0520SBard Liao #define RT5640_DSP_CLK_96K (0x2 << 12) 1717997b0520SBard Liao #define RT5640_DSP_CLK_64K (0x3 << 12) 1718997b0520SBard Liao #define RT5640_DSP_PD_PIN_MASK (0x1 << 11) 1719997b0520SBard Liao #define RT5640_DSP_PD_PIN_SFT 11 1720997b0520SBard Liao #define RT5640_DSP_PD_PIN_LO (0x0 << 11) 1721997b0520SBard Liao #define RT5640_DSP_PD_PIN_HI (0x1 << 11) 1722997b0520SBard Liao #define RT5640_DSP_RST_PIN_MASK (0x1 << 10) 1723997b0520SBard Liao #define RT5640_DSP_RST_PIN_SFT 10 1724997b0520SBard Liao #define RT5640_DSP_RST_PIN_LO (0x0 << 10) 1725997b0520SBard Liao #define RT5640_DSP_RST_PIN_HI (0x1 << 10) 1726997b0520SBard Liao #define RT5640_DSP_R_EN (0x1 << 9) 1727997b0520SBard Liao #define RT5640_DSP_R_EN_BIT 9 1728997b0520SBard Liao #define RT5640_DSP_W_EN (0x1 << 8) 1729997b0520SBard Liao #define RT5640_DSP_W_EN_BIT 8 1730997b0520SBard Liao #define RT5640_DSP_CMD_MASK (0xff) 1731997b0520SBard Liao #define RT5640_DSP_CMD_SFT 0 1732997b0520SBard Liao #define RT5640_DSP_CMD_MW (0x3B) /* Memory Write */ 1733997b0520SBard Liao #define RT5640_DSP_CMD_MR (0x37) /* Memory Read */ 1734997b0520SBard Liao #define RT5640_DSP_CMD_RR (0x60) /* Register Read */ 1735997b0520SBard Liao #define RT5640_DSP_CMD_RW (0x68) /* Register Write */ 1736997b0520SBard Liao 1737997b0520SBard Liao /* Programmable Register Array Control 1 (0xc8) */ 1738997b0520SBard Liao #define RT5640_REG_SEQ_MASK (0xf << 12) 1739997b0520SBard Liao #define RT5640_REG_SEQ_SFT 12 1740997b0520SBard Liao #define RT5640_SEQ1_ST_MASK (0x1 << 11) /*RO*/ 1741997b0520SBard Liao #define RT5640_SEQ1_ST_SFT 11 1742997b0520SBard Liao #define RT5640_SEQ1_ST_RUN (0x0 << 11) 1743997b0520SBard Liao #define RT5640_SEQ1_ST_FIN (0x1 << 11) 1744997b0520SBard Liao #define RT5640_SEQ2_ST_MASK (0x1 << 10) /*RO*/ 1745997b0520SBard Liao #define RT5640_SEQ2_ST_SFT 10 1746997b0520SBard Liao #define RT5640_SEQ2_ST_RUN (0x0 << 10) 1747997b0520SBard Liao #define RT5640_SEQ2_ST_FIN (0x1 << 10) 1748997b0520SBard Liao #define RT5640_REG_LV_MASK (0x1 << 9) 1749997b0520SBard Liao #define RT5640_REG_LV_SFT 9 1750997b0520SBard Liao #define RT5640_REG_LV_MX (0x0 << 9) 1751997b0520SBard Liao #define RT5640_REG_LV_PR (0x1 << 9) 1752997b0520SBard Liao #define RT5640_SEQ_2_PT_MASK (0x1 << 8) 1753997b0520SBard Liao #define RT5640_SEQ_2_PT_BIT 8 1754997b0520SBard Liao #define RT5640_REG_IDX_MASK (0xff) 1755997b0520SBard Liao #define RT5640_REG_IDX_SFT 0 1756997b0520SBard Liao 1757997b0520SBard Liao /* Programmable Register Array Control 2 (0xc9) */ 1758997b0520SBard Liao #define RT5640_REG_DAT_MASK (0xffff) 1759997b0520SBard Liao #define RT5640_REG_DAT_SFT 0 1760997b0520SBard Liao 1761997b0520SBard Liao /* Programmable Register Array Control 3 (0xca) */ 1762997b0520SBard Liao #define RT5640_SEQ_DLY_MASK (0xff << 8) 1763997b0520SBard Liao #define RT5640_SEQ_DLY_SFT 8 1764997b0520SBard Liao #define RT5640_PROG_MASK (0x1 << 7) 1765997b0520SBard Liao #define RT5640_PROG_SFT 7 1766997b0520SBard Liao #define RT5640_PROG_DIS (0x0 << 7) 1767997b0520SBard Liao #define RT5640_PROG_EN (0x1 << 7) 1768997b0520SBard Liao #define RT5640_SEQ1_PT_RUN (0x1 << 6) 1769997b0520SBard Liao #define RT5640_SEQ1_PT_RUN_BIT 6 1770997b0520SBard Liao #define RT5640_SEQ2_PT_RUN (0x1 << 5) 1771997b0520SBard Liao #define RT5640_SEQ2_PT_RUN_BIT 5 1772997b0520SBard Liao 1773997b0520SBard Liao /* Programmable Register Array Control 4 (0xcb) */ 1774997b0520SBard Liao #define RT5640_SEQ1_START_MASK (0xf << 8) 1775997b0520SBard Liao #define RT5640_SEQ1_START_SFT 8 1776997b0520SBard Liao #define RT5640_SEQ1_END_MASK (0xf) 1777997b0520SBard Liao #define RT5640_SEQ1_END_SFT 0 1778997b0520SBard Liao 1779997b0520SBard Liao /* Programmable Register Array Control 5 (0xcc) */ 1780997b0520SBard Liao #define RT5640_SEQ2_START_MASK (0xf << 8) 1781997b0520SBard Liao #define RT5640_SEQ2_START_SFT 8 1782997b0520SBard Liao #define RT5640_SEQ2_END_MASK (0xf) 1783997b0520SBard Liao #define RT5640_SEQ2_END_SFT 0 1784997b0520SBard Liao 1785997b0520SBard Liao /* Scramble Function (0xcd) */ 1786997b0520SBard Liao #define RT5640_SCB_KEY_MASK (0xff) 1787997b0520SBard Liao #define RT5640_SCB_KEY_SFT 0 1788997b0520SBard Liao 1789997b0520SBard Liao /* Scramble Control (0xce) */ 1790997b0520SBard Liao #define RT5640_SCB_SWAP_MASK (0x1 << 15) 1791997b0520SBard Liao #define RT5640_SCB_SWAP_SFT 15 1792997b0520SBard Liao #define RT5640_SCB_SWAP_DIS (0x0 << 15) 1793997b0520SBard Liao #define RT5640_SCB_SWAP_EN (0x1 << 15) 1794997b0520SBard Liao #define RT5640_SCB_MASK (0x1 << 14) 1795997b0520SBard Liao #define RT5640_SCB_SFT 14 1796997b0520SBard Liao #define RT5640_SCB_DIS (0x0 << 14) 1797997b0520SBard Liao #define RT5640_SCB_EN (0x1 << 14) 1798997b0520SBard Liao 1799997b0520SBard Liao /* Baseback Control (0xcf) */ 1800997b0520SBard Liao #define RT5640_BB_MASK (0x1 << 15) 1801997b0520SBard Liao #define RT5640_BB_SFT 15 1802997b0520SBard Liao #define RT5640_BB_DIS (0x0 << 15) 1803997b0520SBard Liao #define RT5640_BB_EN (0x1 << 15) 1804997b0520SBard Liao #define RT5640_BB_CT_MASK (0x7 << 12) 1805997b0520SBard Liao #define RT5640_BB_CT_SFT 12 1806997b0520SBard Liao #define RT5640_BB_CT_A (0x0 << 12) 1807997b0520SBard Liao #define RT5640_BB_CT_B (0x1 << 12) 1808997b0520SBard Liao #define RT5640_BB_CT_C (0x2 << 12) 1809997b0520SBard Liao #define RT5640_BB_CT_D (0x3 << 12) 1810997b0520SBard Liao #define RT5640_M_BB_L_MASK (0x1 << 9) 1811997b0520SBard Liao #define RT5640_M_BB_L_SFT 9 1812997b0520SBard Liao #define RT5640_M_BB_R_MASK (0x1 << 8) 1813997b0520SBard Liao #define RT5640_M_BB_R_SFT 8 1814997b0520SBard Liao #define RT5640_M_BB_HPF_L_MASK (0x1 << 7) 1815997b0520SBard Liao #define RT5640_M_BB_HPF_L_SFT 7 1816997b0520SBard Liao #define RT5640_M_BB_HPF_R_MASK (0x1 << 6) 1817997b0520SBard Liao #define RT5640_M_BB_HPF_R_SFT 6 1818997b0520SBard Liao #define RT5640_G_BB_BST_MASK (0x3f) 1819997b0520SBard Liao #define RT5640_G_BB_BST_SFT 0 1820997b0520SBard Liao 1821997b0520SBard Liao /* MP3 Plus Control 1 (0xd0) */ 1822997b0520SBard Liao #define RT5640_M_MP3_L_MASK (0x1 << 15) 1823997b0520SBard Liao #define RT5640_M_MP3_L_SFT 15 1824997b0520SBard Liao #define RT5640_M_MP3_R_MASK (0x1 << 14) 1825997b0520SBard Liao #define RT5640_M_MP3_R_SFT 14 1826997b0520SBard Liao #define RT5640_M_MP3_MASK (0x1 << 13) 1827997b0520SBard Liao #define RT5640_M_MP3_SFT 13 1828997b0520SBard Liao #define RT5640_M_MP3_DIS (0x0 << 13) 1829997b0520SBard Liao #define RT5640_M_MP3_EN (0x1 << 13) 1830997b0520SBard Liao #define RT5640_EG_MP3_MASK (0x1f << 8) 1831997b0520SBard Liao #define RT5640_EG_MP3_SFT 8 1832997b0520SBard Liao #define RT5640_MP3_HLP_MASK (0x1 << 7) 1833997b0520SBard Liao #define RT5640_MP3_HLP_SFT 7 1834997b0520SBard Liao #define RT5640_MP3_HLP_DIS (0x0 << 7) 1835997b0520SBard Liao #define RT5640_MP3_HLP_EN (0x1 << 7) 1836997b0520SBard Liao #define RT5640_M_MP3_ORG_L_MASK (0x1 << 6) 1837997b0520SBard Liao #define RT5640_M_MP3_ORG_L_SFT 6 1838997b0520SBard Liao #define RT5640_M_MP3_ORG_R_MASK (0x1 << 5) 1839997b0520SBard Liao #define RT5640_M_MP3_ORG_R_SFT 5 1840997b0520SBard Liao 1841997b0520SBard Liao /* MP3 Plus Control 2 (0xd1) */ 1842997b0520SBard Liao #define RT5640_MP3_WT_MASK (0x1 << 13) 1843997b0520SBard Liao #define RT5640_MP3_WT_SFT 13 1844997b0520SBard Liao #define RT5640_MP3_WT_1_4 (0x0 << 13) 1845997b0520SBard Liao #define RT5640_MP3_WT_1_2 (0x1 << 13) 1846997b0520SBard Liao #define RT5640_OG_MP3_MASK (0x1f << 8) 1847997b0520SBard Liao #define RT5640_OG_MP3_SFT 8 1848997b0520SBard Liao #define RT5640_HG_MP3_MASK (0x3f) 1849997b0520SBard Liao #define RT5640_HG_MP3_SFT 0 1850997b0520SBard Liao 1851997b0520SBard Liao /* 3D HP Control 1 (0xd2) */ 1852997b0520SBard Liao #define RT5640_3D_CF_MASK (0x1 << 15) 1853997b0520SBard Liao #define RT5640_3D_CF_SFT 15 1854997b0520SBard Liao #define RT5640_3D_CF_DIS (0x0 << 15) 1855997b0520SBard Liao #define RT5640_3D_CF_EN (0x1 << 15) 1856997b0520SBard Liao #define RT5640_3D_HP_MASK (0x1 << 14) 1857997b0520SBard Liao #define RT5640_3D_HP_SFT 14 1858997b0520SBard Liao #define RT5640_3D_HP_DIS (0x0 << 14) 1859997b0520SBard Liao #define RT5640_3D_HP_EN (0x1 << 14) 1860997b0520SBard Liao #define RT5640_3D_BT_MASK (0x1 << 13) 1861997b0520SBard Liao #define RT5640_3D_BT_SFT 13 1862997b0520SBard Liao #define RT5640_3D_BT_DIS (0x0 << 13) 1863997b0520SBard Liao #define RT5640_3D_BT_EN (0x1 << 13) 1864997b0520SBard Liao #define RT5640_3D_1F_MIX_MASK (0x3 << 11) 1865997b0520SBard Liao #define RT5640_3D_1F_MIX_SFT 11 1866997b0520SBard Liao #define RT5640_3D_HP_M_MASK (0x1 << 10) 1867997b0520SBard Liao #define RT5640_3D_HP_M_SFT 10 1868997b0520SBard Liao #define RT5640_3D_HP_M_SUR (0x0 << 10) 1869997b0520SBard Liao #define RT5640_3D_HP_M_FRO (0x1 << 10) 1870997b0520SBard Liao #define RT5640_M_3D_HRTF_MASK (0x1 << 9) 1871997b0520SBard Liao #define RT5640_M_3D_HRTF_SFT 9 1872997b0520SBard Liao #define RT5640_M_3D_D2H_MASK (0x1 << 8) 1873997b0520SBard Liao #define RT5640_M_3D_D2H_SFT 8 1874997b0520SBard Liao #define RT5640_M_3D_D2R_MASK (0x1 << 7) 1875997b0520SBard Liao #define RT5640_M_3D_D2R_SFT 7 1876997b0520SBard Liao #define RT5640_M_3D_REVB_MASK (0x1 << 6) 1877997b0520SBard Liao #define RT5640_M_3D_REVB_SFT 6 1878997b0520SBard Liao 1879997b0520SBard Liao /* Adjustable high pass filter control 1 (0xd3) */ 1880997b0520SBard Liao #define RT5640_2ND_HPF_MASK (0x1 << 15) 1881997b0520SBard Liao #define RT5640_2ND_HPF_SFT 15 1882997b0520SBard Liao #define RT5640_2ND_HPF_DIS (0x0 << 15) 1883997b0520SBard Liao #define RT5640_2ND_HPF_EN (0x1 << 15) 1884997b0520SBard Liao #define RT5640_HPF_CF_L_MASK (0x7 << 12) 1885997b0520SBard Liao #define RT5640_HPF_CF_L_SFT 12 1886997b0520SBard Liao #define RT5640_1ST_HPF_MASK (0x1 << 11) 1887997b0520SBard Liao #define RT5640_1ST_HPF_SFT 11 1888997b0520SBard Liao #define RT5640_1ST_HPF_DIS (0x0 << 11) 1889997b0520SBard Liao #define RT5640_1ST_HPF_EN (0x1 << 11) 1890997b0520SBard Liao #define RT5640_HPF_CF_R_MASK (0x7 << 8) 1891997b0520SBard Liao #define RT5640_HPF_CF_R_SFT 8 1892997b0520SBard Liao #define RT5640_ZD_T_MASK (0x3 << 6) 1893997b0520SBard Liao #define RT5640_ZD_T_SFT 6 1894997b0520SBard Liao #define RT5640_ZD_F_MASK (0x3 << 4) 1895997b0520SBard Liao #define RT5640_ZD_F_SFT 4 1896997b0520SBard Liao #define RT5640_ZD_F_IM (0x0 << 4) 1897997b0520SBard Liao #define RT5640_ZD_F_ZC_IM (0x1 << 4) 1898997b0520SBard Liao #define RT5640_ZD_F_ZC_IOD (0x2 << 4) 1899997b0520SBard Liao #define RT5640_ZD_F_UN (0x3 << 4) 1900997b0520SBard Liao 1901997b0520SBard Liao /* HP calibration control and Amp detection (0xd6) */ 1902997b0520SBard Liao #define RT5640_SI_DAC_MASK (0x1 << 11) 1903997b0520SBard Liao #define RT5640_SI_DAC_SFT 11 1904997b0520SBard Liao #define RT5640_SI_DAC_AUTO (0x0 << 11) 1905997b0520SBard Liao #define RT5640_SI_DAC_TEST (0x1 << 11) 1906997b0520SBard Liao #define RT5640_DC_CAL_M_MASK (0x1 << 10) 1907997b0520SBard Liao #define RT5640_DC_CAL_M_SFT 10 1908997b0520SBard Liao #define RT5640_DC_CAL_M_CAL (0x0 << 10) 1909997b0520SBard Liao #define RT5640_DC_CAL_M_NOR (0x1 << 10) 1910997b0520SBard Liao #define RT5640_DC_CAL_MASK (0x1 << 9) 1911997b0520SBard Liao #define RT5640_DC_CAL_SFT 9 1912997b0520SBard Liao #define RT5640_DC_CAL_DIS (0x0 << 9) 1913997b0520SBard Liao #define RT5640_DC_CAL_EN (0x1 << 9) 1914997b0520SBard Liao #define RT5640_HPD_RCV_MASK (0x7 << 6) 1915997b0520SBard Liao #define RT5640_HPD_RCV_SFT 6 1916997b0520SBard Liao #define RT5640_HPD_PS_MASK (0x1 << 5) 1917997b0520SBard Liao #define RT5640_HPD_PS_SFT 5 1918997b0520SBard Liao #define RT5640_HPD_PS_DIS (0x0 << 5) 1919997b0520SBard Liao #define RT5640_HPD_PS_EN (0x1 << 5) 1920997b0520SBard Liao #define RT5640_CAL_M_MASK (0x1 << 4) 1921997b0520SBard Liao #define RT5640_CAL_M_SFT 4 1922997b0520SBard Liao #define RT5640_CAL_M_DEP (0x0 << 4) 1923997b0520SBard Liao #define RT5640_CAL_M_CAL (0x1 << 4) 1924997b0520SBard Liao #define RT5640_CAL_MASK (0x1 << 3) 1925997b0520SBard Liao #define RT5640_CAL_SFT 3 1926997b0520SBard Liao #define RT5640_CAL_DIS (0x0 << 3) 1927997b0520SBard Liao #define RT5640_CAL_EN (0x1 << 3) 1928997b0520SBard Liao #define RT5640_CAL_TEST_MASK (0x1 << 2) 1929997b0520SBard Liao #define RT5640_CAL_TEST_SFT 2 1930997b0520SBard Liao #define RT5640_CAL_TEST_DIS (0x0 << 2) 1931997b0520SBard Liao #define RT5640_CAL_TEST_EN (0x1 << 2) 1932997b0520SBard Liao #define RT5640_CAL_P_MASK (0x3) 1933997b0520SBard Liao #define RT5640_CAL_P_SFT 0 1934997b0520SBard Liao #define RT5640_CAL_P_NONE (0x0) 1935997b0520SBard Liao #define RT5640_CAL_P_CAL (0x1) 1936997b0520SBard Liao #define RT5640_CAL_P_DAC_CAL (0x2) 1937997b0520SBard Liao 1938997b0520SBard Liao /* Soft volume and zero cross control 1 (0xd9) */ 1939997b0520SBard Liao #define RT5640_SV_MASK (0x1 << 15) 1940997b0520SBard Liao #define RT5640_SV_SFT 15 1941997b0520SBard Liao #define RT5640_SV_DIS (0x0 << 15) 1942997b0520SBard Liao #define RT5640_SV_EN (0x1 << 15) 1943997b0520SBard Liao #define RT5640_SPO_SV_MASK (0x1 << 14) 1944997b0520SBard Liao #define RT5640_SPO_SV_SFT 14 1945997b0520SBard Liao #define RT5640_SPO_SV_DIS (0x0 << 14) 1946997b0520SBard Liao #define RT5640_SPO_SV_EN (0x1 << 14) 1947997b0520SBard Liao #define RT5640_OUT_SV_MASK (0x1 << 13) 1948997b0520SBard Liao #define RT5640_OUT_SV_SFT 13 1949997b0520SBard Liao #define RT5640_OUT_SV_DIS (0x0 << 13) 1950997b0520SBard Liao #define RT5640_OUT_SV_EN (0x1 << 13) 1951997b0520SBard Liao #define RT5640_HP_SV_MASK (0x1 << 12) 1952997b0520SBard Liao #define RT5640_HP_SV_SFT 12 1953997b0520SBard Liao #define RT5640_HP_SV_DIS (0x0 << 12) 1954997b0520SBard Liao #define RT5640_HP_SV_EN (0x1 << 12) 1955997b0520SBard Liao #define RT5640_ZCD_DIG_MASK (0x1 << 11) 1956997b0520SBard Liao #define RT5640_ZCD_DIG_SFT 11 1957997b0520SBard Liao #define RT5640_ZCD_DIG_DIS (0x0 << 11) 1958997b0520SBard Liao #define RT5640_ZCD_DIG_EN (0x1 << 11) 1959997b0520SBard Liao #define RT5640_ZCD_MASK (0x1 << 10) 1960997b0520SBard Liao #define RT5640_ZCD_SFT 10 1961997b0520SBard Liao #define RT5640_ZCD_PD (0x0 << 10) 1962997b0520SBard Liao #define RT5640_ZCD_PU (0x1 << 10) 1963997b0520SBard Liao #define RT5640_M_ZCD_MASK (0x3f << 4) 1964997b0520SBard Liao #define RT5640_M_ZCD_SFT 4 1965997b0520SBard Liao #define RT5640_M_ZCD_RM_L (0x1 << 9) 1966997b0520SBard Liao #define RT5640_M_ZCD_RM_R (0x1 << 8) 1967997b0520SBard Liao #define RT5640_M_ZCD_SM_L (0x1 << 7) 1968997b0520SBard Liao #define RT5640_M_ZCD_SM_R (0x1 << 6) 1969997b0520SBard Liao #define RT5640_M_ZCD_OM_L (0x1 << 5) 1970997b0520SBard Liao #define RT5640_M_ZCD_OM_R (0x1 << 4) 1971997b0520SBard Liao #define RT5640_SV_DLY_MASK (0xf) 1972997b0520SBard Liao #define RT5640_SV_DLY_SFT 0 1973997b0520SBard Liao 1974997b0520SBard Liao /* Soft volume and zero cross control 2 (0xda) */ 1975997b0520SBard Liao #define RT5640_ZCD_HP_MASK (0x1 << 15) 1976997b0520SBard Liao #define RT5640_ZCD_HP_SFT 15 1977997b0520SBard Liao #define RT5640_ZCD_HP_DIS (0x0 << 15) 1978997b0520SBard Liao #define RT5640_ZCD_HP_EN (0x1 << 15) 1979997b0520SBard Liao 198025fb7062SBard Liao /* General Control 1 (0xfa) */ 198144b54f54SOndrej Jirman #define RT5640_EN_LOUT_DF (0x1 << 14) 198244b54f54SOndrej Jirman #define RT5640_EN_LOUT_DF_SFT 14 1983ca5f17c5SBard Liao #define RT5640_M_MONO_ADC_L (0x1 << 13) 1984ca5f17c5SBard Liao #define RT5640_M_MONO_ADC_L_SFT 13 1985ca5f17c5SBard Liao #define RT5640_M_MONO_ADC_R (0x1 << 12) 1986ca5f17c5SBard Liao #define RT5640_M_MONO_ADC_R_SFT 12 198725fb7062SBard Liao #define RT5640_MCLK_DET (0x1 << 11) 1988997b0520SBard Liao 1989b2ddf399SOder Chiou /* General Control 1 (0xfb) */ 1990b2ddf399SOder Chiou #define RT5640_IRQ_JD2_MASK (0x1 << 12) 1991b2ddf399SOder Chiou #define RT5640_IRQ_JD2_SFT 12 1992b2ddf399SOder Chiou #define RT5640_IRQ_JD2_BP (0x0 << 12) 1993b2ddf399SOder Chiou #define RT5640_IRQ_JD2_NOR (0x1 << 12) 1994b2ddf399SOder Chiou #define RT5640_JD2_P_MASK (0x1 << 10) 1995b2ddf399SOder Chiou #define RT5640_JD2_P_SFT 10 1996b2ddf399SOder Chiou #define RT5640_JD2_P_NOR (0x0 << 10) 1997b2ddf399SOder Chiou #define RT5640_JD2_P_INV (0x1 << 10) 1998b2ddf399SOder Chiou #define RT5640_JD2_MASK (0x1 << 8) 1999b2ddf399SOder Chiou #define RT5640_JD2_SFT 8 2000b2ddf399SOder Chiou #define RT5640_JD2_DIS (0x0 << 8) 2001b2ddf399SOder Chiou #define RT5640_JD2_EN (0x1 << 8) 2002b2ddf399SOder Chiou 2003997b0520SBard Liao /* Codec Private Register definition */ 20048210804bSHans de Goede 20058210804bSHans de Goede /* MIC Over current threshold scale factor (0x15) */ 20068210804bSHans de Goede #define RT5640_MIC_OVCD_SF_MASK (0x3 << 8) 20078210804bSHans de Goede #define RT5640_MIC_OVCD_SF_SFT 8 20088210804bSHans de Goede #define RT5640_MIC_OVCD_SF_0P5 (0x0 << 8) 20098210804bSHans de Goede #define RT5640_MIC_OVCD_SF_0P75 (0x1 << 8) 20108210804bSHans de Goede #define RT5640_MIC_OVCD_SF_1P0 (0x2 << 8) 20118210804bSHans de Goede #define RT5640_MIC_OVCD_SF_1P5 (0x3 << 8) 20128210804bSHans de Goede 2013997b0520SBard Liao /* 3D Speaker Control (0x63) */ 2014997b0520SBard Liao #define RT5640_3D_SPK_MASK (0x1 << 15) 2015997b0520SBard Liao #define RT5640_3D_SPK_SFT 15 2016997b0520SBard Liao #define RT5640_3D_SPK_DIS (0x0 << 15) 2017997b0520SBard Liao #define RT5640_3D_SPK_EN (0x1 << 15) 2018997b0520SBard Liao #define RT5640_3D_SPK_M_MASK (0x3 << 13) 2019997b0520SBard Liao #define RT5640_3D_SPK_M_SFT 13 2020997b0520SBard Liao #define RT5640_3D_SPK_CG_MASK (0x1f << 8) 2021997b0520SBard Liao #define RT5640_3D_SPK_CG_SFT 8 2022997b0520SBard Liao #define RT5640_3D_SPK_SG_MASK (0x1f) 2023997b0520SBard Liao #define RT5640_3D_SPK_SG_SFT 0 2024997b0520SBard Liao 2025997b0520SBard Liao /* Wind Noise Detection Control 1 (0x6c) */ 2026997b0520SBard Liao #define RT5640_WND_MASK (0x1 << 15) 2027997b0520SBard Liao #define RT5640_WND_SFT 15 2028997b0520SBard Liao #define RT5640_WND_DIS (0x0 << 15) 2029997b0520SBard Liao #define RT5640_WND_EN (0x1 << 15) 2030997b0520SBard Liao 2031997b0520SBard Liao /* Wind Noise Detection Control 2 (0x6d) */ 2032997b0520SBard Liao #define RT5640_WND_FC_NW_MASK (0x3f << 10) 2033997b0520SBard Liao #define RT5640_WND_FC_NW_SFT 10 2034997b0520SBard Liao #define RT5640_WND_FC_WK_MASK (0x3f << 4) 2035997b0520SBard Liao #define RT5640_WND_FC_WK_SFT 4 2036997b0520SBard Liao 2037997b0520SBard Liao /* Wind Noise Detection Control 3 (0x6e) */ 2038997b0520SBard Liao #define RT5640_HPF_FC_MASK (0x3f << 6) 2039997b0520SBard Liao #define RT5640_HPF_FC_SFT 6 2040997b0520SBard Liao #define RT5640_WND_FC_ST_MASK (0x3f) 2041997b0520SBard Liao #define RT5640_WND_FC_ST_SFT 0 2042997b0520SBard Liao 2043997b0520SBard Liao /* Wind Noise Detection Control 4 (0x6f) */ 2044997b0520SBard Liao #define RT5640_WND_TH_LO_MASK (0x3ff) 2045997b0520SBard Liao #define RT5640_WND_TH_LO_SFT 0 2046997b0520SBard Liao 2047997b0520SBard Liao /* Wind Noise Detection Control 5 (0x70) */ 2048997b0520SBard Liao #define RT5640_WND_TH_HI_MASK (0x3ff) 2049997b0520SBard Liao #define RT5640_WND_TH_HI_SFT 0 2050997b0520SBard Liao 2051997b0520SBard Liao /* Wind Noise Detection Control 8 (0x73) */ 2052997b0520SBard Liao #define RT5640_WND_WIND_MASK (0x1 << 13) /* Read-Only */ 2053997b0520SBard Liao #define RT5640_WND_WIND_SFT 13 2054997b0520SBard Liao #define RT5640_WND_STRONG_MASK (0x1 << 12) /* Read-Only */ 2055997b0520SBard Liao #define RT5640_WND_STRONG_SFT 12 2056997b0520SBard Liao enum { 2057997b0520SBard Liao RT5640_NO_WIND, 2058997b0520SBard Liao RT5640_BREEZE, 2059997b0520SBard Liao RT5640_STORM, 2060997b0520SBard Liao }; 2061997b0520SBard Liao 2062997b0520SBard Liao /* Dipole Speaker Interface (0x75) */ 2063997b0520SBard Liao #define RT5640_DP_ATT_MASK (0x3 << 14) 2064997b0520SBard Liao #define RT5640_DP_ATT_SFT 14 2065997b0520SBard Liao #define RT5640_DP_SPK_MASK (0x1 << 10) 2066997b0520SBard Liao #define RT5640_DP_SPK_SFT 10 2067997b0520SBard Liao #define RT5640_DP_SPK_DIS (0x0 << 10) 2068997b0520SBard Liao #define RT5640_DP_SPK_EN (0x1 << 10) 2069997b0520SBard Liao 2070997b0520SBard Liao /* EQ Pre Volume Control (0xb3) */ 2071997b0520SBard Liao #define RT5640_EQ_PRE_VOL_MASK (0xffff) 2072997b0520SBard Liao #define RT5640_EQ_PRE_VOL_SFT 0 2073997b0520SBard Liao 2074997b0520SBard Liao /* EQ Post Volume Control (0xb4) */ 2075997b0520SBard Liao #define RT5640_EQ_PST_VOL_MASK (0xffff) 2076997b0520SBard Liao #define RT5640_EQ_PST_VOL_SFT 0 2077997b0520SBard Liao 2078997b0520SBard Liao #define RT5640_NO_JACK BIT(0) 2079997b0520SBard Liao #define RT5640_HEADSET_DET BIT(1) 2080997b0520SBard Liao #define RT5640_HEADPHO_DET BIT(2) 2081997b0520SBard Liao 2082997b0520SBard Liao /* System Clock Source */ 2083997b0520SBard Liao #define RT5640_SCLK_S_MCLK 0 2084997b0520SBard Liao #define RT5640_SCLK_S_PLL1 1 2085997b0520SBard Liao #define RT5640_SCLK_S_PLL1_TK 2 2086997b0520SBard Liao #define RT5640_SCLK_S_RCCLK 3 2087997b0520SBard Liao 2088997b0520SBard Liao /* PLL1 Source */ 2089997b0520SBard Liao #define RT5640_PLL1_S_MCLK 0 2090997b0520SBard Liao #define RT5640_PLL1_S_BCLK1 1 2091997b0520SBard Liao #define RT5640_PLL1_S_BCLK2 2 2092997b0520SBard Liao #define RT5640_PLL1_S_BCLK3 3 2093997b0520SBard Liao 2094997b0520SBard Liao 2095997b0520SBard Liao enum { 2096997b0520SBard Liao RT5640_AIF1, 2097997b0520SBard Liao RT5640_AIF2, 2098997b0520SBard Liao RT5640_AIF3, 2099997b0520SBard Liao RT5640_AIFS, 2100997b0520SBard Liao }; 2101997b0520SBard Liao 2102997b0520SBard Liao enum { 2103997b0520SBard Liao RT5640_U_IF1 = 0x1, 2104997b0520SBard Liao RT5640_U_IF2 = 0x2, 2105997b0520SBard Liao RT5640_U_IF3 = 0x4, 2106997b0520SBard Liao }; 2107997b0520SBard Liao 2108997b0520SBard Liao enum { 2109997b0520SBard Liao RT5640_IF_123, 2110997b0520SBard Liao RT5640_IF_132, 2111997b0520SBard Liao RT5640_IF_312, 2112997b0520SBard Liao RT5640_IF_321, 2113997b0520SBard Liao RT5640_IF_231, 2114997b0520SBard Liao RT5640_IF_213, 2115997b0520SBard Liao RT5640_IF_113, 2116997b0520SBard Liao RT5640_IF_223, 2117997b0520SBard Liao RT5640_IF_ALL, 2118997b0520SBard Liao }; 2119997b0520SBard Liao 2120997b0520SBard Liao enum { 2121997b0520SBard Liao RT5640_DMIC_DIS, 2122997b0520SBard Liao RT5640_DMIC1, 2123997b0520SBard Liao RT5640_DMIC2, 2124997b0520SBard Liao }; 2125997b0520SBard Liao 2126bee3e020SJack Yu /* filter mask */ 2127bee3e020SJack Yu enum { 2128bee3e020SJack Yu RT5640_DA_STEREO_FILTER = 0x1, 2129bee3e020SJack Yu RT5640_DA_MONO_L_FILTER = (0x1 << 1), 2130bee3e020SJack Yu RT5640_DA_MONO_R_FILTER = (0x1 << 2), 2131bee3e020SJack Yu RT5640_AD_STEREO_FILTER = (0x1 << 3), 2132bee3e020SJack Yu RT5640_AD_MONO_L_FILTER = (0x1 << 4), 2133bee3e020SJack Yu RT5640_AD_MONO_R_FILTER = (0x1 << 5), 2134bee3e020SJack Yu }; 2135bee3e020SJack Yu 2136997b0520SBard Liao struct rt5640_priv { 2137d5a41b5dSKuninori Morimoto struct snd_soc_component *component; 2138997b0520SBard Liao struct regmap *regmap; 21396049af00SSugar Zhang struct clk *mclk; 2140997b0520SBard Liao 2141*a9b5f210SLinus Walleij struct gpio_desc *ldo1_en; /* GPIO for LDO1_EN */ 21428210804bSHans de Goede int irq; 2143701d636aSHans de Goede int jd_gpio_irq; 2144997b0520SBard Liao int sysclk; 2145997b0520SBard Liao int sysclk_src; 2146997b0520SBard Liao int lrck[RT5640_AIFS]; 2147997b0520SBard Liao int bclk[RT5640_AIFS]; 2148997b0520SBard Liao int master[RT5640_AIFS]; 2149997b0520SBard Liao 2150997b0520SBard Liao int pll_src; 2151997b0520SBard Liao int pll_in; 2152997b0520SBard Liao int pll_out; 2153997b0520SBard Liao 2154246693baSBard Liao bool hp_mute; 2155bee3e020SJack Yu bool asrc_en; 2156701d636aSHans de Goede bool irq_requested; 2157701d636aSHans de Goede bool jd_gpio_irq_requested; 21588210804bSHans de Goede 2159b16188a2SHans de Goede /* Jack and button detect data */ 2160b16188a2SHans de Goede bool ovcd_irq_enabled; 2161b16188a2SHans de Goede bool pressed; 2162b16188a2SHans de Goede bool press_reported; 2163b16188a2SHans de Goede int press_count; 2164b16188a2SHans de Goede int release_count; 2165b16188a2SHans de Goede int poll_count; 2166b16188a2SHans de Goede struct delayed_work bp_work; 2167a3b1aaf7SHans de Goede struct delayed_work jack_work; 21688210804bSHans de Goede struct snd_soc_jack *jack; 2169701d636aSHans de Goede struct gpio_desc *jd_gpio; 21708210804bSHans de Goede unsigned int jd_src; 21718210804bSHans de Goede bool jd_inverted; 21728210804bSHans de Goede unsigned int ovcd_th; 21738210804bSHans de Goede unsigned int ovcd_sf; 217483229680SOder Chiou bool use_platform_clock; 2175997b0520SBard Liao }; 2176997b0520SBard Liao 2177b35a9ab4SHans de Goede struct rt5640_set_jack_data { 2178b35a9ab4SHans de Goede int codec_irq_override; 2179701d636aSHans de Goede struct gpio_desc *jd_gpio; 218083229680SOder Chiou bool use_platform_clock; 2181b35a9ab4SHans de Goede }; 2182b35a9ab4SHans de Goede 2183d5a41b5dSKuninori Morimoto int rt5640_dmic_enable(struct snd_soc_component *component, 2184cd69dc88SJarkko Nikula bool dmic1_data_pin, bool dmic2_data_pin); 2185d5a41b5dSKuninori Morimoto int rt5640_sel_asrc_clk_src(struct snd_soc_component *component, 2186bee3e020SJack Yu unsigned int filter_mask, unsigned int clk_src); 2187e3f2a660SHans de Goede 2188e3f2a660SHans de Goede void rt5640_set_ovcd_params(struct snd_soc_component *component); 2189e3f2a660SHans de Goede void rt5640_enable_micbias1_for_ovcd(struct snd_soc_component *component); 2190e3f2a660SHans de Goede void rt5640_disable_micbias1_for_ovcd(struct snd_soc_component *component); 2191d21213b4SHans de Goede int rt5640_detect_headset(struct snd_soc_component *component, struct gpio_desc *hp_det_gpio); 2192cd69dc88SJarkko Nikula 2193997b0520SBard Liao #endif 2194