xref: /openbmc/linux/sound/soc/codecs/rt5631.h (revision b2441318)
1b2441318SGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0 */
2d8085222Sjohnnyhsu@realtek.com #ifndef __RTCODEC5631_H__
3d8085222Sjohnnyhsu@realtek.com #define __RTCODEC5631_H__
4d8085222Sjohnnyhsu@realtek.com 
5d8085222Sjohnnyhsu@realtek.com 
6d8085222Sjohnnyhsu@realtek.com #define RT5631_RESET				0x00
7d8085222Sjohnnyhsu@realtek.com #define RT5631_SPK_OUT_VOL			0x02
8d8085222Sjohnnyhsu@realtek.com #define RT5631_HP_OUT_VOL			0x04
9d8085222Sjohnnyhsu@realtek.com #define RT5631_MONO_AXO_1_2_VOL		0x06
10d8085222Sjohnnyhsu@realtek.com #define RT5631_AUX_IN_VOL			0x0A
11d8085222Sjohnnyhsu@realtek.com #define RT5631_STEREO_DAC_VOL_1		0x0C
12d8085222Sjohnnyhsu@realtek.com #define RT5631_MIC_CTRL_1			0x0E
13d8085222Sjohnnyhsu@realtek.com #define RT5631_STEREO_DAC_VOL_2		0x10
14d8085222Sjohnnyhsu@realtek.com #define RT5631_ADC_CTRL_1			0x12
15d8085222Sjohnnyhsu@realtek.com #define RT5631_ADC_REC_MIXER			0x14
16d8085222Sjohnnyhsu@realtek.com #define RT5631_ADC_CTRL_2			0x16
17d8085222Sjohnnyhsu@realtek.com #define RT5631_VDAC_DIG_VOL			0x18
18d8085222Sjohnnyhsu@realtek.com #define RT5631_OUTMIXER_L_CTRL			0x1A
19d8085222Sjohnnyhsu@realtek.com #define RT5631_OUTMIXER_R_CTRL			0x1C
20d8085222Sjohnnyhsu@realtek.com #define RT5631_AXO1MIXER_CTRL			0x1E
21d8085222Sjohnnyhsu@realtek.com #define RT5631_AXO2MIXER_CTRL			0x20
22d8085222Sjohnnyhsu@realtek.com #define RT5631_MIC_CTRL_2			0x22
23d8085222Sjohnnyhsu@realtek.com #define RT5631_DIG_MIC_CTRL			0x24
24d8085222Sjohnnyhsu@realtek.com #define RT5631_MONO_INPUT_VOL			0x26
25d8085222Sjohnnyhsu@realtek.com #define RT5631_SPK_MIXER_CTRL			0x28
26d8085222Sjohnnyhsu@realtek.com #define RT5631_SPK_MONO_OUT_CTRL		0x2A
27d8085222Sjohnnyhsu@realtek.com #define RT5631_SPK_MONO_HP_OUT_CTRL		0x2C
28d8085222Sjohnnyhsu@realtek.com #define RT5631_SDP_CTRL				0x34
29d8085222Sjohnnyhsu@realtek.com #define RT5631_MONO_SDP_CTRL			0x36
30d8085222Sjohnnyhsu@realtek.com #define RT5631_STEREO_AD_DA_CLK_CTRL		0x38
31d8085222Sjohnnyhsu@realtek.com #define RT5631_PWR_MANAG_ADD1		0x3A
32d8085222Sjohnnyhsu@realtek.com #define RT5631_PWR_MANAG_ADD2		0x3B
33d8085222Sjohnnyhsu@realtek.com #define RT5631_PWR_MANAG_ADD3		0x3C
34d8085222Sjohnnyhsu@realtek.com #define RT5631_PWR_MANAG_ADD4		0x3E
35d8085222Sjohnnyhsu@realtek.com #define RT5631_GEN_PUR_CTRL_REG		0x40
36d8085222Sjohnnyhsu@realtek.com #define RT5631_GLOBAL_CLK_CTRL			0x42
37d8085222Sjohnnyhsu@realtek.com #define RT5631_PLL_CTRL				0x44
38d8085222Sjohnnyhsu@realtek.com #define RT5631_INT_ST_IRQ_CTRL_1		0x48
39d8085222Sjohnnyhsu@realtek.com #define RT5631_INT_ST_IRQ_CTRL_2		0x4A
40d8085222Sjohnnyhsu@realtek.com #define RT5631_GPIO_CTRL			0x4C
41d8085222Sjohnnyhsu@realtek.com #define RT5631_MISC_CTRL			0x52
42d8085222Sjohnnyhsu@realtek.com #define RT5631_DEPOP_FUN_CTRL_1		0x54
43d8085222Sjohnnyhsu@realtek.com #define RT5631_DEPOP_FUN_CTRL_2		0x56
44d8085222Sjohnnyhsu@realtek.com #define RT5631_JACK_DET_CTRL			0x5A
45d8085222Sjohnnyhsu@realtek.com #define RT5631_SOFT_VOL_CTRL			0x5C
46d8085222Sjohnnyhsu@realtek.com #define RT5631_ALC_CTRL_1			0x64
47d8085222Sjohnnyhsu@realtek.com #define RT5631_ALC_CTRL_2			0x65
48d8085222Sjohnnyhsu@realtek.com #define RT5631_ALC_CTRL_3			0x66
49d8085222Sjohnnyhsu@realtek.com #define RT5631_PSEUDO_SPATL_CTRL		0x68
50d8085222Sjohnnyhsu@realtek.com #define RT5631_INDEX_ADD			0x6A
51d8085222Sjohnnyhsu@realtek.com #define RT5631_INDEX_DATA			0x6C
52d8085222Sjohnnyhsu@realtek.com #define RT5631_EQ_CTRL				0x6E
53d8085222Sjohnnyhsu@realtek.com #define RT5631_VENDOR_ID			0x7A
54d8085222Sjohnnyhsu@realtek.com #define RT5631_VENDOR_ID1			0x7C
55d8085222Sjohnnyhsu@realtek.com #define RT5631_VENDOR_ID2			0x7E
56d8085222Sjohnnyhsu@realtek.com 
57d8085222Sjohnnyhsu@realtek.com /* Index of Codec Private Register definition */
58d8085222Sjohnnyhsu@realtek.com #define RT5631_EQ_BW_LOP			0x00
59d8085222Sjohnnyhsu@realtek.com #define RT5631_EQ_GAIN_LOP			0x01
60d8085222Sjohnnyhsu@realtek.com #define RT5631_EQ_FC_BP1			0x02
61d8085222Sjohnnyhsu@realtek.com #define RT5631_EQ_BW_BP1			0x03
62d8085222Sjohnnyhsu@realtek.com #define RT5631_EQ_GAIN_BP1			0x04
63d8085222Sjohnnyhsu@realtek.com #define RT5631_EQ_FC_BP2			0x05
64d8085222Sjohnnyhsu@realtek.com #define RT5631_EQ_BW_BP2			0x06
65d8085222Sjohnnyhsu@realtek.com #define RT5631_EQ_GAIN_BP2			0x07
66d8085222Sjohnnyhsu@realtek.com #define RT5631_EQ_FC_BP3			0x08
67d8085222Sjohnnyhsu@realtek.com #define RT5631_EQ_BW_BP3			0x09
68d8085222Sjohnnyhsu@realtek.com #define RT5631_EQ_GAIN_BP3			0x0a
69d8085222Sjohnnyhsu@realtek.com #define RT5631_EQ_BW_HIP			0x0b
70d8085222Sjohnnyhsu@realtek.com #define RT5631_EQ_GAIN_HIP			0x0c
71d8085222Sjohnnyhsu@realtek.com #define RT5631_EQ_HPF_A1			0x0d
72d8085222Sjohnnyhsu@realtek.com #define RT5631_EQ_HPF_A2			0x0e
73d8085222Sjohnnyhsu@realtek.com #define RT5631_EQ_HPF_GAIN			0x0f
74d8085222Sjohnnyhsu@realtek.com #define RT5631_EQ_PRE_VOL_CTRL			0x11
75d8085222Sjohnnyhsu@realtek.com #define RT5631_EQ_POST_VOL_CTRL		0x12
76d8085222Sjohnnyhsu@realtek.com #define RT5631_TEST_MODE_CTRL			0x39
77d8085222Sjohnnyhsu@realtek.com #define RT5631_CP_INTL_REG2			0x45
78d8085222Sjohnnyhsu@realtek.com #define RT5631_ADDA_MIXER_INTL_REG3		0x52
79d8085222Sjohnnyhsu@realtek.com #define RT5631_SPK_INTL_CTRL			0x56
80d8085222Sjohnnyhsu@realtek.com 
81d8085222Sjohnnyhsu@realtek.com 
82d8085222Sjohnnyhsu@realtek.com /* global definition */
83d8085222Sjohnnyhsu@realtek.com #define RT5631_L_MUTE					(0x1 << 15)
84d8085222Sjohnnyhsu@realtek.com #define RT5631_L_MUTE_SHIFT				15
85d8085222Sjohnnyhsu@realtek.com #define RT5631_L_EN					(0x1 << 14)
86d8085222Sjohnnyhsu@realtek.com #define RT5631_L_EN_SHIFT				14
87d8085222Sjohnnyhsu@realtek.com #define RT5631_R_MUTE					(0x1 << 7)
88d8085222Sjohnnyhsu@realtek.com #define RT5631_R_MUTE_SHIFT				7
89d8085222Sjohnnyhsu@realtek.com #define RT5631_R_EN					(0x1 << 6)
90d8085222Sjohnnyhsu@realtek.com #define RT5631_R_EN_SHIFT				6
91d8085222Sjohnnyhsu@realtek.com #define RT5631_VOL_MASK				0x1f
92d8085222Sjohnnyhsu@realtek.com #define RT5631_L_VOL_SHIFT				8
93d8085222Sjohnnyhsu@realtek.com #define RT5631_R_VOL_SHIFT				0
94d8085222Sjohnnyhsu@realtek.com 
95d8085222Sjohnnyhsu@realtek.com /* Speaker Output Control(0x02) */
96d8085222Sjohnnyhsu@realtek.com #define RT5631_SPK_L_VOL_SEL_MASK			(0x1 << 14)
97d8085222Sjohnnyhsu@realtek.com #define RT5631_SPK_L_VOL_SEL_VMID			(0x0 << 14)
98d8085222Sjohnnyhsu@realtek.com #define RT5631_SPK_L_VOL_SEL_SPKMIX_L			(0x1 << 14)
99d8085222Sjohnnyhsu@realtek.com #define RT5631_SPK_R_VOL_SEL_MASK			(0x1 << 6)
100d8085222Sjohnnyhsu@realtek.com #define RT5631_SPK_R_VOL_SEL_VMID			(0x0 << 6)
101d8085222Sjohnnyhsu@realtek.com #define RT5631_SPK_R_VOL_SEL_SPKMIX_R			(0x1 << 6)
102d8085222Sjohnnyhsu@realtek.com 
103d8085222Sjohnnyhsu@realtek.com /* Headphone Output Control(0x04) */
104d8085222Sjohnnyhsu@realtek.com #define RT5631_HP_L_VOL_SEL_MASK			(0x1 << 14)
105d8085222Sjohnnyhsu@realtek.com #define RT5631_HP_L_VOL_SEL_VMID			(0x0 << 14)
106d8085222Sjohnnyhsu@realtek.com #define RT5631_HP_L_VOL_SEL_OUTMIX_L			(0x1 << 14)
107d8085222Sjohnnyhsu@realtek.com #define RT5631_HP_R_VOL_SEL_MASK			(0x1 << 6)
108d8085222Sjohnnyhsu@realtek.com #define RT5631_HP_R_VOL_SEL_VMID			(0x0 << 6)
109d8085222Sjohnnyhsu@realtek.com #define RT5631_HP_R_VOL_SEL_OUTMIX_R			(0x1 << 6)
110d8085222Sjohnnyhsu@realtek.com 
111d8085222Sjohnnyhsu@realtek.com /* Output Control for AUXOUT/MONO(0x06) */
112d8085222Sjohnnyhsu@realtek.com #define RT5631_AUXOUT_1_VOL_SEL_MASK			(0x1 << 14)
113d8085222Sjohnnyhsu@realtek.com #define RT5631_AUXOUT_1_VOL_SEL_VMID			(0x0 << 14)
114d8085222Sjohnnyhsu@realtek.com #define RT5631_AUXOUT_1_VOL_SEL_OUTMIX_L		(0x1 << 14)
115d8085222Sjohnnyhsu@realtek.com #define RT5631_MUTE_MONO				(0x1 << 13)
116d8085222Sjohnnyhsu@realtek.com #define RT5631_MUTE_MONO_SHIFT			13
117d8085222Sjohnnyhsu@realtek.com #define RT5631_AUXOUT_2_VOL_SEL_MASK			(0x1 << 6)
118d8085222Sjohnnyhsu@realtek.com #define RT5631_AUXOUT_2_VOL_SEL_VMID			(0x0 << 6)
119d8085222Sjohnnyhsu@realtek.com #define RT5631_AUXOUT_2_VOL_SEL_OUTMIX_R		(0x1 << 6)
120d8085222Sjohnnyhsu@realtek.com 
121d8085222Sjohnnyhsu@realtek.com /* Microphone Input Control 1(0x0E) */
122d8085222Sjohnnyhsu@realtek.com #define RT5631_MIC1_DIFF_INPUT_CTRL			(0x1 << 15)
123d8085222Sjohnnyhsu@realtek.com #define RT5631_MIC1_DIFF_INPUT_SHIFT			15
124d8085222Sjohnnyhsu@realtek.com #define RT5631_MIC2_DIFF_INPUT_CTRL			(0x1 << 7)
125d8085222Sjohnnyhsu@realtek.com #define RT5631_MIC2_DIFF_INPUT_SHIFT			7
126d8085222Sjohnnyhsu@realtek.com 
127d8085222Sjohnnyhsu@realtek.com /* Stereo DAC Digital Volume2(0x10) */
128d8085222Sjohnnyhsu@realtek.com #define RT5631_DAC_VOL_MASK				0xff
129d8085222Sjohnnyhsu@realtek.com 
130d8085222Sjohnnyhsu@realtek.com /* ADC Recording Mixer Control(0x14) */
131d8085222Sjohnnyhsu@realtek.com #define RT5631_M_OUTMIXER_L_TO_RECMIXER_L		(0x1 << 15)
132d8085222Sjohnnyhsu@realtek.com #define RT5631_M_OUTMIXL_RECMIXL_BIT			15
133d8085222Sjohnnyhsu@realtek.com #define RT5631_M_MIC1_TO_RECMIXER_L			(0x1 << 14)
134d8085222Sjohnnyhsu@realtek.com #define RT5631_M_MIC1_RECMIXL_BIT			14
135d8085222Sjohnnyhsu@realtek.com #define RT5631_M_AXIL_TO_RECMIXER_L			(0x1 << 13)
136d8085222Sjohnnyhsu@realtek.com #define RT5631_M_AXIL_RECMIXL_BIT			13
137d8085222Sjohnnyhsu@realtek.com #define RT5631_M_MONO_IN_TO_RECMIXER_L		(0x1 << 12)
138d8085222Sjohnnyhsu@realtek.com #define RT5631_M_MONO_IN_RECMIXL_BIT			12
139d8085222Sjohnnyhsu@realtek.com #define RT5631_M_OUTMIXER_R_TO_RECMIXER_R		(0x1 << 7)
140d8085222Sjohnnyhsu@realtek.com #define RT5631_M_OUTMIXR_RECMIXR_BIT			7
141d8085222Sjohnnyhsu@realtek.com #define RT5631_M_MIC2_TO_RECMIXER_R			(0x1 << 6)
142d8085222Sjohnnyhsu@realtek.com #define RT5631_M_MIC2_RECMIXR_BIT			6
143d8085222Sjohnnyhsu@realtek.com #define RT5631_M_AXIR_TO_RECMIXER_R			(0x1 << 5)
144d8085222Sjohnnyhsu@realtek.com #define RT5631_M_AXIR_RECMIXR_BIT			5
145d8085222Sjohnnyhsu@realtek.com #define RT5631_M_MONO_IN_TO_RECMIXER_R		(0x1 << 4)
146d8085222Sjohnnyhsu@realtek.com #define RT5631_M_MONO_IN_RECMIXR_BIT			4
147d8085222Sjohnnyhsu@realtek.com 
148d8085222Sjohnnyhsu@realtek.com /* Left Output Mixer Control(0x1A) */
149d8085222Sjohnnyhsu@realtek.com #define RT5631_M_RECMIXER_L_TO_OUTMIXER_L		(0x1 << 15)
150d8085222Sjohnnyhsu@realtek.com #define RT5631_M_RECMIXL_OUTMIXL_BIT			15
151d8085222Sjohnnyhsu@realtek.com #define RT5631_M_RECMIXER_R_TO_OUTMIXER_L		(0x1 << 14)
152d8085222Sjohnnyhsu@realtek.com #define RT5631_M_RECMIXR_OUTMIXL_BIT			14
153d8085222Sjohnnyhsu@realtek.com #define RT5631_M_DAC_L_TO_OUTMIXER_L			(0x1 << 13)
154d8085222Sjohnnyhsu@realtek.com #define RT5631_M_DACL_OUTMIXL_BIT			13
155d8085222Sjohnnyhsu@realtek.com #define RT5631_M_MIC1_TO_OUTMIXER_L			(0x1 << 12)
156d8085222Sjohnnyhsu@realtek.com #define RT5631_M_MIC1_OUTMIXL_BIT			12
157d8085222Sjohnnyhsu@realtek.com #define RT5631_M_MIC2_TO_OUTMIXER_L			(0x1 << 11)
158d8085222Sjohnnyhsu@realtek.com #define RT5631_M_MIC2_OUTMIXL_BIT			11
159d8085222Sjohnnyhsu@realtek.com #define RT5631_M_MONO_IN_P_TO_OUTMIXER_L		(0x1 << 10)
160d8085222Sjohnnyhsu@realtek.com #define RT5631_M_MONO_INP_OUTMIXL_BIT		10
161d8085222Sjohnnyhsu@realtek.com #define RT5631_M_AXIL_TO_OUTMIXER_L			(0x1 << 9)
162d8085222Sjohnnyhsu@realtek.com #define RT5631_M_AXIL_OUTMIXL_BIT			9
163d8085222Sjohnnyhsu@realtek.com #define RT5631_M_AXIR_TO_OUTMIXER_L			(0x1 << 8)
164d8085222Sjohnnyhsu@realtek.com #define RT5631_M_AXIR_OUTMIXL_BIT			8
165d8085222Sjohnnyhsu@realtek.com #define RT5631_M_VDAC_TO_OUTMIXER_L			(0x1 << 7)
166d8085222Sjohnnyhsu@realtek.com #define RT5631_M_VDAC_OUTMIXL_BIT			7
167d8085222Sjohnnyhsu@realtek.com 
168d8085222Sjohnnyhsu@realtek.com /* Right Output Mixer Control(0x1C) */
169d8085222Sjohnnyhsu@realtek.com #define RT5631_M_RECMIXER_L_TO_OUTMIXER_R		(0x1 << 15)
170d8085222Sjohnnyhsu@realtek.com #define RT5631_M_RECMIXL_OUTMIXR_BIT			15
171d8085222Sjohnnyhsu@realtek.com #define RT5631_M_RECMIXER_R_TO_OUTMIXER_R		(0x1 << 14)
172d8085222Sjohnnyhsu@realtek.com #define RT5631_M_RECMIXR_OUTMIXR_BIT			14
173d8085222Sjohnnyhsu@realtek.com #define RT5631_M_DAC_R_TO_OUTMIXER_R			(0x1 << 13)
174d8085222Sjohnnyhsu@realtek.com #define RT5631_M_DACR_OUTMIXR_BIT			13
175d8085222Sjohnnyhsu@realtek.com #define RT5631_M_MIC1_TO_OUTMIXER_R			(0x1 << 12)
176d8085222Sjohnnyhsu@realtek.com #define RT5631_M_MIC1_OUTMIXR_BIT			12
177d8085222Sjohnnyhsu@realtek.com #define RT5631_M_MIC2_TO_OUTMIXER_R			(0x1 << 11)
178d8085222Sjohnnyhsu@realtek.com #define RT5631_M_MIC2_OUTMIXR_BIT			11
179d8085222Sjohnnyhsu@realtek.com #define RT5631_M_MONO_IN_N_TO_OUTMIXER_R		(0x1 << 10)
180d8085222Sjohnnyhsu@realtek.com #define RT5631_M_MONO_INN_OUTMIXR_BIT		10
181d8085222Sjohnnyhsu@realtek.com #define RT5631_M_AXIL_TO_OUTMIXER_R			(0x1 << 9)
182d8085222Sjohnnyhsu@realtek.com #define RT5631_M_AXIL_OUTMIXR_BIT			9
183d8085222Sjohnnyhsu@realtek.com #define RT5631_M_AXIR_TO_OUTMIXER_R			(0x1 << 8)
184d8085222Sjohnnyhsu@realtek.com #define RT5631_M_AXIR_OUTMIXR_BIT			8
185d8085222Sjohnnyhsu@realtek.com #define RT5631_M_VDAC_TO_OUTMIXER_R			(0x1 << 7)
186d8085222Sjohnnyhsu@realtek.com #define RT5631_M_VDAC_OUTMIXR_BIT			7
187d8085222Sjohnnyhsu@realtek.com 
188d8085222Sjohnnyhsu@realtek.com /* Lout Mixer Control(0x1E) */
189d8085222Sjohnnyhsu@realtek.com #define RT5631_M_MIC1_TO_AXO1MIXER			(0x1 << 15)
190d8085222Sjohnnyhsu@realtek.com #define RT5631_M_MIC1_AXO1MIX_BIT			15
191d8085222Sjohnnyhsu@realtek.com #define RT5631_M_MIC2_TO_AXO1MIXER			(0x1 << 11)
192d8085222Sjohnnyhsu@realtek.com #define RT5631_M_MIC2_AXO1MIX_BIT			11
193d8085222Sjohnnyhsu@realtek.com #define RT5631_M_OUTMIXER_L_TO_AXO1MIXER		(0x1 << 7)
194d8085222Sjohnnyhsu@realtek.com #define RT5631_M_OUTMIXL_AXO1MIX_BIT			7
195d8085222Sjohnnyhsu@realtek.com #define RT5631_M_OUTMIXER_R_TO_AXO1MIXER		(0x1 << 6)
196d8085222Sjohnnyhsu@realtek.com #define RT5631_M_OUTMIXR_AXO1MIX_BIT			6
197d8085222Sjohnnyhsu@realtek.com 
198d8085222Sjohnnyhsu@realtek.com /* Rout Mixer Control(0x20) */
199d8085222Sjohnnyhsu@realtek.com #define RT5631_M_MIC1_TO_AXO2MIXER			(0x1 << 15)
200d8085222Sjohnnyhsu@realtek.com #define RT5631_M_MIC1_AXO2MIX_BIT			15
201d8085222Sjohnnyhsu@realtek.com #define RT5631_M_MIC2_TO_AXO2MIXER			(0x1 << 11)
202d8085222Sjohnnyhsu@realtek.com #define RT5631_M_MIC2_AXO2MIX_BIT			11
203d8085222Sjohnnyhsu@realtek.com #define RT5631_M_OUTMIXER_L_TO_AXO2MIXER		(0x1 << 7)
204d8085222Sjohnnyhsu@realtek.com #define RT5631_M_OUTMIXL_AXO2MIX_BIT			7
205d8085222Sjohnnyhsu@realtek.com #define RT5631_M_OUTMIXER_R_TO_AXO2MIXER		(0x1 << 6)
206d8085222Sjohnnyhsu@realtek.com #define RT5631_M_OUTMIXR_AXO2MIX_BIT			6
207d8085222Sjohnnyhsu@realtek.com 
208d8085222Sjohnnyhsu@realtek.com /* Micphone Input Control 2(0x22) */
209d8085222Sjohnnyhsu@realtek.com #define RT5631_MIC_BIAS_90_PRECNET_AVDD 1
210d8085222Sjohnnyhsu@realtek.com #define RT5631_MIC_BIAS_75_PRECNET_AVDD 2
211d8085222Sjohnnyhsu@realtek.com 
212d8085222Sjohnnyhsu@realtek.com #define RT5631_MIC1_BOOST_CTRL_MASK			(0xf << 12)
213d8085222Sjohnnyhsu@realtek.com #define RT5631_MIC1_BOOST_CTRL_BYPASS		(0x0 << 12)
214d8085222Sjohnnyhsu@realtek.com #define RT5631_MIC1_BOOST_CTRL_20DB			(0x1 << 12)
215d8085222Sjohnnyhsu@realtek.com #define RT5631_MIC1_BOOST_CTRL_24DB			(0x2 << 12)
216d8085222Sjohnnyhsu@realtek.com #define RT5631_MIC1_BOOST_CTRL_30DB			(0x3 << 12)
217d8085222Sjohnnyhsu@realtek.com #define RT5631_MIC1_BOOST_CTRL_35DB			(0x4 << 12)
218d8085222Sjohnnyhsu@realtek.com #define RT5631_MIC1_BOOST_CTRL_40DB			(0x5 << 12)
219d8085222Sjohnnyhsu@realtek.com #define RT5631_MIC1_BOOST_CTRL_34DB			(0x6 << 12)
220d8085222Sjohnnyhsu@realtek.com #define RT5631_MIC1_BOOST_CTRL_50DB			(0x7 << 12)
221d8085222Sjohnnyhsu@realtek.com #define RT5631_MIC1_BOOST_CTRL_52DB			(0x8 << 12)
222d8085222Sjohnnyhsu@realtek.com #define RT5631_MIC1_BOOST_SHIFT			12
223d8085222Sjohnnyhsu@realtek.com 
224d8085222Sjohnnyhsu@realtek.com #define RT5631_MIC2_BOOST_CTRL_MASK			(0xf << 8)
225d8085222Sjohnnyhsu@realtek.com #define RT5631_MIC2_BOOST_CTRL_BYPASS		(0x0 << 8)
226d8085222Sjohnnyhsu@realtek.com #define RT5631_MIC2_BOOST_CTRL_20DB			(0x1 << 8)
227d8085222Sjohnnyhsu@realtek.com #define RT5631_MIC2_BOOST_CTRL_24DB			(0x2 << 8)
228d8085222Sjohnnyhsu@realtek.com #define RT5631_MIC2_BOOST_CTRL_30DB			(0x3 << 8)
229d8085222Sjohnnyhsu@realtek.com #define RT5631_MIC2_BOOST_CTRL_35DB			(0x4 << 8)
230d8085222Sjohnnyhsu@realtek.com #define RT5631_MIC2_BOOST_CTRL_40DB			(0x5 << 8)
231d8085222Sjohnnyhsu@realtek.com #define RT5631_MIC2_BOOST_CTRL_34DB			(0x6 << 8)
232d8085222Sjohnnyhsu@realtek.com #define RT5631_MIC2_BOOST_CTRL_50DB			(0x7 << 8)
233d8085222Sjohnnyhsu@realtek.com #define RT5631_MIC2_BOOST_CTRL_52DB			(0x8 << 8)
234d8085222Sjohnnyhsu@realtek.com #define RT5631_MIC2_BOOST_SHIFT			8
235d8085222Sjohnnyhsu@realtek.com 
236d8085222Sjohnnyhsu@realtek.com #define RT5631_MICBIAS1_VOLT_CTRL_MASK		(0x1 << 7)
237d8085222Sjohnnyhsu@realtek.com #define RT5631_MICBIAS1_VOLT_CTRL_90P			(0x0 << 7)
238d8085222Sjohnnyhsu@realtek.com #define RT5631_MICBIAS1_VOLT_CTRL_75P			(0x1 << 7)
239d8085222Sjohnnyhsu@realtek.com 
240d8085222Sjohnnyhsu@realtek.com #define RT5631_MICBIAS1_S_C_DET_MASK			(0x1 << 6)
241d8085222Sjohnnyhsu@realtek.com #define RT5631_MICBIAS1_S_C_DET_DIS			(0x0 << 6)
242d8085222Sjohnnyhsu@realtek.com #define RT5631_MICBIAS1_S_C_DET_ENA			(0x1 << 6)
243d8085222Sjohnnyhsu@realtek.com 
244d8085222Sjohnnyhsu@realtek.com #define RT5631_MICBIAS1_SHORT_CURR_DET_MASK		(0x3 << 4)
245d8085222Sjohnnyhsu@realtek.com #define RT5631_MICBIAS1_SHORT_CURR_DET_600UA	(0x0 << 4)
246d8085222Sjohnnyhsu@realtek.com #define RT5631_MICBIAS1_SHORT_CURR_DET_1500UA	(0x1 << 4)
247d8085222Sjohnnyhsu@realtek.com #define RT5631_MICBIAS1_SHORT_CURR_DET_2000UA	(0x2 << 4)
248d8085222Sjohnnyhsu@realtek.com 
249d8085222Sjohnnyhsu@realtek.com #define RT5631_MICBIAS2_VOLT_CTRL_MASK		(0x1 << 3)
250d8085222Sjohnnyhsu@realtek.com #define RT5631_MICBIAS2_VOLT_CTRL_90P			(0x0 << 3)
251d8085222Sjohnnyhsu@realtek.com #define RT5631_MICBIAS2_VOLT_CTRL_75P			(0x1 << 3)
252d8085222Sjohnnyhsu@realtek.com 
253d8085222Sjohnnyhsu@realtek.com #define RT5631_MICBIAS2_S_C_DET_MASK			(0x1 << 2)
254d8085222Sjohnnyhsu@realtek.com #define RT5631_MICBIAS2_S_C_DET_DIS			(0x0 << 2)
255d8085222Sjohnnyhsu@realtek.com #define RT5631_MICBIAS2_S_C_DET_ENA			(0x1 << 2)
256d8085222Sjohnnyhsu@realtek.com 
257d8085222Sjohnnyhsu@realtek.com #define RT5631_MICBIAS2_SHORT_CURR_DET_MASK		(0x3)
258d8085222Sjohnnyhsu@realtek.com #define RT5631_MICBIAS2_SHORT_CURR_DET_600UA	(0x0)
259d8085222Sjohnnyhsu@realtek.com #define RT5631_MICBIAS2_SHORT_CURR_DET_1500UA	(0x1)
260d8085222Sjohnnyhsu@realtek.com #define RT5631_MICBIAS2_SHORT_CURR_DET_2000UA	(0x2)
261d8085222Sjohnnyhsu@realtek.com 
262d8085222Sjohnnyhsu@realtek.com 
263d8085222Sjohnnyhsu@realtek.com /* Digital Microphone Control(0x24) */
264d8085222Sjohnnyhsu@realtek.com #define RT5631_DMIC_ENA_MASK				(0x1 << 15)
265d8085222Sjohnnyhsu@realtek.com #define RT5631_DMIC_ENA_SHIFT				15
266d8085222Sjohnnyhsu@realtek.com /* DMIC_ENA: DMIC to ADC Digital filter */
267d8085222Sjohnnyhsu@realtek.com #define RT5631_DMIC_ENA				(0x1 << 15)
268d8085222Sjohnnyhsu@realtek.com /* DMIC_DIS: ADC mixer to ADC Digital filter */
269d8085222Sjohnnyhsu@realtek.com #define RT5631_DMIC_DIS					(0x0 << 15)
270d8085222Sjohnnyhsu@realtek.com #define RT5631_DMIC_L_CH_MUTE				(0x1 << 13)
271d8085222Sjohnnyhsu@realtek.com #define RT5631_DMIC_L_CH_MUTE_SHIFT			13
272d8085222Sjohnnyhsu@realtek.com #define RT5631_DMIC_R_CH_MUTE				(0x1 << 12)
273d8085222Sjohnnyhsu@realtek.com #define RT5631_DMIC_R_CH_MUTE_SHIFT			12
274d8085222Sjohnnyhsu@realtek.com #define RT5631_DMIC_L_CH_LATCH_MASK			(0x1 << 9)
275d8085222Sjohnnyhsu@realtek.com #define RT5631_DMIC_L_CH_LATCH_RISING			(0x1 << 9)
276d8085222Sjohnnyhsu@realtek.com #define RT5631_DMIC_L_CH_LATCH_FALLING		(0x0 << 9)
277d8085222Sjohnnyhsu@realtek.com #define RT5631_DMIC_R_CH_LATCH_MASK			(0x1 << 8)
278d8085222Sjohnnyhsu@realtek.com #define RT5631_DMIC_R_CH_LATCH_RISING			(0x1 << 8)
279d8085222Sjohnnyhsu@realtek.com #define RT5631_DMIC_R_CH_LATCH_FALLING		(0x0 << 8)
280d8085222Sjohnnyhsu@realtek.com #define RT5631_DMIC_CLK_CTRL_MASK			(0x3 << 4)
281d8085222Sjohnnyhsu@realtek.com #define RT5631_DMIC_CLK_CTRL_TO_128FS			(0x0 << 4)
282d8085222Sjohnnyhsu@realtek.com #define RT5631_DMIC_CLK_CTRL_TO_64FS			(0x1 << 4)
283d8085222Sjohnnyhsu@realtek.com #define RT5631_DMIC_CLK_CTRL_TO_32FS			(0x2 << 4)
284d8085222Sjohnnyhsu@realtek.com 
285d8085222Sjohnnyhsu@realtek.com /* Microphone Input Volume(0x26) */
286d8085222Sjohnnyhsu@realtek.com #define RT5631_MONO_DIFF_INPUT_SHIFT			15
287d8085222Sjohnnyhsu@realtek.com 
288d8085222Sjohnnyhsu@realtek.com /* Speaker Mixer Control(0x28) */
289d8085222Sjohnnyhsu@realtek.com #define RT5631_M_RECMIXER_L_TO_SPKMIXER_L		(0x1 << 15)
290d8085222Sjohnnyhsu@realtek.com #define RT5631_M_RECMIXL_SPKMIXL_BIT			15
291d8085222Sjohnnyhsu@realtek.com #define RT5631_M_MIC1_P_TO_SPKMIXER_L		(0x1 << 14)
292d8085222Sjohnnyhsu@realtek.com #define RT5631_M_MIC1P_SPKMIXL_BIT			14
293d8085222Sjohnnyhsu@realtek.com #define RT5631_M_DAC_L_TO_SPKMIXER_L			(0x1 << 13)
294d8085222Sjohnnyhsu@realtek.com #define RT5631_M_DACL_SPKMIXL_BIT			13
295d8085222Sjohnnyhsu@realtek.com #define RT5631_M_OUTMIXER_L_TO_SPKMIXER_L		(0x1 << 12)
296d8085222Sjohnnyhsu@realtek.com #define RT5631_M_OUTMIXL_SPKMIXL_BIT			12
297d8085222Sjohnnyhsu@realtek.com 
298d8085222Sjohnnyhsu@realtek.com #define RT5631_M_RECMIXER_R_TO_SPKMIXER_R		(0x1 << 7)
299d8085222Sjohnnyhsu@realtek.com #define RT5631_M_RECMIXR_SPKMIXR_BIT			7
300d8085222Sjohnnyhsu@realtek.com #define RT5631_M_MIC2_P_TO_SPKMIXER_R		(0x1 << 6)
301d8085222Sjohnnyhsu@realtek.com #define RT5631_M_MIC2P_SPKMIXR_BIT			6
302d8085222Sjohnnyhsu@realtek.com #define RT5631_M_DAC_R_TO_SPKMIXER_R			(0x1 << 5)
303d8085222Sjohnnyhsu@realtek.com #define RT5631_M_DACR_SPKMIXR_BIT			5
304d8085222Sjohnnyhsu@realtek.com #define RT5631_M_OUTMIXER_R_TO_SPKMIXER_R		(0x1 << 4)
305d8085222Sjohnnyhsu@realtek.com #define RT5631_M_OUTMIXR_SPKMIXR_BIT			4
306d8085222Sjohnnyhsu@realtek.com 
307d8085222Sjohnnyhsu@realtek.com /* Speaker/Mono Output Control(0x2A) */
308d8085222Sjohnnyhsu@realtek.com #define RT5631_M_SPKVOL_L_TO_SPOL_MIXER		(0x1 << 15)
309d8085222Sjohnnyhsu@realtek.com #define RT5631_M_SPKVOLL_SPOLMIX_BIT			15
310d8085222Sjohnnyhsu@realtek.com #define RT5631_M_SPKVOL_R_TO_SPOL_MIXER		(0x1 << 14)
311d8085222Sjohnnyhsu@realtek.com #define RT5631_M_SPKVOLR_SPOLMIX_BIT			14
312d8085222Sjohnnyhsu@realtek.com #define RT5631_M_SPKVOL_L_TO_SPOR_MIXER		(0x1 << 13)
313d8085222Sjohnnyhsu@realtek.com #define RT5631_M_SPKVOLL_SPORMIX_BIT			13
314d8085222Sjohnnyhsu@realtek.com #define RT5631_M_SPKVOL_R_TO_SPOR_MIXER		(0x1 << 12)
315d8085222Sjohnnyhsu@realtek.com #define RT5631_M_SPKVOLR_SPORMIX_BIT			12
316d8085222Sjohnnyhsu@realtek.com #define RT5631_M_OUTVOL_L_TO_MONOMIXER		(0x1 << 11)
317d8085222Sjohnnyhsu@realtek.com #define RT5631_M_OUTVOLL_MONOMIX_BIT			11
318d8085222Sjohnnyhsu@realtek.com #define RT5631_M_OUTVOL_R_TO_MONOMIXER		(0x1 << 10)
319d8085222Sjohnnyhsu@realtek.com #define RT5631_M_OUTVOLR_MONOMIX_BIT			10
320d8085222Sjohnnyhsu@realtek.com 
321d8085222Sjohnnyhsu@realtek.com /* Speaker/Mono/HP Output Control(0x2C) */
322d8085222Sjohnnyhsu@realtek.com #define RT5631_SPK_L_MUX_SEL_MASK			(0x3 << 14)
323d8085222Sjohnnyhsu@realtek.com #define RT5631_SPK_L_MUX_SEL_SPKMIXER_L		(0x0 << 14)
324d8085222Sjohnnyhsu@realtek.com #define RT5631_SPK_L_MUX_SEL_MONO_IN			(0x1 << 14)
325d8085222Sjohnnyhsu@realtek.com #define RT5631_SPK_L_MUX_SEL_DAC_L			(0x3 << 14)
326d8085222Sjohnnyhsu@realtek.com #define RT5631_SPK_L_MUX_SEL_SHIFT			14
327d8085222Sjohnnyhsu@realtek.com 
328d8085222Sjohnnyhsu@realtek.com #define RT5631_SPK_R_MUX_SEL_MASK			(0x3 << 10)
329d8085222Sjohnnyhsu@realtek.com #define RT5631_SPK_R_MUX_SEL_SPKMIXER_R		(0x0 << 10)
330d8085222Sjohnnyhsu@realtek.com #define RT5631_SPK_R_MUX_SEL_MONO_IN			(0x1 << 10)
331d8085222Sjohnnyhsu@realtek.com #define RT5631_SPK_R_MUX_SEL_DAC_R			(0x3 << 10)
332d8085222Sjohnnyhsu@realtek.com #define RT5631_SPK_R_MUX_SEL_SHIFT			10
333d8085222Sjohnnyhsu@realtek.com 
334d8085222Sjohnnyhsu@realtek.com #define RT5631_MONO_MUX_SEL_MASK			(0x3 << 6)
335d8085222Sjohnnyhsu@realtek.com #define RT5631_MONO_MUX_SEL_MONOMIXER		(0x0 << 6)
336d8085222Sjohnnyhsu@realtek.com #define RT5631_MONO_MUX_SEL_MONO_IN			(0x1 << 6)
337d8085222Sjohnnyhsu@realtek.com #define RT5631_MONO_MUX_SEL_SHIFT			6
338d8085222Sjohnnyhsu@realtek.com 
339d8085222Sjohnnyhsu@realtek.com #define RT5631_HP_L_MUX_SEL_MASK			(0x1 << 3)
340d8085222Sjohnnyhsu@realtek.com #define RT5631_HP_L_MUX_SEL_HPVOL_L			(0x0 << 3)
341d8085222Sjohnnyhsu@realtek.com #define RT5631_HP_L_MUX_SEL_DAC_L			(0x1 << 3)
342d8085222Sjohnnyhsu@realtek.com #define RT5631_HP_L_MUX_SEL_SHIFT			3
343d8085222Sjohnnyhsu@realtek.com 
344d8085222Sjohnnyhsu@realtek.com #define RT5631_HP_R_MUX_SEL_MASK			(0x1 << 2)
345d8085222Sjohnnyhsu@realtek.com #define RT5631_HP_R_MUX_SEL_HPVOL_R			(0x0 << 2)
346d8085222Sjohnnyhsu@realtek.com #define RT5631_HP_R_MUX_SEL_DAC_R			(0x1 << 2)
347d8085222Sjohnnyhsu@realtek.com #define RT5631_HP_R_MUX_SEL_SHIFT			2
348d8085222Sjohnnyhsu@realtek.com 
349d8085222Sjohnnyhsu@realtek.com /* Stereo I2S Serial Data Port Control(0x34) */
350d8085222Sjohnnyhsu@realtek.com #define RT5631_SDP_MODE_SEL_MASK			(0x1 << 15)
351d8085222Sjohnnyhsu@realtek.com #define RT5631_SDP_MODE_SEL_MASTER			(0x0 << 15)
352d8085222Sjohnnyhsu@realtek.com #define RT5631_SDP_MODE_SEL_SLAVE			(0x1 << 15)
353d8085222Sjohnnyhsu@realtek.com 
354d8085222Sjohnnyhsu@realtek.com #define RT5631_SDP_ADC_CPS_SEL_MASK			(0x3 << 10)
355d8085222Sjohnnyhsu@realtek.com #define RT5631_SDP_ADC_CPS_SEL_OFF			(0x0 << 10)
356d8085222Sjohnnyhsu@realtek.com #define RT5631_SDP_ADC_CPS_SEL_U_LAW			(0x1 << 10)
357d8085222Sjohnnyhsu@realtek.com #define RT5631_SDP_ADC_CPS_SEL_A_LAW			(0x2 << 10)
358d8085222Sjohnnyhsu@realtek.com 
359d8085222Sjohnnyhsu@realtek.com #define RT5631_SDP_DAC_CPS_SEL_MASK			(0x3 << 8)
360d8085222Sjohnnyhsu@realtek.com #define RT5631_SDP_DAC_CPS_SEL_OFF			(0x0 << 8)
361d8085222Sjohnnyhsu@realtek.com #define RT5631_SDP_DAC_CPS_SEL_U_LAW			(0x1 << 8)
362d8085222Sjohnnyhsu@realtek.com #define RT5631_SDP_DAC_CPS_SEL_A_LAW			(0x2 << 8)
363d8085222Sjohnnyhsu@realtek.com /* 0:Normal 1:Invert */
364d8085222Sjohnnyhsu@realtek.com #define RT5631_SDP_I2S_BCLK_POL_CTRL			(0x1 << 7)
365d8085222Sjohnnyhsu@realtek.com /* 0:Normal 1:Invert */
366d8085222Sjohnnyhsu@realtek.com #define RT5631_SDP_DAC_R_INV				(0x1 << 6)
367d8085222Sjohnnyhsu@realtek.com /* 0:ADC data appear at left phase of LRCK
368d8085222Sjohnnyhsu@realtek.com  * 1:ADC data appear at right phase of LRCK
369d8085222Sjohnnyhsu@realtek.com  */
370d8085222Sjohnnyhsu@realtek.com #define RT5631_SDP_ADC_DATA_L_R_SWAP			(0x1 << 5)
371d8085222Sjohnnyhsu@realtek.com /* 0:DAC data appear at left phase of LRCK
372d8085222Sjohnnyhsu@realtek.com  * 1:DAC data appear at right phase of LRCK
373d8085222Sjohnnyhsu@realtek.com  */
374d8085222Sjohnnyhsu@realtek.com #define RT5631_SDP_DAC_DATA_L_R_SWAP			(0x1 << 4)
375d8085222Sjohnnyhsu@realtek.com 
376d8085222Sjohnnyhsu@realtek.com /* Data Length Slection */
377d8085222Sjohnnyhsu@realtek.com #define RT5631_SDP_I2S_DL_MASK				(0x3 << 2)
378d8085222Sjohnnyhsu@realtek.com #define RT5631_SDP_I2S_DL_16				(0x0 << 2)
379d8085222Sjohnnyhsu@realtek.com #define RT5631_SDP_I2S_DL_20				(0x1 << 2)
380d8085222Sjohnnyhsu@realtek.com #define RT5631_SDP_I2S_DL_24				(0x2 << 2)
381d8085222Sjohnnyhsu@realtek.com #define RT5631_SDP_I2S_DL_8				(0x3 << 2)
382d8085222Sjohnnyhsu@realtek.com 
383d8085222Sjohnnyhsu@realtek.com /* PCM Data Format Selection */
384d8085222Sjohnnyhsu@realtek.com #define RT5631_SDP_I2S_DF_MASK				(0x3)
385d8085222Sjohnnyhsu@realtek.com #define RT5631_SDP_I2S_DF_I2S				(0x0)
386d8085222Sjohnnyhsu@realtek.com #define RT5631_SDP_I2S_DF_LEFT				(0x1)
387d8085222Sjohnnyhsu@realtek.com #define RT5631_SDP_I2S_DF_PCM_A			(0x2)
388d8085222Sjohnnyhsu@realtek.com #define RT5631_SDP_I2S_DF_PCM_B			(0x3)
389d8085222Sjohnnyhsu@realtek.com 
390d8085222Sjohnnyhsu@realtek.com /* Stereo AD/DA Clock Control(0x38h) */
391d8085222Sjohnnyhsu@realtek.com #define RT5631_I2S_PRE_DIV_MASK			(0x7 << 13)
392d8085222Sjohnnyhsu@realtek.com #define RT5631_I2S_PRE_DIV_1				(0x0 << 13)
393d8085222Sjohnnyhsu@realtek.com #define RT5631_I2S_PRE_DIV_2				(0x1 << 13)
394d8085222Sjohnnyhsu@realtek.com #define RT5631_I2S_PRE_DIV_4				(0x2 << 13)
395d8085222Sjohnnyhsu@realtek.com #define RT5631_I2S_PRE_DIV_8				(0x3 << 13)
396d8085222Sjohnnyhsu@realtek.com #define RT5631_I2S_PRE_DIV_16				(0x4 << 13)
397d8085222Sjohnnyhsu@realtek.com #define RT5631_I2S_PRE_DIV_32				(0x5 << 13)
398d8085222Sjohnnyhsu@realtek.com /* CLOCK RELATIVE OF BCLK AND LCRK */
399d8085222Sjohnnyhsu@realtek.com #define RT5631_I2S_LRCK_SEL_N_BCLK_MASK		(0x1 << 12)
400d8085222Sjohnnyhsu@realtek.com #define RT5631_I2S_LRCK_SEL_64_BCLK			(0x0 << 12) /* 64FS */
401d8085222Sjohnnyhsu@realtek.com #define RT5631_I2S_LRCK_SEL_32_BCLK			(0x1 << 12) /* 32FS */
402d8085222Sjohnnyhsu@realtek.com 
403d8085222Sjohnnyhsu@realtek.com #define RT5631_DAC_OSR_SEL_MASK			(0x3 << 10)
404d8085222Sjohnnyhsu@realtek.com #define RT5631_DAC_OSR_SEL_128FS			(0x3 << 10)
405d8085222Sjohnnyhsu@realtek.com #define RT5631_DAC_OSR_SEL_64FS			(0x3 << 10)
406d8085222Sjohnnyhsu@realtek.com #define RT5631_DAC_OSR_SEL_32FS			(0x3 << 10)
407d8085222Sjohnnyhsu@realtek.com #define RT5631_DAC_OSR_SEL_16FS			(0x3 << 10)
408d8085222Sjohnnyhsu@realtek.com 
409d8085222Sjohnnyhsu@realtek.com #define RT5631_ADC_OSR_SEL_MASK			(0x3 << 8)
410d8085222Sjohnnyhsu@realtek.com #define RT5631_ADC_OSR_SEL_128FS			(0x3 << 8)
411d8085222Sjohnnyhsu@realtek.com #define RT5631_ADC_OSR_SEL_64FS			(0x3 << 8)
412d8085222Sjohnnyhsu@realtek.com #define RT5631_ADC_OSR_SEL_32FS			(0x3 << 8)
413d8085222Sjohnnyhsu@realtek.com #define RT5631_ADC_OSR_SEL_16FS			(0x3 << 8)
414d8085222Sjohnnyhsu@realtek.com 
415d8085222Sjohnnyhsu@realtek.com #define RT5631_ADDA_FILTER_CLK_SEL_256FS		(0 << 7) /* 256FS */
416d8085222Sjohnnyhsu@realtek.com #define RT5631_ADDA_FILTER_CLK_SEL_384FS		(1 << 7) /* 384FS */
417d8085222Sjohnnyhsu@realtek.com 
418d8085222Sjohnnyhsu@realtek.com /* Power managment addition 1 (0x3A) */
419d8085222Sjohnnyhsu@realtek.com #define RT5631_PWR_MAIN_I2S_EN			(0x1 << 15)
420d8085222Sjohnnyhsu@realtek.com #define RT5631_PWR_MAIN_I2S_BIT			15
421d8085222Sjohnnyhsu@realtek.com #define RT5631_PWR_CLASS_D				(0x1 << 12)
422d8085222Sjohnnyhsu@realtek.com #define RT5631_PWR_CLASS_D_BIT			12
423d8085222Sjohnnyhsu@realtek.com #define RT5631_PWR_ADC_L_CLK				(0x1 << 11)
424d8085222Sjohnnyhsu@realtek.com #define RT5631_PWR_ADC_L_CLK_BIT			11
425d8085222Sjohnnyhsu@realtek.com #define RT5631_PWR_ADC_R_CLK				(0x1 << 10)
426d8085222Sjohnnyhsu@realtek.com #define RT5631_PWR_ADC_R_CLK_BIT			10
427d8085222Sjohnnyhsu@realtek.com #define RT5631_PWR_DAC_L_CLK				(0x1 << 9)
428d8085222Sjohnnyhsu@realtek.com #define RT5631_PWR_DAC_L_CLK_BIT			9
429d8085222Sjohnnyhsu@realtek.com #define RT5631_PWR_DAC_R_CLK				(0x1 << 8)
430d8085222Sjohnnyhsu@realtek.com #define RT5631_PWR_DAC_R_CLK_BIT			8
431d8085222Sjohnnyhsu@realtek.com #define RT5631_PWR_DAC_REF				(0x1 << 7)
432d8085222Sjohnnyhsu@realtek.com #define RT5631_PWR_DAC_REF_BIT			7
433d8085222Sjohnnyhsu@realtek.com #define RT5631_PWR_DAC_L_TO_MIXER			(0x1 << 6)
434d8085222Sjohnnyhsu@realtek.com #define RT5631_PWR_DAC_L_TO_MIXER_BIT		6
435d8085222Sjohnnyhsu@realtek.com #define RT5631_PWR_DAC_R_TO_MIXER			(0x1 << 5)
436d8085222Sjohnnyhsu@realtek.com #define RT5631_PWR_DAC_R_TO_MIXER_BIT		5
437d8085222Sjohnnyhsu@realtek.com 
438d8085222Sjohnnyhsu@realtek.com /* Power managment addition 2 (0x3B) */
439d8085222Sjohnnyhsu@realtek.com #define RT5631_PWR_OUTMIXER_L				(0x1 << 15)
440d8085222Sjohnnyhsu@realtek.com #define RT5631_PWR_OUTMIXER_L_BIT			15
441d8085222Sjohnnyhsu@realtek.com #define RT5631_PWR_OUTMIXER_R				(0x1 << 14)
442d8085222Sjohnnyhsu@realtek.com #define RT5631_PWR_OUTMIXER_R_BIT			14
443d8085222Sjohnnyhsu@realtek.com #define RT5631_PWR_SPKMIXER_L				(0x1 << 13)
444d8085222Sjohnnyhsu@realtek.com #define RT5631_PWR_SPKMIXER_L_BIT			13
445d8085222Sjohnnyhsu@realtek.com #define RT5631_PWR_SPKMIXER_R				(0x1 << 12)
446d8085222Sjohnnyhsu@realtek.com #define RT5631_PWR_SPKMIXER_R_BIT			12
447d8085222Sjohnnyhsu@realtek.com #define RT5631_PWR_RECMIXER_L				(0x1 << 11)
448d8085222Sjohnnyhsu@realtek.com #define RT5631_PWR_RECMIXER_L_BIT			11
449d8085222Sjohnnyhsu@realtek.com #define RT5631_PWR_RECMIXER_R				(0x1 << 10)
450d8085222Sjohnnyhsu@realtek.com #define RT5631_PWR_RECMIXER_R_BIT			10
451d8085222Sjohnnyhsu@realtek.com #define RT5631_PWR_MIC1_BOOT_GAIN			(0x1 << 5)
452d8085222Sjohnnyhsu@realtek.com #define RT5631_PWR_MIC1_BOOT_GAIN_BIT		5
453d8085222Sjohnnyhsu@realtek.com #define RT5631_PWR_MIC2_BOOT_GAIN			(0x1 << 4)
454d8085222Sjohnnyhsu@realtek.com #define RT5631_PWR_MIC2_BOOT_GAIN_BIT		4
455d8085222Sjohnnyhsu@realtek.com #define RT5631_PWR_MICBIAS1_VOL			(0x1 << 3)
456d8085222Sjohnnyhsu@realtek.com #define RT5631_PWR_MICBIAS1_VOL_BIT			3
457d8085222Sjohnnyhsu@realtek.com #define RT5631_PWR_MICBIAS2_VOL			(0x1 << 2)
458d8085222Sjohnnyhsu@realtek.com #define RT5631_PWR_MICBIAS2_VOL_BIT			2
459d8085222Sjohnnyhsu@realtek.com #define RT5631_PWR_PLL1				(0x1 << 1)
460d8085222Sjohnnyhsu@realtek.com #define RT5631_PWR_PLL1_BIT				1
461d8085222Sjohnnyhsu@realtek.com #define RT5631_PWR_PLL2				(0x1 << 0)
462d8085222Sjohnnyhsu@realtek.com #define RT5631_PWR_PLL2_BIT				0
463d8085222Sjohnnyhsu@realtek.com 
464d8085222Sjohnnyhsu@realtek.com /* Power managment addition 3(0x3C) */
465d8085222Sjohnnyhsu@realtek.com #define RT5631_PWR_VREF				(0x1 << 15)
466d8085222Sjohnnyhsu@realtek.com #define RT5631_PWR_VREF_BIT				15
467d8085222Sjohnnyhsu@realtek.com #define RT5631_PWR_FAST_VREF_CTRL			(0x1 << 14)
468d8085222Sjohnnyhsu@realtek.com #define RT5631_PWR_FAST_VREF_CTRL_BIT			14
469d8085222Sjohnnyhsu@realtek.com #define RT5631_PWR_MAIN_BIAS				(0x1 << 13)
470d8085222Sjohnnyhsu@realtek.com #define RT5631_PWR_MAIN_BIAS_BIT			13
471d8085222Sjohnnyhsu@realtek.com #define RT5631_PWR_AXO1MIXER				(0x1 << 11)
472d8085222Sjohnnyhsu@realtek.com #define RT5631_PWR_AXO1MIXER_BIT			11
473d8085222Sjohnnyhsu@realtek.com #define RT5631_PWR_AXO2MIXER				(0x1 << 10)
474d8085222Sjohnnyhsu@realtek.com #define RT5631_PWR_AXO2MIXER_BIT			10
475d8085222Sjohnnyhsu@realtek.com #define RT5631_PWR_MONOMIXER				(0x1 << 9)
476d8085222Sjohnnyhsu@realtek.com #define RT5631_PWR_MONOMIXER_BIT			9
477d8085222Sjohnnyhsu@realtek.com #define RT5631_PWR_MONO_DEPOP_DIS			(0x1 << 8)
478d8085222Sjohnnyhsu@realtek.com #define RT5631_PWR_MONO_DEPOP_DIS_BIT		8
479d8085222Sjohnnyhsu@realtek.com #define RT5631_PWR_MONO_AMP_EN			(0x1 << 7)
480d8085222Sjohnnyhsu@realtek.com #define RT5631_PWR_MONO_AMP_EN_BIT			7
481d8085222Sjohnnyhsu@realtek.com #define RT5631_PWR_CHARGE_PUMP			(0x1 << 4)
482d8085222Sjohnnyhsu@realtek.com #define RT5631_PWR_CHARGE_PUMP_BIT			4
483d8085222Sjohnnyhsu@realtek.com #define RT5631_PWR_HP_L_AMP				(0x1 << 3)
484d8085222Sjohnnyhsu@realtek.com #define RT5631_PWR_HP_L_AMP_BIT			3
485d8085222Sjohnnyhsu@realtek.com #define RT5631_PWR_HP_R_AMP				(0x1 << 2)
486d8085222Sjohnnyhsu@realtek.com #define RT5631_PWR_HP_R_AMP_BIT			2
487d8085222Sjohnnyhsu@realtek.com #define RT5631_PWR_HP_DEPOP_DIS			(0x1 << 1)
488d8085222Sjohnnyhsu@realtek.com #define RT5631_PWR_HP_DEPOP_DIS_BIT			1
489d8085222Sjohnnyhsu@realtek.com #define RT5631_PWR_HP_AMP_DRIVING			(0x1 << 0)
490d8085222Sjohnnyhsu@realtek.com #define RT5631_PWR_HP_AMP_DRIVING_BIT		0
491d8085222Sjohnnyhsu@realtek.com 
492d8085222Sjohnnyhsu@realtek.com /* Power managment addition 4(0x3E) */
493d8085222Sjohnnyhsu@realtek.com #define RT5631_PWR_SPK_L_VOL				(0x1 << 15)
494d8085222Sjohnnyhsu@realtek.com #define RT5631_PWR_SPK_L_VOL_BIT			15
495d8085222Sjohnnyhsu@realtek.com #define RT5631_PWR_SPK_R_VOL				(0x1 << 14)
496d8085222Sjohnnyhsu@realtek.com #define RT5631_PWR_SPK_R_VOL_BIT			14
497d8085222Sjohnnyhsu@realtek.com #define RT5631_PWR_LOUT_VOL				(0x1 << 13)
498d8085222Sjohnnyhsu@realtek.com #define RT5631_PWR_LOUT_VOL_BIT			13
499d8085222Sjohnnyhsu@realtek.com #define RT5631_PWR_ROUT_VOL				(0x1 << 12)
500d8085222Sjohnnyhsu@realtek.com #define RT5631_PWR_ROUT_VOL_BIT			12
501d8085222Sjohnnyhsu@realtek.com #define RT5631_PWR_HP_L_OUT_VOL			(0x1 << 11)
502d8085222Sjohnnyhsu@realtek.com #define RT5631_PWR_HP_L_OUT_VOL_BIT			11
503d8085222Sjohnnyhsu@realtek.com #define RT5631_PWR_HP_R_OUT_VOL			(0x1 << 10)
504d8085222Sjohnnyhsu@realtek.com #define RT5631_PWR_HP_R_OUT_VOL_BIT			10
505d8085222Sjohnnyhsu@realtek.com #define RT5631_PWR_AXIL_IN_VOL				(0x1 << 9)
506d8085222Sjohnnyhsu@realtek.com #define RT5631_PWR_AXIL_IN_VOL_BIT			9
507d8085222Sjohnnyhsu@realtek.com #define RT5631_PWR_AXIR_IN_VOL			(0x1 << 8)
508d8085222Sjohnnyhsu@realtek.com #define RT5631_PWR_AXIR_IN_VOL_BIT			8
509d8085222Sjohnnyhsu@realtek.com #define RT5631_PWR_MONO_IN_P_VOL			(0x1 << 7)
510d8085222Sjohnnyhsu@realtek.com #define RT5631_PWR_MONO_IN_P_VOL_BIT			7
511d8085222Sjohnnyhsu@realtek.com #define RT5631_PWR_MONO_IN_N_VOL			(0x1 << 6)
512d8085222Sjohnnyhsu@realtek.com #define RT5631_PWR_MONO_IN_N_VOL_BIT			6
513d8085222Sjohnnyhsu@realtek.com 
514d8085222Sjohnnyhsu@realtek.com /* General Purpose Control Register(0x40) */
515d8085222Sjohnnyhsu@realtek.com #define RT5631_SPK_AMP_AUTO_RATIO_EN			(0x1 << 15)
516d8085222Sjohnnyhsu@realtek.com 
517d8085222Sjohnnyhsu@realtek.com #define RT5631_SPK_AMP_RATIO_CTRL_MASK		(0x7 << 12)
518d8085222Sjohnnyhsu@realtek.com #define RT5631_SPK_AMP_RATIO_CTRL_2_34		(0x0 << 12) /* 7.40DB */
519d8085222Sjohnnyhsu@realtek.com #define RT5631_SPK_AMP_RATIO_CTRL_1_99		(0x1 << 12) /* 5.99DB */
520d8085222Sjohnnyhsu@realtek.com #define RT5631_SPK_AMP_RATIO_CTRL_1_68		(0x2 << 12) /* 4.50DB */
521d8085222Sjohnnyhsu@realtek.com #define RT5631_SPK_AMP_RATIO_CTRL_1_56		(0x3 << 12) /* 3.86DB */
522d8085222Sjohnnyhsu@realtek.com #define RT5631_SPK_AMP_RATIO_CTRL_1_44		(0x4 << 12) /* 3.16DB */
523d8085222Sjohnnyhsu@realtek.com #define RT5631_SPK_AMP_RATIO_CTRL_1_27		(0x5 << 12) /* 2.10DB */
524d8085222Sjohnnyhsu@realtek.com #define RT5631_SPK_AMP_RATIO_CTRL_1_09		(0x6 << 12) /* 0.80DB */
525d8085222Sjohnnyhsu@realtek.com #define RT5631_SPK_AMP_RATIO_CTRL_1_00		(0x7 << 12) /* 0.00DB */
526d8085222Sjohnnyhsu@realtek.com #define RT5631_SPK_AMP_RATIO_CTRL_SHIFT		12
527d8085222Sjohnnyhsu@realtek.com 
528d8085222Sjohnnyhsu@realtek.com #define RT5631_STEREO_DAC_HI_PASS_FILT_EN		(0x1 << 11)
529d8085222Sjohnnyhsu@realtek.com #define RT5631_STEREO_ADC_HI_PASS_FILT_EN		(0x1 << 10)
530d8085222Sjohnnyhsu@realtek.com /* Select ADC Wind Filter Clock type */
531d8085222Sjohnnyhsu@realtek.com #define RT5631_ADC_WIND_FILT_MASK			(0x3 << 4)
532d8085222Sjohnnyhsu@realtek.com #define RT5631_ADC_WIND_FILT_8_16_32K			(0x0 << 4) /*8/16/32k*/
533d8085222Sjohnnyhsu@realtek.com #define RT5631_ADC_WIND_FILT_11_22_44K		(0x1 << 4) /*11/22/44k*/
534d8085222Sjohnnyhsu@realtek.com #define RT5631_ADC_WIND_FILT_12_24_48K		(0x2 << 4) /*12/24/48k*/
535d8085222Sjohnnyhsu@realtek.com #define RT5631_ADC_WIND_FILT_EN			(0x1 << 3)
536d8085222Sjohnnyhsu@realtek.com /* SelectADC Wind Filter Corner Frequency */
537d8085222Sjohnnyhsu@realtek.com #define RT5631_ADC_WIND_CNR_FREQ_MASK	(0x7 << 0)
538d8085222Sjohnnyhsu@realtek.com #define RT5631_ADC_WIND_CNR_FREQ_82_113_122	(0x0 << 0) /* 82/113/122 Hz */
539d8085222Sjohnnyhsu@realtek.com #define RT5631_ADC_WIND_CNR_FREQ_102_141_153 (0x1 << 0) /* 102/141/153 Hz */
540d8085222Sjohnnyhsu@realtek.com #define RT5631_ADC_WIND_CNR_FREQ_131_180_156 (0x2 << 0) /* 131/180/156 Hz */
541d8085222Sjohnnyhsu@realtek.com #define RT5631_ADC_WIND_CNR_FREQ_163_225_245 (0x3 << 0) /* 163/225/245 Hz */
542d8085222Sjohnnyhsu@realtek.com #define RT5631_ADC_WIND_CNR_FREQ_204_281_306 (0x4 << 0) /* 204/281/306 Hz */
543d8085222Sjohnnyhsu@realtek.com #define RT5631_ADC_WIND_CNR_FREQ_261_360_392 (0x5 << 0) /* 261/360/392 Hz */
544d8085222Sjohnnyhsu@realtek.com #define RT5631_ADC_WIND_CNR_FREQ_327_450_490 (0x6 << 0) /* 327/450/490 Hz */
545d8085222Sjohnnyhsu@realtek.com #define RT5631_ADC_WIND_CNR_FREQ_408_563_612 (0x7 << 0) /* 408/563/612 Hz */
546d8085222Sjohnnyhsu@realtek.com 
547d8085222Sjohnnyhsu@realtek.com /* Global Clock Control Register(0x42) */
548d8085222Sjohnnyhsu@realtek.com #define RT5631_SYSCLK_SOUR_SEL_MASK			(0x3 << 14)
549d8085222Sjohnnyhsu@realtek.com #define RT5631_SYSCLK_SOUR_SEL_MCLK			(0x0 << 14)
550d8085222Sjohnnyhsu@realtek.com #define RT5631_SYSCLK_SOUR_SEL_PLL			(0x1 << 14)
551d8085222Sjohnnyhsu@realtek.com #define RT5631_SYSCLK_SOUR_SEL_PLL_TCK		(0x2 << 14)
552d8085222Sjohnnyhsu@realtek.com 
553d8085222Sjohnnyhsu@realtek.com #define RT5631_PLLCLK_SOUR_SEL_MASK			(0x3 << 12)
554d8085222Sjohnnyhsu@realtek.com #define RT5631_PLLCLK_SOUR_SEL_MCLK			(0x0 << 12)
555d8085222Sjohnnyhsu@realtek.com #define RT5631_PLLCLK_SOUR_SEL_BCLK			(0x1 << 12)
556d8085222Sjohnnyhsu@realtek.com #define RT5631_PLLCLK_SOUR_SEL_VBCLK			(0x2 << 12)
557d8085222Sjohnnyhsu@realtek.com 
558d8085222Sjohnnyhsu@realtek.com #define RT5631_PLLCLK_PRE_DIV1				(0x0 << 11)
559d8085222Sjohnnyhsu@realtek.com #define RT5631_PLLCLK_PRE_DIV2				(0x1 << 11)
560d8085222Sjohnnyhsu@realtek.com 
561d8085222Sjohnnyhsu@realtek.com /* PLL Control(0x44) */
562d8085222Sjohnnyhsu@realtek.com #define RT5631_PLL_CTRL_M_VAL(m)			((m)&0xf)
563d8085222Sjohnnyhsu@realtek.com #define RT5631_PLL_CTRL_K_VAL(k)			(((k)&0x7) << 4)
564d8085222Sjohnnyhsu@realtek.com #define RT5631_PLL_CTRL_N_VAL(n)			(((n)&0xff) << 8)
565d8085222Sjohnnyhsu@realtek.com 
566d8085222Sjohnnyhsu@realtek.com /* Internal Status and IRQ Control2(0x4A) */
567d8085222Sjohnnyhsu@realtek.com #define RT5631_ADC_DATA_SEL_MASK			(0x3 << 14)
568d8085222Sjohnnyhsu@realtek.com #define RT5631_ADC_DATA_SEL_Disable			(0x0 << 14)
569d8085222Sjohnnyhsu@realtek.com #define RT5631_ADC_DATA_SEL_MIC1			(0x1 << 14)
570d8085222Sjohnnyhsu@realtek.com #define RT5631_ADC_DATA_SEL_MIC1_SHIFT		14
571d8085222Sjohnnyhsu@realtek.com #define RT5631_ADC_DATA_SEL_MIC2			(0x2 << 14)
572d8085222Sjohnnyhsu@realtek.com #define RT5631_ADC_DATA_SEL_MIC2_SHIFT		15
573d8085222Sjohnnyhsu@realtek.com #define RT5631_ADC_DATA_SEL_STO			(0x3 << 14)
574d8085222Sjohnnyhsu@realtek.com #define RT5631_ADC_DATA_SEL_SHIFT			14
575d8085222Sjohnnyhsu@realtek.com 
576d8085222Sjohnnyhsu@realtek.com /* GPIO Pin Configuration(0x4C) */
577d8085222Sjohnnyhsu@realtek.com #define RT5631_GPIO_PIN_FUN_SEL_MASK			(0x1 << 15)
578d8085222Sjohnnyhsu@realtek.com #define RT5631_GPIO_PIN_FUN_SEL_IRQ			(0x1 << 15)
579d8085222Sjohnnyhsu@realtek.com #define RT5631_GPIO_PIN_FUN_SEL_GPIO_DIMC		(0x0 << 15)
580d8085222Sjohnnyhsu@realtek.com 
581d8085222Sjohnnyhsu@realtek.com #define RT5631_GPIO_DMIC_FUN_SEL_MASK		(0x1 << 3)
582d8085222Sjohnnyhsu@realtek.com #define RT5631_GPIO_DMIC_FUN_SEL_DIMC		(0x1 << 3)
583d8085222Sjohnnyhsu@realtek.com #define RT5631_GPIO_DMIC_FUN_SEL_GPIO			(0x0 << 3)
584d8085222Sjohnnyhsu@realtek.com 
585d8085222Sjohnnyhsu@realtek.com #define RT5631_GPIO_PIN_CON_MASK			(0x1 << 2)
586d8085222Sjohnnyhsu@realtek.com #define RT5631_GPIO_PIN_SET_INPUT			(0x0 << 2)
587d8085222Sjohnnyhsu@realtek.com #define RT5631_GPIO_PIN_SET_OUTPUT			(0x1 << 2)
588d8085222Sjohnnyhsu@realtek.com 
589d8085222Sjohnnyhsu@realtek.com /* De-POP function Control 1(0x54) */
590d8085222Sjohnnyhsu@realtek.com #define RT5631_POW_ON_SOFT_GEN			(0x1 << 15)
591d8085222Sjohnnyhsu@realtek.com #define RT5631_EN_MUTE_UNMUTE_DEPOP			(0x1 << 14)
592d8085222Sjohnnyhsu@realtek.com #define RT5631_EN_DEPOP2_FOR_HP			(0x1 << 7)
593d8085222Sjohnnyhsu@realtek.com /* Power Down HPAMP_L Starts Up Signal */
594d8085222Sjohnnyhsu@realtek.com #define RT5631_PD_HPAMP_L_ST_UP			(0x1 << 5)
595d8085222Sjohnnyhsu@realtek.com /* Power Down HPAMP_R Starts Up Signal */
596d8085222Sjohnnyhsu@realtek.com #define RT5631_PD_HPAMP_R_ST_UP			(0x1 << 4)
597d8085222Sjohnnyhsu@realtek.com /* Enable left HP mute/unmute depop */
598d8085222Sjohnnyhsu@realtek.com #define RT5631_EN_HP_L_M_UN_MUTE_DEPOP		(0x1 << 1)
599d8085222Sjohnnyhsu@realtek.com /* Enable right HP mute/unmute depop */
600d8085222Sjohnnyhsu@realtek.com #define RT5631_EN_HP_R_M_UN_MUTE_DEPOP		(0x1 << 0)
601d8085222Sjohnnyhsu@realtek.com 
602d8085222Sjohnnyhsu@realtek.com /* De-POP Fnction Control(0x56) */
603d8085222Sjohnnyhsu@realtek.com #define RT5631_EN_ONE_BIT_DEPOP			(0x1 << 15)
604d8085222Sjohnnyhsu@realtek.com #define RT5631_EN_CAP_FREE_DEPOP			(0x1 << 14)
605d8085222Sjohnnyhsu@realtek.com 
606d8085222Sjohnnyhsu@realtek.com /* Jack Detect Control Register(0x5A) */
607d8085222Sjohnnyhsu@realtek.com #define RT5631_JD_USE_MASK				(0x3 << 14)
608d8085222Sjohnnyhsu@realtek.com #define RT5631_JD_USE_JD2				(0x3 << 14)
609d8085222Sjohnnyhsu@realtek.com #define RT5631_JD_USE_JD1				(0x2 << 14)
610d8085222Sjohnnyhsu@realtek.com #define RT5631_JD_USE_GPIO				(0x1 << 14)
611d8085222Sjohnnyhsu@realtek.com #define RT5631_JD_OFF					(0x0 << 14)
612d8085222Sjohnnyhsu@realtek.com /* JD trigger enable for HP */
613d8085222Sjohnnyhsu@realtek.com #define RT5631_JD_HP_EN					(0x1 << 11)
614d8085222Sjohnnyhsu@realtek.com #define RT5631_JD_HP_TRI_MASK				(0x1 << 10)
615d8085222Sjohnnyhsu@realtek.com #define RT5631_JD_HP_TRI_HI				(0x1 << 10)
616d8085222Sjohnnyhsu@realtek.com #define RT5631_JD_HP_TRI_LO				(0x1 << 10)
617d8085222Sjohnnyhsu@realtek.com /* JD trigger enable for speaker LP/LN */
618d8085222Sjohnnyhsu@realtek.com #define RT5631_JD_SPK_L_EN				(0x1 << 9)
619d8085222Sjohnnyhsu@realtek.com #define RT5631_JD_SPK_L_TRI_MASK			(0x1 << 8)
620d8085222Sjohnnyhsu@realtek.com #define RT5631_JD_SPK_L_TRI_HI				(0x1 << 8)
621d8085222Sjohnnyhsu@realtek.com #define RT5631_JD_SPK_L_TRI_LO				(0x0 << 8)
622d8085222Sjohnnyhsu@realtek.com /* JD trigger enable for speaker RP/RN */
623d8085222Sjohnnyhsu@realtek.com #define RT5631_JD_SPK_R_EN				(0x1 << 7)
624d8085222Sjohnnyhsu@realtek.com #define RT5631_JD_SPK_R_TRI_MASK			(0x1 << 6)
625d8085222Sjohnnyhsu@realtek.com #define RT5631_JD_SPK_R_TRI_HI				(0x1 << 6)
626d8085222Sjohnnyhsu@realtek.com #define RT5631_JD_SPK_R_TRI_LO				(0x0 << 6)
627d8085222Sjohnnyhsu@realtek.com /* JD trigger enable for monoout */
628d8085222Sjohnnyhsu@realtek.com #define RT5631_JD_MONO_EN				(0x1 << 5)
629d8085222Sjohnnyhsu@realtek.com #define RT5631_JD_MONO_TRI_MASK			(0x1 << 4)
630d8085222Sjohnnyhsu@realtek.com #define RT5631_JD_MONO_TRI_HI				(0x1 << 4)
631d8085222Sjohnnyhsu@realtek.com #define RT5631_JD_MONO_TRI_LO				(0x0 << 4)
632d8085222Sjohnnyhsu@realtek.com /* JD trigger enable for Lout */
633d8085222Sjohnnyhsu@realtek.com #define RT5631_JD_AUX_1_EN				(0x1 << 3)
634d8085222Sjohnnyhsu@realtek.com #define RT5631_JD_AUX_1_MASK				(0x1 << 2)
635d8085222Sjohnnyhsu@realtek.com #define RT5631_JD_AUX_1_TRI_HI				(0x1 << 2)
636d8085222Sjohnnyhsu@realtek.com #define RT5631_JD_AUX_1_TRI_LO				(0x0 << 2)
637d8085222Sjohnnyhsu@realtek.com /* JD trigger enable for Rout */
638d8085222Sjohnnyhsu@realtek.com #define RT5631_JD_AUX_2_EN				(0x1 << 1)
639d8085222Sjohnnyhsu@realtek.com #define RT5631_JD_AUX_2_MASK				(0x1 << 0)
640d8085222Sjohnnyhsu@realtek.com #define RT5631_JD_AUX_2_TRI_HI				(0x1 << 0)
641d8085222Sjohnnyhsu@realtek.com #define RT5631_JD_AUX_2_TRI_LO				(0x0 << 0)
642d8085222Sjohnnyhsu@realtek.com 
643d8085222Sjohnnyhsu@realtek.com /* ALC CONTROL 1(0x64) */
644d8085222Sjohnnyhsu@realtek.com #define RT5631_ALC_ATTACK_RATE_MASK			(0x1F << 8)
645d8085222Sjohnnyhsu@realtek.com #define RT5631_ALC_RECOVERY_RATE_MASK		(0x1F << 0)
646d8085222Sjohnnyhsu@realtek.com 
647d8085222Sjohnnyhsu@realtek.com /* ALC CONTROL 2(0x65) */
648d8085222Sjohnnyhsu@realtek.com /* select Compensation gain for Noise gate function */
649d8085222Sjohnnyhsu@realtek.com #define RT5631_ALC_COM_NOISE_GATE_MASK		(0xF << 0)
650d8085222Sjohnnyhsu@realtek.com 
651d8085222Sjohnnyhsu@realtek.com /* ALC CONTROL 3(0x66) */
652d8085222Sjohnnyhsu@realtek.com #define RT5631_ALC_FUN_MASK				(0x3 << 14)
653d8085222Sjohnnyhsu@realtek.com #define RT5631_ALC_FUN_DIS				(0x0 << 14)
654d8085222Sjohnnyhsu@realtek.com #define RT5631_ALC_ENA_DAC_PATH			(0x1 << 14)
655d8085222Sjohnnyhsu@realtek.com #define RT5631_ALC_ENA_ADC_PATH			(0x3 << 14)
656d8085222Sjohnnyhsu@realtek.com #define RT5631_ALC_PARA_UPDATE			(0x1 << 13)
657d8085222Sjohnnyhsu@realtek.com #define RT5631_ALC_LIMIT_LEVEL_MASK			(0x1F << 8)
658d8085222Sjohnnyhsu@realtek.com #define RT5631_ALC_NOISE_GATE_FUN_MASK		(0x1 << 7)
659d8085222Sjohnnyhsu@realtek.com #define RT5631_ALC_NOISE_GATE_FUN_DIS			(0x0 << 7)
660d8085222Sjohnnyhsu@realtek.com #define RT5631_ALC_NOISE_GATE_FUN_ENA		(0x1 << 7)
661d8085222Sjohnnyhsu@realtek.com /* ALC noise gate hold data function */
662d8085222Sjohnnyhsu@realtek.com #define RT5631_ALC_NOISE_GATE_H_D_MASK		(0x1 << 6)
663d8085222Sjohnnyhsu@realtek.com #define RT5631_ALC_NOISE_GATE_H_D_DIS			(0x0 << 6)
664d8085222Sjohnnyhsu@realtek.com #define RT5631_ALC_NOISE_GATE_H_D_ENA		(0x1 << 6)
665d8085222Sjohnnyhsu@realtek.com 
666d8085222Sjohnnyhsu@realtek.com /* Psedueo Stereo & Spatial Effect Block Control(0x68) */
667d8085222Sjohnnyhsu@realtek.com #define RT5631_SPATIAL_CTRL_EN				(0x1 << 15)
668d8085222Sjohnnyhsu@realtek.com #define RT5631_ALL_PASS_FILTER_EN			(0x1 << 14)
669d8085222Sjohnnyhsu@realtek.com #define RT5631_PSEUDO_STEREO_EN			(0x1 << 13)
670d8085222Sjohnnyhsu@realtek.com #define RT5631_STEREO_EXPENSION_EN			(0x1 << 12)
671d8085222Sjohnnyhsu@realtek.com /* 3D gain parameter */
672d8085222Sjohnnyhsu@realtek.com #define RT5631_GAIN_3D_PARA_MASK		(0x3 << 6)
673d8085222Sjohnnyhsu@realtek.com #define RT5631_GAIN_3D_PARA_1_00		(0x0 << 6) /* 3D gain 1.0 */
674d8085222Sjohnnyhsu@realtek.com #define RT5631_GAIN_3D_PARA_1_50		(0x1 << 6) /* 3D gain 1.5 */
675d8085222Sjohnnyhsu@realtek.com #define RT5631_GAIN_3D_PARA_2_00		(0x2 << 6) /* 3D gain 2.0 */
676d8085222Sjohnnyhsu@realtek.com /* 3D ratio parameter */
677d8085222Sjohnnyhsu@realtek.com #define RT5631_RATIO_3D_MASK			(0x3 << 4)
678d8085222Sjohnnyhsu@realtek.com #define RT5631_RATIO_3D_0_0			(0x0 << 4) /* 3D ratio 0.0 */
679d8085222Sjohnnyhsu@realtek.com #define RT5631_RATIO_3D_0_66			(0x1 << 4) /* 3D ratio 0.66 */
680d8085222Sjohnnyhsu@realtek.com #define RT5631_RATIO_3D_1_0			(0x2 << 4) /* 3D ratio 1.0 */
681d8085222Sjohnnyhsu@realtek.com /* select samplerate for all pass filter */
682d8085222Sjohnnyhsu@realtek.com #define RT5631_APF_FUN_SLE_MASK			(0x3 << 0)
683d8085222Sjohnnyhsu@realtek.com #define RT5631_APF_FUN_SEL_48K				(0x3 << 0)
684d8085222Sjohnnyhsu@realtek.com #define RT5631_APF_FUN_SEL_44_1K			(0x2 << 0)
685d8085222Sjohnnyhsu@realtek.com #define RT5631_APF_FUN_SEL_32K				(0x1 << 0)
686d8085222Sjohnnyhsu@realtek.com #define RT5631_APF_FUN_DIS				(0x0 << 0)
687d8085222Sjohnnyhsu@realtek.com 
688d8085222Sjohnnyhsu@realtek.com /* EQ CONTROL 1(0x6E) */
689d8085222Sjohnnyhsu@realtek.com #define RT5631_HW_EQ_PATH_SEL_MASK			(0x1 << 15)
690d8085222Sjohnnyhsu@realtek.com #define RT5631_HW_EQ_PATH_SEL_DAC			(0x0 << 15)
691d8085222Sjohnnyhsu@realtek.com #define RT5631_HW_EQ_PATH_SEL_ADC			(0x1 << 15)
692d8085222Sjohnnyhsu@realtek.com #define RT5631_HW_EQ_UPDATE_CTRL			(0x1 << 14)
693d8085222Sjohnnyhsu@realtek.com 
694d8085222Sjohnnyhsu@realtek.com #define RT5631_EN_HW_EQ_HPF2				(0x1 << 5)
695d8085222Sjohnnyhsu@realtek.com #define RT5631_EN_HW_EQ_HPF1				(0x1 << 4)
696d8085222Sjohnnyhsu@realtek.com #define RT5631_EN_HW_EQ_BP3				(0x1 << 3)
697d8085222Sjohnnyhsu@realtek.com #define RT5631_EN_HW_EQ_BP2				(0x1 << 2)
698d8085222Sjohnnyhsu@realtek.com #define RT5631_EN_HW_EQ_BP1				(0x1 << 1)
699d8085222Sjohnnyhsu@realtek.com #define RT5631_EN_HW_EQ_LPF				(0x1 << 0)
700d8085222Sjohnnyhsu@realtek.com 
701d8085222Sjohnnyhsu@realtek.com 
702d8085222Sjohnnyhsu@realtek.com #endif /* __RTCODEC5631_H__ */
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