xref: /openbmc/linux/sound/soc/codecs/rt5514.h (revision 4a6180ea)
14a6180eaSOder Chiou /*
24a6180eaSOder Chiou  * rt5514.h  --  RT5514 ALSA SoC audio driver
34a6180eaSOder Chiou  *
44a6180eaSOder Chiou  * Copyright 2015 Realtek Microelectronics
54a6180eaSOder Chiou  * Author: Oder Chiou <oder_chiou@realtek.com>
64a6180eaSOder Chiou  *
74a6180eaSOder Chiou  * This program is free software; you can redistribute it and/or modify
84a6180eaSOder Chiou  * it under the terms of the GNU General Public License version 2 as
94a6180eaSOder Chiou  * published by the Free Software Foundation.
104a6180eaSOder Chiou  */
114a6180eaSOder Chiou 
124a6180eaSOder Chiou #ifndef __RT5514_H__
134a6180eaSOder Chiou #define __RT5514_H__
144a6180eaSOder Chiou 
154a6180eaSOder Chiou #define RT5514_DEVICE_ID			0x10ec5514
164a6180eaSOder Chiou 
174a6180eaSOder Chiou #define RT5514_RESET				0x2000
184a6180eaSOder Chiou #define RT5514_PWR_ANA1				0x2004
194a6180eaSOder Chiou #define RT5514_PWR_ANA2				0x2008
204a6180eaSOder Chiou #define RT5514_I2S_CTRL1			0x2010
214a6180eaSOder Chiou #define RT5514_I2S_CTRL2			0x2014
224a6180eaSOder Chiou #define RT5514_VAD_CTRL6			0x2030
234a6180eaSOder Chiou #define RT5514_EXT_VAD_CTRL			0x206c
244a6180eaSOder Chiou #define RT5514_DIG_IO_CTRL			0x2070
254a6180eaSOder Chiou #define RT5514_PAD_CTRL1			0x2080
264a6180eaSOder Chiou #define RT5514_DMIC_DATA_CTRL			0x20a0
274a6180eaSOder Chiou #define RT5514_DIG_SOURCE_CTRL			0x20a4
284a6180eaSOder Chiou #define RT5514_SRC_CTRL				0x20ac
294a6180eaSOder Chiou #define RT5514_DOWNFILTER2_CTRL1		0x20d0
304a6180eaSOder Chiou #define RT5514_PLL_SOURCE_CTRL			0x2100
314a6180eaSOder Chiou #define RT5514_CLK_CTRL1			0x2104
324a6180eaSOder Chiou #define RT5514_CLK_CTRL2			0x2108
334a6180eaSOder Chiou #define RT5514_PLL3_CALIB_CTRL1			0x2110
344a6180eaSOder Chiou #define RT5514_PLL3_CALIB_CTRL5			0x2124
354a6180eaSOder Chiou #define RT5514_DELAY_BUF_CTRL1			0x2140
364a6180eaSOder Chiou #define RT5514_DELAY_BUF_CTRL3			0x2148
374a6180eaSOder Chiou #define RT5514_DOWNFILTER0_CTRL1		0x2190
384a6180eaSOder Chiou #define RT5514_DOWNFILTER0_CTRL2		0x2194
394a6180eaSOder Chiou #define RT5514_DOWNFILTER0_CTRL3		0x2198
404a6180eaSOder Chiou #define RT5514_DOWNFILTER1_CTRL1		0x21a0
414a6180eaSOder Chiou #define RT5514_DOWNFILTER1_CTRL2		0x21a4
424a6180eaSOder Chiou #define RT5514_DOWNFILTER1_CTRL3		0x21a8
434a6180eaSOder Chiou #define RT5514_ANA_CTRL_LDO10			0x2200
444a6180eaSOder Chiou #define RT5514_ANA_CTRL_LDO18_16		0x2204
454a6180eaSOder Chiou #define RT5514_ANA_CTRL_ADC12			0x2210
464a6180eaSOder Chiou #define RT5514_ANA_CTRL_ADC21			0x2214
474a6180eaSOder Chiou #define RT5514_ANA_CTRL_ADC22			0x2218
484a6180eaSOder Chiou #define RT5514_ANA_CTRL_ADC23			0x221c
494a6180eaSOder Chiou #define RT5514_ANA_CTRL_MICBST			0x2220
504a6180eaSOder Chiou #define RT5514_ANA_CTRL_ADCFED			0x2224
514a6180eaSOder Chiou #define RT5514_ANA_CTRL_INBUF			0x2228
524a6180eaSOder Chiou #define RT5514_ANA_CTRL_VREF			0x222c
534a6180eaSOder Chiou #define RT5514_ANA_CTRL_PLL3			0x2240
544a6180eaSOder Chiou #define RT5514_ANA_CTRL_PLL1_1			0x2260
554a6180eaSOder Chiou #define RT5514_ANA_CTRL_PLL1_2			0x2264
564a6180eaSOder Chiou #define RT5514_DMIC_LP_CTRL			0x2e00
574a6180eaSOder Chiou #define RT5514_MISC_CTRL_DSP			0x2e04
584a6180eaSOder Chiou #define RT5514_DSP_CTRL1			0x2f00
594a6180eaSOder Chiou #define RT5514_DSP_CTRL3			0x2f08
604a6180eaSOder Chiou #define RT5514_DSP_CTRL4			0x2f10
614a6180eaSOder Chiou #define RT5514_VENDOR_ID1			0x2ff0
624a6180eaSOder Chiou #define RT5514_VENDOR_ID2			0x2ff4
634a6180eaSOder Chiou 
644a6180eaSOder Chiou #define RT5514_DSP_MAPPING			0x18000000
654a6180eaSOder Chiou 
664a6180eaSOder Chiou /* RT5514_PWR_ANA1 (0x2004) */
674a6180eaSOder Chiou #define RT5514_POW_LDO18_IN			(0x1 << 5)
684a6180eaSOder Chiou #define RT5514_POW_LDO18_IN_BIT			5
694a6180eaSOder Chiou #define RT5514_POW_LDO18_ADC			(0x1 << 4)
704a6180eaSOder Chiou #define RT5514_POW_LDO18_ADC_BIT		4
714a6180eaSOder Chiou #define RT5514_POW_LDO21			(0x1 << 3)
724a6180eaSOder Chiou #define RT5514_POW_LDO21_BIT			3
734a6180eaSOder Chiou #define RT5514_POW_BG_LDO18_IN			(0x1 << 2)
744a6180eaSOder Chiou #define RT5514_POW_BG_LDO18_IN_BIT		2
754a6180eaSOder Chiou #define RT5514_POW_BG_LDO21			(0x1 << 1)
764a6180eaSOder Chiou #define RT5514_POW_BG_LDO21_BIT			1
774a6180eaSOder Chiou 
784a6180eaSOder Chiou /* RT5514_PWR_ANA2 (0x2008) */
794a6180eaSOder Chiou #define RT5514_POW_PLL1				(0x1 << 18)
804a6180eaSOder Chiou #define RT5514_POW_PLL1_BIT			18
814a6180eaSOder Chiou #define RT5514_POW_PLL1_LDO			(0x1 << 16)
824a6180eaSOder Chiou #define RT5514_POW_PLL1_LDO_BIT			16
834a6180eaSOder Chiou #define RT5514_POW_BG_MBIAS			(0x1 << 15)
844a6180eaSOder Chiou #define RT5514_POW_BG_MBIAS_BIT			15
854a6180eaSOder Chiou #define RT5514_POW_MBIAS			(0x1 << 14)
864a6180eaSOder Chiou #define RT5514_POW_MBIAS_BIT			14
874a6180eaSOder Chiou #define RT5514_POW_VREF2			(0x1 << 13)
884a6180eaSOder Chiou #define RT5514_POW_VREF2_BIT			13
894a6180eaSOder Chiou #define RT5514_POW_VREF1			(0x1 << 12)
904a6180eaSOder Chiou #define RT5514_POW_VREF1_BIT			12
914a6180eaSOder Chiou #define RT5514_POWR_LDO16			(0x1 << 11)
924a6180eaSOder Chiou #define RT5514_POWR_LDO16_BIT			11
934a6180eaSOder Chiou #define RT5514_POWL_LDO16			(0x1 << 10)
944a6180eaSOder Chiou #define RT5514_POWL_LDO16_BIT			10
954a6180eaSOder Chiou #define RT5514_POW_ADC2				(0x1 << 9)
964a6180eaSOder Chiou #define RT5514_POW_ADC2_BIT			9
974a6180eaSOder Chiou #define RT5514_POW_INPUT_BUF			(0x1 << 8)
984a6180eaSOder Chiou #define RT5514_POW_INPUT_BUF_BIT		8
994a6180eaSOder Chiou #define RT5514_POW_ADC1_R			(0x1 << 7)
1004a6180eaSOder Chiou #define RT5514_POW_ADC1_R_BIT			7
1014a6180eaSOder Chiou #define RT5514_POW_ADC1_L			(0x1 << 6)
1024a6180eaSOder Chiou #define RT5514_POW_ADC1_L_BIT			6
1034a6180eaSOder Chiou #define RT5514_POW2_BSTR			(0x1 << 5)
1044a6180eaSOder Chiou #define RT5514_POW2_BSTR_BIT			5
1054a6180eaSOder Chiou #define RT5514_POW2_BSTL			(0x1 << 4)
1064a6180eaSOder Chiou #define RT5514_POW2_BSTL_BIT			4
1074a6180eaSOder Chiou #define RT5514_POW_BSTR				(0x1 << 3)
1084a6180eaSOder Chiou #define RT5514_POW_BSTR_BIT			3
1094a6180eaSOder Chiou #define RT5514_POW_BSTL				(0x1 << 2)
1104a6180eaSOder Chiou #define RT5514_POW_BSTL_BIT			2
1114a6180eaSOder Chiou #define RT5514_POW_ADCFEDR			(0x1 << 1)
1124a6180eaSOder Chiou #define RT5514_POW_ADCFEDR_BIT			1
1134a6180eaSOder Chiou #define RT5514_POW_ADCFEDL			(0x1 << 0)
1144a6180eaSOder Chiou #define RT5514_POW_ADCFEDL_BIT			0
1154a6180eaSOder Chiou 
1164a6180eaSOder Chiou /* RT5514_I2S_CTRL1 (0x2010) */
1174a6180eaSOder Chiou #define RT5514_TDM_MODE				(0x1 << 28)
1184a6180eaSOder Chiou #define RT5514_TDM_MODE_SFT			28
1194a6180eaSOder Chiou #define RT5514_I2S_LR_MASK			(0x1 << 26)
1204a6180eaSOder Chiou #define RT5514_I2S_LR_SFT			26
1214a6180eaSOder Chiou #define RT5514_I2S_LR_NOR			(0x0 << 26)
1224a6180eaSOder Chiou #define RT5514_I2S_LR_INV			(0x1 << 26)
1234a6180eaSOder Chiou #define RT5514_I2S_BP_MASK			(0x1 << 25)
1244a6180eaSOder Chiou #define RT5514_I2S_BP_SFT			25
1254a6180eaSOder Chiou #define RT5514_I2S_BP_NOR			(0x0 << 25)
1264a6180eaSOder Chiou #define RT5514_I2S_BP_INV			(0x1 << 25)
1274a6180eaSOder Chiou #define RT5514_I2S_DF_MASK			(0x7 << 16)
1284a6180eaSOder Chiou #define RT5514_I2S_DF_SFT			16
1294a6180eaSOder Chiou #define RT5514_I2S_DF_I2S			(0x0 << 16)
1304a6180eaSOder Chiou #define RT5514_I2S_DF_LEFT			(0x1 << 16)
1314a6180eaSOder Chiou #define RT5514_I2S_DF_PCM_A			(0x2 << 16)
1324a6180eaSOder Chiou #define RT5514_I2S_DF_PCM_B			(0x3 << 16)
1334a6180eaSOder Chiou #define RT5514_TDMSLOT_SEL_RX_MASK		(0x3 << 10)
1344a6180eaSOder Chiou #define RT5514_TDMSLOT_SEL_RX_SFT		10
1354a6180eaSOder Chiou #define RT5514_TDMSLOT_SEL_RX_4CH		(0x1 << 10)
1364a6180eaSOder Chiou #define RT5514_CH_LEN_RX_MASK			(0x3 << 8)
1374a6180eaSOder Chiou #define RT5514_CH_LEN_RX_SFT			8
1384a6180eaSOder Chiou #define RT5514_CH_LEN_RX_16			(0x0 << 8)
1394a6180eaSOder Chiou #define RT5514_CH_LEN_RX_20			(0x1 << 8)
1404a6180eaSOder Chiou #define RT5514_CH_LEN_RX_24			(0x2 << 8)
1414a6180eaSOder Chiou #define RT5514_CH_LEN_RX_32			(0x3 << 8)
1424a6180eaSOder Chiou #define RT5514_TDMSLOT_SEL_TX_MASK		(0x3 << 6)
1434a6180eaSOder Chiou #define RT5514_TDMSLOT_SEL_TX_SFT		6
1444a6180eaSOder Chiou #define RT5514_TDMSLOT_SEL_TX_4CH		(0x1 << 6)
1454a6180eaSOder Chiou #define RT5514_CH_LEN_TX_MASK			(0x3 << 4)
1464a6180eaSOder Chiou #define RT5514_CH_LEN_TX_SFT			4
1474a6180eaSOder Chiou #define RT5514_CH_LEN_TX_16			(0x0 << 4)
1484a6180eaSOder Chiou #define RT5514_CH_LEN_TX_20			(0x1 << 4)
1494a6180eaSOder Chiou #define RT5514_CH_LEN_TX_24			(0x2 << 4)
1504a6180eaSOder Chiou #define RT5514_CH_LEN_TX_32			(0x3 << 4)
1514a6180eaSOder Chiou #define RT5514_I2S_DL_MASK			(0x3 << 0)
1524a6180eaSOder Chiou #define RT5514_I2S_DL_SFT			0
1534a6180eaSOder Chiou #define RT5514_I2S_DL_16			(0x0 << 0)
1544a6180eaSOder Chiou #define RT5514_I2S_DL_20			(0x1 << 0)
1554a6180eaSOder Chiou #define RT5514_I2S_DL_24			(0x2 << 0)
1564a6180eaSOder Chiou #define RT5514_I2S_DL_8				(0x3 << 0)
1574a6180eaSOder Chiou 
1584a6180eaSOder Chiou /* RT5514_DIG_SOURCE_CTRL (0x20a4) */
1594a6180eaSOder Chiou #define RT5514_AD1_DMIC_INPUT_SEL		(0x1 << 1)
1604a6180eaSOder Chiou #define RT5514_AD1_DMIC_INPUT_SEL_SFT		1
1614a6180eaSOder Chiou #define RT5514_AD0_DMIC_INPUT_SEL		(0x1 << 0)
1624a6180eaSOder Chiou #define RT5514_AD0_DMIC_INPUT_SEL_SFT		0
1634a6180eaSOder Chiou 
1644a6180eaSOder Chiou /* RT5514_PLL_SOURCE_CTRL (0x2100) */
1654a6180eaSOder Chiou #define RT5514_PLL_1_SEL_MASK			(0x7 << 12)
1664a6180eaSOder Chiou #define RT5514_PLL_1_SEL_SFT			12
1674a6180eaSOder Chiou #define RT5514_PLL_1_SEL_SCLK			(0x3 << 12)
1684a6180eaSOder Chiou #define RT5514_PLL_1_SEL_MCLK			(0x4 << 12)
1694a6180eaSOder Chiou 
1704a6180eaSOder Chiou /* RT5514_CLK_CTRL1 (0x2104) */
1714a6180eaSOder Chiou #define RT5514_CLK_AD_ANA1_EN			(0x1 << 31)
1724a6180eaSOder Chiou #define RT5514_CLK_AD_ANA1_EN_BIT		31
1734a6180eaSOder Chiou #define RT5514_CLK_AD1_EN			(0x1 << 24)
1744a6180eaSOder Chiou #define RT5514_CLK_AD1_EN_BIT			24
1754a6180eaSOder Chiou #define RT5514_CLK_AD0_EN			(0x1 << 23)
1764a6180eaSOder Chiou #define RT5514_CLK_AD0_EN_BIT			23
1774a6180eaSOder Chiou #define RT5514_CLK_DMIC_OUT_SEL_MASK		(0x7 << 8)
1784a6180eaSOder Chiou #define RT5514_CLK_DMIC_OUT_SEL_SFT		8
1794a6180eaSOder Chiou 
1804a6180eaSOder Chiou /* RT5514_CLK_CTRL2 (0x2108) */
1814a6180eaSOder Chiou #define RT5514_CLK_SYS_DIV_OUT_MASK		(0x7 << 8)
1824a6180eaSOder Chiou #define RT5514_CLK_SYS_DIV_OUT_SFT		8
1834a6180eaSOder Chiou #define RT5514_SEL_ADC_OSR_MASK			(0x7 << 4)
1844a6180eaSOder Chiou #define RT5514_SEL_ADC_OSR_SFT			4
1854a6180eaSOder Chiou #define RT5514_CLK_SYS_PRE_SEL_MASK		(0x3 << 0)
1864a6180eaSOder Chiou #define RT5514_CLK_SYS_PRE_SEL_SFT		0
1874a6180eaSOder Chiou #define RT5514_CLK_SYS_PRE_SEL_MCLK		(0x2 << 0)
1884a6180eaSOder Chiou #define RT5514_CLK_SYS_PRE_SEL_PLL		(0x3 << 0)
1894a6180eaSOder Chiou 
1904a6180eaSOder Chiou /*  RT5514_DOWNFILTER_CTRL (0x2190 0x2194 0x21a0 0x21a4) */
1914a6180eaSOder Chiou #define RT5514_AD_DMIC_MIX			(0x1 << 11)
1924a6180eaSOder Chiou #define RT5514_AD_DMIC_MIX_BIT			11
1934a6180eaSOder Chiou #define RT5514_AD_AD_MIX			(0x1 << 10)
1944a6180eaSOder Chiou #define RT5514_AD_AD_MIX_BIT			10
1954a6180eaSOder Chiou #define RT5514_AD_AD_MUTE			(0x1 << 7)
1964a6180eaSOder Chiou #define RT5514_AD_AD_MUTE_BIT			7
1974a6180eaSOder Chiou #define RT5514_AD_GAIN_MASK			(0x7f << 0)
1984a6180eaSOder Chiou #define RT5514_AD_GAIN_SFT			0
1994a6180eaSOder Chiou 
2004a6180eaSOder Chiou /*  RT5514_ANA_CTRL_MICBST (0x2220) */
2014a6180eaSOder Chiou #define RT5514_SEL_BSTL_MASK			(0xf << 4)
2024a6180eaSOder Chiou #define RT5514_SEL_BSTL_SFT			4
2034a6180eaSOder Chiou #define RT5514_SEL_BSTR_MASK			(0xf << 0)
2044a6180eaSOder Chiou #define RT5514_SEL_BSTR_SFT			0
2054a6180eaSOder Chiou 
2064a6180eaSOder Chiou /*  RT5514_ANA_CTRL_PLL1_1 (0x2260) */
2074a6180eaSOder Chiou #define RT5514_PLL_K_MAX			0x1f
2084a6180eaSOder Chiou #define RT5514_PLL_K_MASK			(RT5514_PLL_K_MAX << 16)
2094a6180eaSOder Chiou #define RT5514_PLL_K_SFT			16
2104a6180eaSOder Chiou #define RT5514_PLL_N_MAX			0x1ff
2114a6180eaSOder Chiou #define RT5514_PLL_N_MASK			(RT5514_PLL_N_MAX << 7)
2124a6180eaSOder Chiou #define RT5514_PLL_N_SFT			4
2134a6180eaSOder Chiou #define RT5514_PLL_M_MAX			0xf
2144a6180eaSOder Chiou #define RT5514_PLL_M_MASK			(RT5514_PLL_M_MAX << 0)
2154a6180eaSOder Chiou #define RT5514_PLL_M_SFT			0
2164a6180eaSOder Chiou 
2174a6180eaSOder Chiou /*  RT5514_ANA_CTRL_PLL1_2 (0x2264) */
2184a6180eaSOder Chiou #define RT5514_PLL_M_BP				(0x1 << 2)
2194a6180eaSOder Chiou #define RT5514_PLL_M_BP_SFT			2
2204a6180eaSOder Chiou #define RT5514_PLL_K_BP				(0x1 << 1)
2214a6180eaSOder Chiou #define RT5514_PLL_K_BP_SFT			1
2224a6180eaSOder Chiou #define RT5514_EN_LDO_PLL1			(0x1 << 0)
2234a6180eaSOder Chiou #define RT5514_EN_LDO_PLL1_BIT			0
2244a6180eaSOder Chiou 
2254a6180eaSOder Chiou #define RT5514_PLL_INP_MAX			40000000
2264a6180eaSOder Chiou #define RT5514_PLL_INP_MIN			256000
2274a6180eaSOder Chiou 
2284a6180eaSOder Chiou /* System Clock Source */
2294a6180eaSOder Chiou enum {
2304a6180eaSOder Chiou 	RT5514_SCLK_S_MCLK,
2314a6180eaSOder Chiou 	RT5514_SCLK_S_PLL1,
2324a6180eaSOder Chiou };
2334a6180eaSOder Chiou 
2344a6180eaSOder Chiou /* PLL1 Source */
2354a6180eaSOder Chiou enum {
2364a6180eaSOder Chiou 	RT5514_PLL1_S_MCLK,
2374a6180eaSOder Chiou 	RT5514_PLL1_S_BCLK,
2384a6180eaSOder Chiou };
2394a6180eaSOder Chiou 
2404a6180eaSOder Chiou struct rt5514_priv {
2414a6180eaSOder Chiou 	struct snd_soc_codec *codec;
2424a6180eaSOder Chiou 	struct regmap *i2c_regmap, *regmap;
2434a6180eaSOder Chiou 	int sysclk;
2444a6180eaSOder Chiou 	int sysclk_src;
2454a6180eaSOder Chiou 	int lrck;
2464a6180eaSOder Chiou 	int bclk;
2474a6180eaSOder Chiou 	int pll_src;
2484a6180eaSOder Chiou 	int pll_in;
2494a6180eaSOder Chiou 	int pll_out;
2504a6180eaSOder Chiou };
2514a6180eaSOder Chiou 
2524a6180eaSOder Chiou #endif /* __RT5514_H__ */
253